rx_mpdu_details.h 14 KB

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  1. /*
  2. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _RX_MPDU_DETAILS_H_
  17. #define _RX_MPDU_DETAILS_H_
  18. #if !defined(__ASSEMBLER__)
  19. #endif
  20. #include "buffer_addr_info.h"
  21. #include "rx_mpdu_desc_info.h"
  22. // ################ START SUMMARY #################
  23. //
  24. // Dword Fields
  25. // 0-1 struct buffer_addr_info msdu_link_desc_addr_info;
  26. // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
  27. //
  28. // ################ END SUMMARY #################
  29. #define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
  30. struct rx_mpdu_details {
  31. struct buffer_addr_info msdu_link_desc_addr_info;
  32. struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
  33. };
  34. /*
  35. struct buffer_addr_info msdu_link_desc_addr_info
  36. Consumer: REO/SW/FW
  37. Producer: RXDMA
  38. Details of the physical address of the MSDU link
  39. descriptor that contains pointers to MSDUs related to this
  40. MPDU
  41. struct rx_mpdu_desc_info rx_mpdu_desc_info_details
  42. Consumer: REO/SW/FW
  43. Producer: RXDMA
  44. General information related to the MPDU that should be
  45. */
  46. /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
  47. /* Description RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
  48. Address (lower 32 bits) of the MSDU buffer OR
  49. MSDU_EXTENSION descriptor OR Link Descriptor
  50. In case of 'NULL' pointer, this field is set to 0
  51. <legal all>
  52. */
  53. #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
  54. #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  55. #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  56. /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
  57. Address (upper 8 bits) of the MSDU buffer OR
  58. MSDU_EXTENSION descriptor OR Link Descriptor
  59. In case of 'NULL' pointer, this field is set to 0
  60. <legal all>
  61. */
  62. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
  63. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  64. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  65. /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
  66. Consumer: WBM
  67. Producer: SW/FW
  68. In case of 'NULL' pointer, this field is set to 0
  69. Indicates to which buffer manager the buffer OR
  70. MSDU_EXTENSION descriptor OR link descriptor that is being
  71. pointed to shall be returned after the frame has been
  72. processed. It is used by WBM for routing purposes.
  73. <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
  74. to the WMB buffer idle list
  75. <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
  76. returned to the WMB idle link descriptor idle list
  77. <enum 2 FW_BM> This buffer shall be returned to the FW
  78. <enum 3 SW0_BM> This buffer shall be returned to the SW,
  79. ring 0
  80. <enum 4 SW1_BM> This buffer shall be returned to the SW,
  81. ring 1
  82. <enum 5 SW2_BM> This buffer shall be returned to the SW,
  83. ring 2
  84. <enum 6 SW3_BM> This buffer shall be returned to the SW,
  85. ring 3
  86. <enum 7 SW4_BM> This buffer shall be returned to the SW,
  87. ring 4
  88. <legal all>
  89. */
  90. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
  91. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
  92. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
  93. /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
  94. Cookie field exclusively used by SW.
  95. In case of 'NULL' pointer, this field is set to 0
  96. HW ignores the contents, accept that it passes the
  97. programmed value on to other descriptors together with the
  98. physical address
  99. Field can be used by SW to for example associate the
  100. buffers physical address with the virtual address
  101. The bit definitions as used by SW are within SW HLD
  102. specification
  103. NOTE1:
  104. The three most significant bits can have a special
  105. meaning in case this struct is embedded in a TX_MPDU_DETAILS
  106. STRUCT, and field transmit_bw_restriction is set
  107. In case of NON punctured transmission:
  108. Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
  109. Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
  110. Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
  111. Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
  112. In case of punctured transmission:
  113. Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
  114. Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
  115. Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
  116. Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
  117. Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
  118. Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
  119. Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
  120. Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
  121. Note: a punctured transmission is indicated by the
  122. presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
  123. TLV
  124. NOTE 2:The five most significant bits can have a special
  125. meaning in case this struct is embedded in an
  126. RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
  127. configured for passing on the additional info
  128. from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
  129. (FR56821). This is not supported in HastingsPrime, Pine or
  130. Moselle.
  131. Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
  132. control field
  133. Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
  134. indicates MPDUs with a QoS control field.
  135. <legal all>
  136. */
  137. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
  138. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
  139. #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
  140. /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
  141. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
  142. Consumer: REO/SW/FW
  143. Producer: RXDMA
  144. The number of MSDUs within the MPDU
  145. <legal all>
  146. */
  147. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
  148. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
  149. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
  150. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
  151. Consumer: REO/SW/FW
  152. Producer: RXDMA
  153. The field can have two different meanings based on the
  154. setting of field 'BAR_frame':
  155. 'BAR_frame' is NOT set:
  156. The MPDU sequence number of the received frame.
  157. 'BAR_frame' is set.
  158. The MPDU Start sequence number from the BAR frame
  159. <legal all>
  160. */
  161. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
  162. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
  163. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
  164. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
  165. Consumer: REO/SW/FW
  166. Producer: RXDMA
  167. When set, this MPDU is a fragment and REO should forward
  168. this fragment MPDU to the REO destination ring without any
  169. reorder checks, pn checks or bitmap update. This implies
  170. that REO is forwarding the pointer to the MSDU link
  171. descriptor. The destination ring is coming from a
  172. programmable register setting in REO
  173. <legal all>
  174. */
  175. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
  176. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
  177. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
  178. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
  179. Consumer: REO/SW/FW
  180. Producer: RXDMA
  181. The retry bit setting from the MPDU header of the
  182. received frame
  183. <legal all>
  184. */
  185. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
  186. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
  187. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
  188. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
  189. Consumer: REO/SW/FW
  190. Producer: RXDMA
  191. When set, the MPDU was received as part of an A-MPDU.
  192. <legal all>
  193. */
  194. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
  195. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
  196. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
  197. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
  198. Consumer: REO/SW/FW
  199. Producer: RXDMA
  200. When set, the received frame is a BAR frame. After
  201. processing, this frame shall be pushed to SW or deleted.
  202. <legal all>
  203. */
  204. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
  205. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
  206. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
  207. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
  208. Consumer: REO/SW/FW
  209. Producer: RXDMA
  210. Copied here by RXDMA from RX_MPDU_END
  211. When not set, REO will Not perform a PN sequence number
  212. check
  213. */
  214. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
  215. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
  216. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
  217. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
  218. When set, OLE found a valid SA entry for all MSDUs in
  219. this MPDU
  220. <legal all>
  221. */
  222. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
  223. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
  224. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
  225. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
  226. When set, at least 1 MSDU within the MPDU has an
  227. unsuccessful MAC source address search due to the expiration
  228. of the search timer.
  229. <legal all>
  230. */
  231. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
  232. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
  233. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
  234. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
  235. When set, OLE found a valid DA entry for all MSDUs in
  236. this MPDU
  237. <legal all>
  238. */
  239. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
  240. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
  241. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
  242. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
  243. Field Only valid if da_is_valid is set
  244. When set, at least one of the DA addresses is a
  245. Multicast or Broadcast address.
  246. <legal all>
  247. */
  248. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
  249. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
  250. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
  251. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
  252. When set, at least 1 MSDU within the MPDU has an
  253. unsuccessful MAC destination address search due to the
  254. expiration of the search timer.
  255. <legal all>
  256. */
  257. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
  258. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
  259. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
  260. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
  261. Field only valid when first_msdu_in_mpdu_flag is set.
  262. When set, the contents in the MSDU buffer contains a
  263. 'RAW' MPDU. This 'RAW' MPDU might be spread out over
  264. multiple MSDU buffers.
  265. <legal all>
  266. */
  267. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
  268. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
  269. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
  270. /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
  271. The More Fragment bit setting from the MPDU header of
  272. the received frame
  273. <legal all>
  274. */
  275. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
  276. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
  277. #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
  278. /* Description RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
  279. Meta data that SW has programmed in the Peer table entry
  280. of the transmitting STA.
  281. <legal all>
  282. */
  283. #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
  284. #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
  285. #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
  286. #endif // _RX_MPDU_DETAILS_H_