dp_tx.c 144 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. /* Flag to skip CCE classify when mesh or tid override enabled */
  52. #define DP_TX_SKIP_CCE_CLASSIFY \
  53. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  54. /* TODO Add support in TSO */
  55. #define DP_DESC_NUM_FRAG(x) 0
  56. /* disable TQM_BYPASS */
  57. #define TQM_BYPASS_WAR 0
  58. /* invalid peer id for reinject*/
  59. #define DP_INVALID_PEER 0XFFFE
  60. #define DP_RETRY_COUNT 7
  61. /*mapping between hal encrypt type and cdp_sec_type*/
  62. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  63. HAL_TX_ENCRYPT_TYPE_WEP_128,
  64. HAL_TX_ENCRYPT_TYPE_WEP_104,
  65. HAL_TX_ENCRYPT_TYPE_WEP_40,
  66. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  67. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  68. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  69. HAL_TX_ENCRYPT_TYPE_WAPI,
  70. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  71. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  72. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  73. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  74. qdf_export_symbol(sec_type_map);
  75. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  76. /**
  77. * dp_update_tx_desc_stats - Update the increase or decrease in
  78. * outstanding tx desc count
  79. * values on pdev and soc
  80. * @vdev: DP pdev handle
  81. *
  82. * Return: void
  83. */
  84. static inline void
  85. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  86. {
  87. int32_t tx_descs_cnt =
  88. qdf_atomic_read(&pdev->num_tx_outstanding);
  89. if (pdev->tx_descs_max < tx_descs_cnt)
  90. pdev->tx_descs_max = tx_descs_cnt;
  91. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  92. pdev->tx_descs_max);
  93. }
  94. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  95. static inline void
  96. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  97. {
  98. }
  99. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  100. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  101. static inline
  102. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  103. {
  104. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  105. QDF_DMA_TO_DEVICE,
  106. desc->nbuf->len);
  107. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  108. }
  109. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  110. {
  111. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  112. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  113. QDF_DMA_TO_DEVICE,
  114. desc->nbuf->len);
  115. }
  116. #else
  117. static inline
  118. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  119. {
  120. }
  121. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  122. {
  123. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  124. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  125. }
  126. #endif
  127. #ifdef QCA_TX_LIMIT_CHECK
  128. /**
  129. * dp_tx_limit_check - Check if allocated tx descriptors reached
  130. * soc max limit and pdev max limit
  131. * @vdev: DP vdev handle
  132. *
  133. * Return: true if allocated tx descriptors reached max configured value, else
  134. * false
  135. */
  136. static inline bool
  137. dp_tx_limit_check(struct dp_vdev *vdev)
  138. {
  139. struct dp_pdev *pdev = vdev->pdev;
  140. struct dp_soc *soc = pdev->soc;
  141. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  142. soc->num_tx_allowed) {
  143. dp_tx_info("queued packets are more than max tx, drop the frame");
  144. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  145. return true;
  146. }
  147. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  148. pdev->num_tx_allowed) {
  149. dp_tx_info("queued packets are more than max tx, drop the frame");
  150. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  151. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  152. return true;
  153. }
  154. return false;
  155. }
  156. /**
  157. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  158. * reached soc max limit
  159. * @vdev: DP vdev handle
  160. *
  161. * Return: true if allocated tx descriptors reached max configured value, else
  162. * false
  163. */
  164. static inline bool
  165. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  166. {
  167. struct dp_pdev *pdev = vdev->pdev;
  168. struct dp_soc *soc = pdev->soc;
  169. if (qdf_atomic_read(&soc->num_tx_exception) >=
  170. soc->num_msdu_exception_desc) {
  171. dp_info("exc packets are more than max drop the exc pkt");
  172. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  173. return true;
  174. }
  175. return false;
  176. }
  177. /**
  178. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  179. * @vdev: DP pdev handle
  180. *
  181. * Return: void
  182. */
  183. static inline void
  184. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  185. {
  186. struct dp_soc *soc = pdev->soc;
  187. qdf_atomic_inc(&pdev->num_tx_outstanding);
  188. qdf_atomic_inc(&soc->num_tx_outstanding);
  189. dp_update_tx_desc_stats(pdev);
  190. }
  191. /**
  192. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  193. * @vdev: DP pdev handle
  194. *
  195. * Return: void
  196. */
  197. static inline void
  198. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  199. {
  200. struct dp_soc *soc = pdev->soc;
  201. qdf_atomic_dec(&pdev->num_tx_outstanding);
  202. qdf_atomic_dec(&soc->num_tx_outstanding);
  203. dp_update_tx_desc_stats(pdev);
  204. }
  205. #else //QCA_TX_LIMIT_CHECK
  206. static inline bool
  207. dp_tx_limit_check(struct dp_vdev *vdev)
  208. {
  209. return false;
  210. }
  211. static inline bool
  212. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  213. {
  214. return false;
  215. }
  216. static inline void
  217. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  218. {
  219. qdf_atomic_inc(&pdev->num_tx_outstanding);
  220. dp_update_tx_desc_stats(pdev);
  221. }
  222. static inline void
  223. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  224. {
  225. qdf_atomic_dec(&pdev->num_tx_outstanding);
  226. dp_update_tx_desc_stats(pdev);
  227. }
  228. #endif //QCA_TX_LIMIT_CHECK
  229. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  230. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  231. {
  232. enum dp_tx_event_type type;
  233. if (flags & DP_TX_DESC_FLAG_FLUSH)
  234. type = DP_TX_DESC_FLUSH;
  235. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  236. type = DP_TX_COMP_UNMAP_ERR;
  237. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  238. type = DP_TX_COMP_UNMAP;
  239. else
  240. type = DP_TX_DESC_UNMAP;
  241. return type;
  242. }
  243. static inline void
  244. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  245. qdf_nbuf_t skb, uint32_t sw_cookie,
  246. enum dp_tx_event_type type)
  247. {
  248. struct dp_tx_desc_event *entry;
  249. uint32_t idx;
  250. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  251. return;
  252. switch (type) {
  253. case DP_TX_COMP_UNMAP:
  254. case DP_TX_COMP_UNMAP_ERR:
  255. case DP_TX_COMP_MSDU_EXT:
  256. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  257. DP_TX_COMP_HISTORY_SIZE);
  258. entry = &soc->tx_comp_history->entry[idx];
  259. break;
  260. case DP_TX_DESC_MAP:
  261. case DP_TX_DESC_UNMAP:
  262. case DP_TX_DESC_COOKIE:
  263. case DP_TX_DESC_FLUSH:
  264. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  265. DP_TX_TCL_HISTORY_SIZE);
  266. entry = &soc->tx_tcl_history->entry[idx];
  267. break;
  268. default:
  269. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  270. return;
  271. }
  272. entry->skb = skb;
  273. entry->paddr = paddr;
  274. entry->sw_cookie = sw_cookie;
  275. entry->type = type;
  276. entry->ts = qdf_get_log_timestamp();
  277. }
  278. static inline void
  279. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  280. struct qdf_tso_seg_elem_t *tso_seg,
  281. qdf_nbuf_t skb, uint32_t sw_cookie,
  282. enum dp_tx_event_type type)
  283. {
  284. int i;
  285. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  286. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  287. skb, sw_cookie, type);
  288. }
  289. if (!tso_seg->next)
  290. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  291. skb, 0xFFFFFFFF, type);
  292. }
  293. static inline void
  294. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  295. qdf_nbuf_t skb, uint32_t sw_cookie,
  296. enum dp_tx_event_type type)
  297. {
  298. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  299. uint32_t num_segs = tso_info.num_segs;
  300. while (num_segs) {
  301. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  302. curr_seg = curr_seg->next;
  303. num_segs--;
  304. }
  305. }
  306. #else
  307. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  308. {
  309. return DP_TX_DESC_INVAL_EVT;
  310. }
  311. static inline void
  312. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  313. qdf_nbuf_t skb, uint32_t sw_cookie,
  314. enum dp_tx_event_type type)
  315. {
  316. }
  317. static inline void
  318. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  319. struct qdf_tso_seg_elem_t *tso_seg,
  320. qdf_nbuf_t skb, uint32_t sw_cookie,
  321. enum dp_tx_event_type type)
  322. {
  323. }
  324. static inline void
  325. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  326. qdf_nbuf_t skb, uint32_t sw_cookie,
  327. enum dp_tx_event_type type)
  328. {
  329. }
  330. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  331. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  332. /**
  333. * dp_is_tput_high() - Check if throughput is high
  334. *
  335. * @soc - core txrx main context
  336. *
  337. * The current function is based of the RTPM tput policy variable where RTPM is
  338. * avoided based on throughput.
  339. */
  340. static inline int dp_is_tput_high(struct dp_soc *soc)
  341. {
  342. return dp_get_rtpm_tput_policy_requirement(soc);
  343. }
  344. #if defined(FEATURE_TSO)
  345. /**
  346. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  347. *
  348. * @soc - core txrx main context
  349. * @seg_desc - tso segment descriptor
  350. * @num_seg_desc - tso number segment descriptor
  351. */
  352. static void dp_tx_tso_unmap_segment(
  353. struct dp_soc *soc,
  354. struct qdf_tso_seg_elem_t *seg_desc,
  355. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  356. {
  357. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  358. if (qdf_unlikely(!seg_desc)) {
  359. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  360. __func__, __LINE__);
  361. qdf_assert(0);
  362. } else if (qdf_unlikely(!num_seg_desc)) {
  363. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  364. __func__, __LINE__);
  365. qdf_assert(0);
  366. } else {
  367. bool is_last_seg;
  368. /* no tso segment left to do dma unmap */
  369. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  370. return;
  371. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  372. true : false;
  373. qdf_nbuf_unmap_tso_segment(soc->osdev,
  374. seg_desc, is_last_seg);
  375. num_seg_desc->num_seg.tso_cmn_num_seg--;
  376. }
  377. }
  378. /**
  379. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  380. * back to the freelist
  381. *
  382. * @soc - soc device handle
  383. * @tx_desc - Tx software descriptor
  384. */
  385. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  386. struct dp_tx_desc_s *tx_desc)
  387. {
  388. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  389. if (qdf_unlikely(!tx_desc->tso_desc)) {
  390. dp_tx_err("SO desc is NULL!");
  391. qdf_assert(0);
  392. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  393. dp_tx_err("TSO num desc is NULL!");
  394. qdf_assert(0);
  395. } else {
  396. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  397. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  398. /* Add the tso num segment into the free list */
  399. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  400. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  401. tx_desc->tso_num_desc);
  402. tx_desc->tso_num_desc = NULL;
  403. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  404. }
  405. /* Add the tso segment into the free list*/
  406. dp_tx_tso_desc_free(soc,
  407. tx_desc->pool_id, tx_desc->tso_desc);
  408. tx_desc->tso_desc = NULL;
  409. }
  410. }
  411. #else
  412. static void dp_tx_tso_unmap_segment(
  413. struct dp_soc *soc,
  414. struct qdf_tso_seg_elem_t *seg_desc,
  415. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  416. {
  417. }
  418. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  419. struct dp_tx_desc_s *tx_desc)
  420. {
  421. }
  422. #endif
  423. /**
  424. * dp_tx_desc_release() - Release Tx Descriptor
  425. * @tx_desc : Tx Descriptor
  426. * @desc_pool_id: Descriptor Pool ID
  427. *
  428. * Deallocate all resources attached to Tx descriptor and free the Tx
  429. * descriptor.
  430. *
  431. * Return:
  432. */
  433. static void
  434. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  435. {
  436. struct dp_pdev *pdev = tx_desc->pdev;
  437. struct dp_soc *soc;
  438. uint8_t comp_status = 0;
  439. qdf_assert(pdev);
  440. soc = pdev->soc;
  441. dp_tx_outstanding_dec(pdev);
  442. if (tx_desc->frm_type == dp_tx_frm_tso)
  443. dp_tx_tso_desc_release(soc, tx_desc);
  444. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  445. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  446. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  447. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  448. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  449. qdf_atomic_dec(&soc->num_tx_exception);
  450. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  451. tx_desc->buffer_src)
  452. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  453. soc->hal_soc);
  454. else
  455. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  456. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  457. tx_desc->id, comp_status,
  458. qdf_atomic_read(&pdev->num_tx_outstanding));
  459. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  460. return;
  461. }
  462. /**
  463. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  464. * @vdev: DP vdev Handle
  465. * @nbuf: skb
  466. * @msdu_info: msdu_info required to create HTT metadata
  467. *
  468. * Prepares and fills HTT metadata in the frame pre-header for special frames
  469. * that should be transmitted using varying transmit parameters.
  470. * There are 2 VDEV modes that currently needs this special metadata -
  471. * 1) Mesh Mode
  472. * 2) DSRC Mode
  473. *
  474. * Return: HTT metadata size
  475. *
  476. */
  477. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  478. struct dp_tx_msdu_info_s *msdu_info)
  479. {
  480. uint32_t *meta_data = msdu_info->meta_data;
  481. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  482. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  483. uint8_t htt_desc_size;
  484. /* Size rounded of multiple of 8 bytes */
  485. uint8_t htt_desc_size_aligned;
  486. uint8_t *hdr = NULL;
  487. /*
  488. * Metadata - HTT MSDU Extension header
  489. */
  490. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  491. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  492. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  493. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  494. meta_data[0])) {
  495. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  496. htt_desc_size_aligned)) {
  497. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  498. htt_desc_size_aligned);
  499. if (!nbuf) {
  500. /*
  501. * qdf_nbuf_realloc_headroom won't do skb_clone
  502. * as skb_realloc_headroom does. so, no free is
  503. * needed here.
  504. */
  505. DP_STATS_INC(vdev,
  506. tx_i.dropped.headroom_insufficient,
  507. 1);
  508. qdf_print(" %s[%d] skb_realloc_headroom failed",
  509. __func__, __LINE__);
  510. return 0;
  511. }
  512. }
  513. /* Fill and add HTT metaheader */
  514. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  515. if (!hdr) {
  516. dp_tx_err("Error in filling HTT metadata");
  517. return 0;
  518. }
  519. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  520. } else if (vdev->opmode == wlan_op_mode_ocb) {
  521. /* Todo - Add support for DSRC */
  522. }
  523. return htt_desc_size_aligned;
  524. }
  525. /**
  526. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  527. * @tso_seg: TSO segment to process
  528. * @ext_desc: Pointer to MSDU extension descriptor
  529. *
  530. * Return: void
  531. */
  532. #if defined(FEATURE_TSO)
  533. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  534. void *ext_desc)
  535. {
  536. uint8_t num_frag;
  537. uint32_t tso_flags;
  538. /*
  539. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  540. * tcp_flag_mask
  541. *
  542. * Checksum enable flags are set in TCL descriptor and not in Extension
  543. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  544. */
  545. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  546. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  547. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  548. tso_seg->tso_flags.ip_len);
  549. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  550. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  551. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  552. uint32_t lo = 0;
  553. uint32_t hi = 0;
  554. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  555. (tso_seg->tso_frags[num_frag].length));
  556. qdf_dmaaddr_to_32s(
  557. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  558. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  559. tso_seg->tso_frags[num_frag].length);
  560. }
  561. return;
  562. }
  563. #else
  564. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  565. void *ext_desc)
  566. {
  567. return;
  568. }
  569. #endif
  570. #if defined(FEATURE_TSO)
  571. /**
  572. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  573. * allocated and free them
  574. *
  575. * @soc: soc handle
  576. * @free_seg: list of tso segments
  577. * @msdu_info: msdu descriptor
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_tso_seg_list(
  582. struct dp_soc *soc,
  583. struct qdf_tso_seg_elem_t *free_seg,
  584. struct dp_tx_msdu_info_s *msdu_info)
  585. {
  586. struct qdf_tso_seg_elem_t *next_seg;
  587. while (free_seg) {
  588. next_seg = free_seg->next;
  589. dp_tx_tso_desc_free(soc,
  590. msdu_info->tx_queue.desc_pool_id,
  591. free_seg);
  592. free_seg = next_seg;
  593. }
  594. }
  595. /**
  596. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  597. * allocated and free them
  598. *
  599. * @soc: soc handle
  600. * @free_num_seg: list of tso number segments
  601. * @msdu_info: msdu descriptor
  602. * Return - void
  603. */
  604. static void dp_tx_free_tso_num_seg_list(
  605. struct dp_soc *soc,
  606. struct qdf_tso_num_seg_elem_t *free_num_seg,
  607. struct dp_tx_msdu_info_s *msdu_info)
  608. {
  609. struct qdf_tso_num_seg_elem_t *next_num_seg;
  610. while (free_num_seg) {
  611. next_num_seg = free_num_seg->next;
  612. dp_tso_num_seg_free(soc,
  613. msdu_info->tx_queue.desc_pool_id,
  614. free_num_seg);
  615. free_num_seg = next_num_seg;
  616. }
  617. }
  618. /**
  619. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  620. * do dma unmap for each segment
  621. *
  622. * @soc: soc handle
  623. * @free_seg: list of tso segments
  624. * @num_seg_desc: tso number segment descriptor
  625. *
  626. * Return - void
  627. */
  628. static void dp_tx_unmap_tso_seg_list(
  629. struct dp_soc *soc,
  630. struct qdf_tso_seg_elem_t *free_seg,
  631. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  632. {
  633. struct qdf_tso_seg_elem_t *next_seg;
  634. if (qdf_unlikely(!num_seg_desc)) {
  635. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  636. return;
  637. }
  638. while (free_seg) {
  639. next_seg = free_seg->next;
  640. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  641. free_seg = next_seg;
  642. }
  643. }
  644. #ifdef FEATURE_TSO_STATS
  645. /**
  646. * dp_tso_get_stats_idx: Retrieve the tso packet id
  647. * @pdev - pdev handle
  648. *
  649. * Return: id
  650. */
  651. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  652. {
  653. uint32_t stats_idx;
  654. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  655. % CDP_MAX_TSO_PACKETS);
  656. return stats_idx;
  657. }
  658. #else
  659. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  660. {
  661. return 0;
  662. }
  663. #endif /* FEATURE_TSO_STATS */
  664. /**
  665. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  666. * free the tso segments descriptor and
  667. * tso num segments descriptor
  668. *
  669. * @soc: soc handle
  670. * @msdu_info: msdu descriptor
  671. * @tso_seg_unmap: flag to show if dma unmap is necessary
  672. *
  673. * Return - void
  674. */
  675. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  676. struct dp_tx_msdu_info_s *msdu_info,
  677. bool tso_seg_unmap)
  678. {
  679. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  680. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  681. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  682. tso_info->tso_num_seg_list;
  683. /* do dma unmap for each segment */
  684. if (tso_seg_unmap)
  685. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  686. /* free all tso number segment descriptor though looks only have 1 */
  687. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  688. /* free all tso segment descriptor */
  689. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  690. }
  691. /**
  692. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  693. * @vdev: virtual device handle
  694. * @msdu: network buffer
  695. * @msdu_info: meta data associated with the msdu
  696. *
  697. * Return: QDF_STATUS_SUCCESS success
  698. */
  699. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  700. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  701. {
  702. struct qdf_tso_seg_elem_t *tso_seg;
  703. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  704. struct dp_soc *soc = vdev->pdev->soc;
  705. struct dp_pdev *pdev = vdev->pdev;
  706. struct qdf_tso_info_t *tso_info;
  707. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  708. tso_info = &msdu_info->u.tso_info;
  709. tso_info->curr_seg = NULL;
  710. tso_info->tso_seg_list = NULL;
  711. tso_info->num_segs = num_seg;
  712. msdu_info->frm_type = dp_tx_frm_tso;
  713. tso_info->tso_num_seg_list = NULL;
  714. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  715. while (num_seg) {
  716. tso_seg = dp_tx_tso_desc_alloc(
  717. soc, msdu_info->tx_queue.desc_pool_id);
  718. if (tso_seg) {
  719. tso_seg->next = tso_info->tso_seg_list;
  720. tso_info->tso_seg_list = tso_seg;
  721. num_seg--;
  722. } else {
  723. dp_err_rl("Failed to alloc tso seg desc");
  724. DP_STATS_INC_PKT(vdev->pdev,
  725. tso_stats.tso_no_mem_dropped, 1,
  726. qdf_nbuf_len(msdu));
  727. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  728. return QDF_STATUS_E_NOMEM;
  729. }
  730. }
  731. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  732. tso_num_seg = dp_tso_num_seg_alloc(soc,
  733. msdu_info->tx_queue.desc_pool_id);
  734. if (tso_num_seg) {
  735. tso_num_seg->next = tso_info->tso_num_seg_list;
  736. tso_info->tso_num_seg_list = tso_num_seg;
  737. } else {
  738. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  739. __func__);
  740. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  741. return QDF_STATUS_E_NOMEM;
  742. }
  743. msdu_info->num_seg =
  744. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  745. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  746. msdu_info->num_seg);
  747. if (!(msdu_info->num_seg)) {
  748. /*
  749. * Free allocated TSO seg desc and number seg desc,
  750. * do unmap for segments if dma map has done.
  751. */
  752. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  753. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  754. return QDF_STATUS_E_INVAL;
  755. }
  756. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  757. msdu, 0, DP_TX_DESC_MAP);
  758. tso_info->curr_seg = tso_info->tso_seg_list;
  759. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  760. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  761. msdu, msdu_info->num_seg);
  762. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  763. tso_info->msdu_stats_idx);
  764. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  765. return QDF_STATUS_SUCCESS;
  766. }
  767. #else
  768. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  769. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  770. {
  771. return QDF_STATUS_E_NOMEM;
  772. }
  773. #endif
  774. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  775. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  776. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  777. /**
  778. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  779. * @vdev: DP Vdev handle
  780. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  781. * @desc_pool_id: Descriptor Pool ID
  782. *
  783. * Return:
  784. */
  785. static
  786. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  787. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  788. {
  789. uint8_t i;
  790. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  791. struct dp_tx_seg_info_s *seg_info;
  792. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  793. struct dp_soc *soc = vdev->pdev->soc;
  794. /* Allocate an extension descriptor */
  795. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  796. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  797. if (!msdu_ext_desc) {
  798. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  799. return NULL;
  800. }
  801. if (msdu_info->exception_fw &&
  802. qdf_unlikely(vdev->mesh_vdev)) {
  803. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  804. &msdu_info->meta_data[0],
  805. sizeof(struct htt_tx_msdu_desc_ext2_t));
  806. qdf_atomic_inc(&soc->num_tx_exception);
  807. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  808. }
  809. switch (msdu_info->frm_type) {
  810. case dp_tx_frm_sg:
  811. case dp_tx_frm_me:
  812. case dp_tx_frm_raw:
  813. seg_info = msdu_info->u.sg_info.curr_seg;
  814. /* Update the buffer pointers in MSDU Extension Descriptor */
  815. for (i = 0; i < seg_info->frag_cnt; i++) {
  816. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  817. seg_info->frags[i].paddr_lo,
  818. seg_info->frags[i].paddr_hi,
  819. seg_info->frags[i].len);
  820. }
  821. break;
  822. case dp_tx_frm_tso:
  823. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  824. &cached_ext_desc[0]);
  825. break;
  826. default:
  827. break;
  828. }
  829. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  830. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  831. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  832. msdu_ext_desc->vaddr);
  833. return msdu_ext_desc;
  834. }
  835. /**
  836. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  837. *
  838. * @skb: skb to be traced
  839. * @msdu_id: msdu_id of the packet
  840. * @vdev_id: vdev_id of the packet
  841. *
  842. * Return: None
  843. */
  844. #ifdef DP_DISABLE_TX_PKT_TRACE
  845. static void dp_tx_trace_pkt(struct dp_soc *soc,
  846. qdf_nbuf_t skb, uint16_t msdu_id,
  847. uint8_t vdev_id)
  848. {
  849. }
  850. #else
  851. static void dp_tx_trace_pkt(struct dp_soc *soc,
  852. qdf_nbuf_t skb, uint16_t msdu_id,
  853. uint8_t vdev_id)
  854. {
  855. if (dp_is_tput_high(soc))
  856. return;
  857. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  858. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  859. DPTRACE(qdf_dp_trace_ptr(skb,
  860. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  861. QDF_TRACE_DEFAULT_PDEV_ID,
  862. qdf_nbuf_data_addr(skb),
  863. sizeof(qdf_nbuf_data(skb)),
  864. msdu_id, vdev_id, 0));
  865. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  866. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  867. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  868. msdu_id, QDF_TX));
  869. }
  870. #endif
  871. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  872. /**
  873. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  874. * exception by the upper layer (OS_IF)
  875. * @soc: DP soc handle
  876. * @nbuf: packet to be transmitted
  877. *
  878. * Returns: 1 if the packet is marked as exception,
  879. * 0, if the packet is not marked as exception.
  880. */
  881. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  882. qdf_nbuf_t nbuf)
  883. {
  884. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  885. }
  886. #else
  887. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  888. qdf_nbuf_t nbuf)
  889. {
  890. return 0;
  891. }
  892. #endif
  893. /**
  894. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  895. * @vdev: DP vdev handle
  896. * @nbuf: skb
  897. * @desc_pool_id: Descriptor pool ID
  898. * @meta_data: Metadata to the fw
  899. * @tx_exc_metadata: Handle that holds exception path metadata
  900. * Allocate and prepare Tx descriptor with msdu information.
  901. *
  902. * Return: Pointer to Tx Descriptor on success,
  903. * NULL on failure
  904. */
  905. static
  906. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  907. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  908. struct dp_tx_msdu_info_s *msdu_info,
  909. struct cdp_tx_exception_metadata *tx_exc_metadata)
  910. {
  911. uint8_t align_pad;
  912. uint8_t is_exception = 0;
  913. uint8_t htt_hdr_size;
  914. struct dp_tx_desc_s *tx_desc;
  915. struct dp_pdev *pdev = vdev->pdev;
  916. struct dp_soc *soc = pdev->soc;
  917. if (dp_tx_limit_check(vdev))
  918. return NULL;
  919. /* Allocate software Tx descriptor */
  920. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  921. if (qdf_unlikely(!tx_desc)) {
  922. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  923. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  924. return NULL;
  925. }
  926. dp_tx_outstanding_inc(pdev);
  927. /* Initialize the SW tx descriptor */
  928. tx_desc->nbuf = nbuf;
  929. tx_desc->frm_type = dp_tx_frm_std;
  930. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  931. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  932. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  933. tx_desc->vdev_id = vdev->vdev_id;
  934. tx_desc->pdev = pdev;
  935. tx_desc->msdu_ext_desc = NULL;
  936. tx_desc->pkt_offset = 0;
  937. tx_desc->length = qdf_nbuf_headlen(nbuf);
  938. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  939. if (qdf_unlikely(vdev->multipass_en)) {
  940. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  941. goto failure;
  942. }
  943. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  944. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  945. is_exception = 1;
  946. /*
  947. * For special modes (vdev_type == ocb or mesh), data frames should be
  948. * transmitted using varying transmit parameters (tx spec) which include
  949. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  950. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  951. * These frames are sent as exception packets to firmware.
  952. *
  953. * HW requirement is that metadata should always point to a
  954. * 8-byte aligned address. So we add alignment pad to start of buffer.
  955. * HTT Metadata should be ensured to be multiple of 8-bytes,
  956. * to get 8-byte aligned start address along with align_pad added
  957. *
  958. * |-----------------------------|
  959. * | |
  960. * |-----------------------------| <-----Buffer Pointer Address given
  961. * | | ^ in HW descriptor (aligned)
  962. * | HTT Metadata | |
  963. * | | |
  964. * | | | Packet Offset given in descriptor
  965. * | | |
  966. * |-----------------------------| |
  967. * | Alignment Pad | v
  968. * |-----------------------------| <----- Actual buffer start address
  969. * | SKB Data | (Unaligned)
  970. * | |
  971. * | |
  972. * | |
  973. * | |
  974. * | |
  975. * |-----------------------------|
  976. */
  977. if (qdf_unlikely((msdu_info->exception_fw)) ||
  978. (vdev->opmode == wlan_op_mode_ocb) ||
  979. (tx_exc_metadata &&
  980. tx_exc_metadata->is_tx_sniffer)) {
  981. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  982. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  983. DP_STATS_INC(vdev,
  984. tx_i.dropped.headroom_insufficient, 1);
  985. goto failure;
  986. }
  987. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  988. dp_tx_err("qdf_nbuf_push_head failed");
  989. goto failure;
  990. }
  991. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  992. msdu_info);
  993. if (htt_hdr_size == 0)
  994. goto failure;
  995. tx_desc->length = qdf_nbuf_headlen(nbuf);
  996. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  997. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  998. is_exception = 1;
  999. tx_desc->length -= tx_desc->pkt_offset;
  1000. }
  1001. #if !TQM_BYPASS_WAR
  1002. if (is_exception || tx_exc_metadata)
  1003. #endif
  1004. {
  1005. /* Temporary WAR due to TQM VP issues */
  1006. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1007. qdf_atomic_inc(&soc->num_tx_exception);
  1008. }
  1009. return tx_desc;
  1010. failure:
  1011. dp_tx_desc_release(tx_desc, desc_pool_id);
  1012. return NULL;
  1013. }
  1014. /**
  1015. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1016. * @vdev: DP vdev handle
  1017. * @nbuf: skb
  1018. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1019. * @desc_pool_id : Descriptor Pool ID
  1020. *
  1021. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1022. * information. For frames wth fragments, allocate and prepare
  1023. * an MSDU extension descriptor
  1024. *
  1025. * Return: Pointer to Tx Descriptor on success,
  1026. * NULL on failure
  1027. */
  1028. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1029. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1030. uint8_t desc_pool_id)
  1031. {
  1032. struct dp_tx_desc_s *tx_desc;
  1033. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1034. struct dp_pdev *pdev = vdev->pdev;
  1035. struct dp_soc *soc = pdev->soc;
  1036. if (dp_tx_limit_check(vdev))
  1037. return NULL;
  1038. /* Allocate software Tx descriptor */
  1039. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1040. if (!tx_desc) {
  1041. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1042. return NULL;
  1043. }
  1044. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1045. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1046. dp_tx_outstanding_inc(pdev);
  1047. /* Initialize the SW tx descriptor */
  1048. tx_desc->nbuf = nbuf;
  1049. tx_desc->frm_type = msdu_info->frm_type;
  1050. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1051. tx_desc->vdev_id = vdev->vdev_id;
  1052. tx_desc->pdev = pdev;
  1053. tx_desc->pkt_offset = 0;
  1054. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1055. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1056. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1057. /* Handle scattered frames - TSO/SG/ME */
  1058. /* Allocate and prepare an extension descriptor for scattered frames */
  1059. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1060. if (!msdu_ext_desc) {
  1061. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1062. goto failure;
  1063. }
  1064. #if TQM_BYPASS_WAR
  1065. /* Temporary WAR due to TQM VP issues */
  1066. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1067. qdf_atomic_inc(&soc->num_tx_exception);
  1068. #endif
  1069. if (qdf_unlikely(msdu_info->exception_fw))
  1070. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1071. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1072. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1073. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1074. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1075. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1076. else
  1077. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1078. return tx_desc;
  1079. failure:
  1080. dp_tx_desc_release(tx_desc, desc_pool_id);
  1081. return NULL;
  1082. }
  1083. /**
  1084. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1085. * @vdev: DP vdev handle
  1086. * @nbuf: buffer pointer
  1087. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1088. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1089. * descriptor
  1090. *
  1091. * Return:
  1092. */
  1093. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1094. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1095. {
  1096. qdf_nbuf_t curr_nbuf = NULL;
  1097. uint16_t total_len = 0;
  1098. qdf_dma_addr_t paddr;
  1099. int32_t i;
  1100. int32_t mapped_buf_num = 0;
  1101. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1102. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1103. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1104. /* Continue only if frames are of DATA type */
  1105. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1106. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1107. dp_tx_debug("Pkt. recd is of not data type");
  1108. goto error;
  1109. }
  1110. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1111. if (vdev->raw_mode_war &&
  1112. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1113. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1114. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1115. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1116. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1117. /*
  1118. * Number of nbuf's must not exceed the size of the frags
  1119. * array in seg_info.
  1120. */
  1121. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1122. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1123. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1124. goto error;
  1125. }
  1126. if (QDF_STATUS_SUCCESS !=
  1127. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1128. curr_nbuf,
  1129. QDF_DMA_TO_DEVICE,
  1130. curr_nbuf->len)) {
  1131. dp_tx_err("%s dma map error ", __func__);
  1132. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1133. goto error;
  1134. }
  1135. /* Update the count of mapped nbuf's */
  1136. mapped_buf_num++;
  1137. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1138. seg_info->frags[i].paddr_lo = paddr;
  1139. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1140. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1141. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1142. total_len += qdf_nbuf_len(curr_nbuf);
  1143. }
  1144. seg_info->frag_cnt = i;
  1145. seg_info->total_len = total_len;
  1146. seg_info->next = NULL;
  1147. sg_info->curr_seg = seg_info;
  1148. msdu_info->frm_type = dp_tx_frm_raw;
  1149. msdu_info->num_seg = 1;
  1150. return nbuf;
  1151. error:
  1152. i = 0;
  1153. while (nbuf) {
  1154. curr_nbuf = nbuf;
  1155. if (i < mapped_buf_num) {
  1156. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1157. QDF_DMA_TO_DEVICE,
  1158. curr_nbuf->len);
  1159. i++;
  1160. }
  1161. nbuf = qdf_nbuf_next(nbuf);
  1162. qdf_nbuf_free(curr_nbuf);
  1163. }
  1164. return NULL;
  1165. }
  1166. /**
  1167. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1168. * @soc: DP soc handle
  1169. * @nbuf: Buffer pointer
  1170. *
  1171. * unmap the chain of nbufs that belong to this RAW frame.
  1172. *
  1173. * Return: None
  1174. */
  1175. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1176. qdf_nbuf_t nbuf)
  1177. {
  1178. qdf_nbuf_t cur_nbuf = nbuf;
  1179. do {
  1180. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1181. QDF_DMA_TO_DEVICE,
  1182. cur_nbuf->len);
  1183. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1184. } while (cur_nbuf);
  1185. }
  1186. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1187. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1188. qdf_nbuf_t nbuf)
  1189. {
  1190. qdf_nbuf_t nbuf_local;
  1191. struct dp_vdev *vdev_local = vdev_hdl;
  1192. do {
  1193. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1194. break;
  1195. nbuf_local = nbuf;
  1196. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1197. htt_cmn_pkt_type_raw))
  1198. break;
  1199. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1200. break;
  1201. else if (qdf_nbuf_is_tso((nbuf_local)))
  1202. break;
  1203. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1204. (nbuf_local),
  1205. NULL, 1, 0);
  1206. } while (0);
  1207. }
  1208. #endif
  1209. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1210. /**
  1211. * dp_tx_update_stats() - Update soc level tx stats
  1212. * @soc: DP soc handle
  1213. * @nbuf: packet being transmitted
  1214. *
  1215. * Returns: none
  1216. */
  1217. void dp_tx_update_stats(struct dp_soc *soc,
  1218. qdf_nbuf_t nbuf)
  1219. {
  1220. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1221. }
  1222. int
  1223. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1224. struct dp_tx_desc_s *tx_desc,
  1225. uint8_t tid)
  1226. {
  1227. struct dp_swlm *swlm = &soc->swlm;
  1228. union swlm_data swlm_query_data;
  1229. struct dp_swlm_tcl_data tcl_data;
  1230. QDF_STATUS status;
  1231. int ret;
  1232. if (qdf_unlikely(!swlm->is_enabled))
  1233. return 0;
  1234. tcl_data.nbuf = tx_desc->nbuf;
  1235. tcl_data.tid = tid;
  1236. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1237. swlm_query_data.tcl_data = &tcl_data;
  1238. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1239. if (QDF_IS_STATUS_ERROR(status)) {
  1240. dp_swlm_tcl_reset_session_data(soc);
  1241. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1242. return 0;
  1243. }
  1244. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1245. if (ret) {
  1246. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1247. } else {
  1248. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1249. }
  1250. return ret;
  1251. }
  1252. void
  1253. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1254. int coalesce)
  1255. {
  1256. if (coalesce)
  1257. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1258. else
  1259. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1260. }
  1261. #endif
  1262. #ifdef FEATURE_RUNTIME_PM
  1263. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1264. {
  1265. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1266. }
  1267. /**
  1268. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1269. * @soc: Datapath soc handle
  1270. * @hal_ring_hdl: HAL ring handle
  1271. * @coalesce: Coalesce the current write or not
  1272. *
  1273. * Wrapper for HAL ring access end for data transmission for
  1274. * FEATURE_RUNTIME_PM
  1275. *
  1276. * Returns: none
  1277. */
  1278. void
  1279. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1280. hal_ring_handle_t hal_ring_hdl,
  1281. int coalesce)
  1282. {
  1283. int ret;
  1284. /*
  1285. * Avoid runtime get and put APIs under high throughput scenarios.
  1286. */
  1287. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1288. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1289. return;
  1290. }
  1291. ret = hif_pm_runtime_get(soc->hif_handle,
  1292. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1293. switch (ret) {
  1294. case 0:
  1295. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1296. hif_pm_runtime_put(soc->hif_handle,
  1297. RTPM_ID_DW_TX_HW_ENQUEUE);
  1298. break;
  1299. /*
  1300. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1301. * take the dp runtime refcount using dp_runtime_get,
  1302. * check link state,if up, write TX ring HP, else just set flush event.
  1303. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1304. * zero or time out, then flush pending tx.
  1305. */
  1306. case -EBUSY:
  1307. case -EINPROGRESS:
  1308. dp_runtime_get(soc);
  1309. if (hif_pm_get_link_state(soc->hif_handle) ==
  1310. HIF_PM_LINK_STATE_UP) {
  1311. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1312. } else {
  1313. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1314. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1315. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1316. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1317. }
  1318. dp_runtime_put(soc);
  1319. break;
  1320. default:
  1321. dp_runtime_get(soc);
  1322. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1323. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1324. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1325. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1326. dp_runtime_put(soc);
  1327. }
  1328. }
  1329. #else
  1330. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1331. {
  1332. return 0;
  1333. }
  1334. #endif
  1335. /**
  1336. * dp_cce_classify() - Classify the frame based on CCE rules
  1337. * @vdev: DP vdev handle
  1338. * @nbuf: skb
  1339. *
  1340. * Classify frames based on CCE rules
  1341. * Return: bool( true if classified,
  1342. * else false)
  1343. */
  1344. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1345. {
  1346. qdf_ether_header_t *eh = NULL;
  1347. uint16_t ether_type;
  1348. qdf_llc_t *llcHdr;
  1349. qdf_nbuf_t nbuf_clone = NULL;
  1350. qdf_dot3_qosframe_t *qos_wh = NULL;
  1351. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1352. /*
  1353. * In case of mesh packets or hlos tid override enabled,
  1354. * don't do any classification
  1355. */
  1356. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1357. & DP_TX_SKIP_CCE_CLASSIFY))
  1358. return false;
  1359. }
  1360. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1361. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1362. ether_type = eh->ether_type;
  1363. llcHdr = (qdf_llc_t *)(nbuf->data +
  1364. sizeof(qdf_ether_header_t));
  1365. } else {
  1366. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1367. /* For encrypted packets don't do any classification */
  1368. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1369. return false;
  1370. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1371. if (qdf_unlikely(
  1372. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1373. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1374. ether_type = *(uint16_t *)(nbuf->data
  1375. + QDF_IEEE80211_4ADDR_HDR_LEN
  1376. + sizeof(qdf_llc_t)
  1377. - sizeof(ether_type));
  1378. llcHdr = (qdf_llc_t *)(nbuf->data +
  1379. QDF_IEEE80211_4ADDR_HDR_LEN);
  1380. } else {
  1381. ether_type = *(uint16_t *)(nbuf->data
  1382. + QDF_IEEE80211_3ADDR_HDR_LEN
  1383. + sizeof(qdf_llc_t)
  1384. - sizeof(ether_type));
  1385. llcHdr = (qdf_llc_t *)(nbuf->data +
  1386. QDF_IEEE80211_3ADDR_HDR_LEN);
  1387. }
  1388. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1389. && (ether_type ==
  1390. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1391. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1392. return true;
  1393. }
  1394. }
  1395. return false;
  1396. }
  1397. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1398. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1399. sizeof(*llcHdr));
  1400. nbuf_clone = qdf_nbuf_clone(nbuf);
  1401. if (qdf_unlikely(nbuf_clone)) {
  1402. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1403. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1404. qdf_nbuf_pull_head(nbuf_clone,
  1405. sizeof(qdf_net_vlanhdr_t));
  1406. }
  1407. }
  1408. } else {
  1409. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1410. nbuf_clone = qdf_nbuf_clone(nbuf);
  1411. if (qdf_unlikely(nbuf_clone)) {
  1412. qdf_nbuf_pull_head(nbuf_clone,
  1413. sizeof(qdf_net_vlanhdr_t));
  1414. }
  1415. }
  1416. }
  1417. if (qdf_unlikely(nbuf_clone))
  1418. nbuf = nbuf_clone;
  1419. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1420. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1421. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1422. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1423. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1424. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1425. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1426. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1427. if (qdf_unlikely(nbuf_clone))
  1428. qdf_nbuf_free(nbuf_clone);
  1429. return true;
  1430. }
  1431. if (qdf_unlikely(nbuf_clone))
  1432. qdf_nbuf_free(nbuf_clone);
  1433. return false;
  1434. }
  1435. /**
  1436. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1437. * @vdev: DP vdev handle
  1438. * @nbuf: skb
  1439. *
  1440. * Extract the DSCP or PCP information from frame and map into TID value.
  1441. *
  1442. * Return: void
  1443. */
  1444. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1445. struct dp_tx_msdu_info_s *msdu_info)
  1446. {
  1447. uint8_t tos = 0, dscp_tid_override = 0;
  1448. uint8_t *hdr_ptr, *L3datap;
  1449. uint8_t is_mcast = 0;
  1450. qdf_ether_header_t *eh = NULL;
  1451. qdf_ethervlan_header_t *evh = NULL;
  1452. uint16_t ether_type;
  1453. qdf_llc_t *llcHdr;
  1454. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1455. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1456. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1457. eh = (qdf_ether_header_t *)nbuf->data;
  1458. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1459. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1460. } else {
  1461. qdf_dot3_qosframe_t *qos_wh =
  1462. (qdf_dot3_qosframe_t *) nbuf->data;
  1463. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1464. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1465. return;
  1466. }
  1467. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1468. ether_type = eh->ether_type;
  1469. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1470. /*
  1471. * Check if packet is dot3 or eth2 type.
  1472. */
  1473. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1474. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1475. sizeof(*llcHdr));
  1476. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1477. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1478. sizeof(*llcHdr);
  1479. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1480. + sizeof(*llcHdr) +
  1481. sizeof(qdf_net_vlanhdr_t));
  1482. } else {
  1483. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1484. sizeof(*llcHdr);
  1485. }
  1486. } else {
  1487. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1488. evh = (qdf_ethervlan_header_t *) eh;
  1489. ether_type = evh->ether_type;
  1490. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1491. }
  1492. }
  1493. /*
  1494. * Find priority from IP TOS DSCP field
  1495. */
  1496. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1497. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1498. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1499. /* Only for unicast frames */
  1500. if (!is_mcast) {
  1501. /* send it on VO queue */
  1502. msdu_info->tid = DP_VO_TID;
  1503. }
  1504. } else {
  1505. /*
  1506. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1507. * from TOS byte.
  1508. */
  1509. tos = ip->ip_tos;
  1510. dscp_tid_override = 1;
  1511. }
  1512. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1513. /* TODO
  1514. * use flowlabel
  1515. *igmpmld cases to be handled in phase 2
  1516. */
  1517. unsigned long ver_pri_flowlabel;
  1518. unsigned long pri;
  1519. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1520. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1521. DP_IPV6_PRIORITY_SHIFT;
  1522. tos = pri;
  1523. dscp_tid_override = 1;
  1524. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1525. msdu_info->tid = DP_VO_TID;
  1526. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1527. /* Only for unicast frames */
  1528. if (!is_mcast) {
  1529. /* send ucast arp on VO queue */
  1530. msdu_info->tid = DP_VO_TID;
  1531. }
  1532. }
  1533. /*
  1534. * Assign all MCAST packets to BE
  1535. */
  1536. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1537. if (is_mcast) {
  1538. tos = 0;
  1539. dscp_tid_override = 1;
  1540. }
  1541. }
  1542. if (dscp_tid_override == 1) {
  1543. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1544. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1545. }
  1546. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1547. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1548. return;
  1549. }
  1550. /**
  1551. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1552. * @vdev: DP vdev handle
  1553. * @nbuf: skb
  1554. *
  1555. * Software based TID classification is required when more than 2 DSCP-TID
  1556. * mapping tables are needed.
  1557. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1558. *
  1559. * Return: void
  1560. */
  1561. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1562. struct dp_tx_msdu_info_s *msdu_info)
  1563. {
  1564. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1565. /*
  1566. * skip_sw_tid_classification flag will set in below cases-
  1567. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1568. * 2. hlos_tid_override enabled for vdev
  1569. * 3. mesh mode enabled for vdev
  1570. */
  1571. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1572. /* Update tid in msdu_info from skb priority */
  1573. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1574. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1575. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1576. return;
  1577. }
  1578. return;
  1579. }
  1580. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1581. }
  1582. #ifdef FEATURE_WLAN_TDLS
  1583. /**
  1584. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1585. * @soc: datapath SOC
  1586. * @vdev: datapath vdev
  1587. * @tx_desc: TX descriptor
  1588. *
  1589. * Return: None
  1590. */
  1591. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1592. struct dp_vdev *vdev,
  1593. struct dp_tx_desc_s *tx_desc)
  1594. {
  1595. if (vdev) {
  1596. if (vdev->is_tdls_frame) {
  1597. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1598. vdev->is_tdls_frame = false;
  1599. }
  1600. }
  1601. }
  1602. /**
  1603. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1604. * @soc: dp_soc handle
  1605. * @tx_desc: TX descriptor
  1606. * @vdev: datapath vdev handle
  1607. *
  1608. * Return: None
  1609. */
  1610. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1611. struct dp_tx_desc_s *tx_desc)
  1612. {
  1613. struct hal_tx_completion_status ts = {0};
  1614. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1615. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1616. DP_MOD_ID_TDLS);
  1617. if (qdf_unlikely(!vdev)) {
  1618. dp_err_rl("vdev is null!");
  1619. goto error;
  1620. }
  1621. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1622. if (vdev->tx_non_std_data_callback.func) {
  1623. qdf_nbuf_set_next(nbuf, NULL);
  1624. vdev->tx_non_std_data_callback.func(
  1625. vdev->tx_non_std_data_callback.ctxt,
  1626. nbuf, ts.status);
  1627. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1628. return;
  1629. } else {
  1630. dp_err_rl("callback func is null");
  1631. }
  1632. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1633. error:
  1634. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1635. qdf_nbuf_free(nbuf);
  1636. }
  1637. /**
  1638. * dp_tx_msdu_single_map() - do nbuf map
  1639. * @vdev: DP vdev handle
  1640. * @tx_desc: DP TX descriptor pointer
  1641. * @nbuf: skb pointer
  1642. *
  1643. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1644. * operation done in other component.
  1645. *
  1646. * Return: QDF_STATUS
  1647. */
  1648. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1649. struct dp_tx_desc_s *tx_desc,
  1650. qdf_nbuf_t nbuf)
  1651. {
  1652. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1653. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1654. nbuf,
  1655. QDF_DMA_TO_DEVICE,
  1656. nbuf->len);
  1657. else
  1658. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1659. QDF_DMA_TO_DEVICE);
  1660. }
  1661. #else
  1662. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1663. struct dp_vdev *vdev,
  1664. struct dp_tx_desc_s *tx_desc)
  1665. {
  1666. }
  1667. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1668. struct dp_tx_desc_s *tx_desc)
  1669. {
  1670. }
  1671. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1672. struct dp_tx_desc_s *tx_desc,
  1673. qdf_nbuf_t nbuf)
  1674. {
  1675. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1676. nbuf,
  1677. QDF_DMA_TO_DEVICE,
  1678. nbuf->len);
  1679. }
  1680. #endif
  1681. #ifdef MESH_MODE_SUPPORT
  1682. /**
  1683. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1684. * @soc: datapath SOC
  1685. * @vdev: datapath vdev
  1686. * @tx_desc: TX descriptor
  1687. *
  1688. * Return: None
  1689. */
  1690. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1691. struct dp_vdev *vdev,
  1692. struct dp_tx_desc_s *tx_desc)
  1693. {
  1694. if (qdf_unlikely(vdev->mesh_vdev))
  1695. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1696. }
  1697. /**
  1698. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1699. * @soc: dp_soc handle
  1700. * @tx_desc: TX descriptor
  1701. * @vdev: datapath vdev handle
  1702. *
  1703. * Return: None
  1704. */
  1705. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1706. struct dp_tx_desc_s *tx_desc)
  1707. {
  1708. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1709. struct dp_vdev *vdev = NULL;
  1710. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1711. qdf_nbuf_free(nbuf);
  1712. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1713. } else {
  1714. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1715. DP_MOD_ID_MESH);
  1716. if (vdev && vdev->osif_tx_free_ext)
  1717. vdev->osif_tx_free_ext((nbuf));
  1718. else
  1719. qdf_nbuf_free(nbuf);
  1720. if (vdev)
  1721. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1722. }
  1723. }
  1724. #else
  1725. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1726. struct dp_vdev *vdev,
  1727. struct dp_tx_desc_s *tx_desc)
  1728. {
  1729. }
  1730. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1731. struct dp_tx_desc_s *tx_desc)
  1732. {
  1733. }
  1734. #endif
  1735. /**
  1736. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1737. * @vdev: DP vdev handle
  1738. * @nbuf: skb
  1739. *
  1740. * Return: 1 if frame needs to be dropped else 0
  1741. */
  1742. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1743. {
  1744. struct dp_pdev *pdev = NULL;
  1745. struct dp_ast_entry *src_ast_entry = NULL;
  1746. struct dp_ast_entry *dst_ast_entry = NULL;
  1747. struct dp_soc *soc = NULL;
  1748. qdf_assert(vdev);
  1749. pdev = vdev->pdev;
  1750. qdf_assert(pdev);
  1751. soc = pdev->soc;
  1752. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1753. (soc, dstmac, vdev->pdev->pdev_id);
  1754. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1755. (soc, srcmac, vdev->pdev->pdev_id);
  1756. if (dst_ast_entry && src_ast_entry) {
  1757. if (dst_ast_entry->peer_id ==
  1758. src_ast_entry->peer_id)
  1759. return 1;
  1760. }
  1761. return 0;
  1762. }
  1763. /**
  1764. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1765. * @vdev: DP vdev handle
  1766. * @nbuf: skb
  1767. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1768. * @meta_data: Metadata to the fw
  1769. * @tx_q: Tx queue to be used for this Tx frame
  1770. * @peer_id: peer_id of the peer in case of NAWDS frames
  1771. * @tx_exc_metadata: Handle that holds exception path metadata
  1772. *
  1773. * Return: NULL on success,
  1774. * nbuf when it fails to send
  1775. */
  1776. qdf_nbuf_t
  1777. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1778. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1779. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1780. {
  1781. struct dp_pdev *pdev = vdev->pdev;
  1782. struct dp_soc *soc = pdev->soc;
  1783. struct dp_tx_desc_s *tx_desc;
  1784. QDF_STATUS status;
  1785. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1786. uint16_t htt_tcl_metadata = 0;
  1787. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1788. uint8_t tid = msdu_info->tid;
  1789. struct cdp_tid_tx_stats *tid_stats = NULL;
  1790. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1791. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1792. msdu_info, tx_exc_metadata);
  1793. if (!tx_desc) {
  1794. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1795. vdev, tx_q->desc_pool_id);
  1796. drop_code = TX_DESC_ERR;
  1797. goto fail_return;
  1798. }
  1799. if (qdf_unlikely(soc->cce_disable)) {
  1800. if (dp_cce_classify(vdev, nbuf) == true) {
  1801. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1802. tid = DP_VO_TID;
  1803. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1804. }
  1805. }
  1806. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1807. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1808. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1809. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1810. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1811. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1812. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1813. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1814. peer_id);
  1815. } else
  1816. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1817. if (msdu_info->exception_fw)
  1818. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1819. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1820. !pdev->enhanced_stats_en);
  1821. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1822. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1823. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1824. /* Handle failure */
  1825. dp_err("qdf_nbuf_map failed");
  1826. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1827. drop_code = TX_DMA_MAP_ERR;
  1828. goto release_desc;
  1829. }
  1830. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1831. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1832. tx_desc->id, DP_TX_DESC_MAP);
  1833. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1834. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1835. htt_tcl_metadata,
  1836. tx_exc_metadata, msdu_info);
  1837. if (status != QDF_STATUS_SUCCESS) {
  1838. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1839. tx_desc, tx_q->ring_id);
  1840. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1841. tx_desc->id, DP_TX_DESC_UNMAP);
  1842. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1843. QDF_DMA_TO_DEVICE,
  1844. nbuf->len);
  1845. drop_code = TX_HW_ENQUEUE;
  1846. goto release_desc;
  1847. }
  1848. return NULL;
  1849. release_desc:
  1850. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1851. fail_return:
  1852. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1853. tid_stats = &pdev->stats.tid_stats.
  1854. tid_tx_stats[tx_q->ring_id][tid];
  1855. tid_stats->swdrop_cnt[drop_code]++;
  1856. return nbuf;
  1857. }
  1858. /**
  1859. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1860. * @soc: Soc handle
  1861. * @desc: software Tx descriptor to be processed
  1862. *
  1863. * Return: none
  1864. */
  1865. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1866. struct dp_tx_desc_s *desc)
  1867. {
  1868. qdf_nbuf_t nbuf = desc->nbuf;
  1869. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1870. /* nbuf already freed in vdev detach path */
  1871. if (!nbuf)
  1872. return;
  1873. /* If it is TDLS mgmt, don't unmap or free the frame */
  1874. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1875. return dp_non_std_tx_comp_free_buff(soc, desc);
  1876. /* 0 : MSDU buffer, 1 : MLE */
  1877. if (desc->msdu_ext_desc) {
  1878. /* TSO free */
  1879. if (hal_tx_ext_desc_get_tso_enable(
  1880. desc->msdu_ext_desc->vaddr)) {
  1881. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1882. desc->id, DP_TX_COMP_MSDU_EXT);
  1883. dp_tx_tso_seg_history_add(soc, desc->tso_desc,
  1884. desc->nbuf, desc->id, type);
  1885. /* unmap eash TSO seg before free the nbuf */
  1886. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1887. desc->tso_num_desc);
  1888. qdf_nbuf_free(nbuf);
  1889. return;
  1890. }
  1891. }
  1892. /* If it's ME frame, dont unmap the cloned nbuf's */
  1893. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1894. goto nbuf_free;
  1895. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1896. dp_tx_unmap(soc, desc);
  1897. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1898. return dp_mesh_tx_comp_free_buff(soc, desc);
  1899. nbuf_free:
  1900. qdf_nbuf_free(nbuf);
  1901. }
  1902. /**
  1903. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1904. * @vdev: DP vdev handle
  1905. * @nbuf: skb
  1906. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1907. *
  1908. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1909. *
  1910. * Return: NULL on success,
  1911. * nbuf when it fails to send
  1912. */
  1913. #if QDF_LOCK_STATS
  1914. noinline
  1915. #else
  1916. #endif
  1917. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1918. struct dp_tx_msdu_info_s *msdu_info)
  1919. {
  1920. uint32_t i;
  1921. struct dp_pdev *pdev = vdev->pdev;
  1922. struct dp_soc *soc = pdev->soc;
  1923. struct dp_tx_desc_s *tx_desc;
  1924. bool is_cce_classified = false;
  1925. QDF_STATUS status;
  1926. uint16_t htt_tcl_metadata = 0;
  1927. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1928. struct cdp_tid_tx_stats *tid_stats = NULL;
  1929. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1930. if (qdf_unlikely(soc->cce_disable)) {
  1931. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1932. if (is_cce_classified) {
  1933. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1934. msdu_info->tid = DP_VO_TID;
  1935. }
  1936. }
  1937. if (msdu_info->frm_type == dp_tx_frm_me)
  1938. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1939. i = 0;
  1940. /* Print statement to track i and num_seg */
  1941. /*
  1942. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1943. * descriptors using information in msdu_info
  1944. */
  1945. while (i < msdu_info->num_seg) {
  1946. /*
  1947. * Setup Tx descriptor for an MSDU, and MSDU extension
  1948. * descriptor
  1949. */
  1950. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1951. tx_q->desc_pool_id);
  1952. if (!tx_desc) {
  1953. if (msdu_info->frm_type == dp_tx_frm_me) {
  1954. prep_desc_fail++;
  1955. dp_tx_me_free_buf(pdev,
  1956. (void *)(msdu_info->u.sg_info
  1957. .curr_seg->frags[0].vaddr));
  1958. if (prep_desc_fail == msdu_info->num_seg) {
  1959. /*
  1960. * Unmap is needed only if descriptor
  1961. * preparation failed for all segments.
  1962. */
  1963. qdf_nbuf_unmap(soc->osdev,
  1964. msdu_info->u.sg_info.
  1965. curr_seg->nbuf,
  1966. QDF_DMA_TO_DEVICE);
  1967. }
  1968. /*
  1969. * Free the nbuf for the current segment
  1970. * and make it point to the next in the list.
  1971. * For me, there are as many segments as there
  1972. * are no of clients.
  1973. */
  1974. qdf_nbuf_free(msdu_info->u.sg_info
  1975. .curr_seg->nbuf);
  1976. if (msdu_info->u.sg_info.curr_seg->next) {
  1977. msdu_info->u.sg_info.curr_seg =
  1978. msdu_info->u.sg_info
  1979. .curr_seg->next;
  1980. nbuf = msdu_info->u.sg_info
  1981. .curr_seg->nbuf;
  1982. }
  1983. i++;
  1984. continue;
  1985. }
  1986. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1987. dp_tx_tso_seg_history_add(
  1988. soc,
  1989. msdu_info->u.tso_info.curr_seg,
  1990. nbuf, 0, DP_TX_DESC_UNMAP);
  1991. dp_tx_tso_unmap_segment(soc,
  1992. msdu_info->u.tso_info.
  1993. curr_seg,
  1994. msdu_info->u.tso_info.
  1995. tso_num_seg_list);
  1996. if (msdu_info->u.tso_info.curr_seg->next) {
  1997. msdu_info->u.tso_info.curr_seg =
  1998. msdu_info->u.tso_info.curr_seg->next;
  1999. i++;
  2000. continue;
  2001. }
  2002. }
  2003. goto done;
  2004. }
  2005. if (msdu_info->frm_type == dp_tx_frm_me) {
  2006. tx_desc->me_buffer =
  2007. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  2008. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2009. }
  2010. if (is_cce_classified)
  2011. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2012. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2013. if (msdu_info->exception_fw) {
  2014. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2015. }
  2016. /*
  2017. * For frames with multiple segments (TSO, ME), jump to next
  2018. * segment.
  2019. */
  2020. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2021. if (msdu_info->u.tso_info.curr_seg->next) {
  2022. msdu_info->u.tso_info.curr_seg =
  2023. msdu_info->u.tso_info.curr_seg->next;
  2024. /*
  2025. * If this is a jumbo nbuf, then increment the
  2026. * number of nbuf users for each additional
  2027. * segment of the msdu. This will ensure that
  2028. * the skb is freed only after receiving tx
  2029. * completion for all segments of an nbuf
  2030. */
  2031. qdf_nbuf_inc_users(nbuf);
  2032. /* Check with MCL if this is needed */
  2033. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2034. */
  2035. }
  2036. }
  2037. /*
  2038. * Enqueue the Tx MSDU descriptor to HW for transmit
  2039. */
  2040. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2041. htt_tcl_metadata,
  2042. NULL, msdu_info);
  2043. if (status != QDF_STATUS_SUCCESS) {
  2044. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2045. tx_desc, tx_q->ring_id);
  2046. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2047. tid_stats = &pdev->stats.tid_stats.
  2048. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2049. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2050. if (msdu_info->frm_type == dp_tx_frm_me) {
  2051. hw_enq_fail++;
  2052. if (hw_enq_fail == msdu_info->num_seg) {
  2053. /*
  2054. * Unmap is needed only if enqueue
  2055. * failed for all segments.
  2056. */
  2057. qdf_nbuf_unmap(soc->osdev,
  2058. msdu_info->u.sg_info.
  2059. curr_seg->nbuf,
  2060. QDF_DMA_TO_DEVICE);
  2061. }
  2062. /*
  2063. * Free the nbuf for the current segment
  2064. * and make it point to the next in the list.
  2065. * For me, there are as many segments as there
  2066. * are no of clients.
  2067. */
  2068. qdf_nbuf_free(msdu_info->u.sg_info
  2069. .curr_seg->nbuf);
  2070. if (msdu_info->u.sg_info.curr_seg->next) {
  2071. msdu_info->u.sg_info.curr_seg =
  2072. msdu_info->u.sg_info
  2073. .curr_seg->next;
  2074. nbuf = msdu_info->u.sg_info
  2075. .curr_seg->nbuf;
  2076. } else
  2077. break;
  2078. i++;
  2079. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2080. continue;
  2081. }
  2082. /*
  2083. * For TSO frames, the nbuf users increment done for
  2084. * the current segment has to be reverted, since the
  2085. * hw enqueue for this segment failed
  2086. */
  2087. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2088. msdu_info->u.tso_info.curr_seg) {
  2089. /*
  2090. * unmap and free current,
  2091. * retransmit remaining segments
  2092. */
  2093. dp_tx_comp_free_buf(soc, tx_desc);
  2094. i++;
  2095. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2096. continue;
  2097. }
  2098. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2099. goto done;
  2100. }
  2101. /*
  2102. * TODO
  2103. * if tso_info structure can be modified to have curr_seg
  2104. * as first element, following 2 blocks of code (for TSO and SG)
  2105. * can be combined into 1
  2106. */
  2107. /*
  2108. * For Multicast-Unicast converted packets,
  2109. * each converted frame (for a client) is represented as
  2110. * 1 segment
  2111. */
  2112. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2113. (msdu_info->frm_type == dp_tx_frm_me)) {
  2114. if (msdu_info->u.sg_info.curr_seg->next) {
  2115. msdu_info->u.sg_info.curr_seg =
  2116. msdu_info->u.sg_info.curr_seg->next;
  2117. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2118. } else
  2119. break;
  2120. }
  2121. i++;
  2122. }
  2123. nbuf = NULL;
  2124. done:
  2125. return nbuf;
  2126. }
  2127. /**
  2128. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2129. * for SG frames
  2130. * @vdev: DP vdev handle
  2131. * @nbuf: skb
  2132. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2133. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2134. *
  2135. * Return: NULL on success,
  2136. * nbuf when it fails to send
  2137. */
  2138. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2139. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2140. {
  2141. uint32_t cur_frag, nr_frags, i;
  2142. qdf_dma_addr_t paddr;
  2143. struct dp_tx_sg_info_s *sg_info;
  2144. sg_info = &msdu_info->u.sg_info;
  2145. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2146. if (QDF_STATUS_SUCCESS !=
  2147. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2148. QDF_DMA_TO_DEVICE,
  2149. qdf_nbuf_headlen(nbuf))) {
  2150. dp_tx_err("dma map error");
  2151. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2152. qdf_nbuf_free(nbuf);
  2153. return NULL;
  2154. }
  2155. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2156. seg_info->frags[0].paddr_lo = paddr;
  2157. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2158. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2159. seg_info->frags[0].vaddr = (void *) nbuf;
  2160. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2161. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2162. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2163. dp_tx_err("frag dma map error");
  2164. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2165. goto map_err;
  2166. }
  2167. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2168. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2169. seg_info->frags[cur_frag + 1].paddr_hi =
  2170. ((uint64_t) paddr) >> 32;
  2171. seg_info->frags[cur_frag + 1].len =
  2172. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2173. }
  2174. seg_info->frag_cnt = (cur_frag + 1);
  2175. seg_info->total_len = qdf_nbuf_len(nbuf);
  2176. seg_info->next = NULL;
  2177. sg_info->curr_seg = seg_info;
  2178. msdu_info->frm_type = dp_tx_frm_sg;
  2179. msdu_info->num_seg = 1;
  2180. return nbuf;
  2181. map_err:
  2182. /* restore paddr into nbuf before calling unmap */
  2183. qdf_nbuf_mapped_paddr_set(nbuf,
  2184. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2185. ((uint64_t)
  2186. seg_info->frags[0].paddr_hi) << 32));
  2187. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2188. QDF_DMA_TO_DEVICE,
  2189. seg_info->frags[0].len);
  2190. for (i = 1; i <= cur_frag; i++) {
  2191. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2192. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2193. seg_info->frags[i].paddr_hi) << 32),
  2194. seg_info->frags[i].len,
  2195. QDF_DMA_TO_DEVICE);
  2196. }
  2197. qdf_nbuf_free(nbuf);
  2198. return NULL;
  2199. }
  2200. /**
  2201. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2202. * @vdev: DP vdev handle
  2203. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2204. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2205. *
  2206. * Return: NULL on failure,
  2207. * nbuf when extracted successfully
  2208. */
  2209. static
  2210. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2211. struct dp_tx_msdu_info_s *msdu_info,
  2212. uint16_t ppdu_cookie)
  2213. {
  2214. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2215. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2216. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2217. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2218. (msdu_info->meta_data[5], 1);
  2219. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2220. (msdu_info->meta_data[5], 1);
  2221. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2222. (msdu_info->meta_data[6], ppdu_cookie);
  2223. msdu_info->exception_fw = 1;
  2224. msdu_info->is_tx_sniffer = 1;
  2225. }
  2226. #ifdef MESH_MODE_SUPPORT
  2227. /**
  2228. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2229. and prepare msdu_info for mesh frames.
  2230. * @vdev: DP vdev handle
  2231. * @nbuf: skb
  2232. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2233. *
  2234. * Return: NULL on failure,
  2235. * nbuf when extracted successfully
  2236. */
  2237. static
  2238. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2239. struct dp_tx_msdu_info_s *msdu_info)
  2240. {
  2241. struct meta_hdr_s *mhdr;
  2242. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2243. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2244. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2245. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2246. msdu_info->exception_fw = 0;
  2247. goto remove_meta_hdr;
  2248. }
  2249. msdu_info->exception_fw = 1;
  2250. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2251. meta_data->host_tx_desc_pool = 1;
  2252. meta_data->update_peer_cache = 1;
  2253. meta_data->learning_frame = 1;
  2254. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2255. meta_data->power = mhdr->power;
  2256. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2257. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2258. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2259. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2260. meta_data->dyn_bw = 1;
  2261. meta_data->valid_pwr = 1;
  2262. meta_data->valid_mcs_mask = 1;
  2263. meta_data->valid_nss_mask = 1;
  2264. meta_data->valid_preamble_type = 1;
  2265. meta_data->valid_retries = 1;
  2266. meta_data->valid_bw_info = 1;
  2267. }
  2268. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2269. meta_data->encrypt_type = 0;
  2270. meta_data->valid_encrypt_type = 1;
  2271. meta_data->learning_frame = 0;
  2272. }
  2273. meta_data->valid_key_flags = 1;
  2274. meta_data->key_flags = (mhdr->keyix & 0x3);
  2275. remove_meta_hdr:
  2276. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2277. dp_tx_err("qdf_nbuf_pull_head failed");
  2278. qdf_nbuf_free(nbuf);
  2279. return NULL;
  2280. }
  2281. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2282. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2283. " tid %d to_fw %d",
  2284. msdu_info->meta_data[0],
  2285. msdu_info->meta_data[1],
  2286. msdu_info->meta_data[2],
  2287. msdu_info->meta_data[3],
  2288. msdu_info->meta_data[4],
  2289. msdu_info->meta_data[5],
  2290. msdu_info->tid, msdu_info->exception_fw);
  2291. return nbuf;
  2292. }
  2293. #else
  2294. static
  2295. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2296. struct dp_tx_msdu_info_s *msdu_info)
  2297. {
  2298. return nbuf;
  2299. }
  2300. #endif
  2301. /**
  2302. * dp_check_exc_metadata() - Checks if parameters are valid
  2303. * @tx_exc - holds all exception path parameters
  2304. *
  2305. * Returns true when all the parameters are valid else false
  2306. *
  2307. */
  2308. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2309. {
  2310. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2311. HTT_INVALID_TID);
  2312. bool invalid_encap_type =
  2313. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2314. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2315. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2316. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2317. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2318. tx_exc->ppdu_cookie == 0);
  2319. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2320. invalid_cookie) {
  2321. return false;
  2322. }
  2323. return true;
  2324. }
  2325. #ifdef ATH_SUPPORT_IQUE
  2326. /**
  2327. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2328. * @vdev: vdev handle
  2329. * @nbuf: skb
  2330. *
  2331. * Return: true on success,
  2332. * false on failure
  2333. */
  2334. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2335. {
  2336. qdf_ether_header_t *eh;
  2337. /* Mcast to Ucast Conversion*/
  2338. if (qdf_likely(!vdev->mcast_enhancement_en))
  2339. return true;
  2340. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2341. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2342. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2343. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2344. qdf_nbuf_set_next(nbuf, NULL);
  2345. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2346. qdf_nbuf_len(nbuf));
  2347. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2348. QDF_STATUS_SUCCESS) {
  2349. return false;
  2350. }
  2351. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2352. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2353. QDF_STATUS_SUCCESS) {
  2354. return false;
  2355. }
  2356. }
  2357. }
  2358. return true;
  2359. }
  2360. #else
  2361. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2362. {
  2363. return true;
  2364. }
  2365. #endif
  2366. /**
  2367. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2368. * @nbuf: qdf_nbuf_t
  2369. * @vdev: struct dp_vdev *
  2370. *
  2371. * Allow packet for processing only if it is for peer client which is
  2372. * connected with same vap. Drop packet if client is connected to
  2373. * different vap.
  2374. *
  2375. * Return: QDF_STATUS
  2376. */
  2377. static inline QDF_STATUS
  2378. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2379. {
  2380. struct dp_ast_entry *dst_ast_entry = NULL;
  2381. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2382. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2383. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2384. return QDF_STATUS_SUCCESS;
  2385. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2386. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2387. eh->ether_dhost,
  2388. vdev->vdev_id);
  2389. /* If there is no ast entry, return failure */
  2390. if (qdf_unlikely(!dst_ast_entry)) {
  2391. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2392. return QDF_STATUS_E_FAILURE;
  2393. }
  2394. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2395. return QDF_STATUS_SUCCESS;
  2396. }
  2397. /**
  2398. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2399. * @soc: DP soc handle
  2400. * @vdev_id: id of DP vdev handle
  2401. * @nbuf: skb
  2402. * @tx_exc_metadata: Handle that holds exception path meta data
  2403. *
  2404. * Entry point for Core Tx layer (DP_TX) invoked from
  2405. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2406. *
  2407. * Return: NULL on success,
  2408. * nbuf when it fails to send
  2409. */
  2410. qdf_nbuf_t
  2411. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2412. qdf_nbuf_t nbuf,
  2413. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2414. {
  2415. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2416. qdf_ether_header_t *eh = NULL;
  2417. struct dp_tx_msdu_info_s msdu_info;
  2418. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2419. DP_MOD_ID_TX_EXCEPTION);
  2420. if (qdf_unlikely(!vdev))
  2421. goto fail;
  2422. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2423. if (!tx_exc_metadata)
  2424. goto fail;
  2425. msdu_info.tid = tx_exc_metadata->tid;
  2426. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2427. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2428. QDF_MAC_ADDR_REF(nbuf->data));
  2429. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2430. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2431. dp_tx_err("Invalid parameters in exception path");
  2432. goto fail;
  2433. }
  2434. /* Basic sanity checks for unsupported packets */
  2435. /* MESH mode */
  2436. if (qdf_unlikely(vdev->mesh_vdev)) {
  2437. dp_tx_err("Mesh mode is not supported in exception path");
  2438. goto fail;
  2439. }
  2440. /*
  2441. * Classify the frame and call corresponding
  2442. * "prepare" function which extracts the segment (TSO)
  2443. * and fragmentation information (for TSO , SG, ME, or Raw)
  2444. * into MSDU_INFO structure which is later used to fill
  2445. * SW and HW descriptors.
  2446. */
  2447. if (qdf_nbuf_is_tso(nbuf)) {
  2448. dp_verbose_debug("TSO frame %pK", vdev);
  2449. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2450. qdf_nbuf_len(nbuf));
  2451. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2452. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2453. qdf_nbuf_len(nbuf));
  2454. goto fail;
  2455. }
  2456. goto send_multiple;
  2457. }
  2458. /* SG */
  2459. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2460. struct dp_tx_seg_info_s seg_info = {0};
  2461. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2462. if (!nbuf)
  2463. goto fail;
  2464. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2465. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2466. qdf_nbuf_len(nbuf));
  2467. goto send_multiple;
  2468. }
  2469. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2470. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2471. qdf_nbuf_len(nbuf));
  2472. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2473. tx_exc_metadata->ppdu_cookie);
  2474. }
  2475. /*
  2476. * Get HW Queue to use for this frame.
  2477. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2478. * dedicated for data and 1 for command.
  2479. * "queue_id" maps to one hardware ring.
  2480. * With each ring, we also associate a unique Tx descriptor pool
  2481. * to minimize lock contention for these resources.
  2482. */
  2483. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2484. /*
  2485. * Check exception descriptors
  2486. */
  2487. if (dp_tx_exception_limit_check(vdev))
  2488. goto fail;
  2489. /* Single linear frame */
  2490. /*
  2491. * If nbuf is a simple linear frame, use send_single function to
  2492. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2493. * SRNG. There is no need to setup a MSDU extension descriptor.
  2494. */
  2495. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2496. tx_exc_metadata->peer_id, tx_exc_metadata);
  2497. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2498. return nbuf;
  2499. send_multiple:
  2500. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2501. fail:
  2502. if (vdev)
  2503. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2504. dp_verbose_debug("pkt send failed");
  2505. return nbuf;
  2506. }
  2507. /**
  2508. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2509. * in exception path in special case to avoid regular exception path chk.
  2510. * @soc: DP soc handle
  2511. * @vdev_id: id of DP vdev handle
  2512. * @nbuf: skb
  2513. * @tx_exc_metadata: Handle that holds exception path meta data
  2514. *
  2515. * Entry point for Core Tx layer (DP_TX) invoked from
  2516. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2517. *
  2518. * Return: NULL on success,
  2519. * nbuf when it fails to send
  2520. */
  2521. qdf_nbuf_t
  2522. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2523. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2524. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2525. {
  2526. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2527. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2528. DP_MOD_ID_TX_EXCEPTION);
  2529. if (qdf_unlikely(!vdev))
  2530. goto fail;
  2531. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2532. == QDF_STATUS_E_FAILURE)) {
  2533. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2534. goto fail;
  2535. }
  2536. /* Unref count as it will agin be taken inside dp_tx_exception */
  2537. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2538. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2539. fail:
  2540. if (vdev)
  2541. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2542. dp_verbose_debug("pkt send failed");
  2543. return nbuf;
  2544. }
  2545. /**
  2546. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2547. * @soc: DP soc handle
  2548. * @vdev_id: DP vdev handle
  2549. * @nbuf: skb
  2550. *
  2551. * Entry point for Core Tx layer (DP_TX) invoked from
  2552. * hard_start_xmit in OSIF/HDD
  2553. *
  2554. * Return: NULL on success,
  2555. * nbuf when it fails to send
  2556. */
  2557. #ifdef MESH_MODE_SUPPORT
  2558. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2559. qdf_nbuf_t nbuf)
  2560. {
  2561. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2562. struct meta_hdr_s *mhdr;
  2563. qdf_nbuf_t nbuf_mesh = NULL;
  2564. qdf_nbuf_t nbuf_clone = NULL;
  2565. struct dp_vdev *vdev;
  2566. uint8_t no_enc_frame = 0;
  2567. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2568. if (!nbuf_mesh) {
  2569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2570. "qdf_nbuf_unshare failed");
  2571. return nbuf;
  2572. }
  2573. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2574. if (!vdev) {
  2575. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2576. "vdev is NULL for vdev_id %d", vdev_id);
  2577. return nbuf;
  2578. }
  2579. nbuf = nbuf_mesh;
  2580. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2581. if ((vdev->sec_type != cdp_sec_type_none) &&
  2582. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2583. no_enc_frame = 1;
  2584. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2585. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2586. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2587. !no_enc_frame) {
  2588. nbuf_clone = qdf_nbuf_clone(nbuf);
  2589. if (!nbuf_clone) {
  2590. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2591. "qdf_nbuf_clone failed");
  2592. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2593. return nbuf;
  2594. }
  2595. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2596. }
  2597. if (nbuf_clone) {
  2598. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2599. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2600. } else {
  2601. qdf_nbuf_free(nbuf_clone);
  2602. }
  2603. }
  2604. if (no_enc_frame)
  2605. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2606. else
  2607. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2608. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2609. if ((!nbuf) && no_enc_frame) {
  2610. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2611. }
  2612. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2613. return nbuf;
  2614. }
  2615. #else
  2616. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2617. qdf_nbuf_t nbuf)
  2618. {
  2619. return dp_tx_send(soc, vdev_id, nbuf);
  2620. }
  2621. #endif
  2622. /**
  2623. * dp_tx_nawds_handler() - NAWDS handler
  2624. *
  2625. * @soc: DP soc handle
  2626. * @vdev_id: id of DP vdev handle
  2627. * @msdu_info: msdu_info required to create HTT metadata
  2628. * @nbuf: skb
  2629. *
  2630. * This API transfers the multicast frames with the peer id
  2631. * on NAWDS enabled peer.
  2632. * Return: none
  2633. */
  2634. static inline
  2635. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2636. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2637. {
  2638. struct dp_peer *peer = NULL;
  2639. qdf_nbuf_t nbuf_clone = NULL;
  2640. uint16_t peer_id = DP_INVALID_PEER;
  2641. uint16_t sa_peer_id = DP_INVALID_PEER;
  2642. struct dp_ast_entry *ast_entry = NULL;
  2643. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2644. if (!soc->ast_offload_support) {
  2645. qdf_spin_lock_bh(&soc->ast_lock);
  2646. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2647. (soc,
  2648. (uint8_t *)(eh->ether_shost),
  2649. vdev->pdev->pdev_id);
  2650. if (ast_entry)
  2651. sa_peer_id = ast_entry->peer_id;
  2652. qdf_spin_unlock_bh(&soc->ast_lock);
  2653. }
  2654. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2655. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2656. if (!peer->bss_peer && peer->nawds_enabled) {
  2657. peer_id = peer->peer_id;
  2658. /* Multicast packets needs to be
  2659. * dropped in case of intra bss forwarding
  2660. */
  2661. if (!soc->ast_offload_support) {
  2662. if (sa_peer_id == peer->peer_id) {
  2663. dp_tx_debug("multicast packet");
  2664. DP_STATS_INC(peer, tx.nawds_mcast_drop,
  2665. 1);
  2666. continue;
  2667. }
  2668. }
  2669. nbuf_clone = qdf_nbuf_clone(nbuf);
  2670. if (!nbuf_clone) {
  2671. QDF_TRACE(QDF_MODULE_ID_DP,
  2672. QDF_TRACE_LEVEL_ERROR,
  2673. FL("nbuf clone failed"));
  2674. break;
  2675. }
  2676. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2677. msdu_info, peer_id,
  2678. NULL);
  2679. if (nbuf_clone) {
  2680. dp_tx_debug("pkt send failed");
  2681. qdf_nbuf_free(nbuf_clone);
  2682. } else {
  2683. if (peer_id != DP_INVALID_PEER)
  2684. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2685. 1, qdf_nbuf_len(nbuf));
  2686. }
  2687. }
  2688. }
  2689. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2690. }
  2691. /**
  2692. * dp_tx_send() - Transmit a frame on a given VAP
  2693. * @soc: DP soc handle
  2694. * @vdev_id: id of DP vdev handle
  2695. * @nbuf: skb
  2696. *
  2697. * Entry point for Core Tx layer (DP_TX) invoked from
  2698. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2699. * cases
  2700. *
  2701. * Return: NULL on success,
  2702. * nbuf when it fails to send
  2703. */
  2704. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2705. qdf_nbuf_t nbuf)
  2706. {
  2707. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2708. uint16_t peer_id = HTT_INVALID_PEER;
  2709. /*
  2710. * doing a memzero is causing additional function call overhead
  2711. * so doing static stack clearing
  2712. */
  2713. struct dp_tx_msdu_info_s msdu_info = {0};
  2714. struct dp_vdev *vdev = NULL;
  2715. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2716. return nbuf;
  2717. /*
  2718. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2719. * this in per packet path.
  2720. *
  2721. * As in this path vdev memory is already protected with netdev
  2722. * tx lock
  2723. */
  2724. vdev = soc->vdev_id_map[vdev_id];
  2725. if (qdf_unlikely(!vdev))
  2726. return nbuf;
  2727. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2728. QDF_MAC_ADDR_REF(nbuf->data));
  2729. /*
  2730. * Set Default Host TID value to invalid TID
  2731. * (TID override disabled)
  2732. */
  2733. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2734. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2735. if (qdf_unlikely(vdev->mesh_vdev)) {
  2736. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2737. &msdu_info);
  2738. if (!nbuf_mesh) {
  2739. dp_verbose_debug("Extracting mesh metadata failed");
  2740. return nbuf;
  2741. }
  2742. nbuf = nbuf_mesh;
  2743. }
  2744. /*
  2745. * Get HW Queue to use for this frame.
  2746. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2747. * dedicated for data and 1 for command.
  2748. * "queue_id" maps to one hardware ring.
  2749. * With each ring, we also associate a unique Tx descriptor pool
  2750. * to minimize lock contention for these resources.
  2751. */
  2752. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2753. /*
  2754. * TCL H/W supports 2 DSCP-TID mapping tables.
  2755. * Table 1 - Default DSCP-TID mapping table
  2756. * Table 2 - 1 DSCP-TID override table
  2757. *
  2758. * If we need a different DSCP-TID mapping for this vap,
  2759. * call tid_classify to extract DSCP/ToS from frame and
  2760. * map to a TID and store in msdu_info. This is later used
  2761. * to fill in TCL Input descriptor (per-packet TID override).
  2762. */
  2763. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2764. /*
  2765. * Classify the frame and call corresponding
  2766. * "prepare" function which extracts the segment (TSO)
  2767. * and fragmentation information (for TSO , SG, ME, or Raw)
  2768. * into MSDU_INFO structure which is later used to fill
  2769. * SW and HW descriptors.
  2770. */
  2771. if (qdf_nbuf_is_tso(nbuf)) {
  2772. dp_verbose_debug("TSO frame %pK", vdev);
  2773. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2774. qdf_nbuf_len(nbuf));
  2775. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2776. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2777. qdf_nbuf_len(nbuf));
  2778. return nbuf;
  2779. }
  2780. goto send_multiple;
  2781. }
  2782. /* SG */
  2783. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2784. struct dp_tx_seg_info_s seg_info = {0};
  2785. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2786. if (!nbuf)
  2787. return NULL;
  2788. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2789. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2790. qdf_nbuf_len(nbuf));
  2791. goto send_multiple;
  2792. }
  2793. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2794. return NULL;
  2795. /* RAW */
  2796. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2797. struct dp_tx_seg_info_s seg_info = {0};
  2798. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2799. if (!nbuf)
  2800. return NULL;
  2801. dp_verbose_debug("Raw frame %pK", vdev);
  2802. goto send_multiple;
  2803. }
  2804. if (qdf_unlikely(vdev->nawds_enabled)) {
  2805. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2806. qdf_nbuf_data(nbuf);
  2807. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2808. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2809. peer_id = DP_INVALID_PEER;
  2810. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2811. 1, qdf_nbuf_len(nbuf));
  2812. }
  2813. /* Single linear frame */
  2814. /*
  2815. * If nbuf is a simple linear frame, use send_single function to
  2816. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2817. * SRNG. There is no need to setup a MSDU extension descriptor.
  2818. */
  2819. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2820. return nbuf;
  2821. send_multiple:
  2822. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2823. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2824. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2825. return nbuf;
  2826. }
  2827. /**
  2828. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2829. * case to vaoid check in perpkt path.
  2830. * @soc: DP soc handle
  2831. * @vdev_id: id of DP vdev handle
  2832. * @nbuf: skb
  2833. *
  2834. * Entry point for Core Tx layer (DP_TX) invoked from
  2835. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2836. * with special condition to avoid per pkt check in dp_tx_send
  2837. *
  2838. * Return: NULL on success,
  2839. * nbuf when it fails to send
  2840. */
  2841. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2842. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2843. {
  2844. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2845. struct dp_vdev *vdev = NULL;
  2846. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2847. return nbuf;
  2848. /*
  2849. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2850. * this in per packet path.
  2851. *
  2852. * As in this path vdev memory is already protected with netdev
  2853. * tx lock
  2854. */
  2855. vdev = soc->vdev_id_map[vdev_id];
  2856. if (qdf_unlikely(!vdev))
  2857. return nbuf;
  2858. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2859. == QDF_STATUS_E_FAILURE)) {
  2860. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2861. return nbuf;
  2862. }
  2863. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2864. }
  2865. #ifdef UMAC_SUPPORT_PROXY_ARP
  2866. /**
  2867. * dp_tx_proxy_arp() - Tx proxy arp handler
  2868. * @vdev: datapath vdev handle
  2869. * @buf: sk buffer
  2870. *
  2871. * Return: status
  2872. */
  2873. static inline
  2874. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2875. {
  2876. if (vdev->osif_proxy_arp)
  2877. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  2878. /*
  2879. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  2880. * osif_proxy_arp has a valid function pointer assigned
  2881. * to it
  2882. */
  2883. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  2884. return QDF_STATUS_NOT_INITIALIZED;
  2885. }
  2886. #else
  2887. /**
  2888. * dp_tx_proxy_arp() - Tx proxy arp handler
  2889. * @vdev: datapath vdev handle
  2890. * @buf: sk buffer
  2891. *
  2892. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  2893. * is not defined.
  2894. *
  2895. * Return: status
  2896. */
  2897. static inline
  2898. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2899. {
  2900. return QDF_STATUS_SUCCESS;
  2901. }
  2902. #endif
  2903. /**
  2904. * dp_tx_reinject_handler() - Tx Reinject Handler
  2905. * @soc: datapath soc handle
  2906. * @vdev: datapath vdev handle
  2907. * @tx_desc: software descriptor head pointer
  2908. * @status : Tx completion status from HTT descriptor
  2909. *
  2910. * This function reinjects frames back to Target.
  2911. * Todo - Host queue needs to be added
  2912. *
  2913. * Return: none
  2914. */
  2915. static
  2916. void dp_tx_reinject_handler(struct dp_soc *soc,
  2917. struct dp_vdev *vdev,
  2918. struct dp_tx_desc_s *tx_desc,
  2919. uint8_t *status)
  2920. {
  2921. struct dp_peer *peer = NULL;
  2922. uint32_t peer_id = HTT_INVALID_PEER;
  2923. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2924. qdf_nbuf_t nbuf_copy = NULL;
  2925. struct dp_tx_msdu_info_s msdu_info;
  2926. #ifdef WDS_VENDOR_EXTENSION
  2927. int is_mcast = 0, is_ucast = 0;
  2928. int num_peers_3addr = 0;
  2929. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2930. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2931. #endif
  2932. qdf_assert(vdev);
  2933. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2934. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2935. dp_tx_debug("Tx reinject path");
  2936. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2937. qdf_nbuf_len(tx_desc->nbuf));
  2938. #ifdef WDS_VENDOR_EXTENSION
  2939. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2940. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2941. } else {
  2942. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2943. }
  2944. is_ucast = !is_mcast;
  2945. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2946. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2947. if (peer->bss_peer)
  2948. continue;
  2949. /* Detect wds peers that use 3-addr framing for mcast.
  2950. * if there are any, the bss_peer is used to send the
  2951. * the mcast frame using 3-addr format. all wds enabled
  2952. * peers that use 4-addr framing for mcast frames will
  2953. * be duplicated and sent as 4-addr frames below.
  2954. */
  2955. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2956. num_peers_3addr = 1;
  2957. break;
  2958. }
  2959. }
  2960. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2961. #endif
  2962. if (qdf_unlikely(vdev->mesh_vdev)) {
  2963. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2964. } else {
  2965. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2966. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2967. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2968. #ifdef WDS_VENDOR_EXTENSION
  2969. /*
  2970. * . if 3-addr STA, then send on BSS Peer
  2971. * . if Peer WDS enabled and accept 4-addr mcast,
  2972. * send mcast on that peer only
  2973. * . if Peer WDS enabled and accept 4-addr ucast,
  2974. * send ucast on that peer only
  2975. */
  2976. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2977. (peer->wds_enabled &&
  2978. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2979. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2980. #else
  2981. (peer->bss_peer &&
  2982. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  2983. #endif
  2984. peer_id = DP_INVALID_PEER;
  2985. nbuf_copy = qdf_nbuf_copy(nbuf);
  2986. if (!nbuf_copy) {
  2987. dp_tx_debug("nbuf copy failed");
  2988. break;
  2989. }
  2990. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2991. nbuf_copy,
  2992. &msdu_info,
  2993. peer_id,
  2994. NULL);
  2995. if (nbuf_copy) {
  2996. dp_tx_debug("pkt send failed");
  2997. qdf_nbuf_free(nbuf_copy);
  2998. }
  2999. }
  3000. }
  3001. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3002. }
  3003. qdf_nbuf_free(nbuf);
  3004. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3005. }
  3006. /**
  3007. * dp_tx_inspect_handler() - Tx Inspect Handler
  3008. * @soc: datapath soc handle
  3009. * @vdev: datapath vdev handle
  3010. * @tx_desc: software descriptor head pointer
  3011. * @status : Tx completion status from HTT descriptor
  3012. *
  3013. * Handles Tx frames sent back to Host for inspection
  3014. * (ProxyARP)
  3015. *
  3016. * Return: none
  3017. */
  3018. static void dp_tx_inspect_handler(struct dp_soc *soc,
  3019. struct dp_vdev *vdev,
  3020. struct dp_tx_desc_s *tx_desc,
  3021. uint8_t *status)
  3022. {
  3023. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3024. "%s Tx inspect path",
  3025. __func__);
  3026. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3027. qdf_nbuf_len(tx_desc->nbuf));
  3028. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3029. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3030. }
  3031. #ifdef MESH_MODE_SUPPORT
  3032. /**
  3033. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3034. * in mesh meta header
  3035. * @tx_desc: software descriptor head pointer
  3036. * @ts: pointer to tx completion stats
  3037. * Return: none
  3038. */
  3039. static
  3040. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3041. struct hal_tx_completion_status *ts)
  3042. {
  3043. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3044. if (!tx_desc->msdu_ext_desc) {
  3045. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3046. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3047. "netbuf %pK offset %d",
  3048. netbuf, tx_desc->pkt_offset);
  3049. return;
  3050. }
  3051. }
  3052. }
  3053. #else
  3054. static
  3055. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3056. struct hal_tx_completion_status *ts)
  3057. {
  3058. }
  3059. #endif
  3060. #ifdef QCA_PEER_EXT_STATS
  3061. /*
  3062. * dp_tx_compute_tid_delay() - Compute per TID delay
  3063. * @stats: Per TID delay stats
  3064. * @tx_desc: Software Tx descriptor
  3065. *
  3066. * Compute the software enqueue and hw enqueue delays and
  3067. * update the respective histograms
  3068. *
  3069. * Return: void
  3070. */
  3071. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3072. struct dp_tx_desc_s *tx_desc)
  3073. {
  3074. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3075. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3076. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3077. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3078. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3079. timestamp_hw_enqueue = tx_desc->timestamp;
  3080. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3081. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3082. timestamp_hw_enqueue);
  3083. /*
  3084. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3085. */
  3086. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3087. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3088. }
  3089. /*
  3090. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3091. * @peer: DP peer context
  3092. * @tx_desc: Tx software descriptor
  3093. * @tid: Transmission ID
  3094. * @ring_id: Rx CPU context ID/CPU_ID
  3095. *
  3096. * Update the peer extended stats. These are enhanced other
  3097. * delay stats per msdu level.
  3098. *
  3099. * Return: void
  3100. */
  3101. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3102. struct dp_tx_desc_s *tx_desc,
  3103. uint8_t tid, uint8_t ring_id)
  3104. {
  3105. struct dp_pdev *pdev = peer->vdev->pdev;
  3106. struct dp_soc *soc = NULL;
  3107. struct cdp_peer_ext_stats *pext_stats = NULL;
  3108. soc = pdev->soc;
  3109. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3110. return;
  3111. pext_stats = peer->pext_stats;
  3112. qdf_assert(pext_stats);
  3113. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3114. /*
  3115. * For non-TID packets use the TID 9
  3116. */
  3117. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3118. tid = CDP_MAX_DATA_TIDS - 1;
  3119. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3120. tx_desc);
  3121. }
  3122. #else
  3123. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3124. struct dp_tx_desc_s *tx_desc,
  3125. uint8_t tid, uint8_t ring_id)
  3126. {
  3127. }
  3128. #endif
  3129. /**
  3130. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3131. * to pass in correct fields
  3132. *
  3133. * @vdev: pdev handle
  3134. * @tx_desc: tx descriptor
  3135. * @tid: tid value
  3136. * @ring_id: TCL or WBM ring number for transmit path
  3137. * Return: none
  3138. */
  3139. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3140. struct dp_tx_desc_s *tx_desc,
  3141. uint8_t tid, uint8_t ring_id)
  3142. {
  3143. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3144. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3145. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3146. return;
  3147. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3148. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3149. timestamp_hw_enqueue = tx_desc->timestamp;
  3150. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3151. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3152. timestamp_hw_enqueue);
  3153. interframe_delay = (uint32_t)(timestamp_ingress -
  3154. vdev->prev_tx_enq_tstamp);
  3155. /*
  3156. * Delay in software enqueue
  3157. */
  3158. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3159. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3160. /*
  3161. * Delay between packet enqueued to HW and Tx completion
  3162. */
  3163. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3164. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3165. /*
  3166. * Update interframe delay stats calculated at hardstart receive point.
  3167. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3168. * interframe delay will not be calculate correctly for 1st frame.
  3169. * On the other side, this will help in avoiding extra per packet check
  3170. * of !vdev->prev_tx_enq_tstamp.
  3171. */
  3172. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3173. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3174. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3175. }
  3176. #ifdef DISABLE_DP_STATS
  3177. static
  3178. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3179. {
  3180. }
  3181. #else
  3182. static
  3183. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3184. {
  3185. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3186. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3187. if (subtype != QDF_PROTO_INVALID)
  3188. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3189. }
  3190. #endif
  3191. /**
  3192. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3193. * per wbm ring
  3194. *
  3195. * @tx_desc: software descriptor head pointer
  3196. * @ts: Tx completion status
  3197. * @peer: peer handle
  3198. * @ring_id: ring number
  3199. *
  3200. * Return: None
  3201. */
  3202. static inline void
  3203. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3204. struct hal_tx_completion_status *ts,
  3205. struct dp_peer *peer, uint8_t ring_id)
  3206. {
  3207. struct dp_pdev *pdev = peer->vdev->pdev;
  3208. struct dp_soc *soc = NULL;
  3209. uint8_t mcs, pkt_type;
  3210. uint8_t tid = ts->tid;
  3211. uint32_t length;
  3212. struct cdp_tid_tx_stats *tid_stats;
  3213. if (!pdev)
  3214. return;
  3215. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3216. tid = CDP_MAX_DATA_TIDS - 1;
  3217. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3218. soc = pdev->soc;
  3219. mcs = ts->mcs;
  3220. pkt_type = ts->pkt_type;
  3221. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3222. dp_err("Release source is not from TQM");
  3223. return;
  3224. }
  3225. length = qdf_nbuf_len(tx_desc->nbuf);
  3226. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3227. if (qdf_unlikely(pdev->delay_stats_flag))
  3228. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3229. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3230. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3231. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3232. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3233. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3234. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3235. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3236. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3237. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3238. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3239. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3240. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3241. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3242. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3243. /*
  3244. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3245. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3246. * are no completions for failed cases. Hence updating tx_failed from
  3247. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3248. * then this has to be removed
  3249. */
  3250. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3251. peer->stats.tx.dropped.fw_rem_notx +
  3252. peer->stats.tx.dropped.fw_rem_tx +
  3253. peer->stats.tx.dropped.age_out +
  3254. peer->stats.tx.dropped.fw_reason1 +
  3255. peer->stats.tx.dropped.fw_reason2 +
  3256. peer->stats.tx.dropped.fw_reason3;
  3257. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3258. tid_stats->tqm_status_cnt[ts->status]++;
  3259. }
  3260. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3261. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3262. return;
  3263. }
  3264. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3265. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3266. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3267. /*
  3268. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3269. * Return from here if HTT PPDU events are enabled.
  3270. */
  3271. if (!(soc->process_tx_status))
  3272. return;
  3273. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3274. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3275. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3276. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3277. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3278. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3279. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3280. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3281. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3282. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3283. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3284. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3285. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3286. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3287. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3288. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3289. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3290. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3291. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3292. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3293. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3294. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3295. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3296. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3297. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3298. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3299. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3300. if (ts->first_msdu)
  3301. DP_STATS_INCC(peer, tx.mpdu_success_with_retries,
  3302. qdf_do_div(ts->transmit_cnt, DP_RETRY_COUNT),
  3303. ts->transmit_cnt > DP_RETRY_COUNT);
  3304. peer->stats.tx.last_tx_ts = qdf_system_ticks();
  3305. }
  3306. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3307. /**
  3308. * dp_tx_flow_pool_lock() - take flow pool lock
  3309. * @soc: core txrx main context
  3310. * @tx_desc: tx desc
  3311. *
  3312. * Return: None
  3313. */
  3314. static inline
  3315. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3316. struct dp_tx_desc_s *tx_desc)
  3317. {
  3318. struct dp_tx_desc_pool_s *pool;
  3319. uint8_t desc_pool_id;
  3320. desc_pool_id = tx_desc->pool_id;
  3321. pool = &soc->tx_desc[desc_pool_id];
  3322. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3323. }
  3324. /**
  3325. * dp_tx_flow_pool_unlock() - release flow pool lock
  3326. * @soc: core txrx main context
  3327. * @tx_desc: tx desc
  3328. *
  3329. * Return: None
  3330. */
  3331. static inline
  3332. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3333. struct dp_tx_desc_s *tx_desc)
  3334. {
  3335. struct dp_tx_desc_pool_s *pool;
  3336. uint8_t desc_pool_id;
  3337. desc_pool_id = tx_desc->pool_id;
  3338. pool = &soc->tx_desc[desc_pool_id];
  3339. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3340. }
  3341. #else
  3342. static inline
  3343. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3344. {
  3345. }
  3346. static inline
  3347. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3348. {
  3349. }
  3350. #endif
  3351. /**
  3352. * dp_tx_notify_completion() - Notify tx completion for this desc
  3353. * @soc: core txrx main context
  3354. * @vdev: datapath vdev handle
  3355. * @tx_desc: tx desc
  3356. * @netbuf: buffer
  3357. * @status: tx status
  3358. *
  3359. * Return: none
  3360. */
  3361. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3362. struct dp_vdev *vdev,
  3363. struct dp_tx_desc_s *tx_desc,
  3364. qdf_nbuf_t netbuf,
  3365. uint8_t status)
  3366. {
  3367. void *osif_dev;
  3368. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3369. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3370. qdf_assert(tx_desc);
  3371. dp_tx_flow_pool_lock(soc, tx_desc);
  3372. if (!vdev ||
  3373. !vdev->osif_vdev) {
  3374. dp_tx_flow_pool_unlock(soc, tx_desc);
  3375. return;
  3376. }
  3377. osif_dev = vdev->osif_vdev;
  3378. tx_compl_cbk = vdev->tx_comp;
  3379. dp_tx_flow_pool_unlock(soc, tx_desc);
  3380. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3381. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3382. if (tx_compl_cbk)
  3383. tx_compl_cbk(netbuf, osif_dev, flag);
  3384. }
  3385. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3386. * @pdev: pdev handle
  3387. * @tid: tid value
  3388. * @txdesc_ts: timestamp from txdesc
  3389. * @ppdu_id: ppdu id
  3390. *
  3391. * Return: none
  3392. */
  3393. #ifdef FEATURE_PERPKT_INFO
  3394. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3395. struct dp_peer *peer,
  3396. uint8_t tid,
  3397. uint64_t txdesc_ts,
  3398. uint32_t ppdu_id)
  3399. {
  3400. uint64_t delta_ms;
  3401. struct cdp_tx_sojourn_stats *sojourn_stats;
  3402. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3403. return;
  3404. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3405. tid >= CDP_DATA_TID_MAX))
  3406. return;
  3407. if (qdf_unlikely(!pdev->sojourn_buf))
  3408. return;
  3409. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3410. qdf_nbuf_data(pdev->sojourn_buf);
  3411. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3412. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3413. txdesc_ts;
  3414. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3415. delta_ms);
  3416. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3417. sojourn_stats->num_msdus[tid] = 1;
  3418. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3419. peer->avg_sojourn_msdu[tid].internal;
  3420. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3421. pdev->sojourn_buf, HTT_INVALID_PEER,
  3422. WDI_NO_VAL, pdev->pdev_id);
  3423. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3424. sojourn_stats->num_msdus[tid] = 0;
  3425. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3426. }
  3427. #else
  3428. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3429. struct dp_peer *peer,
  3430. uint8_t tid,
  3431. uint64_t txdesc_ts,
  3432. uint32_t ppdu_id)
  3433. {
  3434. }
  3435. #endif
  3436. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3437. /**
  3438. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3439. * @soc: dp_soc handle
  3440. * @desc: Tx Descriptor
  3441. * @ts: HAL Tx completion descriptor contents
  3442. *
  3443. * This function is used to send tx completion to packet capture
  3444. */
  3445. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3446. struct dp_tx_desc_s *desc,
  3447. struct hal_tx_completion_status *ts)
  3448. {
  3449. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3450. desc, ts->peer_id,
  3451. WDI_NO_VAL, desc->pdev->pdev_id);
  3452. }
  3453. #endif
  3454. /**
  3455. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3456. * @soc: DP Soc handle
  3457. * @tx_desc: software Tx descriptor
  3458. * @ts : Tx completion status from HAL/HTT descriptor
  3459. *
  3460. * Return: none
  3461. */
  3462. static inline void
  3463. dp_tx_comp_process_desc(struct dp_soc *soc,
  3464. struct dp_tx_desc_s *desc,
  3465. struct hal_tx_completion_status *ts,
  3466. struct dp_peer *peer)
  3467. {
  3468. uint64_t time_latency = 0;
  3469. /*
  3470. * m_copy/tx_capture modes are not supported for
  3471. * scatter gather packets
  3472. */
  3473. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3474. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3475. desc->timestamp);
  3476. }
  3477. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3478. if (!(desc->msdu_ext_desc)) {
  3479. dp_tx_enh_unmap(soc, desc);
  3480. if (QDF_STATUS_SUCCESS ==
  3481. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3482. return;
  3483. }
  3484. if (QDF_STATUS_SUCCESS ==
  3485. dp_get_completion_indication_for_stack(soc,
  3486. desc->pdev,
  3487. peer, ts,
  3488. desc->nbuf,
  3489. time_latency)) {
  3490. dp_send_completion_to_stack(soc,
  3491. desc->pdev,
  3492. ts->peer_id,
  3493. ts->ppdu_id,
  3494. desc->nbuf);
  3495. return;
  3496. }
  3497. }
  3498. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3499. dp_tx_comp_free_buf(soc, desc);
  3500. }
  3501. #ifdef DISABLE_DP_STATS
  3502. /**
  3503. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3504. * @soc: core txrx main context
  3505. * @tx_desc: tx desc
  3506. * @status: tx status
  3507. *
  3508. * Return: none
  3509. */
  3510. static inline
  3511. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3512. struct dp_vdev *vdev,
  3513. struct dp_tx_desc_s *tx_desc,
  3514. uint8_t status)
  3515. {
  3516. }
  3517. #else
  3518. static inline
  3519. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3520. struct dp_vdev *vdev,
  3521. struct dp_tx_desc_s *tx_desc,
  3522. uint8_t status)
  3523. {
  3524. void *osif_dev;
  3525. ol_txrx_stats_rx_fp stats_cbk;
  3526. uint8_t pkt_type;
  3527. qdf_assert(tx_desc);
  3528. if (!vdev ||
  3529. !vdev->osif_vdev ||
  3530. !vdev->stats_cb)
  3531. return;
  3532. osif_dev = vdev->osif_vdev;
  3533. stats_cbk = vdev->stats_cb;
  3534. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3535. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3536. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3537. &pkt_type);
  3538. }
  3539. #endif
  3540. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3541. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3542. uint32_t delta_tsf)
  3543. {
  3544. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3545. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3546. DP_MOD_ID_CDP);
  3547. if (!vdev) {
  3548. dp_err_rl("vdev %d does not exist", vdev_id);
  3549. return;
  3550. }
  3551. vdev->delta_tsf = delta_tsf;
  3552. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3553. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3554. }
  3555. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3556. uint8_t vdev_id, bool enable)
  3557. {
  3558. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3559. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3560. DP_MOD_ID_CDP);
  3561. if (!vdev) {
  3562. dp_err_rl("vdev %d does not exist", vdev_id);
  3563. return QDF_STATUS_E_FAILURE;
  3564. }
  3565. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3566. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3567. return QDF_STATUS_SUCCESS;
  3568. }
  3569. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3570. uint32_t *val)
  3571. {
  3572. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3573. struct dp_vdev *vdev;
  3574. uint32_t delay_accum;
  3575. uint32_t pkts_accum;
  3576. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3577. if (!vdev) {
  3578. dp_err_rl("vdev %d does not exist", vdev_id);
  3579. return QDF_STATUS_E_FAILURE;
  3580. }
  3581. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3582. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3583. return QDF_STATUS_E_FAILURE;
  3584. }
  3585. /* Average uplink delay based on current accumulated values */
  3586. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3587. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3588. *val = delay_accum / pkts_accum;
  3589. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3590. delay_accum, pkts_accum);
  3591. /* Reset accumulated values to 0 */
  3592. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3593. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3594. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3595. return QDF_STATUS_SUCCESS;
  3596. }
  3597. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3598. struct hal_tx_completion_status *ts)
  3599. {
  3600. uint32_t buffer_ts;
  3601. uint32_t delta_tsf;
  3602. uint32_t ul_delay;
  3603. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3604. if (!ts->valid)
  3605. return;
  3606. if (qdf_unlikely(!vdev)) {
  3607. dp_info_rl("vdev is null or delete in progrss");
  3608. return;
  3609. }
  3610. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3611. return;
  3612. delta_tsf = vdev->delta_tsf;
  3613. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3614. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3615. * valid up to 29 bits.
  3616. */
  3617. buffer_ts = ts->buffer_timestamp << 10;
  3618. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3619. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3620. if (ul_delay > 0x1000000) {
  3621. dp_info_rl("----------------------\n"
  3622. "Tx completion status:\n"
  3623. "----------------------\n"
  3624. "release_src = %d\n"
  3625. "ppdu_id = 0x%x\n"
  3626. "release_reason = %d\n"
  3627. "tsf = %u (0x%x)\n"
  3628. "buffer_timestamp = %u (0x%x)\n"
  3629. "delta_tsf = %u (0x%x)\n",
  3630. ts->release_src, ts->ppdu_id, ts->status,
  3631. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3632. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3633. return;
  3634. }
  3635. ul_delay /= 1000; /* in unit of ms */
  3636. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3637. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3638. }
  3639. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3640. static inline
  3641. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3642. struct hal_tx_completion_status *ts)
  3643. {
  3644. }
  3645. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3646. /**
  3647. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3648. * @soc: DP soc handle
  3649. * @tx_desc: software descriptor head pointer
  3650. * @ts: Tx completion status
  3651. * @peer: peer handle
  3652. * @ring_id: ring number
  3653. *
  3654. * Return: none
  3655. */
  3656. static inline
  3657. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3658. struct dp_tx_desc_s *tx_desc,
  3659. struct hal_tx_completion_status *ts,
  3660. struct dp_peer *peer, uint8_t ring_id)
  3661. {
  3662. uint32_t length;
  3663. qdf_ether_header_t *eh;
  3664. struct dp_vdev *vdev = NULL;
  3665. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3666. enum qdf_dp_tx_rx_status dp_status;
  3667. if (!nbuf) {
  3668. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3669. goto out;
  3670. }
  3671. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3672. length = qdf_nbuf_len(nbuf);
  3673. dp_status = dp_tx_hw_to_qdf(ts->status);
  3674. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3675. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3676. QDF_TRACE_DEFAULT_PDEV_ID,
  3677. qdf_nbuf_data_addr(nbuf),
  3678. sizeof(qdf_nbuf_data(nbuf)),
  3679. tx_desc->id, ts->status, dp_status));
  3680. dp_tx_comp_debug("-------------------- \n"
  3681. "Tx Completion Stats: \n"
  3682. "-------------------- \n"
  3683. "ack_frame_rssi = %d \n"
  3684. "first_msdu = %d \n"
  3685. "last_msdu = %d \n"
  3686. "msdu_part_of_amsdu = %d \n"
  3687. "rate_stats valid = %d \n"
  3688. "bw = %d \n"
  3689. "pkt_type = %d \n"
  3690. "stbc = %d \n"
  3691. "ldpc = %d \n"
  3692. "sgi = %d \n"
  3693. "mcs = %d \n"
  3694. "ofdma = %d \n"
  3695. "tones_in_ru = %d \n"
  3696. "tsf = %d \n"
  3697. "ppdu_id = %d \n"
  3698. "transmit_cnt = %d \n"
  3699. "tid = %d \n"
  3700. "peer_id = %d\n",
  3701. ts->ack_frame_rssi, ts->first_msdu,
  3702. ts->last_msdu, ts->msdu_part_of_amsdu,
  3703. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3704. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3705. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3706. ts->transmit_cnt, ts->tid, ts->peer_id);
  3707. /* Update SoC level stats */
  3708. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3709. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3710. if (!peer) {
  3711. dp_info_rl("peer is null or deletion in progress");
  3712. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3713. goto out;
  3714. }
  3715. vdev = peer->vdev;
  3716. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3717. dp_tx_update_uplink_delay(soc, vdev, ts);
  3718. /* Update per-packet stats for mesh mode */
  3719. if (qdf_unlikely(vdev->mesh_vdev) &&
  3720. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3721. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3722. /* Update peer level stats */
  3723. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3724. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3725. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3726. if ((peer->vdev->tx_encap_type ==
  3727. htt_cmn_pkt_type_ethernet) &&
  3728. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3729. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3730. }
  3731. }
  3732. } else {
  3733. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3734. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3735. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3736. if (qdf_unlikely(peer->in_twt)) {
  3737. DP_STATS_INC_PKT(peer,
  3738. tx.tx_success_twt,
  3739. 1, length);
  3740. }
  3741. }
  3742. }
  3743. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3744. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3745. #ifdef QCA_SUPPORT_RDK_STATS
  3746. if (soc->rdkstats_enabled)
  3747. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3748. tx_desc->timestamp,
  3749. ts->ppdu_id);
  3750. #endif
  3751. out:
  3752. return;
  3753. }
  3754. /**
  3755. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3756. * @soc: core txrx main context
  3757. * @comp_head: software descriptor head pointer
  3758. * @ring_id: ring number
  3759. *
  3760. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3761. * and release the software descriptors after processing is complete
  3762. *
  3763. * Return: none
  3764. */
  3765. static void
  3766. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3767. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3768. {
  3769. struct dp_tx_desc_s *desc;
  3770. struct dp_tx_desc_s *next;
  3771. struct hal_tx_completion_status ts;
  3772. struct dp_peer *peer = NULL;
  3773. uint16_t peer_id = DP_INVALID_PEER;
  3774. qdf_nbuf_t netbuf;
  3775. desc = comp_head;
  3776. while (desc) {
  3777. if (peer_id != desc->peer_id) {
  3778. if (peer)
  3779. dp_peer_unref_delete(peer,
  3780. DP_MOD_ID_TX_COMP);
  3781. peer_id = desc->peer_id;
  3782. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3783. DP_MOD_ID_TX_COMP);
  3784. }
  3785. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3786. struct dp_pdev *pdev = desc->pdev;
  3787. if (qdf_likely(peer)) {
  3788. /*
  3789. * Increment peer statistics
  3790. * Minimal statistics update done here
  3791. */
  3792. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3793. desc->length);
  3794. if (desc->tx_status !=
  3795. HAL_TX_TQM_RR_FRAME_ACKED)
  3796. DP_STATS_INC(peer, tx.tx_failed, 1);
  3797. }
  3798. qdf_assert(pdev);
  3799. dp_tx_outstanding_dec(pdev);
  3800. /*
  3801. * Calling a QDF WRAPPER here is creating signifcant
  3802. * performance impact so avoided the wrapper call here
  3803. */
  3804. next = desc->next;
  3805. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  3806. desc->id, DP_TX_COMP_UNMAP);
  3807. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  3808. desc->nbuf,
  3809. desc->dma_addr,
  3810. QDF_DMA_TO_DEVICE,
  3811. desc->length);
  3812. qdf_nbuf_free(desc->nbuf);
  3813. dp_tx_desc_free(soc, desc, desc->pool_id);
  3814. desc = next;
  3815. continue;
  3816. }
  3817. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3818. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3819. netbuf = desc->nbuf;
  3820. /* check tx complete notification */
  3821. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3822. dp_tx_notify_completion(soc, peer->vdev, desc,
  3823. netbuf, ts.status);
  3824. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3825. next = desc->next;
  3826. dp_tx_desc_release(desc, desc->pool_id);
  3827. desc = next;
  3828. }
  3829. if (peer)
  3830. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3831. }
  3832. /**
  3833. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3834. * @soc: Handle to DP soc structure
  3835. * @tx_desc: software descriptor head pointer
  3836. * @status : Tx completion status from HTT descriptor
  3837. * @ring_id: ring number
  3838. *
  3839. * This function will process HTT Tx indication messages from Target
  3840. *
  3841. * Return: none
  3842. */
  3843. static
  3844. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3845. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3846. uint8_t ring_id)
  3847. {
  3848. uint8_t tx_status;
  3849. struct dp_pdev *pdev;
  3850. struct dp_vdev *vdev;
  3851. struct hal_tx_completion_status ts = {0};
  3852. uint32_t *htt_desc = (uint32_t *)status;
  3853. struct dp_peer *peer;
  3854. struct cdp_tid_tx_stats *tid_stats = NULL;
  3855. struct htt_soc *htt_handle;
  3856. uint8_t vdev_id;
  3857. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3858. htt_handle = (struct htt_soc *)soc->htt_handle;
  3859. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3860. /*
  3861. * There can be scenario where WBM consuming descriptor enqueued
  3862. * from TQM2WBM first and TQM completion can happen before MEC
  3863. * notification comes from FW2WBM. Avoid access any field of tx
  3864. * descriptor in case of MEC notify.
  3865. */
  3866. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3867. qdf_assert_always(!soc->mec_fw_offload);
  3868. /*
  3869. * Get vdev id from HTT status word in case of MEC
  3870. * notification
  3871. */
  3872. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3873. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3874. return;
  3875. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3876. DP_MOD_ID_HTT_COMP);
  3877. if (!vdev)
  3878. return;
  3879. dp_tx_mec_handler(vdev, status);
  3880. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3881. return;
  3882. }
  3883. /*
  3884. * If the descriptor is already freed in vdev_detach,
  3885. * continue to next descriptor
  3886. */
  3887. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3888. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d", tx_desc->id);
  3889. return;
  3890. }
  3891. pdev = tx_desc->pdev;
  3892. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3893. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  3894. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3895. dp_tx_comp_free_buf(soc, tx_desc);
  3896. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3897. return;
  3898. }
  3899. qdf_assert(tx_desc->pdev);
  3900. vdev_id = tx_desc->vdev_id;
  3901. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3902. DP_MOD_ID_HTT_COMP);
  3903. if (!vdev)
  3904. return;
  3905. switch (tx_status) {
  3906. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3907. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3908. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3909. {
  3910. uint8_t tid;
  3911. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3912. ts.peer_id =
  3913. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3914. htt_desc[2]);
  3915. ts.tid =
  3916. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3917. htt_desc[2]);
  3918. } else {
  3919. ts.peer_id = HTT_INVALID_PEER;
  3920. ts.tid = HTT_INVALID_TID;
  3921. }
  3922. ts.ppdu_id =
  3923. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3924. htt_desc[1]);
  3925. ts.ack_frame_rssi =
  3926. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3927. htt_desc[1]);
  3928. ts.tsf = htt_desc[3];
  3929. ts.first_msdu = 1;
  3930. ts.last_msdu = 1;
  3931. tid = ts.tid;
  3932. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3933. tid = CDP_MAX_DATA_TIDS - 1;
  3934. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3935. if (qdf_unlikely(pdev->delay_stats_flag))
  3936. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3937. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3938. tid_stats->htt_status_cnt[tx_status]++;
  3939. }
  3940. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3941. DP_MOD_ID_HTT_COMP);
  3942. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3943. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3944. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3945. if (qdf_likely(peer))
  3946. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3947. break;
  3948. }
  3949. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3950. {
  3951. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3952. break;
  3953. }
  3954. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3955. {
  3956. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3957. break;
  3958. }
  3959. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  3960. {
  3961. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3962. goto release_tx_desc;
  3963. }
  3964. default:
  3965. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  3966. tx_status);
  3967. goto release_tx_desc;
  3968. }
  3969. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3970. return;
  3971. release_tx_desc:
  3972. dp_tx_comp_free_buf(soc, tx_desc);
  3973. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3974. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3975. }
  3976. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3977. static inline
  3978. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3979. int max_reap_limit)
  3980. {
  3981. bool limit_hit = false;
  3982. limit_hit =
  3983. (num_reaped >= max_reap_limit) ? true : false;
  3984. if (limit_hit)
  3985. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3986. return limit_hit;
  3987. }
  3988. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3989. {
  3990. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3991. }
  3992. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3993. {
  3994. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3995. return cfg->tx_comp_loop_pkt_limit;
  3996. }
  3997. #else
  3998. static inline
  3999. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4000. int max_reap_limit)
  4001. {
  4002. return false;
  4003. }
  4004. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4005. {
  4006. return false;
  4007. }
  4008. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4009. {
  4010. return 0;
  4011. }
  4012. #endif
  4013. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4014. static inline int
  4015. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4016. int *max_reap_limit)
  4017. {
  4018. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4019. max_reap_limit);
  4020. }
  4021. #else
  4022. static inline int
  4023. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4024. int *max_reap_limit)
  4025. {
  4026. return 0;
  4027. }
  4028. #endif
  4029. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4030. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4031. uint32_t quota)
  4032. {
  4033. void *tx_comp_hal_desc;
  4034. uint8_t buffer_src;
  4035. struct dp_tx_desc_s *tx_desc = NULL;
  4036. struct dp_tx_desc_s *head_desc = NULL;
  4037. struct dp_tx_desc_s *tail_desc = NULL;
  4038. uint32_t num_processed = 0;
  4039. uint32_t count;
  4040. uint32_t num_avail_for_reap = 0;
  4041. bool force_break = false;
  4042. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4043. int max_reap_limit, ring_near_full;
  4044. DP_HIST_INIT();
  4045. more_data:
  4046. /* Re-initialize local variables to be re-used */
  4047. head_desc = NULL;
  4048. tail_desc = NULL;
  4049. count = 0;
  4050. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4051. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4052. &max_reap_limit);
  4053. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4054. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4055. return 0;
  4056. }
  4057. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  4058. if (num_avail_for_reap >= quota)
  4059. num_avail_for_reap = quota;
  4060. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4061. /* Find head descriptor from completion ring */
  4062. while (qdf_likely(num_avail_for_reap--)) {
  4063. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4064. if (qdf_unlikely(!tx_comp_hal_desc))
  4065. break;
  4066. buffer_src = hal_tx_comp_get_buffer_source(soc->hal_soc,
  4067. tx_comp_hal_desc);
  4068. /* If this buffer was not released by TQM or FW, then it is not
  4069. * Tx completion indication, assert */
  4070. if (qdf_unlikely(buffer_src !=
  4071. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4072. (qdf_unlikely(buffer_src !=
  4073. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4074. uint8_t wbm_internal_error;
  4075. dp_err_rl(
  4076. "Tx comp release_src != TQM | FW but from %d",
  4077. buffer_src);
  4078. hal_dump_comp_desc(tx_comp_hal_desc);
  4079. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4080. /* When WBM sees NULL buffer_addr_info in any of
  4081. * ingress rings it sends an error indication,
  4082. * with wbm_internal_error=1, to a specific ring.
  4083. * The WBM2SW ring used to indicate these errors is
  4084. * fixed in HW, and that ring is being used as Tx
  4085. * completion ring. These errors are not related to
  4086. * Tx completions, and should just be ignored
  4087. */
  4088. wbm_internal_error = hal_get_wbm_internal_error(
  4089. soc->hal_soc,
  4090. tx_comp_hal_desc);
  4091. if (wbm_internal_error) {
  4092. dp_err_rl("Tx comp wbm_internal_error!!");
  4093. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4094. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4095. buffer_src)
  4096. dp_handle_wbm_internal_error(
  4097. soc,
  4098. tx_comp_hal_desc,
  4099. hal_tx_comp_get_buffer_type(
  4100. tx_comp_hal_desc));
  4101. } else {
  4102. dp_err_rl("Tx comp wbm_internal_error false");
  4103. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4104. }
  4105. continue;
  4106. }
  4107. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4108. tx_comp_hal_desc,
  4109. &tx_desc);
  4110. if (!tx_desc) {
  4111. dp_err("unable to retrieve tx_desc!");
  4112. QDF_BUG(0);
  4113. continue;
  4114. }
  4115. tx_desc->buffer_src = buffer_src;
  4116. /*
  4117. * If the release source is FW, process the HTT status
  4118. */
  4119. if (qdf_unlikely(buffer_src ==
  4120. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4121. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4122. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4123. htt_tx_status);
  4124. dp_tx_process_htt_completion(soc, tx_desc,
  4125. htt_tx_status, ring_id);
  4126. } else {
  4127. tx_desc->tx_status =
  4128. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4129. tx_desc->buffer_src = buffer_src;
  4130. /*
  4131. * If the fast completion mode is enabled extended
  4132. * metadata from descriptor is not copied
  4133. */
  4134. if (qdf_likely(tx_desc->flags &
  4135. DP_TX_DESC_FLAG_SIMPLE))
  4136. goto add_to_pool;
  4137. /*
  4138. * If the descriptor is already freed in vdev_detach,
  4139. * continue to next descriptor
  4140. */
  4141. if (qdf_unlikely
  4142. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4143. !tx_desc->flags)) {
  4144. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4145. tx_desc->id);
  4146. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4147. continue;
  4148. }
  4149. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4150. dp_tx_comp_info_rl("pdev in down state %d",
  4151. tx_desc->id);
  4152. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4153. dp_tx_comp_free_buf(soc, tx_desc);
  4154. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4155. goto next_desc;
  4156. }
  4157. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4158. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4159. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4160. tx_desc->flags, tx_desc->id);
  4161. qdf_assert_always(0);
  4162. }
  4163. /* Collect hw completion contents */
  4164. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4165. &tx_desc->comp, 1);
  4166. add_to_pool:
  4167. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4168. /* First ring descriptor on the cycle */
  4169. if (!head_desc) {
  4170. head_desc = tx_desc;
  4171. tail_desc = tx_desc;
  4172. }
  4173. tail_desc->next = tx_desc;
  4174. tx_desc->next = NULL;
  4175. tail_desc = tx_desc;
  4176. }
  4177. next_desc:
  4178. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4179. /*
  4180. * Processed packet count is more than given quota
  4181. * stop to processing
  4182. */
  4183. count++;
  4184. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4185. break;
  4186. }
  4187. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4188. /* Process the reaped descriptors */
  4189. if (head_desc)
  4190. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4191. /*
  4192. * If we are processing in near-full condition, there are 3 scenario
  4193. * 1) Ring entries has reached critical state
  4194. * 2) Ring entries are still near high threshold
  4195. * 3) Ring entries are below the safe level
  4196. *
  4197. * One more loop will move te state to normal processing and yield
  4198. */
  4199. if (ring_near_full)
  4200. goto more_data;
  4201. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4202. if (num_processed >= quota)
  4203. force_break = true;
  4204. if (!force_break &&
  4205. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4206. hal_ring_hdl)) {
  4207. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4208. if (!hif_exec_should_yield(soc->hif_handle,
  4209. int_ctx->dp_intr_id))
  4210. goto more_data;
  4211. }
  4212. }
  4213. DP_TX_HIST_STATS_PER_PDEV();
  4214. return num_processed;
  4215. }
  4216. #ifdef FEATURE_WLAN_TDLS
  4217. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4218. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4219. {
  4220. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4221. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4222. DP_MOD_ID_TDLS);
  4223. if (!vdev) {
  4224. dp_err("vdev handle for id %d is NULL", vdev_id);
  4225. return NULL;
  4226. }
  4227. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4228. vdev->is_tdls_frame = true;
  4229. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4230. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4231. }
  4232. #endif
  4233. /**
  4234. * dp_tx_vdev_attach() - attach vdev to dp tx
  4235. * @vdev: virtual device instance
  4236. *
  4237. * Return: QDF_STATUS_SUCCESS: success
  4238. * QDF_STATUS_E_RESOURCES: Error return
  4239. */
  4240. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4241. {
  4242. int pdev_id;
  4243. /*
  4244. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4245. */
  4246. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4247. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4248. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4249. vdev->vdev_id);
  4250. pdev_id =
  4251. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4252. vdev->pdev->pdev_id);
  4253. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4254. /*
  4255. * Set HTT Extension Valid bit to 0 by default
  4256. */
  4257. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4258. dp_tx_vdev_update_search_flags(vdev);
  4259. return QDF_STATUS_SUCCESS;
  4260. }
  4261. #ifndef FEATURE_WDS
  4262. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4263. {
  4264. return false;
  4265. }
  4266. #endif
  4267. /**
  4268. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4269. * @vdev: virtual device instance
  4270. *
  4271. * Return: void
  4272. *
  4273. */
  4274. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4275. {
  4276. struct dp_soc *soc = vdev->pdev->soc;
  4277. /*
  4278. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4279. * for TDLS link
  4280. *
  4281. * Enable AddrY (SA based search) only for non-WDS STA and
  4282. * ProxySTA VAP (in HKv1) modes.
  4283. *
  4284. * In all other VAP modes, only DA based search should be
  4285. * enabled
  4286. */
  4287. if (vdev->opmode == wlan_op_mode_sta &&
  4288. vdev->tdls_link_connected)
  4289. vdev->hal_desc_addr_search_flags =
  4290. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4291. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4292. !dp_tx_da_search_override(vdev))
  4293. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4294. else
  4295. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4296. if (vdev->opmode == wlan_op_mode_sta)
  4297. vdev->search_type = soc->sta_mode_search_policy;
  4298. else
  4299. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4300. }
  4301. static inline bool
  4302. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4303. struct dp_vdev *vdev,
  4304. struct dp_tx_desc_s *tx_desc)
  4305. {
  4306. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4307. return false;
  4308. /*
  4309. * if vdev is given, then only check whether desc
  4310. * vdev match. if vdev is NULL, then check whether
  4311. * desc pdev match.
  4312. */
  4313. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4314. (tx_desc->pdev == pdev);
  4315. }
  4316. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4317. /**
  4318. * dp_tx_desc_flush() - release resources associated
  4319. * to TX Desc
  4320. *
  4321. * @dp_pdev: Handle to DP pdev structure
  4322. * @vdev: virtual device instance
  4323. * NULL: no specific Vdev is required and check all allcated TX desc
  4324. * on this pdev.
  4325. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4326. *
  4327. * @force_free:
  4328. * true: flush the TX desc.
  4329. * false: only reset the Vdev in each allocated TX desc
  4330. * that associated to current Vdev.
  4331. *
  4332. * This function will go through the TX desc pool to flush
  4333. * the outstanding TX data or reset Vdev to NULL in associated TX
  4334. * Desc.
  4335. */
  4336. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4337. bool force_free)
  4338. {
  4339. uint8_t i;
  4340. uint32_t j;
  4341. uint32_t num_desc, page_id, offset;
  4342. uint16_t num_desc_per_page;
  4343. struct dp_soc *soc = pdev->soc;
  4344. struct dp_tx_desc_s *tx_desc = NULL;
  4345. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4346. if (!vdev && !force_free) {
  4347. dp_err("Reset TX desc vdev, Vdev param is required!");
  4348. return;
  4349. }
  4350. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4351. tx_desc_pool = &soc->tx_desc[i];
  4352. if (!(tx_desc_pool->pool_size) ||
  4353. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4354. !(tx_desc_pool->desc_pages.cacheable_pages))
  4355. continue;
  4356. /*
  4357. * Add flow pool lock protection in case pool is freed
  4358. * due to all tx_desc is recycled when handle TX completion.
  4359. * this is not necessary when do force flush as:
  4360. * a. double lock will happen if dp_tx_desc_release is
  4361. * also trying to acquire it.
  4362. * b. dp interrupt has been disabled before do force TX desc
  4363. * flush in dp_pdev_deinit().
  4364. */
  4365. if (!force_free)
  4366. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4367. num_desc = tx_desc_pool->pool_size;
  4368. num_desc_per_page =
  4369. tx_desc_pool->desc_pages.num_element_per_page;
  4370. for (j = 0; j < num_desc; j++) {
  4371. page_id = j / num_desc_per_page;
  4372. offset = j % num_desc_per_page;
  4373. if (qdf_unlikely(!(tx_desc_pool->
  4374. desc_pages.cacheable_pages)))
  4375. break;
  4376. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4377. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4378. /*
  4379. * Free TX desc if force free is
  4380. * required, otherwise only reset vdev
  4381. * in this TX desc.
  4382. */
  4383. if (force_free) {
  4384. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4385. dp_tx_comp_free_buf(soc, tx_desc);
  4386. dp_tx_desc_release(tx_desc, i);
  4387. } else {
  4388. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4389. }
  4390. }
  4391. }
  4392. if (!force_free)
  4393. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4394. }
  4395. }
  4396. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4397. /**
  4398. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4399. *
  4400. * @soc: Handle to DP soc structure
  4401. * @tx_desc: pointer of one TX desc
  4402. * @desc_pool_id: TX Desc pool id
  4403. */
  4404. static inline void
  4405. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4406. uint8_t desc_pool_id)
  4407. {
  4408. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4409. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4410. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4411. }
  4412. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4413. bool force_free)
  4414. {
  4415. uint8_t i, num_pool;
  4416. uint32_t j;
  4417. uint32_t num_desc, page_id, offset;
  4418. uint16_t num_desc_per_page;
  4419. struct dp_soc *soc = pdev->soc;
  4420. struct dp_tx_desc_s *tx_desc = NULL;
  4421. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4422. if (!vdev && !force_free) {
  4423. dp_err("Reset TX desc vdev, Vdev param is required!");
  4424. return;
  4425. }
  4426. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4427. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4428. for (i = 0; i < num_pool; i++) {
  4429. tx_desc_pool = &soc->tx_desc[i];
  4430. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4431. continue;
  4432. num_desc_per_page =
  4433. tx_desc_pool->desc_pages.num_element_per_page;
  4434. for (j = 0; j < num_desc; j++) {
  4435. page_id = j / num_desc_per_page;
  4436. offset = j % num_desc_per_page;
  4437. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4438. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4439. if (force_free) {
  4440. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4441. dp_tx_comp_free_buf(soc, tx_desc);
  4442. dp_tx_desc_release(tx_desc, i);
  4443. } else {
  4444. dp_tx_desc_reset_vdev(soc, tx_desc,
  4445. i);
  4446. }
  4447. }
  4448. }
  4449. }
  4450. }
  4451. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4452. /**
  4453. * dp_tx_vdev_detach() - detach vdev from dp tx
  4454. * @vdev: virtual device instance
  4455. *
  4456. * Return: QDF_STATUS_SUCCESS: success
  4457. * QDF_STATUS_E_RESOURCES: Error return
  4458. */
  4459. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4460. {
  4461. struct dp_pdev *pdev = vdev->pdev;
  4462. /* Reset TX desc associated to this Vdev as NULL */
  4463. dp_tx_desc_flush(pdev, vdev, false);
  4464. return QDF_STATUS_SUCCESS;
  4465. }
  4466. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4467. /* Pools will be allocated dynamically */
  4468. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4469. int num_desc)
  4470. {
  4471. uint8_t i;
  4472. for (i = 0; i < num_pool; i++) {
  4473. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4474. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4475. }
  4476. return QDF_STATUS_SUCCESS;
  4477. }
  4478. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4479. int num_desc)
  4480. {
  4481. return QDF_STATUS_SUCCESS;
  4482. }
  4483. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4484. {
  4485. }
  4486. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4487. {
  4488. uint8_t i;
  4489. for (i = 0; i < num_pool; i++)
  4490. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4491. }
  4492. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4493. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4494. int num_desc)
  4495. {
  4496. uint8_t i, count;
  4497. /* Allocate software Tx descriptor pools */
  4498. for (i = 0; i < num_pool; i++) {
  4499. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4500. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4501. FL("Tx Desc Pool alloc %d failed %pK"),
  4502. i, soc);
  4503. goto fail;
  4504. }
  4505. }
  4506. return QDF_STATUS_SUCCESS;
  4507. fail:
  4508. for (count = 0; count < i; count++)
  4509. dp_tx_desc_pool_free(soc, count);
  4510. return QDF_STATUS_E_NOMEM;
  4511. }
  4512. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4513. int num_desc)
  4514. {
  4515. uint8_t i;
  4516. for (i = 0; i < num_pool; i++) {
  4517. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4518. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4519. FL("Tx Desc Pool init %d failed %pK"),
  4520. i, soc);
  4521. return QDF_STATUS_E_NOMEM;
  4522. }
  4523. }
  4524. return QDF_STATUS_SUCCESS;
  4525. }
  4526. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4527. {
  4528. uint8_t i;
  4529. for (i = 0; i < num_pool; i++)
  4530. dp_tx_desc_pool_deinit(soc, i);
  4531. }
  4532. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4533. {
  4534. uint8_t i;
  4535. for (i = 0; i < num_pool; i++)
  4536. dp_tx_desc_pool_free(soc, i);
  4537. }
  4538. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4539. /**
  4540. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4541. * @soc: core txrx main context
  4542. * @num_pool: number of pools
  4543. *
  4544. */
  4545. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4546. {
  4547. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4548. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4549. }
  4550. /**
  4551. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4552. * @soc: core txrx main context
  4553. * @num_pool: number of pools
  4554. *
  4555. */
  4556. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4557. {
  4558. dp_tx_tso_desc_pool_free(soc, num_pool);
  4559. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4560. }
  4561. /**
  4562. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4563. * @soc: core txrx main context
  4564. *
  4565. * This function frees all tx related descriptors as below
  4566. * 1. Regular TX descriptors (static pools)
  4567. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4568. * 3. TSO descriptors
  4569. *
  4570. */
  4571. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4572. {
  4573. uint8_t num_pool;
  4574. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4575. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4576. dp_tx_ext_desc_pool_free(soc, num_pool);
  4577. dp_tx_delete_static_pools(soc, num_pool);
  4578. }
  4579. /**
  4580. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4581. * @soc: core txrx main context
  4582. *
  4583. * This function de-initializes all tx related descriptors as below
  4584. * 1. Regular TX descriptors (static pools)
  4585. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4586. * 3. TSO descriptors
  4587. *
  4588. */
  4589. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4590. {
  4591. uint8_t num_pool;
  4592. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4593. dp_tx_flow_control_deinit(soc);
  4594. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4595. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4596. dp_tx_deinit_static_pools(soc, num_pool);
  4597. }
  4598. /**
  4599. * dp_tso_attach() - TSO attach handler
  4600. * @txrx_soc: Opaque Dp handle
  4601. *
  4602. * Reserve TSO descriptor buffers
  4603. *
  4604. * Return: QDF_STATUS_E_FAILURE on failure or
  4605. * QDF_STATUS_SUCCESS on success
  4606. */
  4607. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4608. uint8_t num_pool,
  4609. uint16_t num_desc)
  4610. {
  4611. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4612. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4613. return QDF_STATUS_E_FAILURE;
  4614. }
  4615. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4616. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4617. num_pool, soc);
  4618. return QDF_STATUS_E_FAILURE;
  4619. }
  4620. return QDF_STATUS_SUCCESS;
  4621. }
  4622. /**
  4623. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4624. * @soc: DP soc handle
  4625. * @num_pool: Number of pools
  4626. * @num_desc: Number of descriptors
  4627. *
  4628. * Initialize TSO descriptor pools
  4629. *
  4630. * Return: QDF_STATUS_E_FAILURE on failure or
  4631. * QDF_STATUS_SUCCESS on success
  4632. */
  4633. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4634. uint8_t num_pool,
  4635. uint16_t num_desc)
  4636. {
  4637. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4638. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4639. return QDF_STATUS_E_FAILURE;
  4640. }
  4641. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4642. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4643. num_pool, soc);
  4644. return QDF_STATUS_E_FAILURE;
  4645. }
  4646. return QDF_STATUS_SUCCESS;
  4647. }
  4648. /**
  4649. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4650. * @soc: core txrx main context
  4651. *
  4652. * This function allocates memory for following descriptor pools
  4653. * 1. regular sw tx descriptor pools (static pools)
  4654. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4655. * 3. TSO descriptor pools
  4656. *
  4657. * Return: QDF_STATUS_SUCCESS: success
  4658. * QDF_STATUS_E_RESOURCES: Error return
  4659. */
  4660. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4661. {
  4662. uint8_t num_pool;
  4663. uint32_t num_desc;
  4664. uint32_t num_ext_desc;
  4665. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4666. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4667. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4669. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4670. __func__, num_pool, num_desc);
  4671. if ((num_pool > MAX_TXDESC_POOLS) ||
  4672. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4673. goto fail1;
  4674. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4675. goto fail1;
  4676. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4677. goto fail2;
  4678. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4679. return QDF_STATUS_SUCCESS;
  4680. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4681. goto fail3;
  4682. return QDF_STATUS_SUCCESS;
  4683. fail3:
  4684. dp_tx_ext_desc_pool_free(soc, num_pool);
  4685. fail2:
  4686. dp_tx_delete_static_pools(soc, num_pool);
  4687. fail1:
  4688. return QDF_STATUS_E_RESOURCES;
  4689. }
  4690. /**
  4691. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4692. * @soc: core txrx main context
  4693. *
  4694. * This function initializes the following TX descriptor pools
  4695. * 1. regular sw tx descriptor pools (static pools)
  4696. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4697. * 3. TSO descriptor pools
  4698. *
  4699. * Return: QDF_STATUS_SUCCESS: success
  4700. * QDF_STATUS_E_RESOURCES: Error return
  4701. */
  4702. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4703. {
  4704. uint8_t num_pool;
  4705. uint32_t num_desc;
  4706. uint32_t num_ext_desc;
  4707. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4708. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4709. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4710. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4711. goto fail1;
  4712. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4713. goto fail2;
  4714. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4715. return QDF_STATUS_SUCCESS;
  4716. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4717. goto fail3;
  4718. dp_tx_flow_control_init(soc);
  4719. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4720. return QDF_STATUS_SUCCESS;
  4721. fail3:
  4722. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4723. fail2:
  4724. dp_tx_deinit_static_pools(soc, num_pool);
  4725. fail1:
  4726. return QDF_STATUS_E_RESOURCES;
  4727. }
  4728. /**
  4729. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4730. * @txrx_soc: dp soc handle
  4731. *
  4732. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4733. * QDF_STATUS_E_FAILURE
  4734. */
  4735. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4736. {
  4737. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4738. uint8_t num_pool;
  4739. uint32_t num_desc;
  4740. uint32_t num_ext_desc;
  4741. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4742. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4743. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4744. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4745. return QDF_STATUS_E_FAILURE;
  4746. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4747. return QDF_STATUS_E_FAILURE;
  4748. return QDF_STATUS_SUCCESS;
  4749. }
  4750. /**
  4751. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4752. * @txrx_soc: dp soc handle
  4753. *
  4754. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4755. */
  4756. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4757. {
  4758. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4759. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4760. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4761. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4762. return QDF_STATUS_SUCCESS;
  4763. }