msm_drv.c 50 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063
  1. /*
  2. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. /*
  19. * Copyright (c) 2016 Intel Corporation
  20. *
  21. * Permission to use, copy, modify, distribute, and sell this software and its
  22. * documentation for any purpose is hereby granted without fee, provided that
  23. * the above copyright notice appear in all copies and that both that copyright
  24. * notice and this permission notice appear in supporting documentation, and
  25. * that the name of the copyright holders not be used in advertising or
  26. * publicity pertaining to distribution of the software without specific,
  27. * written prior permission. The copyright holders make no representations
  28. * about the suitability of this software for any purpose. It is provided "as
  29. * is" without express or implied warranty.
  30. *
  31. * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  32. * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  33. * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  34. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  35. * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  36. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  37. * OF THIS SOFTWARE.
  38. */
  39. #include <linux/of_address.h>
  40. #include <linux/kthread.h>
  41. #include <uapi/linux/sched/types.h>
  42. #include <drm/drm_of.h>
  43. #include "msm_drv.h"
  44. #include "msm_kms.h"
  45. #include "msm_mmu.h"
  46. #include "sde_wb.h"
  47. #include "sde_dbg.h"
  48. /*
  49. * MSM driver version:
  50. * - 1.0.0 - initial interface
  51. * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
  52. * - 1.2.0 - adds explicit fence support for submit ioctl
  53. * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
  54. * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
  55. * MSM_GEM_INFO ioctl.
  56. */
  57. #define MSM_VERSION_MAJOR 1
  58. #define MSM_VERSION_MINOR 3
  59. #define MSM_VERSION_PATCHLEVEL 0
  60. static void msm_fb_output_poll_changed(struct drm_device *dev)
  61. {
  62. struct msm_drm_private *priv = NULL;
  63. if (!dev) {
  64. DRM_ERROR("output_poll_changed failed, invalid input\n");
  65. return;
  66. }
  67. priv = dev->dev_private;
  68. if (priv->fbdev)
  69. drm_fb_helper_hotplug_event(priv->fbdev);
  70. }
  71. /**
  72. * msm_atomic_helper_check - validate state object
  73. * @dev: DRM device
  74. * @state: the driver state object
  75. *
  76. * This is a wrapper for the drm_atomic_helper_check to check the modeset
  77. * and state checking for planes. Additionally it checks if any secure
  78. * transition(moving CRTC and planes between secure and non-secure states and
  79. * vice versa) is allowed or not. When going to secure state, planes
  80. * with fb_mode as dir translated only can be staged on the CRTC, and only one
  81. * CRTC should be active.
  82. * Also mixing of secure and non-secure is not allowed.
  83. *
  84. * RETURNS
  85. * Zero for success or -errorno.
  86. */
  87. int msm_atomic_check(struct drm_device *dev,
  88. struct drm_atomic_state *state)
  89. {
  90. struct msm_drm_private *priv;
  91. priv = dev->dev_private;
  92. if (priv && priv->kms && priv->kms->funcs &&
  93. priv->kms->funcs->atomic_check)
  94. return priv->kms->funcs->atomic_check(priv->kms, state);
  95. return drm_atomic_helper_check(dev, state);
  96. }
  97. static const struct drm_mode_config_funcs mode_config_funcs = {
  98. .fb_create = msm_framebuffer_create,
  99. .output_poll_changed = msm_fb_output_poll_changed,
  100. .atomic_check = msm_atomic_check,
  101. .atomic_commit = msm_atomic_commit,
  102. .atomic_state_alloc = msm_atomic_state_alloc,
  103. .atomic_state_clear = msm_atomic_state_clear,
  104. .atomic_state_free = msm_atomic_state_free,
  105. };
  106. static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
  107. .atomic_commit_tail = msm_atomic_commit_tail,
  108. };
  109. #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
  110. static bool reglog = false;
  111. MODULE_PARM_DESC(reglog, "Enable register read/write logging");
  112. module_param(reglog, bool, 0600);
  113. #else
  114. #define reglog 0
  115. #endif
  116. #ifdef CONFIG_DRM_FBDEV_EMULATION
  117. static bool fbdev = true;
  118. MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
  119. module_param(fbdev, bool, 0600);
  120. #endif
  121. static char *vram = "16m";
  122. MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
  123. module_param(vram, charp, 0);
  124. bool dumpstate = false;
  125. MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
  126. module_param(dumpstate, bool, 0600);
  127. static bool modeset = true;
  128. MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
  129. module_param(modeset, bool, 0600);
  130. /*
  131. * Util/helpers:
  132. */
  133. int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
  134. {
  135. struct property *prop;
  136. const char *name;
  137. struct clk_bulk_data *local;
  138. int i = 0, ret, count;
  139. count = of_property_count_strings(dev->of_node, "clock-names");
  140. if (count < 1)
  141. return 0;
  142. local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
  143. count, GFP_KERNEL);
  144. if (!local)
  145. return -ENOMEM;
  146. of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
  147. local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
  148. if (!local[i].id) {
  149. devm_kfree(dev, local);
  150. return -ENOMEM;
  151. }
  152. i++;
  153. }
  154. ret = devm_clk_bulk_get(dev, count, local);
  155. if (ret) {
  156. for (i = 0; i < count; i++)
  157. devm_kfree(dev, (void *) local[i].id);
  158. devm_kfree(dev, local);
  159. return ret;
  160. }
  161. *bulk = local;
  162. return count;
  163. }
  164. struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
  165. const char *name)
  166. {
  167. int i;
  168. char n[32];
  169. snprintf(n, sizeof(n), "%s_clk", name);
  170. for (i = 0; bulk && i < count; i++) {
  171. if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
  172. return bulk[i].clk;
  173. }
  174. return NULL;
  175. }
  176. struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
  177. {
  178. struct clk *clk;
  179. char name2[32];
  180. clk = devm_clk_get(&pdev->dev, name);
  181. if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
  182. return clk;
  183. snprintf(name2, sizeof(name2), "%s_clk", name);
  184. clk = devm_clk_get(&pdev->dev, name2);
  185. if (!IS_ERR(clk))
  186. dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
  187. "\"%s\" instead of \"%s\"\n", name, name2);
  188. return clk;
  189. }
  190. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  191. const char *dbgname)
  192. {
  193. struct resource *res;
  194. unsigned long size;
  195. void __iomem *ptr;
  196. if (name)
  197. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  198. else
  199. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  200. if (!res) {
  201. dev_dbg(&pdev->dev, "failed to get memory resource: %s\n",
  202. name);
  203. return ERR_PTR(-EINVAL);
  204. }
  205. size = resource_size(res);
  206. ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
  207. if (!ptr) {
  208. dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
  209. return ERR_PTR(-ENOMEM);
  210. }
  211. if (reglog)
  212. dev_dbg(&pdev->dev, "IO:region %s %pK %08lx\n",
  213. dbgname, ptr, size);
  214. return ptr;
  215. }
  216. unsigned long msm_iomap_size(struct platform_device *pdev, const char *name)
  217. {
  218. struct resource *res;
  219. if (name)
  220. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  221. else
  222. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  223. if (!res) {
  224. dev_dbg(&pdev->dev, "failed to get memory resource: %s\n",
  225. name);
  226. return 0;
  227. }
  228. return resource_size(res);
  229. }
  230. void msm_iounmap(struct platform_device *pdev, void __iomem *addr)
  231. {
  232. devm_iounmap(&pdev->dev, addr);
  233. }
  234. void msm_writel(u32 data, void __iomem *addr)
  235. {
  236. if (reglog)
  237. pr_debug("IO:W %pK %08x\n", addr, data);
  238. writel(data, addr);
  239. }
  240. u32 msm_readl(const void __iomem *addr)
  241. {
  242. u32 val = readl(addr);
  243. if (reglog)
  244. pr_err("IO:R %pK %08x\n", addr, val);
  245. return val;
  246. }
  247. struct vblank_work {
  248. struct kthread_work work;
  249. int crtc_id;
  250. bool enable;
  251. struct msm_drm_private *priv;
  252. };
  253. static void vblank_ctrl_worker(struct kthread_work *work)
  254. {
  255. struct vblank_work *cur_work = container_of(work,
  256. struct vblank_work, work);
  257. struct msm_drm_private *priv = cur_work->priv;
  258. struct msm_kms *kms = priv->kms;
  259. if (cur_work->enable)
  260. kms->funcs->enable_vblank(kms, priv->crtcs[cur_work->crtc_id]);
  261. else
  262. kms->funcs->disable_vblank(kms, priv->crtcs[cur_work->crtc_id]);
  263. kfree(cur_work);
  264. }
  265. static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
  266. int crtc_id, bool enable)
  267. {
  268. struct vblank_work *cur_work;
  269. if (!priv || crtc_id >= priv->num_crtcs)
  270. return -EINVAL;
  271. cur_work = kzalloc(sizeof(*cur_work), GFP_ATOMIC);
  272. if (!cur_work)
  273. return -ENOMEM;
  274. kthread_init_work(&cur_work->work, vblank_ctrl_worker);
  275. cur_work->crtc_id = crtc_id;
  276. cur_work->enable = enable;
  277. cur_work->priv = priv;
  278. kthread_queue_work(&priv->disp_thread[crtc_id].worker, &cur_work->work);
  279. return 0;
  280. }
  281. static int msm_drm_uninit(struct device *dev)
  282. {
  283. struct platform_device *pdev = to_platform_device(dev);
  284. struct drm_device *ddev = platform_get_drvdata(pdev);
  285. struct msm_drm_private *priv = ddev->dev_private;
  286. struct msm_kms *kms = priv->kms;
  287. int i;
  288. /* clean up display commit/event worker threads */
  289. for (i = 0; i < priv->num_crtcs; i++) {
  290. if (priv->disp_thread[i].thread) {
  291. kthread_flush_worker(&priv->disp_thread[i].worker);
  292. kthread_stop(priv->disp_thread[i].thread);
  293. priv->disp_thread[i].thread = NULL;
  294. }
  295. if (priv->event_thread[i].thread) {
  296. kthread_flush_worker(&priv->event_thread[i].worker);
  297. kthread_stop(priv->event_thread[i].thread);
  298. priv->event_thread[i].thread = NULL;
  299. }
  300. }
  301. drm_kms_helper_poll_fini(ddev);
  302. drm_mode_config_cleanup(ddev);
  303. if (priv->registered) {
  304. drm_dev_unregister(ddev);
  305. priv->registered = false;
  306. }
  307. #ifdef CONFIG_DRM_FBDEV_EMULATION
  308. if (fbdev && priv->fbdev)
  309. msm_fbdev_free(ddev);
  310. #endif
  311. drm_mode_config_cleanup(ddev);
  312. pm_runtime_get_sync(dev);
  313. drm_irq_uninstall(ddev);
  314. pm_runtime_put_sync(dev);
  315. flush_workqueue(priv->wq);
  316. destroy_workqueue(priv->wq);
  317. if (kms && kms->funcs)
  318. kms->funcs->destroy(kms);
  319. if (priv->vram.paddr) {
  320. unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
  321. drm_mm_takedown(&priv->vram.mm);
  322. dma_free_attrs(dev, priv->vram.size, NULL,
  323. priv->vram.paddr, attrs);
  324. }
  325. component_unbind_all(dev, ddev);
  326. sde_dbg_destroy();
  327. debugfs_remove_recursive(priv->debug_root);
  328. sde_power_resource_deinit(pdev, &priv->phandle);
  329. msm_mdss_destroy(ddev);
  330. ddev->dev_private = NULL;
  331. kfree(priv);
  332. drm_dev_put(ddev);
  333. return 0;
  334. }
  335. #define KMS_MDP4 4
  336. #define KMS_MDP5 5
  337. #define KMS_SDE 3
  338. static int get_mdp_ver(struct platform_device *pdev)
  339. {
  340. #ifdef CONFIG_OF
  341. static const struct of_device_id match_types[] = { {
  342. .compatible = "qcom,mdss_mdp",
  343. .data = (void *)KMS_MDP5,
  344. },
  345. {
  346. .compatible = "qcom,sde-kms",
  347. .data = (void *)KMS_SDE,
  348. },
  349. {},
  350. };
  351. struct device *dev = &pdev->dev;
  352. const struct of_device_id *match;
  353. match = of_match_node(match_types, dev->of_node);
  354. if (match)
  355. return (int)(unsigned long)match->data;
  356. #endif
  357. return KMS_MDP4;
  358. }
  359. static int msm_init_vram(struct drm_device *dev)
  360. {
  361. struct msm_drm_private *priv = dev->dev_private;
  362. struct device_node *node;
  363. unsigned long size = 0;
  364. int ret = 0;
  365. /* In the device-tree world, we could have a 'memory-region'
  366. * phandle, which gives us a link to our "vram". Allocating
  367. * is all nicely abstracted behind the dma api, but we need
  368. * to know the entire size to allocate it all in one go. There
  369. * are two cases:
  370. * 1) device with no IOMMU, in which case we need exclusive
  371. * access to a VRAM carveout big enough for all gpu
  372. * buffers
  373. * 2) device with IOMMU, but where the bootloader puts up
  374. * a splash screen. In this case, the VRAM carveout
  375. * need only be large enough for fbdev fb. But we need
  376. * exclusive access to the buffer to avoid the kernel
  377. * using those pages for other purposes (which appears
  378. * as corruption on screen before we have a chance to
  379. * load and do initial modeset)
  380. */
  381. node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
  382. if (node) {
  383. struct resource r;
  384. ret = of_address_to_resource(node, 0, &r);
  385. of_node_put(node);
  386. if (ret)
  387. return ret;
  388. size = r.end - r.start;
  389. DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
  390. /* if we have no IOMMU, then we need to use carveout allocator.
  391. * Grab the entire CMA chunk carved out in early startup in
  392. * mach-msm:
  393. */
  394. } else if (!iommu_present(&platform_bus_type)) {
  395. DRM_INFO("using %s VRAM carveout\n", vram);
  396. size = memparse(vram, NULL);
  397. }
  398. if (size) {
  399. unsigned long attrs = 0;
  400. void *p;
  401. priv->vram.size = size;
  402. drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
  403. spin_lock_init(&priv->vram.lock);
  404. attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
  405. attrs |= DMA_ATTR_WRITE_COMBINE;
  406. /* note that for no-kernel-mapping, the vaddr returned
  407. * is bogus, but non-null if allocation succeeded:
  408. */
  409. p = dma_alloc_attrs(dev->dev, size,
  410. &priv->vram.paddr, GFP_KERNEL, attrs);
  411. if (!p) {
  412. dev_err(dev->dev, "failed to allocate VRAM\n");
  413. priv->vram.paddr = 0;
  414. return -ENOMEM;
  415. }
  416. dev_info(dev->dev, "VRAM: %08x->%08x\n",
  417. (uint32_t)priv->vram.paddr,
  418. (uint32_t)(priv->vram.paddr + size));
  419. }
  420. return ret;
  421. }
  422. #ifdef CONFIG_OF
  423. static int msm_component_bind_all(struct device *dev,
  424. struct drm_device *drm_dev)
  425. {
  426. int ret;
  427. ret = component_bind_all(dev, drm_dev);
  428. if (ret)
  429. DRM_ERROR("component_bind_all failed: %d\n", ret);
  430. return ret;
  431. }
  432. #else
  433. static int msm_component_bind_all(struct device *dev,
  434. struct drm_device *drm_dev)
  435. {
  436. return 0;
  437. }
  438. #endif
  439. static int msm_drm_display_thread_create(struct sched_param param,
  440. struct msm_drm_private *priv, struct drm_device *ddev,
  441. struct device *dev)
  442. {
  443. int i, ret = 0;
  444. /**
  445. * this priority was found during empiric testing to have appropriate
  446. * realtime scheduling to process display updates and interact with
  447. * other real time and normal priority task
  448. */
  449. param.sched_priority = 16;
  450. for (i = 0; i < priv->num_crtcs; i++) {
  451. /* initialize display thread */
  452. priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
  453. kthread_init_worker(&priv->disp_thread[i].worker);
  454. priv->disp_thread[i].dev = ddev;
  455. priv->disp_thread[i].thread =
  456. kthread_run(kthread_worker_fn,
  457. &priv->disp_thread[i].worker,
  458. "crtc_commit:%d", priv->disp_thread[i].crtc_id);
  459. ret = sched_setscheduler(priv->disp_thread[i].thread,
  460. SCHED_FIFO, &param);
  461. if (ret)
  462. pr_warn("display thread priority update failed: %d\n",
  463. ret);
  464. if (IS_ERR(priv->disp_thread[i].thread)) {
  465. dev_err(dev, "failed to create crtc_commit kthread\n");
  466. priv->disp_thread[i].thread = NULL;
  467. }
  468. /* initialize event thread */
  469. priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
  470. kthread_init_worker(&priv->event_thread[i].worker);
  471. priv->event_thread[i].dev = ddev;
  472. priv->event_thread[i].thread =
  473. kthread_run(kthread_worker_fn,
  474. &priv->event_thread[i].worker,
  475. "crtc_event:%d", priv->event_thread[i].crtc_id);
  476. /**
  477. * event thread should also run at same priority as disp_thread
  478. * because it is handling frame_done events. A lower priority
  479. * event thread and higher priority disp_thread can causes
  480. * frame_pending counters beyond 2. This can lead to commit
  481. * failure at crtc commit level.
  482. */
  483. ret = sched_setscheduler(priv->event_thread[i].thread,
  484. SCHED_FIFO, &param);
  485. if (ret)
  486. pr_warn("display event thread priority update failed: %d\n",
  487. ret);
  488. if (IS_ERR(priv->event_thread[i].thread)) {
  489. dev_err(dev, "failed to create crtc_event kthread\n");
  490. priv->event_thread[i].thread = NULL;
  491. }
  492. if ((!priv->disp_thread[i].thread) ||
  493. !priv->event_thread[i].thread) {
  494. /* clean up previously created threads if any */
  495. for ( ; i >= 0; i--) {
  496. if (priv->disp_thread[i].thread) {
  497. kthread_stop(
  498. priv->disp_thread[i].thread);
  499. priv->disp_thread[i].thread = NULL;
  500. }
  501. if (priv->event_thread[i].thread) {
  502. kthread_stop(
  503. priv->event_thread[i].thread);
  504. priv->event_thread[i].thread = NULL;
  505. }
  506. }
  507. return -EINVAL;
  508. }
  509. }
  510. /**
  511. * Since pp interrupt is heavy weight, try to queue the work
  512. * into a dedicated worker thread, so that they dont interrupt
  513. * other important events.
  514. */
  515. kthread_init_worker(&priv->pp_event_worker);
  516. priv->pp_event_thread = kthread_run(kthread_worker_fn,
  517. &priv->pp_event_worker, "pp_event");
  518. ret = sched_setscheduler(priv->pp_event_thread,
  519. SCHED_FIFO, &param);
  520. if (ret)
  521. pr_warn("pp_event thread priority update failed: %d\n",
  522. ret);
  523. if (IS_ERR(priv->pp_event_thread)) {
  524. dev_err(dev, "failed to create pp_event kthread\n");
  525. ret = PTR_ERR(priv->pp_event_thread);
  526. priv->pp_event_thread = NULL;
  527. return ret;
  528. }
  529. return 0;
  530. }
  531. static struct msm_kms *_msm_drm_init_helper(struct msm_drm_private *priv,
  532. struct drm_device *ddev, struct device *dev,
  533. struct platform_device *pdev)
  534. {
  535. int ret;
  536. struct msm_kms *kms;
  537. switch (get_mdp_ver(pdev)) {
  538. case KMS_MDP4:
  539. kms = mdp4_kms_init(ddev);
  540. break;
  541. case KMS_MDP5:
  542. kms = mdp5_kms_init(ddev);
  543. break;
  544. case KMS_SDE:
  545. kms = sde_kms_init(ddev);
  546. break;
  547. default:
  548. kms = ERR_PTR(-ENODEV);
  549. break;
  550. }
  551. if (IS_ERR_OR_NULL(kms)) {
  552. /*
  553. * NOTE: once we have GPU support, having no kms should not
  554. * be considered fatal.. ideally we would still support gpu
  555. * and (for example) use dmabuf/prime to share buffers with
  556. * imx drm driver on iMX5
  557. */
  558. dev_err(dev, "failed to load kms\n");
  559. return kms;
  560. }
  561. priv->kms = kms;
  562. pm_runtime_enable(dev);
  563. /**
  564. * Since kms->funcs->hw_init(kms) might call
  565. * drm_object_property_set_value to initialize some custom
  566. * properties we need to make sure mode_config.funcs are populated
  567. * beforehand to avoid dereferencing an unset value during the
  568. * drm_drv_uses_atomic_modeset check.
  569. */
  570. ddev->mode_config.funcs = &mode_config_funcs;
  571. ret = (kms)->funcs->hw_init(kms);
  572. if (ret) {
  573. dev_err(dev, "kms hw init failed: %d\n", ret);
  574. return ERR_PTR(ret);
  575. }
  576. return kms;
  577. }
  578. static int msm_drm_init(struct device *dev, struct drm_driver *drv)
  579. {
  580. struct platform_device *pdev = to_platform_device(dev);
  581. struct drm_device *ddev;
  582. struct msm_drm_private *priv;
  583. struct msm_kms *kms = NULL;
  584. int ret;
  585. struct sched_param param = { 0 };
  586. struct drm_crtc *crtc;
  587. ddev = drm_dev_alloc(drv, dev);
  588. if (!ddev) {
  589. dev_err(dev, "failed to allocate drm_device\n");
  590. return -ENOMEM;
  591. }
  592. drm_mode_config_init(ddev);
  593. platform_set_drvdata(pdev, ddev);
  594. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  595. if (!priv) {
  596. ret = -ENOMEM;
  597. goto priv_alloc_fail;
  598. }
  599. ddev->dev_private = priv;
  600. priv->dev = ddev;
  601. ret = msm_mdss_init(ddev);
  602. if (ret)
  603. goto mdss_init_fail;
  604. priv->wq = alloc_ordered_workqueue("msm_drm", 0);
  605. init_waitqueue_head(&priv->pending_crtcs_event);
  606. INIT_LIST_HEAD(&priv->client_event_list);
  607. INIT_LIST_HEAD(&priv->inactive_list);
  608. ret = sde_power_resource_init(pdev, &priv->phandle);
  609. if (ret) {
  610. pr_err("sde power resource init failed\n");
  611. goto power_init_fail;
  612. }
  613. ret = sde_dbg_init(&pdev->dev);
  614. if (ret) {
  615. dev_err(dev, "failed to init sde dbg: %d\n", ret);
  616. goto dbg_init_fail;
  617. }
  618. /* Bind all our sub-components: */
  619. ret = msm_component_bind_all(dev, ddev);
  620. if (ret)
  621. goto bind_fail;
  622. ret = msm_init_vram(ddev);
  623. if (ret)
  624. goto fail;
  625. ddev->mode_config.funcs = &mode_config_funcs;
  626. ddev->mode_config.helper_private = &mode_config_helper_funcs;
  627. kms = _msm_drm_init_helper(priv, ddev, dev, pdev);
  628. if (IS_ERR_OR_NULL(kms)) {
  629. dev_err(dev, "msm_drm_init_helper failed\n");
  630. goto fail;
  631. }
  632. ret = msm_drm_display_thread_create(param, priv, ddev, dev);
  633. if (ret) {
  634. dev_err(dev, "msm_drm_display_thread_create failed\n");
  635. goto fail;
  636. }
  637. ret = drm_vblank_init(ddev, priv->num_crtcs);
  638. if (ret < 0) {
  639. dev_err(dev, "failed to initialize vblank\n");
  640. goto fail;
  641. }
  642. drm_for_each_crtc(crtc, ddev)
  643. drm_crtc_vblank_reset(crtc);
  644. if (kms) {
  645. pm_runtime_get_sync(dev);
  646. ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
  647. pm_runtime_put_sync(dev);
  648. if (ret < 0) {
  649. dev_err(dev, "failed to install IRQ handler\n");
  650. goto fail;
  651. }
  652. }
  653. ret = drm_dev_register(ddev, 0);
  654. if (ret)
  655. goto fail;
  656. priv->registered = true;
  657. drm_mode_config_reset(ddev);
  658. if (kms && kms->funcs && kms->funcs->cont_splash_config) {
  659. ret = kms->funcs->cont_splash_config(kms);
  660. if (ret) {
  661. dev_err(dev, "kms cont_splash config failed.\n");
  662. goto fail;
  663. }
  664. }
  665. #ifdef CONFIG_DRM_FBDEV_EMULATION
  666. if (fbdev)
  667. priv->fbdev = msm_fbdev_init(ddev);
  668. #endif
  669. priv->debug_root = debugfs_create_dir("debug",
  670. ddev->primary->debugfs_root);
  671. if (IS_ERR_OR_NULL(priv->debug_root)) {
  672. pr_err("debugfs_root create_dir fail, error %ld\n",
  673. PTR_ERR(priv->debug_root));
  674. priv->debug_root = NULL;
  675. goto fail;
  676. }
  677. ret = sde_dbg_debugfs_register(priv->debug_root);
  678. if (ret) {
  679. dev_err(dev, "failed to reg sde dbg debugfs: %d\n", ret);
  680. goto fail;
  681. }
  682. /* perform subdriver post initialization */
  683. if (kms && kms->funcs && kms->funcs->postinit) {
  684. ret = kms->funcs->postinit(kms);
  685. if (ret) {
  686. pr_err("kms post init failed: %d\n", ret);
  687. goto fail;
  688. }
  689. }
  690. drm_kms_helper_poll_init(ddev);
  691. return 0;
  692. fail:
  693. msm_drm_uninit(dev);
  694. return ret;
  695. bind_fail:
  696. sde_dbg_destroy();
  697. dbg_init_fail:
  698. sde_power_resource_deinit(pdev, &priv->phandle);
  699. power_init_fail:
  700. msm_mdss_destroy(ddev);
  701. mdss_init_fail:
  702. kfree(priv);
  703. priv_alloc_fail:
  704. drm_dev_put(ddev);
  705. return ret;
  706. }
  707. /*
  708. * DRM operations:
  709. */
  710. static int context_init(struct drm_device *dev, struct drm_file *file)
  711. {
  712. struct msm_file_private *ctx;
  713. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  714. if (!ctx)
  715. return -ENOMEM;
  716. mutex_init(&ctx->power_lock);
  717. file->driver_priv = ctx;
  718. if (dev && dev->dev_private) {
  719. struct msm_drm_private *priv = dev->dev_private;
  720. struct msm_kms *kms;
  721. kms = priv->kms;
  722. if (kms && kms->funcs && kms->funcs->postopen)
  723. kms->funcs->postopen(kms, file);
  724. }
  725. return 0;
  726. }
  727. static int msm_open(struct drm_device *dev, struct drm_file *file)
  728. {
  729. return context_init(dev, file);
  730. }
  731. static void context_close(struct msm_file_private *ctx)
  732. {
  733. kfree(ctx);
  734. }
  735. static void msm_preclose(struct drm_device *dev, struct drm_file *file)
  736. {
  737. struct msm_drm_private *priv = dev->dev_private;
  738. struct msm_kms *kms = priv->kms;
  739. if (kms && kms->funcs && kms->funcs->preclose)
  740. kms->funcs->preclose(kms, file);
  741. }
  742. static void msm_postclose(struct drm_device *dev, struct drm_file *file)
  743. {
  744. struct msm_drm_private *priv = dev->dev_private;
  745. struct msm_file_private *ctx = file->driver_priv;
  746. struct msm_kms *kms = priv->kms;
  747. if (kms && kms->funcs && kms->funcs->postclose)
  748. kms->funcs->postclose(kms, file);
  749. mutex_lock(&dev->struct_mutex);
  750. if (ctx == priv->lastctx)
  751. priv->lastctx = NULL;
  752. mutex_unlock(&dev->struct_mutex);
  753. mutex_lock(&ctx->power_lock);
  754. if (ctx->enable_refcnt) {
  755. SDE_EVT32(ctx->enable_refcnt);
  756. pm_runtime_put_sync(dev->dev);
  757. }
  758. mutex_unlock(&ctx->power_lock);
  759. context_close(ctx);
  760. }
  761. static int msm_disable_all_modes_commit(
  762. struct drm_device *dev,
  763. struct drm_atomic_state *state)
  764. {
  765. struct drm_plane *plane;
  766. struct drm_crtc *crtc;
  767. unsigned int plane_mask;
  768. int ret;
  769. plane_mask = 0;
  770. drm_for_each_plane(plane, dev) {
  771. struct drm_plane_state *plane_state;
  772. plane_state = drm_atomic_get_plane_state(state, plane);
  773. if (IS_ERR(plane_state)) {
  774. ret = PTR_ERR(plane_state);
  775. goto fail;
  776. }
  777. plane_state->rotation = 0;
  778. plane->old_fb = plane->fb;
  779. plane_mask |= 1 << drm_plane_index(plane);
  780. /* disable non-primary: */
  781. if (plane->type == DRM_PLANE_TYPE_PRIMARY)
  782. continue;
  783. DRM_DEBUG("disabling plane %d\n", plane->base.id);
  784. ret = __drm_atomic_helper_disable_plane(plane, plane_state);
  785. if (ret != 0)
  786. DRM_ERROR("error %d disabling plane %d\n", ret,
  787. plane->base.id);
  788. }
  789. drm_for_each_crtc(crtc, dev) {
  790. struct drm_mode_set mode_set;
  791. memset(&mode_set, 0, sizeof(struct drm_mode_set));
  792. mode_set.crtc = crtc;
  793. DRM_DEBUG("disabling crtc %d\n", crtc->base.id);
  794. ret = __drm_atomic_helper_set_config(&mode_set, state);
  795. if (ret != 0)
  796. DRM_ERROR("error %d disabling crtc %d\n", ret,
  797. crtc->base.id);
  798. }
  799. DRM_DEBUG("committing disables\n");
  800. ret = drm_atomic_commit(state);
  801. fail:
  802. DRM_DEBUG("disables result %d\n", ret);
  803. return ret;
  804. }
  805. /**
  806. * msm_clear_all_modes - disables all planes and crtcs via an atomic commit
  807. * based on restore_fbdev_mode_atomic in drm_fb_helper.c
  808. * @dev: device pointer
  809. * @Return: 0 on success, otherwise -error
  810. */
  811. static int msm_disable_all_modes(
  812. struct drm_device *dev,
  813. struct drm_modeset_acquire_ctx *ctx)
  814. {
  815. struct drm_atomic_state *state;
  816. int ret, i;
  817. state = drm_atomic_state_alloc(dev);
  818. if (!state)
  819. return -ENOMEM;
  820. state->acquire_ctx = ctx;
  821. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  822. ret = msm_disable_all_modes_commit(dev, state);
  823. if (ret != -EDEADLK || ret != -ERESTARTSYS)
  824. break;
  825. drm_atomic_state_clear(state);
  826. drm_modeset_backoff(ctx);
  827. }
  828. drm_atomic_state_put(state);
  829. return ret;
  830. }
  831. static void msm_lastclose(struct drm_device *dev)
  832. {
  833. struct msm_drm_private *priv = dev->dev_private;
  834. struct msm_kms *kms = priv->kms;
  835. struct drm_modeset_acquire_ctx ctx;
  836. int i, rc;
  837. /* check for splash status before triggering cleanup
  838. * if we end up here with splash status ON i.e before first
  839. * commit then ignore the last close call
  840. */
  841. if (kms && kms->funcs && kms->funcs->check_for_splash
  842. && kms->funcs->check_for_splash(kms))
  843. return;
  844. /*
  845. * clean up vblank disable immediately as this is the last close.
  846. */
  847. for (i = 0; i < dev->num_crtcs; i++) {
  848. struct drm_vblank_crtc *vblank = &dev->vblank[i];
  849. struct timer_list *disable_timer = &vblank->disable_timer;
  850. if (del_timer_sync(disable_timer))
  851. disable_timer->function(disable_timer);
  852. }
  853. /* wait for pending vblank requests to be executed by worker thread */
  854. flush_workqueue(priv->wq);
  855. if (priv->fbdev) {
  856. drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  857. return;
  858. }
  859. drm_modeset_acquire_init(&ctx, 0);
  860. retry:
  861. rc = drm_modeset_lock_all_ctx(dev, &ctx);
  862. if (rc)
  863. goto fail;
  864. rc = msm_disable_all_modes(dev, &ctx);
  865. if (rc)
  866. goto fail;
  867. if (kms && kms->funcs && kms->funcs->lastclose)
  868. kms->funcs->lastclose(kms, &ctx);
  869. fail:
  870. if (rc == -EDEADLK) {
  871. drm_modeset_backoff(&ctx);
  872. goto retry;
  873. } else if (rc) {
  874. pr_err("last close failed: %d\n", rc);
  875. }
  876. drm_modeset_drop_locks(&ctx);
  877. drm_modeset_acquire_fini(&ctx);
  878. }
  879. static irqreturn_t msm_irq(int irq, void *arg)
  880. {
  881. struct drm_device *dev = arg;
  882. struct msm_drm_private *priv = dev->dev_private;
  883. struct msm_kms *kms = priv->kms;
  884. BUG_ON(!kms);
  885. return kms->funcs->irq(kms);
  886. }
  887. static void msm_irq_preinstall(struct drm_device *dev)
  888. {
  889. struct msm_drm_private *priv = dev->dev_private;
  890. struct msm_kms *kms = priv->kms;
  891. BUG_ON(!kms);
  892. kms->funcs->irq_preinstall(kms);
  893. }
  894. static int msm_irq_postinstall(struct drm_device *dev)
  895. {
  896. struct msm_drm_private *priv = dev->dev_private;
  897. struct msm_kms *kms = priv->kms;
  898. BUG_ON(!kms);
  899. return kms->funcs->irq_postinstall(kms);
  900. }
  901. static void msm_irq_uninstall(struct drm_device *dev)
  902. {
  903. struct msm_drm_private *priv = dev->dev_private;
  904. struct msm_kms *kms = priv->kms;
  905. BUG_ON(!kms);
  906. kms->funcs->irq_uninstall(kms);
  907. }
  908. static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
  909. {
  910. struct msm_drm_private *priv = dev->dev_private;
  911. struct msm_kms *kms = priv->kms;
  912. if (!kms)
  913. return -ENXIO;
  914. DBG("dev=%pK, crtc=%u", dev, pipe);
  915. return vblank_ctrl_queue_work(priv, pipe, true);
  916. }
  917. static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
  918. {
  919. struct msm_drm_private *priv = dev->dev_private;
  920. struct msm_kms *kms = priv->kms;
  921. if (!kms)
  922. return;
  923. DBG("dev=%pK, crtc=%u", dev, pipe);
  924. vblank_ctrl_queue_work(priv, pipe, false);
  925. }
  926. /*
  927. * DRM ioctls:
  928. */
  929. static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
  930. struct drm_file *file)
  931. {
  932. struct drm_msm_gem_new *args = data;
  933. if (args->flags & ~MSM_BO_FLAGS) {
  934. DRM_ERROR("invalid flags: %08x\n", args->flags);
  935. return -EINVAL;
  936. }
  937. return msm_gem_new_handle(dev, file, args->size,
  938. args->flags, &args->handle);
  939. }
  940. static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
  941. {
  942. return ktime_set(timeout.tv_sec, timeout.tv_nsec);
  943. }
  944. static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  945. struct drm_file *file)
  946. {
  947. struct drm_msm_gem_cpu_prep *args = data;
  948. struct drm_gem_object *obj;
  949. ktime_t timeout = to_ktime(args->timeout);
  950. int ret;
  951. if (args->op & ~MSM_PREP_FLAGS) {
  952. DRM_ERROR("invalid op: %08x\n", args->op);
  953. return -EINVAL;
  954. }
  955. obj = drm_gem_object_lookup(file, args->handle);
  956. if (!obj)
  957. return -ENOENT;
  958. ret = msm_gem_cpu_prep(obj, args->op, &timeout);
  959. drm_gem_object_put_unlocked(obj);
  960. return ret;
  961. }
  962. static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  963. struct drm_file *file)
  964. {
  965. struct drm_msm_gem_cpu_fini *args = data;
  966. struct drm_gem_object *obj;
  967. int ret;
  968. obj = drm_gem_object_lookup(file, args->handle);
  969. if (!obj)
  970. return -ENOENT;
  971. ret = msm_gem_cpu_fini(obj);
  972. drm_gem_object_put_unlocked(obj);
  973. return ret;
  974. }
  975. static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
  976. struct drm_file *file)
  977. {
  978. struct drm_msm_gem_madvise *args = data;
  979. struct drm_gem_object *obj;
  980. int ret;
  981. switch (args->madv) {
  982. case MSM_MADV_DONTNEED:
  983. case MSM_MADV_WILLNEED:
  984. break;
  985. default:
  986. return -EINVAL;
  987. }
  988. ret = mutex_lock_interruptible(&dev->struct_mutex);
  989. if (ret)
  990. return ret;
  991. obj = drm_gem_object_lookup(file, args->handle);
  992. if (!obj) {
  993. ret = -ENOENT;
  994. goto unlock;
  995. }
  996. ret = msm_gem_madvise(obj, args->madv);
  997. if (ret >= 0) {
  998. args->retained = ret;
  999. ret = 0;
  1000. }
  1001. drm_gem_object_put(obj);
  1002. unlock:
  1003. mutex_unlock(&dev->struct_mutex);
  1004. return ret;
  1005. }
  1006. static int msm_drm_object_supports_event(struct drm_device *dev,
  1007. struct drm_msm_event_req *req)
  1008. {
  1009. int ret = -EINVAL;
  1010. struct drm_mode_object *arg_obj;
  1011. arg_obj = drm_mode_object_find(dev, NULL, req->object_id,
  1012. req->object_type);
  1013. if (!arg_obj)
  1014. return -ENOENT;
  1015. switch (arg_obj->type) {
  1016. case DRM_MODE_OBJECT_CRTC:
  1017. case DRM_MODE_OBJECT_CONNECTOR:
  1018. ret = 0;
  1019. break;
  1020. default:
  1021. ret = -EOPNOTSUPP;
  1022. break;
  1023. }
  1024. drm_mode_object_put(arg_obj);
  1025. return ret;
  1026. }
  1027. static int msm_register_event(struct drm_device *dev,
  1028. struct drm_msm_event_req *req, struct drm_file *file, bool en)
  1029. {
  1030. int ret = -EINVAL;
  1031. struct msm_drm_private *priv = dev->dev_private;
  1032. struct msm_kms *kms = priv->kms;
  1033. struct drm_mode_object *arg_obj;
  1034. arg_obj = drm_mode_object_find(dev, file, req->object_id,
  1035. req->object_type);
  1036. if (!arg_obj)
  1037. return -ENOENT;
  1038. ret = kms->funcs->register_events(kms, arg_obj, req->event, en);
  1039. drm_mode_object_put(arg_obj);
  1040. return ret;
  1041. }
  1042. static int msm_event_client_count(struct drm_device *dev,
  1043. struct drm_msm_event_req *req_event, bool locked)
  1044. {
  1045. struct msm_drm_private *priv = dev->dev_private;
  1046. unsigned long flag = 0;
  1047. struct msm_drm_event *node;
  1048. int count = 0;
  1049. if (!locked)
  1050. spin_lock_irqsave(&dev->event_lock, flag);
  1051. list_for_each_entry(node, &priv->client_event_list, base.link) {
  1052. if (node->event.type == req_event->event &&
  1053. node->info.object_id == req_event->object_id)
  1054. count++;
  1055. }
  1056. if (!locked)
  1057. spin_unlock_irqrestore(&dev->event_lock, flag);
  1058. return count;
  1059. }
  1060. static int msm_ioctl_register_event(struct drm_device *dev, void *data,
  1061. struct drm_file *file)
  1062. {
  1063. struct msm_drm_private *priv = dev->dev_private;
  1064. struct drm_msm_event_req *req_event = data;
  1065. struct msm_drm_event *client, *node;
  1066. unsigned long flag = 0;
  1067. bool dup_request = false;
  1068. int ret = 0, count = 0;
  1069. ret = msm_drm_object_supports_event(dev, req_event);
  1070. if (ret) {
  1071. DRM_ERROR("unsupported event %x object %x object id %d\n",
  1072. req_event->event, req_event->object_type,
  1073. req_event->object_id);
  1074. return ret;
  1075. }
  1076. spin_lock_irqsave(&dev->event_lock, flag);
  1077. list_for_each_entry(node, &priv->client_event_list, base.link) {
  1078. if (node->base.file_priv != file)
  1079. continue;
  1080. if (node->event.type == req_event->event &&
  1081. node->info.object_id == req_event->object_id) {
  1082. DRM_DEBUG("duplicate request for event %x obj id %d\n",
  1083. node->event.type, node->info.object_id);
  1084. dup_request = true;
  1085. break;
  1086. }
  1087. }
  1088. spin_unlock_irqrestore(&dev->event_lock, flag);
  1089. if (dup_request)
  1090. return -EALREADY;
  1091. client = kzalloc(sizeof(*client), GFP_KERNEL);
  1092. if (!client)
  1093. return -ENOMEM;
  1094. client->base.file_priv = file;
  1095. client->base.event = &client->event;
  1096. client->event.type = req_event->event;
  1097. memcpy(&client->info, req_event, sizeof(client->info));
  1098. /* Get the count of clients that have registered for event.
  1099. * Event should be enabled for first client, for subsequent enable
  1100. * calls add to client list and return.
  1101. */
  1102. count = msm_event_client_count(dev, req_event, false);
  1103. /* Add current client to list */
  1104. spin_lock_irqsave(&dev->event_lock, flag);
  1105. list_add_tail(&client->base.link, &priv->client_event_list);
  1106. spin_unlock_irqrestore(&dev->event_lock, flag);
  1107. if (count)
  1108. return 0;
  1109. ret = msm_register_event(dev, req_event, file, true);
  1110. if (ret) {
  1111. DRM_ERROR("failed to enable event %x object %x object id %d\n",
  1112. req_event->event, req_event->object_type,
  1113. req_event->object_id);
  1114. spin_lock_irqsave(&dev->event_lock, flag);
  1115. list_del(&client->base.link);
  1116. spin_unlock_irqrestore(&dev->event_lock, flag);
  1117. kfree(client);
  1118. }
  1119. return ret;
  1120. }
  1121. static int msm_ioctl_deregister_event(struct drm_device *dev, void *data,
  1122. struct drm_file *file)
  1123. {
  1124. struct msm_drm_private *priv = dev->dev_private;
  1125. struct drm_msm_event_req *req_event = data;
  1126. struct msm_drm_event *client = NULL, *node, *temp;
  1127. unsigned long flag = 0;
  1128. int count = 0;
  1129. bool found = false;
  1130. int ret = 0;
  1131. ret = msm_drm_object_supports_event(dev, req_event);
  1132. if (ret) {
  1133. DRM_ERROR("unsupported event %x object %x object id %d\n",
  1134. req_event->event, req_event->object_type,
  1135. req_event->object_id);
  1136. return ret;
  1137. }
  1138. spin_lock_irqsave(&dev->event_lock, flag);
  1139. list_for_each_entry_safe(node, temp, &priv->client_event_list,
  1140. base.link) {
  1141. if (node->event.type == req_event->event &&
  1142. node->info.object_id == req_event->object_id &&
  1143. node->base.file_priv == file) {
  1144. client = node;
  1145. list_del(&client->base.link);
  1146. found = true;
  1147. kfree(client);
  1148. break;
  1149. }
  1150. }
  1151. spin_unlock_irqrestore(&dev->event_lock, flag);
  1152. if (!found)
  1153. return -ENOENT;
  1154. count = msm_event_client_count(dev, req_event, false);
  1155. if (!count)
  1156. ret = msm_register_event(dev, req_event, file, false);
  1157. return ret;
  1158. }
  1159. void msm_mode_object_event_notify(struct drm_mode_object *obj,
  1160. struct drm_device *dev, struct drm_event *event, u8 *payload)
  1161. {
  1162. struct msm_drm_private *priv = NULL;
  1163. unsigned long flags;
  1164. struct msm_drm_event *notify, *node;
  1165. int len = 0, ret;
  1166. if (!obj || !event || !event->length || !payload) {
  1167. DRM_ERROR("err param obj %pK event %pK len %d payload %pK\n",
  1168. obj, event, ((event) ? (event->length) : -1),
  1169. payload);
  1170. return;
  1171. }
  1172. priv = (dev) ? dev->dev_private : NULL;
  1173. if (!dev || !priv) {
  1174. DRM_ERROR("invalid dev %pK priv %pK\n", dev, priv);
  1175. return;
  1176. }
  1177. spin_lock_irqsave(&dev->event_lock, flags);
  1178. list_for_each_entry(node, &priv->client_event_list, base.link) {
  1179. if (node->event.type != event->type ||
  1180. obj->id != node->info.object_id)
  1181. continue;
  1182. len = event->length + sizeof(struct msm_drm_event);
  1183. if (node->base.file_priv->event_space < len) {
  1184. DRM_ERROR("Insufficient space %d for event %x len %d\n",
  1185. node->base.file_priv->event_space, event->type,
  1186. len);
  1187. continue;
  1188. }
  1189. notify = kzalloc(len, GFP_ATOMIC);
  1190. if (!notify)
  1191. continue;
  1192. notify->base.file_priv = node->base.file_priv;
  1193. notify->base.event = &notify->event;
  1194. notify->event.type = node->event.type;
  1195. notify->event.length = event->length +
  1196. sizeof(struct drm_msm_event_resp);
  1197. memcpy(&notify->info, &node->info, sizeof(notify->info));
  1198. memcpy(notify->data, payload, event->length);
  1199. ret = drm_event_reserve_init_locked(dev, node->base.file_priv,
  1200. &notify->base, &notify->event);
  1201. if (ret) {
  1202. kfree(notify);
  1203. continue;
  1204. }
  1205. drm_send_event_locked(dev, &notify->base);
  1206. }
  1207. spin_unlock_irqrestore(&dev->event_lock, flags);
  1208. }
  1209. static int msm_release(struct inode *inode, struct file *filp)
  1210. {
  1211. struct drm_file *file_priv = filp->private_data;
  1212. struct drm_minor *minor = file_priv->minor;
  1213. struct drm_device *dev = minor->dev;
  1214. struct msm_drm_private *priv = dev->dev_private;
  1215. struct msm_drm_event *node, *temp, *tmp_node;
  1216. u32 count;
  1217. unsigned long flags;
  1218. LIST_HEAD(tmp_head);
  1219. spin_lock_irqsave(&dev->event_lock, flags);
  1220. list_for_each_entry_safe(node, temp, &priv->client_event_list,
  1221. base.link) {
  1222. if (node->base.file_priv != file_priv)
  1223. continue;
  1224. list_del(&node->base.link);
  1225. list_add_tail(&node->base.link, &tmp_head);
  1226. }
  1227. spin_unlock_irqrestore(&dev->event_lock, flags);
  1228. list_for_each_entry_safe(node, temp, &tmp_head,
  1229. base.link) {
  1230. list_del(&node->base.link);
  1231. count = msm_event_client_count(dev, &node->info, false);
  1232. list_for_each_entry(tmp_node, &tmp_head, base.link) {
  1233. if (tmp_node->event.type == node->info.event &&
  1234. tmp_node->info.object_id ==
  1235. node->info.object_id)
  1236. count++;
  1237. }
  1238. if (!count)
  1239. msm_register_event(dev, &node->info, file_priv, false);
  1240. kfree(node);
  1241. }
  1242. return drm_release(inode, filp);
  1243. }
  1244. /**
  1245. * msm_ioctl_rmfb2 - remove an FB from the configuration
  1246. * @dev: drm device for the ioctl
  1247. * @data: data pointer for the ioctl
  1248. * @file_priv: drm file for the ioctl call
  1249. *
  1250. * Remove the FB specified by the user.
  1251. *
  1252. * Called by the user via ioctl.
  1253. *
  1254. * Returns:
  1255. * Zero on success, negative errno on failure.
  1256. */
  1257. int msm_ioctl_rmfb2(struct drm_device *dev, void *data,
  1258. struct drm_file *file_priv)
  1259. {
  1260. struct drm_framebuffer *fb = NULL;
  1261. struct drm_framebuffer *fbl = NULL;
  1262. uint32_t *id = data;
  1263. int found = 0;
  1264. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  1265. return -EINVAL;
  1266. fb = drm_framebuffer_lookup(dev, file_priv, *id);
  1267. if (!fb)
  1268. return -ENOENT;
  1269. /* drop extra ref from traversing drm_framebuffer_lookup */
  1270. drm_framebuffer_put(fb);
  1271. mutex_lock(&file_priv->fbs_lock);
  1272. list_for_each_entry(fbl, &file_priv->fbs, filp_head)
  1273. if (fb == fbl)
  1274. found = 1;
  1275. if (!found) {
  1276. mutex_unlock(&file_priv->fbs_lock);
  1277. return -ENOENT;
  1278. }
  1279. list_del_init(&fb->filp_head);
  1280. mutex_unlock(&file_priv->fbs_lock);
  1281. drm_framebuffer_put(fb);
  1282. return 0;
  1283. }
  1284. EXPORT_SYMBOL(msm_ioctl_rmfb2);
  1285. /**
  1286. * msm_ioctl_power_ctrl - enable/disable power vote on MDSS Hw
  1287. * @dev: drm device for the ioctl
  1288. * @data: data pointer for the ioctl
  1289. * @file_priv: drm file for the ioctl call
  1290. *
  1291. */
  1292. int msm_ioctl_power_ctrl(struct drm_device *dev, void *data,
  1293. struct drm_file *file_priv)
  1294. {
  1295. struct msm_file_private *ctx = file_priv->driver_priv;
  1296. struct msm_drm_private *priv;
  1297. struct drm_msm_power_ctrl *power_ctrl = data;
  1298. bool vote_req = false;
  1299. int old_cnt;
  1300. int rc = 0;
  1301. if (unlikely(!power_ctrl)) {
  1302. DRM_ERROR("invalid ioctl data\n");
  1303. return -EINVAL;
  1304. }
  1305. priv = dev->dev_private;
  1306. mutex_lock(&ctx->power_lock);
  1307. old_cnt = ctx->enable_refcnt;
  1308. if (power_ctrl->enable) {
  1309. if (!ctx->enable_refcnt)
  1310. vote_req = true;
  1311. ctx->enable_refcnt++;
  1312. } else if (ctx->enable_refcnt) {
  1313. ctx->enable_refcnt--;
  1314. if (!ctx->enable_refcnt)
  1315. vote_req = true;
  1316. } else {
  1317. pr_err("ignoring, unbalanced disable\n");
  1318. }
  1319. if (vote_req) {
  1320. if (power_ctrl->enable)
  1321. rc = pm_runtime_get_sync(dev->dev);
  1322. else
  1323. pm_runtime_put_sync(dev->dev);
  1324. if (rc < 0)
  1325. ctx->enable_refcnt = old_cnt;
  1326. }
  1327. pr_debug("pid %d enable %d, refcnt %d, vote_req %d\n",
  1328. current->pid, power_ctrl->enable, ctx->enable_refcnt,
  1329. vote_req);
  1330. SDE_EVT32(current->pid, power_ctrl->enable, ctx->enable_refcnt,
  1331. vote_req);
  1332. mutex_unlock(&ctx->power_lock);
  1333. return rc;
  1334. }
  1335. static const struct drm_ioctl_desc msm_ioctls[] = {
  1336. DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
  1337. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
  1338. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
  1339. DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
  1340. DRM_IOCTL_DEF_DRV(SDE_WB_CONFIG, sde_wb_config, DRM_UNLOCKED|DRM_AUTH),
  1341. DRM_IOCTL_DEF_DRV(MSM_REGISTER_EVENT, msm_ioctl_register_event,
  1342. DRM_UNLOCKED),
  1343. DRM_IOCTL_DEF_DRV(MSM_DEREGISTER_EVENT, msm_ioctl_deregister_event,
  1344. DRM_UNLOCKED),
  1345. DRM_IOCTL_DEF_DRV(MSM_RMFB2, msm_ioctl_rmfb2, DRM_UNLOCKED),
  1346. DRM_IOCTL_DEF_DRV(MSM_POWER_CTRL, msm_ioctl_power_ctrl,
  1347. DRM_RENDER_ALLOW),
  1348. };
  1349. static const struct vm_operations_struct vm_ops = {
  1350. .fault = msm_gem_fault,
  1351. .open = drm_gem_vm_open,
  1352. .close = drm_gem_vm_close,
  1353. };
  1354. static const struct file_operations fops = {
  1355. .owner = THIS_MODULE,
  1356. .open = drm_open,
  1357. .release = msm_release,
  1358. .unlocked_ioctl = drm_ioctl,
  1359. .compat_ioctl = drm_compat_ioctl,
  1360. .poll = drm_poll,
  1361. .read = drm_read,
  1362. .llseek = no_llseek,
  1363. .mmap = msm_gem_mmap,
  1364. };
  1365. static struct drm_driver msm_driver = {
  1366. .driver_features = DRIVER_HAVE_IRQ |
  1367. DRIVER_GEM |
  1368. DRIVER_PRIME |
  1369. DRIVER_RENDER |
  1370. DRIVER_ATOMIC |
  1371. DRIVER_MODESET,
  1372. .open = msm_open,
  1373. .preclose = msm_preclose,
  1374. .postclose = msm_postclose,
  1375. .lastclose = msm_lastclose,
  1376. .irq_handler = msm_irq,
  1377. .irq_preinstall = msm_irq_preinstall,
  1378. .irq_postinstall = msm_irq_postinstall,
  1379. .irq_uninstall = msm_irq_uninstall,
  1380. .enable_vblank = msm_enable_vblank,
  1381. .disable_vblank = msm_disable_vblank,
  1382. .gem_free_object = msm_gem_free_object,
  1383. .gem_vm_ops = &vm_ops,
  1384. .dumb_create = msm_gem_dumb_create,
  1385. .dumb_map_offset = msm_gem_dumb_map_offset,
  1386. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  1387. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  1388. .gem_prime_export = drm_gem_prime_export,
  1389. .gem_prime_import = msm_gem_prime_import,
  1390. .gem_prime_res_obj = msm_gem_prime_res_obj,
  1391. .gem_prime_pin = msm_gem_prime_pin,
  1392. .gem_prime_unpin = msm_gem_prime_unpin,
  1393. .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
  1394. .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
  1395. .gem_prime_vmap = msm_gem_prime_vmap,
  1396. .gem_prime_vunmap = msm_gem_prime_vunmap,
  1397. .gem_prime_mmap = msm_gem_prime_mmap,
  1398. .ioctls = msm_ioctls,
  1399. .num_ioctls = ARRAY_SIZE(msm_ioctls),
  1400. .fops = &fops,
  1401. .name = "msm_drm",
  1402. .desc = "MSM Snapdragon DRM",
  1403. .date = "20130625",
  1404. .major = MSM_VERSION_MAJOR,
  1405. .minor = MSM_VERSION_MINOR,
  1406. .patchlevel = MSM_VERSION_PATCHLEVEL,
  1407. };
  1408. #ifdef CONFIG_PM_SLEEP
  1409. static int msm_pm_suspend(struct device *dev)
  1410. {
  1411. struct drm_device *ddev;
  1412. struct msm_drm_private *priv;
  1413. struct msm_kms *kms;
  1414. if (!dev)
  1415. return -EINVAL;
  1416. ddev = dev_get_drvdata(dev);
  1417. if (!ddev || !ddev->dev_private)
  1418. return -EINVAL;
  1419. priv = ddev->dev_private;
  1420. kms = priv->kms;
  1421. if (kms && kms->funcs && kms->funcs->pm_suspend)
  1422. return kms->funcs->pm_suspend(dev);
  1423. /* disable hot-plug polling */
  1424. drm_kms_helper_poll_disable(ddev);
  1425. return 0;
  1426. }
  1427. static int msm_pm_resume(struct device *dev)
  1428. {
  1429. struct drm_device *ddev;
  1430. struct msm_drm_private *priv;
  1431. struct msm_kms *kms;
  1432. if (!dev)
  1433. return -EINVAL;
  1434. ddev = dev_get_drvdata(dev);
  1435. if (!ddev || !ddev->dev_private)
  1436. return -EINVAL;
  1437. priv = ddev->dev_private;
  1438. kms = priv->kms;
  1439. if (kms && kms->funcs && kms->funcs->pm_resume)
  1440. return kms->funcs->pm_resume(dev);
  1441. /* enable hot-plug polling */
  1442. drm_kms_helper_poll_enable(ddev);
  1443. return 0;
  1444. }
  1445. #endif
  1446. #ifdef CONFIG_PM
  1447. static int msm_runtime_suspend(struct device *dev)
  1448. {
  1449. struct drm_device *ddev = dev_get_drvdata(dev);
  1450. struct msm_drm_private *priv = ddev->dev_private;
  1451. DBG("");
  1452. if (priv->mdss)
  1453. msm_mdss_disable(priv->mdss);
  1454. else
  1455. sde_power_resource_enable(&priv->phandle, false);
  1456. return 0;
  1457. }
  1458. static int msm_runtime_resume(struct device *dev)
  1459. {
  1460. struct drm_device *ddev = dev_get_drvdata(dev);
  1461. struct msm_drm_private *priv = ddev->dev_private;
  1462. int ret;
  1463. DBG("");
  1464. if (priv->mdss)
  1465. ret = msm_mdss_enable(priv->mdss);
  1466. else
  1467. ret = sde_power_resource_enable(&priv->phandle, true);
  1468. return ret;
  1469. }
  1470. #endif
  1471. static const struct dev_pm_ops msm_pm_ops = {
  1472. SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
  1473. SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
  1474. };
  1475. /*
  1476. * Componentized driver support:
  1477. */
  1478. /*
  1479. * NOTE: duplication of the same code as exynos or imx (or probably any other).
  1480. * so probably some room for some helpers
  1481. */
  1482. static int compare_of(struct device *dev, void *data)
  1483. {
  1484. return dev->of_node == data;
  1485. }
  1486. /*
  1487. * Identify what components need to be added by parsing what remote-endpoints
  1488. * our MDP output ports are connected to. In the case of LVDS on MDP4, there
  1489. * is no external component that we need to add since LVDS is within MDP4
  1490. * itself.
  1491. */
  1492. static int add_components_mdp(struct device *mdp_dev,
  1493. struct component_match **matchptr)
  1494. {
  1495. struct device_node *np = mdp_dev->of_node;
  1496. struct device_node *ep_node;
  1497. struct device *master_dev;
  1498. /*
  1499. * on MDP4 based platforms, the MDP platform device is the component
  1500. * master that adds other display interface components to itself.
  1501. *
  1502. * on MDP5 based platforms, the MDSS platform device is the component
  1503. * master that adds MDP5 and other display interface components to
  1504. * itself.
  1505. */
  1506. if (of_device_is_compatible(np, "qcom,mdp4"))
  1507. master_dev = mdp_dev;
  1508. else
  1509. master_dev = mdp_dev->parent;
  1510. for_each_endpoint_of_node(np, ep_node) {
  1511. struct device_node *intf;
  1512. struct of_endpoint ep;
  1513. int ret;
  1514. ret = of_graph_parse_endpoint(ep_node, &ep);
  1515. if (ret) {
  1516. dev_err(mdp_dev, "unable to parse port endpoint\n");
  1517. of_node_put(ep_node);
  1518. return ret;
  1519. }
  1520. /*
  1521. * The LCDC/LVDS port on MDP4 is a speacial case where the
  1522. * remote-endpoint isn't a component that we need to add
  1523. */
  1524. if (of_device_is_compatible(np, "qcom,mdp4") &&
  1525. ep.port == 0)
  1526. continue;
  1527. /*
  1528. * It's okay if some of the ports don't have a remote endpoint
  1529. * specified. It just means that the port isn't connected to
  1530. * any external interface.
  1531. */
  1532. intf = of_graph_get_remote_port_parent(ep_node);
  1533. if (!intf)
  1534. continue;
  1535. if (of_device_is_available(intf))
  1536. drm_of_component_match_add(master_dev, matchptr,
  1537. compare_of, intf);
  1538. of_node_put(intf);
  1539. }
  1540. return 0;
  1541. }
  1542. static int compare_name_mdp(struct device *dev, void *data)
  1543. {
  1544. return (strnstr(dev_name(dev), "mdp", strlen("mdp")) != NULL);
  1545. }
  1546. static int add_display_components(struct device *dev,
  1547. struct component_match **matchptr)
  1548. {
  1549. struct device *mdp_dev = NULL;
  1550. struct device_node *node;
  1551. int ret;
  1552. if (of_device_is_compatible(dev->of_node, "qcom,sde-kms")) {
  1553. struct device_node *np = dev->of_node;
  1554. unsigned int i;
  1555. for (i = 0; ; i++) {
  1556. node = of_parse_phandle(np, "connectors", i);
  1557. if (!node)
  1558. break;
  1559. component_match_add(dev, matchptr, compare_of, node);
  1560. }
  1561. return 0;
  1562. }
  1563. /*
  1564. * MDP5 based devices don't have a flat hierarchy. There is a top level
  1565. * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
  1566. * children devices, find the MDP5 node, and then add the interfaces
  1567. * to our components list.
  1568. */
  1569. if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {
  1570. ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
  1571. if (ret) {
  1572. dev_err(dev, "failed to populate children devices\n");
  1573. return ret;
  1574. }
  1575. mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
  1576. if (!mdp_dev) {
  1577. dev_err(dev, "failed to find MDSS MDP node\n");
  1578. of_platform_depopulate(dev);
  1579. return -ENODEV;
  1580. }
  1581. put_device(mdp_dev);
  1582. /* add the MDP component itself */
  1583. component_match_add(dev, matchptr, compare_of,
  1584. mdp_dev->of_node);
  1585. } else {
  1586. /* MDP4 */
  1587. mdp_dev = dev;
  1588. }
  1589. ret = add_components_mdp(mdp_dev, matchptr);
  1590. if (ret)
  1591. of_platform_depopulate(dev);
  1592. return ret;
  1593. }
  1594. struct msm_gem_address_space *
  1595. msm_gem_smmu_address_space_get(struct drm_device *dev,
  1596. unsigned int domain)
  1597. {
  1598. struct msm_drm_private *priv = NULL;
  1599. struct msm_kms *kms;
  1600. const struct msm_kms_funcs *funcs;
  1601. if ((!dev) || (!dev->dev_private))
  1602. return NULL;
  1603. priv = dev->dev_private;
  1604. kms = priv->kms;
  1605. if (!kms)
  1606. return NULL;
  1607. funcs = kms->funcs;
  1608. if ((!funcs) || (!funcs->get_address_space))
  1609. return NULL;
  1610. return funcs->get_address_space(priv->kms, domain);
  1611. }
  1612. static int msm_drm_bind(struct device *dev)
  1613. {
  1614. return msm_drm_init(dev, &msm_driver);
  1615. }
  1616. static void msm_drm_unbind(struct device *dev)
  1617. {
  1618. msm_drm_uninit(dev);
  1619. }
  1620. static const struct component_master_ops msm_drm_ops = {
  1621. .bind = msm_drm_bind,
  1622. .unbind = msm_drm_unbind,
  1623. };
  1624. /*
  1625. * Platform driver:
  1626. */
  1627. static int msm_pdev_probe(struct platform_device *pdev)
  1628. {
  1629. int ret;
  1630. struct component_match *match = NULL;
  1631. ret = add_display_components(&pdev->dev, &match);
  1632. if (ret)
  1633. return ret;
  1634. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  1635. return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
  1636. }
  1637. static int msm_pdev_remove(struct platform_device *pdev)
  1638. {
  1639. component_master_del(&pdev->dev, &msm_drm_ops);
  1640. of_platform_depopulate(&pdev->dev);
  1641. msm_drm_unbind(&pdev->dev);
  1642. component_master_del(&pdev->dev, &msm_drm_ops);
  1643. return 0;
  1644. }
  1645. static void msm_pdev_shutdown(struct platform_device *pdev)
  1646. {
  1647. struct drm_device *ddev = platform_get_drvdata(pdev);
  1648. struct msm_drm_private *priv = NULL;
  1649. if (!ddev) {
  1650. DRM_ERROR("invalid drm device node\n");
  1651. return;
  1652. }
  1653. priv = ddev->dev_private;
  1654. if (!priv) {
  1655. DRM_ERROR("invalid msm drm private node\n");
  1656. return;
  1657. }
  1658. msm_lastclose(ddev);
  1659. /* set this after lastclose to allow kickoff from lastclose */
  1660. priv->shutdown_in_progress = true;
  1661. }
  1662. static const struct of_device_id dt_match[] = {
  1663. { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
  1664. { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
  1665. { .compatible = "qcom,sde-kms", .data = (void *)KMS_SDE },
  1666. {},
  1667. };
  1668. MODULE_DEVICE_TABLE(of, dt_match);
  1669. static struct platform_driver msm_platform_driver = {
  1670. .probe = msm_pdev_probe,
  1671. .remove = msm_pdev_remove,
  1672. .shutdown = msm_pdev_shutdown,
  1673. .driver = {
  1674. .name = "msm_drm",
  1675. .of_match_table = dt_match,
  1676. .pm = &msm_pm_ops,
  1677. .suppress_bind_attrs = true,
  1678. },
  1679. };
  1680. #ifdef CONFIG_QCOM_KGSL
  1681. void __init adreno_register(void)
  1682. {
  1683. }
  1684. void __exit adreno_unregister(void)
  1685. {
  1686. }
  1687. #endif
  1688. static int __init msm_drm_register(void)
  1689. {
  1690. if (!modeset)
  1691. return -EINVAL;
  1692. DBG("init");
  1693. msm_smmu_driver_init();
  1694. msm_dsi_register();
  1695. msm_edp_register();
  1696. msm_hdmi_register();
  1697. adreno_register();
  1698. return platform_driver_register(&msm_platform_driver);
  1699. }
  1700. static void __exit msm_drm_unregister(void)
  1701. {
  1702. DBG("fini");
  1703. platform_driver_unregister(&msm_platform_driver);
  1704. msm_hdmi_unregister();
  1705. adreno_unregister();
  1706. msm_edp_unregister();
  1707. msm_dsi_unregister();
  1708. msm_smmu_driver_cleanup();
  1709. }
  1710. module_init(msm_drm_register);
  1711. module_exit(msm_drm_unregister);
  1712. MODULE_AUTHOR("Rob Clark <[email protected]");
  1713. MODULE_DESCRIPTION("MSM DRM Driver");
  1714. MODULE_LICENSE("GPL");