dp_tx.c 139 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef QCA_TX_LIMIT_CHECK
  71. /**
  72. * dp_tx_limit_check - Check if allocated tx descriptors reached
  73. * soc max limit and pdev max limit
  74. * @vdev: DP vdev handle
  75. *
  76. * Return: true if allocated tx descriptors reached max configured value, else
  77. * false
  78. */
  79. static inline bool
  80. dp_tx_limit_check(struct dp_vdev *vdev)
  81. {
  82. struct dp_pdev *pdev = vdev->pdev;
  83. struct dp_soc *soc = pdev->soc;
  84. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  85. soc->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  93. pdev->num_tx_allowed) {
  94. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  95. "%s: queued packets are more than max tx, drop the frame",
  96. __func__);
  97. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  98. return true;
  99. }
  100. return false;
  101. }
  102. /**
  103. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  104. * reached soc max limit
  105. * @vdev: DP vdev handle
  106. *
  107. * Return: true if allocated tx descriptors reached max configured value, else
  108. * false
  109. */
  110. static inline bool
  111. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  112. {
  113. struct dp_pdev *pdev = vdev->pdev;
  114. struct dp_soc *soc = pdev->soc;
  115. if (qdf_atomic_read(&soc->num_tx_exception) >=
  116. soc->num_msdu_exception_desc) {
  117. dp_info("exc packets are more than max drop the exc pkt");
  118. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  119. return true;
  120. }
  121. return false;
  122. }
  123. /**
  124. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  125. * @vdev: DP pdev handle
  126. *
  127. * Return: void
  128. */
  129. static inline void
  130. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  131. {
  132. struct dp_soc *soc = pdev->soc;
  133. qdf_atomic_inc(&pdev->num_tx_outstanding);
  134. qdf_atomic_inc(&soc->num_tx_outstanding);
  135. }
  136. /**
  137. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  138. * @vdev: DP pdev handle
  139. *
  140. * Return: void
  141. */
  142. static inline void
  143. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  144. {
  145. struct dp_soc *soc = pdev->soc;
  146. qdf_atomic_dec(&pdev->num_tx_outstanding);
  147. qdf_atomic_dec(&soc->num_tx_outstanding);
  148. }
  149. #else //QCA_TX_LIMIT_CHECK
  150. static inline bool
  151. dp_tx_limit_check(struct dp_vdev *vdev)
  152. {
  153. return false;
  154. }
  155. static inline bool
  156. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  157. {
  158. return false;
  159. }
  160. static inline void
  161. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  162. {
  163. qdf_atomic_inc(&pdev->num_tx_outstanding);
  164. }
  165. static inline void
  166. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  167. {
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. }
  170. #endif //QCA_TX_LIMIT_CHECK
  171. #if defined(FEATURE_TSO)
  172. /**
  173. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  174. *
  175. * @soc - core txrx main context
  176. * @seg_desc - tso segment descriptor
  177. * @num_seg_desc - tso number segment descriptor
  178. */
  179. static void dp_tx_tso_unmap_segment(
  180. struct dp_soc *soc,
  181. struct qdf_tso_seg_elem_t *seg_desc,
  182. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  183. {
  184. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  185. if (qdf_unlikely(!seg_desc)) {
  186. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  187. __func__, __LINE__);
  188. qdf_assert(0);
  189. } else if (qdf_unlikely(!num_seg_desc)) {
  190. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  191. __func__, __LINE__);
  192. qdf_assert(0);
  193. } else {
  194. bool is_last_seg;
  195. /* no tso segment left to do dma unmap */
  196. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  197. return;
  198. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  199. true : false;
  200. qdf_nbuf_unmap_tso_segment(soc->osdev,
  201. seg_desc, is_last_seg);
  202. num_seg_desc->num_seg.tso_cmn_num_seg--;
  203. }
  204. }
  205. /**
  206. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  207. * back to the freelist
  208. *
  209. * @soc - soc device handle
  210. * @tx_desc - Tx software descriptor
  211. */
  212. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  213. struct dp_tx_desc_s *tx_desc)
  214. {
  215. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  216. if (qdf_unlikely(!tx_desc->tso_desc)) {
  217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  218. "%s %d TSO desc is NULL!",
  219. __func__, __LINE__);
  220. qdf_assert(0);
  221. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  222. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  223. "%s %d TSO num desc is NULL!",
  224. __func__, __LINE__);
  225. qdf_assert(0);
  226. } else {
  227. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  228. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  229. /* Add the tso num segment into the free list */
  230. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  231. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  232. tx_desc->tso_num_desc);
  233. tx_desc->tso_num_desc = NULL;
  234. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  235. }
  236. /* Add the tso segment into the free list*/
  237. dp_tx_tso_desc_free(soc,
  238. tx_desc->pool_id, tx_desc->tso_desc);
  239. tx_desc->tso_desc = NULL;
  240. }
  241. }
  242. #else
  243. static void dp_tx_tso_unmap_segment(
  244. struct dp_soc *soc,
  245. struct qdf_tso_seg_elem_t *seg_desc,
  246. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  247. {
  248. }
  249. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  250. struct dp_tx_desc_s *tx_desc)
  251. {
  252. }
  253. #endif
  254. /**
  255. * dp_tx_desc_release() - Release Tx Descriptor
  256. * @tx_desc : Tx Descriptor
  257. * @desc_pool_id: Descriptor Pool ID
  258. *
  259. * Deallocate all resources attached to Tx descriptor and free the Tx
  260. * descriptor.
  261. *
  262. * Return:
  263. */
  264. static void
  265. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  266. {
  267. struct dp_pdev *pdev = tx_desc->pdev;
  268. struct dp_soc *soc;
  269. uint8_t comp_status = 0;
  270. qdf_assert(pdev);
  271. soc = pdev->soc;
  272. dp_tx_outstanding_dec(pdev);
  273. if (tx_desc->frm_type == dp_tx_frm_tso)
  274. dp_tx_tso_desc_release(soc, tx_desc);
  275. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  276. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  277. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  278. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  279. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  280. qdf_atomic_dec(&soc->num_tx_exception);
  281. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  282. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  283. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  284. soc->hal_soc);
  285. else
  286. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  287. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  288. "Tx Completion Release desc %d status %d outstanding %d",
  289. tx_desc->id, comp_status,
  290. qdf_atomic_read(&pdev->num_tx_outstanding));
  291. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  292. return;
  293. }
  294. /**
  295. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  296. * @vdev: DP vdev Handle
  297. * @nbuf: skb
  298. * @msdu_info: msdu_info required to create HTT metadata
  299. *
  300. * Prepares and fills HTT metadata in the frame pre-header for special frames
  301. * that should be transmitted using varying transmit parameters.
  302. * There are 2 VDEV modes that currently needs this special metadata -
  303. * 1) Mesh Mode
  304. * 2) DSRC Mode
  305. *
  306. * Return: HTT metadata size
  307. *
  308. */
  309. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  310. struct dp_tx_msdu_info_s *msdu_info)
  311. {
  312. uint32_t *meta_data = msdu_info->meta_data;
  313. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  314. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  315. uint8_t htt_desc_size;
  316. /* Size rounded of multiple of 8 bytes */
  317. uint8_t htt_desc_size_aligned;
  318. uint8_t *hdr = NULL;
  319. /*
  320. * Metadata - HTT MSDU Extension header
  321. */
  322. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  323. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  324. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  325. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  326. meta_data[0])) {
  327. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  328. htt_desc_size_aligned)) {
  329. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  330. htt_desc_size_aligned);
  331. if (!nbuf) {
  332. /*
  333. * qdf_nbuf_realloc_headroom won't do skb_clone
  334. * as skb_realloc_headroom does. so, no free is
  335. * needed here.
  336. */
  337. DP_STATS_INC(vdev,
  338. tx_i.dropped.headroom_insufficient,
  339. 1);
  340. qdf_print(" %s[%d] skb_realloc_headroom failed",
  341. __func__, __LINE__);
  342. return 0;
  343. }
  344. }
  345. /* Fill and add HTT metaheader */
  346. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  347. if (!hdr) {
  348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  349. "Error in filling HTT metadata");
  350. return 0;
  351. }
  352. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  353. } else if (vdev->opmode == wlan_op_mode_ocb) {
  354. /* Todo - Add support for DSRC */
  355. }
  356. return htt_desc_size_aligned;
  357. }
  358. /**
  359. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  360. * @tso_seg: TSO segment to process
  361. * @ext_desc: Pointer to MSDU extension descriptor
  362. *
  363. * Return: void
  364. */
  365. #if defined(FEATURE_TSO)
  366. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  367. void *ext_desc)
  368. {
  369. uint8_t num_frag;
  370. uint32_t tso_flags;
  371. /*
  372. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  373. * tcp_flag_mask
  374. *
  375. * Checksum enable flags are set in TCL descriptor and not in Extension
  376. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  377. */
  378. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  379. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  380. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  381. tso_seg->tso_flags.ip_len);
  382. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  383. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  384. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  385. uint32_t lo = 0;
  386. uint32_t hi = 0;
  387. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  388. (tso_seg->tso_frags[num_frag].length));
  389. qdf_dmaaddr_to_32s(
  390. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  391. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  392. tso_seg->tso_frags[num_frag].length);
  393. }
  394. return;
  395. }
  396. #else
  397. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  398. void *ext_desc)
  399. {
  400. return;
  401. }
  402. #endif
  403. #if defined(FEATURE_TSO)
  404. /**
  405. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  406. * allocated and free them
  407. *
  408. * @soc: soc handle
  409. * @free_seg: list of tso segments
  410. * @msdu_info: msdu descriptor
  411. *
  412. * Return - void
  413. */
  414. static void dp_tx_free_tso_seg_list(
  415. struct dp_soc *soc,
  416. struct qdf_tso_seg_elem_t *free_seg,
  417. struct dp_tx_msdu_info_s *msdu_info)
  418. {
  419. struct qdf_tso_seg_elem_t *next_seg;
  420. while (free_seg) {
  421. next_seg = free_seg->next;
  422. dp_tx_tso_desc_free(soc,
  423. msdu_info->tx_queue.desc_pool_id,
  424. free_seg);
  425. free_seg = next_seg;
  426. }
  427. }
  428. /**
  429. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  430. * allocated and free them
  431. *
  432. * @soc: soc handle
  433. * @free_num_seg: list of tso number segments
  434. * @msdu_info: msdu descriptor
  435. * Return - void
  436. */
  437. static void dp_tx_free_tso_num_seg_list(
  438. struct dp_soc *soc,
  439. struct qdf_tso_num_seg_elem_t *free_num_seg,
  440. struct dp_tx_msdu_info_s *msdu_info)
  441. {
  442. struct qdf_tso_num_seg_elem_t *next_num_seg;
  443. while (free_num_seg) {
  444. next_num_seg = free_num_seg->next;
  445. dp_tso_num_seg_free(soc,
  446. msdu_info->tx_queue.desc_pool_id,
  447. free_num_seg);
  448. free_num_seg = next_num_seg;
  449. }
  450. }
  451. /**
  452. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  453. * do dma unmap for each segment
  454. *
  455. * @soc: soc handle
  456. * @free_seg: list of tso segments
  457. * @num_seg_desc: tso number segment descriptor
  458. *
  459. * Return - void
  460. */
  461. static void dp_tx_unmap_tso_seg_list(
  462. struct dp_soc *soc,
  463. struct qdf_tso_seg_elem_t *free_seg,
  464. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  465. {
  466. struct qdf_tso_seg_elem_t *next_seg;
  467. if (qdf_unlikely(!num_seg_desc)) {
  468. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  469. return;
  470. }
  471. while (free_seg) {
  472. next_seg = free_seg->next;
  473. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  474. free_seg = next_seg;
  475. }
  476. }
  477. #ifdef FEATURE_TSO_STATS
  478. /**
  479. * dp_tso_get_stats_idx: Retrieve the tso packet id
  480. * @pdev - pdev handle
  481. *
  482. * Return: id
  483. */
  484. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  485. {
  486. uint32_t stats_idx;
  487. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  488. % CDP_MAX_TSO_PACKETS);
  489. return stats_idx;
  490. }
  491. #else
  492. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  493. {
  494. return 0;
  495. }
  496. #endif /* FEATURE_TSO_STATS */
  497. /**
  498. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  499. * free the tso segments descriptor and
  500. * tso num segments descriptor
  501. *
  502. * @soc: soc handle
  503. * @msdu_info: msdu descriptor
  504. * @tso_seg_unmap: flag to show if dma unmap is necessary
  505. *
  506. * Return - void
  507. */
  508. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  509. struct dp_tx_msdu_info_s *msdu_info,
  510. bool tso_seg_unmap)
  511. {
  512. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  513. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  514. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  515. tso_info->tso_num_seg_list;
  516. /* do dma unmap for each segment */
  517. if (tso_seg_unmap)
  518. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  519. /* free all tso number segment descriptor though looks only have 1 */
  520. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  521. /* free all tso segment descriptor */
  522. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  523. }
  524. /**
  525. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  526. * @vdev: virtual device handle
  527. * @msdu: network buffer
  528. * @msdu_info: meta data associated with the msdu
  529. *
  530. * Return: QDF_STATUS_SUCCESS success
  531. */
  532. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  533. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  534. {
  535. struct qdf_tso_seg_elem_t *tso_seg;
  536. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  537. struct dp_soc *soc = vdev->pdev->soc;
  538. struct dp_pdev *pdev = vdev->pdev;
  539. struct qdf_tso_info_t *tso_info;
  540. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  541. tso_info = &msdu_info->u.tso_info;
  542. tso_info->curr_seg = NULL;
  543. tso_info->tso_seg_list = NULL;
  544. tso_info->num_segs = num_seg;
  545. msdu_info->frm_type = dp_tx_frm_tso;
  546. tso_info->tso_num_seg_list = NULL;
  547. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  548. while (num_seg) {
  549. tso_seg = dp_tx_tso_desc_alloc(
  550. soc, msdu_info->tx_queue.desc_pool_id);
  551. if (tso_seg) {
  552. tso_seg->next = tso_info->tso_seg_list;
  553. tso_info->tso_seg_list = tso_seg;
  554. num_seg--;
  555. } else {
  556. dp_err_rl("Failed to alloc tso seg desc");
  557. DP_STATS_INC_PKT(vdev->pdev,
  558. tso_stats.tso_no_mem_dropped, 1,
  559. qdf_nbuf_len(msdu));
  560. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  561. return QDF_STATUS_E_NOMEM;
  562. }
  563. }
  564. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  565. tso_num_seg = dp_tso_num_seg_alloc(soc,
  566. msdu_info->tx_queue.desc_pool_id);
  567. if (tso_num_seg) {
  568. tso_num_seg->next = tso_info->tso_num_seg_list;
  569. tso_info->tso_num_seg_list = tso_num_seg;
  570. } else {
  571. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  572. __func__);
  573. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  574. return QDF_STATUS_E_NOMEM;
  575. }
  576. msdu_info->num_seg =
  577. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  578. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  579. msdu_info->num_seg);
  580. if (!(msdu_info->num_seg)) {
  581. /*
  582. * Free allocated TSO seg desc and number seg desc,
  583. * do unmap for segments if dma map has done.
  584. */
  585. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  586. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  587. return QDF_STATUS_E_INVAL;
  588. }
  589. tso_info->curr_seg = tso_info->tso_seg_list;
  590. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  591. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  592. msdu, msdu_info->num_seg);
  593. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  594. tso_info->msdu_stats_idx);
  595. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  596. return QDF_STATUS_SUCCESS;
  597. }
  598. #else
  599. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  600. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  601. {
  602. return QDF_STATUS_E_NOMEM;
  603. }
  604. #endif
  605. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  606. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  607. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  608. /**
  609. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  610. * @vdev: DP Vdev handle
  611. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  612. * @desc_pool_id: Descriptor Pool ID
  613. *
  614. * Return:
  615. */
  616. static
  617. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  618. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  619. {
  620. uint8_t i;
  621. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  622. struct dp_tx_seg_info_s *seg_info;
  623. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  624. struct dp_soc *soc = vdev->pdev->soc;
  625. /* Allocate an extension descriptor */
  626. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  627. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  628. if (!msdu_ext_desc) {
  629. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  630. return NULL;
  631. }
  632. if (msdu_info->exception_fw &&
  633. qdf_unlikely(vdev->mesh_vdev)) {
  634. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  635. &msdu_info->meta_data[0],
  636. sizeof(struct htt_tx_msdu_desc_ext2_t));
  637. qdf_atomic_inc(&soc->num_tx_exception);
  638. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  639. }
  640. switch (msdu_info->frm_type) {
  641. case dp_tx_frm_sg:
  642. case dp_tx_frm_me:
  643. case dp_tx_frm_raw:
  644. seg_info = msdu_info->u.sg_info.curr_seg;
  645. /* Update the buffer pointers in MSDU Extension Descriptor */
  646. for (i = 0; i < seg_info->frag_cnt; i++) {
  647. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  648. seg_info->frags[i].paddr_lo,
  649. seg_info->frags[i].paddr_hi,
  650. seg_info->frags[i].len);
  651. }
  652. break;
  653. case dp_tx_frm_tso:
  654. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  655. &cached_ext_desc[0]);
  656. break;
  657. default:
  658. break;
  659. }
  660. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  661. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  662. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  663. msdu_ext_desc->vaddr);
  664. return msdu_ext_desc;
  665. }
  666. /**
  667. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  668. *
  669. * @skb: skb to be traced
  670. * @msdu_id: msdu_id of the packet
  671. * @vdev_id: vdev_id of the packet
  672. *
  673. * Return: None
  674. */
  675. #ifdef DP_DISABLE_TX_PKT_TRACE
  676. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  677. uint8_t vdev_id)
  678. {
  679. }
  680. #else
  681. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  682. uint8_t vdev_id)
  683. {
  684. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  685. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  686. DPTRACE(qdf_dp_trace_ptr(skb,
  687. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  688. QDF_TRACE_DEFAULT_PDEV_ID,
  689. qdf_nbuf_data_addr(skb),
  690. sizeof(qdf_nbuf_data(skb)),
  691. msdu_id, vdev_id));
  692. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  693. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  694. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  695. msdu_id, QDF_TX));
  696. }
  697. #endif
  698. /**
  699. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  700. * @vdev: DP vdev handle
  701. * @nbuf: skb
  702. * @desc_pool_id: Descriptor pool ID
  703. * @meta_data: Metadata to the fw
  704. * @tx_exc_metadata: Handle that holds exception path metadata
  705. * Allocate and prepare Tx descriptor with msdu information.
  706. *
  707. * Return: Pointer to Tx Descriptor on success,
  708. * NULL on failure
  709. */
  710. static
  711. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  712. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  713. struct dp_tx_msdu_info_s *msdu_info,
  714. struct cdp_tx_exception_metadata *tx_exc_metadata)
  715. {
  716. uint8_t align_pad;
  717. uint8_t is_exception = 0;
  718. uint8_t htt_hdr_size;
  719. struct dp_tx_desc_s *tx_desc;
  720. struct dp_pdev *pdev = vdev->pdev;
  721. struct dp_soc *soc = pdev->soc;
  722. if (dp_tx_limit_check(vdev))
  723. return NULL;
  724. /* Allocate software Tx descriptor */
  725. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  726. if (qdf_unlikely(!tx_desc)) {
  727. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  728. return NULL;
  729. }
  730. dp_tx_outstanding_inc(pdev);
  731. /* Initialize the SW tx descriptor */
  732. tx_desc->nbuf = nbuf;
  733. tx_desc->frm_type = dp_tx_frm_std;
  734. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  735. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  736. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  737. tx_desc->vdev_id = vdev->vdev_id;
  738. tx_desc->pdev = pdev;
  739. tx_desc->msdu_ext_desc = NULL;
  740. tx_desc->pkt_offset = 0;
  741. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  742. if (qdf_unlikely(vdev->multipass_en)) {
  743. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  744. goto failure;
  745. }
  746. /*
  747. * For special modes (vdev_type == ocb or mesh), data frames should be
  748. * transmitted using varying transmit parameters (tx spec) which include
  749. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  750. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  751. * These frames are sent as exception packets to firmware.
  752. *
  753. * HW requirement is that metadata should always point to a
  754. * 8-byte aligned address. So we add alignment pad to start of buffer.
  755. * HTT Metadata should be ensured to be multiple of 8-bytes,
  756. * to get 8-byte aligned start address along with align_pad added
  757. *
  758. * |-----------------------------|
  759. * | |
  760. * |-----------------------------| <-----Buffer Pointer Address given
  761. * | | ^ in HW descriptor (aligned)
  762. * | HTT Metadata | |
  763. * | | |
  764. * | | | Packet Offset given in descriptor
  765. * | | |
  766. * |-----------------------------| |
  767. * | Alignment Pad | v
  768. * |-----------------------------| <----- Actual buffer start address
  769. * | SKB Data | (Unaligned)
  770. * | |
  771. * | |
  772. * | |
  773. * | |
  774. * | |
  775. * |-----------------------------|
  776. */
  777. if (qdf_unlikely((msdu_info->exception_fw)) ||
  778. (vdev->opmode == wlan_op_mode_ocb) ||
  779. (tx_exc_metadata &&
  780. tx_exc_metadata->is_tx_sniffer)) {
  781. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  782. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  783. DP_STATS_INC(vdev,
  784. tx_i.dropped.headroom_insufficient, 1);
  785. goto failure;
  786. }
  787. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  788. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  789. "qdf_nbuf_push_head failed");
  790. goto failure;
  791. }
  792. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  793. msdu_info);
  794. if (htt_hdr_size == 0)
  795. goto failure;
  796. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  797. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  798. is_exception = 1;
  799. }
  800. #if !TQM_BYPASS_WAR
  801. if (is_exception || tx_exc_metadata)
  802. #endif
  803. {
  804. /* Temporary WAR due to TQM VP issues */
  805. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  806. qdf_atomic_inc(&soc->num_tx_exception);
  807. }
  808. return tx_desc;
  809. failure:
  810. dp_tx_desc_release(tx_desc, desc_pool_id);
  811. return NULL;
  812. }
  813. /**
  814. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  815. * @vdev: DP vdev handle
  816. * @nbuf: skb
  817. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  818. * @desc_pool_id : Descriptor Pool ID
  819. *
  820. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  821. * information. For frames wth fragments, allocate and prepare
  822. * an MSDU extension descriptor
  823. *
  824. * Return: Pointer to Tx Descriptor on success,
  825. * NULL on failure
  826. */
  827. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  828. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  829. uint8_t desc_pool_id)
  830. {
  831. struct dp_tx_desc_s *tx_desc;
  832. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  833. struct dp_pdev *pdev = vdev->pdev;
  834. struct dp_soc *soc = pdev->soc;
  835. if (dp_tx_limit_check(vdev))
  836. return NULL;
  837. /* Allocate software Tx descriptor */
  838. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  839. if (!tx_desc) {
  840. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  841. return NULL;
  842. }
  843. dp_tx_outstanding_inc(pdev);
  844. /* Initialize the SW tx descriptor */
  845. tx_desc->nbuf = nbuf;
  846. tx_desc->frm_type = msdu_info->frm_type;
  847. tx_desc->tx_encap_type = vdev->tx_encap_type;
  848. tx_desc->vdev_id = vdev->vdev_id;
  849. tx_desc->pdev = pdev;
  850. tx_desc->pkt_offset = 0;
  851. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  852. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  853. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  854. /* Handle scattered frames - TSO/SG/ME */
  855. /* Allocate and prepare an extension descriptor for scattered frames */
  856. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  857. if (!msdu_ext_desc) {
  858. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  859. "%s Tx Extension Descriptor Alloc Fail",
  860. __func__);
  861. goto failure;
  862. }
  863. #if TQM_BYPASS_WAR
  864. /* Temporary WAR due to TQM VP issues */
  865. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  866. qdf_atomic_inc(&soc->num_tx_exception);
  867. #endif
  868. if (qdf_unlikely(msdu_info->exception_fw))
  869. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  870. tx_desc->msdu_ext_desc = msdu_ext_desc;
  871. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  872. return tx_desc;
  873. failure:
  874. dp_tx_desc_release(tx_desc, desc_pool_id);
  875. return NULL;
  876. }
  877. /**
  878. * dp_tx_prepare_raw() - Prepare RAW packet TX
  879. * @vdev: DP vdev handle
  880. * @nbuf: buffer pointer
  881. * @seg_info: Pointer to Segment info Descriptor to be prepared
  882. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  883. * descriptor
  884. *
  885. * Return:
  886. */
  887. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  888. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. qdf_nbuf_t curr_nbuf = NULL;
  891. uint16_t total_len = 0;
  892. qdf_dma_addr_t paddr;
  893. int32_t i;
  894. int32_t mapped_buf_num = 0;
  895. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  896. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  897. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  898. /* Continue only if frames are of DATA type */
  899. if (!DP_FRAME_IS_DATA(qos_wh)) {
  900. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  901. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  902. "Pkt. recd is of not data type");
  903. goto error;
  904. }
  905. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  906. if (vdev->raw_mode_war &&
  907. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  908. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  909. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  910. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  911. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  912. /*
  913. * Number of nbuf's must not exceed the size of the frags
  914. * array in seg_info.
  915. */
  916. if (i >= DP_TX_MAX_NUM_FRAGS) {
  917. dp_err_rl("nbuf cnt exceeds the max number of segs");
  918. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  919. goto error;
  920. }
  921. if (QDF_STATUS_SUCCESS !=
  922. qdf_nbuf_map_nbytes_single(vdev->osdev,
  923. curr_nbuf,
  924. QDF_DMA_TO_DEVICE,
  925. curr_nbuf->len)) {
  926. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  927. "%s dma map error ", __func__);
  928. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  929. goto error;
  930. }
  931. /* Update the count of mapped nbuf's */
  932. mapped_buf_num++;
  933. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  934. seg_info->frags[i].paddr_lo = paddr;
  935. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  936. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  937. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  938. total_len += qdf_nbuf_len(curr_nbuf);
  939. }
  940. seg_info->frag_cnt = i;
  941. seg_info->total_len = total_len;
  942. seg_info->next = NULL;
  943. sg_info->curr_seg = seg_info;
  944. msdu_info->frm_type = dp_tx_frm_raw;
  945. msdu_info->num_seg = 1;
  946. return nbuf;
  947. error:
  948. i = 0;
  949. while (nbuf) {
  950. curr_nbuf = nbuf;
  951. if (i < mapped_buf_num) {
  952. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  953. QDF_DMA_TO_DEVICE,
  954. curr_nbuf->len);
  955. i++;
  956. }
  957. nbuf = qdf_nbuf_next(nbuf);
  958. qdf_nbuf_free(curr_nbuf);
  959. }
  960. return NULL;
  961. }
  962. /**
  963. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  964. * @soc: DP soc handle
  965. * @nbuf: Buffer pointer
  966. *
  967. * unmap the chain of nbufs that belong to this RAW frame.
  968. *
  969. * Return: None
  970. */
  971. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  972. qdf_nbuf_t nbuf)
  973. {
  974. qdf_nbuf_t cur_nbuf = nbuf;
  975. do {
  976. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  977. QDF_DMA_TO_DEVICE,
  978. cur_nbuf->len);
  979. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  980. } while (cur_nbuf);
  981. }
  982. #ifdef VDEV_PEER_PROTOCOL_COUNT
  983. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  984. { \
  985. qdf_nbuf_t nbuf_local; \
  986. struct dp_vdev *vdev_local = vdev_hdl; \
  987. do { \
  988. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  989. break; \
  990. nbuf_local = nbuf; \
  991. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  992. htt_cmn_pkt_type_raw)) \
  993. break; \
  994. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  995. break; \
  996. else if (qdf_nbuf_is_tso((nbuf_local))) \
  997. break; \
  998. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  999. (nbuf_local), \
  1000. NULL, 1, 0); \
  1001. } while (0); \
  1002. }
  1003. #else
  1004. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1005. #endif
  1006. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1007. /**
  1008. * dp_tx_update_stats() - Update soc level tx stats
  1009. * @soc: DP soc handle
  1010. * @nbuf: packet being transmitted
  1011. *
  1012. * Returns: none
  1013. */
  1014. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1015. qdf_nbuf_t nbuf)
  1016. {
  1017. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1018. }
  1019. /**
  1020. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1021. * @soc: Datapath soc handle
  1022. * @tx_desc: tx packet descriptor
  1023. * @tid: TID for pkt transmission
  1024. *
  1025. * Returns: 1, if coalescing is to be done
  1026. * 0, if coalescing is not to be done
  1027. */
  1028. static inline int
  1029. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1030. struct dp_tx_desc_s *tx_desc,
  1031. uint8_t tid)
  1032. {
  1033. struct dp_swlm *swlm = &soc->swlm;
  1034. union swlm_data swlm_query_data;
  1035. struct dp_swlm_tcl_data tcl_data;
  1036. QDF_STATUS status;
  1037. int ret;
  1038. if (qdf_unlikely(!swlm->is_enabled))
  1039. return 0;
  1040. tcl_data.nbuf = tx_desc->nbuf;
  1041. tcl_data.tid = tid;
  1042. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1043. swlm_query_data.tcl_data = &tcl_data;
  1044. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1045. if (QDF_IS_STATUS_ERROR(status)) {
  1046. dp_swlm_tcl_reset_session_data(soc);
  1047. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1048. return 0;
  1049. }
  1050. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1051. if (ret) {
  1052. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1053. } else {
  1054. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1055. }
  1056. return ret;
  1057. }
  1058. /**
  1059. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1060. * @soc: Datapath soc handle
  1061. * @hal_ring_hdl: HAL ring handle
  1062. * @coalesce: Coalesce the current write or not
  1063. *
  1064. * Returns: none
  1065. */
  1066. static inline void
  1067. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1068. int coalesce)
  1069. {
  1070. if (coalesce)
  1071. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1072. else
  1073. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1074. }
  1075. #else
  1076. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1077. qdf_nbuf_t nbuf)
  1078. {
  1079. }
  1080. static inline int
  1081. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1082. struct dp_tx_desc_s *tx_desc,
  1083. uint8_t tid)
  1084. {
  1085. return 0;
  1086. }
  1087. static inline void
  1088. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1089. int coalesce)
  1090. {
  1091. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1092. }
  1093. #endif
  1094. /**
  1095. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1096. * @soc: DP Soc Handle
  1097. * @vdev: DP vdev handle
  1098. * @tx_desc: Tx Descriptor Handle
  1099. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1100. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1101. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1102. * @tx_exc_metadata: Handle that holds exception path meta data
  1103. *
  1104. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1105. * from software Tx descriptor
  1106. *
  1107. * Return: QDF_STATUS_SUCCESS: success
  1108. * QDF_STATUS_E_RESOURCES: Error return
  1109. */
  1110. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1111. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1112. uint16_t fw_metadata, uint8_t ring_id,
  1113. struct cdp_tx_exception_metadata
  1114. *tx_exc_metadata)
  1115. {
  1116. uint8_t type;
  1117. void *hal_tx_desc;
  1118. uint32_t *hal_tx_desc_cached;
  1119. int coalesce = 0;
  1120. /*
  1121. * Setting it initialization statically here to avoid
  1122. * a memset call jump with qdf_mem_set call
  1123. */
  1124. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1125. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1126. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1127. tx_exc_metadata->sec_type : vdev->sec_type);
  1128. /* Return Buffer Manager ID */
  1129. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1130. hal_ring_handle_t hal_ring_hdl = NULL;
  1131. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1132. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1133. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1134. return QDF_STATUS_E_RESOURCES;
  1135. }
  1136. hal_tx_desc_cached = (void *) cached_desc;
  1137. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1138. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1139. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1140. if (tx_desc->msdu_ext_desc->flags &
  1141. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1142. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1143. else
  1144. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1145. } else {
  1146. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1147. tx_desc->pkt_offset;
  1148. type = HAL_TX_BUF_TYPE_BUFFER;
  1149. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1150. }
  1151. qdf_assert_always(tx_desc->dma_addr);
  1152. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1153. tx_desc->dma_addr, bm_id, tx_desc->id,
  1154. type);
  1155. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1156. vdev->lmac_id);
  1157. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1158. vdev->search_type);
  1159. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1160. vdev->bss_ast_idx);
  1161. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1162. vdev->dscp_tid_map_id);
  1163. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1164. sec_type_map[sec_type]);
  1165. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1166. (vdev->bss_ast_hash & 0xF));
  1167. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1168. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1169. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1170. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1171. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1172. vdev->hal_desc_addr_search_flags);
  1173. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1174. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1175. /* verify checksum offload configuration*/
  1176. if (vdev->csum_enabled &&
  1177. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1178. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1179. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1180. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1181. }
  1182. if (tid != HTT_TX_EXT_TID_INVALID)
  1183. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1184. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1185. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1186. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1187. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1188. soc->wlan_cfg_ctx)))
  1189. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1190. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1191. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1192. tx_desc->pkt_offset, tx_desc->id);
  1193. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1194. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1195. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1196. "%s %d : HAL RING Access Failed -- %pK",
  1197. __func__, __LINE__, hal_ring_hdl);
  1198. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1199. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1200. return status;
  1201. }
  1202. /* Sync cached descriptor with HW */
  1203. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1204. if (qdf_unlikely(!hal_tx_desc)) {
  1205. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1206. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1207. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1208. goto ring_access_fail;
  1209. }
  1210. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1211. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1212. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1213. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1214. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1215. dp_tx_update_stats(soc, tx_desc->nbuf);
  1216. status = QDF_STATUS_SUCCESS;
  1217. ring_access_fail:
  1218. if (hif_pm_runtime_get(soc->hif_handle,
  1219. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1220. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1221. hif_pm_runtime_put(soc->hif_handle,
  1222. RTPM_ID_DW_TX_HW_ENQUEUE);
  1223. } else {
  1224. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1225. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1226. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1227. }
  1228. return status;
  1229. }
  1230. /**
  1231. * dp_cce_classify() - Classify the frame based on CCE rules
  1232. * @vdev: DP vdev handle
  1233. * @nbuf: skb
  1234. *
  1235. * Classify frames based on CCE rules
  1236. * Return: bool( true if classified,
  1237. * else false)
  1238. */
  1239. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1240. {
  1241. qdf_ether_header_t *eh = NULL;
  1242. uint16_t ether_type;
  1243. qdf_llc_t *llcHdr;
  1244. qdf_nbuf_t nbuf_clone = NULL;
  1245. qdf_dot3_qosframe_t *qos_wh = NULL;
  1246. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1247. /*
  1248. * In case of mesh packets or hlos tid override enabled,
  1249. * don't do any classification
  1250. */
  1251. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1252. & DP_TX_SKIP_CCE_CLASSIFY))
  1253. return false;
  1254. }
  1255. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1256. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1257. ether_type = eh->ether_type;
  1258. llcHdr = (qdf_llc_t *)(nbuf->data +
  1259. sizeof(qdf_ether_header_t));
  1260. } else {
  1261. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1262. /* For encrypted packets don't do any classification */
  1263. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1264. return false;
  1265. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1266. if (qdf_unlikely(
  1267. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1268. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1269. ether_type = *(uint16_t *)(nbuf->data
  1270. + QDF_IEEE80211_4ADDR_HDR_LEN
  1271. + sizeof(qdf_llc_t)
  1272. - sizeof(ether_type));
  1273. llcHdr = (qdf_llc_t *)(nbuf->data +
  1274. QDF_IEEE80211_4ADDR_HDR_LEN);
  1275. } else {
  1276. ether_type = *(uint16_t *)(nbuf->data
  1277. + QDF_IEEE80211_3ADDR_HDR_LEN
  1278. + sizeof(qdf_llc_t)
  1279. - sizeof(ether_type));
  1280. llcHdr = (qdf_llc_t *)(nbuf->data +
  1281. QDF_IEEE80211_3ADDR_HDR_LEN);
  1282. }
  1283. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1284. && (ether_type ==
  1285. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1286. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1287. return true;
  1288. }
  1289. }
  1290. return false;
  1291. }
  1292. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1293. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1294. sizeof(*llcHdr));
  1295. nbuf_clone = qdf_nbuf_clone(nbuf);
  1296. if (qdf_unlikely(nbuf_clone)) {
  1297. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1298. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1299. qdf_nbuf_pull_head(nbuf_clone,
  1300. sizeof(qdf_net_vlanhdr_t));
  1301. }
  1302. }
  1303. } else {
  1304. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1305. nbuf_clone = qdf_nbuf_clone(nbuf);
  1306. if (qdf_unlikely(nbuf_clone)) {
  1307. qdf_nbuf_pull_head(nbuf_clone,
  1308. sizeof(qdf_net_vlanhdr_t));
  1309. }
  1310. }
  1311. }
  1312. if (qdf_unlikely(nbuf_clone))
  1313. nbuf = nbuf_clone;
  1314. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1315. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1316. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1317. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1318. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1319. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1320. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1321. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1322. if (qdf_unlikely(nbuf_clone))
  1323. qdf_nbuf_free(nbuf_clone);
  1324. return true;
  1325. }
  1326. if (qdf_unlikely(nbuf_clone))
  1327. qdf_nbuf_free(nbuf_clone);
  1328. return false;
  1329. }
  1330. /**
  1331. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1332. * @vdev: DP vdev handle
  1333. * @nbuf: skb
  1334. *
  1335. * Extract the DSCP or PCP information from frame and map into TID value.
  1336. *
  1337. * Return: void
  1338. */
  1339. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1340. struct dp_tx_msdu_info_s *msdu_info)
  1341. {
  1342. uint8_t tos = 0, dscp_tid_override = 0;
  1343. uint8_t *hdr_ptr, *L3datap;
  1344. uint8_t is_mcast = 0;
  1345. qdf_ether_header_t *eh = NULL;
  1346. qdf_ethervlan_header_t *evh = NULL;
  1347. uint16_t ether_type;
  1348. qdf_llc_t *llcHdr;
  1349. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1350. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1351. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1352. eh = (qdf_ether_header_t *)nbuf->data;
  1353. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1354. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1355. } else {
  1356. qdf_dot3_qosframe_t *qos_wh =
  1357. (qdf_dot3_qosframe_t *) nbuf->data;
  1358. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1359. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1360. return;
  1361. }
  1362. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1363. ether_type = eh->ether_type;
  1364. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1365. /*
  1366. * Check if packet is dot3 or eth2 type.
  1367. */
  1368. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1369. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1370. sizeof(*llcHdr));
  1371. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1372. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1373. sizeof(*llcHdr);
  1374. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1375. + sizeof(*llcHdr) +
  1376. sizeof(qdf_net_vlanhdr_t));
  1377. } else {
  1378. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1379. sizeof(*llcHdr);
  1380. }
  1381. } else {
  1382. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1383. evh = (qdf_ethervlan_header_t *) eh;
  1384. ether_type = evh->ether_type;
  1385. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1386. }
  1387. }
  1388. /*
  1389. * Find priority from IP TOS DSCP field
  1390. */
  1391. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1392. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1393. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1394. /* Only for unicast frames */
  1395. if (!is_mcast) {
  1396. /* send it on VO queue */
  1397. msdu_info->tid = DP_VO_TID;
  1398. }
  1399. } else {
  1400. /*
  1401. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1402. * from TOS byte.
  1403. */
  1404. tos = ip->ip_tos;
  1405. dscp_tid_override = 1;
  1406. }
  1407. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1408. /* TODO
  1409. * use flowlabel
  1410. *igmpmld cases to be handled in phase 2
  1411. */
  1412. unsigned long ver_pri_flowlabel;
  1413. unsigned long pri;
  1414. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1415. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1416. DP_IPV6_PRIORITY_SHIFT;
  1417. tos = pri;
  1418. dscp_tid_override = 1;
  1419. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1420. msdu_info->tid = DP_VO_TID;
  1421. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1422. /* Only for unicast frames */
  1423. if (!is_mcast) {
  1424. /* send ucast arp on VO queue */
  1425. msdu_info->tid = DP_VO_TID;
  1426. }
  1427. }
  1428. /*
  1429. * Assign all MCAST packets to BE
  1430. */
  1431. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1432. if (is_mcast) {
  1433. tos = 0;
  1434. dscp_tid_override = 1;
  1435. }
  1436. }
  1437. if (dscp_tid_override == 1) {
  1438. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1439. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1440. }
  1441. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1442. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1443. return;
  1444. }
  1445. /**
  1446. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1447. * @vdev: DP vdev handle
  1448. * @nbuf: skb
  1449. *
  1450. * Software based TID classification is required when more than 2 DSCP-TID
  1451. * mapping tables are needed.
  1452. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1453. *
  1454. * Return: void
  1455. */
  1456. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1457. struct dp_tx_msdu_info_s *msdu_info)
  1458. {
  1459. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1460. /*
  1461. * skip_sw_tid_classification flag will set in below cases-
  1462. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1463. * 2. hlos_tid_override enabled for vdev
  1464. * 3. mesh mode enabled for vdev
  1465. */
  1466. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1467. /* Update tid in msdu_info from skb priority */
  1468. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1469. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1470. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1471. return;
  1472. }
  1473. return;
  1474. }
  1475. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1476. }
  1477. #ifdef FEATURE_WLAN_TDLS
  1478. /**
  1479. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1480. * @soc: datapath SOC
  1481. * @vdev: datapath vdev
  1482. * @tx_desc: TX descriptor
  1483. *
  1484. * Return: None
  1485. */
  1486. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1487. struct dp_vdev *vdev,
  1488. struct dp_tx_desc_s *tx_desc)
  1489. {
  1490. if (vdev) {
  1491. if (vdev->is_tdls_frame) {
  1492. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1493. vdev->is_tdls_frame = false;
  1494. }
  1495. }
  1496. }
  1497. /**
  1498. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1499. * @soc: dp_soc handle
  1500. * @tx_desc: TX descriptor
  1501. * @vdev: datapath vdev handle
  1502. *
  1503. * Return: None
  1504. */
  1505. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1506. struct dp_tx_desc_s *tx_desc)
  1507. {
  1508. struct hal_tx_completion_status ts = {0};
  1509. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1510. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1511. DP_MOD_ID_TDLS);
  1512. if (qdf_unlikely(!vdev)) {
  1513. dp_err_rl("vdev is null!");
  1514. goto error;
  1515. }
  1516. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1517. if (vdev->tx_non_std_data_callback.func) {
  1518. qdf_nbuf_set_next(nbuf, NULL);
  1519. vdev->tx_non_std_data_callback.func(
  1520. vdev->tx_non_std_data_callback.ctxt,
  1521. nbuf, ts.status);
  1522. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1523. return;
  1524. } else {
  1525. dp_err_rl("callback func is null");
  1526. }
  1527. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1528. error:
  1529. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1530. qdf_nbuf_free(nbuf);
  1531. }
  1532. /**
  1533. * dp_tx_msdu_single_map() - do nbuf map
  1534. * @vdev: DP vdev handle
  1535. * @tx_desc: DP TX descriptor pointer
  1536. * @nbuf: skb pointer
  1537. *
  1538. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1539. * operation done in other component.
  1540. *
  1541. * Return: QDF_STATUS
  1542. */
  1543. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1544. struct dp_tx_desc_s *tx_desc,
  1545. qdf_nbuf_t nbuf)
  1546. {
  1547. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1548. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1549. nbuf,
  1550. QDF_DMA_TO_DEVICE,
  1551. nbuf->len);
  1552. else
  1553. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1554. QDF_DMA_TO_DEVICE);
  1555. }
  1556. #else
  1557. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1558. struct dp_vdev *vdev,
  1559. struct dp_tx_desc_s *tx_desc)
  1560. {
  1561. }
  1562. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1563. struct dp_tx_desc_s *tx_desc)
  1564. {
  1565. }
  1566. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1567. struct dp_tx_desc_s *tx_desc,
  1568. qdf_nbuf_t nbuf)
  1569. {
  1570. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1571. nbuf,
  1572. QDF_DMA_TO_DEVICE,
  1573. nbuf->len);
  1574. }
  1575. #endif
  1576. #ifdef MESH_MODE_SUPPORT
  1577. /**
  1578. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1579. * @soc: datapath SOC
  1580. * @vdev: datapath vdev
  1581. * @tx_desc: TX descriptor
  1582. *
  1583. * Return: None
  1584. */
  1585. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1586. struct dp_vdev *vdev,
  1587. struct dp_tx_desc_s *tx_desc)
  1588. {
  1589. if (qdf_unlikely(vdev->mesh_vdev))
  1590. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1591. }
  1592. /**
  1593. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1594. * @soc: dp_soc handle
  1595. * @tx_desc: TX descriptor
  1596. * @vdev: datapath vdev handle
  1597. *
  1598. * Return: None
  1599. */
  1600. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1601. struct dp_tx_desc_s *tx_desc)
  1602. {
  1603. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1604. struct dp_vdev *vdev = NULL;
  1605. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1606. qdf_nbuf_free(nbuf);
  1607. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1608. } else {
  1609. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1610. DP_MOD_ID_MESH);
  1611. if (vdev && vdev->osif_tx_free_ext)
  1612. vdev->osif_tx_free_ext((nbuf));
  1613. else
  1614. qdf_nbuf_free(nbuf);
  1615. if (vdev)
  1616. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1617. }
  1618. }
  1619. #else
  1620. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1621. struct dp_vdev *vdev,
  1622. struct dp_tx_desc_s *tx_desc)
  1623. {
  1624. }
  1625. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1626. struct dp_tx_desc_s *tx_desc)
  1627. {
  1628. }
  1629. #endif
  1630. /**
  1631. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1632. * @vdev: DP vdev handle
  1633. * @nbuf: skb
  1634. *
  1635. * Return: 1 if frame needs to be dropped else 0
  1636. */
  1637. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1638. {
  1639. struct dp_pdev *pdev = NULL;
  1640. struct dp_ast_entry *src_ast_entry = NULL;
  1641. struct dp_ast_entry *dst_ast_entry = NULL;
  1642. struct dp_soc *soc = NULL;
  1643. qdf_assert(vdev);
  1644. pdev = vdev->pdev;
  1645. qdf_assert(pdev);
  1646. soc = pdev->soc;
  1647. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1648. (soc, dstmac, vdev->pdev->pdev_id);
  1649. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1650. (soc, srcmac, vdev->pdev->pdev_id);
  1651. if (dst_ast_entry && src_ast_entry) {
  1652. if (dst_ast_entry->peer_id ==
  1653. src_ast_entry->peer_id)
  1654. return 1;
  1655. }
  1656. return 0;
  1657. }
  1658. /**
  1659. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1660. * @vdev: DP vdev handle
  1661. * @nbuf: skb
  1662. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1663. * @meta_data: Metadata to the fw
  1664. * @tx_q: Tx queue to be used for this Tx frame
  1665. * @peer_id: peer_id of the peer in case of NAWDS frames
  1666. * @tx_exc_metadata: Handle that holds exception path metadata
  1667. *
  1668. * Return: NULL on success,
  1669. * nbuf when it fails to send
  1670. */
  1671. qdf_nbuf_t
  1672. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1673. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1674. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1675. {
  1676. struct dp_pdev *pdev = vdev->pdev;
  1677. struct dp_soc *soc = pdev->soc;
  1678. struct dp_tx_desc_s *tx_desc;
  1679. QDF_STATUS status;
  1680. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1681. uint16_t htt_tcl_metadata = 0;
  1682. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1683. uint8_t tid = msdu_info->tid;
  1684. struct cdp_tid_tx_stats *tid_stats = NULL;
  1685. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1686. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1687. msdu_info, tx_exc_metadata);
  1688. if (!tx_desc) {
  1689. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1690. vdev, tx_q->desc_pool_id);
  1691. drop_code = TX_DESC_ERR;
  1692. goto fail_return;
  1693. }
  1694. if (qdf_unlikely(soc->cce_disable)) {
  1695. if (dp_cce_classify(vdev, nbuf) == true) {
  1696. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1697. tid = DP_VO_TID;
  1698. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1699. }
  1700. }
  1701. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1702. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1703. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1704. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1705. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1706. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1707. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1708. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1709. peer_id);
  1710. } else
  1711. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1712. if (msdu_info->exception_fw)
  1713. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1714. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1715. !pdev->enhanced_stats_en);
  1716. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1717. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1718. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1719. /* Handle failure */
  1720. dp_err("qdf_nbuf_map failed");
  1721. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1722. drop_code = TX_DMA_MAP_ERR;
  1723. goto release_desc;
  1724. }
  1725. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1726. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1727. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1728. if (status != QDF_STATUS_SUCCESS) {
  1729. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1730. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1731. __func__, tx_desc, tx_q->ring_id);
  1732. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1733. QDF_DMA_TO_DEVICE,
  1734. nbuf->len);
  1735. drop_code = TX_HW_ENQUEUE;
  1736. goto release_desc;
  1737. }
  1738. return NULL;
  1739. release_desc:
  1740. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1741. fail_return:
  1742. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1743. tid_stats = &pdev->stats.tid_stats.
  1744. tid_tx_stats[tx_q->ring_id][tid];
  1745. tid_stats->swdrop_cnt[drop_code]++;
  1746. return nbuf;
  1747. }
  1748. /**
  1749. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1750. * @vdev: DP vdev handle
  1751. * @nbuf: skb
  1752. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1753. *
  1754. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1755. *
  1756. * Return: NULL on success,
  1757. * nbuf when it fails to send
  1758. */
  1759. #if QDF_LOCK_STATS
  1760. noinline
  1761. #else
  1762. #endif
  1763. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1764. struct dp_tx_msdu_info_s *msdu_info)
  1765. {
  1766. uint32_t i;
  1767. struct dp_pdev *pdev = vdev->pdev;
  1768. struct dp_soc *soc = pdev->soc;
  1769. struct dp_tx_desc_s *tx_desc;
  1770. bool is_cce_classified = false;
  1771. QDF_STATUS status;
  1772. uint16_t htt_tcl_metadata = 0;
  1773. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1774. struct cdp_tid_tx_stats *tid_stats = NULL;
  1775. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1776. if (qdf_unlikely(soc->cce_disable)) {
  1777. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1778. if (is_cce_classified) {
  1779. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1780. msdu_info->tid = DP_VO_TID;
  1781. }
  1782. }
  1783. if (msdu_info->frm_type == dp_tx_frm_me)
  1784. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1785. i = 0;
  1786. /* Print statement to track i and num_seg */
  1787. /*
  1788. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1789. * descriptors using information in msdu_info
  1790. */
  1791. while (i < msdu_info->num_seg) {
  1792. /*
  1793. * Setup Tx descriptor for an MSDU, and MSDU extension
  1794. * descriptor
  1795. */
  1796. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1797. tx_q->desc_pool_id);
  1798. if (!tx_desc) {
  1799. if (msdu_info->frm_type == dp_tx_frm_me) {
  1800. prep_desc_fail++;
  1801. dp_tx_me_free_buf(pdev,
  1802. (void *)(msdu_info->u.sg_info
  1803. .curr_seg->frags[0].vaddr));
  1804. if (prep_desc_fail == msdu_info->num_seg) {
  1805. /*
  1806. * Unmap is needed only if descriptor
  1807. * preparation failed for all segments.
  1808. */
  1809. qdf_nbuf_unmap(soc->osdev,
  1810. msdu_info->u.sg_info.
  1811. curr_seg->nbuf,
  1812. QDF_DMA_TO_DEVICE);
  1813. }
  1814. /*
  1815. * Free the nbuf for the current segment
  1816. * and make it point to the next in the list.
  1817. * For me, there are as many segments as there
  1818. * are no of clients.
  1819. */
  1820. qdf_nbuf_free(msdu_info->u.sg_info
  1821. .curr_seg->nbuf);
  1822. if (msdu_info->u.sg_info.curr_seg->next)
  1823. msdu_info->u.sg_info.curr_seg =
  1824. msdu_info->u.sg_info
  1825. .curr_seg->next;
  1826. i++;
  1827. continue;
  1828. }
  1829. goto done;
  1830. }
  1831. if (msdu_info->frm_type == dp_tx_frm_me) {
  1832. tx_desc->me_buffer =
  1833. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1834. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1835. }
  1836. if (is_cce_classified)
  1837. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1838. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1839. if (msdu_info->exception_fw) {
  1840. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1841. }
  1842. /*
  1843. * Enqueue the Tx MSDU descriptor to HW for transmit
  1844. */
  1845. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1846. htt_tcl_metadata, tx_q->ring_id, NULL);
  1847. if (status != QDF_STATUS_SUCCESS) {
  1848. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1849. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1850. __func__, tx_desc, tx_q->ring_id);
  1851. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1852. tid_stats = &pdev->stats.tid_stats.
  1853. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1854. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1855. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1856. if (msdu_info->frm_type == dp_tx_frm_me) {
  1857. hw_enq_fail++;
  1858. if (hw_enq_fail == msdu_info->num_seg) {
  1859. /*
  1860. * Unmap is needed only if enqueue
  1861. * failed for all segments.
  1862. */
  1863. qdf_nbuf_unmap(soc->osdev,
  1864. msdu_info->u.sg_info.
  1865. curr_seg->nbuf,
  1866. QDF_DMA_TO_DEVICE);
  1867. }
  1868. /*
  1869. * Free the nbuf for the current segment
  1870. * and make it point to the next in the list.
  1871. * For me, there are as many segments as there
  1872. * are no of clients.
  1873. */
  1874. qdf_nbuf_free(msdu_info->u.sg_info
  1875. .curr_seg->nbuf);
  1876. if (msdu_info->u.sg_info.curr_seg->next)
  1877. msdu_info->u.sg_info.curr_seg =
  1878. msdu_info->u.sg_info
  1879. .curr_seg->next;
  1880. i++;
  1881. continue;
  1882. }
  1883. goto done;
  1884. }
  1885. /*
  1886. * TODO
  1887. * if tso_info structure can be modified to have curr_seg
  1888. * as first element, following 2 blocks of code (for TSO and SG)
  1889. * can be combined into 1
  1890. */
  1891. /*
  1892. * For frames with multiple segments (TSO, ME), jump to next
  1893. * segment.
  1894. */
  1895. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1896. if (msdu_info->u.tso_info.curr_seg->next) {
  1897. msdu_info->u.tso_info.curr_seg =
  1898. msdu_info->u.tso_info.curr_seg->next;
  1899. /*
  1900. * If this is a jumbo nbuf, then increment the number of
  1901. * nbuf users for each additional segment of the msdu.
  1902. * This will ensure that the skb is freed only after
  1903. * receiving tx completion for all segments of an nbuf
  1904. */
  1905. qdf_nbuf_inc_users(nbuf);
  1906. /* Check with MCL if this is needed */
  1907. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1908. }
  1909. }
  1910. /*
  1911. * For Multicast-Unicast converted packets,
  1912. * each converted frame (for a client) is represented as
  1913. * 1 segment
  1914. */
  1915. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1916. (msdu_info->frm_type == dp_tx_frm_me)) {
  1917. if (msdu_info->u.sg_info.curr_seg->next) {
  1918. msdu_info->u.sg_info.curr_seg =
  1919. msdu_info->u.sg_info.curr_seg->next;
  1920. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1921. }
  1922. }
  1923. i++;
  1924. }
  1925. nbuf = NULL;
  1926. done:
  1927. return nbuf;
  1928. }
  1929. /**
  1930. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1931. * for SG frames
  1932. * @vdev: DP vdev handle
  1933. * @nbuf: skb
  1934. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1935. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1936. *
  1937. * Return: NULL on success,
  1938. * nbuf when it fails to send
  1939. */
  1940. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1941. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1942. {
  1943. uint32_t cur_frag, nr_frags, i;
  1944. qdf_dma_addr_t paddr;
  1945. struct dp_tx_sg_info_s *sg_info;
  1946. sg_info = &msdu_info->u.sg_info;
  1947. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1948. if (QDF_STATUS_SUCCESS !=
  1949. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1950. QDF_DMA_TO_DEVICE,
  1951. qdf_nbuf_headlen(nbuf))) {
  1952. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1953. "dma map error");
  1954. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1955. qdf_nbuf_free(nbuf);
  1956. return NULL;
  1957. }
  1958. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1959. seg_info->frags[0].paddr_lo = paddr;
  1960. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1961. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1962. seg_info->frags[0].vaddr = (void *) nbuf;
  1963. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1964. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1965. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1966. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1967. "frag dma map error");
  1968. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1969. goto map_err;
  1970. }
  1971. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1972. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1973. seg_info->frags[cur_frag + 1].paddr_hi =
  1974. ((uint64_t) paddr) >> 32;
  1975. seg_info->frags[cur_frag + 1].len =
  1976. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1977. }
  1978. seg_info->frag_cnt = (cur_frag + 1);
  1979. seg_info->total_len = qdf_nbuf_len(nbuf);
  1980. seg_info->next = NULL;
  1981. sg_info->curr_seg = seg_info;
  1982. msdu_info->frm_type = dp_tx_frm_sg;
  1983. msdu_info->num_seg = 1;
  1984. return nbuf;
  1985. map_err:
  1986. /* restore paddr into nbuf before calling unmap */
  1987. qdf_nbuf_mapped_paddr_set(nbuf,
  1988. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  1989. ((uint64_t)
  1990. seg_info->frags[0].paddr_hi) << 32));
  1991. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1992. QDF_DMA_TO_DEVICE,
  1993. seg_info->frags[0].len);
  1994. for (i = 1; i <= cur_frag; i++) {
  1995. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  1996. (seg_info->frags[i].paddr_lo | ((uint64_t)
  1997. seg_info->frags[i].paddr_hi) << 32),
  1998. seg_info->frags[i].len,
  1999. QDF_DMA_TO_DEVICE);
  2000. }
  2001. qdf_nbuf_free(nbuf);
  2002. return NULL;
  2003. }
  2004. /**
  2005. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2006. * @vdev: DP vdev handle
  2007. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2008. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2009. *
  2010. * Return: NULL on failure,
  2011. * nbuf when extracted successfully
  2012. */
  2013. static
  2014. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2015. struct dp_tx_msdu_info_s *msdu_info,
  2016. uint16_t ppdu_cookie)
  2017. {
  2018. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2019. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2020. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2021. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2022. (msdu_info->meta_data[5], 1);
  2023. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2024. (msdu_info->meta_data[5], 1);
  2025. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2026. (msdu_info->meta_data[6], ppdu_cookie);
  2027. msdu_info->exception_fw = 1;
  2028. msdu_info->is_tx_sniffer = 1;
  2029. }
  2030. #ifdef MESH_MODE_SUPPORT
  2031. /**
  2032. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2033. and prepare msdu_info for mesh frames.
  2034. * @vdev: DP vdev handle
  2035. * @nbuf: skb
  2036. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2037. *
  2038. * Return: NULL on failure,
  2039. * nbuf when extracted successfully
  2040. */
  2041. static
  2042. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2043. struct dp_tx_msdu_info_s *msdu_info)
  2044. {
  2045. struct meta_hdr_s *mhdr;
  2046. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2047. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2048. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2049. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2050. msdu_info->exception_fw = 0;
  2051. goto remove_meta_hdr;
  2052. }
  2053. msdu_info->exception_fw = 1;
  2054. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2055. meta_data->host_tx_desc_pool = 1;
  2056. meta_data->update_peer_cache = 1;
  2057. meta_data->learning_frame = 1;
  2058. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2059. meta_data->power = mhdr->power;
  2060. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2061. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2062. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2063. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2064. meta_data->dyn_bw = 1;
  2065. meta_data->valid_pwr = 1;
  2066. meta_data->valid_mcs_mask = 1;
  2067. meta_data->valid_nss_mask = 1;
  2068. meta_data->valid_preamble_type = 1;
  2069. meta_data->valid_retries = 1;
  2070. meta_data->valid_bw_info = 1;
  2071. }
  2072. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2073. meta_data->encrypt_type = 0;
  2074. meta_data->valid_encrypt_type = 1;
  2075. meta_data->learning_frame = 0;
  2076. }
  2077. meta_data->valid_key_flags = 1;
  2078. meta_data->key_flags = (mhdr->keyix & 0x3);
  2079. remove_meta_hdr:
  2080. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2081. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2082. "qdf_nbuf_pull_head failed");
  2083. qdf_nbuf_free(nbuf);
  2084. return NULL;
  2085. }
  2086. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2087. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2088. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2089. " tid %d to_fw %d",
  2090. __func__, msdu_info->meta_data[0],
  2091. msdu_info->meta_data[1],
  2092. msdu_info->meta_data[2],
  2093. msdu_info->meta_data[3],
  2094. msdu_info->meta_data[4],
  2095. msdu_info->meta_data[5],
  2096. msdu_info->tid, msdu_info->exception_fw);
  2097. return nbuf;
  2098. }
  2099. #else
  2100. static
  2101. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2102. struct dp_tx_msdu_info_s *msdu_info)
  2103. {
  2104. return nbuf;
  2105. }
  2106. #endif
  2107. /**
  2108. * dp_check_exc_metadata() - Checks if parameters are valid
  2109. * @tx_exc - holds all exception path parameters
  2110. *
  2111. * Returns true when all the parameters are valid else false
  2112. *
  2113. */
  2114. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2115. {
  2116. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2117. HTT_INVALID_TID);
  2118. bool invalid_encap_type =
  2119. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2120. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2121. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2122. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2123. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2124. tx_exc->ppdu_cookie == 0);
  2125. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2126. invalid_cookie) {
  2127. return false;
  2128. }
  2129. return true;
  2130. }
  2131. /**
  2132. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2133. * @nbuf: qdf_nbuf_t
  2134. * @vdev: struct dp_vdev *
  2135. *
  2136. * Allow packet for processing only if it is for peer client which is
  2137. * connected with same vap. Drop packet if client is connected to
  2138. * different vap.
  2139. *
  2140. * Return: QDF_STATUS
  2141. */
  2142. static inline QDF_STATUS
  2143. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2144. {
  2145. struct dp_ast_entry *dst_ast_entry = NULL;
  2146. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2147. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2148. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2149. return QDF_STATUS_SUCCESS;
  2150. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2151. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2152. eh->ether_dhost,
  2153. vdev->vdev_id);
  2154. /* If there is no ast entry, return failure */
  2155. if (qdf_unlikely(!dst_ast_entry)) {
  2156. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2157. return QDF_STATUS_E_FAILURE;
  2158. }
  2159. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2160. return QDF_STATUS_SUCCESS;
  2161. }
  2162. /**
  2163. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2164. * @soc: DP soc handle
  2165. * @vdev_id: id of DP vdev handle
  2166. * @nbuf: skb
  2167. * @tx_exc_metadata: Handle that holds exception path meta data
  2168. *
  2169. * Entry point for Core Tx layer (DP_TX) invoked from
  2170. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2171. *
  2172. * Return: NULL on success,
  2173. * nbuf when it fails to send
  2174. */
  2175. qdf_nbuf_t
  2176. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2177. qdf_nbuf_t nbuf,
  2178. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2179. {
  2180. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2181. qdf_ether_header_t *eh = NULL;
  2182. struct dp_tx_msdu_info_s msdu_info;
  2183. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2184. DP_MOD_ID_TX_EXCEPTION);
  2185. if (qdf_unlikely(!vdev))
  2186. goto fail;
  2187. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2188. if (!tx_exc_metadata)
  2189. goto fail;
  2190. msdu_info.tid = tx_exc_metadata->tid;
  2191. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2192. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2193. QDF_MAC_ADDR_REF(nbuf->data));
  2194. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2195. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2197. "Invalid parameters in exception path");
  2198. goto fail;
  2199. }
  2200. /* Basic sanity checks for unsupported packets */
  2201. /* MESH mode */
  2202. if (qdf_unlikely(vdev->mesh_vdev)) {
  2203. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2204. "Mesh mode is not supported in exception path");
  2205. goto fail;
  2206. }
  2207. /* TSO or SG */
  2208. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  2209. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2210. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2211. "TSO and SG are not supported in exception path");
  2212. goto fail;
  2213. }
  2214. /* RAW */
  2215. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2217. "Raw frame is not supported in exception path");
  2218. goto fail;
  2219. }
  2220. /* Mcast enhancement*/
  2221. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2222. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2223. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2224. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2225. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  2226. }
  2227. }
  2228. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2229. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2230. qdf_nbuf_len(nbuf));
  2231. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2232. tx_exc_metadata->ppdu_cookie);
  2233. }
  2234. /*
  2235. * Get HW Queue to use for this frame.
  2236. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2237. * dedicated for data and 1 for command.
  2238. * "queue_id" maps to one hardware ring.
  2239. * With each ring, we also associate a unique Tx descriptor pool
  2240. * to minimize lock contention for these resources.
  2241. */
  2242. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2243. /*
  2244. * Check exception descriptors
  2245. */
  2246. if (dp_tx_exception_limit_check(vdev))
  2247. goto fail;
  2248. /* Single linear frame */
  2249. /*
  2250. * If nbuf is a simple linear frame, use send_single function to
  2251. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2252. * SRNG. There is no need to setup a MSDU extension descriptor.
  2253. */
  2254. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2255. tx_exc_metadata->peer_id, tx_exc_metadata);
  2256. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2257. return nbuf;
  2258. fail:
  2259. if (vdev)
  2260. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2261. dp_verbose_debug("pkt send failed");
  2262. return nbuf;
  2263. }
  2264. /**
  2265. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2266. * in exception path in special case to avoid regular exception path chk.
  2267. * @soc: DP soc handle
  2268. * @vdev_id: id of DP vdev handle
  2269. * @nbuf: skb
  2270. * @tx_exc_metadata: Handle that holds exception path meta data
  2271. *
  2272. * Entry point for Core Tx layer (DP_TX) invoked from
  2273. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2274. *
  2275. * Return: NULL on success,
  2276. * nbuf when it fails to send
  2277. */
  2278. qdf_nbuf_t
  2279. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2280. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2281. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2282. {
  2283. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2284. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2285. DP_MOD_ID_TX_EXCEPTION);
  2286. if (qdf_unlikely(!vdev))
  2287. goto fail;
  2288. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2289. == QDF_STATUS_E_FAILURE)) {
  2290. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2291. goto fail;
  2292. }
  2293. /* Unref count as it will agin be taken inside dp_tx_exception */
  2294. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2295. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2296. fail:
  2297. if (vdev)
  2298. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2299. dp_verbose_debug("pkt send failed");
  2300. return nbuf;
  2301. }
  2302. /**
  2303. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2304. * @soc: DP soc handle
  2305. * @vdev_id: DP vdev handle
  2306. * @nbuf: skb
  2307. *
  2308. * Entry point for Core Tx layer (DP_TX) invoked from
  2309. * hard_start_xmit in OSIF/HDD
  2310. *
  2311. * Return: NULL on success,
  2312. * nbuf when it fails to send
  2313. */
  2314. #ifdef MESH_MODE_SUPPORT
  2315. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2316. qdf_nbuf_t nbuf)
  2317. {
  2318. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2319. struct meta_hdr_s *mhdr;
  2320. qdf_nbuf_t nbuf_mesh = NULL;
  2321. qdf_nbuf_t nbuf_clone = NULL;
  2322. struct dp_vdev *vdev;
  2323. uint8_t no_enc_frame = 0;
  2324. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2325. if (!nbuf_mesh) {
  2326. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2327. "qdf_nbuf_unshare failed");
  2328. return nbuf;
  2329. }
  2330. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2331. if (!vdev) {
  2332. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2333. "vdev is NULL for vdev_id %d", vdev_id);
  2334. return nbuf;
  2335. }
  2336. nbuf = nbuf_mesh;
  2337. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2338. if ((vdev->sec_type != cdp_sec_type_none) &&
  2339. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2340. no_enc_frame = 1;
  2341. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2342. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2343. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2344. !no_enc_frame) {
  2345. nbuf_clone = qdf_nbuf_clone(nbuf);
  2346. if (!nbuf_clone) {
  2347. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2348. "qdf_nbuf_clone failed");
  2349. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2350. return nbuf;
  2351. }
  2352. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2353. }
  2354. if (nbuf_clone) {
  2355. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2356. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2357. } else {
  2358. qdf_nbuf_free(nbuf_clone);
  2359. }
  2360. }
  2361. if (no_enc_frame)
  2362. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2363. else
  2364. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2365. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2366. if ((!nbuf) && no_enc_frame) {
  2367. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2368. }
  2369. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2370. return nbuf;
  2371. }
  2372. #else
  2373. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2374. qdf_nbuf_t nbuf)
  2375. {
  2376. return dp_tx_send(soc, vdev_id, nbuf);
  2377. }
  2378. #endif
  2379. /**
  2380. * dp_tx_nawds_handler() - NAWDS handler
  2381. *
  2382. * @soc: DP soc handle
  2383. * @vdev_id: id of DP vdev handle
  2384. * @msdu_info: msdu_info required to create HTT metadata
  2385. * @nbuf: skb
  2386. *
  2387. * This API transfers the multicast frames with the peer id
  2388. * on NAWDS enabled peer.
  2389. * Return: none
  2390. */
  2391. static inline
  2392. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2393. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2394. {
  2395. struct dp_peer *peer = NULL;
  2396. qdf_nbuf_t nbuf_clone = NULL;
  2397. uint16_t peer_id = DP_INVALID_PEER;
  2398. uint16_t sa_peer_id = DP_INVALID_PEER;
  2399. struct dp_ast_entry *ast_entry = NULL;
  2400. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2401. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2402. qdf_spin_lock_bh(&soc->ast_lock);
  2403. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2404. (soc,
  2405. (uint8_t *)(eh->ether_shost),
  2406. vdev->pdev->pdev_id);
  2407. if (ast_entry)
  2408. sa_peer_id = ast_entry->peer_id;
  2409. qdf_spin_unlock_bh(&soc->ast_lock);
  2410. }
  2411. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2412. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2413. if (!peer->bss_peer && peer->nawds_enabled) {
  2414. peer_id = peer->peer_id;
  2415. /* Multicast packets needs to be
  2416. * dropped in case of intra bss forwarding
  2417. */
  2418. if (sa_peer_id == peer->peer_id) {
  2419. QDF_TRACE(QDF_MODULE_ID_DP,
  2420. QDF_TRACE_LEVEL_DEBUG,
  2421. " %s: multicast packet", __func__);
  2422. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2423. continue;
  2424. }
  2425. nbuf_clone = qdf_nbuf_clone(nbuf);
  2426. if (!nbuf_clone) {
  2427. QDF_TRACE(QDF_MODULE_ID_DP,
  2428. QDF_TRACE_LEVEL_ERROR,
  2429. FL("nbuf clone failed"));
  2430. break;
  2431. }
  2432. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2433. msdu_info, peer_id,
  2434. NULL);
  2435. if (nbuf_clone) {
  2436. QDF_TRACE(QDF_MODULE_ID_DP,
  2437. QDF_TRACE_LEVEL_DEBUG,
  2438. FL("pkt send failed"));
  2439. qdf_nbuf_free(nbuf_clone);
  2440. } else {
  2441. if (peer_id != DP_INVALID_PEER)
  2442. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2443. 1, qdf_nbuf_len(nbuf));
  2444. }
  2445. }
  2446. }
  2447. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2448. }
  2449. /**
  2450. * dp_tx_send() - Transmit a frame on a given VAP
  2451. * @soc: DP soc handle
  2452. * @vdev_id: id of DP vdev handle
  2453. * @nbuf: skb
  2454. *
  2455. * Entry point for Core Tx layer (DP_TX) invoked from
  2456. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2457. * cases
  2458. *
  2459. * Return: NULL on success,
  2460. * nbuf when it fails to send
  2461. */
  2462. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2463. qdf_nbuf_t nbuf)
  2464. {
  2465. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2466. uint16_t peer_id = HTT_INVALID_PEER;
  2467. /*
  2468. * doing a memzero is causing additional function call overhead
  2469. * so doing static stack clearing
  2470. */
  2471. struct dp_tx_msdu_info_s msdu_info = {0};
  2472. struct dp_vdev *vdev = NULL;
  2473. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2474. return nbuf;
  2475. /*
  2476. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2477. * this in per packet path.
  2478. *
  2479. * As in this path vdev memory is already protected with netdev
  2480. * tx lock
  2481. */
  2482. vdev = soc->vdev_id_map[vdev_id];
  2483. if (qdf_unlikely(!vdev))
  2484. return nbuf;
  2485. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2486. QDF_MAC_ADDR_REF(nbuf->data));
  2487. /*
  2488. * Set Default Host TID value to invalid TID
  2489. * (TID override disabled)
  2490. */
  2491. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2492. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2493. if (qdf_unlikely(vdev->mesh_vdev)) {
  2494. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2495. &msdu_info);
  2496. if (!nbuf_mesh) {
  2497. dp_verbose_debug("Extracting mesh metadata failed");
  2498. return nbuf;
  2499. }
  2500. nbuf = nbuf_mesh;
  2501. }
  2502. /*
  2503. * Get HW Queue to use for this frame.
  2504. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2505. * dedicated for data and 1 for command.
  2506. * "queue_id" maps to one hardware ring.
  2507. * With each ring, we also associate a unique Tx descriptor pool
  2508. * to minimize lock contention for these resources.
  2509. */
  2510. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2511. /*
  2512. * TCL H/W supports 2 DSCP-TID mapping tables.
  2513. * Table 1 - Default DSCP-TID mapping table
  2514. * Table 2 - 1 DSCP-TID override table
  2515. *
  2516. * If we need a different DSCP-TID mapping for this vap,
  2517. * call tid_classify to extract DSCP/ToS from frame and
  2518. * map to a TID and store in msdu_info. This is later used
  2519. * to fill in TCL Input descriptor (per-packet TID override).
  2520. */
  2521. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2522. /*
  2523. * Classify the frame and call corresponding
  2524. * "prepare" function which extracts the segment (TSO)
  2525. * and fragmentation information (for TSO , SG, ME, or Raw)
  2526. * into MSDU_INFO structure which is later used to fill
  2527. * SW and HW descriptors.
  2528. */
  2529. if (qdf_nbuf_is_tso(nbuf)) {
  2530. dp_verbose_debug("TSO frame %pK", vdev);
  2531. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2532. qdf_nbuf_len(nbuf));
  2533. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2534. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2535. qdf_nbuf_len(nbuf));
  2536. return nbuf;
  2537. }
  2538. goto send_multiple;
  2539. }
  2540. /* SG */
  2541. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2542. struct dp_tx_seg_info_s seg_info = {0};
  2543. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2544. if (!nbuf)
  2545. return NULL;
  2546. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2547. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2548. qdf_nbuf_len(nbuf));
  2549. goto send_multiple;
  2550. }
  2551. #ifdef ATH_SUPPORT_IQUE
  2552. /* Mcast to Ucast Conversion*/
  2553. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2554. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2555. qdf_nbuf_data(nbuf);
  2556. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2557. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2558. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2559. DP_STATS_INC_PKT(vdev,
  2560. tx_i.mcast_en.mcast_pkt, 1,
  2561. qdf_nbuf_len(nbuf));
  2562. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2563. QDF_STATUS_SUCCESS) {
  2564. return NULL;
  2565. }
  2566. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2567. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2568. QDF_STATUS_SUCCESS) {
  2569. return NULL;
  2570. }
  2571. }
  2572. }
  2573. }
  2574. #endif
  2575. /* RAW */
  2576. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2577. struct dp_tx_seg_info_s seg_info = {0};
  2578. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2579. if (!nbuf)
  2580. return NULL;
  2581. dp_verbose_debug("Raw frame %pK", vdev);
  2582. goto send_multiple;
  2583. }
  2584. if (qdf_unlikely(vdev->nawds_enabled)) {
  2585. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2586. qdf_nbuf_data(nbuf);
  2587. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2588. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2589. peer_id = DP_INVALID_PEER;
  2590. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2591. 1, qdf_nbuf_len(nbuf));
  2592. }
  2593. /* Single linear frame */
  2594. /*
  2595. * If nbuf is a simple linear frame, use send_single function to
  2596. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2597. * SRNG. There is no need to setup a MSDU extension descriptor.
  2598. */
  2599. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2600. return nbuf;
  2601. send_multiple:
  2602. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2603. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2604. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2605. return nbuf;
  2606. }
  2607. /**
  2608. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2609. * case to vaoid check in perpkt path.
  2610. * @soc: DP soc handle
  2611. * @vdev_id: id of DP vdev handle
  2612. * @nbuf: skb
  2613. *
  2614. * Entry point for Core Tx layer (DP_TX) invoked from
  2615. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2616. * with special condition to avoid per pkt check in dp_tx_send
  2617. *
  2618. * Return: NULL on success,
  2619. * nbuf when it fails to send
  2620. */
  2621. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2622. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2623. {
  2624. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2625. struct dp_vdev *vdev = NULL;
  2626. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2627. return nbuf;
  2628. /*
  2629. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2630. * this in per packet path.
  2631. *
  2632. * As in this path vdev memory is already protected with netdev
  2633. * tx lock
  2634. */
  2635. vdev = soc->vdev_id_map[vdev_id];
  2636. if (qdf_unlikely(!vdev))
  2637. return nbuf;
  2638. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2639. == QDF_STATUS_E_FAILURE)) {
  2640. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2641. return nbuf;
  2642. }
  2643. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2644. }
  2645. /**
  2646. * dp_tx_reinject_handler() - Tx Reinject Handler
  2647. * @soc: datapath soc handle
  2648. * @vdev: datapath vdev handle
  2649. * @tx_desc: software descriptor head pointer
  2650. * @status : Tx completion status from HTT descriptor
  2651. *
  2652. * This function reinjects frames back to Target.
  2653. * Todo - Host queue needs to be added
  2654. *
  2655. * Return: none
  2656. */
  2657. static
  2658. void dp_tx_reinject_handler(struct dp_soc *soc,
  2659. struct dp_vdev *vdev,
  2660. struct dp_tx_desc_s *tx_desc,
  2661. uint8_t *status)
  2662. {
  2663. struct dp_peer *peer = NULL;
  2664. uint32_t peer_id = HTT_INVALID_PEER;
  2665. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2666. qdf_nbuf_t nbuf_copy = NULL;
  2667. struct dp_tx_msdu_info_s msdu_info;
  2668. #ifdef WDS_VENDOR_EXTENSION
  2669. int is_mcast = 0, is_ucast = 0;
  2670. int num_peers_3addr = 0;
  2671. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2672. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2673. #endif
  2674. qdf_assert(vdev);
  2675. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2676. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2677. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2678. "%s Tx reinject path", __func__);
  2679. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2680. qdf_nbuf_len(tx_desc->nbuf));
  2681. #ifdef WDS_VENDOR_EXTENSION
  2682. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2683. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2684. } else {
  2685. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2686. }
  2687. is_ucast = !is_mcast;
  2688. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2689. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2690. if (peer->bss_peer)
  2691. continue;
  2692. /* Detect wds peers that use 3-addr framing for mcast.
  2693. * if there are any, the bss_peer is used to send the
  2694. * the mcast frame using 3-addr format. all wds enabled
  2695. * peers that use 4-addr framing for mcast frames will
  2696. * be duplicated and sent as 4-addr frames below.
  2697. */
  2698. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2699. num_peers_3addr = 1;
  2700. break;
  2701. }
  2702. }
  2703. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2704. #endif
  2705. if (qdf_unlikely(vdev->mesh_vdev)) {
  2706. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2707. } else {
  2708. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2709. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2710. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2711. #ifdef WDS_VENDOR_EXTENSION
  2712. /*
  2713. * . if 3-addr STA, then send on BSS Peer
  2714. * . if Peer WDS enabled and accept 4-addr mcast,
  2715. * send mcast on that peer only
  2716. * . if Peer WDS enabled and accept 4-addr ucast,
  2717. * send ucast on that peer only
  2718. */
  2719. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2720. (peer->wds_enabled &&
  2721. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2722. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2723. #else
  2724. ((peer->bss_peer &&
  2725. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2726. #endif
  2727. peer_id = DP_INVALID_PEER;
  2728. nbuf_copy = qdf_nbuf_copy(nbuf);
  2729. if (!nbuf_copy) {
  2730. QDF_TRACE(QDF_MODULE_ID_DP,
  2731. QDF_TRACE_LEVEL_DEBUG,
  2732. FL("nbuf copy failed"));
  2733. break;
  2734. }
  2735. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2736. nbuf_copy,
  2737. &msdu_info,
  2738. peer_id,
  2739. NULL);
  2740. if (nbuf_copy) {
  2741. QDF_TRACE(QDF_MODULE_ID_DP,
  2742. QDF_TRACE_LEVEL_DEBUG,
  2743. FL("pkt send failed"));
  2744. qdf_nbuf_free(nbuf_copy);
  2745. }
  2746. }
  2747. }
  2748. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2749. }
  2750. qdf_nbuf_free(nbuf);
  2751. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2752. }
  2753. /**
  2754. * dp_tx_inspect_handler() - Tx Inspect Handler
  2755. * @soc: datapath soc handle
  2756. * @vdev: datapath vdev handle
  2757. * @tx_desc: software descriptor head pointer
  2758. * @status : Tx completion status from HTT descriptor
  2759. *
  2760. * Handles Tx frames sent back to Host for inspection
  2761. * (ProxyARP)
  2762. *
  2763. * Return: none
  2764. */
  2765. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2766. struct dp_vdev *vdev,
  2767. struct dp_tx_desc_s *tx_desc,
  2768. uint8_t *status)
  2769. {
  2770. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2771. "%s Tx inspect path",
  2772. __func__);
  2773. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2774. qdf_nbuf_len(tx_desc->nbuf));
  2775. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2776. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2777. }
  2778. #ifdef FEATURE_PERPKT_INFO
  2779. /**
  2780. * dp_get_completion_indication_for_stack() - send completion to stack
  2781. * @soc : dp_soc handle
  2782. * @pdev: dp_pdev handle
  2783. * @peer: dp peer handle
  2784. * @ts: transmit completion status structure
  2785. * @netbuf: Buffer pointer for free
  2786. *
  2787. * This function is used for indication whether buffer needs to be
  2788. * sent to stack for freeing or not
  2789. */
  2790. QDF_STATUS
  2791. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2792. struct dp_pdev *pdev,
  2793. struct dp_peer *peer,
  2794. struct hal_tx_completion_status *ts,
  2795. qdf_nbuf_t netbuf,
  2796. uint64_t time_latency)
  2797. {
  2798. struct tx_capture_hdr *ppdu_hdr;
  2799. uint16_t peer_id = ts->peer_id;
  2800. uint32_t ppdu_id = ts->ppdu_id;
  2801. uint8_t first_msdu = ts->first_msdu;
  2802. uint8_t last_msdu = ts->last_msdu;
  2803. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2804. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2805. !pdev->latency_capture_enable))
  2806. return QDF_STATUS_E_NOSUPPORT;
  2807. if (!peer) {
  2808. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2809. FL("Peer Invalid"));
  2810. return QDF_STATUS_E_INVAL;
  2811. }
  2812. if (pdev->mcopy_mode) {
  2813. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2814. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2815. * for each MPDU
  2816. */
  2817. if (pdev->mcopy_mode == M_COPY) {
  2818. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2819. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2820. return QDF_STATUS_E_INVAL;
  2821. }
  2822. }
  2823. if (!first_msdu)
  2824. return QDF_STATUS_E_INVAL;
  2825. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2826. pdev->m_copy_id.tx_peer_id = peer_id;
  2827. }
  2828. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2829. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2830. if (!netbuf) {
  2831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2832. FL("No headroom"));
  2833. return QDF_STATUS_E_NOMEM;
  2834. }
  2835. }
  2836. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2837. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2838. FL("No headroom"));
  2839. return QDF_STATUS_E_NOMEM;
  2840. }
  2841. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2842. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2843. QDF_MAC_ADDR_SIZE);
  2844. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2845. QDF_MAC_ADDR_SIZE);
  2846. ppdu_hdr->ppdu_id = ppdu_id;
  2847. ppdu_hdr->peer_id = peer_id;
  2848. ppdu_hdr->first_msdu = first_msdu;
  2849. ppdu_hdr->last_msdu = last_msdu;
  2850. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2851. ppdu_hdr->tsf = ts->tsf;
  2852. ppdu_hdr->time_latency = time_latency;
  2853. }
  2854. return QDF_STATUS_SUCCESS;
  2855. }
  2856. /**
  2857. * dp_send_completion_to_stack() - send completion to stack
  2858. * @soc : dp_soc handle
  2859. * @pdev: dp_pdev handle
  2860. * @peer_id: peer_id of the peer for which completion came
  2861. * @ppdu_id: ppdu_id
  2862. * @netbuf: Buffer pointer for free
  2863. *
  2864. * This function is used to send completion to stack
  2865. * to free buffer
  2866. */
  2867. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2868. uint16_t peer_id, uint32_t ppdu_id,
  2869. qdf_nbuf_t netbuf)
  2870. {
  2871. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2872. netbuf, peer_id,
  2873. WDI_NO_VAL, pdev->pdev_id);
  2874. }
  2875. #else
  2876. static QDF_STATUS
  2877. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2878. struct dp_pdev *pdev,
  2879. struct dp_peer *peer,
  2880. struct hal_tx_completion_status *ts,
  2881. qdf_nbuf_t netbuf,
  2882. uint64_t time_latency)
  2883. {
  2884. return QDF_STATUS_E_NOSUPPORT;
  2885. }
  2886. static void
  2887. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2888. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2889. {
  2890. }
  2891. #endif
  2892. /**
  2893. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2894. * @soc: Soc handle
  2895. * @desc: software Tx descriptor to be processed
  2896. *
  2897. * Return: none
  2898. */
  2899. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2900. struct dp_tx_desc_s *desc)
  2901. {
  2902. qdf_nbuf_t nbuf = desc->nbuf;
  2903. /* nbuf already freed in vdev detach path */
  2904. if (!nbuf)
  2905. return;
  2906. /* If it is TDLS mgmt, don't unmap or free the frame */
  2907. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2908. return dp_non_std_tx_comp_free_buff(soc, desc);
  2909. /* 0 : MSDU buffer, 1 : MLE */
  2910. if (desc->msdu_ext_desc) {
  2911. /* TSO free */
  2912. if (hal_tx_ext_desc_get_tso_enable(
  2913. desc->msdu_ext_desc->vaddr)) {
  2914. /* unmap eash TSO seg before free the nbuf */
  2915. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2916. desc->tso_num_desc);
  2917. qdf_nbuf_free(nbuf);
  2918. return;
  2919. }
  2920. }
  2921. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2922. QDF_DMA_TO_DEVICE, nbuf->len);
  2923. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2924. return dp_mesh_tx_comp_free_buff(soc, desc);
  2925. qdf_nbuf_free(nbuf);
  2926. }
  2927. #ifdef MESH_MODE_SUPPORT
  2928. /**
  2929. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2930. * in mesh meta header
  2931. * @tx_desc: software descriptor head pointer
  2932. * @ts: pointer to tx completion stats
  2933. * Return: none
  2934. */
  2935. static
  2936. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2937. struct hal_tx_completion_status *ts)
  2938. {
  2939. struct meta_hdr_s *mhdr;
  2940. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2941. if (!tx_desc->msdu_ext_desc) {
  2942. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2943. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2944. "netbuf %pK offset %d",
  2945. netbuf, tx_desc->pkt_offset);
  2946. return;
  2947. }
  2948. }
  2949. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2950. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2951. "netbuf %pK offset %lu", netbuf,
  2952. sizeof(struct meta_hdr_s));
  2953. return;
  2954. }
  2955. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2956. mhdr->rssi = ts->ack_frame_rssi;
  2957. mhdr->band = tx_desc->pdev->operating_channel.band;
  2958. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2959. }
  2960. #else
  2961. static
  2962. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2963. struct hal_tx_completion_status *ts)
  2964. {
  2965. }
  2966. #endif
  2967. #ifdef QCA_PEER_EXT_STATS
  2968. /*
  2969. * dp_tx_compute_tid_delay() - Compute per TID delay
  2970. * @stats: Per TID delay stats
  2971. * @tx_desc: Software Tx descriptor
  2972. *
  2973. * Compute the software enqueue and hw enqueue delays and
  2974. * update the respective histograms
  2975. *
  2976. * Return: void
  2977. */
  2978. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2979. struct dp_tx_desc_s *tx_desc)
  2980. {
  2981. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2982. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2983. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2984. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2985. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2986. timestamp_hw_enqueue = tx_desc->timestamp;
  2987. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2988. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2989. timestamp_hw_enqueue);
  2990. /*
  2991. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2992. */
  2993. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2994. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2995. }
  2996. /*
  2997. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2998. * @peer: DP peer context
  2999. * @tx_desc: Tx software descriptor
  3000. * @tid: Transmission ID
  3001. * @ring_id: Rx CPU context ID/CPU_ID
  3002. *
  3003. * Update the peer extended stats. These are enhanced other
  3004. * delay stats per msdu level.
  3005. *
  3006. * Return: void
  3007. */
  3008. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3009. struct dp_tx_desc_s *tx_desc,
  3010. uint8_t tid, uint8_t ring_id)
  3011. {
  3012. struct dp_pdev *pdev = peer->vdev->pdev;
  3013. struct dp_soc *soc = NULL;
  3014. struct cdp_peer_ext_stats *pext_stats = NULL;
  3015. soc = pdev->soc;
  3016. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3017. return;
  3018. pext_stats = peer->pext_stats;
  3019. qdf_assert(pext_stats);
  3020. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3021. /*
  3022. * For non-TID packets use the TID 9
  3023. */
  3024. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3025. tid = CDP_MAX_DATA_TIDS - 1;
  3026. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3027. tx_desc);
  3028. }
  3029. #else
  3030. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3031. struct dp_tx_desc_s *tx_desc,
  3032. uint8_t tid, uint8_t ring_id)
  3033. {
  3034. }
  3035. #endif
  3036. /**
  3037. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3038. * to pass in correct fields
  3039. *
  3040. * @vdev: pdev handle
  3041. * @tx_desc: tx descriptor
  3042. * @tid: tid value
  3043. * @ring_id: TCL or WBM ring number for transmit path
  3044. * Return: none
  3045. */
  3046. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3047. struct dp_tx_desc_s *tx_desc,
  3048. uint8_t tid, uint8_t ring_id)
  3049. {
  3050. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3051. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3052. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3053. return;
  3054. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3055. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3056. timestamp_hw_enqueue = tx_desc->timestamp;
  3057. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3058. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3059. timestamp_hw_enqueue);
  3060. interframe_delay = (uint32_t)(timestamp_ingress -
  3061. vdev->prev_tx_enq_tstamp);
  3062. /*
  3063. * Delay in software enqueue
  3064. */
  3065. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3066. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3067. /*
  3068. * Delay between packet enqueued to HW and Tx completion
  3069. */
  3070. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3071. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3072. /*
  3073. * Update interframe delay stats calculated at hardstart receive point.
  3074. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3075. * interframe delay will not be calculate correctly for 1st frame.
  3076. * On the other side, this will help in avoiding extra per packet check
  3077. * of !vdev->prev_tx_enq_tstamp.
  3078. */
  3079. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3080. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3081. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3082. }
  3083. #ifdef DISABLE_DP_STATS
  3084. static
  3085. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3086. {
  3087. }
  3088. #else
  3089. static
  3090. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3091. {
  3092. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3093. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3094. if (subtype != QDF_PROTO_INVALID)
  3095. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3096. }
  3097. #endif
  3098. /**
  3099. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3100. * per wbm ring
  3101. *
  3102. * @tx_desc: software descriptor head pointer
  3103. * @ts: Tx completion status
  3104. * @peer: peer handle
  3105. * @ring_id: ring number
  3106. *
  3107. * Return: None
  3108. */
  3109. static inline void
  3110. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3111. struct hal_tx_completion_status *ts,
  3112. struct dp_peer *peer, uint8_t ring_id)
  3113. {
  3114. struct dp_pdev *pdev = peer->vdev->pdev;
  3115. struct dp_soc *soc = NULL;
  3116. uint8_t mcs, pkt_type;
  3117. uint8_t tid = ts->tid;
  3118. uint32_t length;
  3119. struct cdp_tid_tx_stats *tid_stats;
  3120. if (!pdev)
  3121. return;
  3122. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3123. tid = CDP_MAX_DATA_TIDS - 1;
  3124. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3125. soc = pdev->soc;
  3126. mcs = ts->mcs;
  3127. pkt_type = ts->pkt_type;
  3128. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3129. dp_err("Release source is not from TQM");
  3130. return;
  3131. }
  3132. length = qdf_nbuf_len(tx_desc->nbuf);
  3133. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3134. if (qdf_unlikely(pdev->delay_stats_flag))
  3135. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3136. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3137. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3138. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3139. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3140. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3141. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3142. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3143. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3144. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3145. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3146. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3147. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3148. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3149. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3150. /*
  3151. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3152. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3153. * are no completions for failed cases. Hence updating tx_failed from
  3154. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3155. * then this has to be removed
  3156. */
  3157. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3158. peer->stats.tx.dropped.fw_rem_notx +
  3159. peer->stats.tx.dropped.fw_rem_tx +
  3160. peer->stats.tx.dropped.age_out +
  3161. peer->stats.tx.dropped.fw_reason1 +
  3162. peer->stats.tx.dropped.fw_reason2 +
  3163. peer->stats.tx.dropped.fw_reason3;
  3164. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3165. tid_stats->tqm_status_cnt[ts->status]++;
  3166. }
  3167. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3168. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3169. return;
  3170. }
  3171. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3172. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3173. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3174. /*
  3175. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3176. * Return from here if HTT PPDU events are enabled.
  3177. */
  3178. if (!(soc->process_tx_status))
  3179. return;
  3180. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3181. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3182. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3183. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3184. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3185. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3186. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3187. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3188. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3189. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3190. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3191. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3192. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3193. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3194. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3195. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3196. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3197. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3198. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3199. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3200. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3201. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3202. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3203. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3204. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3205. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3206. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3207. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3208. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3209. &peer->stats, ts->peer_id,
  3210. UPDATE_PEER_STATS, pdev->pdev_id);
  3211. #endif
  3212. }
  3213. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3214. /**
  3215. * dp_tx_flow_pool_lock() - take flow pool lock
  3216. * @soc: core txrx main context
  3217. * @tx_desc: tx desc
  3218. *
  3219. * Return: None
  3220. */
  3221. static inline
  3222. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3223. struct dp_tx_desc_s *tx_desc)
  3224. {
  3225. struct dp_tx_desc_pool_s *pool;
  3226. uint8_t desc_pool_id;
  3227. desc_pool_id = tx_desc->pool_id;
  3228. pool = &soc->tx_desc[desc_pool_id];
  3229. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3230. }
  3231. /**
  3232. * dp_tx_flow_pool_unlock() - release flow pool lock
  3233. * @soc: core txrx main context
  3234. * @tx_desc: tx desc
  3235. *
  3236. * Return: None
  3237. */
  3238. static inline
  3239. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3240. struct dp_tx_desc_s *tx_desc)
  3241. {
  3242. struct dp_tx_desc_pool_s *pool;
  3243. uint8_t desc_pool_id;
  3244. desc_pool_id = tx_desc->pool_id;
  3245. pool = &soc->tx_desc[desc_pool_id];
  3246. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3247. }
  3248. #else
  3249. static inline
  3250. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3251. {
  3252. }
  3253. static inline
  3254. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3255. {
  3256. }
  3257. #endif
  3258. /**
  3259. * dp_tx_notify_completion() - Notify tx completion for this desc
  3260. * @soc: core txrx main context
  3261. * @vdev: datapath vdev handle
  3262. * @tx_desc: tx desc
  3263. * @netbuf: buffer
  3264. * @status: tx status
  3265. *
  3266. * Return: none
  3267. */
  3268. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3269. struct dp_vdev *vdev,
  3270. struct dp_tx_desc_s *tx_desc,
  3271. qdf_nbuf_t netbuf,
  3272. uint8_t status)
  3273. {
  3274. void *osif_dev;
  3275. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3276. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3277. qdf_assert(tx_desc);
  3278. dp_tx_flow_pool_lock(soc, tx_desc);
  3279. if (!vdev ||
  3280. !vdev->osif_vdev) {
  3281. dp_tx_flow_pool_unlock(soc, tx_desc);
  3282. return;
  3283. }
  3284. osif_dev = vdev->osif_vdev;
  3285. tx_compl_cbk = vdev->tx_comp;
  3286. dp_tx_flow_pool_unlock(soc, tx_desc);
  3287. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3288. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3289. if (tx_compl_cbk)
  3290. tx_compl_cbk(netbuf, osif_dev, flag);
  3291. }
  3292. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3293. * @pdev: pdev handle
  3294. * @tid: tid value
  3295. * @txdesc_ts: timestamp from txdesc
  3296. * @ppdu_id: ppdu id
  3297. *
  3298. * Return: none
  3299. */
  3300. #ifdef FEATURE_PERPKT_INFO
  3301. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3302. struct dp_peer *peer,
  3303. uint8_t tid,
  3304. uint64_t txdesc_ts,
  3305. uint32_t ppdu_id)
  3306. {
  3307. uint64_t delta_ms;
  3308. struct cdp_tx_sojourn_stats *sojourn_stats;
  3309. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3310. return;
  3311. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3312. tid >= CDP_DATA_TID_MAX))
  3313. return;
  3314. if (qdf_unlikely(!pdev->sojourn_buf))
  3315. return;
  3316. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3317. qdf_nbuf_data(pdev->sojourn_buf);
  3318. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3319. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3320. txdesc_ts;
  3321. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3322. delta_ms);
  3323. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3324. sojourn_stats->num_msdus[tid] = 1;
  3325. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3326. peer->avg_sojourn_msdu[tid].internal;
  3327. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3328. pdev->sojourn_buf, HTT_INVALID_PEER,
  3329. WDI_NO_VAL, pdev->pdev_id);
  3330. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3331. sojourn_stats->num_msdus[tid] = 0;
  3332. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3333. }
  3334. #else
  3335. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3336. struct dp_peer *peer,
  3337. uint8_t tid,
  3338. uint64_t txdesc_ts,
  3339. uint32_t ppdu_id)
  3340. {
  3341. }
  3342. #endif
  3343. /**
  3344. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3345. * @soc: DP Soc handle
  3346. * @tx_desc: software Tx descriptor
  3347. * @ts : Tx completion status from HAL/HTT descriptor
  3348. *
  3349. * Return: none
  3350. */
  3351. static inline void
  3352. dp_tx_comp_process_desc(struct dp_soc *soc,
  3353. struct dp_tx_desc_s *desc,
  3354. struct hal_tx_completion_status *ts,
  3355. struct dp_peer *peer)
  3356. {
  3357. uint64_t time_latency = 0;
  3358. /*
  3359. * m_copy/tx_capture modes are not supported for
  3360. * scatter gather packets
  3361. */
  3362. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3363. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3364. desc->timestamp);
  3365. }
  3366. if (!(desc->msdu_ext_desc)) {
  3367. if (QDF_STATUS_SUCCESS ==
  3368. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3369. return;
  3370. }
  3371. if (QDF_STATUS_SUCCESS ==
  3372. dp_get_completion_indication_for_stack(soc,
  3373. desc->pdev,
  3374. peer, ts,
  3375. desc->nbuf,
  3376. time_latency)) {
  3377. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3378. QDF_DMA_TO_DEVICE,
  3379. desc->nbuf->len);
  3380. dp_send_completion_to_stack(soc,
  3381. desc->pdev,
  3382. ts->peer_id,
  3383. ts->ppdu_id,
  3384. desc->nbuf);
  3385. return;
  3386. }
  3387. }
  3388. dp_tx_comp_free_buf(soc, desc);
  3389. }
  3390. #ifdef DISABLE_DP_STATS
  3391. /**
  3392. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3393. * @soc: core txrx main context
  3394. * @tx_desc: tx desc
  3395. * @status: tx status
  3396. *
  3397. * Return: none
  3398. */
  3399. static inline
  3400. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3401. struct dp_vdev *vdev,
  3402. struct dp_tx_desc_s *tx_desc,
  3403. uint8_t status)
  3404. {
  3405. }
  3406. #else
  3407. static inline
  3408. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3409. struct dp_vdev *vdev,
  3410. struct dp_tx_desc_s *tx_desc,
  3411. uint8_t status)
  3412. {
  3413. void *osif_dev;
  3414. ol_txrx_stats_rx_fp stats_cbk;
  3415. uint8_t pkt_type;
  3416. qdf_assert(tx_desc);
  3417. if (!vdev ||
  3418. !vdev->osif_vdev ||
  3419. !vdev->stats_cb)
  3420. return;
  3421. osif_dev = vdev->osif_vdev;
  3422. stats_cbk = vdev->stats_cb;
  3423. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3424. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3425. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3426. &pkt_type);
  3427. }
  3428. #endif
  3429. /**
  3430. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3431. * @soc: DP soc handle
  3432. * @tx_desc: software descriptor head pointer
  3433. * @ts: Tx completion status
  3434. * @peer: peer handle
  3435. * @ring_id: ring number
  3436. *
  3437. * Return: none
  3438. */
  3439. static inline
  3440. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3441. struct dp_tx_desc_s *tx_desc,
  3442. struct hal_tx_completion_status *ts,
  3443. struct dp_peer *peer, uint8_t ring_id)
  3444. {
  3445. uint32_t length;
  3446. qdf_ether_header_t *eh;
  3447. struct dp_vdev *vdev = NULL;
  3448. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3449. uint8_t dp_status;
  3450. if (!nbuf) {
  3451. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3452. goto out;
  3453. }
  3454. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3455. length = qdf_nbuf_len(nbuf);
  3456. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3457. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3458. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3459. QDF_TRACE_DEFAULT_PDEV_ID,
  3460. qdf_nbuf_data_addr(nbuf),
  3461. sizeof(qdf_nbuf_data(nbuf)),
  3462. tx_desc->id,
  3463. dp_status));
  3464. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3465. "-------------------- \n"
  3466. "Tx Completion Stats: \n"
  3467. "-------------------- \n"
  3468. "ack_frame_rssi = %d \n"
  3469. "first_msdu = %d \n"
  3470. "last_msdu = %d \n"
  3471. "msdu_part_of_amsdu = %d \n"
  3472. "rate_stats valid = %d \n"
  3473. "bw = %d \n"
  3474. "pkt_type = %d \n"
  3475. "stbc = %d \n"
  3476. "ldpc = %d \n"
  3477. "sgi = %d \n"
  3478. "mcs = %d \n"
  3479. "ofdma = %d \n"
  3480. "tones_in_ru = %d \n"
  3481. "tsf = %d \n"
  3482. "ppdu_id = %d \n"
  3483. "transmit_cnt = %d \n"
  3484. "tid = %d \n"
  3485. "peer_id = %d\n",
  3486. ts->ack_frame_rssi, ts->first_msdu,
  3487. ts->last_msdu, ts->msdu_part_of_amsdu,
  3488. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3489. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3490. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3491. ts->transmit_cnt, ts->tid, ts->peer_id);
  3492. /* Update SoC level stats */
  3493. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3494. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3495. if (!peer) {
  3496. dp_err_rl("peer is null or deletion in progress");
  3497. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3498. goto out;
  3499. }
  3500. vdev = peer->vdev;
  3501. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3502. /* Update per-packet stats for mesh mode */
  3503. if (qdf_unlikely(vdev->mesh_vdev) &&
  3504. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3505. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3506. /* Update peer level stats */
  3507. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3508. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3509. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3510. if ((peer->vdev->tx_encap_type ==
  3511. htt_cmn_pkt_type_ethernet) &&
  3512. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3513. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3514. }
  3515. }
  3516. } else {
  3517. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3518. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3519. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3520. if (qdf_unlikely(peer->in_twt)) {
  3521. DP_STATS_INC_PKT(peer,
  3522. tx.tx_success_twt,
  3523. 1, length);
  3524. }
  3525. }
  3526. }
  3527. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3528. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3529. #ifdef QCA_SUPPORT_RDK_STATS
  3530. if (soc->rdkstats_enabled)
  3531. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3532. tx_desc->timestamp,
  3533. ts->ppdu_id);
  3534. #endif
  3535. out:
  3536. return;
  3537. }
  3538. /**
  3539. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3540. * @soc: core txrx main context
  3541. * @comp_head: software descriptor head pointer
  3542. * @ring_id: ring number
  3543. *
  3544. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3545. * and release the software descriptors after processing is complete
  3546. *
  3547. * Return: none
  3548. */
  3549. static void
  3550. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3551. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3552. {
  3553. struct dp_tx_desc_s *desc;
  3554. struct dp_tx_desc_s *next;
  3555. struct hal_tx_completion_status ts;
  3556. struct dp_peer *peer = NULL;
  3557. uint16_t peer_id = DP_INVALID_PEER;
  3558. qdf_nbuf_t netbuf;
  3559. desc = comp_head;
  3560. while (desc) {
  3561. if (peer_id != desc->peer_id) {
  3562. if (peer)
  3563. dp_peer_unref_delete(peer,
  3564. DP_MOD_ID_TX_COMP);
  3565. peer_id = desc->peer_id;
  3566. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3567. DP_MOD_ID_TX_COMP);
  3568. }
  3569. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3570. struct dp_pdev *pdev = desc->pdev;
  3571. if (qdf_likely(peer)) {
  3572. /*
  3573. * Increment peer statistics
  3574. * Minimal statistics update done here
  3575. */
  3576. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3577. desc->length);
  3578. if (desc->tx_status !=
  3579. HAL_TX_TQM_RR_FRAME_ACKED)
  3580. DP_STATS_INC(peer, tx.tx_failed, 1);
  3581. }
  3582. qdf_assert(pdev);
  3583. dp_tx_outstanding_dec(pdev);
  3584. /*
  3585. * Calling a QDF WRAPPER here is creating signifcant
  3586. * performance impact so avoided the wrapper call here
  3587. */
  3588. next = desc->next;
  3589. qdf_mem_unmap_nbytes_single(soc->osdev,
  3590. desc->dma_addr,
  3591. QDF_DMA_TO_DEVICE,
  3592. desc->length);
  3593. qdf_nbuf_free(desc->nbuf);
  3594. dp_tx_desc_free(soc, desc, desc->pool_id);
  3595. desc = next;
  3596. continue;
  3597. }
  3598. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3599. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3600. netbuf = desc->nbuf;
  3601. /* check tx complete notification */
  3602. if (peer &&
  3603. QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3604. dp_tx_notify_completion(soc, peer->vdev, desc,
  3605. netbuf, ts.status);
  3606. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3607. next = desc->next;
  3608. dp_tx_desc_release(desc, desc->pool_id);
  3609. desc = next;
  3610. }
  3611. if (peer)
  3612. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3613. }
  3614. /**
  3615. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3616. * @tx_desc: software descriptor head pointer
  3617. * @status : Tx completion status from HTT descriptor
  3618. * @ring_id: ring number
  3619. *
  3620. * This function will process HTT Tx indication messages from Target
  3621. *
  3622. * Return: none
  3623. */
  3624. static
  3625. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3626. uint8_t ring_id)
  3627. {
  3628. uint8_t tx_status;
  3629. struct dp_pdev *pdev;
  3630. struct dp_vdev *vdev;
  3631. struct dp_soc *soc;
  3632. struct hal_tx_completion_status ts = {0};
  3633. uint32_t *htt_desc = (uint32_t *)status;
  3634. struct dp_peer *peer;
  3635. struct cdp_tid_tx_stats *tid_stats = NULL;
  3636. struct htt_soc *htt_handle;
  3637. /*
  3638. * If the descriptor is already freed in vdev_detach,
  3639. * continue to next descriptor
  3640. */
  3641. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3642. QDF_TRACE(QDF_MODULE_ID_DP,
  3643. QDF_TRACE_LEVEL_INFO,
  3644. "Descriptor freed in vdev_detach %d",
  3645. tx_desc->id);
  3646. return;
  3647. }
  3648. pdev = tx_desc->pdev;
  3649. soc = pdev->soc;
  3650. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3651. QDF_TRACE(QDF_MODULE_ID_DP,
  3652. QDF_TRACE_LEVEL_INFO,
  3653. "pdev in down state %d",
  3654. tx_desc->id);
  3655. dp_tx_comp_free_buf(soc, tx_desc);
  3656. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3657. return;
  3658. }
  3659. qdf_assert(tx_desc->pdev);
  3660. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  3661. DP_MOD_ID_HTT_COMP);
  3662. if (!vdev)
  3663. return;
  3664. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3665. htt_handle = (struct htt_soc *)soc->htt_handle;
  3666. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3667. switch (tx_status) {
  3668. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3669. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3670. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3671. {
  3672. uint8_t tid;
  3673. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3674. ts.peer_id =
  3675. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3676. htt_desc[2]);
  3677. ts.tid =
  3678. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3679. htt_desc[2]);
  3680. } else {
  3681. ts.peer_id = HTT_INVALID_PEER;
  3682. ts.tid = HTT_INVALID_TID;
  3683. }
  3684. ts.ppdu_id =
  3685. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3686. htt_desc[1]);
  3687. ts.ack_frame_rssi =
  3688. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3689. htt_desc[1]);
  3690. ts.tsf = htt_desc[3];
  3691. ts.first_msdu = 1;
  3692. ts.last_msdu = 1;
  3693. tid = ts.tid;
  3694. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3695. tid = CDP_MAX_DATA_TIDS - 1;
  3696. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3697. if (qdf_unlikely(pdev->delay_stats_flag))
  3698. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3699. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3700. tid_stats->htt_status_cnt[tx_status]++;
  3701. }
  3702. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3703. DP_MOD_ID_HTT_COMP);
  3704. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3705. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3706. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3707. if (qdf_likely(peer))
  3708. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3709. break;
  3710. }
  3711. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3712. {
  3713. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3714. break;
  3715. }
  3716. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3717. {
  3718. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3719. break;
  3720. }
  3721. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3722. {
  3723. dp_tx_mec_handler(vdev, status);
  3724. break;
  3725. }
  3726. default:
  3727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3728. "%s Invalid HTT tx_status %d\n",
  3729. __func__, tx_status);
  3730. break;
  3731. }
  3732. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3733. }
  3734. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3735. static inline
  3736. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3737. {
  3738. bool limit_hit = false;
  3739. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3740. limit_hit =
  3741. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3742. if (limit_hit)
  3743. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3744. return limit_hit;
  3745. }
  3746. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3747. {
  3748. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3749. }
  3750. #else
  3751. static inline
  3752. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3753. {
  3754. return false;
  3755. }
  3756. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3757. {
  3758. return false;
  3759. }
  3760. #endif
  3761. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3762. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3763. uint32_t quota)
  3764. {
  3765. void *tx_comp_hal_desc;
  3766. uint8_t buffer_src;
  3767. uint8_t pool_id;
  3768. uint32_t tx_desc_id;
  3769. struct dp_tx_desc_s *tx_desc = NULL;
  3770. struct dp_tx_desc_s *head_desc = NULL;
  3771. struct dp_tx_desc_s *tail_desc = NULL;
  3772. uint32_t num_processed = 0;
  3773. uint32_t count;
  3774. uint32_t num_avail_for_reap = 0;
  3775. bool force_break = false;
  3776. DP_HIST_INIT();
  3777. more_data:
  3778. /* Re-initialize local variables to be re-used */
  3779. head_desc = NULL;
  3780. tail_desc = NULL;
  3781. count = 0;
  3782. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3783. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3784. return 0;
  3785. }
  3786. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3787. if (num_avail_for_reap >= quota)
  3788. num_avail_for_reap = quota;
  3789. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3790. /* Find head descriptor from completion ring */
  3791. while (qdf_likely(num_avail_for_reap)) {
  3792. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3793. if (qdf_unlikely(!tx_comp_hal_desc))
  3794. break;
  3795. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3796. /* If this buffer was not released by TQM or FW, then it is not
  3797. * Tx completion indication, assert */
  3798. if (qdf_unlikely(buffer_src !=
  3799. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3800. (qdf_unlikely(buffer_src !=
  3801. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3802. uint8_t wbm_internal_error;
  3803. dp_err_rl(
  3804. "Tx comp release_src != TQM | FW but from %d",
  3805. buffer_src);
  3806. hal_dump_comp_desc(tx_comp_hal_desc);
  3807. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3808. /* When WBM sees NULL buffer_addr_info in any of
  3809. * ingress rings it sends an error indication,
  3810. * with wbm_internal_error=1, to a specific ring.
  3811. * The WBM2SW ring used to indicate these errors is
  3812. * fixed in HW, and that ring is being used as Tx
  3813. * completion ring. These errors are not related to
  3814. * Tx completions, and should just be ignored
  3815. */
  3816. wbm_internal_error = hal_get_wbm_internal_error(
  3817. soc->hal_soc,
  3818. tx_comp_hal_desc);
  3819. if (wbm_internal_error) {
  3820. dp_err_rl("Tx comp wbm_internal_error!!");
  3821. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3822. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3823. buffer_src)
  3824. dp_handle_wbm_internal_error(
  3825. soc,
  3826. tx_comp_hal_desc,
  3827. hal_tx_comp_get_buffer_type(
  3828. tx_comp_hal_desc));
  3829. } else {
  3830. dp_err_rl("Tx comp wbm_internal_error false");
  3831. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3832. }
  3833. continue;
  3834. }
  3835. /* Get descriptor id */
  3836. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3837. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3838. DP_TX_DESC_ID_POOL_OS;
  3839. /* Find Tx descriptor */
  3840. tx_desc = dp_tx_desc_find(soc, pool_id,
  3841. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3842. DP_TX_DESC_ID_PAGE_OS,
  3843. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3844. DP_TX_DESC_ID_OFFSET_OS);
  3845. /*
  3846. * If the release source is FW, process the HTT status
  3847. */
  3848. if (qdf_unlikely(buffer_src ==
  3849. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3850. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3851. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3852. htt_tx_status);
  3853. dp_tx_process_htt_completion(tx_desc,
  3854. htt_tx_status, ring_id);
  3855. } else {
  3856. tx_desc->peer_id =
  3857. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3858. tx_desc->tx_status =
  3859. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3860. /*
  3861. * If the fast completion mode is enabled extended
  3862. * metadata from descriptor is not copied
  3863. */
  3864. if (qdf_likely(tx_desc->flags &
  3865. DP_TX_DESC_FLAG_SIMPLE))
  3866. goto add_to_pool;
  3867. /*
  3868. * If the descriptor is already freed in vdev_detach,
  3869. * continue to next descriptor
  3870. */
  3871. if (qdf_unlikely
  3872. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  3873. !tx_desc->flags)) {
  3874. QDF_TRACE(QDF_MODULE_ID_DP,
  3875. QDF_TRACE_LEVEL_INFO,
  3876. "Descriptor freed in vdev_detach %d",
  3877. tx_desc_id);
  3878. continue;
  3879. }
  3880. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3881. QDF_TRACE(QDF_MODULE_ID_DP,
  3882. QDF_TRACE_LEVEL_INFO,
  3883. "pdev in down state %d",
  3884. tx_desc_id);
  3885. dp_tx_comp_free_buf(soc, tx_desc);
  3886. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3887. goto next_desc;
  3888. }
  3889. /* Pool id is not matching. Error */
  3890. if (tx_desc->pool_id != pool_id) {
  3891. QDF_TRACE(QDF_MODULE_ID_DP,
  3892. QDF_TRACE_LEVEL_FATAL,
  3893. "Tx Comp pool id %d not matched %d",
  3894. pool_id, tx_desc->pool_id);
  3895. qdf_assert_always(0);
  3896. }
  3897. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3898. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3899. QDF_TRACE(QDF_MODULE_ID_DP,
  3900. QDF_TRACE_LEVEL_FATAL,
  3901. "Txdesc invalid, flgs = %x,id = %d",
  3902. tx_desc->flags, tx_desc_id);
  3903. qdf_assert_always(0);
  3904. }
  3905. /* Collect hw completion contents */
  3906. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3907. &tx_desc->comp, 1);
  3908. add_to_pool:
  3909. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3910. /* First ring descriptor on the cycle */
  3911. if (!head_desc) {
  3912. head_desc = tx_desc;
  3913. tail_desc = tx_desc;
  3914. }
  3915. tail_desc->next = tx_desc;
  3916. tx_desc->next = NULL;
  3917. tail_desc = tx_desc;
  3918. }
  3919. next_desc:
  3920. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3921. /*
  3922. * Processed packet count is more than given quota
  3923. * stop to processing
  3924. */
  3925. count++;
  3926. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3927. break;
  3928. }
  3929. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3930. /* Process the reaped descriptors */
  3931. if (head_desc)
  3932. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3933. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3934. if (num_processed >= quota)
  3935. force_break = true;
  3936. if (!force_break &&
  3937. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3938. hal_ring_hdl)) {
  3939. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3940. if (!hif_exec_should_yield(soc->hif_handle,
  3941. int_ctx->dp_intr_id))
  3942. goto more_data;
  3943. }
  3944. }
  3945. DP_TX_HIST_STATS_PER_PDEV();
  3946. return num_processed;
  3947. }
  3948. #ifdef FEATURE_WLAN_TDLS
  3949. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3950. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3951. {
  3952. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3953. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3954. DP_MOD_ID_TDLS);
  3955. if (!vdev) {
  3956. dp_err("vdev handle for id %d is NULL", vdev_id);
  3957. return NULL;
  3958. }
  3959. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3960. vdev->is_tdls_frame = true;
  3961. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  3962. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3963. }
  3964. #endif
  3965. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3966. {
  3967. struct wlan_cfg_dp_soc_ctxt *cfg;
  3968. struct dp_soc *soc;
  3969. soc = vdev->pdev->soc;
  3970. if (!soc)
  3971. return;
  3972. cfg = soc->wlan_cfg_ctx;
  3973. if (!cfg)
  3974. return;
  3975. if (vdev->opmode == wlan_op_mode_ndi)
  3976. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3977. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3978. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3979. (vdev->subtype == wlan_op_subtype_p2p_go))
  3980. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3981. else
  3982. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3983. }
  3984. /**
  3985. * dp_tx_vdev_attach() - attach vdev to dp tx
  3986. * @vdev: virtual device instance
  3987. *
  3988. * Return: QDF_STATUS_SUCCESS: success
  3989. * QDF_STATUS_E_RESOURCES: Error return
  3990. */
  3991. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3992. {
  3993. int pdev_id;
  3994. /*
  3995. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3996. */
  3997. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3998. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3999. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4000. vdev->vdev_id);
  4001. pdev_id =
  4002. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4003. vdev->pdev->pdev_id);
  4004. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4005. /*
  4006. * Set HTT Extension Valid bit to 0 by default
  4007. */
  4008. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4009. dp_tx_vdev_update_search_flags(vdev);
  4010. dp_tx_vdev_update_feature_flags(vdev);
  4011. return QDF_STATUS_SUCCESS;
  4012. }
  4013. #ifndef FEATURE_WDS
  4014. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4015. {
  4016. return false;
  4017. }
  4018. #endif
  4019. /**
  4020. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4021. * @vdev: virtual device instance
  4022. *
  4023. * Return: void
  4024. *
  4025. */
  4026. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4027. {
  4028. struct dp_soc *soc = vdev->pdev->soc;
  4029. /*
  4030. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4031. * for TDLS link
  4032. *
  4033. * Enable AddrY (SA based search) only for non-WDS STA and
  4034. * ProxySTA VAP (in HKv1) modes.
  4035. *
  4036. * In all other VAP modes, only DA based search should be
  4037. * enabled
  4038. */
  4039. if (vdev->opmode == wlan_op_mode_sta &&
  4040. vdev->tdls_link_connected)
  4041. vdev->hal_desc_addr_search_flags =
  4042. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4043. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4044. !dp_tx_da_search_override(vdev))
  4045. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4046. else
  4047. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4048. /* Set search type only when peer map v2 messaging is enabled
  4049. * as we will have the search index (AST hash) only when v2 is
  4050. * enabled
  4051. */
  4052. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4053. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4054. else
  4055. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4056. }
  4057. static inline bool
  4058. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4059. struct dp_vdev *vdev,
  4060. struct dp_tx_desc_s *tx_desc)
  4061. {
  4062. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4063. return false;
  4064. /*
  4065. * if vdev is given, then only check whether desc
  4066. * vdev match. if vdev is NULL, then check whether
  4067. * desc pdev match.
  4068. */
  4069. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4070. (tx_desc->pdev == pdev);
  4071. }
  4072. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4073. /**
  4074. * dp_tx_desc_flush() - release resources associated
  4075. * to TX Desc
  4076. *
  4077. * @dp_pdev: Handle to DP pdev structure
  4078. * @vdev: virtual device instance
  4079. * NULL: no specific Vdev is required and check all allcated TX desc
  4080. * on this pdev.
  4081. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4082. *
  4083. * @force_free:
  4084. * true: flush the TX desc.
  4085. * false: only reset the Vdev in each allocated TX desc
  4086. * that associated to current Vdev.
  4087. *
  4088. * This function will go through the TX desc pool to flush
  4089. * the outstanding TX data or reset Vdev to NULL in associated TX
  4090. * Desc.
  4091. */
  4092. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4093. bool force_free)
  4094. {
  4095. uint8_t i;
  4096. uint32_t j;
  4097. uint32_t num_desc, page_id, offset;
  4098. uint16_t num_desc_per_page;
  4099. struct dp_soc *soc = pdev->soc;
  4100. struct dp_tx_desc_s *tx_desc = NULL;
  4101. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4102. if (!vdev && !force_free) {
  4103. dp_err("Reset TX desc vdev, Vdev param is required!");
  4104. return;
  4105. }
  4106. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4107. tx_desc_pool = &soc->tx_desc[i];
  4108. if (!(tx_desc_pool->pool_size) ||
  4109. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4110. !(tx_desc_pool->desc_pages.cacheable_pages))
  4111. continue;
  4112. /*
  4113. * Add flow pool lock protection in case pool is freed
  4114. * due to all tx_desc is recycled when handle TX completion.
  4115. * this is not necessary when do force flush as:
  4116. * a. double lock will happen if dp_tx_desc_release is
  4117. * also trying to acquire it.
  4118. * b. dp interrupt has been disabled before do force TX desc
  4119. * flush in dp_pdev_deinit().
  4120. */
  4121. if (!force_free)
  4122. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4123. num_desc = tx_desc_pool->pool_size;
  4124. num_desc_per_page =
  4125. tx_desc_pool->desc_pages.num_element_per_page;
  4126. for (j = 0; j < num_desc; j++) {
  4127. page_id = j / num_desc_per_page;
  4128. offset = j % num_desc_per_page;
  4129. if (qdf_unlikely(!(tx_desc_pool->
  4130. desc_pages.cacheable_pages)))
  4131. break;
  4132. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4133. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4134. /*
  4135. * Free TX desc if force free is
  4136. * required, otherwise only reset vdev
  4137. * in this TX desc.
  4138. */
  4139. if (force_free) {
  4140. dp_tx_comp_free_buf(soc, tx_desc);
  4141. dp_tx_desc_release(tx_desc, i);
  4142. } else {
  4143. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4144. }
  4145. }
  4146. }
  4147. if (!force_free)
  4148. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4149. }
  4150. }
  4151. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4152. /**
  4153. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4154. *
  4155. * @soc: Handle to DP soc structure
  4156. * @tx_desc: pointer of one TX desc
  4157. * @desc_pool_id: TX Desc pool id
  4158. */
  4159. static inline void
  4160. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4161. uint8_t desc_pool_id)
  4162. {
  4163. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4164. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4165. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4166. }
  4167. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4168. bool force_free)
  4169. {
  4170. uint8_t i, num_pool;
  4171. uint32_t j;
  4172. uint32_t num_desc, page_id, offset;
  4173. uint16_t num_desc_per_page;
  4174. struct dp_soc *soc = pdev->soc;
  4175. struct dp_tx_desc_s *tx_desc = NULL;
  4176. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4177. if (!vdev && !force_free) {
  4178. dp_err("Reset TX desc vdev, Vdev param is required!");
  4179. return;
  4180. }
  4181. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4182. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4183. for (i = 0; i < num_pool; i++) {
  4184. tx_desc_pool = &soc->tx_desc[i];
  4185. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4186. continue;
  4187. num_desc_per_page =
  4188. tx_desc_pool->desc_pages.num_element_per_page;
  4189. for (j = 0; j < num_desc; j++) {
  4190. page_id = j / num_desc_per_page;
  4191. offset = j % num_desc_per_page;
  4192. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4193. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4194. if (force_free) {
  4195. dp_tx_comp_free_buf(soc, tx_desc);
  4196. dp_tx_desc_release(tx_desc, i);
  4197. } else {
  4198. dp_tx_desc_reset_vdev(soc, tx_desc,
  4199. i);
  4200. }
  4201. }
  4202. }
  4203. }
  4204. }
  4205. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4206. /**
  4207. * dp_tx_vdev_detach() - detach vdev from dp tx
  4208. * @vdev: virtual device instance
  4209. *
  4210. * Return: QDF_STATUS_SUCCESS: success
  4211. * QDF_STATUS_E_RESOURCES: Error return
  4212. */
  4213. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4214. {
  4215. struct dp_pdev *pdev = vdev->pdev;
  4216. /* Reset TX desc associated to this Vdev as NULL */
  4217. dp_tx_desc_flush(pdev, vdev, false);
  4218. dp_tx_vdev_multipass_deinit(vdev);
  4219. return QDF_STATUS_SUCCESS;
  4220. }
  4221. /**
  4222. * dp_tx_pdev_attach() - attach pdev to dp tx
  4223. * @pdev: physical device instance
  4224. *
  4225. * Return: QDF_STATUS_SUCCESS: success
  4226. * QDF_STATUS_E_RESOURCES: Error return
  4227. */
  4228. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4229. {
  4230. struct dp_soc *soc = pdev->soc;
  4231. /* Initialize Flow control counters */
  4232. qdf_atomic_init(&pdev->num_tx_outstanding);
  4233. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4234. /* Initialize descriptors in TCL Ring */
  4235. hal_tx_init_data_ring(soc->hal_soc,
  4236. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4237. }
  4238. return QDF_STATUS_SUCCESS;
  4239. }
  4240. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4241. /* Pools will be allocated dynamically */
  4242. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4243. int num_desc)
  4244. {
  4245. uint8_t i;
  4246. for (i = 0; i < num_pool; i++) {
  4247. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4248. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4249. }
  4250. return QDF_STATUS_SUCCESS;
  4251. }
  4252. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4253. int num_desc)
  4254. {
  4255. return QDF_STATUS_SUCCESS;
  4256. }
  4257. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4258. {
  4259. }
  4260. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4261. {
  4262. uint8_t i;
  4263. for (i = 0; i < num_pool; i++)
  4264. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4265. }
  4266. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4267. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4268. int num_desc)
  4269. {
  4270. uint8_t i, count;
  4271. /* Allocate software Tx descriptor pools */
  4272. for (i = 0; i < num_pool; i++) {
  4273. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4274. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4275. FL("Tx Desc Pool alloc %d failed %pK"),
  4276. i, soc);
  4277. goto fail;
  4278. }
  4279. }
  4280. return QDF_STATUS_SUCCESS;
  4281. fail:
  4282. for (count = 0; count < i; count++)
  4283. dp_tx_desc_pool_free(soc, count);
  4284. return QDF_STATUS_E_NOMEM;
  4285. }
  4286. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4287. int num_desc)
  4288. {
  4289. uint8_t i;
  4290. for (i = 0; i < num_pool; i++) {
  4291. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4292. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4293. FL("Tx Desc Pool init %d failed %pK"),
  4294. i, soc);
  4295. return QDF_STATUS_E_NOMEM;
  4296. }
  4297. }
  4298. return QDF_STATUS_SUCCESS;
  4299. }
  4300. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4301. {
  4302. uint8_t i;
  4303. for (i = 0; i < num_pool; i++)
  4304. dp_tx_desc_pool_deinit(soc, i);
  4305. }
  4306. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4307. {
  4308. uint8_t i;
  4309. for (i = 0; i < num_pool; i++)
  4310. dp_tx_desc_pool_free(soc, i);
  4311. }
  4312. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4313. /**
  4314. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4315. * @soc: core txrx main context
  4316. * @num_pool: number of pools
  4317. *
  4318. */
  4319. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4320. {
  4321. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4322. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4323. }
  4324. /**
  4325. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4326. * @soc: core txrx main context
  4327. * @num_pool: number of pools
  4328. *
  4329. */
  4330. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4331. {
  4332. dp_tx_tso_desc_pool_free(soc, num_pool);
  4333. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4334. }
  4335. /**
  4336. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4337. * @soc: core txrx main context
  4338. *
  4339. * This function frees all tx related descriptors as below
  4340. * 1. Regular TX descriptors (static pools)
  4341. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4342. * 3. TSO descriptors
  4343. *
  4344. */
  4345. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4346. {
  4347. uint8_t num_pool;
  4348. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4349. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4350. dp_tx_ext_desc_pool_free(soc, num_pool);
  4351. dp_tx_delete_static_pools(soc, num_pool);
  4352. }
  4353. /**
  4354. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4355. * @soc: core txrx main context
  4356. *
  4357. * This function de-initializes all tx related descriptors as below
  4358. * 1. Regular TX descriptors (static pools)
  4359. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4360. * 3. TSO descriptors
  4361. *
  4362. */
  4363. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4364. {
  4365. uint8_t num_pool;
  4366. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4367. dp_tx_flow_control_deinit(soc);
  4368. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4369. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4370. dp_tx_deinit_static_pools(soc, num_pool);
  4371. }
  4372. /**
  4373. * dp_tso_attach() - TSO attach handler
  4374. * @txrx_soc: Opaque Dp handle
  4375. *
  4376. * Reserve TSO descriptor buffers
  4377. *
  4378. * Return: QDF_STATUS_E_FAILURE on failure or
  4379. * QDF_STATUS_SUCCESS on success
  4380. */
  4381. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4382. uint8_t num_pool,
  4383. uint16_t num_desc)
  4384. {
  4385. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4386. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4387. return QDF_STATUS_E_FAILURE;
  4388. }
  4389. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4390. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4391. num_pool, soc);
  4392. return QDF_STATUS_E_FAILURE;
  4393. }
  4394. return QDF_STATUS_SUCCESS;
  4395. }
  4396. /**
  4397. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4398. * @soc: DP soc handle
  4399. * @num_pool: Number of pools
  4400. * @num_desc: Number of descriptors
  4401. *
  4402. * Initialize TSO descriptor pools
  4403. *
  4404. * Return: QDF_STATUS_E_FAILURE on failure or
  4405. * QDF_STATUS_SUCCESS on success
  4406. */
  4407. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4408. uint8_t num_pool,
  4409. uint16_t num_desc)
  4410. {
  4411. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4412. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4413. return QDF_STATUS_E_FAILURE;
  4414. }
  4415. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4416. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4417. num_pool, soc);
  4418. return QDF_STATUS_E_FAILURE;
  4419. }
  4420. return QDF_STATUS_SUCCESS;
  4421. }
  4422. /**
  4423. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4424. * @soc: core txrx main context
  4425. *
  4426. * This function allocates memory for following descriptor pools
  4427. * 1. regular sw tx descriptor pools (static pools)
  4428. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4429. * 3. TSO descriptor pools
  4430. *
  4431. * Return: QDF_STATUS_SUCCESS: success
  4432. * QDF_STATUS_E_RESOURCES: Error return
  4433. */
  4434. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4435. {
  4436. uint8_t num_pool;
  4437. uint32_t num_desc;
  4438. uint32_t num_ext_desc;
  4439. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4440. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4441. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4442. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4443. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4444. __func__, num_pool, num_desc);
  4445. if ((num_pool > MAX_TXDESC_POOLS) ||
  4446. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4447. goto fail1;
  4448. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4449. goto fail1;
  4450. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4451. goto fail2;
  4452. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4453. return QDF_STATUS_SUCCESS;
  4454. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4455. goto fail3;
  4456. return QDF_STATUS_SUCCESS;
  4457. fail3:
  4458. dp_tx_ext_desc_pool_free(soc, num_pool);
  4459. fail2:
  4460. dp_tx_delete_static_pools(soc, num_pool);
  4461. fail1:
  4462. return QDF_STATUS_E_RESOURCES;
  4463. }
  4464. /**
  4465. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4466. * @soc: core txrx main context
  4467. *
  4468. * This function initializes the following TX descriptor pools
  4469. * 1. regular sw tx descriptor pools (static pools)
  4470. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4471. * 3. TSO descriptor pools
  4472. *
  4473. * Return: QDF_STATUS_SUCCESS: success
  4474. * QDF_STATUS_E_RESOURCES: Error return
  4475. */
  4476. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4477. {
  4478. uint8_t num_pool;
  4479. uint32_t num_desc;
  4480. uint32_t num_ext_desc;
  4481. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4482. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4483. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4484. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4485. goto fail1;
  4486. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4487. goto fail2;
  4488. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4489. return QDF_STATUS_SUCCESS;
  4490. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4491. goto fail3;
  4492. dp_tx_flow_control_init(soc);
  4493. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4494. return QDF_STATUS_SUCCESS;
  4495. fail3:
  4496. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4497. fail2:
  4498. dp_tx_deinit_static_pools(soc, num_pool);
  4499. fail1:
  4500. return QDF_STATUS_E_RESOURCES;
  4501. }
  4502. /**
  4503. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4504. * @txrx_soc: dp soc handle
  4505. *
  4506. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4507. * QDF_STATUS_E_FAILURE
  4508. */
  4509. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4510. {
  4511. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4512. uint8_t num_pool;
  4513. uint32_t num_desc;
  4514. uint32_t num_ext_desc;
  4515. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4516. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4517. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4518. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4519. return QDF_STATUS_E_FAILURE;
  4520. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4521. return QDF_STATUS_E_FAILURE;
  4522. return QDF_STATUS_SUCCESS;
  4523. }
  4524. /**
  4525. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4526. * @txrx_soc: dp soc handle
  4527. *
  4528. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4529. */
  4530. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4531. {
  4532. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4533. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4534. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4535. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4536. return QDF_STATUS_SUCCESS;
  4537. }