dp_main.c 146 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <hal_api.h>
  23. #include <hif.h>
  24. #include <htt.h>
  25. #include <wdi_event.h>
  26. #include <queue.h>
  27. #include "dp_htt.h"
  28. #include "dp_types.h"
  29. #include "dp_internal.h"
  30. #include "dp_tx.h"
  31. #include "dp_tx_desc.h"
  32. #include "dp_rx.h"
  33. #include <cdp_txrx_handle.h>
  34. #include <wlan_cfg.h>
  35. #include "cdp_txrx_cmn_struct.h"
  36. #include <qdf_util.h>
  37. #include "dp_peer.h"
  38. #include "dp_rx_mon.h"
  39. #include "htt_stats.h"
  40. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  41. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  42. #include "cdp_txrx_flow_ctrl_v2.h"
  43. #else
  44. static inline void
  45. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  46. {
  47. return;
  48. }
  49. #endif
  50. #include <ol_cfg.h>
  51. #include "dp_ipa.h"
  52. #define DP_INTR_POLL_TIMER_MS 10
  53. #define DP_WDS_AGING_TIMER_DEFAULT_MS 6000
  54. #define DP_MCS_LENGTH (6*MAX_MCS)
  55. #define DP_NSS_LENGTH (6*SS_COUNT)
  56. #define DP_RXDMA_ERR_LENGTH (6*MAX_RXDMA_ERRORS)
  57. #define DP_REO_ERR_LENGTH (6*REO_ERROR_TYPE_MAX)
  58. #define DP_CURR_FW_STATS_AVAIL 19
  59. #define DP_HTT_DBG_EXT_STATS_MAX 256
  60. #ifdef IPA_OFFLOAD
  61. /* Exclude IPA rings from the interrupt context */
  62. #define TX_RING_MASK_VAL 0x7
  63. #define RX_RING_MASK_VAL 0x7
  64. #else
  65. #define TX_RING_MASK_VAL 0xF
  66. #define RX_RING_MASK_VAL 0xF
  67. #endif
  68. /**
  69. * default_dscp_tid_map - Default DSCP-TID mapping
  70. *
  71. * DSCP TID AC
  72. * 000000 0 WME_AC_BE
  73. * 001000 1 WME_AC_BK
  74. * 010000 1 WME_AC_BK
  75. * 011000 0 WME_AC_BE
  76. * 100000 5 WME_AC_VI
  77. * 101000 5 WME_AC_VI
  78. * 110000 6 WME_AC_VO
  79. * 111000 6 WME_AC_VO
  80. */
  81. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  82. 0, 0, 0, 0, 0, 0, 0, 0,
  83. 1, 1, 1, 1, 1, 1, 1, 1,
  84. 1, 1, 1, 1, 1, 1, 1, 1,
  85. 0, 0, 0, 0, 0, 0, 0, 0,
  86. 5, 5, 5, 5, 5, 5, 5, 5,
  87. 5, 5, 5, 5, 5, 5, 5, 5,
  88. 6, 6, 6, 6, 6, 6, 6, 6,
  89. 6, 6, 6, 6, 6, 6, 6, 6,
  90. };
  91. /**
  92. * @brief Cpu ring map types
  93. */
  94. enum dp_cpu_ring_map_types {
  95. DP_DEFAULT_MAP,
  96. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  97. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  98. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  99. DP_CPU_RING_MAP_MAX
  100. };
  101. /**
  102. * @brief Cpu to tx ring map
  103. */
  104. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  105. {0x0, 0x1, 0x2, 0x0},
  106. {0x1, 0x2, 0x1, 0x2},
  107. {0x0, 0x2, 0x0, 0x2},
  108. {0x2, 0x2, 0x2, 0x2}
  109. };
  110. /**
  111. * @brief Select the type of statistics
  112. */
  113. enum dp_stats_type {
  114. STATS_FW = 0,
  115. STATS_HOST = 1,
  116. STATS_TYPE_MAX = 2,
  117. };
  118. /**
  119. * @brief General Firmware statistics options
  120. *
  121. */
  122. enum dp_fw_stats {
  123. TXRX_FW_STATS_INVALID = -1,
  124. };
  125. /**
  126. * @brief Firmware and Host statistics
  127. * currently supported
  128. */
  129. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  130. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  131. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  132. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  133. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  134. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  135. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  136. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  137. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  138. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  139. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  140. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  141. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  142. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  143. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  144. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  145. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  146. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  147. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  148. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  149. /* Last ENUM for HTT FW STATS */
  150. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  151. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  152. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  153. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  154. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  155. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  156. };
  157. /**
  158. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  159. * @ring_num: ring num of the ring being queried
  160. * @grp_mask: the grp_mask array for the ring type in question.
  161. *
  162. * The grp_mask array is indexed by group number and the bit fields correspond
  163. * to ring numbers. We are finding which interrupt group a ring belongs to.
  164. *
  165. * Return: the index in the grp_mask array with the ring number.
  166. * -QDF_STATUS_E_NOENT if no entry is found
  167. */
  168. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  169. {
  170. int ext_group_num;
  171. int mask = 1 << ring_num;
  172. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  173. ext_group_num++) {
  174. if (mask & grp_mask[ext_group_num])
  175. return ext_group_num;
  176. }
  177. return -QDF_STATUS_E_NOENT;
  178. }
  179. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  180. enum hal_ring_type ring_type,
  181. int ring_num)
  182. {
  183. int *grp_mask;
  184. switch (ring_type) {
  185. case WBM2SW_RELEASE:
  186. /* dp_tx_comp_handler - soc->tx_comp_ring */
  187. if (ring_num < 3)
  188. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  189. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  190. else if (ring_num == 3) {
  191. /* sw treats this as a separate ring type */
  192. grp_mask = &soc->wlan_cfg_ctx->
  193. int_rx_wbm_rel_ring_mask[0];
  194. ring_num = 0;
  195. } else {
  196. qdf_assert(0);
  197. return -QDF_STATUS_E_NOENT;
  198. }
  199. break;
  200. case REO_EXCEPTION:
  201. /* dp_rx_err_process - &soc->reo_exception_ring */
  202. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  203. break;
  204. case REO_DST:
  205. /* dp_rx_process - soc->reo_dest_ring */
  206. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  207. break;
  208. case REO_STATUS:
  209. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  210. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  211. break;
  212. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  213. case RXDMA_MONITOR_STATUS:
  214. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  215. case RXDMA_MONITOR_DST:
  216. /* dp_mon_process */
  217. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  218. break;
  219. case RXDMA_MONITOR_BUF:
  220. case RXDMA_BUF:
  221. /* TODO: support low_thresh interrupt */
  222. return -QDF_STATUS_E_NOENT;
  223. break;
  224. case TCL_DATA:
  225. case TCL_CMD:
  226. case REO_CMD:
  227. case SW2WBM_RELEASE:
  228. case WBM_IDLE_LINK:
  229. /* normally empty SW_TO_HW rings */
  230. return -QDF_STATUS_E_NOENT;
  231. break;
  232. case TCL_STATUS:
  233. case REO_REINJECT:
  234. case RXDMA_DST:
  235. /* misc unused rings */
  236. return -QDF_STATUS_E_NOENT;
  237. break;
  238. case CE_SRC:
  239. case CE_DST:
  240. case CE_DST_STATUS:
  241. /* CE_rings - currently handled by hif */
  242. default:
  243. return -QDF_STATUS_E_NOENT;
  244. break;
  245. }
  246. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  247. }
  248. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  249. *ring_params, int ring_type, int ring_num)
  250. {
  251. int msi_group_number;
  252. int msi_data_count;
  253. int ret;
  254. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  255. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  256. &msi_data_count, &msi_data_start,
  257. &msi_irq_start);
  258. if (ret)
  259. return;
  260. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  261. ring_num);
  262. if (msi_group_number < 0) {
  263. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  264. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  265. ring_type, ring_num);
  266. ring_params->msi_addr = 0;
  267. ring_params->msi_data = 0;
  268. return;
  269. }
  270. if (msi_group_number > msi_data_count) {
  271. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  272. FL("2 msi_groups will share an msi; msi_group_num %d"),
  273. msi_group_number);
  274. QDF_ASSERT(0);
  275. }
  276. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  277. ring_params->msi_addr = addr_low;
  278. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  279. ring_params->msi_data = (msi_group_number % msi_data_count)
  280. + msi_data_start;
  281. ring_params->flags |= HAL_SRNG_MSI_INTR;
  282. }
  283. /**
  284. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  285. */
  286. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  287. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  288. {
  289. void *hal_soc = soc->hal_soc;
  290. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  291. /* TODO: See if we should get align size from hal */
  292. uint32_t ring_base_align = 8;
  293. struct hal_srng_params ring_params;
  294. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  295. /* TODO: Currently hal layer takes care of endianness related settings.
  296. * See if these settings need to passed from DP layer
  297. */
  298. ring_params.flags = 0;
  299. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  300. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  301. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  302. srng->hal_srng = NULL;
  303. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  304. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  305. soc->osdev, soc->osdev->dev, srng->alloc_size,
  306. &(srng->base_paddr_unaligned));
  307. if (!srng->base_vaddr_unaligned) {
  308. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  309. FL("alloc failed - ring_type: %d, ring_num %d"),
  310. ring_type, ring_num);
  311. return QDF_STATUS_E_NOMEM;
  312. }
  313. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  314. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  315. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  316. ((unsigned long)(ring_params.ring_base_vaddr) -
  317. (unsigned long)srng->base_vaddr_unaligned);
  318. ring_params.num_entries = num_entries;
  319. if (soc->intr_mode == DP_INTR_MSI) {
  320. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  321. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  322. FL("Using MSI for ring_type: %d, ring_num %d"),
  323. ring_type, ring_num);
  324. } else {
  325. ring_params.msi_data = 0;
  326. ring_params.msi_addr = 0;
  327. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  328. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  329. ring_type, ring_num);
  330. }
  331. /*
  332. * Setup interrupt timer and batch counter thresholds for
  333. * interrupt mitigation based on ring type
  334. */
  335. if (ring_type == REO_DST) {
  336. ring_params.intr_timer_thres_us =
  337. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  338. ring_params.intr_batch_cntr_thres_entries =
  339. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  340. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  341. ring_params.intr_timer_thres_us =
  342. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  343. ring_params.intr_batch_cntr_thres_entries =
  344. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  345. } else {
  346. ring_params.intr_timer_thres_us =
  347. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  348. ring_params.intr_batch_cntr_thres_entries =
  349. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  350. }
  351. /* Enable low threshold interrupts for rx buffer rings (regular and
  352. * monitor buffer rings.
  353. * TODO: See if this is required for any other ring
  354. */
  355. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  356. /* TODO: Setting low threshold to 1/8th of ring size
  357. * see if this needs to be configurable
  358. */
  359. ring_params.low_threshold = num_entries >> 3;
  360. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  361. ring_params.intr_timer_thres_us = 0x1000;
  362. }
  363. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  364. mac_id, &ring_params);
  365. return 0;
  366. }
  367. /**
  368. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  369. * Any buffers allocated and attached to ring entries are expected to be freed
  370. * before calling this function.
  371. */
  372. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  373. int ring_type, int ring_num)
  374. {
  375. if (!srng->hal_srng) {
  376. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  377. FL("Ring type: %d, num:%d not setup"),
  378. ring_type, ring_num);
  379. return;
  380. }
  381. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  382. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  383. srng->alloc_size,
  384. srng->base_vaddr_unaligned,
  385. srng->base_paddr_unaligned, 0);
  386. }
  387. #ifdef IPA_OFFLOAD
  388. /**
  389. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  390. * @soc: data path instance
  391. * @pdev: core txrx pdev context
  392. *
  393. * Free allocated TX buffers with WBM SRNG
  394. *
  395. * Return: none
  396. */
  397. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  398. {
  399. int idx;
  400. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  401. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  402. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  403. }
  404. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  405. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  406. }
  407. /**
  408. * dp_rx_ipa_uc_detach - free autonomy RX resources
  409. * @soc: data path instance
  410. * @pdev: core txrx pdev context
  411. *
  412. * This function will detach DP RX into main device context
  413. * will free DP Rx resources.
  414. *
  415. * Return: none
  416. */
  417. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  418. {
  419. }
  420. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  421. {
  422. /* TX resource detach */
  423. dp_tx_ipa_uc_detach(soc, pdev);
  424. /* RX resource detach */
  425. dp_rx_ipa_uc_detach(soc, pdev);
  426. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  427. return QDF_STATUS_SUCCESS; /* success */
  428. }
  429. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  430. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  431. /**
  432. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  433. * @soc: data path instance
  434. * @pdev: Physical device handle
  435. *
  436. * Allocate TX buffer from non-cacheable memory
  437. * Attache allocated TX buffers with WBM SRNG
  438. *
  439. * Return: int
  440. */
  441. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  442. {
  443. uint32_t tx_buffer_count;
  444. uint32_t ring_base_align = 8;
  445. void *buffer_vaddr_unaligned;
  446. void *buffer_vaddr;
  447. qdf_dma_addr_t buffer_paddr_unaligned;
  448. qdf_dma_addr_t buffer_paddr;
  449. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  450. uint32_t paddr_lo;
  451. uint32_t paddr_hi;
  452. void *ring_entry;
  453. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  454. int retval = QDF_STATUS_SUCCESS;
  455. /*
  456. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  457. * unsigned int uc_tx_buf_sz =
  458. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  459. */
  460. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  461. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  462. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  463. "requested %d buffers to be posted to wbm ring",
  464. ring_size);
  465. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  466. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  467. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  468. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  469. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  470. return -ENOMEM;
  471. }
  472. hal_srng_access_start(soc->hal_soc, wbm_srng);
  473. /* Allocate TX buffers as many as possible */
  474. for (tx_buffer_count = 0;
  475. tx_buffer_count < ring_size; tx_buffer_count++) {
  476. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  477. if (!ring_entry) {
  478. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  479. "Failed to get WBM ring entry\n");
  480. goto fail;
  481. }
  482. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  483. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  484. if (!buffer_vaddr_unaligned) {
  485. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  486. "IPA WDI TX buffer alloc fail %d allocated\n",
  487. tx_buffer_count);
  488. break;
  489. }
  490. buffer_vaddr = buffer_vaddr_unaligned +
  491. ((unsigned long)buffer_vaddr_unaligned %
  492. ring_base_align);
  493. buffer_paddr = buffer_paddr_unaligned +
  494. ((unsigned long)(buffer_vaddr) -
  495. (unsigned long)buffer_vaddr_unaligned);
  496. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  497. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  498. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  499. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  500. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  501. buffer_vaddr;
  502. }
  503. hal_srng_access_end(soc->hal_soc, wbm_srng);
  504. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  505. return retval;
  506. fail:
  507. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  508. return retval;
  509. }
  510. /**
  511. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  512. * @soc: data path instance
  513. * @pdev: core txrx pdev context
  514. *
  515. * This function will attach a DP RX instance into the main
  516. * device (SOC) context.
  517. *
  518. * Return: QDF_STATUS_SUCCESS: success
  519. * QDF_STATUS_E_RESOURCES: Error return
  520. */
  521. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  522. {
  523. return QDF_STATUS_SUCCESS;
  524. }
  525. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  526. {
  527. int error;
  528. /* TX resource attach */
  529. error = dp_tx_ipa_uc_attach(soc, pdev);
  530. if (error) {
  531. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  532. "DP IPA UC TX attach fail code %d\n", error);
  533. return error;
  534. }
  535. /* RX resource attach */
  536. error = dp_rx_ipa_uc_attach(soc, pdev);
  537. if (error) {
  538. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  539. "DP IPA UC RX attach fail code %d\n", error);
  540. dp_tx_ipa_uc_detach(soc, pdev);
  541. return error;
  542. }
  543. return QDF_STATUS_SUCCESS; /* success */
  544. }
  545. #else
  546. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  547. {
  548. return QDF_STATUS_SUCCESS;
  549. }
  550. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  551. {
  552. return QDF_STATUS_SUCCESS;
  553. }
  554. #endif
  555. /* TODO: Need this interface from HIF */
  556. void *hif_get_hal_handle(void *hif_handle);
  557. /*
  558. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  559. * @dp_ctx: DP SOC handle
  560. * @budget: Number of frames/descriptors that can be processed in one shot
  561. *
  562. * Return: remaining budget/quota for the soc device
  563. */
  564. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  565. {
  566. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  567. struct dp_soc *soc = int_ctx->soc;
  568. int ring = 0;
  569. uint32_t work_done = 0;
  570. uint32_t budget = dp_budget;
  571. uint8_t tx_mask = int_ctx->tx_ring_mask;
  572. uint8_t rx_mask = int_ctx->rx_ring_mask;
  573. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  574. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  575. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  576. /* Process Tx completion interrupts first to return back buffers */
  577. if (tx_mask) {
  578. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  579. if (tx_mask & (1 << ring)) {
  580. work_done =
  581. dp_tx_comp_handler(soc, ring, budget);
  582. budget -= work_done;
  583. if (work_done)
  584. QDF_TRACE(QDF_MODULE_ID_DP,
  585. QDF_TRACE_LEVEL_INFO,
  586. "tx mask 0x%x ring %d,"
  587. "budget %d",
  588. tx_mask, ring, budget);
  589. if (budget <= 0)
  590. goto budget_done;
  591. }
  592. }
  593. }
  594. /* Process REO Exception ring interrupt */
  595. if (rx_err_mask) {
  596. work_done = dp_rx_err_process(soc,
  597. soc->reo_exception_ring.hal_srng, budget);
  598. budget -= work_done;
  599. if (work_done)
  600. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  601. "REO Exception Ring: work_done %d budget %d",
  602. work_done, budget);
  603. if (budget <= 0) {
  604. goto budget_done;
  605. }
  606. }
  607. /* Process Rx WBM release ring interrupt */
  608. if (rx_wbm_rel_mask) {
  609. work_done = dp_rx_wbm_err_process(soc,
  610. soc->rx_rel_ring.hal_srng, budget);
  611. budget -= work_done;
  612. if (work_done)
  613. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  614. "WBM Release Ring: work_done %d budget %d",
  615. work_done, budget);
  616. if (budget <= 0) {
  617. goto budget_done;
  618. }
  619. }
  620. /* Process Rx interrupts */
  621. if (rx_mask) {
  622. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  623. if (rx_mask & (1 << ring)) {
  624. work_done =
  625. dp_rx_process(int_ctx,
  626. soc->reo_dest_ring[ring].hal_srng,
  627. budget);
  628. budget -= work_done;
  629. if (work_done)
  630. QDF_TRACE(QDF_MODULE_ID_DP,
  631. QDF_TRACE_LEVEL_INFO,
  632. "rx mask 0x%x ring %d,"
  633. "budget %d",
  634. tx_mask, ring, budget);
  635. if (budget <= 0)
  636. goto budget_done;
  637. }
  638. }
  639. }
  640. if (reo_status_mask)
  641. dp_reo_status_ring_handler(soc);
  642. /* Process LMAC interrupts */
  643. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  644. if (soc->pdev_list[ring] == NULL)
  645. continue;
  646. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  647. work_done =
  648. dp_mon_process(soc, ring, budget);
  649. budget -= work_done;
  650. }
  651. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  652. work_done =
  653. dp_rxdma_err_process(soc, ring, budget);
  654. budget -= work_done;
  655. }
  656. }
  657. qdf_lro_flush(int_ctx->lro_ctx);
  658. budget_done:
  659. return dp_budget - budget;
  660. }
  661. #ifdef DP_INTR_POLL_BASED
  662. /* dp_interrupt_timer()- timer poll for interrupts
  663. *
  664. * @arg: SoC Handle
  665. *
  666. * Return:
  667. *
  668. */
  669. static void dp_interrupt_timer(void *arg)
  670. {
  671. struct dp_soc *soc = (struct dp_soc *) arg;
  672. int i;
  673. if (qdf_atomic_read(&soc->cmn_init_done)) {
  674. for (i = 0;
  675. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  676. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  677. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  678. }
  679. }
  680. /*
  681. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  682. * @txrx_soc: DP SOC handle
  683. *
  684. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  685. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  686. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  687. *
  688. * Return: 0 for success. nonzero for failure.
  689. */
  690. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  691. {
  692. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  693. int i;
  694. soc->intr_mode = DP_INTR_POLL;
  695. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  696. soc->intr_ctx[i].dp_intr_id = i;
  697. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  698. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  699. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  700. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  701. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  702. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  703. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  704. soc->intr_ctx[i].soc = soc;
  705. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  706. }
  707. qdf_timer_init(soc->osdev, &soc->int_timer,
  708. dp_interrupt_timer, (void *)soc,
  709. QDF_TIMER_TYPE_WAKE_APPS);
  710. return QDF_STATUS_SUCCESS;
  711. }
  712. #ifdef CONFIG_MCL
  713. extern int con_mode_monitor;
  714. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  715. /*
  716. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  717. * @txrx_soc: DP SOC handle
  718. *
  719. * Call the appropriate attach function based on the mode of operation.
  720. * This is a WAR for enabling monitor mode.
  721. *
  722. * Return: 0 for success. nonzero for failure.
  723. */
  724. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  725. {
  726. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  728. FL("Attach interrupts in Poll mode"));
  729. return dp_soc_interrupt_attach_poll(txrx_soc);
  730. } else {
  731. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  732. FL("Attach interrupts in MSI mode"));
  733. return dp_soc_interrupt_attach(txrx_soc);
  734. }
  735. }
  736. #else
  737. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  738. {
  739. return dp_soc_interrupt_attach_poll(txrx_soc);
  740. }
  741. #endif
  742. #endif
  743. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  744. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  745. {
  746. int j;
  747. int num_irq = 0;
  748. int tx_mask =
  749. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  750. int rx_mask =
  751. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  752. int rx_mon_mask =
  753. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  754. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  755. soc->wlan_cfg_ctx, intr_ctx_num);
  756. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  757. soc->wlan_cfg_ctx, intr_ctx_num);
  758. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  759. soc->wlan_cfg_ctx, intr_ctx_num);
  760. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  761. if (tx_mask & (1 << j)) {
  762. irq_id_map[num_irq++] =
  763. (wbm2host_tx_completions_ring1 - j);
  764. }
  765. if (rx_mask & (1 << j)) {
  766. irq_id_map[num_irq++] =
  767. (reo2host_destination_ring1 - j);
  768. }
  769. if (rx_mon_mask & (1 << j)) {
  770. irq_id_map[num_irq++] =
  771. (ppdu_end_interrupts_mac1 - j);
  772. }
  773. if (rx_wbm_rel_ring_mask & (1 << j))
  774. irq_id_map[num_irq++] = wbm2host_rx_release;
  775. if (rx_err_ring_mask & (1 << j))
  776. irq_id_map[num_irq++] = reo2host_exception;
  777. if (reo_status_ring_mask & (1 << j))
  778. irq_id_map[num_irq++] = reo2host_status;
  779. }
  780. *num_irq_r = num_irq;
  781. }
  782. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  783. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  784. int msi_vector_count, int msi_vector_start)
  785. {
  786. int tx_mask = wlan_cfg_get_tx_ring_mask(
  787. soc->wlan_cfg_ctx, intr_ctx_num);
  788. int rx_mask = wlan_cfg_get_rx_ring_mask(
  789. soc->wlan_cfg_ctx, intr_ctx_num);
  790. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  791. soc->wlan_cfg_ctx, intr_ctx_num);
  792. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  793. soc->wlan_cfg_ctx, intr_ctx_num);
  794. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  795. soc->wlan_cfg_ctx, intr_ctx_num);
  796. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  797. soc->wlan_cfg_ctx, intr_ctx_num);
  798. unsigned int vector =
  799. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  800. int num_irq = 0;
  801. soc->intr_mode = DP_INTR_MSI;
  802. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  803. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  804. irq_id_map[num_irq++] =
  805. pld_get_msi_irq(soc->osdev->dev, vector);
  806. *num_irq_r = num_irq;
  807. }
  808. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  809. int *irq_id_map, int *num_irq)
  810. {
  811. int msi_vector_count, ret;
  812. uint32_t msi_base_data, msi_vector_start;
  813. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  814. &msi_vector_count,
  815. &msi_base_data,
  816. &msi_vector_start);
  817. if (ret)
  818. return dp_soc_interrupt_map_calculate_integrated(soc,
  819. intr_ctx_num, irq_id_map, num_irq);
  820. else
  821. dp_soc_interrupt_map_calculate_msi(soc,
  822. intr_ctx_num, irq_id_map, num_irq,
  823. msi_vector_count, msi_vector_start);
  824. }
  825. /*
  826. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  827. * @txrx_soc: DP SOC handle
  828. *
  829. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  830. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  831. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  832. *
  833. * Return: 0 for success. nonzero for failure.
  834. */
  835. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  836. {
  837. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  838. int i = 0;
  839. int num_irq = 0;
  840. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  841. int ret = 0;
  842. /* Map of IRQ ids registered with one interrupt context */
  843. int irq_id_map[HIF_MAX_GRP_IRQ];
  844. int tx_mask =
  845. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  846. int rx_mask =
  847. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  848. int rx_mon_mask =
  849. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  850. int rx_err_ring_mask =
  851. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  852. int rx_wbm_rel_ring_mask =
  853. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  854. int reo_status_ring_mask =
  855. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  856. int rxdma2host_ring_mask =
  857. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  858. soc->intr_ctx[i].dp_intr_id = i;
  859. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  860. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  861. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  862. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  863. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  864. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  865. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  866. soc->intr_ctx[i].soc = soc;
  867. num_irq = 0;
  868. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  869. &num_irq);
  870. ret = hif_register_ext_group(soc->hif_handle,
  871. num_irq, irq_id_map, dp_service_srngs,
  872. &soc->intr_ctx[i], "dp_intr",
  873. HIF_EXEC_NAPI_TYPE);
  874. if (ret) {
  875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  876. FL("failed, ret = %d"), ret);
  877. return QDF_STATUS_E_FAILURE;
  878. }
  879. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  880. }
  881. hif_configure_ext_group_interrupts(soc->hif_handle);
  882. return QDF_STATUS_SUCCESS;
  883. }
  884. /*
  885. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  886. * @txrx_soc: DP SOC handle
  887. *
  888. * Return: void
  889. */
  890. static void dp_soc_interrupt_detach(void *txrx_soc)
  891. {
  892. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  893. int i;
  894. if (soc->intr_mode == DP_INTR_POLL) {
  895. qdf_timer_stop(&soc->int_timer);
  896. qdf_timer_free(&soc->int_timer);
  897. }
  898. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  899. soc->intr_ctx[i].tx_ring_mask = 0;
  900. soc->intr_ctx[i].rx_ring_mask = 0;
  901. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  902. soc->intr_ctx[i].rx_err_ring_mask = 0;
  903. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  904. soc->intr_ctx[i].reo_status_ring_mask = 0;
  905. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  906. }
  907. }
  908. #define AVG_MAX_MPDUS_PER_TID 128
  909. #define AVG_TIDS_PER_CLIENT 2
  910. #define AVG_FLOWS_PER_TID 2
  911. #define AVG_MSDUS_PER_FLOW 128
  912. #define AVG_MSDUS_PER_MPDU 4
  913. /*
  914. * Allocate and setup link descriptor pool that will be used by HW for
  915. * various link and queue descriptors and managed by WBM
  916. */
  917. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  918. {
  919. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  920. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  921. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  922. uint32_t num_mpdus_per_link_desc =
  923. hal_num_mpdus_per_link_desc(soc->hal_soc);
  924. uint32_t num_msdus_per_link_desc =
  925. hal_num_msdus_per_link_desc(soc->hal_soc);
  926. uint32_t num_mpdu_links_per_queue_desc =
  927. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  928. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  929. uint32_t total_link_descs, total_mem_size;
  930. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  931. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  932. uint32_t num_link_desc_banks;
  933. uint32_t last_bank_size = 0;
  934. uint32_t entry_size, num_entries;
  935. int i;
  936. uint32_t desc_id = 0;
  937. /* Only Tx queue descriptors are allocated from common link descriptor
  938. * pool Rx queue descriptors are not included in this because (REO queue
  939. * extension descriptors) they are expected to be allocated contiguously
  940. * with REO queue descriptors
  941. */
  942. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  943. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  944. num_mpdu_queue_descs = num_mpdu_link_descs /
  945. num_mpdu_links_per_queue_desc;
  946. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  947. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  948. num_msdus_per_link_desc;
  949. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  950. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  951. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  952. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  953. /* Round up to power of 2 */
  954. total_link_descs = 1;
  955. while (total_link_descs < num_entries)
  956. total_link_descs <<= 1;
  957. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  958. FL("total_link_descs: %u, link_desc_size: %d"),
  959. total_link_descs, link_desc_size);
  960. total_mem_size = total_link_descs * link_desc_size;
  961. total_mem_size += link_desc_align;
  962. if (total_mem_size <= max_alloc_size) {
  963. num_link_desc_banks = 0;
  964. last_bank_size = total_mem_size;
  965. } else {
  966. num_link_desc_banks = (total_mem_size) /
  967. (max_alloc_size - link_desc_align);
  968. last_bank_size = total_mem_size %
  969. (max_alloc_size - link_desc_align);
  970. }
  971. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  972. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  973. total_mem_size, num_link_desc_banks);
  974. for (i = 0; i < num_link_desc_banks; i++) {
  975. soc->link_desc_banks[i].base_vaddr_unaligned =
  976. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  977. max_alloc_size,
  978. &(soc->link_desc_banks[i].base_paddr_unaligned));
  979. soc->link_desc_banks[i].size = max_alloc_size;
  980. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  981. soc->link_desc_banks[i].base_vaddr_unaligned) +
  982. ((unsigned long)(
  983. soc->link_desc_banks[i].base_vaddr_unaligned) %
  984. link_desc_align));
  985. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  986. soc->link_desc_banks[i].base_paddr_unaligned) +
  987. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  988. (unsigned long)(
  989. soc->link_desc_banks[i].base_vaddr_unaligned));
  990. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  992. FL("Link descriptor memory alloc failed"));
  993. goto fail;
  994. }
  995. }
  996. if (last_bank_size) {
  997. /* Allocate last bank in case total memory required is not exact
  998. * multiple of max_alloc_size
  999. */
  1000. soc->link_desc_banks[i].base_vaddr_unaligned =
  1001. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1002. last_bank_size,
  1003. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1004. soc->link_desc_banks[i].size = last_bank_size;
  1005. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1006. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1007. ((unsigned long)(
  1008. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1009. link_desc_align));
  1010. soc->link_desc_banks[i].base_paddr =
  1011. (unsigned long)(
  1012. soc->link_desc_banks[i].base_paddr_unaligned) +
  1013. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1014. (unsigned long)(
  1015. soc->link_desc_banks[i].base_vaddr_unaligned));
  1016. }
  1017. /* Allocate and setup link descriptor idle list for HW internal use */
  1018. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1019. total_mem_size = entry_size * total_link_descs;
  1020. if (total_mem_size <= max_alloc_size) {
  1021. void *desc;
  1022. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1023. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1024. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1025. FL("Link desc idle ring setup failed"));
  1026. goto fail;
  1027. }
  1028. hal_srng_access_start_unlocked(soc->hal_soc,
  1029. soc->wbm_idle_link_ring.hal_srng);
  1030. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1031. soc->link_desc_banks[i].base_paddr; i++) {
  1032. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1033. ((unsigned long)(
  1034. soc->link_desc_banks[i].base_vaddr) -
  1035. (unsigned long)(
  1036. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1037. / link_desc_size;
  1038. unsigned long paddr = (unsigned long)(
  1039. soc->link_desc_banks[i].base_paddr);
  1040. while (num_entries && (desc = hal_srng_src_get_next(
  1041. soc->hal_soc,
  1042. soc->wbm_idle_link_ring.hal_srng))) {
  1043. hal_set_link_desc_addr(desc,
  1044. LINK_DESC_COOKIE(desc_id, i), paddr);
  1045. num_entries--;
  1046. desc_id++;
  1047. paddr += link_desc_size;
  1048. }
  1049. }
  1050. hal_srng_access_end_unlocked(soc->hal_soc,
  1051. soc->wbm_idle_link_ring.hal_srng);
  1052. } else {
  1053. uint32_t num_scatter_bufs;
  1054. uint32_t num_entries_per_buf;
  1055. uint32_t rem_entries;
  1056. uint8_t *scatter_buf_ptr;
  1057. uint16_t scatter_buf_num;
  1058. soc->wbm_idle_scatter_buf_size =
  1059. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1060. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1061. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1062. num_scatter_bufs = (total_mem_size /
  1063. soc->wbm_idle_scatter_buf_size) + (total_mem_size %
  1064. soc->wbm_idle_scatter_buf_size) ? 1 : 0;
  1065. for (i = 0; i < num_scatter_bufs; i++) {
  1066. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1067. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1068. soc->wbm_idle_scatter_buf_size,
  1069. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1070. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1071. QDF_TRACE(QDF_MODULE_ID_DP,
  1072. QDF_TRACE_LEVEL_ERROR,
  1073. FL("Scatter list memory alloc failed"));
  1074. goto fail;
  1075. }
  1076. }
  1077. /* Populate idle list scatter buffers with link descriptor
  1078. * pointers
  1079. */
  1080. scatter_buf_num = 0;
  1081. scatter_buf_ptr = (uint8_t *)(
  1082. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1083. rem_entries = num_entries_per_buf;
  1084. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1085. soc->link_desc_banks[i].base_paddr; i++) {
  1086. uint32_t num_link_descs =
  1087. (soc->link_desc_banks[i].size -
  1088. ((unsigned long)(
  1089. soc->link_desc_banks[i].base_vaddr) -
  1090. (unsigned long)(
  1091. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1092. / link_desc_size;
  1093. unsigned long paddr = (unsigned long)(
  1094. soc->link_desc_banks[i].base_paddr);
  1095. while (num_link_descs) {
  1096. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1097. LINK_DESC_COOKIE(desc_id, i), paddr);
  1098. num_link_descs--;
  1099. desc_id++;
  1100. paddr += link_desc_size;
  1101. if (rem_entries) {
  1102. rem_entries--;
  1103. scatter_buf_ptr += link_desc_size;
  1104. } else {
  1105. rem_entries = num_entries_per_buf;
  1106. scatter_buf_num++;
  1107. scatter_buf_ptr = (uint8_t *)(
  1108. soc->wbm_idle_scatter_buf_base_vaddr[
  1109. scatter_buf_num]);
  1110. }
  1111. }
  1112. }
  1113. /* Setup link descriptor idle list in HW */
  1114. hal_setup_link_idle_list(soc->hal_soc,
  1115. soc->wbm_idle_scatter_buf_base_paddr,
  1116. soc->wbm_idle_scatter_buf_base_vaddr,
  1117. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1118. (uint32_t)(scatter_buf_ptr -
  1119. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1120. scatter_buf_num])));
  1121. }
  1122. return 0;
  1123. fail:
  1124. if (soc->wbm_idle_link_ring.hal_srng) {
  1125. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1126. WBM_IDLE_LINK, 0);
  1127. }
  1128. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1129. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1130. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1131. soc->wbm_idle_scatter_buf_size,
  1132. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1133. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1134. }
  1135. }
  1136. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1137. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1138. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1139. soc->link_desc_banks[i].size,
  1140. soc->link_desc_banks[i].base_vaddr_unaligned,
  1141. soc->link_desc_banks[i].base_paddr_unaligned,
  1142. 0);
  1143. }
  1144. }
  1145. return QDF_STATUS_E_FAILURE;
  1146. }
  1147. #ifdef notused
  1148. /*
  1149. * Free link descriptor pool that was setup HW
  1150. */
  1151. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1152. {
  1153. int i;
  1154. if (soc->wbm_idle_link_ring.hal_srng) {
  1155. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1156. WBM_IDLE_LINK, 0);
  1157. }
  1158. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1159. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1160. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1161. soc->wbm_idle_scatter_buf_size,
  1162. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1163. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1164. }
  1165. }
  1166. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1167. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1168. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1169. soc->link_desc_banks[i].size,
  1170. soc->link_desc_banks[i].base_vaddr_unaligned,
  1171. soc->link_desc_banks[i].base_paddr_unaligned,
  1172. 0);
  1173. }
  1174. }
  1175. }
  1176. #endif /* notused */
  1177. /* TODO: Following should be configurable */
  1178. #define WBM_RELEASE_RING_SIZE 64
  1179. #define TCL_CMD_RING_SIZE 32
  1180. #define TCL_STATUS_RING_SIZE 32
  1181. #if defined(QCA_WIFI_QCA6290)
  1182. #define REO_DST_RING_SIZE 1024
  1183. #else
  1184. #define REO_DST_RING_SIZE 2048
  1185. #endif
  1186. #define REO_REINJECT_RING_SIZE 32
  1187. #define RX_RELEASE_RING_SIZE 1024
  1188. #define REO_EXCEPTION_RING_SIZE 128
  1189. #define REO_CMD_RING_SIZE 32
  1190. #define REO_STATUS_RING_SIZE 32
  1191. #define RXDMA_BUF_RING_SIZE 1024
  1192. #define RXDMA_REFILL_RING_SIZE 2048
  1193. #define RXDMA_MONITOR_BUF_RING_SIZE 1024
  1194. #define RXDMA_MONITOR_DST_RING_SIZE 1024
  1195. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1196. #define RXDMA_MONITOR_DESC_RING_SIZE 1024
  1197. #define RXDMA_ERR_DST_RING_SIZE 1024
  1198. /*
  1199. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1200. * @soc: Datapath SOC handle
  1201. *
  1202. * This is a timer function used to age out stale WDS nodes from
  1203. * AST table
  1204. */
  1205. #ifdef FEATURE_WDS
  1206. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1207. {
  1208. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1209. struct dp_pdev *pdev;
  1210. struct dp_vdev *vdev;
  1211. struct dp_peer *peer;
  1212. struct dp_ast_entry *ase;
  1213. int i;
  1214. qdf_spin_lock_bh(&soc->ast_lock);
  1215. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1216. pdev = soc->pdev_list[i];
  1217. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1218. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1219. DP_PEER_ITERATE_ASE_LIST(peer, ase) {
  1220. /*
  1221. * Do not expire static ast entries
  1222. */
  1223. if (ase->is_static)
  1224. continue;
  1225. if (ase->is_active) {
  1226. ase->is_active = FALSE;
  1227. continue;
  1228. }
  1229. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1230. pdev->osif_pdev,
  1231. ase->mac_addr.raw);
  1232. dp_peer_del_ast(soc, ase);
  1233. }
  1234. }
  1235. }
  1236. }
  1237. qdf_spin_unlock_bh(&soc->ast_lock);
  1238. if (qdf_atomic_read(&soc->cmn_init_done))
  1239. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1240. }
  1241. /*
  1242. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1243. * @soc: Datapath SOC handle
  1244. *
  1245. * Return: None
  1246. */
  1247. static void dp_soc_wds_attach(struct dp_soc *soc)
  1248. {
  1249. qdf_spinlock_create(&soc->ast_lock);
  1250. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1251. dp_wds_aging_timer_fn, (void *)soc,
  1252. QDF_TIMER_TYPE_WAKE_APPS);
  1253. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1254. }
  1255. /*
  1256. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1257. * @txrx_soc: DP SOC handle
  1258. *
  1259. * Return: None
  1260. */
  1261. static void dp_soc_wds_detach(struct dp_soc *soc)
  1262. {
  1263. qdf_timer_stop(&soc->wds_aging_timer);
  1264. qdf_timer_free(&soc->wds_aging_timer);
  1265. qdf_spinlock_destroy(&soc->ast_lock);
  1266. }
  1267. #else
  1268. static void dp_soc_wds_attach(struct dp_soc *soc)
  1269. {
  1270. }
  1271. static void dp_soc_wds_detach(struct dp_soc *soc)
  1272. {
  1273. }
  1274. #endif
  1275. /*
  1276. * dp_soc_reset_ring_map() - Reset cpu ring map
  1277. * @soc: Datapath soc handler
  1278. *
  1279. * This api resets the default cpu ring map
  1280. */
  1281. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1282. {
  1283. uint8_t i;
  1284. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1285. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1286. if (nss_config == 1) {
  1287. /*
  1288. * Setting Tx ring map for one nss offloaded radio
  1289. */
  1290. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1291. } else if (nss_config == 2) {
  1292. /*
  1293. * Setting Tx ring for two nss offloaded radios
  1294. */
  1295. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1296. } else {
  1297. /*
  1298. * Setting Tx ring map for all nss offloaded radios
  1299. */
  1300. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1301. }
  1302. }
  1303. }
  1304. /*
  1305. * dp_soc_cmn_setup() - Common SoC level initializion
  1306. * @soc: Datapath SOC handle
  1307. *
  1308. * This is an internal function used to setup common SOC data structures,
  1309. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1310. */
  1311. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1312. {
  1313. int i;
  1314. struct hal_reo_params reo_params;
  1315. int tx_ring_size;
  1316. int tx_comp_ring_size;
  1317. if (qdf_atomic_read(&soc->cmn_init_done))
  1318. return 0;
  1319. if (dp_peer_find_attach(soc))
  1320. goto fail0;
  1321. if (dp_hw_link_desc_pool_setup(soc))
  1322. goto fail1;
  1323. /* Setup SRNG rings */
  1324. /* Common rings */
  1325. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1326. WBM_RELEASE_RING_SIZE)) {
  1327. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1328. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1329. goto fail1;
  1330. }
  1331. soc->num_tcl_data_rings = 0;
  1332. /* Tx data rings */
  1333. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1334. soc->num_tcl_data_rings =
  1335. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1336. tx_comp_ring_size =
  1337. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1338. tx_ring_size =
  1339. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1340. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1341. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1342. TCL_DATA, i, 0, tx_ring_size)) {
  1343. QDF_TRACE(QDF_MODULE_ID_DP,
  1344. QDF_TRACE_LEVEL_ERROR,
  1345. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1346. goto fail1;
  1347. }
  1348. /*
  1349. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1350. * count
  1351. */
  1352. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1353. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1354. QDF_TRACE(QDF_MODULE_ID_DP,
  1355. QDF_TRACE_LEVEL_ERROR,
  1356. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1357. goto fail1;
  1358. }
  1359. }
  1360. } else {
  1361. /* This will be incremented during per pdev ring setup */
  1362. soc->num_tcl_data_rings = 0;
  1363. }
  1364. if (dp_tx_soc_attach(soc)) {
  1365. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1366. FL("dp_tx_soc_attach failed"));
  1367. goto fail1;
  1368. }
  1369. /* TCL command and status rings */
  1370. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1371. TCL_CMD_RING_SIZE)) {
  1372. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1373. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1374. goto fail1;
  1375. }
  1376. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1377. TCL_STATUS_RING_SIZE)) {
  1378. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1379. FL("dp_srng_setup failed for tcl_status_ring"));
  1380. goto fail1;
  1381. }
  1382. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1383. * descriptors
  1384. */
  1385. /* Rx data rings */
  1386. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1387. soc->num_reo_dest_rings =
  1388. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1389. QDF_TRACE(QDF_MODULE_ID_DP,
  1390. QDF_TRACE_LEVEL_ERROR,
  1391. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1392. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1393. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1394. i, 0, REO_DST_RING_SIZE)) {
  1395. QDF_TRACE(QDF_MODULE_ID_DP,
  1396. QDF_TRACE_LEVEL_ERROR,
  1397. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1398. goto fail1;
  1399. }
  1400. }
  1401. } else {
  1402. /* This will be incremented during per pdev ring setup */
  1403. soc->num_reo_dest_rings = 0;
  1404. }
  1405. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1406. /* REO reinjection ring */
  1407. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1408. REO_REINJECT_RING_SIZE)) {
  1409. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1410. FL("dp_srng_setup failed for reo_reinject_ring"));
  1411. goto fail1;
  1412. }
  1413. /* Rx release ring */
  1414. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1415. RX_RELEASE_RING_SIZE)) {
  1416. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1417. FL("dp_srng_setup failed for rx_rel_ring"));
  1418. goto fail1;
  1419. }
  1420. /* Rx exception ring */
  1421. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1422. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1424. FL("dp_srng_setup failed for reo_exception_ring"));
  1425. goto fail1;
  1426. }
  1427. /* REO command and status rings */
  1428. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1429. REO_CMD_RING_SIZE)) {
  1430. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1431. FL("dp_srng_setup failed for reo_cmd_ring"));
  1432. goto fail1;
  1433. }
  1434. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1435. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1436. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1437. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1438. REO_STATUS_RING_SIZE)) {
  1439. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1440. FL("dp_srng_setup failed for reo_status_ring"));
  1441. goto fail1;
  1442. }
  1443. dp_soc_wds_attach(soc);
  1444. /* Reset the cpu ring map if radio is NSS offloaded */
  1445. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1446. dp_soc_reset_cpu_ring_map(soc);
  1447. }
  1448. /* Setup HW REO */
  1449. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1450. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx))
  1451. reo_params.rx_hash_enabled = true;
  1452. hal_reo_setup(soc->hal_soc, &reo_params);
  1453. qdf_atomic_set(&soc->cmn_init_done, 1);
  1454. qdf_nbuf_queue_init(&soc->htt_stats_msg);
  1455. return 0;
  1456. fail1:
  1457. /*
  1458. * Cleanup will be done as part of soc_detach, which will
  1459. * be called on pdev attach failure
  1460. */
  1461. fail0:
  1462. return QDF_STATUS_E_FAILURE;
  1463. }
  1464. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1465. static void dp_lro_hash_setup(struct dp_soc *soc)
  1466. {
  1467. struct cdp_lro_hash_config lro_hash;
  1468. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1469. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1471. FL("LRO disabled RX hash disabled"));
  1472. return;
  1473. }
  1474. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1475. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1476. lro_hash.lro_enable = 1;
  1477. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1478. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1479. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1480. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1481. }
  1482. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1483. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1484. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1485. LRO_IPV4_SEED_ARR_SZ));
  1486. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1487. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1488. LRO_IPV6_SEED_ARR_SZ));
  1489. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1490. "lro_hash: lro_enable: 0x%x"
  1491. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1492. lro_hash.lro_enable, lro_hash.tcp_flag,
  1493. lro_hash.tcp_flag_mask);
  1494. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1495. FL("lro_hash: toeplitz_hash_ipv4:"));
  1496. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1497. QDF_TRACE_LEVEL_ERROR,
  1498. (void *)lro_hash.toeplitz_hash_ipv4,
  1499. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1500. LRO_IPV4_SEED_ARR_SZ));
  1501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1502. FL("lro_hash: toeplitz_hash_ipv6:"));
  1503. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1504. QDF_TRACE_LEVEL_ERROR,
  1505. (void *)lro_hash.toeplitz_hash_ipv6,
  1506. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1507. LRO_IPV6_SEED_ARR_SZ));
  1508. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1509. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1510. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1511. (soc->osif_soc, &lro_hash);
  1512. }
  1513. /*
  1514. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1515. * @soc: data path SoC handle
  1516. * @pdev: Physical device handle
  1517. *
  1518. * Return: 0 - success, > 0 - failure
  1519. */
  1520. #ifdef QCA_HOST2FW_RXBUF_RING
  1521. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1522. struct dp_pdev *pdev)
  1523. {
  1524. int max_mac_rings =
  1525. wlan_cfg_get_num_mac_rings
  1526. (pdev->wlan_cfg_ctx);
  1527. int i;
  1528. for (i = 0; i < max_mac_rings; i++) {
  1529. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1530. "%s: pdev_id %d mac_id %d\n",
  1531. __func__, pdev->pdev_id, i);
  1532. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1533. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1534. QDF_TRACE(QDF_MODULE_ID_DP,
  1535. QDF_TRACE_LEVEL_ERROR,
  1536. FL("failed rx mac ring setup"));
  1537. return QDF_STATUS_E_FAILURE;
  1538. }
  1539. }
  1540. return QDF_STATUS_SUCCESS;
  1541. }
  1542. #else
  1543. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1544. struct dp_pdev *pdev)
  1545. {
  1546. return QDF_STATUS_SUCCESS;
  1547. }
  1548. #endif
  1549. /**
  1550. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1551. * @pdev - DP_PDEV handle
  1552. *
  1553. * Return: void
  1554. */
  1555. static inline void
  1556. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1557. {
  1558. uint8_t map_id;
  1559. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1560. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1561. sizeof(default_dscp_tid_map));
  1562. }
  1563. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1564. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1565. pdev->dscp_tid_map[map_id],
  1566. map_id);
  1567. }
  1568. }
  1569. /*
  1570. * dp_reset_intr_mask() - reset interrupt mask
  1571. * @dp_soc - DP Soc handle
  1572. * @dp_pdev - DP pdev handle
  1573. *
  1574. * Return: Return void
  1575. */
  1576. static inline
  1577. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1578. {
  1579. /*
  1580. * We will set the interrupt mask to zero for NSS offloaded radio
  1581. */
  1582. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1583. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1584. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1585. }
  1586. /*
  1587. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1588. * @soc: data path SoC handle
  1589. *
  1590. * Return: none
  1591. */
  1592. #ifdef IPA_OFFLOAD
  1593. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1594. struct dp_pdev *pdev)
  1595. {
  1596. void *hal_srng;
  1597. struct hal_srng_params srng_params;
  1598. qdf_dma_addr_t hp_addr, tp_addr;
  1599. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1600. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1601. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1602. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1603. srng_params.ring_base_paddr;
  1604. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1605. srng_params.ring_base_vaddr;
  1606. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1607. srng_params.num_entries * srng_params.entry_size;
  1608. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1609. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1610. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1611. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1612. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1613. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1614. srng_params.ring_base_paddr;
  1615. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1616. srng_params.ring_base_vaddr;
  1617. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1618. srng_params.num_entries * srng_params.entry_size;
  1619. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1620. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1621. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1622. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1623. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1624. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1625. srng_params.ring_base_paddr;
  1626. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1627. srng_params.ring_base_vaddr;
  1628. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1629. srng_params.num_entries * srng_params.entry_size;
  1630. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1631. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1632. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1633. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1634. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1635. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1636. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1637. __func__);
  1638. return -EFAULT;
  1639. }
  1640. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1641. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1642. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1643. srng_params.ring_base_paddr;
  1644. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1645. srng_params.ring_base_vaddr;
  1646. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1647. srng_params.num_entries * srng_params.entry_size;
  1648. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1649. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1650. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1651. "%s: ring_base_paddr:%p, ring_base_vaddr:%p"
  1652. "_entries:%d, hp_addr:%p\n",
  1653. __func__,
  1654. (void *)srng_params.ring_base_paddr,
  1655. (void *)srng_params.ring_base_vaddr,
  1656. srng_params.num_entries,
  1657. (void *)hp_addr);
  1658. return 0;
  1659. }
  1660. #else
  1661. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1662. struct dp_pdev *pdev)
  1663. {
  1664. return 0;
  1665. }
  1666. #endif
  1667. /*
  1668. * dp_pdev_attach_wifi3() - attach txrx pdev
  1669. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1670. * @txrx_soc: Datapath SOC handle
  1671. * @htc_handle: HTC handle for host-target interface
  1672. * @qdf_osdev: QDF OS device
  1673. * @pdev_id: PDEV ID
  1674. *
  1675. * Return: DP PDEV handle on success, NULL on failure
  1676. */
  1677. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1678. struct cdp_cfg *ctrl_pdev,
  1679. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1680. {
  1681. int tx_ring_size;
  1682. int tx_comp_ring_size;
  1683. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1684. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1685. if (!pdev) {
  1686. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1687. FL("DP PDEV memory allocation failed"));
  1688. goto fail0;
  1689. }
  1690. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1691. if (!pdev->wlan_cfg_ctx) {
  1692. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1693. FL("pdev cfg_attach failed"));
  1694. qdf_mem_free(pdev);
  1695. goto fail0;
  1696. }
  1697. /*
  1698. * set nss pdev config based on soc config
  1699. */
  1700. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1701. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1702. pdev->soc = soc;
  1703. pdev->osif_pdev = ctrl_pdev;
  1704. pdev->pdev_id = pdev_id;
  1705. soc->pdev_list[pdev_id] = pdev;
  1706. soc->pdev_count++;
  1707. TAILQ_INIT(&pdev->vdev_list);
  1708. pdev->vdev_count = 0;
  1709. qdf_spinlock_create(&pdev->tx_mutex);
  1710. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1711. TAILQ_INIT(&pdev->neighbour_peers_list);
  1712. if (dp_soc_cmn_setup(soc)) {
  1713. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1714. FL("dp_soc_cmn_setup failed"));
  1715. goto fail1;
  1716. }
  1717. /* Setup per PDEV TCL rings if configured */
  1718. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1719. tx_ring_size =
  1720. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1721. tx_comp_ring_size =
  1722. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1723. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1724. pdev_id, pdev_id, tx_ring_size)) {
  1725. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1726. FL("dp_srng_setup failed for tcl_data_ring"));
  1727. goto fail1;
  1728. }
  1729. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1730. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1731. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1732. FL("dp_srng_setup failed for tx_comp_ring"));
  1733. goto fail1;
  1734. }
  1735. soc->num_tcl_data_rings++;
  1736. }
  1737. /* Tx specific init */
  1738. if (dp_tx_pdev_attach(pdev)) {
  1739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1740. FL("dp_tx_pdev_attach failed"));
  1741. goto fail1;
  1742. }
  1743. /* Setup per PDEV REO rings if configured */
  1744. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1745. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1746. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1747. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1748. FL("dp_srng_setup failed for reo_dest_ringn"));
  1749. goto fail1;
  1750. }
  1751. soc->num_reo_dest_rings++;
  1752. }
  1753. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1754. RXDMA_REFILL_RING_SIZE)) {
  1755. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1756. FL("dp_srng_setup failed rx refill ring"));
  1757. goto fail1;
  1758. }
  1759. if (dp_rxdma_ring_setup(soc, pdev)) {
  1760. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1761. FL("RXDMA ring config failed"));
  1762. goto fail1;
  1763. }
  1764. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1765. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1766. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1767. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1768. goto fail1;
  1769. }
  1770. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1771. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1772. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1773. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1774. goto fail1;
  1775. }
  1776. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1777. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1778. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1780. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1781. goto fail1;
  1782. }
  1783. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1784. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1785. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1786. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1787. goto fail1;
  1788. }
  1789. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  1790. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  1791. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1792. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1793. goto fail1;
  1794. }
  1795. if (dp_ipa_ring_resource_setup(soc, pdev))
  1796. goto fail1;
  1797. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  1798. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1799. "%s: dp_ipa_uc_attach failed\n", __func__);
  1800. goto fail1;
  1801. }
  1802. /* Rx specific init */
  1803. if (dp_rx_pdev_attach(pdev)) {
  1804. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1805. FL("dp_rx_pdev_attach failed "));
  1806. goto fail0;
  1807. }
  1808. DP_STATS_INIT(pdev);
  1809. #ifndef CONFIG_WIN
  1810. /* MCL */
  1811. dp_local_peer_id_pool_init(pdev);
  1812. #endif
  1813. dp_dscp_tid_map_setup(pdev);
  1814. /* Rx monitor mode specific init */
  1815. if (dp_rx_pdev_mon_attach(pdev)) {
  1816. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1817. "dp_rx_pdev_attach failed\n");
  1818. goto fail1;
  1819. }
  1820. if (dp_wdi_event_attach(pdev)) {
  1821. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1822. "dp_wdi_evet_attach failed\n");
  1823. goto fail1;
  1824. }
  1825. /* set the reo destination during initialization */
  1826. pdev->reo_dest = pdev->pdev_id + 1;
  1827. /*
  1828. * reset the interrupt mask for offloaded radio
  1829. */
  1830. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  1831. dp_soc_reset_intr_mask(soc, pdev);
  1832. }
  1833. return (struct cdp_pdev *)pdev;
  1834. fail1:
  1835. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  1836. fail0:
  1837. return NULL;
  1838. }
  1839. /*
  1840. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  1841. * @soc: data path SoC handle
  1842. * @pdev: Physical device handle
  1843. *
  1844. * Return: void
  1845. */
  1846. #ifdef QCA_HOST2FW_RXBUF_RING
  1847. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1848. struct dp_pdev *pdev)
  1849. {
  1850. int max_mac_rings =
  1851. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  1852. int i;
  1853. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  1854. max_mac_rings : MAX_RX_MAC_RINGS;
  1855. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  1856. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  1857. RXDMA_BUF, 1);
  1858. }
  1859. #else
  1860. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1861. struct dp_pdev *pdev)
  1862. {
  1863. }
  1864. #endif
  1865. /*
  1866. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  1867. * @pdev: device object
  1868. *
  1869. * Return: void
  1870. */
  1871. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  1872. {
  1873. struct dp_neighbour_peer *peer = NULL;
  1874. struct dp_neighbour_peer *temp_peer = NULL;
  1875. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  1876. neighbour_peer_list_elem, temp_peer) {
  1877. /* delete this peer from the list */
  1878. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  1879. peer, neighbour_peer_list_elem);
  1880. qdf_mem_free(peer);
  1881. }
  1882. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  1883. }
  1884. /*
  1885. * dp_pdev_detach_wifi3() - detach txrx pdev
  1886. * @txrx_pdev: Datapath PDEV handle
  1887. * @force: Force detach
  1888. *
  1889. */
  1890. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  1891. {
  1892. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  1893. struct dp_soc *soc = pdev->soc;
  1894. dp_wdi_event_detach(pdev);
  1895. dp_tx_pdev_detach(pdev);
  1896. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1897. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  1898. TCL_DATA, pdev->pdev_id);
  1899. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  1900. WBM2SW_RELEASE, pdev->pdev_id);
  1901. }
  1902. dp_rx_pdev_detach(pdev);
  1903. dp_rx_pdev_mon_detach(pdev);
  1904. dp_neighbour_peers_detach(pdev);
  1905. qdf_spinlock_destroy(&pdev->tx_mutex);
  1906. dp_ipa_uc_detach(soc, pdev);
  1907. /* Cleanup per PDEV REO rings if configured */
  1908. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1909. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  1910. REO_DST, pdev->pdev_id);
  1911. }
  1912. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  1913. dp_rxdma_ring_cleanup(soc, pdev);
  1914. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  1915. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  1916. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  1917. RXDMA_MONITOR_STATUS, 0);
  1918. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  1919. RXDMA_MONITOR_DESC, 0);
  1920. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  1921. soc->pdev_list[pdev->pdev_id] = NULL;
  1922. soc->pdev_count--;
  1923. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  1924. qdf_mem_free(pdev);
  1925. }
  1926. /*
  1927. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  1928. * @soc: DP SOC handle
  1929. */
  1930. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  1931. {
  1932. struct reo_desc_list_node *desc;
  1933. struct dp_rx_tid *rx_tid;
  1934. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  1935. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  1936. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  1937. rx_tid = &desc->rx_tid;
  1938. qdf_mem_unmap_nbytes_single(soc->osdev,
  1939. rx_tid->hw_qdesc_paddr,
  1940. QDF_DMA_BIDIRECTIONAL,
  1941. rx_tid->hw_qdesc_alloc_size);
  1942. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  1943. qdf_mem_free(desc);
  1944. }
  1945. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  1946. qdf_list_destroy(&soc->reo_desc_freelist);
  1947. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  1948. }
  1949. /*
  1950. * dp_soc_detach_wifi3() - Detach txrx SOC
  1951. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  1952. */
  1953. static void dp_soc_detach_wifi3(void *txrx_soc)
  1954. {
  1955. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1956. int i;
  1957. qdf_atomic_set(&soc->cmn_init_done, 0);
  1958. qdf_flush_work(0, &soc->htt_stats_work);
  1959. qdf_disable_work(0, &soc->htt_stats_work);
  1960. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1961. if (soc->pdev_list[i])
  1962. dp_pdev_detach_wifi3(
  1963. (struct cdp_pdev *)soc->pdev_list[i], 1);
  1964. }
  1965. dp_peer_find_detach(soc);
  1966. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  1967. * SW descriptors
  1968. */
  1969. /* Free the ring memories */
  1970. /* Common rings */
  1971. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  1972. dp_tx_soc_detach(soc);
  1973. /* Tx data rings */
  1974. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1975. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1976. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  1977. TCL_DATA, i);
  1978. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  1979. WBM2SW_RELEASE, i);
  1980. }
  1981. }
  1982. /* TCL command and status rings */
  1983. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  1984. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  1985. /* Rx data rings */
  1986. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1987. soc->num_reo_dest_rings =
  1988. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1989. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1990. /* TODO: Get number of rings and ring sizes
  1991. * from wlan_cfg
  1992. */
  1993. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  1994. REO_DST, i);
  1995. }
  1996. }
  1997. /* REO reinjection ring */
  1998. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  1999. /* Rx release ring */
  2000. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2001. /* Rx exception ring */
  2002. /* TODO: Better to store ring_type and ring_num in
  2003. * dp_srng during setup
  2004. */
  2005. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2006. /* REO command and status rings */
  2007. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2008. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2009. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2010. htt_soc_detach(soc->htt_handle);
  2011. dp_reo_cmdlist_destroy(soc);
  2012. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2013. dp_reo_desc_freelist_destroy(soc);
  2014. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2015. dp_soc_wds_detach(soc);
  2016. qdf_mem_free(soc);
  2017. }
  2018. /*
  2019. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2020. * @soc: data path SoC handle
  2021. * @pdev: physical device handle
  2022. *
  2023. * Return: void
  2024. */
  2025. #ifdef IPA_OFFLOAD
  2026. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2027. struct dp_pdev *pdev)
  2028. {
  2029. htt_srng_setup(soc->htt_handle, 0,
  2030. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2031. }
  2032. #else
  2033. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2034. struct dp_pdev *pdev)
  2035. {
  2036. }
  2037. #endif
  2038. /*
  2039. * dp_rxdma_ring_config() - configure the RX DMA rings
  2040. *
  2041. * This function is used to configure the MAC rings.
  2042. * On MCL host provides buffers in Host2FW ring
  2043. * FW refills (copies) buffers to the ring and updates
  2044. * ring_idx in register
  2045. *
  2046. * @soc: data path SoC handle
  2047. *
  2048. * Return: void
  2049. */
  2050. #ifdef QCA_HOST2FW_RXBUF_RING
  2051. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2052. {
  2053. int i;
  2054. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2055. struct dp_pdev *pdev = soc->pdev_list[i];
  2056. if (pdev) {
  2057. int mac_id = 0;
  2058. int j;
  2059. bool dbs_enable = 0;
  2060. int max_mac_rings =
  2061. wlan_cfg_get_num_mac_rings
  2062. (pdev->wlan_cfg_ctx);
  2063. htt_srng_setup(soc->htt_handle, 0,
  2064. pdev->rx_refill_buf_ring.hal_srng,
  2065. RXDMA_BUF);
  2066. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2067. if (soc->cdp_soc.ol_ops->
  2068. is_hw_dbs_2x2_capable) {
  2069. dbs_enable = soc->cdp_soc.ol_ops->
  2070. is_hw_dbs_2x2_capable(soc->psoc);
  2071. }
  2072. if (dbs_enable) {
  2073. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2074. QDF_TRACE_LEVEL_ERROR,
  2075. FL("DBS enabled max_mac_rings %d\n"),
  2076. max_mac_rings);
  2077. } else {
  2078. max_mac_rings = 1;
  2079. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2080. QDF_TRACE_LEVEL_ERROR,
  2081. FL("DBS disabled, max_mac_rings %d\n"),
  2082. max_mac_rings);
  2083. }
  2084. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2085. FL("pdev_id %d max_mac_rings %d\n"),
  2086. pdev->pdev_id, max_mac_rings);
  2087. for (j = 0; j < max_mac_rings; j++) {
  2088. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2089. QDF_TRACE_LEVEL_ERROR,
  2090. FL("mac_id %d\n"), mac_id);
  2091. htt_srng_setup(soc->htt_handle, mac_id,
  2092. pdev->rx_mac_buf_ring[j]
  2093. .hal_srng,
  2094. RXDMA_BUF);
  2095. mac_id++;
  2096. }
  2097. /* Configure monitor mode rings */
  2098. htt_srng_setup(soc->htt_handle, i,
  2099. pdev->rxdma_mon_buf_ring.hal_srng,
  2100. RXDMA_MONITOR_BUF);
  2101. htt_srng_setup(soc->htt_handle, i,
  2102. pdev->rxdma_mon_dst_ring.hal_srng,
  2103. RXDMA_MONITOR_DST);
  2104. htt_srng_setup(soc->htt_handle, i,
  2105. pdev->rxdma_mon_status_ring.hal_srng,
  2106. RXDMA_MONITOR_STATUS);
  2107. htt_srng_setup(soc->htt_handle, i,
  2108. pdev->rxdma_mon_desc_ring.hal_srng,
  2109. RXDMA_MONITOR_DESC);
  2110. htt_srng_setup(soc->htt_handle, i,
  2111. pdev->rxdma_err_dst_ring.hal_srng,
  2112. RXDMA_DST);
  2113. }
  2114. }
  2115. }
  2116. #else
  2117. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2118. {
  2119. int i;
  2120. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2121. struct dp_pdev *pdev = soc->pdev_list[i];
  2122. if (pdev) {
  2123. htt_srng_setup(soc->htt_handle, i,
  2124. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2125. htt_srng_setup(soc->htt_handle, i,
  2126. pdev->rxdma_mon_buf_ring.hal_srng,
  2127. RXDMA_MONITOR_BUF);
  2128. htt_srng_setup(soc->htt_handle, i,
  2129. pdev->rxdma_mon_dst_ring.hal_srng,
  2130. RXDMA_MONITOR_DST);
  2131. htt_srng_setup(soc->htt_handle, i,
  2132. pdev->rxdma_mon_status_ring.hal_srng,
  2133. RXDMA_MONITOR_STATUS);
  2134. htt_srng_setup(soc->htt_handle, i,
  2135. pdev->rxdma_mon_desc_ring.hal_srng,
  2136. RXDMA_MONITOR_DESC);
  2137. htt_srng_setup(soc->htt_handle, i,
  2138. pdev->rxdma_err_dst_ring.hal_srng,
  2139. RXDMA_DST);
  2140. }
  2141. }
  2142. }
  2143. #endif
  2144. /*
  2145. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2146. * @txrx_soc: Datapath SOC handle
  2147. */
  2148. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2149. {
  2150. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2151. htt_soc_attach_target(soc->htt_handle);
  2152. dp_rxdma_ring_config(soc);
  2153. DP_STATS_INIT(soc);
  2154. /* initialize work queue for stats processing */
  2155. qdf_create_work(0, &soc->htt_stats_work, htt_t2h_stats_handler, soc);
  2156. return 0;
  2157. }
  2158. /*
  2159. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2160. * @txrx_soc: Datapath SOC handle
  2161. */
  2162. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2163. {
  2164. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2165. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2166. }
  2167. /*
  2168. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2169. * @txrx_soc: Datapath SOC handle
  2170. * @nss_cfg: nss config
  2171. */
  2172. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2173. {
  2174. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2175. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2176. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2177. FL("nss-wifi<0> nss config is enabled"));
  2178. }
  2179. /*
  2180. * dp_vdev_attach_wifi3() - attach txrx vdev
  2181. * @txrx_pdev: Datapath PDEV handle
  2182. * @vdev_mac_addr: MAC address of the virtual interface
  2183. * @vdev_id: VDEV Id
  2184. * @wlan_op_mode: VDEV operating mode
  2185. *
  2186. * Return: DP VDEV handle on success, NULL on failure
  2187. */
  2188. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2189. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2190. {
  2191. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2192. struct dp_soc *soc = pdev->soc;
  2193. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2194. int tx_ring_size;
  2195. if (!vdev) {
  2196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2197. FL("DP VDEV memory allocation failed"));
  2198. goto fail0;
  2199. }
  2200. vdev->pdev = pdev;
  2201. vdev->vdev_id = vdev_id;
  2202. vdev->opmode = op_mode;
  2203. vdev->osdev = soc->osdev;
  2204. vdev->osif_rx = NULL;
  2205. vdev->osif_rsim_rx_decap = NULL;
  2206. vdev->osif_rx_mon = NULL;
  2207. vdev->osif_tx_free_ext = NULL;
  2208. vdev->osif_vdev = NULL;
  2209. vdev->delete.pending = 0;
  2210. vdev->safemode = 0;
  2211. vdev->drop_unenc = 1;
  2212. #ifdef notyet
  2213. vdev->filters_num = 0;
  2214. #endif
  2215. qdf_mem_copy(
  2216. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2217. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2218. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2219. vdev->dscp_tid_map_id = 0;
  2220. vdev->mcast_enhancement_en = 0;
  2221. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2222. /* TODO: Initialize default HTT meta data that will be used in
  2223. * TCL descriptors for packets transmitted from this VDEV
  2224. */
  2225. TAILQ_INIT(&vdev->peer_list);
  2226. /* add this vdev into the pdev's list */
  2227. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2228. pdev->vdev_count++;
  2229. dp_tx_vdev_attach(vdev);
  2230. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2231. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2232. goto fail1;
  2233. if ((soc->intr_mode == DP_INTR_POLL) &&
  2234. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2235. if (pdev->vdev_count == 1)
  2236. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2237. }
  2238. dp_lro_hash_setup(soc);
  2239. /* LRO */
  2240. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2241. wlan_op_mode_sta == vdev->opmode)
  2242. vdev->lro_enable = true;
  2243. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2244. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2246. "Created vdev %p (%pM)", vdev, vdev->mac_addr.raw);
  2247. DP_STATS_INIT(vdev);
  2248. return (struct cdp_vdev *)vdev;
  2249. fail1:
  2250. dp_tx_vdev_detach(vdev);
  2251. qdf_mem_free(vdev);
  2252. fail0:
  2253. return NULL;
  2254. }
  2255. /**
  2256. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2257. * @vdev: Datapath VDEV handle
  2258. * @osif_vdev: OSIF vdev handle
  2259. * @txrx_ops: Tx and Rx operations
  2260. *
  2261. * Return: DP VDEV handle on success, NULL on failure
  2262. */
  2263. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2264. void *osif_vdev,
  2265. struct ol_txrx_ops *txrx_ops)
  2266. {
  2267. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2268. vdev->osif_vdev = osif_vdev;
  2269. vdev->osif_rx = txrx_ops->rx.rx;
  2270. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2271. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2272. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2273. #ifdef notyet
  2274. #if ATH_SUPPORT_WAPI
  2275. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2276. #endif
  2277. #endif
  2278. #ifdef UMAC_SUPPORT_PROXY_ARP
  2279. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2280. #endif
  2281. vdev->me_convert = txrx_ops->me_convert;
  2282. /* TODO: Enable the following once Tx code is integrated */
  2283. txrx_ops->tx.tx = dp_tx_send;
  2284. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2285. "DP Vdev Register success");
  2286. }
  2287. /*
  2288. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2289. * @txrx_vdev: Datapath VDEV handle
  2290. * @callback: Callback OL_IF on completion of detach
  2291. * @cb_context: Callback context
  2292. *
  2293. */
  2294. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2295. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2296. {
  2297. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2298. struct dp_pdev *pdev = vdev->pdev;
  2299. struct dp_soc *soc = pdev->soc;
  2300. /* preconditions */
  2301. qdf_assert(vdev);
  2302. /* remove the vdev from its parent pdev's list */
  2303. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2304. /*
  2305. * Use peer_ref_mutex while accessing peer_list, in case
  2306. * a peer is in the process of being removed from the list.
  2307. */
  2308. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2309. /* check that the vdev has no peers allocated */
  2310. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2311. /* debug print - will be removed later */
  2312. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2313. FL("not deleting vdev object %p (%pM)"
  2314. "until deletion finishes for all its peers"),
  2315. vdev, vdev->mac_addr.raw);
  2316. /* indicate that the vdev needs to be deleted */
  2317. vdev->delete.pending = 1;
  2318. vdev->delete.callback = callback;
  2319. vdev->delete.context = cb_context;
  2320. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2321. return;
  2322. }
  2323. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2324. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2325. vdev->vdev_id);
  2326. dp_tx_vdev_detach(vdev);
  2327. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2328. FL("deleting vdev object %p (%pM)"), vdev, vdev->mac_addr.raw);
  2329. qdf_mem_free(vdev);
  2330. if (callback)
  2331. callback(cb_context);
  2332. }
  2333. /*
  2334. * dp_peer_create_wifi3() - attach txrx peer
  2335. * @txrx_vdev: Datapath VDEV handle
  2336. * @peer_mac_addr: Peer MAC address
  2337. *
  2338. * Return: DP peeer handle on success, NULL on failure
  2339. */
  2340. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2341. uint8_t *peer_mac_addr)
  2342. {
  2343. struct dp_peer *peer;
  2344. int i;
  2345. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2346. struct dp_pdev *pdev;
  2347. struct dp_soc *soc;
  2348. /* preconditions */
  2349. qdf_assert(vdev);
  2350. qdf_assert(peer_mac_addr);
  2351. pdev = vdev->pdev;
  2352. soc = pdev->soc;
  2353. #ifdef notyet
  2354. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2355. soc->mempool_ol_ath_peer);
  2356. #else
  2357. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2358. #endif
  2359. if (!peer)
  2360. return NULL; /* failure */
  2361. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2362. TAILQ_INIT(&peer->ast_entry_list);
  2363. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2364. qdf_spinlock_create(&peer->peer_info_lock);
  2365. /* store provided params */
  2366. peer->vdev = vdev;
  2367. qdf_mem_copy(
  2368. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2369. /* TODO: See of rx_opt_proc is really required */
  2370. peer->rx_opt_proc = soc->rx_opt_proc;
  2371. /* initialize the peer_id */
  2372. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2373. peer->peer_ids[i] = HTT_INVALID_PEER;
  2374. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2375. qdf_atomic_init(&peer->ref_cnt);
  2376. /* keep one reference for attach */
  2377. qdf_atomic_inc(&peer->ref_cnt);
  2378. /* add this peer into the vdev's list */
  2379. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2380. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2381. /* TODO: See if hash based search is required */
  2382. dp_peer_find_hash_add(soc, peer);
  2383. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2384. "vdev %p created peer %p (%pM) ref_cnt: %d",
  2385. vdev, peer, peer->mac_addr.raw,
  2386. qdf_atomic_read(&peer->ref_cnt));
  2387. /*
  2388. * For every peer MAp message search and set if bss_peer
  2389. */
  2390. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2391. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2392. "vdev bss_peer!!!!");
  2393. peer->bss_peer = 1;
  2394. vdev->vap_bss_peer = peer;
  2395. }
  2396. #ifndef CONFIG_WIN
  2397. dp_local_peer_id_alloc(pdev, peer);
  2398. #endif
  2399. DP_STATS_INIT(peer);
  2400. return (void *)peer;
  2401. }
  2402. /*
  2403. * dp_peer_setup_wifi3() - initialize the peer
  2404. * @vdev_hdl: virtual device object
  2405. * @peer: Peer object
  2406. *
  2407. * Return: void
  2408. */
  2409. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2410. {
  2411. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2412. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2413. struct dp_pdev *pdev;
  2414. struct dp_soc *soc;
  2415. bool hash_based = 0;
  2416. enum cdp_host_reo_dest_ring reo_dest;
  2417. /* preconditions */
  2418. qdf_assert(vdev);
  2419. qdf_assert(peer);
  2420. pdev = vdev->pdev;
  2421. soc = pdev->soc;
  2422. dp_peer_rx_init(pdev, peer);
  2423. peer->last_assoc_rcvd = 0;
  2424. peer->last_disassoc_rcvd = 0;
  2425. peer->last_deauth_rcvd = 0;
  2426. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2428. FL("hash based steering %d\n"), hash_based);
  2429. if (!hash_based)
  2430. reo_dest = pdev->reo_dest;
  2431. else
  2432. reo_dest = 1;
  2433. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2434. /* TODO: Check the destination ring number to be passed to FW */
  2435. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2436. pdev->osif_pdev, peer->mac_addr.raw,
  2437. peer->vdev->vdev_id, hash_based, reo_dest);
  2438. }
  2439. return;
  2440. }
  2441. /*
  2442. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2443. * @vdev_handle: virtual device object
  2444. * @htt_pkt_type: type of pkt
  2445. *
  2446. * Return: void
  2447. */
  2448. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2449. enum htt_cmn_pkt_type val)
  2450. {
  2451. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2452. vdev->tx_encap_type = val;
  2453. }
  2454. /*
  2455. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2456. * @vdev_handle: virtual device object
  2457. * @htt_pkt_type: type of pkt
  2458. *
  2459. * Return: void
  2460. */
  2461. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2462. enum htt_cmn_pkt_type val)
  2463. {
  2464. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2465. vdev->rx_decap_type = val;
  2466. }
  2467. /*
  2468. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2469. * @pdev_handle: physical device object
  2470. * @val: reo destination ring index (1 - 4)
  2471. *
  2472. * Return: void
  2473. */
  2474. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2475. enum cdp_host_reo_dest_ring val)
  2476. {
  2477. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2478. if (pdev)
  2479. pdev->reo_dest = val;
  2480. }
  2481. /*
  2482. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2483. * @pdev_handle: physical device object
  2484. *
  2485. * Return: reo destination ring index
  2486. */
  2487. static enum cdp_host_reo_dest_ring
  2488. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2489. {
  2490. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2491. if (pdev)
  2492. return pdev->reo_dest;
  2493. else
  2494. return cdp_host_reo_dest_ring_unknown;
  2495. }
  2496. #ifdef QCA_SUPPORT_SON
  2497. static void dp_son_peer_authorize(struct dp_peer *peer)
  2498. {
  2499. struct dp_soc *soc;
  2500. soc = peer->vdev->pdev->soc;
  2501. peer->peer_bs_inact_flag = 0;
  2502. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2503. return;
  2504. }
  2505. #else
  2506. static void dp_son_peer_authorize(struct dp_peer *peer)
  2507. {
  2508. return;
  2509. }
  2510. #endif
  2511. /*
  2512. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2513. * @pdev_handle: device object
  2514. * @val: value to be set
  2515. *
  2516. * Return: void
  2517. */
  2518. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2519. uint32_t val)
  2520. {
  2521. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2522. /* Enable/Disable smart mesh filtering. This flag will be checked
  2523. * during rx processing to check if packets are from NAC clients.
  2524. */
  2525. pdev->filter_neighbour_peers = val;
  2526. return 0;
  2527. }
  2528. /*
  2529. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2530. * address for smart mesh filtering
  2531. * @pdev_handle: device object
  2532. * @cmd: Add/Del command
  2533. * @macaddr: nac client mac address
  2534. *
  2535. * Return: void
  2536. */
  2537. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2538. uint32_t cmd, uint8_t *macaddr)
  2539. {
  2540. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2541. struct dp_neighbour_peer *peer = NULL;
  2542. if (!macaddr)
  2543. goto fail0;
  2544. /* Store address of NAC (neighbour peer) which will be checked
  2545. * against TA of received packets.
  2546. */
  2547. if (cmd == DP_NAC_PARAM_ADD) {
  2548. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2549. sizeof(*peer));
  2550. if (!peer) {
  2551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2552. FL("DP neighbour peer node memory allocation failed"));
  2553. goto fail0;
  2554. }
  2555. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2556. macaddr, DP_MAC_ADDR_LEN);
  2557. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2558. /* add this neighbour peer into the list */
  2559. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2560. neighbour_peer_list_elem);
  2561. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2562. return 1;
  2563. } else if (cmd == DP_NAC_PARAM_DEL) {
  2564. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2565. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2566. neighbour_peer_list_elem) {
  2567. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2568. macaddr, DP_MAC_ADDR_LEN)) {
  2569. /* delete this peer from the list */
  2570. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2571. peer, neighbour_peer_list_elem);
  2572. qdf_mem_free(peer);
  2573. break;
  2574. }
  2575. }
  2576. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2577. return 1;
  2578. }
  2579. fail0:
  2580. return 0;
  2581. }
  2582. /*
  2583. * dp_peer_authorize() - authorize txrx peer
  2584. * @peer_handle: Datapath peer handle
  2585. * @authorize
  2586. *
  2587. */
  2588. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2589. {
  2590. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2591. struct dp_soc *soc;
  2592. if (peer != NULL) {
  2593. soc = peer->vdev->pdev->soc;
  2594. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2595. dp_son_peer_authorize(peer);
  2596. peer->authorize = authorize ? 1 : 0;
  2597. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2598. }
  2599. }
  2600. /*
  2601. * dp_peer_unref_delete() - unref and delete peer
  2602. * @peer_handle: Datapath peer handle
  2603. *
  2604. */
  2605. void dp_peer_unref_delete(void *peer_handle)
  2606. {
  2607. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2608. struct dp_vdev *vdev = peer->vdev;
  2609. struct dp_pdev *pdev = vdev->pdev;
  2610. struct dp_soc *soc = pdev->soc;
  2611. struct dp_peer *tmppeer;
  2612. int found = 0;
  2613. uint16_t peer_id;
  2614. /*
  2615. * Hold the lock all the way from checking if the peer ref count
  2616. * is zero until the peer references are removed from the hash
  2617. * table and vdev list (if the peer ref count is zero).
  2618. * This protects against a new HL tx operation starting to use the
  2619. * peer object just after this function concludes it's done being used.
  2620. * Furthermore, the lock needs to be held while checking whether the
  2621. * vdev's list of peers is empty, to make sure that list is not modified
  2622. * concurrently with the empty check.
  2623. */
  2624. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2625. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2626. "%s: peer %p ref_cnt(before decrement): %d\n", __func__,
  2627. peer, qdf_atomic_read(&peer->ref_cnt));
  2628. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2629. peer_id = peer->peer_ids[0];
  2630. /*
  2631. * Make sure that the reference to the peer in
  2632. * peer object map is removed
  2633. */
  2634. if (peer_id != HTT_INVALID_PEER)
  2635. soc->peer_id_to_obj_map[peer_id] = NULL;
  2636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2637. "Deleting peer %p (%pM)", peer, peer->mac_addr.raw);
  2638. /* remove the reference to the peer from the hash table */
  2639. dp_peer_find_hash_remove(soc, peer);
  2640. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2641. if (tmppeer == peer) {
  2642. found = 1;
  2643. break;
  2644. }
  2645. }
  2646. if (found) {
  2647. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2648. peer_list_elem);
  2649. } else {
  2650. /*Ignoring the remove operation as peer not found*/
  2651. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2652. "peer %p not found in vdev (%p)->peer_list:%p",
  2653. peer, vdev, &peer->vdev->peer_list);
  2654. }
  2655. /* cleanup the peer data */
  2656. dp_peer_cleanup(vdev, peer);
  2657. /* check whether the parent vdev has no peers left */
  2658. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2659. /*
  2660. * Now that there are no references to the peer, we can
  2661. * release the peer reference lock.
  2662. */
  2663. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2664. /*
  2665. * Check if the parent vdev was waiting for its peers
  2666. * to be deleted, in order for it to be deleted too.
  2667. */
  2668. if (vdev->delete.pending) {
  2669. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2670. vdev->delete.callback;
  2671. void *vdev_delete_context =
  2672. vdev->delete.context;
  2673. QDF_TRACE(QDF_MODULE_ID_DP,
  2674. QDF_TRACE_LEVEL_INFO_HIGH,
  2675. FL("deleting vdev object %p (%pM)"
  2676. " - its last peer is done"),
  2677. vdev, vdev->mac_addr.raw);
  2678. /* all peers are gone, go ahead and delete it */
  2679. qdf_mem_free(vdev);
  2680. if (vdev_delete_cb)
  2681. vdev_delete_cb(vdev_delete_context);
  2682. }
  2683. } else {
  2684. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2685. }
  2686. #ifdef notyet
  2687. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2688. #else
  2689. qdf_mem_free(peer);
  2690. #endif
  2691. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2692. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2693. vdev->vdev_id, peer->mac_addr.raw);
  2694. }
  2695. } else {
  2696. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2697. }
  2698. }
  2699. /*
  2700. * dp_peer_detach_wifi3() – Detach txrx peer
  2701. * @peer_handle: Datapath peer handle
  2702. *
  2703. */
  2704. static void dp_peer_delete_wifi3(void *peer_handle)
  2705. {
  2706. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2707. /* redirect the peer's rx delivery function to point to a
  2708. * discard func
  2709. */
  2710. peer->rx_opt_proc = dp_rx_discard;
  2711. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2712. FL("peer %p (%pM)"), peer, peer->mac_addr.raw);
  2713. #ifndef CONFIG_WIN
  2714. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2715. #endif
  2716. qdf_spinlock_destroy(&peer->peer_info_lock);
  2717. /*
  2718. * Remove the reference added during peer_attach.
  2719. * The peer will still be left allocated until the
  2720. * PEER_UNMAP message arrives to remove the other
  2721. * reference, added by the PEER_MAP message.
  2722. */
  2723. dp_peer_unref_delete(peer_handle);
  2724. }
  2725. /*
  2726. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2727. * @peer_handle: Datapath peer handle
  2728. *
  2729. */
  2730. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2731. {
  2732. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2733. return vdev->mac_addr.raw;
  2734. }
  2735. /*
  2736. * dp_vdev_set_wds() - Enable per packet stats
  2737. * @vdev_handle: DP VDEV handle
  2738. * @val: value
  2739. *
  2740. * Return: none
  2741. */
  2742. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2743. {
  2744. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2745. vdev->wds_enabled = val;
  2746. return 0;
  2747. }
  2748. /*
  2749. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2750. * @peer_handle: Datapath peer handle
  2751. *
  2752. */
  2753. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2754. uint8_t vdev_id)
  2755. {
  2756. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2757. struct dp_vdev *vdev = NULL;
  2758. if (qdf_unlikely(!pdev))
  2759. return NULL;
  2760. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2761. if (vdev->vdev_id == vdev_id)
  2762. break;
  2763. }
  2764. return (struct cdp_vdev *)vdev;
  2765. }
  2766. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2767. {
  2768. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2769. return vdev->opmode;
  2770. }
  2771. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2772. {
  2773. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2774. struct dp_pdev *pdev = vdev->pdev;
  2775. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2776. }
  2777. /**
  2778. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  2779. * @vdev_handle: Datapath VDEV handle
  2780. * @smart_monitor: Flag to denote if its smart monitor mode
  2781. *
  2782. * Return: 0 on success, not 0 on failure
  2783. */
  2784. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  2785. uint8_t smart_monitor)
  2786. {
  2787. /* Many monitor VAPs can exists in a system but only one can be up at
  2788. * anytime
  2789. */
  2790. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2791. struct dp_pdev *pdev;
  2792. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2793. struct dp_soc *soc;
  2794. uint8_t pdev_id;
  2795. qdf_assert(vdev);
  2796. pdev = vdev->pdev;
  2797. pdev_id = pdev->pdev_id;
  2798. soc = pdev->soc;
  2799. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  2800. "pdev=%p, pdev_id=%d, soc=%p vdev=%p\n",
  2801. pdev, pdev_id, soc, vdev);
  2802. /*Check if current pdev's monitor_vdev exists */
  2803. if (pdev->monitor_vdev) {
  2804. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2805. "vdev=%p\n", vdev);
  2806. qdf_assert(vdev);
  2807. }
  2808. pdev->monitor_vdev = vdev;
  2809. /* If smart monitor mode, do not configure monitor ring */
  2810. if (smart_monitor)
  2811. return QDF_STATUS_SUCCESS;
  2812. htt_tlv_filter.mpdu_start = 1;
  2813. htt_tlv_filter.msdu_start = 1;
  2814. htt_tlv_filter.packet = 1;
  2815. htt_tlv_filter.msdu_end = 1;
  2816. htt_tlv_filter.mpdu_end = 1;
  2817. htt_tlv_filter.packet_header = 1;
  2818. htt_tlv_filter.attention = 1;
  2819. htt_tlv_filter.ppdu_start = 0;
  2820. htt_tlv_filter.ppdu_end = 0;
  2821. htt_tlv_filter.ppdu_end_user_stats = 0;
  2822. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  2823. htt_tlv_filter.ppdu_end_status_done = 0;
  2824. htt_tlv_filter.enable_fp = 1;
  2825. htt_tlv_filter.enable_md = 0;
  2826. htt_tlv_filter.enable_mo = 1;
  2827. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2828. pdev->rxdma_mon_buf_ring.hal_srng,
  2829. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2830. htt_tlv_filter.mpdu_start = 1;
  2831. htt_tlv_filter.msdu_start = 1;
  2832. htt_tlv_filter.packet = 0;
  2833. htt_tlv_filter.msdu_end = 1;
  2834. htt_tlv_filter.mpdu_end = 1;
  2835. htt_tlv_filter.packet_header = 1;
  2836. htt_tlv_filter.attention = 1;
  2837. htt_tlv_filter.ppdu_start = 1;
  2838. htt_tlv_filter.ppdu_end = 1;
  2839. htt_tlv_filter.ppdu_end_user_stats = 1;
  2840. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  2841. htt_tlv_filter.ppdu_end_status_done = 1;
  2842. htt_tlv_filter.enable_fp = 1;
  2843. htt_tlv_filter.enable_md = 0;
  2844. htt_tlv_filter.enable_mo = 1;
  2845. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2846. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2847. RX_BUFFER_SIZE, &htt_tlv_filter);
  2848. return QDF_STATUS_SUCCESS;
  2849. }
  2850. #ifdef MESH_MODE_SUPPORT
  2851. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  2852. {
  2853. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2854. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2855. FL("val %d"), val);
  2856. vdev->mesh_vdev = val;
  2857. }
  2858. /*
  2859. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  2860. * @vdev_hdl: virtual device object
  2861. * @val: value to be set
  2862. *
  2863. * Return: void
  2864. */
  2865. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  2866. {
  2867. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2868. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2869. FL("val %d"), val);
  2870. vdev->mesh_rx_filter = val;
  2871. }
  2872. #endif
  2873. /**
  2874. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  2875. * @vdev: DP VDEV handle
  2876. *
  2877. * return: void
  2878. */
  2879. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  2880. {
  2881. struct dp_peer *peer = NULL;
  2882. int i;
  2883. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  2884. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  2885. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2886. if (!peer)
  2887. return;
  2888. for (i = 0; i <= MAX_MCS; i++) {
  2889. DP_STATS_AGGR(vdev, peer, tx.pkt_type[0].mcs_count[i]);
  2890. DP_STATS_AGGR(vdev, peer, tx.pkt_type[1].mcs_count[i]);
  2891. DP_STATS_AGGR(vdev, peer, tx.pkt_type[2].mcs_count[i]);
  2892. DP_STATS_AGGR(vdev, peer, tx.pkt_type[3].mcs_count[i]);
  2893. DP_STATS_AGGR(vdev, peer, tx.pkt_type[4].mcs_count[i]);
  2894. DP_STATS_AGGR(vdev, peer, rx.pkt_type[0].mcs_count[i]);
  2895. DP_STATS_AGGR(vdev, peer, rx.pkt_type[1].mcs_count[i]);
  2896. DP_STATS_AGGR(vdev, peer, rx.pkt_type[2].mcs_count[i]);
  2897. DP_STATS_AGGR(vdev, peer, rx.pkt_type[3].mcs_count[i]);
  2898. DP_STATS_AGGR(vdev, peer, rx.pkt_type[4].mcs_count[i]);
  2899. }
  2900. for (i = 0; i < SUPPORTED_BW; i++) {
  2901. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  2902. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  2903. }
  2904. for (i = 0; i < SS_COUNT; i++)
  2905. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  2906. for (i = 0; i < WME_AC_MAX; i++) {
  2907. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  2908. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  2909. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  2910. }
  2911. for (i = 0; i < MAX_MCS + 1; i++) {
  2912. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  2913. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  2914. }
  2915. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  2916. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  2917. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  2918. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  2919. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  2920. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  2921. DP_STATS_AGGR(vdev, peer, tx.stbc);
  2922. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  2923. DP_STATS_AGGR(vdev, peer, tx.retries);
  2924. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  2925. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  2926. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard);
  2927. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_retired);
  2928. DP_STATS_AGGR(vdev, peer, tx.dropped.mpdu_age_out);
  2929. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason1);
  2930. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason2);
  2931. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_discard_reason3);
  2932. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  2933. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  2934. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  2935. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  2936. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  2937. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  2938. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  2939. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  2940. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  2941. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  2942. peer->stats.rx.multicast.num;
  2943. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  2944. peer->stats.rx.multicast.bytes;
  2945. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  2946. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  2947. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  2948. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  2949. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  2950. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  2951. vdev->stats.tx.last_ack_rssi =
  2952. peer->stats.tx.last_ack_rssi;
  2953. }
  2954. }
  2955. /**
  2956. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  2957. * @pdev: DP PDEV handle
  2958. *
  2959. * return: void
  2960. */
  2961. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  2962. {
  2963. struct dp_vdev *vdev = NULL;
  2964. uint8_t i;
  2965. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  2966. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  2967. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  2968. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2969. if (!vdev)
  2970. return;
  2971. dp_aggregate_vdev_stats(vdev);
  2972. for (i = 0; i <= MAX_MCS; i++) {
  2973. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[0].mcs_count[i]);
  2974. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[1].mcs_count[i]);
  2975. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[2].mcs_count[i]);
  2976. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[3].mcs_count[i]);
  2977. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[4].mcs_count[i]);
  2978. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[0].mcs_count[i]);
  2979. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[1].mcs_count[i]);
  2980. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[2].mcs_count[i]);
  2981. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[3].mcs_count[i]);
  2982. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[4].mcs_count[i]);
  2983. }
  2984. for (i = 0; i < SUPPORTED_BW; i++) {
  2985. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  2986. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  2987. }
  2988. for (i = 0; i < SS_COUNT; i++)
  2989. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  2990. for (i = 0; i < WME_AC_MAX; i++) {
  2991. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  2992. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  2993. DP_STATS_AGGR(pdev, vdev,
  2994. tx.excess_retries_ac[i]);
  2995. }
  2996. for (i = 0; i < MAX_MCS + 1; i++) {
  2997. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  2998. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  2999. }
  3000. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3001. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3002. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3003. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3004. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3005. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3006. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3007. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3008. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3009. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3010. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3011. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_discard);
  3012. DP_STATS_AGGR(pdev, vdev,
  3013. tx.dropped.fw_discard_retired);
  3014. DP_STATS_AGGR(pdev, vdev, tx.dropped.mpdu_age_out);
  3015. DP_STATS_AGGR(pdev, vdev,
  3016. tx.dropped.fw_discard_reason1);
  3017. DP_STATS_AGGR(pdev, vdev,
  3018. tx.dropped.fw_discard_reason2);
  3019. DP_STATS_AGGR(pdev, vdev,
  3020. tx.dropped.fw_discard_reason3);
  3021. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3022. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3023. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3024. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3025. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3026. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3027. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3028. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3029. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3030. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3031. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3032. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3033. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3034. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3035. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3036. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3037. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3038. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3039. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3040. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3041. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3042. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3043. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3044. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3045. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3046. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3047. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3048. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3049. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3050. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3051. DP_STATS_AGGR(pdev, vdev,
  3052. tx_i.mcast_en.dropped_map_error);
  3053. DP_STATS_AGGR(pdev, vdev,
  3054. tx_i.mcast_en.dropped_self_mac);
  3055. DP_STATS_AGGR(pdev, vdev,
  3056. tx_i.mcast_en.dropped_send_fail);
  3057. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3058. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3059. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3060. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3061. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3062. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3063. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3064. pdev->stats.tx_i.dropped.dma_error +
  3065. pdev->stats.tx_i.dropped.ring_full +
  3066. pdev->stats.tx_i.dropped.enqueue_fail +
  3067. pdev->stats.tx_i.dropped.desc_na +
  3068. pdev->stats.tx_i.dropped.res_full;
  3069. pdev->stats.tx.last_ack_rssi =
  3070. vdev->stats.tx.last_ack_rssi;
  3071. pdev->stats.tx_i.tso.num_seg =
  3072. vdev->stats.tx_i.tso.num_seg;
  3073. }
  3074. }
  3075. /**
  3076. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3077. * @pdev: DP_PDEV Handle
  3078. *
  3079. * Return:void
  3080. */
  3081. static inline void
  3082. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3083. {
  3084. DP_TRACE_STATS(FATAL, "WLAN Tx Stats:\n");
  3085. DP_TRACE_STATS(FATAL, "Received From Stack:\n");
  3086. DP_TRACE_STATS(FATAL, "Packets = %d",
  3087. pdev->stats.tx_i.rcvd.num);
  3088. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  3089. pdev->stats.tx_i.rcvd.bytes);
  3090. DP_TRACE_STATS(FATAL, "Processed:\n");
  3091. DP_TRACE_STATS(FATAL, "Packets = %d",
  3092. pdev->stats.tx_i.processed.num);
  3093. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  3094. pdev->stats.tx_i.processed.bytes);
  3095. DP_TRACE_STATS(FATAL, "Completions:\n");
  3096. DP_TRACE_STATS(FATAL, "Packets = %d",
  3097. pdev->stats.tx.comp_pkt.num);
  3098. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  3099. pdev->stats.tx.comp_pkt.bytes);
  3100. DP_TRACE_STATS(FATAL, "Dropped:\n");
  3101. DP_TRACE_STATS(FATAL, "Packets = %d",
  3102. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3103. DP_TRACE_STATS(FATAL, "Dma_map_error = %d",
  3104. pdev->stats.tx_i.dropped.dma_error);
  3105. DP_TRACE_STATS(FATAL, "Ring Full = %d",
  3106. pdev->stats.tx_i.dropped.ring_full);
  3107. DP_TRACE_STATS(FATAL, "Descriptor Not available = %d",
  3108. pdev->stats.tx_i.dropped.desc_na);
  3109. DP_TRACE_STATS(FATAL, "HW enqueue failed= %d",
  3110. pdev->stats.tx_i.dropped.enqueue_fail);
  3111. DP_TRACE_STATS(FATAL, "Resources Full = %d",
  3112. pdev->stats.tx_i.dropped.res_full);
  3113. DP_TRACE_STATS(FATAL, "Fw Discard = %d",
  3114. pdev->stats.tx.dropped.fw_discard);
  3115. DP_TRACE_STATS(FATAL, "Fw Discard Retired = %d",
  3116. pdev->stats.tx.dropped.fw_discard_retired);
  3117. DP_TRACE_STATS(FATAL, "Firmware Discard Untransmitted = %d",
  3118. pdev->stats.tx.dropped.fw_discard_untransmitted);
  3119. DP_TRACE_STATS(FATAL, "Mpdu Age Out = %d",
  3120. pdev->stats.tx.dropped.mpdu_age_out);
  3121. DP_TRACE_STATS(FATAL, "Firmware Discard Reason1 = %d",
  3122. pdev->stats.tx.dropped.fw_discard_reason1);
  3123. DP_TRACE_STATS(FATAL, "Firmware Discard Reason2 = %d",
  3124. pdev->stats.tx.dropped.fw_discard_reason2);
  3125. DP_TRACE_STATS(FATAL, "Firmware Discard Reason3 = %d\n",
  3126. pdev->stats.tx.dropped.fw_discard_reason3);
  3127. DP_TRACE_STATS(FATAL, "Scatter Gather:\n");
  3128. DP_TRACE_STATS(FATAL, "Packets = %d",
  3129. pdev->stats.tx_i.sg.sg_pkt.num);
  3130. DP_TRACE_STATS(FATAL, "Bytes = %d",
  3131. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3132. DP_TRACE_STATS(FATAL, "Dropped By Host = %d",
  3133. pdev->stats.tx_i.sg.dropped_host);
  3134. DP_TRACE_STATS(FATAL, "Dropped By Target = %d\n",
  3135. pdev->stats.tx_i.sg.dropped_target);
  3136. DP_TRACE_STATS(FATAL, "Tso:\n");
  3137. DP_TRACE_STATS(FATAL, "Number of Segments = %d",
  3138. pdev->stats.tx_i.tso.num_seg);
  3139. DP_TRACE_STATS(FATAL, "Packets = %d",
  3140. pdev->stats.tx_i.tso.tso_pkt.num);
  3141. DP_TRACE_STATS(FATAL, "Bytes = %d",
  3142. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3143. DP_TRACE_STATS(FATAL, "Dropped By Host = %d\n",
  3144. pdev->stats.tx_i.tso.dropped_host);
  3145. DP_TRACE_STATS(FATAL, "Mcast Enhancement:\n");
  3146. DP_TRACE_STATS(FATAL, "Packets = %d",
  3147. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3148. DP_TRACE_STATS(FATAL, "Bytes = %d",
  3149. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3150. DP_TRACE_STATS(FATAL, "Dropped: Map Errors = %d",
  3151. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3152. DP_TRACE_STATS(FATAL, "Dropped: Self Mac = %d",
  3153. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3154. DP_TRACE_STATS(FATAL, "Dropped: Send Fail = %d",
  3155. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3156. DP_TRACE_STATS(FATAL, "Unicast sent = %d\n",
  3157. pdev->stats.tx_i.mcast_en.ucast);
  3158. DP_TRACE_STATS(FATAL, "Raw:\n");
  3159. DP_TRACE_STATS(FATAL, "Packets = %d",
  3160. pdev->stats.tx_i.raw.raw_pkt.num);
  3161. DP_TRACE_STATS(FATAL, "Bytes = %d",
  3162. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3163. DP_TRACE_STATS(FATAL, "DMA map error = %d\n",
  3164. pdev->stats.tx_i.raw.dma_map_error);
  3165. DP_TRACE_STATS(FATAL, "Reinjected:\n");
  3166. DP_TRACE_STATS(FATAL, "Packets = %d",
  3167. pdev->stats.tx_i.reinject_pkts.num);
  3168. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  3169. pdev->stats.tx_i.reinject_pkts.bytes);
  3170. DP_TRACE_STATS(FATAL, "Inspected:\n");
  3171. DP_TRACE_STATS(FATAL, "Packets = %d",
  3172. pdev->stats.tx_i.inspect_pkts.num);
  3173. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  3174. pdev->stats.tx_i.inspect_pkts.bytes);
  3175. }
  3176. /**
  3177. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3178. * @pdev: DP_PDEV Handle
  3179. *
  3180. * Return: void
  3181. */
  3182. static inline void
  3183. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3184. {
  3185. DP_TRACE_STATS(FATAL, "WLAN Rx Stats:\n");
  3186. DP_TRACE_STATS(FATAL, "Received From HW (Per Rx Ring):\n");
  3187. DP_TRACE_STATS(FATAL, "Packets = %d %d %d %d",
  3188. pdev->stats.rx.rcvd_reo[0].num,
  3189. pdev->stats.rx.rcvd_reo[1].num,
  3190. pdev->stats.rx.rcvd_reo[2].num,
  3191. pdev->stats.rx.rcvd_reo[3].num);
  3192. DP_TRACE_STATS(FATAL, "Bytes = %d %d %d %d\n",
  3193. pdev->stats.rx.rcvd_reo[0].bytes,
  3194. pdev->stats.rx.rcvd_reo[1].bytes,
  3195. pdev->stats.rx.rcvd_reo[2].bytes,
  3196. pdev->stats.rx.rcvd_reo[3].bytes);
  3197. DP_TRACE_STATS(FATAL, "Replenished:\n");
  3198. DP_TRACE_STATS(FATAL, "Packets = %d",
  3199. pdev->stats.replenish.pkts.num);
  3200. DP_TRACE_STATS(FATAL, "Bytes = %d",
  3201. pdev->stats.replenish.pkts.bytes);
  3202. DP_TRACE_STATS(FATAL, "Buffers Added To Freelist = %d\n",
  3203. pdev->stats.buf_freelist);
  3204. DP_TRACE_STATS(FATAL, "Dropped:\n");
  3205. DP_TRACE_STATS(FATAL, "Total Packets With Msdu Not Done = %d\n",
  3206. pdev->stats.dropped.msdu_not_done);
  3207. DP_TRACE_STATS(FATAL, "Sent To Stack:\n");
  3208. DP_TRACE_STATS(FATAL, "Packets = %d",
  3209. pdev->stats.rx.to_stack.num);
  3210. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  3211. pdev->stats.rx.to_stack.bytes);
  3212. DP_TRACE_STATS(FATAL, "Multicast/Broadcast:\n");
  3213. DP_TRACE_STATS(FATAL, "Packets = %d",
  3214. pdev->stats.rx.multicast.num);
  3215. DP_TRACE_STATS(FATAL, "Bytes = %d\n",
  3216. pdev->stats.rx.multicast.bytes);
  3217. DP_TRACE_STATS(FATAL, "Errors:\n");
  3218. DP_TRACE_STATS(FATAL, "Rxdma Ring Un-inititalized = %d",
  3219. pdev->stats.replenish.rxdma_err);
  3220. DP_TRACE_STATS(FATAL, "Desc Alloc Failed: = %d",
  3221. pdev->stats.err.desc_alloc_fail);
  3222. }
  3223. /**
  3224. * dp_print_soc_tx_stats(): Print SOC level stats
  3225. * @soc DP_SOC Handle
  3226. *
  3227. * Return: void
  3228. */
  3229. static inline void
  3230. dp_print_soc_tx_stats(struct dp_soc *soc)
  3231. {
  3232. DP_TRACE_STATS(FATAL, "SOC Tx Stats:\n");
  3233. DP_TRACE_STATS(FATAL, "Tx Descriptors In Use = %d",
  3234. soc->stats.tx.desc_in_use);
  3235. DP_TRACE_STATS(FATAL, "Invalid peer:\n");
  3236. DP_TRACE_STATS(FATAL, "Packets = %d",
  3237. soc->stats.tx.tx_invalid_peer.num);
  3238. DP_TRACE_STATS(FATAL, "Bytes = %d",
  3239. soc->stats.tx.tx_invalid_peer.bytes);
  3240. DP_TRACE_STATS(FATAL, "Packets dropped due to TCL ring full = %d %d %d",
  3241. soc->stats.tx.tcl_ring_full[0],
  3242. soc->stats.tx.tcl_ring_full[1],
  3243. soc->stats.tx.tcl_ring_full[2]);
  3244. }
  3245. /**
  3246. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3247. * @soc: DP_SOC Handle
  3248. *
  3249. * Return:void
  3250. */
  3251. static inline void
  3252. dp_print_soc_rx_stats(struct dp_soc *soc)
  3253. {
  3254. uint32_t i;
  3255. char reo_error[DP_REO_ERR_LENGTH];
  3256. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3257. uint8_t index = 0;
  3258. DP_TRACE_STATS(FATAL, "SOC Rx Stats:\n");
  3259. DP_TRACE_STATS(FATAL, "Errors:\n");
  3260. DP_TRACE_STATS(FATAL, "Rx Decrypt Errors = %d",
  3261. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3262. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3263. DP_TRACE_STATS(FATAL, "Invalid RBM = %d",
  3264. soc->stats.rx.err.invalid_rbm);
  3265. DP_TRACE_STATS(FATAL, "Invalid Vdev = %d",
  3266. soc->stats.rx.err.invalid_vdev);
  3267. DP_TRACE_STATS(FATAL, "Invalid Pdev = %d",
  3268. soc->stats.rx.err.invalid_pdev);
  3269. DP_TRACE_STATS(FATAL, "Invalid Peer = %d",
  3270. soc->stats.rx.err.rx_invalid_peer.num);
  3271. DP_TRACE_STATS(FATAL, "HAL Ring Access Fail = %d",
  3272. soc->stats.rx.err.hal_ring_access_fail);
  3273. for (i = 0; i < MAX_RXDMA_ERRORS; i++) {
  3274. index += qdf_snprint(&rxdma_error[index],
  3275. DP_RXDMA_ERR_LENGTH - index,
  3276. " %d", soc->stats.rx.err.rxdma_error[i]);
  3277. }
  3278. DP_TRACE_STATS(FATAL, "RXDMA Error (0-31):%s",
  3279. rxdma_error);
  3280. index = 0;
  3281. for (i = 0; i < REO_ERROR_TYPE_MAX; i++) {
  3282. index += qdf_snprint(&reo_error[index],
  3283. DP_REO_ERR_LENGTH - index,
  3284. " %d", soc->stats.rx.err.reo_error[i]);
  3285. }
  3286. DP_TRACE_STATS(FATAL, "REO Error(0-14):%s",
  3287. reo_error);
  3288. }
  3289. /**
  3290. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3291. * @vdev: DP_VDEV handle
  3292. *
  3293. * Return:void
  3294. */
  3295. static inline void
  3296. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3297. {
  3298. struct dp_peer *peer = NULL;
  3299. DP_STATS_CLR(vdev->pdev);
  3300. DP_STATS_CLR(vdev->pdev->soc);
  3301. DP_STATS_CLR(vdev);
  3302. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3303. if (!peer)
  3304. return;
  3305. DP_STATS_CLR(peer);
  3306. }
  3307. }
  3308. /**
  3309. * dp_print_rx_rates(): Print Rx rate stats
  3310. * @vdev: DP_VDEV handle
  3311. *
  3312. * Return:void
  3313. */
  3314. static inline void
  3315. dp_print_rx_rates(struct dp_vdev *vdev)
  3316. {
  3317. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3318. uint8_t i, pkt_type;
  3319. uint8_t index = 0;
  3320. char rx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  3321. char nss[DP_NSS_LENGTH];
  3322. DP_TRACE_STATS(FATAL, "Rx Rate Info:\n");
  3323. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3324. index = 0;
  3325. for (i = 0; i < MAX_MCS; i++) {
  3326. index += qdf_snprint(&rx_mcs[pkt_type][index],
  3327. DP_MCS_LENGTH - index,
  3328. " %d ",
  3329. pdev->stats.rx.pkt_type[pkt_type].
  3330. mcs_count[i]);
  3331. }
  3332. }
  3333. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  3334. rx_mcs[0]);
  3335. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  3336. pdev->stats.rx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  3337. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  3338. rx_mcs[1]);
  3339. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  3340. pdev->stats.rx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  3341. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  3342. rx_mcs[2]);
  3343. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  3344. pdev->stats.rx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  3345. DP_TRACE_STATS(FATAL, "Type 11AC MCS(0-9) = %s",
  3346. rx_mcs[3]);
  3347. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  3348. pdev->stats.rx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  3349. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  3350. rx_mcs[4]);
  3351. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  3352. pdev->stats.rx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  3353. index = 0;
  3354. for (i = 0; i < SS_COUNT; i++) {
  3355. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3356. " %d", pdev->stats.rx.nss[i]);
  3357. }
  3358. DP_TRACE_STATS(FATAL, "NSS(0-7) = %s",
  3359. nss);
  3360. DP_TRACE_STATS(FATAL, "SGI ="
  3361. " 0.8us %d,"
  3362. " 0.4us %d,"
  3363. " 1.6us %d,"
  3364. " 3.2us %d,",
  3365. pdev->stats.rx.sgi_count[0],
  3366. pdev->stats.rx.sgi_count[1],
  3367. pdev->stats.rx.sgi_count[2],
  3368. pdev->stats.rx.sgi_count[3]);
  3369. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3370. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3371. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3372. DP_TRACE_STATS(FATAL, "Reception Type ="
  3373. " SU: %d,"
  3374. " MU_MIMO:%d,"
  3375. " MU_OFDMA:%d,"
  3376. " MU_OFDMA_MIMO:%d\n",
  3377. pdev->stats.rx.reception_type[0],
  3378. pdev->stats.rx.reception_type[1],
  3379. pdev->stats.rx.reception_type[2],
  3380. pdev->stats.rx.reception_type[3]);
  3381. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  3382. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Ampdus = %d",
  3383. pdev->stats.rx.ampdu_cnt);
  3384. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Mpdu Level Aggregation : %d",
  3385. pdev->stats.rx.non_ampdu_cnt);
  3386. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu: %d",
  3387. pdev->stats.rx.amsdu_cnt);
  3388. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation: %d",
  3389. pdev->stats.rx.non_amsdu_cnt);
  3390. }
  3391. /**
  3392. * dp_print_tx_rates(): Print tx rates
  3393. * @vdev: DP_VDEV handle
  3394. *
  3395. * Return:void
  3396. */
  3397. static inline void
  3398. dp_print_tx_rates(struct dp_vdev *vdev)
  3399. {
  3400. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3401. uint8_t i, pkt_type;
  3402. char mcs[DOT11_MAX][DP_MCS_LENGTH];
  3403. uint32_t index;
  3404. DP_TRACE_STATS(FATAL, "Tx Rate Info:\n");
  3405. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3406. index = 0;
  3407. for (i = 0; i < MAX_MCS; i++) {
  3408. index += qdf_snprint(&mcs[pkt_type][index],
  3409. DP_MCS_LENGTH - index,
  3410. " %d ",
  3411. pdev->stats.tx.pkt_type[pkt_type].
  3412. mcs_count[i]);
  3413. }
  3414. }
  3415. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  3416. mcs[0]);
  3417. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  3418. pdev->stats.tx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  3419. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  3420. mcs[1]);
  3421. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  3422. pdev->stats.tx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  3423. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  3424. mcs[2]);
  3425. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  3426. pdev->stats.tx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  3427. DP_TRACE_STATS(FATAL, "Type 11AC MCS(0-9) = %s",
  3428. mcs[3]);
  3429. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  3430. pdev->stats.tx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  3431. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  3432. mcs[4]);
  3433. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  3434. pdev->stats.tx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  3435. DP_TRACE_STATS(FATAL, "SGI ="
  3436. " 0.8us %d"
  3437. " 0.4us %d"
  3438. " 1.6us %d"
  3439. " 3.2us %d",
  3440. pdev->stats.tx.sgi_count[0],
  3441. pdev->stats.tx.sgi_count[1],
  3442. pdev->stats.tx.sgi_count[2],
  3443. pdev->stats.tx.sgi_count[3]);
  3444. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3445. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3446. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3447. DP_TRACE_STATS(FATAL, "OFDMA = %d", pdev->stats.tx.ofdma);
  3448. DP_TRACE_STATS(FATAL, "STBC = %d", pdev->stats.tx.stbc);
  3449. DP_TRACE_STATS(FATAL, "LDPC = %d", pdev->stats.tx.ldpc);
  3450. DP_TRACE_STATS(FATAL, "Retries = %d", pdev->stats.tx.retries);
  3451. DP_TRACE_STATS(FATAL, "Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3452. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  3453. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  3454. pdev->stats.tx.amsdu_cnt);
  3455. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d",
  3456. pdev->stats.tx.non_amsdu_cnt);
  3457. }
  3458. /**
  3459. * dp_print_peer_stats():print peer stats
  3460. * @peer: DP_PEER handle
  3461. *
  3462. * return void
  3463. */
  3464. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3465. {
  3466. uint8_t i, pkt_type;
  3467. char tx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  3468. char rx_mcs[DOT11_MAX][DP_MCS_LENGTH];
  3469. uint32_t index;
  3470. char nss[DP_NSS_LENGTH];
  3471. DP_TRACE_STATS(FATAL, "Node Tx Stats:\n");
  3472. DP_TRACE_STATS(FATAL, "Total Packet Completions = %d",
  3473. peer->stats.tx.comp_pkt.num);
  3474. DP_TRACE_STATS(FATAL, "Total Bytes Completions = %d",
  3475. peer->stats.tx.comp_pkt.bytes);
  3476. DP_TRACE_STATS(FATAL, "Success Packets = %d",
  3477. peer->stats.tx.tx_success.num);
  3478. DP_TRACE_STATS(FATAL, "Success Bytes = %d",
  3479. peer->stats.tx.tx_success.bytes);
  3480. DP_TRACE_STATS(FATAL, "Packets Failed = %d",
  3481. peer->stats.tx.tx_failed);
  3482. DP_TRACE_STATS(FATAL, "Packets In OFDMA = %d",
  3483. peer->stats.tx.ofdma);
  3484. DP_TRACE_STATS(FATAL, "Packets In STBC = %d",
  3485. peer->stats.tx.stbc);
  3486. DP_TRACE_STATS(FATAL, "Packets In LDPC = %d",
  3487. peer->stats.tx.ldpc);
  3488. DP_TRACE_STATS(FATAL, "Packet Retries = %d",
  3489. peer->stats.tx.retries);
  3490. DP_TRACE_STATS(FATAL, "Msdu's Not Part of Ampdu = %d",
  3491. peer->stats.tx.non_amsdu_cnt);
  3492. DP_TRACE_STATS(FATAL, "Mpdu's Part of Ampdu = %d",
  3493. peer->stats.tx.amsdu_cnt);
  3494. DP_TRACE_STATS(FATAL, "Last Packet RSSI = %d",
  3495. peer->stats.tx.last_ack_rssi);
  3496. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard = %d",
  3497. peer->stats.tx.dropped.fw_discard);
  3498. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard Retired = %d",
  3499. peer->stats.tx.dropped.fw_discard_retired);
  3500. DP_TRACE_STATS(FATAL, "Dropped At FW: FW Discard Untransmitted = %d",
  3501. peer->stats.tx.dropped.fw_discard_untransmitted);
  3502. DP_TRACE_STATS(FATAL, "Dropped : Mpdu Age Out = %d",
  3503. peer->stats.tx.dropped.mpdu_age_out);
  3504. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason1 = %d",
  3505. peer->stats.tx.dropped.fw_discard_reason1);
  3506. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason2 = %d",
  3507. peer->stats.tx.dropped.fw_discard_reason2);
  3508. DP_TRACE_STATS(FATAL, "Dropped : FW Discard Reason3 = %d",
  3509. peer->stats.tx.dropped.fw_discard_reason3);
  3510. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3511. index = 0;
  3512. for (i = 0; i < MAX_MCS; i++) {
  3513. index += qdf_snprint(&tx_mcs[pkt_type][index],
  3514. DP_MCS_LENGTH - index,
  3515. " %d ",
  3516. peer->stats.tx.pkt_type[pkt_type].
  3517. mcs_count[i]);
  3518. }
  3519. }
  3520. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  3521. tx_mcs[0]);
  3522. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  3523. peer->stats.tx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  3524. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  3525. tx_mcs[1]);
  3526. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  3527. peer->stats.tx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  3528. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  3529. tx_mcs[2]);
  3530. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  3531. peer->stats.tx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  3532. DP_TRACE_STATS(FATAL, "11AC MCS(0-9) = %s",
  3533. tx_mcs[3]);
  3534. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  3535. peer->stats.tx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  3536. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  3537. tx_mcs[4]);
  3538. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  3539. peer->stats.tx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  3540. DP_TRACE_STATS(FATAL, "SGI = "
  3541. " 0.8us %d"
  3542. " 0.4us %d"
  3543. " 1.6us %d"
  3544. " 3.2us %d",
  3545. peer->stats.tx.sgi_count[0],
  3546. peer->stats.tx.sgi_count[1],
  3547. peer->stats.tx.sgi_count[2],
  3548. peer->stats.tx.sgi_count[3]);
  3549. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3550. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3551. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3552. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  3553. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  3554. peer->stats.tx.amsdu_cnt);
  3555. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3556. peer->stats.tx.non_amsdu_cnt);
  3557. DP_TRACE_STATS(FATAL, "Node Rx Stats:\n");
  3558. DP_TRACE_STATS(FATAL, "Packets Sent To Stack = %d",
  3559. peer->stats.rx.to_stack.num);
  3560. DP_TRACE_STATS(FATAL, "Bytes Sent To Stack = %d",
  3561. peer->stats.rx.to_stack.bytes);
  3562. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3563. DP_TRACE_STATS(FATAL, "Packets Received = %d",
  3564. peer->stats.rx.rcvd_reo[i].num);
  3565. DP_TRACE_STATS(FATAL, "Bytes Received = %d",
  3566. peer->stats.rx.rcvd_reo[i].bytes);
  3567. }
  3568. DP_TRACE_STATS(FATAL, "Multicast Packets Received = %d",
  3569. peer->stats.rx.multicast.num);
  3570. DP_TRACE_STATS(FATAL, "Multicast Bytes Received = %d",
  3571. peer->stats.rx.multicast.bytes);
  3572. DP_TRACE_STATS(FATAL, "WDS Packets Received = %d",
  3573. peer->stats.rx.wds.num);
  3574. DP_TRACE_STATS(FATAL, "WDS Bytes Received = %d",
  3575. peer->stats.rx.wds.bytes);
  3576. DP_TRACE_STATS(FATAL, "Intra BSS Packets Received = %d",
  3577. peer->stats.rx.intra_bss.pkts.num);
  3578. DP_TRACE_STATS(FATAL, "Intra BSS Bytes Received = %d",
  3579. peer->stats.rx.intra_bss.pkts.bytes);
  3580. DP_TRACE_STATS(FATAL, "Raw Packets Received = %d",
  3581. peer->stats.rx.raw.num);
  3582. DP_TRACE_STATS(FATAL, "Raw Bytes Received = %d",
  3583. peer->stats.rx.raw.bytes);
  3584. DP_TRACE_STATS(FATAL, "Errors: MIC Errors = %d",
  3585. peer->stats.rx.err.mic_err);
  3586. DP_TRACE_STATS(FATAL, "Erros: Decryption Errors = %d",
  3587. peer->stats.rx.err.decrypt_err);
  3588. DP_TRACE_STATS(FATAL, "Msdu's Received As Part of Ampdu = %d",
  3589. peer->stats.rx.non_ampdu_cnt);
  3590. DP_TRACE_STATS(FATAL, "Msdu's Recived As Ampdu = %d",
  3591. peer->stats.rx.ampdu_cnt);
  3592. DP_TRACE_STATS(FATAL, "Msdu's Received Not Part of Amsdu's = %d",
  3593. peer->stats.rx.non_amsdu_cnt);
  3594. DP_TRACE_STATS(FATAL, "MSDUs Received As Part of Amsdu = %d",
  3595. peer->stats.rx.amsdu_cnt);
  3596. DP_TRACE_STATS(FATAL, "SGI ="
  3597. " 0.8us %d"
  3598. " 0.4us %d"
  3599. " 1.6us %d"
  3600. " 3.2us %d",
  3601. peer->stats.rx.sgi_count[0],
  3602. peer->stats.rx.sgi_count[1],
  3603. peer->stats.rx.sgi_count[2],
  3604. peer->stats.rx.sgi_count[3]);
  3605. DP_TRACE_STATS(FATAL, "BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3606. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3607. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3608. DP_TRACE_STATS(FATAL, "Reception Type ="
  3609. " SU %d,"
  3610. " MU_MIMO %d,"
  3611. " MU_OFDMA %d,"
  3612. " MU_OFDMA_MIMO %d",
  3613. peer->stats.rx.reception_type[0],
  3614. peer->stats.rx.reception_type[1],
  3615. peer->stats.rx.reception_type[2],
  3616. peer->stats.rx.reception_type[3]);
  3617. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3618. index = 0;
  3619. for (i = 0; i < MAX_MCS; i++) {
  3620. index += qdf_snprint(&rx_mcs[pkt_type][index],
  3621. DP_MCS_LENGTH - index,
  3622. " %d ",
  3623. peer->stats.rx.pkt_type[pkt_type].
  3624. mcs_count[i]);
  3625. }
  3626. }
  3627. DP_TRACE_STATS(FATAL, "11A MCS(0-7) = %s",
  3628. rx_mcs[0]);
  3629. DP_TRACE_STATS(FATAL, "11A MCS Invalid = %d",
  3630. peer->stats.rx.pkt_type[DOT11_A].mcs_count[MAX_MCS]);
  3631. DP_TRACE_STATS(FATAL, "11B MCS(0-6) = %s",
  3632. rx_mcs[1]);
  3633. DP_TRACE_STATS(FATAL, "11B MCS Invalid = %d",
  3634. peer->stats.rx.pkt_type[DOT11_B].mcs_count[MAX_MCS]);
  3635. DP_TRACE_STATS(FATAL, "11N MCS(0-7) = %s",
  3636. rx_mcs[2]);
  3637. DP_TRACE_STATS(FATAL, "11N MCS Invalid = %d",
  3638. peer->stats.rx.pkt_type[DOT11_N].mcs_count[MAX_MCS]);
  3639. DP_TRACE_STATS(FATAL, "11AC MCS(0-9) = %s",
  3640. rx_mcs[3]);
  3641. DP_TRACE_STATS(FATAL, "11AC MCS Invalid = %d",
  3642. peer->stats.rx.pkt_type[DOT11_AC].mcs_count[MAX_MCS]);
  3643. DP_TRACE_STATS(FATAL, "11AX MCS(0-11) = %s",
  3644. rx_mcs[4]);
  3645. DP_TRACE_STATS(FATAL, "11AX MCS Invalid = %d",
  3646. peer->stats.rx.pkt_type[DOT11_AX].mcs_count[MAX_MCS]);
  3647. index = 0;
  3648. for (i = 0; i < SS_COUNT; i++) {
  3649. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3650. " %d", peer->stats.rx.nss[i]);
  3651. }
  3652. DP_TRACE_STATS(FATAL, "NSS(0-7) = %s\n",
  3653. nss);
  3654. DP_TRACE_STATS(FATAL, "Aggregation:\n");
  3655. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Ampdu = %d",
  3656. peer->stats.rx.ampdu_cnt);
  3657. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Mpdu Level Aggregation = %d",
  3658. peer->stats.rx.non_ampdu_cnt);
  3659. DP_TRACE_STATS(FATAL, "Number of Msdu's Part of Amsdu = %d",
  3660. peer->stats.rx.amsdu_cnt);
  3661. DP_TRACE_STATS(FATAL, "Number of Msdu's With No Msdu Level Aggregation = %d",
  3662. peer->stats.rx.non_amsdu_cnt);
  3663. }
  3664. /**
  3665. * dp_print_host_stats()- Function to print the stats aggregated at host
  3666. * @vdev_handle: DP_VDEV handle
  3667. * @type: host stats type
  3668. *
  3669. * Available Stat types
  3670. * TXRX_CLEAR_STATS : Clear the stats
  3671. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3672. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3673. * TXRX_TX_HOST_STATS: Print Tx Stats
  3674. * TXRX_RX_HOST_STATS: Print Rx Stats
  3675. *
  3676. * Return: 0 on success, print error message in case of failure
  3677. */
  3678. static int
  3679. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3680. {
  3681. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3682. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3683. dp_aggregate_pdev_stats(pdev);
  3684. switch (type) {
  3685. case TXRX_CLEAR_STATS:
  3686. dp_txrx_host_stats_clr(vdev);
  3687. break;
  3688. case TXRX_RX_RATE_STATS:
  3689. dp_print_rx_rates(vdev);
  3690. break;
  3691. case TXRX_TX_RATE_STATS:
  3692. dp_print_tx_rates(vdev);
  3693. break;
  3694. case TXRX_TX_HOST_STATS:
  3695. dp_print_pdev_tx_stats(pdev);
  3696. dp_print_soc_tx_stats(pdev->soc);
  3697. break;
  3698. case TXRX_RX_HOST_STATS:
  3699. dp_print_pdev_rx_stats(pdev);
  3700. dp_print_soc_rx_stats(pdev->soc);
  3701. break;
  3702. default:
  3703. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3704. break;
  3705. }
  3706. return 0;
  3707. }
  3708. /*
  3709. * dp_get_host_peer_stats()- function to print peer stats
  3710. * @pdev_handle: DP_PDEV handle
  3711. * @mac_addr: mac address of the peer
  3712. *
  3713. * Return: void
  3714. */
  3715. static void
  3716. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3717. {
  3718. struct dp_peer *peer;
  3719. uint8_t local_id;
  3720. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3721. &local_id);
  3722. if (!peer) {
  3723. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3724. "%s: Invalid peer\n", __func__);
  3725. return;
  3726. }
  3727. dp_print_peer_stats(peer);
  3728. dp_peer_rxtid_stats(peer);
  3729. return;
  3730. }
  3731. /*
  3732. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3733. * @pdev_handle: DP_PDEV handle
  3734. *
  3735. * Return: void
  3736. */
  3737. static void
  3738. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3739. {
  3740. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3741. pdev->enhanced_stats_en = 1;
  3742. }
  3743. /*
  3744. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3745. * @pdev_handle: DP_PDEV handle
  3746. *
  3747. * Return: void
  3748. */
  3749. static void
  3750. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3751. {
  3752. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3753. pdev->enhanced_stats_en = 0;
  3754. }
  3755. /*
  3756. * dp_get_fw_peer_stats()- function to print peer stats
  3757. * @pdev_handle: DP_PDEV handle
  3758. * @mac_addr: mac address of the peer
  3759. * @cap: Type of htt stats requested
  3760. *
  3761. * Currently Supporting only MAC ID based requests Only
  3762. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3763. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3764. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3765. *
  3766. * Return: void
  3767. */
  3768. static void
  3769. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3770. uint32_t cap)
  3771. {
  3772. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3773. uint32_t config_param0 = 0;
  3774. uint32_t config_param1 = 0;
  3775. uint32_t config_param2 = 0;
  3776. uint32_t config_param3 = 0;
  3777. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3778. config_param0 |= (1 << (cap + 1));
  3779. config_param1 = 0x8f;
  3780. config_param2 |= (mac_addr[0] & 0x000000ff);
  3781. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3782. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3783. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3784. config_param3 |= (mac_addr[4] & 0x000000ff);
  3785. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3786. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3787. config_param0, config_param1, config_param2,
  3788. config_param3);
  3789. }
  3790. /*
  3791. * dp_set_vdev_param: function to set parameters in vdev
  3792. * @param: parameter type to be set
  3793. * @val: value of parameter to be set
  3794. *
  3795. * return: void
  3796. */
  3797. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  3798. enum cdp_vdev_param_type param, uint32_t val)
  3799. {
  3800. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3801. switch (param) {
  3802. case CDP_ENABLE_WDS:
  3803. vdev->wds_enabled = val;
  3804. break;
  3805. case CDP_ENABLE_NAWDS:
  3806. vdev->nawds_enabled = val;
  3807. break;
  3808. case CDP_ENABLE_MCAST_EN:
  3809. vdev->mcast_enhancement_en = val;
  3810. break;
  3811. case CDP_ENABLE_PROXYSTA:
  3812. vdev->proxysta_vdev = val;
  3813. break;
  3814. case CDP_UPDATE_TDLS_FLAGS:
  3815. vdev->tdls_link_connected = val;
  3816. break;
  3817. case CDP_CFG_WDS_AGING_TIMER:
  3818. if (val == 0)
  3819. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  3820. else if (val != vdev->wds_aging_timer_val)
  3821. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  3822. vdev->wds_aging_timer_val = val;
  3823. break;
  3824. default:
  3825. break;
  3826. }
  3827. dp_tx_vdev_update_search_flags(vdev);
  3828. }
  3829. /**
  3830. * dp_peer_set_nawds: set nawds bit in peer
  3831. * @peer_handle: pointer to peer
  3832. * @value: enable/disable nawds
  3833. *
  3834. * return: void
  3835. */
  3836. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  3837. {
  3838. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3839. peer->nawds_enabled = value;
  3840. }
  3841. /*
  3842. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  3843. * @vdev_handle: DP_VDEV handle
  3844. * @map_id:ID of map that needs to be updated
  3845. *
  3846. * Return: void
  3847. */
  3848. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  3849. uint8_t map_id)
  3850. {
  3851. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3852. vdev->dscp_tid_map_id = map_id;
  3853. return;
  3854. }
  3855. /**
  3856. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  3857. * @pdev: DP_PDEV handle
  3858. * @map_id: ID of map that needs to be updated
  3859. * @tos: index value in map
  3860. * @tid: tid value passed by the user
  3861. *
  3862. * Return: void
  3863. */
  3864. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  3865. uint8_t map_id, uint8_t tos, uint8_t tid)
  3866. {
  3867. uint8_t dscp;
  3868. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  3869. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  3870. pdev->dscp_tid_map[map_id][dscp] = tid;
  3871. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  3872. map_id, dscp);
  3873. return;
  3874. }
  3875. /**
  3876. * dp_fw_stats_process(): Process TxRX FW stats request
  3877. * @vdev_handle: DP VDEV handle
  3878. * @val: value passed by user
  3879. *
  3880. * return: int
  3881. */
  3882. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  3883. {
  3884. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3885. struct dp_pdev *pdev = NULL;
  3886. if (!vdev) {
  3887. DP_TRACE(NONE, "VDEV not found");
  3888. return 1;
  3889. }
  3890. pdev = vdev->pdev;
  3891. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  3892. }
  3893. /*
  3894. * dp_txrx_stats() - function to map to firmware and host stats
  3895. * @vdev: virtual handle
  3896. * @stats: type of statistics requested
  3897. *
  3898. * Return: integer
  3899. */
  3900. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  3901. {
  3902. int host_stats;
  3903. int fw_stats;
  3904. if (stats >= CDP_TXRX_MAX_STATS)
  3905. return 0;
  3906. /*
  3907. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  3908. * has to be updated if new FW HTT stats added
  3909. */
  3910. if (stats > CDP_TXRX_STATS_HTT_MAX)
  3911. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  3912. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  3913. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  3914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3915. "stats: %u fw_stats_type: %d host_stats_type: %d",
  3916. stats, fw_stats, host_stats);
  3917. if (fw_stats != TXRX_FW_STATS_INVALID)
  3918. return dp_fw_stats_process(vdev, fw_stats);
  3919. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  3920. (host_stats <= TXRX_HOST_STATS_MAX))
  3921. return dp_print_host_stats(vdev, host_stats);
  3922. else
  3923. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3924. "Wrong Input for TxRx Stats");
  3925. return 0;
  3926. }
  3927. /*
  3928. * dp_print_napi_stats(): NAPI stats
  3929. * @soc - soc handle
  3930. */
  3931. static void dp_print_napi_stats(struct dp_soc *soc)
  3932. {
  3933. hif_print_napi_stats(soc->hif_handle);
  3934. }
  3935. /*
  3936. * dp_print_per_ring_stats(): Packet count per ring
  3937. * @soc - soc handle
  3938. */
  3939. static void dp_print_per_ring_stats(struct dp_soc *soc)
  3940. {
  3941. uint8_t core, ring;
  3942. uint64_t total_packets;
  3943. DP_TRACE(FATAL, "Reo packets per ring:");
  3944. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  3945. total_packets = 0;
  3946. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  3947. for (core = 0; core < NR_CPUS; core++) {
  3948. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  3949. core, soc->stats.rx.ring_packets[core][ring]);
  3950. total_packets += soc->stats.rx.ring_packets[core][ring];
  3951. }
  3952. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  3953. ring, total_packets);
  3954. }
  3955. }
  3956. /*
  3957. * dp_txrx_path_stats() - Function to display dump stats
  3958. * @soc - soc handle
  3959. *
  3960. * return: none
  3961. */
  3962. static void dp_txrx_path_stats(struct dp_soc *soc)
  3963. {
  3964. uint8_t error_code;
  3965. uint8_t loop_pdev;
  3966. struct dp_pdev *pdev;
  3967. uint8_t i;
  3968. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  3969. pdev = soc->pdev_list[loop_pdev];
  3970. dp_aggregate_pdev_stats(pdev);
  3971. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3972. "Tx path Statistics:");
  3973. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  3974. pdev->stats.tx_i.rcvd.num,
  3975. pdev->stats.tx_i.rcvd.bytes);
  3976. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  3977. pdev->stats.tx_i.processed.num,
  3978. pdev->stats.tx_i.processed.bytes);
  3979. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  3980. pdev->stats.tx.tx_success.num,
  3981. pdev->stats.tx.tx_success.bytes);
  3982. DP_TRACE(FATAL, "Dropped in host:");
  3983. DP_TRACE(FATAL, "Total packets dropped: %u,",
  3984. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3985. DP_TRACE(FATAL, "Descriptor not available: %u",
  3986. pdev->stats.tx_i.dropped.desc_na);
  3987. DP_TRACE(FATAL, "Ring full: %u",
  3988. pdev->stats.tx_i.dropped.ring_full);
  3989. DP_TRACE(FATAL, "Enqueue fail: %u",
  3990. pdev->stats.tx_i.dropped.enqueue_fail);
  3991. DP_TRACE(FATAL, "DMA Error: %u",
  3992. pdev->stats.tx_i.dropped.dma_error);
  3993. DP_TRACE(FATAL, "Dropped in hardware:");
  3994. DP_TRACE(FATAL, "total packets dropped: %u",
  3995. pdev->stats.tx.tx_failed);
  3996. DP_TRACE(FATAL, "mpdu age out: %u",
  3997. pdev->stats.tx.dropped.mpdu_age_out);
  3998. DP_TRACE(FATAL, "firmware discard reason1: %u",
  3999. pdev->stats.tx.dropped.fw_discard_reason1);
  4000. DP_TRACE(FATAL, "firmware discard reason2: %u",
  4001. pdev->stats.tx.dropped.fw_discard_reason2);
  4002. DP_TRACE(FATAL, "firmware discard reason3: %u",
  4003. pdev->stats.tx.dropped.fw_discard_reason3);
  4004. DP_TRACE(FATAL, "peer_invalid: %u",
  4005. pdev->soc->stats.tx.tx_invalid_peer.num);
  4006. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4007. DP_TRACE(FATAL, "Single Packet: %u",
  4008. pdev->stats.tx_comp_histogram.pkts_1);
  4009. DP_TRACE(FATAL, "2-20 Packets: %u",
  4010. pdev->stats.tx_comp_histogram.pkts_2_20);
  4011. DP_TRACE(FATAL, "21-40 Packets: %u",
  4012. pdev->stats.tx_comp_histogram.pkts_21_40);
  4013. DP_TRACE(FATAL, "41-60 Packets: %u",
  4014. pdev->stats.tx_comp_histogram.pkts_41_60);
  4015. DP_TRACE(FATAL, "61-80 Packets: %u",
  4016. pdev->stats.tx_comp_histogram.pkts_61_80);
  4017. DP_TRACE(FATAL, "81-100 Packets: %u",
  4018. pdev->stats.tx_comp_histogram.pkts_81_100);
  4019. DP_TRACE(FATAL, "101-200 Packets: %u",
  4020. pdev->stats.tx_comp_histogram.pkts_101_200);
  4021. DP_TRACE(FATAL, " 201+ Packets: %u",
  4022. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4023. DP_TRACE(FATAL, "Rx path statistics");
  4024. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4025. pdev->stats.rx.to_stack.num,
  4026. pdev->stats.rx.to_stack.bytes);
  4027. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4028. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4029. i, pdev->stats.rx.rcvd_reo[i].num,
  4030. pdev->stats.rx.rcvd_reo[i].bytes);
  4031. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4032. pdev->stats.rx.intra_bss.pkts.num,
  4033. pdev->stats.rx.intra_bss.pkts.bytes);
  4034. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4035. pdev->stats.rx.raw.num,
  4036. pdev->stats.rx.raw.bytes);
  4037. DP_TRACE(FATAL, "dropped: error %u msdus",
  4038. pdev->stats.rx.err.mic_err);
  4039. DP_TRACE(FATAL, "peer invalid %u",
  4040. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4041. DP_TRACE(FATAL, "Reo Statistics");
  4042. DP_TRACE(FATAL, "rbm error: %u msdus",
  4043. pdev->soc->stats.rx.err.invalid_rbm);
  4044. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4045. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4046. DP_TRACE(FATAL, "Reo errors");
  4047. for (error_code = 0; error_code < REO_ERROR_TYPE_MAX;
  4048. error_code++) {
  4049. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4050. error_code,
  4051. pdev->soc->stats.rx.err.reo_error[error_code]);
  4052. }
  4053. for (error_code = 0; error_code < MAX_RXDMA_ERRORS;
  4054. error_code++) {
  4055. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4056. error_code,
  4057. pdev->soc->stats.rx.err
  4058. .rxdma_error[error_code]);
  4059. }
  4060. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4061. DP_TRACE(FATAL, "Single Packet: %u",
  4062. pdev->stats.rx_ind_histogram.pkts_1);
  4063. DP_TRACE(FATAL, "2-20 Packets: %u",
  4064. pdev->stats.rx_ind_histogram.pkts_2_20);
  4065. DP_TRACE(FATAL, "21-40 Packets: %u",
  4066. pdev->stats.rx_ind_histogram.pkts_21_40);
  4067. DP_TRACE(FATAL, "41-60 Packets: %u",
  4068. pdev->stats.rx_ind_histogram.pkts_41_60);
  4069. DP_TRACE(FATAL, "61-80 Packets: %u",
  4070. pdev->stats.rx_ind_histogram.pkts_61_80);
  4071. DP_TRACE(FATAL, "81-100 Packets: %u",
  4072. pdev->stats.rx_ind_histogram.pkts_81_100);
  4073. DP_TRACE(FATAL, "101-200 Packets: %u",
  4074. pdev->stats.rx_ind_histogram.pkts_101_200);
  4075. DP_TRACE(FATAL, " 201+ Packets: %u",
  4076. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4077. }
  4078. }
  4079. /*
  4080. * dp_txrx_dump_stats() - Dump statistics
  4081. * @value - Statistics option
  4082. */
  4083. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4084. {
  4085. struct dp_soc *soc =
  4086. (struct dp_soc *)psoc;
  4087. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4088. if (!soc) {
  4089. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4090. "%s: soc is NULL", __func__);
  4091. return QDF_STATUS_E_INVAL;
  4092. }
  4093. switch (value) {
  4094. case CDP_TXRX_PATH_STATS:
  4095. dp_txrx_path_stats(soc);
  4096. break;
  4097. case CDP_RX_RING_STATS:
  4098. dp_print_per_ring_stats(soc);
  4099. break;
  4100. case CDP_TXRX_TSO_STATS:
  4101. /* TODO: NOT IMPLEMENTED */
  4102. break;
  4103. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4104. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4105. break;
  4106. case CDP_DP_NAPI_STATS:
  4107. dp_print_napi_stats(soc);
  4108. break;
  4109. case CDP_TXRX_DESC_STATS:
  4110. /* TODO: NOT IMPLEMENTED */
  4111. break;
  4112. default:
  4113. status = QDF_STATUS_E_INVAL;
  4114. break;
  4115. }
  4116. return status;
  4117. }
  4118. static struct cdp_wds_ops dp_ops_wds = {
  4119. .vdev_set_wds = dp_vdev_set_wds,
  4120. };
  4121. /*
  4122. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4123. * @soc - datapath soc handle
  4124. * @peer - datapath peer handle
  4125. *
  4126. * Delete the AST entries belonging to a peer
  4127. */
  4128. #ifdef FEATURE_WDS
  4129. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4130. struct dp_peer *peer)
  4131. {
  4132. struct dp_ast_entry *ast_entry;
  4133. qdf_spin_lock_bh(&soc->ast_lock);
  4134. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry) {
  4135. if (ast_entry->next_hop) {
  4136. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4137. soc->osif_soc,
  4138. ast_entry->mac_addr.raw);
  4139. }
  4140. dp_peer_del_ast(soc, ast_entry);
  4141. }
  4142. qdf_spin_unlock_bh(&soc->ast_lock);
  4143. }
  4144. #else
  4145. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4146. struct dp_peer *peer)
  4147. {
  4148. }
  4149. #endif
  4150. #ifdef CONFIG_WIN
  4151. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4152. {
  4153. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4154. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4155. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4156. dp_peer_delete_ast_entries(soc, peer);
  4157. }
  4158. #endif
  4159. static struct cdp_cmn_ops dp_ops_cmn = {
  4160. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4161. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4162. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4163. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4164. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4165. .txrx_peer_create = dp_peer_create_wifi3,
  4166. .txrx_peer_setup = dp_peer_setup_wifi3,
  4167. #ifdef CONFIG_WIN
  4168. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4169. #else
  4170. .txrx_peer_teardown = NULL,
  4171. #endif
  4172. .txrx_peer_delete = dp_peer_delete_wifi3,
  4173. .txrx_vdev_register = dp_vdev_register_wifi3,
  4174. .txrx_soc_detach = dp_soc_detach_wifi3,
  4175. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4176. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4177. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4178. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4179. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4180. .delba_process = dp_delba_process_wifi3,
  4181. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4182. .flush_cache_rx_queue = NULL,
  4183. /* TODO: get API's for dscp-tid need to be added*/
  4184. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4185. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4186. .txrx_stats = dp_txrx_stats,
  4187. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4188. .display_stats = dp_txrx_dump_stats,
  4189. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4190. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4191. #ifdef DP_INTR_POLL_BASED
  4192. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4193. #else
  4194. .txrx_intr_attach = dp_soc_interrupt_attach,
  4195. #endif
  4196. .txrx_intr_detach = dp_soc_interrupt_detach,
  4197. .set_pn_check = dp_set_pn_check_wifi3,
  4198. /* TODO: Add other functions */
  4199. };
  4200. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4201. .txrx_peer_authorize = dp_peer_authorize,
  4202. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4203. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4204. #ifdef MESH_MODE_SUPPORT
  4205. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4206. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4207. #endif
  4208. .txrx_set_vdev_param = dp_set_vdev_param,
  4209. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4210. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4211. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4212. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4213. .txrx_update_filter_neighbour_peers =
  4214. dp_update_filter_neighbour_peers,
  4215. /* TODO: Add other functions */
  4216. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4217. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4218. };
  4219. static struct cdp_me_ops dp_ops_me = {
  4220. #ifdef ATH_SUPPORT_IQUE
  4221. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4222. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4223. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4224. #endif
  4225. };
  4226. static struct cdp_mon_ops dp_ops_mon = {
  4227. .txrx_monitor_set_filter_ucast_data = NULL,
  4228. .txrx_monitor_set_filter_mcast_data = NULL,
  4229. .txrx_monitor_set_filter_non_data = NULL,
  4230. .txrx_monitor_get_filter_ucast_data = NULL,
  4231. .txrx_monitor_get_filter_mcast_data = NULL,
  4232. .txrx_monitor_get_filter_non_data = NULL,
  4233. .txrx_reset_monitor_mode = NULL,
  4234. };
  4235. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4236. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4237. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4238. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4239. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4240. /* TODO */
  4241. };
  4242. static struct cdp_raw_ops dp_ops_raw = {
  4243. /* TODO */
  4244. };
  4245. #ifdef CONFIG_WIN
  4246. static struct cdp_pflow_ops dp_ops_pflow = {
  4247. /* TODO */
  4248. };
  4249. #endif /* CONFIG_WIN */
  4250. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4251. {
  4252. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4253. struct dp_soc *soc = pdev->soc;
  4254. if (soc->intr_mode == DP_INTR_POLL)
  4255. qdf_timer_stop(&soc->int_timer);
  4256. return QDF_STATUS_SUCCESS;
  4257. }
  4258. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4259. {
  4260. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4261. struct dp_soc *soc = pdev->soc;
  4262. if (soc->intr_mode == DP_INTR_POLL)
  4263. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4264. return QDF_STATUS_SUCCESS;
  4265. }
  4266. #ifndef CONFIG_WIN
  4267. static struct cdp_misc_ops dp_ops_misc = {
  4268. .get_opmode = dp_get_opmode,
  4269. #ifdef FEATURE_RUNTIME_PM
  4270. .runtime_suspend = dp_bus_suspend,
  4271. .runtime_resume = dp_bus_resume,
  4272. #endif
  4273. };
  4274. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4275. /* WIFI 3.0 DP implement as required. */
  4276. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4277. .register_pause_cb = dp_txrx_register_pause_cb,
  4278. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4279. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4280. };
  4281. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4282. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4283. };
  4284. #ifdef IPA_OFFLOAD
  4285. static struct cdp_ipa_ops dp_ops_ipa = {
  4286. .ipa_get_resource = dp_ipa_get_resource,
  4287. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4288. .ipa_op_response = dp_ipa_op_response,
  4289. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4290. .ipa_get_stat = dp_ipa_get_stat,
  4291. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4292. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4293. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4294. .ipa_setup = dp_ipa_setup,
  4295. .ipa_cleanup = dp_ipa_cleanup,
  4296. .ipa_setup_iface = dp_ipa_setup_iface,
  4297. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4298. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4299. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4300. .ipa_set_perf_level = dp_ipa_set_perf_level
  4301. };
  4302. #endif
  4303. static struct cdp_bus_ops dp_ops_bus = {
  4304. .bus_suspend = dp_bus_suspend,
  4305. .bus_resume = dp_bus_resume
  4306. };
  4307. static struct cdp_ocb_ops dp_ops_ocb = {
  4308. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4309. };
  4310. static struct cdp_throttle_ops dp_ops_throttle = {
  4311. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4312. };
  4313. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4314. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4315. };
  4316. static struct cdp_cfg_ops dp_ops_cfg = {
  4317. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4318. };
  4319. static struct cdp_peer_ops dp_ops_peer = {
  4320. .register_peer = dp_register_peer,
  4321. .clear_peer = dp_clear_peer,
  4322. .find_peer_by_addr = dp_find_peer_by_addr,
  4323. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4324. .local_peer_id = dp_local_peer_id,
  4325. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4326. .peer_state_update = dp_peer_state_update,
  4327. .get_vdevid = dp_get_vdevid,
  4328. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4329. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4330. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4331. .get_peer_state = dp_get_peer_state,
  4332. .last_assoc_received = dp_get_last_assoc_received,
  4333. .last_disassoc_received = dp_get_last_disassoc_received,
  4334. .last_deauth_received = dp_get_last_deauth_received,
  4335. };
  4336. #endif
  4337. static struct cdp_ops dp_txrx_ops = {
  4338. .cmn_drv_ops = &dp_ops_cmn,
  4339. .ctrl_ops = &dp_ops_ctrl,
  4340. .me_ops = &dp_ops_me,
  4341. .mon_ops = &dp_ops_mon,
  4342. .host_stats_ops = &dp_ops_host_stats,
  4343. .wds_ops = &dp_ops_wds,
  4344. .raw_ops = &dp_ops_raw,
  4345. #ifdef CONFIG_WIN
  4346. .pflow_ops = &dp_ops_pflow,
  4347. #endif /* CONFIG_WIN */
  4348. #ifndef CONFIG_WIN
  4349. .misc_ops = &dp_ops_misc,
  4350. .cfg_ops = &dp_ops_cfg,
  4351. .flowctl_ops = &dp_ops_flowctl,
  4352. .l_flowctl_ops = &dp_ops_l_flowctl,
  4353. #ifdef IPA_OFFLOAD
  4354. .ipa_ops = &dp_ops_ipa,
  4355. #endif
  4356. .bus_ops = &dp_ops_bus,
  4357. .ocb_ops = &dp_ops_ocb,
  4358. .peer_ops = &dp_ops_peer,
  4359. .throttle_ops = &dp_ops_throttle,
  4360. .mob_stats_ops = &dp_ops_mob_stats,
  4361. #endif
  4362. };
  4363. /*
  4364. * dp_soc_set_txrx_ring_map()
  4365. * @dp_soc: DP handler for soc
  4366. *
  4367. * Return: Void
  4368. */
  4369. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4370. {
  4371. uint32_t i;
  4372. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4373. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4374. }
  4375. }
  4376. /*
  4377. * dp_soc_attach_wifi3() - Attach txrx SOC
  4378. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4379. * @htc_handle: Opaque HTC handle
  4380. * @hif_handle: Opaque HIF handle
  4381. * @qdf_osdev: QDF device
  4382. *
  4383. * Return: DP SOC handle on success, NULL on failure
  4384. */
  4385. /*
  4386. * Local prototype added to temporarily address warning caused by
  4387. * -Wmissing-prototypes. A more correct solution, namely to expose
  4388. * a prototype in an appropriate header file, will come later.
  4389. */
  4390. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4391. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4392. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4393. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4394. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4395. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4396. {
  4397. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4398. if (!soc) {
  4399. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4400. FL("DP SOC memory allocation failed"));
  4401. goto fail0;
  4402. }
  4403. soc->cdp_soc.ops = &dp_txrx_ops;
  4404. soc->cdp_soc.ol_ops = ol_ops;
  4405. soc->osif_soc = osif_soc;
  4406. soc->osdev = qdf_osdev;
  4407. soc->hif_handle = hif_handle;
  4408. soc->psoc = psoc;
  4409. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4410. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4411. soc->hal_soc, qdf_osdev);
  4412. if (!soc->htt_handle) {
  4413. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4414. FL("HTT attach failed"));
  4415. goto fail1;
  4416. }
  4417. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4418. if (!soc->wlan_cfg_ctx) {
  4419. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4420. FL("wlan_cfg_soc_attach failed"));
  4421. goto fail2;
  4422. }
  4423. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4424. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4425. CDP_CFG_MAX_PEER_ID);
  4426. if (ret != -EINVAL) {
  4427. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4428. }
  4429. }
  4430. qdf_spinlock_create(&soc->peer_ref_mutex);
  4431. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4432. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4433. /* fill the tx/rx cpu ring map*/
  4434. dp_soc_set_txrx_ring_map(soc);
  4435. return (void *)soc;
  4436. fail2:
  4437. htt_soc_detach(soc->htt_handle);
  4438. fail1:
  4439. qdf_mem_free(soc);
  4440. fail0:
  4441. return NULL;
  4442. }
  4443. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4444. /*
  4445. * dp_set_pktlog_wifi3() - attach txrx vdev
  4446. * @pdev: Datapath PDEV handle
  4447. * @event: which event's notifications are being subscribed to
  4448. * @enable: WDI event subscribe or not. (True or False)
  4449. *
  4450. * Return: Success, NULL on failure
  4451. */
  4452. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4453. bool enable)
  4454. {
  4455. struct dp_soc *soc = pdev->soc;
  4456. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4457. if (enable) {
  4458. switch (event) {
  4459. case WDI_EVENT_RX_DESC:
  4460. if (pdev->monitor_vdev) {
  4461. /* Nothing needs to be done if monitor mode is
  4462. * enabled
  4463. */
  4464. return 0;
  4465. }
  4466. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4467. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4468. htt_tlv_filter.mpdu_start = 1;
  4469. htt_tlv_filter.msdu_start = 1;
  4470. htt_tlv_filter.msdu_end = 1;
  4471. htt_tlv_filter.mpdu_end = 1;
  4472. htt_tlv_filter.packet_header = 1;
  4473. htt_tlv_filter.attention = 1;
  4474. htt_tlv_filter.ppdu_start = 1;
  4475. htt_tlv_filter.ppdu_end = 1;
  4476. htt_tlv_filter.ppdu_end_user_stats = 1;
  4477. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4478. htt_tlv_filter.ppdu_end_status_done = 1;
  4479. htt_tlv_filter.enable_fp = 1;
  4480. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4481. pdev->pdev_id,
  4482. pdev->rxdma_mon_status_ring.hal_srng,
  4483. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4484. &htt_tlv_filter);
  4485. }
  4486. break;
  4487. case WDI_EVENT_LITE_RX:
  4488. if (pdev->monitor_vdev) {
  4489. /* Nothing needs to be done if monitor mode is
  4490. * enabled
  4491. */
  4492. return 0;
  4493. }
  4494. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4495. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4496. htt_tlv_filter.ppdu_start = 1;
  4497. htt_tlv_filter.ppdu_end = 1;
  4498. htt_tlv_filter.ppdu_end_user_stats = 1;
  4499. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4500. htt_tlv_filter.ppdu_end_status_done = 1;
  4501. htt_tlv_filter.enable_fp = 1;
  4502. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4503. pdev->pdev_id,
  4504. pdev->rxdma_mon_status_ring.hal_srng,
  4505. RXDMA_MONITOR_STATUS,
  4506. RX_BUFFER_SIZE_PKTLOG_LITE,
  4507. &htt_tlv_filter);
  4508. }
  4509. break;
  4510. case WDI_EVENT_LITE_T2H:
  4511. if (pdev->monitor_vdev) {
  4512. /* Nothing needs to be done if monitor mode is
  4513. * enabled
  4514. */
  4515. return 0;
  4516. }
  4517. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4518. * passing value 0xffff. Once these macros will define in htt
  4519. * header file will use proper macros
  4520. */
  4521. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4522. break;
  4523. default:
  4524. /* Nothing needs to be done for other pktlog types */
  4525. break;
  4526. }
  4527. } else {
  4528. switch (event) {
  4529. case WDI_EVENT_RX_DESC:
  4530. case WDI_EVENT_LITE_RX:
  4531. if (pdev->monitor_vdev) {
  4532. /* Nothing needs to be done if monitor mode is
  4533. * enabled
  4534. */
  4535. return 0;
  4536. }
  4537. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4538. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4539. /* htt_tlv_filter is initialized to 0 */
  4540. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4541. pdev->pdev_id,
  4542. pdev->rxdma_mon_status_ring.hal_srng,
  4543. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4544. &htt_tlv_filter);
  4545. }
  4546. break;
  4547. case WDI_EVENT_LITE_T2H:
  4548. if (pdev->monitor_vdev) {
  4549. /* Nothing needs to be done if monitor mode is
  4550. * enabled
  4551. */
  4552. return 0;
  4553. }
  4554. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4555. * passing value 0. Once these macros will define in htt
  4556. * header file will use proper macros
  4557. */
  4558. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4559. break;
  4560. default:
  4561. /* Nothing needs to be done for other pktlog types */
  4562. break;
  4563. }
  4564. }
  4565. return 0;
  4566. }
  4567. #endif