cvp_smem.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/dma-buf.h>
  7. #include <linux/dma-heap.h>
  8. #include <linux/dma-direction.h>
  9. #include <linux/iommu.h>
  10. #include <linux/msm_dma_iommu_mapping.h>
  11. #include <soc/qcom/secure_buffer.h>
  12. #include <linux/mem-buf.h>
  13. #include <linux/slab.h>
  14. #include <linux/types.h>
  15. #include <linux/qcom-dma-mapping.h>
  16. #include <linux/version.h>
  17. #include "msm_cvp_core.h"
  18. #include "msm_cvp_debug.h"
  19. #include "msm_cvp_resources.h"
  20. #include "cvp_core_hfi.h"
  21. #include "msm_cvp_dsp.h"
  22. static void * __cvp_dma_buf_vmap(struct dma_buf *dbuf)
  23. {
  24. #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0))
  25. struct dma_buf_map map;
  26. #else
  27. struct iosys_map map;
  28. #endif
  29. void *dma_map;
  30. int err;
  31. err = dma_buf_vmap(dbuf, &map);
  32. dma_map = err ? NULL : map.vaddr;
  33. if (!dma_map)
  34. dprintk(CVP_ERR, "map to kvaddr failed\n");
  35. return dma_map;
  36. }
  37. static void __cvp_dma_buf_vunmap(struct dma_buf *dbuf, void *vaddr)
  38. {
  39. #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0))
  40. struct dma_buf_map map = { \
  41. .vaddr = vaddr, \
  42. .is_iomem = false, \
  43. };
  44. #else
  45. struct iosys_map map = { \
  46. .vaddr = vaddr, \
  47. .is_iomem = false, \
  48. };
  49. #endif
  50. if (vaddr)
  51. dma_buf_vunmap(dbuf, &map);
  52. }
  53. static int msm_dma_get_device_address(struct dma_buf *dbuf, u32 align,
  54. dma_addr_t *iova, u32 flags, struct msm_cvp_platform_resources *res,
  55. struct cvp_dma_mapping_info *mapping_info)
  56. {
  57. int rc = 0;
  58. struct dma_buf_attachment *attach;
  59. struct sg_table *table = NULL;
  60. struct context_bank_info *cb = NULL;
  61. if (!dbuf || !iova || !mapping_info) {
  62. dprintk(CVP_ERR, "Invalid params: %pK, %pK, %pK\n",
  63. dbuf, iova, mapping_info);
  64. return -EINVAL;
  65. }
  66. if (is_iommu_present(res)) {
  67. cb = msm_cvp_smem_get_context_bank(res, flags);
  68. if (!cb) {
  69. dprintk(CVP_ERR,
  70. "%s: Failed to get context bank device\n",
  71. __func__);
  72. rc = -EIO;
  73. goto mem_map_failed;
  74. }
  75. /* Prepare a dma buf for dma on the given device */
  76. attach = dma_buf_attach(dbuf, cb->dev);
  77. if (IS_ERR_OR_NULL(attach)) {
  78. rc = PTR_ERR(attach) ?: -ENOMEM;
  79. dprintk(CVP_ERR, "Failed to attach dmabuf\n");
  80. goto mem_buf_attach_failed;
  81. }
  82. dprintk(CVP_MEM, "%s: CB dev: %s, attach dev: %s, attach: 0x%lx, dbuf: 0x%lx",
  83. __func__, dev_name(cb->dev), dev_name(attach->dev), attach, dbuf);
  84. /*
  85. * Get the scatterlist for the given attachment
  86. * Mapping of sg is taken care by map attachment
  87. */
  88. /*
  89. * We do not need dma_map function to perform cache operations
  90. * on the whole buffer size and hence pass skip sync flag.
  91. * We do the required cache operations separately for the
  92. * required buffer size
  93. */
  94. attach->dma_map_attrs |= DMA_ATTR_SKIP_CPU_SYNC;
  95. if (flags & SMEM_CAMERA)
  96. attach->dma_map_attrs |= DMA_ATTR_QTI_SMMU_PROXY_MAP;
  97. if (res->sys_cache_present)
  98. attach->dma_map_attrs |=
  99. DMA_ATTR_IOMMU_USE_UPSTREAM_HINT;
  100. table = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
  101. if (IS_ERR_OR_NULL(table)) {
  102. dprintk(CVP_ERR, "Failed to map table %d\n", PTR_ERR(table));
  103. dprintk(CVP_ERR,
  104. "Mapping detail dma_buf 0x%llx, %s, size %#x\n",
  105. dbuf, dbuf->name, dbuf->size);
  106. rc = PTR_ERR(table) ?: -ENOMEM;
  107. goto mem_map_table_failed;
  108. }
  109. if (table->sgl) {
  110. *iova = table->sgl->dma_address;
  111. } else {
  112. dprintk(CVP_ERR, "sgl is NULL\n");
  113. rc = -ENOMEM;
  114. goto mem_map_sg_failed;
  115. }
  116. mapping_info->dev = cb->dev;
  117. mapping_info->domain = cb->domain;
  118. mapping_info->table = table;
  119. mapping_info->attach = attach;
  120. mapping_info->buf = dbuf;
  121. mapping_info->cb_info = (void *)cb;
  122. dprintk(CVP_MEM, "%s: sg-table: 0x%lx, dbuf: 0x%lx, table->sgl->dma_address: 0x%lx",
  123. __func__, table, dbuf, table->sgl->dma_address);
  124. } else {
  125. dprintk(CVP_MEM, "iommu not present, use phys mem addr\n");
  126. }
  127. return 0;
  128. mem_map_sg_failed:
  129. dma_buf_unmap_attachment(attach, table, DMA_BIDIRECTIONAL);
  130. mem_map_table_failed:
  131. dma_buf_detach(dbuf, attach);
  132. mem_buf_attach_failed:
  133. mem_map_failed:
  134. return rc;
  135. }
  136. static int msm_dma_put_device_address(u32 flags,
  137. struct cvp_dma_mapping_info *mapping_info)
  138. {
  139. int rc = 0;
  140. struct dma_buf_attachment *attach = NULL;
  141. struct sg_table *table = NULL;
  142. struct context_bank_info *cb = NULL;
  143. struct dma_buf *dbuf = NULL;
  144. if (!mapping_info) {
  145. dprintk(CVP_WARN, "Invalid mapping_info\n");
  146. return -EINVAL;
  147. }
  148. if (!mapping_info->dev || !mapping_info->table ||
  149. !mapping_info->buf || !mapping_info->attach ||
  150. !mapping_info->cb_info) {
  151. dprintk(CVP_WARN, "Invalid params\n");
  152. return -EINVAL;
  153. }
  154. attach = mapping_info->attach;
  155. table = mapping_info->table;
  156. cb = (struct context_bank_info *) mapping_info->cb_info;
  157. dbuf = mapping_info->buf;
  158. dprintk(CVP_MEM, "%s: CB dev_name: %s, attach dev_name: %s, attach: 0x%lx, dbuf: 0x%lx",
  159. __func__, dev_name(cb->dev), dev_name(attach->dev), attach, dbuf);
  160. dprintk(CVP_MEM, "%s: sg-table: 0x%lx, dbuf: 0x%lx, table->sgl->dma_address: 0x%lx",
  161. __func__, table, dbuf, table->sgl->dma_address);
  162. dma_buf_unmap_attachment(mapping_info->attach,
  163. mapping_info->table, DMA_BIDIRECTIONAL);
  164. dma_buf_detach(mapping_info->buf, mapping_info->attach);
  165. mapping_info->dev = NULL;
  166. mapping_info->domain = NULL;
  167. mapping_info->table = NULL;
  168. mapping_info->attach = NULL;
  169. mapping_info->buf = NULL;
  170. mapping_info->cb_info = NULL;
  171. return rc;
  172. }
  173. struct dma_buf *msm_cvp_smem_get_dma_buf(int fd)
  174. {
  175. struct dma_buf *dma_buf;
  176. dma_buf = dma_buf_get(fd);
  177. if (IS_ERR_OR_NULL(dma_buf)) {
  178. dprintk(CVP_ERR, "Failed to get dma_buf for %d, error %ld\n",
  179. fd, PTR_ERR(dma_buf));
  180. dma_buf = NULL;
  181. }
  182. return dma_buf;
  183. }
  184. void msm_cvp_smem_put_dma_buf(void *dma_buf)
  185. {
  186. if (!dma_buf) {
  187. dprintk(CVP_ERR, "%s: NULL dma_buf\n", __func__);
  188. return;
  189. }
  190. dma_heap_buffer_free((struct dma_buf *)dma_buf);
  191. }
  192. int msm_cvp_map_smem(struct msm_cvp_inst *inst,
  193. struct msm_cvp_smem *smem,
  194. const char *str)
  195. {
  196. int *vmid_list;
  197. int *perms_list;
  198. int nelems = 0;
  199. int i, rc = 0;
  200. dma_addr_t iova = 0;
  201. u32 temp = 0, checksum = 0;
  202. u32 align = SZ_4K;
  203. struct dma_buf *dma_buf;
  204. bool is_config_pkt = false;
  205. if (!inst || !smem) {
  206. dprintk(CVP_ERR, "%s: Invalid params: %pK %pK\n",
  207. __func__, inst, smem);
  208. return -EINVAL;
  209. }
  210. dma_buf = smem->dma_buf;
  211. rc = mem_buf_dma_buf_copy_vmperm(dma_buf,
  212. &vmid_list, &perms_list, &nelems);
  213. if (rc) {
  214. dprintk(CVP_ERR, "%s fail to get vmid and perms %d\n",
  215. __func__, rc);
  216. return rc;
  217. }
  218. for (temp = 0; temp < nelems; temp++) {
  219. if (vmid_list[temp] == VMID_CP_PIXEL)
  220. smem->flags |= (SMEM_SECURE | SMEM_PIXEL);
  221. else if (vmid_list[temp] == VMID_CP_NON_PIXEL)
  222. smem->flags |= (SMEM_SECURE | SMEM_NON_PIXEL);
  223. else if (vmid_list[temp] == VMID_CP_CAMERA ||
  224. /* To-do: what if the EVA driver runs in TVM */
  225. vmid_list[temp] == VMID_TVM)
  226. smem->flags |= (SMEM_SECURE | SMEM_CAMERA);
  227. dprintk(CVP_MEM, "inst %pK VM idx %d VM_ID %d fd %d pkt_type %#x\n",
  228. inst, temp, vmid_list[temp], smem->fd, smem->pkt_type);
  229. }
  230. rc = msm_dma_get_device_address(dma_buf, align, &iova, smem->flags,
  231. &(inst->core->resources), &smem->mapping_info);
  232. if (rc) {
  233. dprintk(CVP_ERR, "Failed to get device address: %d\n", rc);
  234. goto exit;
  235. }
  236. temp = (u32)iova;
  237. if ((dma_addr_t)temp != iova) {
  238. dprintk(CVP_ERR, "iova(%pa) truncated to %#x", &iova, temp);
  239. rc = -EINVAL;
  240. goto exit;
  241. }
  242. smem->size = dma_buf->size;
  243. smem->device_addr = (u32)iova;
  244. i = get_pkt_index_from_type(smem->pkt_type);
  245. if (i > 0 && smem->pkt_type != HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS
  246. && smem->pkt_type != HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS
  247. && smem->pkt_type != HFI_CMD_SESSION_EVA_DLFL_CONFIG)
  248. /* User persist buffer has no feature config info */
  249. is_config_pkt = cvp_hfi_defs[i].is_config_pkt;
  250. if (i > 0 && cvp_hfi_defs[i].checksum_enabled) {
  251. dma_buf_begin_cpu_access(dma_buf, DMA_BIDIRECTIONAL);
  252. smem->kvaddr = __cvp_dma_buf_vmap(dma_buf);
  253. if (!smem->kvaddr) {
  254. dprintk(CVP_WARN, "%s Fail map into kernel\n",
  255. __func__);
  256. dma_buf_end_cpu_access(dma_buf, DMA_BIDIRECTIONAL);
  257. } else {
  258. for (i = 0; i < 256; i++)
  259. checksum += *(u32 *)(smem->kvaddr + i*sizeof(u32));
  260. dprintk(CVP_MEM, "Map checksum %#x fd=%d\n",
  261. checksum, smem->fd);
  262. }
  263. }
  264. print_smem(CVP_MEM, str, inst, smem);
  265. atomic_inc(&inst->smem_count);
  266. goto success;
  267. exit:
  268. smem->device_addr = 0x0;
  269. success:
  270. kfree(vmid_list);
  271. kfree(perms_list);
  272. return rc;
  273. }
  274. int msm_cvp_unmap_smem(struct msm_cvp_inst *inst,
  275. struct msm_cvp_smem *smem,
  276. const char *str)
  277. {
  278. int i, rc = 0;
  279. u32 checksum = 0;
  280. struct dma_buf *dma_buf;
  281. if (!smem) {
  282. dprintk(CVP_ERR, "%s: Invalid params: %pK\n", __func__, smem);
  283. rc = -EINVAL;
  284. goto exit;
  285. }
  286. print_smem(CVP_MEM, str, inst, smem);
  287. dma_buf = smem->dma_buf;
  288. i = get_pkt_index_from_type(smem->pkt_type);
  289. if (i > 0 && cvp_hfi_defs[i].checksum_enabled) {
  290. if (!smem->kvaddr) {
  291. dprintk(CVP_WARN, "%s DS buf Fail map into kernel\n",
  292. __func__);
  293. dma_buf_end_cpu_access(dma_buf, DMA_BIDIRECTIONAL);
  294. } else {
  295. for (i = 0; i < 256; i++)
  296. checksum += *(u32 *)(smem->kvaddr + i*sizeof(u32));
  297. dprintk(CVP_MEM, "Unmap checksum %#x fd=%d\n",
  298. checksum, smem->fd);
  299. __cvp_dma_buf_vunmap(dma_buf, smem->kvaddr);
  300. smem->kvaddr = 0;
  301. dma_buf_end_cpu_access(dma_buf, DMA_BIDIRECTIONAL);
  302. }
  303. }
  304. rc = msm_dma_put_device_address(smem->flags, &smem->mapping_info);
  305. if (rc) {
  306. dprintk(CVP_ERR, "Failed to put device address: %d\n", rc);
  307. goto exit;
  308. }
  309. smem->device_addr = 0x0;
  310. atomic_dec(&inst->smem_count);
  311. exit:
  312. return rc;
  313. }
  314. static int alloc_dma_mem(size_t size, u32 align, int map_kernel,
  315. struct msm_cvp_platform_resources *res, struct msm_cvp_smem *mem)
  316. {
  317. dma_addr_t iova = 0;
  318. int rc = 0;
  319. struct dma_buf *dbuf = NULL;
  320. struct dma_heap *heap = NULL;
  321. struct mem_buf_lend_kernel_arg arg;
  322. int vmids[1];
  323. int perms[1];
  324. if (!res) {
  325. dprintk(CVP_ERR, "%s: NULL res\n", __func__);
  326. return -EINVAL;
  327. }
  328. align = ALIGN(align, SZ_4K);
  329. size = ALIGN(size, SZ_4K);
  330. if (is_iommu_present(res)) {
  331. heap = dma_heap_find("qcom,system");
  332. dprintk(CVP_MEM, "%s size %zx align %d flag %d\n",
  333. __func__, size, align, mem->flags);
  334. } else {
  335. dprintk(CVP_ERR,
  336. "No IOMMU CB: allocate shared memory heap size %zx align %d\n",
  337. size, align);
  338. }
  339. dbuf = dma_heap_buffer_alloc(heap, size, 0, 0);
  340. if (IS_ERR_OR_NULL(dbuf)) {
  341. dprintk(CVP_ERR,
  342. "Failed to allocate shared memory = %x bytes, %x %x\n",
  343. size, mem->flags, PTR_ERR(dbuf));
  344. rc = -ENOMEM;
  345. goto fail_shared_mem_alloc;
  346. }
  347. perms[0] = PERM_READ | PERM_WRITE;
  348. arg.nr_acl_entries = 1;
  349. arg.vmids = vmids;
  350. arg.perms = perms;
  351. if (mem->flags & SMEM_NON_PIXEL) {
  352. vmids[0] = VMID_CP_NON_PIXEL;
  353. rc = mem_buf_lend(dbuf, &arg);
  354. } else if (mem->flags & SMEM_PIXEL) {
  355. vmids[0] = VMID_CP_PIXEL;
  356. rc = mem_buf_lend(dbuf, &arg);
  357. }
  358. if (rc) {
  359. dprintk(CVP_ERR, "Failed to lend dmabuf %d, vmid %d\n",
  360. rc, vmids[0]);
  361. goto fail_device_address;
  362. }
  363. if (!gfa_cv.dmabuf_f_op)
  364. gfa_cv.dmabuf_f_op = (const struct file_operations *)dbuf->file->f_op;
  365. mem->size = size;
  366. mem->dma_buf = dbuf;
  367. mem->kvaddr = NULL;
  368. rc = msm_dma_get_device_address(dbuf, align, &iova, mem->flags,
  369. res, &mem->mapping_info);
  370. if (rc) {
  371. dprintk(CVP_ERR, "Failed to get device address: %d\n",
  372. rc);
  373. goto fail_device_address;
  374. }
  375. mem->device_addr = (u32)iova;
  376. if ((dma_addr_t)mem->device_addr != iova) {
  377. dprintk(CVP_ERR, "iova(%pa) truncated to %#x",
  378. &iova, mem->device_addr);
  379. goto fail_device_address;
  380. }
  381. if (map_kernel) {
  382. dma_buf_begin_cpu_access(dbuf, DMA_BIDIRECTIONAL);
  383. mem->kvaddr = __cvp_dma_buf_vmap(dbuf);
  384. if (!mem->kvaddr) {
  385. dprintk(CVP_ERR,
  386. "Failed to map shared mem in kernel\n");
  387. rc = -EIO;
  388. goto fail_map;
  389. }
  390. }
  391. dprintk(CVP_MEM,
  392. "%s: dma_buf=%pK,iova=%x,size=%d,kvaddr=%pK,flags=%#lx\n",
  393. __func__, mem->dma_buf, mem->device_addr, mem->size,
  394. mem->kvaddr, mem->flags);
  395. return rc;
  396. fail_map:
  397. if (map_kernel)
  398. dma_buf_end_cpu_access(dbuf, DMA_BIDIRECTIONAL);
  399. fail_device_address:
  400. dma_heap_buffer_free(dbuf);
  401. fail_shared_mem_alloc:
  402. return rc;
  403. }
  404. static int free_dma_mem(struct msm_cvp_smem *mem)
  405. {
  406. dprintk(CVP_MEM,
  407. "%s: dma_buf = %pK, device_addr = %x, size = %d, kvaddr = %pK\n",
  408. __func__, mem->dma_buf, mem->device_addr, mem->size, mem->kvaddr);
  409. if (mem->device_addr) {
  410. msm_dma_put_device_address(mem->flags, &mem->mapping_info);
  411. mem->device_addr = 0x0;
  412. }
  413. if (mem->kvaddr) {
  414. __cvp_dma_buf_vunmap(mem->dma_buf, mem->kvaddr);
  415. mem->kvaddr = NULL;
  416. dma_buf_end_cpu_access(mem->dma_buf, DMA_BIDIRECTIONAL);
  417. }
  418. if (mem->dma_buf) {
  419. dma_heap_buffer_free(mem->dma_buf);
  420. mem->dma_buf = NULL;
  421. }
  422. return 0;
  423. }
  424. int msm_cvp_smem_alloc(size_t size, u32 align, int map_kernel,
  425. void *res, struct msm_cvp_smem *smem)
  426. {
  427. int rc = 0;
  428. if (!smem || !size) {
  429. dprintk(CVP_ERR, "%s: NULL smem or %d size\n",
  430. __func__, (u32)size);
  431. return -EINVAL;
  432. }
  433. rc = alloc_dma_mem(size, align, map_kernel,
  434. (struct msm_cvp_platform_resources *)res, smem);
  435. return rc;
  436. }
  437. int msm_cvp_smem_free(struct msm_cvp_smem *smem)
  438. {
  439. int rc = 0;
  440. if (!smem) {
  441. dprintk(CVP_ERR, "NULL smem passed\n");
  442. return -EINVAL;
  443. }
  444. rc = free_dma_mem(smem);
  445. return rc;
  446. };
  447. int msm_cvp_smem_cache_operations(struct dma_buf *dbuf,
  448. enum smem_cache_ops cache_op, unsigned long offset, unsigned long size)
  449. {
  450. int rc = 0;
  451. if (!dbuf) {
  452. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  453. return -EINVAL;
  454. }
  455. switch (cache_op) {
  456. case SMEM_CACHE_CLEAN:
  457. case SMEM_CACHE_CLEAN_INVALIDATE:
  458. rc = dma_buf_begin_cpu_access_partial(dbuf, DMA_BIDIRECTIONAL,
  459. offset, size);
  460. if (rc)
  461. break;
  462. rc = dma_buf_end_cpu_access_partial(dbuf, DMA_BIDIRECTIONAL,
  463. offset, size);
  464. break;
  465. case SMEM_CACHE_INVALIDATE:
  466. rc = dma_buf_begin_cpu_access_partial(dbuf, DMA_TO_DEVICE,
  467. offset, size);
  468. if (rc)
  469. break;
  470. rc = dma_buf_end_cpu_access_partial(dbuf, DMA_FROM_DEVICE,
  471. offset, size);
  472. break;
  473. default:
  474. dprintk(CVP_ERR, "%s: cache (%d) operation not supported\n",
  475. __func__, cache_op);
  476. rc = -EINVAL;
  477. break;
  478. }
  479. return rc;
  480. }
  481. struct context_bank_info *msm_cvp_smem_get_context_bank(
  482. struct msm_cvp_platform_resources *res,
  483. unsigned int flags)
  484. {
  485. struct context_bank_info *cb = NULL, *match = NULL;
  486. char *search_str;
  487. char *non_secure_cb = "cvp_hlos";
  488. char *secure_nonpixel_cb = "cvp_sec_nonpixel";
  489. char *secure_pixel_cb = "cvp_sec_pixel";
  490. char *camera_cb = "cvp_camera";
  491. char *dsp_cb = "cvp_dsp";
  492. bool is_secure = (flags & SMEM_SECURE) ? true : false;
  493. if (flags & SMEM_PIXEL)
  494. search_str = secure_pixel_cb;
  495. else if (flags & SMEM_NON_PIXEL)
  496. search_str = secure_nonpixel_cb;
  497. else if (flags & SMEM_CAMERA)
  498. /* Secure Camera pixel buffer */
  499. search_str = camera_cb;
  500. else if (flags & SMEM_CDSP)
  501. search_str = dsp_cb;
  502. else
  503. search_str = non_secure_cb;
  504. list_for_each_entry(cb, &res->context_banks, list) {
  505. if (cb->is_secure == is_secure &&
  506. !strcmp(search_str, cb->name)) {
  507. match = cb;
  508. break;
  509. }
  510. }
  511. if (!match)
  512. dprintk(CVP_ERR,
  513. "%s: cb not found for flags %x, is_secure %d\n",
  514. __func__, flags, is_secure);
  515. return match;
  516. }
  517. int msm_cvp_map_ipcc_regs(u32 *iova)
  518. {
  519. struct context_bank_info *cb;
  520. struct msm_cvp_core *core;
  521. struct cvp_hfi_ops *ops_tbl;
  522. struct iris_hfi_device *dev = NULL;
  523. phys_addr_t paddr;
  524. u32 size;
  525. core = cvp_driver->cvp_core;
  526. if (core) {
  527. ops_tbl = core->dev_ops;
  528. if (ops_tbl)
  529. dev = ops_tbl->hfi_device_data;
  530. }
  531. if (!dev)
  532. return -EINVAL;
  533. paddr = dev->res->ipcc_reg_base;
  534. size = dev->res->ipcc_reg_size;
  535. if (!paddr || !size)
  536. return -EINVAL;
  537. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  538. if (!cb) {
  539. dprintk(CVP_ERR, "%s: fail to get context bank\n", __func__);
  540. return -EINVAL;
  541. }
  542. *iova = dma_map_resource(cb->dev, paddr, size, DMA_BIDIRECTIONAL, 0);
  543. if (*iova == DMA_MAPPING_ERROR) {
  544. dprintk(CVP_WARN, "%s: fail to map IPCC regs\n", __func__);
  545. return -EFAULT;
  546. }
  547. return 0;
  548. }
  549. int msm_cvp_unmap_ipcc_regs(u32 iova)
  550. {
  551. struct context_bank_info *cb;
  552. struct msm_cvp_core *core;
  553. struct cvp_hfi_ops *ops_tbl;
  554. struct iris_hfi_device *dev = NULL;
  555. u32 size;
  556. core = cvp_driver->cvp_core;
  557. if (core) {
  558. ops_tbl = core->dev_ops;
  559. if (ops_tbl)
  560. dev = ops_tbl->hfi_device_data;
  561. }
  562. if (!dev)
  563. return -EINVAL;
  564. size = dev->res->ipcc_reg_size;
  565. if (!iova || !size)
  566. return -EINVAL;
  567. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  568. if (!cb) {
  569. dprintk(CVP_ERR, "%s: fail to get context bank\n", __func__);
  570. return -EINVAL;
  571. }
  572. dma_unmap_resource(cb->dev, iova, size, DMA_BIDIRECTIONAL, 0);
  573. return 0;
  574. }