dp_main.c 157 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. bool rx_hash = 1;
  71. qdf_declare_param(rx_hash, bool);
  72. #define STR_MAXLEN 64
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  252. };
  253. /**
  254. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  255. * @ring_num: ring num of the ring being queried
  256. * @grp_mask: the grp_mask array for the ring type in question.
  257. *
  258. * The grp_mask array is indexed by group number and the bit fields correspond
  259. * to ring numbers. We are finding which interrupt group a ring belongs to.
  260. *
  261. * Return: the index in the grp_mask array with the ring number.
  262. * -QDF_STATUS_E_NOENT if no entry is found
  263. */
  264. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  265. {
  266. int ext_group_num;
  267. int mask = 1 << ring_num;
  268. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  269. ext_group_num++) {
  270. if (mask & grp_mask[ext_group_num])
  271. return ext_group_num;
  272. }
  273. return -QDF_STATUS_E_NOENT;
  274. }
  275. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  276. enum hal_ring_type ring_type,
  277. int ring_num)
  278. {
  279. int *grp_mask;
  280. switch (ring_type) {
  281. case WBM2SW_RELEASE:
  282. /* dp_tx_comp_handler - soc->tx_comp_ring */
  283. if (ring_num < 3)
  284. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  285. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  286. else if (ring_num == 3) {
  287. /* sw treats this as a separate ring type */
  288. grp_mask = &soc->wlan_cfg_ctx->
  289. int_rx_wbm_rel_ring_mask[0];
  290. ring_num = 0;
  291. } else {
  292. qdf_assert(0);
  293. return -QDF_STATUS_E_NOENT;
  294. }
  295. break;
  296. case REO_EXCEPTION:
  297. /* dp_rx_err_process - &soc->reo_exception_ring */
  298. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  299. break;
  300. case REO_DST:
  301. /* dp_rx_process - soc->reo_dest_ring */
  302. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  303. break;
  304. case REO_STATUS:
  305. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  306. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  307. break;
  308. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  309. case RXDMA_MONITOR_STATUS:
  310. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  311. case RXDMA_MONITOR_DST:
  312. /* dp_mon_process */
  313. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  314. break;
  315. case RXDMA_MONITOR_BUF:
  316. case RXDMA_BUF:
  317. /* TODO: support low_thresh interrupt */
  318. return -QDF_STATUS_E_NOENT;
  319. break;
  320. case TCL_DATA:
  321. case TCL_CMD:
  322. case REO_CMD:
  323. case SW2WBM_RELEASE:
  324. case WBM_IDLE_LINK:
  325. /* normally empty SW_TO_HW rings */
  326. return -QDF_STATUS_E_NOENT;
  327. break;
  328. case TCL_STATUS:
  329. case REO_REINJECT:
  330. case RXDMA_DST:
  331. /* misc unused rings */
  332. return -QDF_STATUS_E_NOENT;
  333. break;
  334. case CE_SRC:
  335. case CE_DST:
  336. case CE_DST_STATUS:
  337. /* CE_rings - currently handled by hif */
  338. default:
  339. return -QDF_STATUS_E_NOENT;
  340. break;
  341. }
  342. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  343. }
  344. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  345. *ring_params, int ring_type, int ring_num)
  346. {
  347. int msi_group_number;
  348. int msi_data_count;
  349. int ret;
  350. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  351. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  352. &msi_data_count, &msi_data_start,
  353. &msi_irq_start);
  354. if (ret)
  355. return;
  356. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  357. ring_num);
  358. if (msi_group_number < 0) {
  359. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  360. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  361. ring_type, ring_num);
  362. ring_params->msi_addr = 0;
  363. ring_params->msi_data = 0;
  364. return;
  365. }
  366. if (msi_group_number > msi_data_count) {
  367. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  368. FL("2 msi_groups will share an msi; msi_group_num %d"),
  369. msi_group_number);
  370. QDF_ASSERT(0);
  371. }
  372. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  373. ring_params->msi_addr = addr_low;
  374. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  375. ring_params->msi_data = (msi_group_number % msi_data_count)
  376. + msi_data_start;
  377. ring_params->flags |= HAL_SRNG_MSI_INTR;
  378. }
  379. /**
  380. * dp_print_ast_stats() - Dump AST table contents
  381. * @soc: Datapath soc handle
  382. *
  383. * return void
  384. */
  385. #ifdef FEATURE_WDS
  386. static void dp_print_ast_stats(struct dp_soc *soc)
  387. {
  388. uint8_t i;
  389. uint8_t num_entries = 0;
  390. struct dp_vdev *vdev;
  391. struct dp_pdev *pdev;
  392. struct dp_peer *peer;
  393. struct dp_ast_entry *ase, *tmp_ase;
  394. DP_PRINT_STATS("AST Stats:");
  395. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  396. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  397. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  398. DP_PRINT_STATS("AST Table:");
  399. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  400. pdev = soc->pdev_list[i];
  401. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  402. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  403. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  404. DP_PRINT_STATS("%6d mac_addr = %pM"
  405. " peer_mac_addr = %pM"
  406. " type = %d"
  407. " next_hop = %d"
  408. " is_active = %d"
  409. " is_bss = %d",
  410. ++num_entries,
  411. ase->mac_addr.raw,
  412. ase->peer->mac_addr.raw,
  413. ase->type,
  414. ase->next_hop,
  415. ase->is_active,
  416. ase->is_bss);
  417. }
  418. }
  419. }
  420. }
  421. }
  422. #else
  423. static void dp_print_ast_stats(struct dp_soc *soc)
  424. {
  425. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  426. return;
  427. }
  428. #endif
  429. /*
  430. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  431. */
  432. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  433. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  434. {
  435. void *hal_soc = soc->hal_soc;
  436. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  437. /* TODO: See if we should get align size from hal */
  438. uint32_t ring_base_align = 8;
  439. struct hal_srng_params ring_params;
  440. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  441. /* TODO: Currently hal layer takes care of endianness related settings.
  442. * See if these settings need to passed from DP layer
  443. */
  444. ring_params.flags = 0;
  445. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  446. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  447. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  448. srng->hal_srng = NULL;
  449. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  450. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  451. soc->osdev, soc->osdev->dev, srng->alloc_size,
  452. &(srng->base_paddr_unaligned));
  453. if (!srng->base_vaddr_unaligned) {
  454. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  455. FL("alloc failed - ring_type: %d, ring_num %d"),
  456. ring_type, ring_num);
  457. return QDF_STATUS_E_NOMEM;
  458. }
  459. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  460. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  461. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  462. ((unsigned long)(ring_params.ring_base_vaddr) -
  463. (unsigned long)srng->base_vaddr_unaligned);
  464. ring_params.num_entries = num_entries;
  465. if (soc->intr_mode == DP_INTR_MSI) {
  466. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  467. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  468. FL("Using MSI for ring_type: %d, ring_num %d"),
  469. ring_type, ring_num);
  470. } else {
  471. ring_params.msi_data = 0;
  472. ring_params.msi_addr = 0;
  473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  474. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  475. ring_type, ring_num);
  476. }
  477. /*
  478. * Setup interrupt timer and batch counter thresholds for
  479. * interrupt mitigation based on ring type
  480. */
  481. if (ring_type == REO_DST) {
  482. ring_params.intr_timer_thres_us =
  483. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  484. ring_params.intr_batch_cntr_thres_entries =
  485. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  486. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  487. ring_params.intr_timer_thres_us =
  488. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  489. ring_params.intr_batch_cntr_thres_entries =
  490. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  491. } else {
  492. ring_params.intr_timer_thres_us =
  493. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  494. ring_params.intr_batch_cntr_thres_entries =
  495. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  496. }
  497. /* Enable low threshold interrupts for rx buffer rings (regular and
  498. * monitor buffer rings.
  499. * TODO: See if this is required for any other ring
  500. */
  501. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  502. /* TODO: Setting low threshold to 1/8th of ring size
  503. * see if this needs to be configurable
  504. */
  505. ring_params.low_threshold = num_entries >> 3;
  506. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  507. ring_params.intr_timer_thres_us = 0x1000;
  508. }
  509. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  510. mac_id, &ring_params);
  511. return 0;
  512. }
  513. /**
  514. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  515. * Any buffers allocated and attached to ring entries are expected to be freed
  516. * before calling this function.
  517. */
  518. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  519. int ring_type, int ring_num)
  520. {
  521. if (!srng->hal_srng) {
  522. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  523. FL("Ring type: %d, num:%d not setup"),
  524. ring_type, ring_num);
  525. return;
  526. }
  527. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  528. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  529. srng->alloc_size,
  530. srng->base_vaddr_unaligned,
  531. srng->base_paddr_unaligned, 0);
  532. srng->hal_srng = NULL;
  533. }
  534. #ifdef IPA_OFFLOAD
  535. /**
  536. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  537. * @soc: data path instance
  538. * @pdev: core txrx pdev context
  539. *
  540. * Free allocated TX buffers with WBM SRNG
  541. *
  542. * Return: none
  543. */
  544. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  545. {
  546. int idx;
  547. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  548. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  549. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  550. }
  551. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  552. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  553. }
  554. /**
  555. * dp_rx_ipa_uc_detach - free autonomy RX resources
  556. * @soc: data path instance
  557. * @pdev: core txrx pdev context
  558. *
  559. * This function will detach DP RX into main device context
  560. * will free DP Rx resources.
  561. *
  562. * Return: none
  563. */
  564. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  565. {
  566. }
  567. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  568. {
  569. /* TX resource detach */
  570. dp_tx_ipa_uc_detach(soc, pdev);
  571. /* RX resource detach */
  572. dp_rx_ipa_uc_detach(soc, pdev);
  573. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  574. return QDF_STATUS_SUCCESS; /* success */
  575. }
  576. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  577. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  578. /**
  579. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  580. * @soc: data path instance
  581. * @pdev: Physical device handle
  582. *
  583. * Allocate TX buffer from non-cacheable memory
  584. * Attache allocated TX buffers with WBM SRNG
  585. *
  586. * Return: int
  587. */
  588. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  589. {
  590. uint32_t tx_buffer_count;
  591. uint32_t ring_base_align = 8;
  592. void *buffer_vaddr_unaligned;
  593. void *buffer_vaddr;
  594. qdf_dma_addr_t buffer_paddr_unaligned;
  595. qdf_dma_addr_t buffer_paddr;
  596. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  597. uint32_t paddr_lo;
  598. uint32_t paddr_hi;
  599. void *ring_entry;
  600. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  601. int retval = QDF_STATUS_SUCCESS;
  602. /*
  603. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  604. * unsigned int uc_tx_buf_sz =
  605. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  606. */
  607. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  608. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  609. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  610. "requested %d buffers to be posted to wbm ring",
  611. ring_size);
  612. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  613. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  614. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  615. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  616. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  617. return -ENOMEM;
  618. }
  619. hal_srng_access_start(soc->hal_soc, wbm_srng);
  620. /* Allocate TX buffers as many as possible */
  621. for (tx_buffer_count = 0;
  622. tx_buffer_count < ring_size; tx_buffer_count++) {
  623. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  624. if (!ring_entry) {
  625. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  626. "Failed to get WBM ring entry\n");
  627. goto fail;
  628. }
  629. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  630. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  631. if (!buffer_vaddr_unaligned) {
  632. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  633. "IPA WDI TX buffer alloc fail %d allocated\n",
  634. tx_buffer_count);
  635. break;
  636. }
  637. buffer_vaddr = buffer_vaddr_unaligned +
  638. ((unsigned long)buffer_vaddr_unaligned %
  639. ring_base_align);
  640. buffer_paddr = buffer_paddr_unaligned +
  641. ((unsigned long)(buffer_vaddr) -
  642. (unsigned long)buffer_vaddr_unaligned);
  643. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  644. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  645. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  646. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  647. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  648. buffer_vaddr;
  649. }
  650. hal_srng_access_end(soc->hal_soc, wbm_srng);
  651. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  652. return retval;
  653. fail:
  654. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  655. return retval;
  656. }
  657. /**
  658. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  659. * @soc: data path instance
  660. * @pdev: core txrx pdev context
  661. *
  662. * This function will attach a DP RX instance into the main
  663. * device (SOC) context.
  664. *
  665. * Return: QDF_STATUS_SUCCESS: success
  666. * QDF_STATUS_E_RESOURCES: Error return
  667. */
  668. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  669. {
  670. return QDF_STATUS_SUCCESS;
  671. }
  672. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  673. {
  674. int error;
  675. /* TX resource attach */
  676. error = dp_tx_ipa_uc_attach(soc, pdev);
  677. if (error) {
  678. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  679. "DP IPA UC TX attach fail code %d\n", error);
  680. return error;
  681. }
  682. /* RX resource attach */
  683. error = dp_rx_ipa_uc_attach(soc, pdev);
  684. if (error) {
  685. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  686. "DP IPA UC RX attach fail code %d\n", error);
  687. dp_tx_ipa_uc_detach(soc, pdev);
  688. return error;
  689. }
  690. return QDF_STATUS_SUCCESS; /* success */
  691. }
  692. #else
  693. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  694. {
  695. return QDF_STATUS_SUCCESS;
  696. }
  697. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  698. {
  699. return QDF_STATUS_SUCCESS;
  700. }
  701. #endif
  702. /* TODO: Need this interface from HIF */
  703. void *hif_get_hal_handle(void *hif_handle);
  704. /*
  705. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  706. * @dp_ctx: DP SOC handle
  707. * @budget: Number of frames/descriptors that can be processed in one shot
  708. *
  709. * Return: remaining budget/quota for the soc device
  710. */
  711. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  712. {
  713. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  714. struct dp_soc *soc = int_ctx->soc;
  715. int ring = 0;
  716. uint32_t work_done = 0;
  717. int budget = dp_budget;
  718. uint8_t tx_mask = int_ctx->tx_ring_mask;
  719. uint8_t rx_mask = int_ctx->rx_ring_mask;
  720. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  721. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  722. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  723. uint32_t remaining_quota = dp_budget;
  724. /* Process Tx completion interrupts first to return back buffers */
  725. while (tx_mask) {
  726. if (tx_mask & 0x1) {
  727. work_done = dp_tx_comp_handler(soc,
  728. soc->tx_comp_ring[ring].hal_srng,
  729. remaining_quota);
  730. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  731. "tx mask 0x%x ring %d, budget %d, work_done %d",
  732. tx_mask, ring, budget, work_done);
  733. budget -= work_done;
  734. if (budget <= 0)
  735. goto budget_done;
  736. remaining_quota = budget;
  737. }
  738. tx_mask = tx_mask >> 1;
  739. ring++;
  740. }
  741. /* Process REO Exception ring interrupt */
  742. if (rx_err_mask) {
  743. work_done = dp_rx_err_process(soc,
  744. soc->reo_exception_ring.hal_srng,
  745. remaining_quota);
  746. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  747. "REO Exception Ring: work_done %d budget %d",
  748. work_done, budget);
  749. budget -= work_done;
  750. if (budget <= 0) {
  751. goto budget_done;
  752. }
  753. remaining_quota = budget;
  754. }
  755. /* Process Rx WBM release ring interrupt */
  756. if (rx_wbm_rel_mask) {
  757. work_done = dp_rx_wbm_err_process(soc,
  758. soc->rx_rel_ring.hal_srng, remaining_quota);
  759. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  760. "WBM Release Ring: work_done %d budget %d",
  761. work_done, budget);
  762. budget -= work_done;
  763. if (budget <= 0) {
  764. goto budget_done;
  765. }
  766. remaining_quota = budget;
  767. }
  768. /* Process Rx interrupts */
  769. if (rx_mask) {
  770. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  771. if (rx_mask & (1 << ring)) {
  772. work_done = dp_rx_process(int_ctx,
  773. soc->reo_dest_ring[ring].hal_srng,
  774. remaining_quota);
  775. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  776. "rx mask 0x%x ring %d, work_done %d budget %d",
  777. rx_mask, ring, work_done, budget);
  778. budget -= work_done;
  779. if (budget <= 0)
  780. goto budget_done;
  781. remaining_quota = budget;
  782. }
  783. }
  784. }
  785. if (reo_status_mask)
  786. dp_reo_status_ring_handler(soc);
  787. /* Process LMAC interrupts */
  788. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  789. if (soc->pdev_list[ring] == NULL)
  790. continue;
  791. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  792. work_done = dp_mon_process(soc, ring, remaining_quota);
  793. budget -= work_done;
  794. remaining_quota = budget;
  795. }
  796. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  797. work_done = dp_rxdma_err_process(soc, ring,
  798. remaining_quota);
  799. budget -= work_done;
  800. }
  801. }
  802. qdf_lro_flush(int_ctx->lro_ctx);
  803. budget_done:
  804. return dp_budget - budget;
  805. }
  806. #ifdef DP_INTR_POLL_BASED
  807. /* dp_interrupt_timer()- timer poll for interrupts
  808. *
  809. * @arg: SoC Handle
  810. *
  811. * Return:
  812. *
  813. */
  814. static void dp_interrupt_timer(void *arg)
  815. {
  816. struct dp_soc *soc = (struct dp_soc *) arg;
  817. int i;
  818. if (qdf_atomic_read(&soc->cmn_init_done)) {
  819. for (i = 0;
  820. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  821. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  822. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  823. }
  824. }
  825. /*
  826. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  827. * @txrx_soc: DP SOC handle
  828. *
  829. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  830. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  831. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  832. *
  833. * Return: 0 for success. nonzero for failure.
  834. */
  835. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  836. {
  837. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  838. int i;
  839. soc->intr_mode = DP_INTR_POLL;
  840. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  841. soc->intr_ctx[i].dp_intr_id = i;
  842. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  843. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  844. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  845. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  846. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  847. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  848. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  849. soc->intr_ctx[i].soc = soc;
  850. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  851. }
  852. qdf_timer_init(soc->osdev, &soc->int_timer,
  853. dp_interrupt_timer, (void *)soc,
  854. QDF_TIMER_TYPE_WAKE_APPS);
  855. return QDF_STATUS_SUCCESS;
  856. }
  857. #endif
  858. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  859. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  860. {
  861. int j;
  862. int num_irq = 0;
  863. int tx_mask =
  864. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  865. int rx_mask =
  866. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  867. int rx_mon_mask =
  868. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  869. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  870. soc->wlan_cfg_ctx, intr_ctx_num);
  871. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  872. soc->wlan_cfg_ctx, intr_ctx_num);
  873. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  874. soc->wlan_cfg_ctx, intr_ctx_num);
  875. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  876. if (tx_mask & (1 << j)) {
  877. irq_id_map[num_irq++] =
  878. (wbm2host_tx_completions_ring1 - j);
  879. }
  880. if (rx_mask & (1 << j)) {
  881. irq_id_map[num_irq++] =
  882. (reo2host_destination_ring1 - j);
  883. }
  884. if (rx_mon_mask & (1 << j)) {
  885. irq_id_map[num_irq++] =
  886. (ppdu_end_interrupts_mac1 - j);
  887. }
  888. if (rx_wbm_rel_ring_mask & (1 << j))
  889. irq_id_map[num_irq++] = wbm2host_rx_release;
  890. if (rx_err_ring_mask & (1 << j))
  891. irq_id_map[num_irq++] = reo2host_exception;
  892. if (reo_status_ring_mask & (1 << j))
  893. irq_id_map[num_irq++] = reo2host_status;
  894. }
  895. *num_irq_r = num_irq;
  896. }
  897. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  898. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  899. int msi_vector_count, int msi_vector_start)
  900. {
  901. int tx_mask = wlan_cfg_get_tx_ring_mask(
  902. soc->wlan_cfg_ctx, intr_ctx_num);
  903. int rx_mask = wlan_cfg_get_rx_ring_mask(
  904. soc->wlan_cfg_ctx, intr_ctx_num);
  905. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  906. soc->wlan_cfg_ctx, intr_ctx_num);
  907. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  908. soc->wlan_cfg_ctx, intr_ctx_num);
  909. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  910. soc->wlan_cfg_ctx, intr_ctx_num);
  911. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  912. soc->wlan_cfg_ctx, intr_ctx_num);
  913. unsigned int vector =
  914. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  915. int num_irq = 0;
  916. soc->intr_mode = DP_INTR_MSI;
  917. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  918. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  919. irq_id_map[num_irq++] =
  920. pld_get_msi_irq(soc->osdev->dev, vector);
  921. *num_irq_r = num_irq;
  922. }
  923. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  924. int *irq_id_map, int *num_irq)
  925. {
  926. int msi_vector_count, ret;
  927. uint32_t msi_base_data, msi_vector_start;
  928. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  929. &msi_vector_count,
  930. &msi_base_data,
  931. &msi_vector_start);
  932. if (ret)
  933. return dp_soc_interrupt_map_calculate_integrated(soc,
  934. intr_ctx_num, irq_id_map, num_irq);
  935. else
  936. dp_soc_interrupt_map_calculate_msi(soc,
  937. intr_ctx_num, irq_id_map, num_irq,
  938. msi_vector_count, msi_vector_start);
  939. }
  940. /*
  941. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  942. * @txrx_soc: DP SOC handle
  943. *
  944. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  945. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  946. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  947. *
  948. * Return: 0 for success. nonzero for failure.
  949. */
  950. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  951. {
  952. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  953. int i = 0;
  954. int num_irq = 0;
  955. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  956. int ret = 0;
  957. /* Map of IRQ ids registered with one interrupt context */
  958. int irq_id_map[HIF_MAX_GRP_IRQ];
  959. int tx_mask =
  960. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  961. int rx_mask =
  962. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  963. int rx_mon_mask =
  964. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  965. int rx_err_ring_mask =
  966. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  967. int rx_wbm_rel_ring_mask =
  968. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  969. int reo_status_ring_mask =
  970. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  971. int rxdma2host_ring_mask =
  972. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  973. soc->intr_ctx[i].dp_intr_id = i;
  974. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  975. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  976. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  977. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  978. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  979. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  980. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  981. soc->intr_ctx[i].soc = soc;
  982. num_irq = 0;
  983. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  984. &num_irq);
  985. ret = hif_register_ext_group(soc->hif_handle,
  986. num_irq, irq_id_map, dp_service_srngs,
  987. &soc->intr_ctx[i], "dp_intr",
  988. HIF_EXEC_NAPI_TYPE, 2);
  989. if (ret) {
  990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  991. FL("failed, ret = %d"), ret);
  992. return QDF_STATUS_E_FAILURE;
  993. }
  994. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  995. }
  996. hif_configure_ext_group_interrupts(soc->hif_handle);
  997. return QDF_STATUS_SUCCESS;
  998. }
  999. #ifdef CONFIG_MCL
  1000. extern int con_mode_monitor;
  1001. /*
  1002. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  1003. * @txrx_soc: DP SOC handle
  1004. *
  1005. * Call the appropriate attach function based on the mode of operation.
  1006. * This is a WAR for enabling monitor mode.
  1007. *
  1008. * Return: 0 for success. nonzero for failure.
  1009. */
  1010. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  1011. {
  1012. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1013. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  1014. con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  1015. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1016. "%s: Poll mode", __func__);
  1017. return dp_soc_interrupt_attach_poll(txrx_soc);
  1018. } else {
  1019. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1020. "%s: Interrupt mode", __func__);
  1021. return dp_soc_interrupt_attach(txrx_soc);
  1022. }
  1023. }
  1024. #else
  1025. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  1026. {
  1027. return dp_soc_interrupt_attach_poll(txrx_soc);
  1028. }
  1029. #endif
  1030. /*
  1031. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1032. * @txrx_soc: DP SOC handle
  1033. *
  1034. * Return: void
  1035. */
  1036. static void dp_soc_interrupt_detach(void *txrx_soc)
  1037. {
  1038. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1039. int i;
  1040. if (soc->intr_mode == DP_INTR_POLL) {
  1041. qdf_timer_stop(&soc->int_timer);
  1042. qdf_timer_free(&soc->int_timer);
  1043. } else {
  1044. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1045. }
  1046. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1047. soc->intr_ctx[i].tx_ring_mask = 0;
  1048. soc->intr_ctx[i].rx_ring_mask = 0;
  1049. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1050. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1051. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1052. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1053. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1054. }
  1055. }
  1056. #define AVG_MAX_MPDUS_PER_TID 128
  1057. #define AVG_TIDS_PER_CLIENT 2
  1058. #define AVG_FLOWS_PER_TID 2
  1059. #define AVG_MSDUS_PER_FLOW 128
  1060. #define AVG_MSDUS_PER_MPDU 4
  1061. /*
  1062. * Allocate and setup link descriptor pool that will be used by HW for
  1063. * various link and queue descriptors and managed by WBM
  1064. */
  1065. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1066. {
  1067. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1068. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1069. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1070. uint32_t num_mpdus_per_link_desc =
  1071. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1072. uint32_t num_msdus_per_link_desc =
  1073. hal_num_msdus_per_link_desc(soc->hal_soc);
  1074. uint32_t num_mpdu_links_per_queue_desc =
  1075. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1076. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1077. uint32_t total_link_descs, total_mem_size;
  1078. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1079. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1080. uint32_t num_link_desc_banks;
  1081. uint32_t last_bank_size = 0;
  1082. uint32_t entry_size, num_entries;
  1083. int i;
  1084. uint32_t desc_id = 0;
  1085. /* Only Tx queue descriptors are allocated from common link descriptor
  1086. * pool Rx queue descriptors are not included in this because (REO queue
  1087. * extension descriptors) they are expected to be allocated contiguously
  1088. * with REO queue descriptors
  1089. */
  1090. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1091. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1092. num_mpdu_queue_descs = num_mpdu_link_descs /
  1093. num_mpdu_links_per_queue_desc;
  1094. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1095. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1096. num_msdus_per_link_desc;
  1097. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1098. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1099. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1100. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1101. /* Round up to power of 2 */
  1102. total_link_descs = 1;
  1103. while (total_link_descs < num_entries)
  1104. total_link_descs <<= 1;
  1105. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1106. FL("total_link_descs: %u, link_desc_size: %d"),
  1107. total_link_descs, link_desc_size);
  1108. total_mem_size = total_link_descs * link_desc_size;
  1109. total_mem_size += link_desc_align;
  1110. if (total_mem_size <= max_alloc_size) {
  1111. num_link_desc_banks = 0;
  1112. last_bank_size = total_mem_size;
  1113. } else {
  1114. num_link_desc_banks = (total_mem_size) /
  1115. (max_alloc_size - link_desc_align);
  1116. last_bank_size = total_mem_size %
  1117. (max_alloc_size - link_desc_align);
  1118. }
  1119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1120. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1121. total_mem_size, num_link_desc_banks);
  1122. for (i = 0; i < num_link_desc_banks; i++) {
  1123. soc->link_desc_banks[i].base_vaddr_unaligned =
  1124. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1125. max_alloc_size,
  1126. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1127. soc->link_desc_banks[i].size = max_alloc_size;
  1128. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1129. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1130. ((unsigned long)(
  1131. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1132. link_desc_align));
  1133. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1134. soc->link_desc_banks[i].base_paddr_unaligned) +
  1135. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1136. (unsigned long)(
  1137. soc->link_desc_banks[i].base_vaddr_unaligned));
  1138. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1139. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1140. FL("Link descriptor memory alloc failed"));
  1141. goto fail;
  1142. }
  1143. }
  1144. if (last_bank_size) {
  1145. /* Allocate last bank in case total memory required is not exact
  1146. * multiple of max_alloc_size
  1147. */
  1148. soc->link_desc_banks[i].base_vaddr_unaligned =
  1149. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1150. last_bank_size,
  1151. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1152. soc->link_desc_banks[i].size = last_bank_size;
  1153. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1154. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1155. ((unsigned long)(
  1156. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1157. link_desc_align));
  1158. soc->link_desc_banks[i].base_paddr =
  1159. (unsigned long)(
  1160. soc->link_desc_banks[i].base_paddr_unaligned) +
  1161. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1162. (unsigned long)(
  1163. soc->link_desc_banks[i].base_vaddr_unaligned));
  1164. }
  1165. /* Allocate and setup link descriptor idle list for HW internal use */
  1166. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1167. total_mem_size = entry_size * total_link_descs;
  1168. if (total_mem_size <= max_alloc_size) {
  1169. void *desc;
  1170. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1171. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1172. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1173. FL("Link desc idle ring setup failed"));
  1174. goto fail;
  1175. }
  1176. hal_srng_access_start_unlocked(soc->hal_soc,
  1177. soc->wbm_idle_link_ring.hal_srng);
  1178. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1179. soc->link_desc_banks[i].base_paddr; i++) {
  1180. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1181. ((unsigned long)(
  1182. soc->link_desc_banks[i].base_vaddr) -
  1183. (unsigned long)(
  1184. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1185. / link_desc_size;
  1186. unsigned long paddr = (unsigned long)(
  1187. soc->link_desc_banks[i].base_paddr);
  1188. while (num_entries && (desc = hal_srng_src_get_next(
  1189. soc->hal_soc,
  1190. soc->wbm_idle_link_ring.hal_srng))) {
  1191. hal_set_link_desc_addr(desc,
  1192. LINK_DESC_COOKIE(desc_id, i), paddr);
  1193. num_entries--;
  1194. desc_id++;
  1195. paddr += link_desc_size;
  1196. }
  1197. }
  1198. hal_srng_access_end_unlocked(soc->hal_soc,
  1199. soc->wbm_idle_link_ring.hal_srng);
  1200. } else {
  1201. uint32_t num_scatter_bufs;
  1202. uint32_t num_entries_per_buf;
  1203. uint32_t rem_entries;
  1204. uint8_t *scatter_buf_ptr;
  1205. uint16_t scatter_buf_num;
  1206. soc->wbm_idle_scatter_buf_size =
  1207. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1208. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1209. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1210. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1211. soc->hal_soc, total_mem_size,
  1212. soc->wbm_idle_scatter_buf_size);
  1213. for (i = 0; i < num_scatter_bufs; i++) {
  1214. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1215. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1216. soc->wbm_idle_scatter_buf_size,
  1217. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1218. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1219. QDF_TRACE(QDF_MODULE_ID_DP,
  1220. QDF_TRACE_LEVEL_ERROR,
  1221. FL("Scatter list memory alloc failed"));
  1222. goto fail;
  1223. }
  1224. }
  1225. /* Populate idle list scatter buffers with link descriptor
  1226. * pointers
  1227. */
  1228. scatter_buf_num = 0;
  1229. scatter_buf_ptr = (uint8_t *)(
  1230. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1231. rem_entries = num_entries_per_buf;
  1232. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1233. soc->link_desc_banks[i].base_paddr; i++) {
  1234. uint32_t num_link_descs =
  1235. (soc->link_desc_banks[i].size -
  1236. ((unsigned long)(
  1237. soc->link_desc_banks[i].base_vaddr) -
  1238. (unsigned long)(
  1239. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1240. / link_desc_size;
  1241. unsigned long paddr = (unsigned long)(
  1242. soc->link_desc_banks[i].base_paddr);
  1243. while (num_link_descs) {
  1244. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1245. LINK_DESC_COOKIE(desc_id, i), paddr);
  1246. num_link_descs--;
  1247. desc_id++;
  1248. paddr += link_desc_size;
  1249. rem_entries--;
  1250. if (rem_entries) {
  1251. scatter_buf_ptr += entry_size;
  1252. } else {
  1253. rem_entries = num_entries_per_buf;
  1254. scatter_buf_num++;
  1255. if (scatter_buf_num >= num_scatter_bufs)
  1256. break;
  1257. scatter_buf_ptr = (uint8_t *)(
  1258. soc->wbm_idle_scatter_buf_base_vaddr[
  1259. scatter_buf_num]);
  1260. }
  1261. }
  1262. }
  1263. /* Setup link descriptor idle list in HW */
  1264. hal_setup_link_idle_list(soc->hal_soc,
  1265. soc->wbm_idle_scatter_buf_base_paddr,
  1266. soc->wbm_idle_scatter_buf_base_vaddr,
  1267. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1268. (uint32_t)(scatter_buf_ptr -
  1269. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1270. scatter_buf_num-1])), total_link_descs);
  1271. }
  1272. return 0;
  1273. fail:
  1274. if (soc->wbm_idle_link_ring.hal_srng) {
  1275. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1276. WBM_IDLE_LINK, 0);
  1277. }
  1278. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1279. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1280. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1281. soc->wbm_idle_scatter_buf_size,
  1282. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1283. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1284. }
  1285. }
  1286. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1287. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1288. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1289. soc->link_desc_banks[i].size,
  1290. soc->link_desc_banks[i].base_vaddr_unaligned,
  1291. soc->link_desc_banks[i].base_paddr_unaligned,
  1292. 0);
  1293. }
  1294. }
  1295. return QDF_STATUS_E_FAILURE;
  1296. }
  1297. /*
  1298. * Free link descriptor pool that was setup HW
  1299. */
  1300. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1301. {
  1302. int i;
  1303. if (soc->wbm_idle_link_ring.hal_srng) {
  1304. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1305. WBM_IDLE_LINK, 0);
  1306. }
  1307. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1308. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1309. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1310. soc->wbm_idle_scatter_buf_size,
  1311. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1312. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1313. }
  1314. }
  1315. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1316. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1317. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1318. soc->link_desc_banks[i].size,
  1319. soc->link_desc_banks[i].base_vaddr_unaligned,
  1320. soc->link_desc_banks[i].base_paddr_unaligned,
  1321. 0);
  1322. }
  1323. }
  1324. }
  1325. /* TODO: Following should be configurable */
  1326. #define WBM_RELEASE_RING_SIZE 64
  1327. #define TCL_CMD_RING_SIZE 32
  1328. #define TCL_STATUS_RING_SIZE 32
  1329. #if defined(QCA_WIFI_QCA6290)
  1330. #define REO_DST_RING_SIZE 1024
  1331. #else
  1332. #define REO_DST_RING_SIZE 2048
  1333. #endif
  1334. #define REO_REINJECT_RING_SIZE 32
  1335. #define RX_RELEASE_RING_SIZE 1024
  1336. #define REO_EXCEPTION_RING_SIZE 128
  1337. #define REO_CMD_RING_SIZE 32
  1338. #define REO_STATUS_RING_SIZE 32
  1339. #define RXDMA_BUF_RING_SIZE 1024
  1340. #define RXDMA_REFILL_RING_SIZE 2048
  1341. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1342. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1343. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1344. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1345. #define RXDMA_ERR_DST_RING_SIZE 1024
  1346. /*
  1347. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1348. * @soc: Datapath SOC handle
  1349. *
  1350. * This is a timer function used to age out stale WDS nodes from
  1351. * AST table
  1352. */
  1353. #ifdef FEATURE_WDS
  1354. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1355. {
  1356. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1357. struct dp_pdev *pdev;
  1358. struct dp_vdev *vdev;
  1359. struct dp_peer *peer;
  1360. struct dp_ast_entry *ase, *temp_ase;
  1361. int i;
  1362. qdf_spin_lock_bh(&soc->ast_lock);
  1363. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1364. pdev = soc->pdev_list[i];
  1365. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1366. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1367. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1368. /*
  1369. * Do not expire static ast entries
  1370. */
  1371. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1372. continue;
  1373. if (ase->is_active) {
  1374. ase->is_active = FALSE;
  1375. continue;
  1376. }
  1377. DP_STATS_INC(soc, ast.aged_out, 1);
  1378. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1379. pdev->osif_pdev,
  1380. ase->mac_addr.raw);
  1381. dp_peer_del_ast(soc, ase);
  1382. }
  1383. }
  1384. }
  1385. }
  1386. qdf_spin_unlock_bh(&soc->ast_lock);
  1387. if (qdf_atomic_read(&soc->cmn_init_done))
  1388. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1389. }
  1390. /*
  1391. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1392. * @soc: Datapath SOC handle
  1393. *
  1394. * Return: None
  1395. */
  1396. static void dp_soc_wds_attach(struct dp_soc *soc)
  1397. {
  1398. qdf_spinlock_create(&soc->ast_lock);
  1399. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1400. dp_wds_aging_timer_fn, (void *)soc,
  1401. QDF_TIMER_TYPE_WAKE_APPS);
  1402. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1403. }
  1404. /*
  1405. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1406. * @txrx_soc: DP SOC handle
  1407. *
  1408. * Return: None
  1409. */
  1410. static void dp_soc_wds_detach(struct dp_soc *soc)
  1411. {
  1412. qdf_timer_stop(&soc->wds_aging_timer);
  1413. qdf_timer_free(&soc->wds_aging_timer);
  1414. qdf_spinlock_destroy(&soc->ast_lock);
  1415. }
  1416. #else
  1417. static void dp_soc_wds_attach(struct dp_soc *soc)
  1418. {
  1419. }
  1420. static void dp_soc_wds_detach(struct dp_soc *soc)
  1421. {
  1422. }
  1423. #endif
  1424. /*
  1425. * dp_soc_reset_ring_map() - Reset cpu ring map
  1426. * @soc: Datapath soc handler
  1427. *
  1428. * This api resets the default cpu ring map
  1429. */
  1430. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1431. {
  1432. uint8_t i;
  1433. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1434. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1435. if (nss_config == 1) {
  1436. /*
  1437. * Setting Tx ring map for one nss offloaded radio
  1438. */
  1439. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1440. } else if (nss_config == 2) {
  1441. /*
  1442. * Setting Tx ring for two nss offloaded radios
  1443. */
  1444. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1445. } else {
  1446. /*
  1447. * Setting Tx ring map for all nss offloaded radios
  1448. */
  1449. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1450. }
  1451. }
  1452. }
  1453. #ifdef IPA_OFFLOAD
  1454. /**
  1455. * dp_reo_remap_config() - configure reo remap register value based
  1456. * nss configuration.
  1457. * based on offload_radio value below remap configuration
  1458. * get applied.
  1459. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1460. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1461. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1462. * 3 - both Radios handled by NSS (remap not required)
  1463. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1464. *
  1465. * @remap1: output parameter indicates reo remap 1 register value
  1466. * @remap2: output parameter indicates reo remap 2 register value
  1467. * Return: bool type, true if remap is configured else false.
  1468. */
  1469. static bool dp_reo_remap_config(struct dp_soc *soc,
  1470. uint32_t *remap1,
  1471. uint32_t *remap2)
  1472. {
  1473. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1474. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1475. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1476. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1477. return true;
  1478. }
  1479. #else
  1480. static bool dp_reo_remap_config(struct dp_soc *soc,
  1481. uint32_t *remap1,
  1482. uint32_t *remap2)
  1483. {
  1484. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1485. switch (offload_radio) {
  1486. case 0:
  1487. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1488. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1489. (0x3 << 18) | (0x4 << 21)) << 8;
  1490. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1491. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1492. (0x3 << 18) | (0x4 << 21)) << 8;
  1493. break;
  1494. case 1:
  1495. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1496. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1497. (0x2 << 18) | (0x3 << 21)) << 8;
  1498. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1499. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1500. (0x4 << 18) | (0x2 << 21)) << 8;
  1501. break;
  1502. case 2:
  1503. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1504. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1505. (0x1 << 18) | (0x3 << 21)) << 8;
  1506. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1507. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1508. (0x4 << 18) | (0x1 << 21)) << 8;
  1509. break;
  1510. case 3:
  1511. /* return false if both radios are offloaded to NSS */
  1512. return false;
  1513. }
  1514. return true;
  1515. }
  1516. #endif
  1517. /*
  1518. * dp_soc_cmn_setup() - Common SoC level initializion
  1519. * @soc: Datapath SOC handle
  1520. *
  1521. * This is an internal function used to setup common SOC data structures,
  1522. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1523. */
  1524. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1525. {
  1526. int i;
  1527. struct hal_reo_params reo_params;
  1528. int tx_ring_size;
  1529. int tx_comp_ring_size;
  1530. if (qdf_atomic_read(&soc->cmn_init_done))
  1531. return 0;
  1532. if (dp_peer_find_attach(soc))
  1533. goto fail0;
  1534. if (dp_hw_link_desc_pool_setup(soc))
  1535. goto fail1;
  1536. /* Setup SRNG rings */
  1537. /* Common rings */
  1538. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1539. WBM_RELEASE_RING_SIZE)) {
  1540. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1541. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1542. goto fail1;
  1543. }
  1544. soc->num_tcl_data_rings = 0;
  1545. /* Tx data rings */
  1546. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1547. soc->num_tcl_data_rings =
  1548. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1549. tx_comp_ring_size =
  1550. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1551. tx_ring_size =
  1552. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1553. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1554. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1555. TCL_DATA, i, 0, tx_ring_size)) {
  1556. QDF_TRACE(QDF_MODULE_ID_DP,
  1557. QDF_TRACE_LEVEL_ERROR,
  1558. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1559. goto fail1;
  1560. }
  1561. /*
  1562. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1563. * count
  1564. */
  1565. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1566. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1567. QDF_TRACE(QDF_MODULE_ID_DP,
  1568. QDF_TRACE_LEVEL_ERROR,
  1569. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1570. goto fail1;
  1571. }
  1572. }
  1573. } else {
  1574. /* This will be incremented during per pdev ring setup */
  1575. soc->num_tcl_data_rings = 0;
  1576. }
  1577. if (dp_tx_soc_attach(soc)) {
  1578. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1579. FL("dp_tx_soc_attach failed"));
  1580. goto fail1;
  1581. }
  1582. /* TCL command and status rings */
  1583. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1584. TCL_CMD_RING_SIZE)) {
  1585. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1586. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1587. goto fail1;
  1588. }
  1589. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1590. TCL_STATUS_RING_SIZE)) {
  1591. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1592. FL("dp_srng_setup failed for tcl_status_ring"));
  1593. goto fail1;
  1594. }
  1595. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1596. * descriptors
  1597. */
  1598. /* Rx data rings */
  1599. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1600. soc->num_reo_dest_rings =
  1601. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1602. QDF_TRACE(QDF_MODULE_ID_DP,
  1603. QDF_TRACE_LEVEL_ERROR,
  1604. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1605. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1606. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1607. i, 0, REO_DST_RING_SIZE)) {
  1608. QDF_TRACE(QDF_MODULE_ID_DP,
  1609. QDF_TRACE_LEVEL_ERROR,
  1610. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1611. goto fail1;
  1612. }
  1613. }
  1614. } else {
  1615. /* This will be incremented during per pdev ring setup */
  1616. soc->num_reo_dest_rings = 0;
  1617. }
  1618. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1619. /* REO reinjection ring */
  1620. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1621. REO_REINJECT_RING_SIZE)) {
  1622. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1623. FL("dp_srng_setup failed for reo_reinject_ring"));
  1624. goto fail1;
  1625. }
  1626. /* Rx release ring */
  1627. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1628. RX_RELEASE_RING_SIZE)) {
  1629. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1630. FL("dp_srng_setup failed for rx_rel_ring"));
  1631. goto fail1;
  1632. }
  1633. /* Rx exception ring */
  1634. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1635. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1637. FL("dp_srng_setup failed for reo_exception_ring"));
  1638. goto fail1;
  1639. }
  1640. /* REO command and status rings */
  1641. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1642. REO_CMD_RING_SIZE)) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1644. FL("dp_srng_setup failed for reo_cmd_ring"));
  1645. goto fail1;
  1646. }
  1647. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1648. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1649. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1650. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1651. REO_STATUS_RING_SIZE)) {
  1652. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1653. FL("dp_srng_setup failed for reo_status_ring"));
  1654. goto fail1;
  1655. }
  1656. dp_soc_wds_attach(soc);
  1657. /* Reset the cpu ring map if radio is NSS offloaded */
  1658. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1659. dp_soc_reset_cpu_ring_map(soc);
  1660. }
  1661. /* Setup HW REO */
  1662. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1663. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1664. /*
  1665. * Reo ring remap is not required if both radios
  1666. * are offloaded to NSS
  1667. */
  1668. if (!dp_reo_remap_config(soc,
  1669. &reo_params.remap1,
  1670. &reo_params.remap2))
  1671. goto out;
  1672. reo_params.rx_hash_enabled = true;
  1673. }
  1674. out:
  1675. hal_reo_setup(soc->hal_soc, &reo_params);
  1676. qdf_atomic_set(&soc->cmn_init_done, 1);
  1677. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1678. return 0;
  1679. fail1:
  1680. /*
  1681. * Cleanup will be done as part of soc_detach, which will
  1682. * be called on pdev attach failure
  1683. */
  1684. fail0:
  1685. return QDF_STATUS_E_FAILURE;
  1686. }
  1687. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1688. static void dp_lro_hash_setup(struct dp_soc *soc)
  1689. {
  1690. struct cdp_lro_hash_config lro_hash;
  1691. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1692. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1693. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1694. FL("LRO disabled RX hash disabled"));
  1695. return;
  1696. }
  1697. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1698. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1699. lro_hash.lro_enable = 1;
  1700. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1701. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1702. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1703. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1704. }
  1705. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1706. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1707. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1708. LRO_IPV4_SEED_ARR_SZ));
  1709. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1710. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1711. LRO_IPV6_SEED_ARR_SZ));
  1712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1713. "lro_hash: lro_enable: 0x%x"
  1714. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1715. lro_hash.lro_enable, lro_hash.tcp_flag,
  1716. lro_hash.tcp_flag_mask);
  1717. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1718. FL("lro_hash: toeplitz_hash_ipv4:"));
  1719. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1720. QDF_TRACE_LEVEL_ERROR,
  1721. (void *)lro_hash.toeplitz_hash_ipv4,
  1722. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1723. LRO_IPV4_SEED_ARR_SZ));
  1724. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1725. FL("lro_hash: toeplitz_hash_ipv6:"));
  1726. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1727. QDF_TRACE_LEVEL_ERROR,
  1728. (void *)lro_hash.toeplitz_hash_ipv6,
  1729. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1730. LRO_IPV6_SEED_ARR_SZ));
  1731. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1732. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1733. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1734. (soc->osif_soc, &lro_hash);
  1735. }
  1736. /*
  1737. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1738. * @soc: data path SoC handle
  1739. * @pdev: Physical device handle
  1740. *
  1741. * Return: 0 - success, > 0 - failure
  1742. */
  1743. #ifdef QCA_HOST2FW_RXBUF_RING
  1744. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1745. struct dp_pdev *pdev)
  1746. {
  1747. int max_mac_rings =
  1748. wlan_cfg_get_num_mac_rings
  1749. (pdev->wlan_cfg_ctx);
  1750. int i;
  1751. for (i = 0; i < max_mac_rings; i++) {
  1752. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1753. "%s: pdev_id %d mac_id %d\n",
  1754. __func__, pdev->pdev_id, i);
  1755. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1756. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1757. QDF_TRACE(QDF_MODULE_ID_DP,
  1758. QDF_TRACE_LEVEL_ERROR,
  1759. FL("failed rx mac ring setup"));
  1760. return QDF_STATUS_E_FAILURE;
  1761. }
  1762. }
  1763. return QDF_STATUS_SUCCESS;
  1764. }
  1765. #else
  1766. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1767. struct dp_pdev *pdev)
  1768. {
  1769. return QDF_STATUS_SUCCESS;
  1770. }
  1771. #endif
  1772. /**
  1773. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1774. * @pdev - DP_PDEV handle
  1775. *
  1776. * Return: void
  1777. */
  1778. static inline void
  1779. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1780. {
  1781. uint8_t map_id;
  1782. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1783. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1784. sizeof(default_dscp_tid_map));
  1785. }
  1786. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1787. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1788. pdev->dscp_tid_map[map_id],
  1789. map_id);
  1790. }
  1791. }
  1792. /*
  1793. * dp_reset_intr_mask() - reset interrupt mask
  1794. * @dp_soc - DP Soc handle
  1795. * @dp_pdev - DP pdev handle
  1796. *
  1797. * Return: Return void
  1798. */
  1799. static inline
  1800. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1801. {
  1802. /*
  1803. * We will set the interrupt mask to zero for NSS offloaded radio
  1804. */
  1805. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1806. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1807. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1808. }
  1809. /*
  1810. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1811. * @soc: data path SoC handle
  1812. *
  1813. * Return: none
  1814. */
  1815. #ifdef IPA_OFFLOAD
  1816. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1817. struct dp_pdev *pdev)
  1818. {
  1819. void *hal_srng;
  1820. struct hal_srng_params srng_params;
  1821. qdf_dma_addr_t hp_addr, tp_addr;
  1822. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1823. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1824. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1825. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1826. srng_params.ring_base_paddr;
  1827. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1828. srng_params.ring_base_vaddr;
  1829. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1830. srng_params.num_entries * srng_params.entry_size;
  1831. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1832. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1833. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1834. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1835. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1836. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1837. srng_params.ring_base_paddr;
  1838. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1839. srng_params.ring_base_vaddr;
  1840. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1841. srng_params.num_entries * srng_params.entry_size;
  1842. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1843. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1844. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1845. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1846. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1847. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1848. srng_params.ring_base_paddr;
  1849. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1850. srng_params.ring_base_vaddr;
  1851. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1852. srng_params.num_entries * srng_params.entry_size;
  1853. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1854. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1855. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1856. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1857. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1858. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1859. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1860. __func__);
  1861. return -EFAULT;
  1862. }
  1863. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1864. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1865. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1866. srng_params.ring_base_paddr;
  1867. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1868. srng_params.ring_base_vaddr;
  1869. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1870. srng_params.num_entries * srng_params.entry_size;
  1871. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1872. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1873. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1874. "%s: ring_base_paddr:%pK, ring_base_vaddr:%pK"
  1875. "_entries:%d, hp_addr:%pK\n",
  1876. __func__,
  1877. (void *)srng_params.ring_base_paddr,
  1878. (void *)srng_params.ring_base_vaddr,
  1879. srng_params.num_entries,
  1880. (void *)hp_addr);
  1881. return 0;
  1882. }
  1883. #else
  1884. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1885. struct dp_pdev *pdev)
  1886. {
  1887. return 0;
  1888. }
  1889. #endif
  1890. /*
  1891. * dp_pdev_attach_wifi3() - attach txrx pdev
  1892. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1893. * @txrx_soc: Datapath SOC handle
  1894. * @htc_handle: HTC handle for host-target interface
  1895. * @qdf_osdev: QDF OS device
  1896. * @pdev_id: PDEV ID
  1897. *
  1898. * Return: DP PDEV handle on success, NULL on failure
  1899. */
  1900. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1901. struct cdp_cfg *ctrl_pdev,
  1902. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1903. {
  1904. int tx_ring_size;
  1905. int tx_comp_ring_size;
  1906. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1907. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1908. if (!pdev) {
  1909. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1910. FL("DP PDEV memory allocation failed"));
  1911. goto fail0;
  1912. }
  1913. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1914. if (!pdev->wlan_cfg_ctx) {
  1915. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1916. FL("pdev cfg_attach failed"));
  1917. qdf_mem_free(pdev);
  1918. goto fail0;
  1919. }
  1920. /*
  1921. * set nss pdev config based on soc config
  1922. */
  1923. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1924. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1925. pdev->soc = soc;
  1926. pdev->osif_pdev = ctrl_pdev;
  1927. pdev->pdev_id = pdev_id;
  1928. soc->pdev_list[pdev_id] = pdev;
  1929. soc->pdev_count++;
  1930. TAILQ_INIT(&pdev->vdev_list);
  1931. pdev->vdev_count = 0;
  1932. qdf_spinlock_create(&pdev->tx_mutex);
  1933. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1934. TAILQ_INIT(&pdev->neighbour_peers_list);
  1935. if (dp_soc_cmn_setup(soc)) {
  1936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1937. FL("dp_soc_cmn_setup failed"));
  1938. goto fail1;
  1939. }
  1940. /* Setup per PDEV TCL rings if configured */
  1941. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1942. tx_ring_size =
  1943. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1944. tx_comp_ring_size =
  1945. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1946. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1947. pdev_id, pdev_id, tx_ring_size)) {
  1948. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1949. FL("dp_srng_setup failed for tcl_data_ring"));
  1950. goto fail1;
  1951. }
  1952. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1953. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1954. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1955. FL("dp_srng_setup failed for tx_comp_ring"));
  1956. goto fail1;
  1957. }
  1958. soc->num_tcl_data_rings++;
  1959. }
  1960. /* Tx specific init */
  1961. if (dp_tx_pdev_attach(pdev)) {
  1962. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1963. FL("dp_tx_pdev_attach failed"));
  1964. goto fail1;
  1965. }
  1966. /* Setup per PDEV REO rings if configured */
  1967. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1968. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1969. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1970. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1971. FL("dp_srng_setup failed for reo_dest_ringn"));
  1972. goto fail1;
  1973. }
  1974. soc->num_reo_dest_rings++;
  1975. }
  1976. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1977. RXDMA_REFILL_RING_SIZE)) {
  1978. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1979. FL("dp_srng_setup failed rx refill ring"));
  1980. goto fail1;
  1981. }
  1982. if (dp_rxdma_ring_setup(soc, pdev)) {
  1983. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1984. FL("RXDMA ring config failed"));
  1985. goto fail1;
  1986. }
  1987. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1988. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1989. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1990. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1991. goto fail1;
  1992. }
  1993. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1994. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1995. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1996. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1997. goto fail1;
  1998. }
  1999. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2000. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2001. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2002. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2003. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2004. goto fail1;
  2005. }
  2006. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2007. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2008. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2009. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2010. goto fail1;
  2011. }
  2012. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2013. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2014. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2015. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2016. goto fail1;
  2017. }
  2018. if (dp_ipa_ring_resource_setup(soc, pdev))
  2019. goto fail1;
  2020. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2021. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2022. "%s: dp_ipa_uc_attach failed\n", __func__);
  2023. goto fail1;
  2024. }
  2025. /* Rx specific init */
  2026. if (dp_rx_pdev_attach(pdev)) {
  2027. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2028. FL("dp_rx_pdev_attach failed "));
  2029. goto fail0;
  2030. }
  2031. DP_STATS_INIT(pdev);
  2032. #ifndef CONFIG_WIN
  2033. /* MCL */
  2034. dp_local_peer_id_pool_init(pdev);
  2035. #endif
  2036. dp_dscp_tid_map_setup(pdev);
  2037. /* Rx monitor mode specific init */
  2038. if (dp_rx_pdev_mon_attach(pdev)) {
  2039. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2040. "dp_rx_pdev_attach failed\n");
  2041. goto fail1;
  2042. }
  2043. if (dp_wdi_event_attach(pdev)) {
  2044. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2045. "dp_wdi_evet_attach failed\n");
  2046. goto fail1;
  2047. }
  2048. /* set the reo destination during initialization */
  2049. pdev->reo_dest = pdev->pdev_id + 1;
  2050. /*
  2051. * reset the interrupt mask for offloaded radio
  2052. */
  2053. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2054. dp_soc_reset_intr_mask(soc, pdev);
  2055. }
  2056. return (struct cdp_pdev *)pdev;
  2057. fail1:
  2058. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2059. fail0:
  2060. return NULL;
  2061. }
  2062. /*
  2063. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2064. * @soc: data path SoC handle
  2065. * @pdev: Physical device handle
  2066. *
  2067. * Return: void
  2068. */
  2069. #ifdef QCA_HOST2FW_RXBUF_RING
  2070. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2071. struct dp_pdev *pdev)
  2072. {
  2073. int max_mac_rings =
  2074. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2075. int i;
  2076. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2077. max_mac_rings : MAX_RX_MAC_RINGS;
  2078. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2079. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2080. RXDMA_BUF, 1);
  2081. }
  2082. #else
  2083. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2084. struct dp_pdev *pdev)
  2085. {
  2086. }
  2087. #endif
  2088. /*
  2089. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2090. * @pdev: device object
  2091. *
  2092. * Return: void
  2093. */
  2094. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2095. {
  2096. struct dp_neighbour_peer *peer = NULL;
  2097. struct dp_neighbour_peer *temp_peer = NULL;
  2098. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2099. neighbour_peer_list_elem, temp_peer) {
  2100. /* delete this peer from the list */
  2101. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2102. peer, neighbour_peer_list_elem);
  2103. qdf_mem_free(peer);
  2104. }
  2105. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2106. }
  2107. /*
  2108. * dp_pdev_detach_wifi3() - detach txrx pdev
  2109. * @txrx_pdev: Datapath PDEV handle
  2110. * @force: Force detach
  2111. *
  2112. */
  2113. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2114. {
  2115. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2116. struct dp_soc *soc = pdev->soc;
  2117. dp_wdi_event_detach(pdev);
  2118. dp_tx_pdev_detach(pdev);
  2119. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2120. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2121. TCL_DATA, pdev->pdev_id);
  2122. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2123. WBM2SW_RELEASE, pdev->pdev_id);
  2124. }
  2125. dp_rx_pdev_detach(pdev);
  2126. dp_rx_pdev_mon_detach(pdev);
  2127. dp_neighbour_peers_detach(pdev);
  2128. qdf_spinlock_destroy(&pdev->tx_mutex);
  2129. dp_ipa_uc_detach(soc, pdev);
  2130. /* Cleanup per PDEV REO rings if configured */
  2131. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2132. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2133. REO_DST, pdev->pdev_id);
  2134. }
  2135. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2136. dp_rxdma_ring_cleanup(soc, pdev);
  2137. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2138. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2139. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2140. RXDMA_MONITOR_STATUS, 0);
  2141. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2142. RXDMA_MONITOR_DESC, 0);
  2143. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2144. soc->pdev_list[pdev->pdev_id] = NULL;
  2145. soc->pdev_count--;
  2146. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2147. qdf_mem_free(pdev);
  2148. }
  2149. /*
  2150. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2151. * @soc: DP SOC handle
  2152. */
  2153. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2154. {
  2155. struct reo_desc_list_node *desc;
  2156. struct dp_rx_tid *rx_tid;
  2157. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2158. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2159. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2160. rx_tid = &desc->rx_tid;
  2161. qdf_mem_unmap_nbytes_single(soc->osdev,
  2162. rx_tid->hw_qdesc_paddr,
  2163. QDF_DMA_BIDIRECTIONAL,
  2164. rx_tid->hw_qdesc_alloc_size);
  2165. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2166. qdf_mem_free(desc);
  2167. }
  2168. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2169. qdf_list_destroy(&soc->reo_desc_freelist);
  2170. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2171. }
  2172. /*
  2173. * dp_soc_detach_wifi3() - Detach txrx SOC
  2174. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2175. */
  2176. static void dp_soc_detach_wifi3(void *txrx_soc)
  2177. {
  2178. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2179. int i;
  2180. qdf_atomic_set(&soc->cmn_init_done, 0);
  2181. qdf_flush_work(0, &soc->htt_stats.work);
  2182. qdf_disable_work(0, &soc->htt_stats.work);
  2183. /* Free pending htt stats messages */
  2184. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2185. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2186. if (soc->pdev_list[i])
  2187. dp_pdev_detach_wifi3(
  2188. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2189. }
  2190. dp_peer_find_detach(soc);
  2191. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2192. * SW descriptors
  2193. */
  2194. /* Free the ring memories */
  2195. /* Common rings */
  2196. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2197. dp_tx_soc_detach(soc);
  2198. /* Tx data rings */
  2199. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2200. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2201. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2202. TCL_DATA, i);
  2203. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2204. WBM2SW_RELEASE, i);
  2205. }
  2206. }
  2207. /* TCL command and status rings */
  2208. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2209. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2210. /* Rx data rings */
  2211. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2212. soc->num_reo_dest_rings =
  2213. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2214. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2215. /* TODO: Get number of rings and ring sizes
  2216. * from wlan_cfg
  2217. */
  2218. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2219. REO_DST, i);
  2220. }
  2221. }
  2222. /* REO reinjection ring */
  2223. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2224. /* Rx release ring */
  2225. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2226. /* Rx exception ring */
  2227. /* TODO: Better to store ring_type and ring_num in
  2228. * dp_srng during setup
  2229. */
  2230. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2231. /* REO command and status rings */
  2232. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2233. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2234. dp_hw_link_desc_pool_cleanup(soc);
  2235. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2236. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2237. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2238. htt_soc_detach(soc->htt_handle);
  2239. dp_reo_cmdlist_destroy(soc);
  2240. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2241. dp_reo_desc_freelist_destroy(soc);
  2242. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2243. dp_soc_wds_detach(soc);
  2244. qdf_mem_free(soc);
  2245. }
  2246. /*
  2247. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2248. * @soc: data path SoC handle
  2249. * @pdev: physical device handle
  2250. *
  2251. * Return: void
  2252. */
  2253. #ifdef IPA_OFFLOAD
  2254. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2255. struct dp_pdev *pdev)
  2256. {
  2257. htt_srng_setup(soc->htt_handle, 0,
  2258. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2259. }
  2260. #else
  2261. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2262. struct dp_pdev *pdev)
  2263. {
  2264. }
  2265. #endif
  2266. /*
  2267. * dp_rxdma_ring_config() - configure the RX DMA rings
  2268. *
  2269. * This function is used to configure the MAC rings.
  2270. * On MCL host provides buffers in Host2FW ring
  2271. * FW refills (copies) buffers to the ring and updates
  2272. * ring_idx in register
  2273. *
  2274. * @soc: data path SoC handle
  2275. *
  2276. * Return: void
  2277. */
  2278. #ifdef QCA_HOST2FW_RXBUF_RING
  2279. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2280. {
  2281. int i;
  2282. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2283. struct dp_pdev *pdev = soc->pdev_list[i];
  2284. if (pdev) {
  2285. int mac_id = 0;
  2286. int j;
  2287. bool dbs_enable = 0;
  2288. int max_mac_rings =
  2289. wlan_cfg_get_num_mac_rings
  2290. (pdev->wlan_cfg_ctx);
  2291. htt_srng_setup(soc->htt_handle, 0,
  2292. pdev->rx_refill_buf_ring.hal_srng,
  2293. RXDMA_BUF);
  2294. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2295. if (soc->cdp_soc.ol_ops->
  2296. is_hw_dbs_2x2_capable) {
  2297. dbs_enable = soc->cdp_soc.ol_ops->
  2298. is_hw_dbs_2x2_capable(soc->psoc);
  2299. }
  2300. if (dbs_enable) {
  2301. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2302. QDF_TRACE_LEVEL_ERROR,
  2303. FL("DBS enabled max_mac_rings %d\n"),
  2304. max_mac_rings);
  2305. } else {
  2306. max_mac_rings = 1;
  2307. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2308. QDF_TRACE_LEVEL_ERROR,
  2309. FL("DBS disabled, max_mac_rings %d\n"),
  2310. max_mac_rings);
  2311. }
  2312. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2313. FL("pdev_id %d max_mac_rings %d\n"),
  2314. pdev->pdev_id, max_mac_rings);
  2315. for (j = 0; j < max_mac_rings; j++) {
  2316. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2317. QDF_TRACE_LEVEL_ERROR,
  2318. FL("mac_id %d\n"), mac_id);
  2319. htt_srng_setup(soc->htt_handle, mac_id,
  2320. pdev->rx_mac_buf_ring[j]
  2321. .hal_srng,
  2322. RXDMA_BUF);
  2323. mac_id++;
  2324. }
  2325. /* Configure monitor mode rings */
  2326. htt_srng_setup(soc->htt_handle, i,
  2327. pdev->rxdma_mon_buf_ring.hal_srng,
  2328. RXDMA_MONITOR_BUF);
  2329. htt_srng_setup(soc->htt_handle, i,
  2330. pdev->rxdma_mon_dst_ring.hal_srng,
  2331. RXDMA_MONITOR_DST);
  2332. htt_srng_setup(soc->htt_handle, i,
  2333. pdev->rxdma_mon_status_ring.hal_srng,
  2334. RXDMA_MONITOR_STATUS);
  2335. htt_srng_setup(soc->htt_handle, i,
  2336. pdev->rxdma_mon_desc_ring.hal_srng,
  2337. RXDMA_MONITOR_DESC);
  2338. htt_srng_setup(soc->htt_handle, i,
  2339. pdev->rxdma_err_dst_ring.hal_srng,
  2340. RXDMA_DST);
  2341. }
  2342. }
  2343. }
  2344. #else
  2345. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2346. {
  2347. int i;
  2348. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2349. struct dp_pdev *pdev = soc->pdev_list[i];
  2350. if (pdev) {
  2351. htt_srng_setup(soc->htt_handle, i,
  2352. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2353. htt_srng_setup(soc->htt_handle, i,
  2354. pdev->rxdma_mon_buf_ring.hal_srng,
  2355. RXDMA_MONITOR_BUF);
  2356. htt_srng_setup(soc->htt_handle, i,
  2357. pdev->rxdma_mon_dst_ring.hal_srng,
  2358. RXDMA_MONITOR_DST);
  2359. htt_srng_setup(soc->htt_handle, i,
  2360. pdev->rxdma_mon_status_ring.hal_srng,
  2361. RXDMA_MONITOR_STATUS);
  2362. htt_srng_setup(soc->htt_handle, i,
  2363. pdev->rxdma_mon_desc_ring.hal_srng,
  2364. RXDMA_MONITOR_DESC);
  2365. htt_srng_setup(soc->htt_handle, i,
  2366. pdev->rxdma_err_dst_ring.hal_srng,
  2367. RXDMA_DST);
  2368. }
  2369. }
  2370. }
  2371. #endif
  2372. /*
  2373. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2374. * @txrx_soc: Datapath SOC handle
  2375. */
  2376. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2377. {
  2378. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2379. htt_soc_attach_target(soc->htt_handle);
  2380. dp_rxdma_ring_config(soc);
  2381. DP_STATS_INIT(soc);
  2382. /* initialize work queue for stats processing */
  2383. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2384. return 0;
  2385. }
  2386. /*
  2387. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2388. * @txrx_soc: Datapath SOC handle
  2389. */
  2390. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2391. {
  2392. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2393. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2394. }
  2395. /*
  2396. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2397. * @txrx_soc: Datapath SOC handle
  2398. * @nss_cfg: nss config
  2399. */
  2400. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2401. {
  2402. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2403. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2404. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2405. FL("nss-wifi<0> nss config is enabled"));
  2406. }
  2407. /*
  2408. * dp_vdev_attach_wifi3() - attach txrx vdev
  2409. * @txrx_pdev: Datapath PDEV handle
  2410. * @vdev_mac_addr: MAC address of the virtual interface
  2411. * @vdev_id: VDEV Id
  2412. * @wlan_op_mode: VDEV operating mode
  2413. *
  2414. * Return: DP VDEV handle on success, NULL on failure
  2415. */
  2416. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2417. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2418. {
  2419. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2420. struct dp_soc *soc = pdev->soc;
  2421. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2422. int tx_ring_size;
  2423. if (!vdev) {
  2424. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2425. FL("DP VDEV memory allocation failed"));
  2426. goto fail0;
  2427. }
  2428. vdev->pdev = pdev;
  2429. vdev->vdev_id = vdev_id;
  2430. vdev->opmode = op_mode;
  2431. vdev->osdev = soc->osdev;
  2432. vdev->osif_rx = NULL;
  2433. vdev->osif_rsim_rx_decap = NULL;
  2434. vdev->osif_get_key = NULL;
  2435. vdev->osif_rx_mon = NULL;
  2436. vdev->osif_tx_free_ext = NULL;
  2437. vdev->osif_vdev = NULL;
  2438. vdev->delete.pending = 0;
  2439. vdev->safemode = 0;
  2440. vdev->drop_unenc = 1;
  2441. #ifdef notyet
  2442. vdev->filters_num = 0;
  2443. #endif
  2444. qdf_mem_copy(
  2445. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2446. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2447. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2448. vdev->dscp_tid_map_id = 0;
  2449. vdev->mcast_enhancement_en = 0;
  2450. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2451. /* TODO: Initialize default HTT meta data that will be used in
  2452. * TCL descriptors for packets transmitted from this VDEV
  2453. */
  2454. TAILQ_INIT(&vdev->peer_list);
  2455. /* add this vdev into the pdev's list */
  2456. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2457. pdev->vdev_count++;
  2458. dp_tx_vdev_attach(vdev);
  2459. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2460. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2461. goto fail1;
  2462. if ((soc->intr_mode == DP_INTR_POLL) &&
  2463. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2464. if (pdev->vdev_count == 1)
  2465. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2466. }
  2467. dp_lro_hash_setup(soc);
  2468. /* LRO */
  2469. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2470. wlan_op_mode_sta == vdev->opmode)
  2471. vdev->lro_enable = true;
  2472. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2473. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2474. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2475. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2476. DP_STATS_INIT(vdev);
  2477. return (struct cdp_vdev *)vdev;
  2478. fail1:
  2479. dp_tx_vdev_detach(vdev);
  2480. qdf_mem_free(vdev);
  2481. fail0:
  2482. return NULL;
  2483. }
  2484. /**
  2485. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2486. * @vdev: Datapath VDEV handle
  2487. * @osif_vdev: OSIF vdev handle
  2488. * @txrx_ops: Tx and Rx operations
  2489. *
  2490. * Return: DP VDEV handle on success, NULL on failure
  2491. */
  2492. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2493. void *osif_vdev,
  2494. struct ol_txrx_ops *txrx_ops)
  2495. {
  2496. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2497. vdev->osif_vdev = osif_vdev;
  2498. vdev->osif_rx = txrx_ops->rx.rx;
  2499. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2500. vdev->osif_get_key = txrx_ops->get_key;
  2501. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2502. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2503. #ifdef notyet
  2504. #if ATH_SUPPORT_WAPI
  2505. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2506. #endif
  2507. #endif
  2508. #ifdef UMAC_SUPPORT_PROXY_ARP
  2509. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2510. #endif
  2511. vdev->me_convert = txrx_ops->me_convert;
  2512. /* TODO: Enable the following once Tx code is integrated */
  2513. txrx_ops->tx.tx = dp_tx_send;
  2514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2515. "DP Vdev Register success");
  2516. }
  2517. /*
  2518. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2519. * @txrx_vdev: Datapath VDEV handle
  2520. * @callback: Callback OL_IF on completion of detach
  2521. * @cb_context: Callback context
  2522. *
  2523. */
  2524. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2525. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2526. {
  2527. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2528. struct dp_pdev *pdev = vdev->pdev;
  2529. struct dp_soc *soc = pdev->soc;
  2530. /* preconditions */
  2531. qdf_assert(vdev);
  2532. /* remove the vdev from its parent pdev's list */
  2533. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2534. /*
  2535. * Use peer_ref_mutex while accessing peer_list, in case
  2536. * a peer is in the process of being removed from the list.
  2537. */
  2538. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2539. /* check that the vdev has no peers allocated */
  2540. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2541. /* debug print - will be removed later */
  2542. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2543. FL("not deleting vdev object %pK (%pM)"
  2544. "until deletion finishes for all its peers"),
  2545. vdev, vdev->mac_addr.raw);
  2546. /* indicate that the vdev needs to be deleted */
  2547. vdev->delete.pending = 1;
  2548. vdev->delete.callback = callback;
  2549. vdev->delete.context = cb_context;
  2550. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2551. return;
  2552. }
  2553. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2554. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2555. vdev->vdev_id);
  2556. dp_tx_vdev_detach(vdev);
  2557. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2558. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2559. qdf_mem_free(vdev);
  2560. if (callback)
  2561. callback(cb_context);
  2562. }
  2563. /*
  2564. * dp_peer_create_wifi3() - attach txrx peer
  2565. * @txrx_vdev: Datapath VDEV handle
  2566. * @peer_mac_addr: Peer MAC address
  2567. *
  2568. * Return: DP peeer handle on success, NULL on failure
  2569. */
  2570. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2571. uint8_t *peer_mac_addr)
  2572. {
  2573. struct dp_peer *peer;
  2574. int i;
  2575. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2576. struct dp_pdev *pdev;
  2577. struct dp_soc *soc;
  2578. /* preconditions */
  2579. qdf_assert(vdev);
  2580. qdf_assert(peer_mac_addr);
  2581. pdev = vdev->pdev;
  2582. soc = pdev->soc;
  2583. #ifdef notyet
  2584. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2585. soc->mempool_ol_ath_peer);
  2586. #else
  2587. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2588. #endif
  2589. if (!peer)
  2590. return NULL; /* failure */
  2591. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2592. TAILQ_INIT(&peer->ast_entry_list);
  2593. /* store provided params */
  2594. peer->vdev = vdev;
  2595. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2596. qdf_spinlock_create(&peer->peer_info_lock);
  2597. qdf_mem_copy(
  2598. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2599. /* TODO: See of rx_opt_proc is really required */
  2600. peer->rx_opt_proc = soc->rx_opt_proc;
  2601. /* initialize the peer_id */
  2602. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2603. peer->peer_ids[i] = HTT_INVALID_PEER;
  2604. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2605. qdf_atomic_init(&peer->ref_cnt);
  2606. /* keep one reference for attach */
  2607. qdf_atomic_inc(&peer->ref_cnt);
  2608. /* add this peer into the vdev's list */
  2609. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2610. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2611. /* TODO: See if hash based search is required */
  2612. dp_peer_find_hash_add(soc, peer);
  2613. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2614. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2615. vdev, peer, peer->mac_addr.raw,
  2616. qdf_atomic_read(&peer->ref_cnt));
  2617. /*
  2618. * For every peer MAp message search and set if bss_peer
  2619. */
  2620. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2622. "vdev bss_peer!!!!");
  2623. peer->bss_peer = 1;
  2624. vdev->vap_bss_peer = peer;
  2625. }
  2626. #ifndef CONFIG_WIN
  2627. dp_local_peer_id_alloc(pdev, peer);
  2628. #endif
  2629. DP_STATS_INIT(peer);
  2630. return (void *)peer;
  2631. }
  2632. /*
  2633. * dp_peer_setup_wifi3() - initialize the peer
  2634. * @vdev_hdl: virtual device object
  2635. * @peer: Peer object
  2636. *
  2637. * Return: void
  2638. */
  2639. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2640. {
  2641. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2642. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2643. struct dp_pdev *pdev;
  2644. struct dp_soc *soc;
  2645. bool hash_based = 0;
  2646. enum cdp_host_reo_dest_ring reo_dest;
  2647. /* preconditions */
  2648. qdf_assert(vdev);
  2649. qdf_assert(peer);
  2650. pdev = vdev->pdev;
  2651. soc = pdev->soc;
  2652. dp_peer_rx_init(pdev, peer);
  2653. peer->last_assoc_rcvd = 0;
  2654. peer->last_disassoc_rcvd = 0;
  2655. peer->last_deauth_rcvd = 0;
  2656. /*
  2657. * hash based steering is disabled for Radios which are offloaded
  2658. * to NSS
  2659. */
  2660. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2661. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2663. FL("hash based steering for pdev: %d is %d\n"),
  2664. pdev->pdev_id, hash_based);
  2665. if (!hash_based)
  2666. reo_dest = pdev->reo_dest;
  2667. else
  2668. reo_dest = 1;
  2669. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2670. /* TODO: Check the destination ring number to be passed to FW */
  2671. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2672. pdev->osif_pdev, peer->mac_addr.raw,
  2673. peer->vdev->vdev_id, hash_based, reo_dest);
  2674. }
  2675. return;
  2676. }
  2677. /*
  2678. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2679. * @vdev_handle: virtual device object
  2680. * @htt_pkt_type: type of pkt
  2681. *
  2682. * Return: void
  2683. */
  2684. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2685. enum htt_cmn_pkt_type val)
  2686. {
  2687. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2688. vdev->tx_encap_type = val;
  2689. }
  2690. /*
  2691. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2692. * @vdev_handle: virtual device object
  2693. * @htt_pkt_type: type of pkt
  2694. *
  2695. * Return: void
  2696. */
  2697. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2698. enum htt_cmn_pkt_type val)
  2699. {
  2700. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2701. vdev->rx_decap_type = val;
  2702. }
  2703. /*
  2704. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2705. * @pdev_handle: physical device object
  2706. * @val: reo destination ring index (1 - 4)
  2707. *
  2708. * Return: void
  2709. */
  2710. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2711. enum cdp_host_reo_dest_ring val)
  2712. {
  2713. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2714. if (pdev)
  2715. pdev->reo_dest = val;
  2716. }
  2717. /*
  2718. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2719. * @pdev_handle: physical device object
  2720. *
  2721. * Return: reo destination ring index
  2722. */
  2723. static enum cdp_host_reo_dest_ring
  2724. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2725. {
  2726. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2727. if (pdev)
  2728. return pdev->reo_dest;
  2729. else
  2730. return cdp_host_reo_dest_ring_unknown;
  2731. }
  2732. #ifdef QCA_SUPPORT_SON
  2733. static void dp_son_peer_authorize(struct dp_peer *peer)
  2734. {
  2735. struct dp_soc *soc;
  2736. soc = peer->vdev->pdev->soc;
  2737. peer->peer_bs_inact_flag = 0;
  2738. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2739. return;
  2740. }
  2741. #else
  2742. static void dp_son_peer_authorize(struct dp_peer *peer)
  2743. {
  2744. return;
  2745. }
  2746. #endif
  2747. /*
  2748. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2749. * @pdev_handle: device object
  2750. * @val: value to be set
  2751. *
  2752. * Return: void
  2753. */
  2754. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2755. uint32_t val)
  2756. {
  2757. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2758. /* Enable/Disable smart mesh filtering. This flag will be checked
  2759. * during rx processing to check if packets are from NAC clients.
  2760. */
  2761. pdev->filter_neighbour_peers = val;
  2762. return 0;
  2763. }
  2764. /*
  2765. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2766. * address for smart mesh filtering
  2767. * @pdev_handle: device object
  2768. * @cmd: Add/Del command
  2769. * @macaddr: nac client mac address
  2770. *
  2771. * Return: void
  2772. */
  2773. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2774. uint32_t cmd, uint8_t *macaddr)
  2775. {
  2776. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2777. struct dp_neighbour_peer *peer = NULL;
  2778. if (!macaddr)
  2779. goto fail0;
  2780. /* Store address of NAC (neighbour peer) which will be checked
  2781. * against TA of received packets.
  2782. */
  2783. if (cmd == DP_NAC_PARAM_ADD) {
  2784. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2785. sizeof(*peer));
  2786. if (!peer) {
  2787. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2788. FL("DP neighbour peer node memory allocation failed"));
  2789. goto fail0;
  2790. }
  2791. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2792. macaddr, DP_MAC_ADDR_LEN);
  2793. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2794. /* add this neighbour peer into the list */
  2795. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2796. neighbour_peer_list_elem);
  2797. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2798. return 1;
  2799. } else if (cmd == DP_NAC_PARAM_DEL) {
  2800. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2801. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2802. neighbour_peer_list_elem) {
  2803. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2804. macaddr, DP_MAC_ADDR_LEN)) {
  2805. /* delete this peer from the list */
  2806. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2807. peer, neighbour_peer_list_elem);
  2808. qdf_mem_free(peer);
  2809. break;
  2810. }
  2811. }
  2812. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2813. return 1;
  2814. }
  2815. fail0:
  2816. return 0;
  2817. }
  2818. /*
  2819. * dp_get_sec_type() - Get the security type
  2820. * @peer: Datapath peer handle
  2821. * @sec_idx: Security id (mcast, ucast)
  2822. *
  2823. * return sec_type: Security type
  2824. */
  2825. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2826. {
  2827. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2828. return dpeer->security[sec_idx].sec_type;
  2829. }
  2830. /*
  2831. * dp_peer_authorize() - authorize txrx peer
  2832. * @peer_handle: Datapath peer handle
  2833. * @authorize
  2834. *
  2835. */
  2836. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2837. {
  2838. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2839. struct dp_soc *soc;
  2840. if (peer != NULL) {
  2841. soc = peer->vdev->pdev->soc;
  2842. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2843. dp_son_peer_authorize(peer);
  2844. peer->authorize = authorize ? 1 : 0;
  2845. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2846. }
  2847. }
  2848. /*
  2849. * dp_peer_unref_delete() - unref and delete peer
  2850. * @peer_handle: Datapath peer handle
  2851. *
  2852. */
  2853. void dp_peer_unref_delete(void *peer_handle)
  2854. {
  2855. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2856. struct dp_vdev *vdev = peer->vdev;
  2857. struct dp_pdev *pdev = vdev->pdev;
  2858. struct dp_soc *soc = pdev->soc;
  2859. struct dp_peer *tmppeer;
  2860. int found = 0;
  2861. uint16_t peer_id;
  2862. /*
  2863. * Hold the lock all the way from checking if the peer ref count
  2864. * is zero until the peer references are removed from the hash
  2865. * table and vdev list (if the peer ref count is zero).
  2866. * This protects against a new HL tx operation starting to use the
  2867. * peer object just after this function concludes it's done being used.
  2868. * Furthermore, the lock needs to be held while checking whether the
  2869. * vdev's list of peers is empty, to make sure that list is not modified
  2870. * concurrently with the empty check.
  2871. */
  2872. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2873. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2874. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2875. peer, qdf_atomic_read(&peer->ref_cnt));
  2876. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2877. peer_id = peer->peer_ids[0];
  2878. /*
  2879. * Make sure that the reference to the peer in
  2880. * peer object map is removed
  2881. */
  2882. if (peer_id != HTT_INVALID_PEER)
  2883. soc->peer_id_to_obj_map[peer_id] = NULL;
  2884. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2885. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2886. /* remove the reference to the peer from the hash table */
  2887. dp_peer_find_hash_remove(soc, peer);
  2888. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2889. if (tmppeer == peer) {
  2890. found = 1;
  2891. break;
  2892. }
  2893. }
  2894. if (found) {
  2895. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2896. peer_list_elem);
  2897. } else {
  2898. /*Ignoring the remove operation as peer not found*/
  2899. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2900. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2901. peer, vdev, &peer->vdev->peer_list);
  2902. }
  2903. /* cleanup the peer data */
  2904. dp_peer_cleanup(vdev, peer);
  2905. /* check whether the parent vdev has no peers left */
  2906. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2907. /*
  2908. * Now that there are no references to the peer, we can
  2909. * release the peer reference lock.
  2910. */
  2911. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2912. /*
  2913. * Check if the parent vdev was waiting for its peers
  2914. * to be deleted, in order for it to be deleted too.
  2915. */
  2916. if (vdev->delete.pending) {
  2917. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2918. vdev->delete.callback;
  2919. void *vdev_delete_context =
  2920. vdev->delete.context;
  2921. QDF_TRACE(QDF_MODULE_ID_DP,
  2922. QDF_TRACE_LEVEL_INFO_HIGH,
  2923. FL("deleting vdev object %pK (%pM)"
  2924. " - its last peer is done"),
  2925. vdev, vdev->mac_addr.raw);
  2926. /* all peers are gone, go ahead and delete it */
  2927. qdf_mem_free(vdev);
  2928. if (vdev_delete_cb)
  2929. vdev_delete_cb(vdev_delete_context);
  2930. }
  2931. } else {
  2932. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2933. }
  2934. #ifdef notyet
  2935. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2936. #else
  2937. qdf_mem_free(peer);
  2938. #endif
  2939. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2940. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2941. vdev->vdev_id, peer->mac_addr.raw);
  2942. }
  2943. } else {
  2944. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2945. }
  2946. }
  2947. /*
  2948. * dp_peer_detach_wifi3() – Detach txrx peer
  2949. * @peer_handle: Datapath peer handle
  2950. *
  2951. */
  2952. static void dp_peer_delete_wifi3(void *peer_handle)
  2953. {
  2954. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2955. /* redirect the peer's rx delivery function to point to a
  2956. * discard func
  2957. */
  2958. peer->rx_opt_proc = dp_rx_discard;
  2959. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2960. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2961. #ifndef CONFIG_WIN
  2962. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2963. #endif
  2964. qdf_spinlock_destroy(&peer->peer_info_lock);
  2965. /*
  2966. * Remove the reference added during peer_attach.
  2967. * The peer will still be left allocated until the
  2968. * PEER_UNMAP message arrives to remove the other
  2969. * reference, added by the PEER_MAP message.
  2970. */
  2971. dp_peer_unref_delete(peer_handle);
  2972. }
  2973. /*
  2974. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2975. * @peer_handle: Datapath peer handle
  2976. *
  2977. */
  2978. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2979. {
  2980. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2981. return vdev->mac_addr.raw;
  2982. }
  2983. /*
  2984. * dp_vdev_set_wds() - Enable per packet stats
  2985. * @vdev_handle: DP VDEV handle
  2986. * @val: value
  2987. *
  2988. * Return: none
  2989. */
  2990. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2991. {
  2992. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2993. vdev->wds_enabled = val;
  2994. return 0;
  2995. }
  2996. /*
  2997. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2998. * @peer_handle: Datapath peer handle
  2999. *
  3000. */
  3001. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3002. uint8_t vdev_id)
  3003. {
  3004. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3005. struct dp_vdev *vdev = NULL;
  3006. if (qdf_unlikely(!pdev))
  3007. return NULL;
  3008. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3009. if (vdev->vdev_id == vdev_id)
  3010. break;
  3011. }
  3012. return (struct cdp_vdev *)vdev;
  3013. }
  3014. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3015. {
  3016. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3017. return vdev->opmode;
  3018. }
  3019. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3020. {
  3021. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3022. struct dp_pdev *pdev = vdev->pdev;
  3023. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3024. }
  3025. /**
  3026. * dp_reset_monitor_mode() - Disable monitor mode
  3027. * @pdev_handle: Datapath PDEV handle
  3028. *
  3029. * Return: 0 on success, not 0 on failure
  3030. */
  3031. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3032. {
  3033. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3034. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3035. struct dp_soc *soc;
  3036. uint8_t pdev_id;
  3037. pdev_id = pdev->pdev_id;
  3038. soc = pdev->soc;
  3039. pdev->monitor_vdev = NULL;
  3040. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3041. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3042. pdev->rxdma_mon_buf_ring.hal_srng,
  3043. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3044. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3045. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3046. RX_BUFFER_SIZE, &htt_tlv_filter);
  3047. return 0;
  3048. }
  3049. /**
  3050. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3051. * @vdev_handle: Datapath VDEV handle
  3052. * @smart_monitor: Flag to denote if its smart monitor mode
  3053. *
  3054. * Return: 0 on success, not 0 on failure
  3055. */
  3056. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3057. uint8_t smart_monitor)
  3058. {
  3059. /* Many monitor VAPs can exists in a system but only one can be up at
  3060. * anytime
  3061. */
  3062. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3063. struct dp_pdev *pdev;
  3064. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3065. struct dp_soc *soc;
  3066. uint8_t pdev_id;
  3067. qdf_assert(vdev);
  3068. pdev = vdev->pdev;
  3069. pdev_id = pdev->pdev_id;
  3070. soc = pdev->soc;
  3071. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3072. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3073. pdev, pdev_id, soc, vdev);
  3074. /*Check if current pdev's monitor_vdev exists */
  3075. if (pdev->monitor_vdev) {
  3076. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3077. "vdev=%pK\n", vdev);
  3078. qdf_assert(vdev);
  3079. }
  3080. pdev->monitor_vdev = vdev;
  3081. /* If smart monitor mode, do not configure monitor ring */
  3082. if (smart_monitor)
  3083. return QDF_STATUS_SUCCESS;
  3084. htt_tlv_filter.mpdu_start = 1;
  3085. htt_tlv_filter.msdu_start = 1;
  3086. htt_tlv_filter.packet = 1;
  3087. htt_tlv_filter.msdu_end = 1;
  3088. htt_tlv_filter.mpdu_end = 1;
  3089. htt_tlv_filter.packet_header = 1;
  3090. htt_tlv_filter.attention = 1;
  3091. htt_tlv_filter.ppdu_start = 0;
  3092. htt_tlv_filter.ppdu_end = 0;
  3093. htt_tlv_filter.ppdu_end_user_stats = 0;
  3094. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3095. htt_tlv_filter.ppdu_end_status_done = 0;
  3096. htt_tlv_filter.header_per_msdu = 1;
  3097. htt_tlv_filter.enable_fp = 1;
  3098. htt_tlv_filter.enable_md = 0;
  3099. htt_tlv_filter.enable_mo = 1;
  3100. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3101. pdev->rxdma_mon_buf_ring.hal_srng,
  3102. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3103. htt_tlv_filter.mpdu_start = 1;
  3104. htt_tlv_filter.msdu_start = 1;
  3105. htt_tlv_filter.packet = 0;
  3106. htt_tlv_filter.msdu_end = 1;
  3107. htt_tlv_filter.mpdu_end = 1;
  3108. htt_tlv_filter.packet_header = 1;
  3109. htt_tlv_filter.attention = 1;
  3110. htt_tlv_filter.ppdu_start = 1;
  3111. htt_tlv_filter.ppdu_end = 1;
  3112. htt_tlv_filter.ppdu_end_user_stats = 1;
  3113. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3114. htt_tlv_filter.ppdu_end_status_done = 1;
  3115. htt_tlv_filter.header_per_msdu = 0;
  3116. htt_tlv_filter.enable_fp = 1;
  3117. htt_tlv_filter.enable_md = 0;
  3118. htt_tlv_filter.enable_mo = 1;
  3119. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3120. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3121. RX_BUFFER_SIZE, &htt_tlv_filter);
  3122. return QDF_STATUS_SUCCESS;
  3123. }
  3124. #ifdef MESH_MODE_SUPPORT
  3125. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3126. {
  3127. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3128. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3129. FL("val %d"), val);
  3130. vdev->mesh_vdev = val;
  3131. }
  3132. /*
  3133. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3134. * @vdev_hdl: virtual device object
  3135. * @val: value to be set
  3136. *
  3137. * Return: void
  3138. */
  3139. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3140. {
  3141. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3142. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3143. FL("val %d"), val);
  3144. vdev->mesh_rx_filter = val;
  3145. }
  3146. #endif
  3147. /**
  3148. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3149. * @vdev: DP VDEV handle
  3150. *
  3151. * return: void
  3152. */
  3153. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3154. {
  3155. struct dp_peer *peer = NULL;
  3156. struct dp_soc *soc = vdev->pdev->soc;
  3157. int i;
  3158. uint8_t pream_type;
  3159. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3160. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3161. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3162. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3163. for (i = 0; i < MAX_MCS; i++) {
  3164. DP_STATS_AGGR(vdev, peer,
  3165. tx.pkt_type[pream_type].mcs_count[i]);
  3166. DP_STATS_AGGR(vdev, peer,
  3167. rx.pkt_type[pream_type].mcs_count[i]);
  3168. }
  3169. }
  3170. for (i = 0; i < MAX_BW; i++) {
  3171. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3172. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3173. }
  3174. for (i = 0; i < SS_COUNT; i++)
  3175. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3176. for (i = 0; i < WME_AC_MAX; i++) {
  3177. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3178. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3179. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3180. }
  3181. for (i = 0; i < MAX_GI; i++) {
  3182. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3183. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3184. }
  3185. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3186. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3187. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3188. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3189. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3190. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3191. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3192. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3193. DP_STATS_AGGR(vdev, peer, tx.retries);
  3194. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3195. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3196. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3197. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3198. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3199. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3200. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3201. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3202. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3203. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3204. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3205. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3206. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3207. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3208. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3209. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3210. peer->stats.rx.multicast.num;
  3211. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3212. peer->stats.rx.multicast.bytes;
  3213. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3214. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3215. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3216. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3217. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3218. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3219. vdev->stats.tx.last_ack_rssi =
  3220. peer->stats.tx.last_ack_rssi;
  3221. }
  3222. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3223. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3224. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3225. }
  3226. /**
  3227. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3228. * @pdev: DP PDEV handle
  3229. *
  3230. * return: void
  3231. */
  3232. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3233. {
  3234. struct dp_vdev *vdev = NULL;
  3235. uint8_t i;
  3236. uint8_t pream_type;
  3237. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3238. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3239. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3240. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3241. dp_aggregate_vdev_stats(vdev);
  3242. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3243. for (i = 0; i < MAX_MCS; i++) {
  3244. DP_STATS_AGGR(pdev, vdev,
  3245. tx.pkt_type[pream_type].mcs_count[i]);
  3246. DP_STATS_AGGR(pdev, vdev,
  3247. rx.pkt_type[pream_type].mcs_count[i]);
  3248. }
  3249. }
  3250. for (i = 0; i < MAX_BW; i++) {
  3251. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3252. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3253. }
  3254. for (i = 0; i < SS_COUNT; i++)
  3255. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3256. for (i = 0; i < WME_AC_MAX; i++) {
  3257. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3258. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3259. DP_STATS_AGGR(pdev, vdev,
  3260. tx.excess_retries_ac[i]);
  3261. }
  3262. for (i = 0; i < MAX_GI; i++) {
  3263. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3264. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3265. }
  3266. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3267. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3268. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3269. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3270. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3271. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3272. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3273. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3274. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3275. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3276. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3277. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3278. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3279. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3280. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3281. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3282. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3283. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3284. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3285. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3286. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3287. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3288. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3289. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3290. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3291. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3292. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3293. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3294. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3295. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3296. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3297. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3298. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3299. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3300. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3301. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3302. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3303. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3304. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3305. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3306. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3307. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3308. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3309. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3310. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3311. DP_STATS_AGGR(pdev, vdev,
  3312. tx_i.mcast_en.dropped_map_error);
  3313. DP_STATS_AGGR(pdev, vdev,
  3314. tx_i.mcast_en.dropped_self_mac);
  3315. DP_STATS_AGGR(pdev, vdev,
  3316. tx_i.mcast_en.dropped_send_fail);
  3317. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3318. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3319. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3320. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3321. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3322. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3323. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3324. pdev->stats.tx_i.dropped.dma_error +
  3325. pdev->stats.tx_i.dropped.ring_full +
  3326. pdev->stats.tx_i.dropped.enqueue_fail +
  3327. pdev->stats.tx_i.dropped.desc_na +
  3328. pdev->stats.tx_i.dropped.res_full;
  3329. pdev->stats.tx.last_ack_rssi =
  3330. vdev->stats.tx.last_ack_rssi;
  3331. pdev->stats.tx_i.tso.num_seg =
  3332. vdev->stats.tx_i.tso.num_seg;
  3333. }
  3334. }
  3335. /**
  3336. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3337. * @pdev: DP_PDEV Handle
  3338. *
  3339. * Return:void
  3340. */
  3341. static inline void
  3342. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3343. {
  3344. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3345. DP_PRINT_STATS("Received From Stack:");
  3346. DP_PRINT_STATS(" Packets = %d",
  3347. pdev->stats.tx_i.rcvd.num);
  3348. DP_PRINT_STATS(" Bytes = %d",
  3349. pdev->stats.tx_i.rcvd.bytes);
  3350. DP_PRINT_STATS("Processed:");
  3351. DP_PRINT_STATS(" Packets = %d",
  3352. pdev->stats.tx_i.processed.num);
  3353. DP_PRINT_STATS(" Bytes = %d",
  3354. pdev->stats.tx_i.processed.bytes);
  3355. DP_PRINT_STATS("Completions:");
  3356. DP_PRINT_STATS(" Packets = %d",
  3357. pdev->stats.tx.comp_pkt.num);
  3358. DP_PRINT_STATS(" Bytes = %d",
  3359. pdev->stats.tx.comp_pkt.bytes);
  3360. DP_PRINT_STATS("Dropped:");
  3361. DP_PRINT_STATS(" Total = %d",
  3362. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3363. DP_PRINT_STATS(" Dma_map_error = %d",
  3364. pdev->stats.tx_i.dropped.dma_error);
  3365. DP_PRINT_STATS(" Ring Full = %d",
  3366. pdev->stats.tx_i.dropped.ring_full);
  3367. DP_PRINT_STATS(" Descriptor Not available = %d",
  3368. pdev->stats.tx_i.dropped.desc_na);
  3369. DP_PRINT_STATS(" HW enqueue failed= %d",
  3370. pdev->stats.tx_i.dropped.enqueue_fail);
  3371. DP_PRINT_STATS(" Resources Full = %d",
  3372. pdev->stats.tx_i.dropped.res_full);
  3373. DP_PRINT_STATS(" FW removed = %d",
  3374. pdev->stats.tx.dropped.fw_rem);
  3375. DP_PRINT_STATS(" FW removed transmitted = %d",
  3376. pdev->stats.tx.dropped.fw_rem_tx);
  3377. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3378. pdev->stats.tx.dropped.fw_rem_notx);
  3379. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3380. pdev->stats.tx.dropped.age_out);
  3381. DP_PRINT_STATS("Scatter Gather:");
  3382. DP_PRINT_STATS(" Packets = %d",
  3383. pdev->stats.tx_i.sg.sg_pkt.num);
  3384. DP_PRINT_STATS(" Bytes = %d",
  3385. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3386. DP_PRINT_STATS(" Dropped By Host = %d",
  3387. pdev->stats.tx_i.sg.dropped_host);
  3388. DP_PRINT_STATS(" Dropped By Target = %d",
  3389. pdev->stats.tx_i.sg.dropped_target);
  3390. DP_PRINT_STATS("TSO:");
  3391. DP_PRINT_STATS(" Number of Segments = %d",
  3392. pdev->stats.tx_i.tso.num_seg);
  3393. DP_PRINT_STATS(" Packets = %d",
  3394. pdev->stats.tx_i.tso.tso_pkt.num);
  3395. DP_PRINT_STATS(" Bytes = %d",
  3396. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3397. DP_PRINT_STATS(" Dropped By Host = %d",
  3398. pdev->stats.tx_i.tso.dropped_host);
  3399. DP_PRINT_STATS("Mcast Enhancement:");
  3400. DP_PRINT_STATS(" Packets = %d",
  3401. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3402. DP_PRINT_STATS(" Bytes = %d",
  3403. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3404. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3405. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3406. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3407. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3408. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3409. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3410. DP_PRINT_STATS(" Unicast sent = %d",
  3411. pdev->stats.tx_i.mcast_en.ucast);
  3412. DP_PRINT_STATS("Raw:");
  3413. DP_PRINT_STATS(" Packets = %d",
  3414. pdev->stats.tx_i.raw.raw_pkt.num);
  3415. DP_PRINT_STATS(" Bytes = %d",
  3416. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3417. DP_PRINT_STATS(" DMA map error = %d",
  3418. pdev->stats.tx_i.raw.dma_map_error);
  3419. DP_PRINT_STATS("Reinjected:");
  3420. DP_PRINT_STATS(" Packets = %d",
  3421. pdev->stats.tx_i.reinject_pkts.num);
  3422. DP_PRINT_STATS("Bytes = %d\n",
  3423. pdev->stats.tx_i.reinject_pkts.bytes);
  3424. DP_PRINT_STATS("Inspected:");
  3425. DP_PRINT_STATS(" Packets = %d",
  3426. pdev->stats.tx_i.inspect_pkts.num);
  3427. DP_PRINT_STATS(" Bytes = %d",
  3428. pdev->stats.tx_i.inspect_pkts.bytes);
  3429. }
  3430. /**
  3431. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3432. * @pdev: DP_PDEV Handle
  3433. *
  3434. * Return: void
  3435. */
  3436. static inline void
  3437. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3438. {
  3439. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3440. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3441. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3442. pdev->stats.rx.rcvd_reo[0].num,
  3443. pdev->stats.rx.rcvd_reo[1].num,
  3444. pdev->stats.rx.rcvd_reo[2].num,
  3445. pdev->stats.rx.rcvd_reo[3].num);
  3446. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3447. pdev->stats.rx.rcvd_reo[0].bytes,
  3448. pdev->stats.rx.rcvd_reo[1].bytes,
  3449. pdev->stats.rx.rcvd_reo[2].bytes,
  3450. pdev->stats.rx.rcvd_reo[3].bytes);
  3451. DP_PRINT_STATS("Replenished:");
  3452. DP_PRINT_STATS(" Packets = %d",
  3453. pdev->stats.replenish.pkts.num);
  3454. DP_PRINT_STATS(" Bytes = %d",
  3455. pdev->stats.replenish.pkts.bytes);
  3456. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3457. pdev->stats.buf_freelist);
  3458. DP_PRINT_STATS("Dropped:");
  3459. DP_PRINT_STATS(" msdu_not_done = %d",
  3460. pdev->stats.dropped.msdu_not_done);
  3461. DP_PRINT_STATS("Sent To Stack:");
  3462. DP_PRINT_STATS(" Packets = %d",
  3463. pdev->stats.rx.to_stack.num);
  3464. DP_PRINT_STATS(" Bytes = %d",
  3465. pdev->stats.rx.to_stack.bytes);
  3466. DP_PRINT_STATS("Multicast/Broadcast:");
  3467. DP_PRINT_STATS(" Packets = %d",
  3468. pdev->stats.rx.multicast.num);
  3469. DP_PRINT_STATS(" Bytes = %d",
  3470. pdev->stats.rx.multicast.bytes);
  3471. DP_PRINT_STATS("Errors:");
  3472. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3473. pdev->stats.replenish.rxdma_err);
  3474. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3475. pdev->stats.err.desc_alloc_fail);
  3476. }
  3477. /**
  3478. * dp_print_soc_tx_stats(): Print SOC level stats
  3479. * @soc DP_SOC Handle
  3480. *
  3481. * Return: void
  3482. */
  3483. static inline void
  3484. dp_print_soc_tx_stats(struct dp_soc *soc)
  3485. {
  3486. DP_PRINT_STATS("SOC Tx Stats:\n");
  3487. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3488. soc->stats.tx.desc_in_use);
  3489. DP_PRINT_STATS("Invalid peer:");
  3490. DP_PRINT_STATS(" Packets = %d",
  3491. soc->stats.tx.tx_invalid_peer.num);
  3492. DP_PRINT_STATS(" Bytes = %d",
  3493. soc->stats.tx.tx_invalid_peer.bytes);
  3494. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3495. soc->stats.tx.tcl_ring_full[0],
  3496. soc->stats.tx.tcl_ring_full[1],
  3497. soc->stats.tx.tcl_ring_full[2]);
  3498. }
  3499. /**
  3500. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3501. * @soc: DP_SOC Handle
  3502. *
  3503. * Return:void
  3504. */
  3505. static inline void
  3506. dp_print_soc_rx_stats(struct dp_soc *soc)
  3507. {
  3508. uint32_t i;
  3509. char reo_error[DP_REO_ERR_LENGTH];
  3510. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3511. uint8_t index = 0;
  3512. DP_PRINT_STATS("SOC Rx Stats:\n");
  3513. DP_PRINT_STATS("Errors:\n");
  3514. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3515. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3516. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3517. DP_PRINT_STATS("Invalid RBM = %d",
  3518. soc->stats.rx.err.invalid_rbm);
  3519. DP_PRINT_STATS("Invalid Vdev = %d",
  3520. soc->stats.rx.err.invalid_vdev);
  3521. DP_PRINT_STATS("Invalid Pdev = %d",
  3522. soc->stats.rx.err.invalid_pdev);
  3523. DP_PRINT_STATS("Invalid Peer = %d",
  3524. soc->stats.rx.err.rx_invalid_peer.num);
  3525. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3526. soc->stats.rx.err.hal_ring_access_fail);
  3527. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3528. index += qdf_snprint(&rxdma_error[index],
  3529. DP_RXDMA_ERR_LENGTH - index,
  3530. " %d", soc->stats.rx.err.rxdma_error[i]);
  3531. }
  3532. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3533. rxdma_error);
  3534. index = 0;
  3535. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3536. index += qdf_snprint(&reo_error[index],
  3537. DP_REO_ERR_LENGTH - index,
  3538. " %d", soc->stats.rx.err.reo_error[i]);
  3539. }
  3540. DP_PRINT_STATS("REO Error(0-14):%s",
  3541. reo_error);
  3542. }
  3543. /**
  3544. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3545. * @soc: DP_SOC handle
  3546. * @srng: DP_SRNG handle
  3547. * @ring_name: SRNG name
  3548. *
  3549. * Return: void
  3550. */
  3551. static inline void
  3552. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3553. char *ring_name)
  3554. {
  3555. uint32_t tailp;
  3556. uint32_t headp;
  3557. if (srng->hal_srng != NULL) {
  3558. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3559. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3560. ring_name, headp, tailp);
  3561. }
  3562. }
  3563. /**
  3564. * dp_print_ring_stats(): Print tail and head pointer
  3565. * @pdev: DP_PDEV handle
  3566. *
  3567. * Return:void
  3568. */
  3569. static inline void
  3570. dp_print_ring_stats(struct dp_pdev *pdev)
  3571. {
  3572. uint32_t i;
  3573. char ring_name[STR_MAXLEN + 1];
  3574. dp_print_ring_stat_from_hal(pdev->soc,
  3575. &pdev->soc->reo_exception_ring,
  3576. "Reo Exception Ring");
  3577. dp_print_ring_stat_from_hal(pdev->soc,
  3578. &pdev->soc->reo_reinject_ring,
  3579. "Reo Inject Ring");
  3580. dp_print_ring_stat_from_hal(pdev->soc,
  3581. &pdev->soc->reo_cmd_ring,
  3582. "Reo Command Ring");
  3583. dp_print_ring_stat_from_hal(pdev->soc,
  3584. &pdev->soc->reo_status_ring,
  3585. "Reo Status Ring");
  3586. dp_print_ring_stat_from_hal(pdev->soc,
  3587. &pdev->soc->rx_rel_ring,
  3588. "Rx Release ring");
  3589. dp_print_ring_stat_from_hal(pdev->soc,
  3590. &pdev->soc->tcl_cmd_ring,
  3591. "Tcl command Ring");
  3592. dp_print_ring_stat_from_hal(pdev->soc,
  3593. &pdev->soc->tcl_status_ring,
  3594. "Tcl Status Ring");
  3595. dp_print_ring_stat_from_hal(pdev->soc,
  3596. &pdev->soc->wbm_desc_rel_ring,
  3597. "Wbm Desc Rel Ring");
  3598. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3599. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3600. dp_print_ring_stat_from_hal(pdev->soc,
  3601. &pdev->soc->reo_dest_ring[i],
  3602. ring_name);
  3603. }
  3604. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3605. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3606. dp_print_ring_stat_from_hal(pdev->soc,
  3607. &pdev->soc->tcl_data_ring[i],
  3608. ring_name);
  3609. }
  3610. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3611. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3612. dp_print_ring_stat_from_hal(pdev->soc,
  3613. &pdev->soc->tx_comp_ring[i],
  3614. ring_name);
  3615. }
  3616. dp_print_ring_stat_from_hal(pdev->soc,
  3617. &pdev->rx_refill_buf_ring,
  3618. "Rx Refill Buf Ring");
  3619. #ifdef IPA_OFFLOAD
  3620. dp_print_ring_stat_from_hal(pdev->soc,
  3621. &pdev->ipa_rx_refill_buf_ring,
  3622. "IPA Rx Refill Buf Ring");
  3623. #endif
  3624. dp_print_ring_stat_from_hal(pdev->soc,
  3625. &pdev->rxdma_mon_buf_ring,
  3626. "Rxdma Mon Buf Ring");
  3627. dp_print_ring_stat_from_hal(pdev->soc,
  3628. &pdev->rxdma_mon_dst_ring,
  3629. "Rxdma Mon Dst Ring");
  3630. dp_print_ring_stat_from_hal(pdev->soc,
  3631. &pdev->rxdma_mon_status_ring,
  3632. "Rxdma Mon Status Ring");
  3633. dp_print_ring_stat_from_hal(pdev->soc,
  3634. &pdev->rxdma_mon_desc_ring,
  3635. "Rxdma mon desc Ring");
  3636. dp_print_ring_stat_from_hal(pdev->soc,
  3637. &pdev->rxdma_err_dst_ring,
  3638. "Rxdma err dst ring");
  3639. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3640. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3641. dp_print_ring_stat_from_hal(pdev->soc,
  3642. &pdev->rx_mac_buf_ring[i],
  3643. ring_name);
  3644. }
  3645. }
  3646. /**
  3647. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3648. * @vdev: DP_VDEV handle
  3649. *
  3650. * Return:void
  3651. */
  3652. static inline void
  3653. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3654. {
  3655. struct dp_peer *peer = NULL;
  3656. DP_STATS_CLR(vdev->pdev);
  3657. DP_STATS_CLR(vdev->pdev->soc);
  3658. DP_STATS_CLR(vdev);
  3659. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3660. if (!peer)
  3661. return;
  3662. DP_STATS_CLR(peer);
  3663. }
  3664. }
  3665. /**
  3666. * dp_print_rx_rates(): Print Rx rate stats
  3667. * @vdev: DP_VDEV handle
  3668. *
  3669. * Return:void
  3670. */
  3671. static inline void
  3672. dp_print_rx_rates(struct dp_vdev *vdev)
  3673. {
  3674. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3675. uint8_t i, mcs, pkt_type;
  3676. uint8_t index = 0;
  3677. char nss[DP_NSS_LENGTH];
  3678. DP_PRINT_STATS("Rx Rate Info:\n");
  3679. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3680. index = 0;
  3681. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3682. if (!dp_rate_string[pkt_type][mcs].valid)
  3683. continue;
  3684. DP_PRINT_STATS(" %s = %d",
  3685. dp_rate_string[pkt_type][mcs].mcs_type,
  3686. pdev->stats.rx.pkt_type[pkt_type].
  3687. mcs_count[mcs]);
  3688. }
  3689. DP_PRINT_STATS("\n");
  3690. }
  3691. index = 0;
  3692. for (i = 0; i < SS_COUNT; i++) {
  3693. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3694. " %d", pdev->stats.rx.nss[i]);
  3695. }
  3696. DP_PRINT_STATS("NSS(0-7) = %s",
  3697. nss);
  3698. DP_PRINT_STATS("SGI ="
  3699. " 0.8us %d,"
  3700. " 0.4us %d,"
  3701. " 1.6us %d,"
  3702. " 3.2us %d,",
  3703. pdev->stats.rx.sgi_count[0],
  3704. pdev->stats.rx.sgi_count[1],
  3705. pdev->stats.rx.sgi_count[2],
  3706. pdev->stats.rx.sgi_count[3]);
  3707. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3708. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3709. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3710. DP_PRINT_STATS("Reception Type ="
  3711. " SU: %d,"
  3712. " MU_MIMO:%d,"
  3713. " MU_OFDMA:%d,"
  3714. " MU_OFDMA_MIMO:%d\n",
  3715. pdev->stats.rx.reception_type[0],
  3716. pdev->stats.rx.reception_type[1],
  3717. pdev->stats.rx.reception_type[2],
  3718. pdev->stats.rx.reception_type[3]);
  3719. DP_PRINT_STATS("Aggregation:\n");
  3720. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3721. pdev->stats.rx.ampdu_cnt);
  3722. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3723. pdev->stats.rx.non_ampdu_cnt);
  3724. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3725. pdev->stats.rx.amsdu_cnt);
  3726. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3727. pdev->stats.rx.non_amsdu_cnt);
  3728. }
  3729. /**
  3730. * dp_print_tx_rates(): Print tx rates
  3731. * @vdev: DP_VDEV handle
  3732. *
  3733. * Return:void
  3734. */
  3735. static inline void
  3736. dp_print_tx_rates(struct dp_vdev *vdev)
  3737. {
  3738. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3739. uint8_t mcs, pkt_type;
  3740. uint32_t index;
  3741. DP_PRINT_STATS("Tx Rate Info:\n");
  3742. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3743. index = 0;
  3744. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3745. if (!dp_rate_string[pkt_type][mcs].valid)
  3746. continue;
  3747. DP_PRINT_STATS(" %s = %d",
  3748. dp_rate_string[pkt_type][mcs].mcs_type,
  3749. pdev->stats.tx.pkt_type[pkt_type].
  3750. mcs_count[mcs]);
  3751. }
  3752. DP_PRINT_STATS("\n");
  3753. }
  3754. DP_PRINT_STATS("SGI ="
  3755. " 0.8us %d"
  3756. " 0.4us %d"
  3757. " 1.6us %d"
  3758. " 3.2us %d",
  3759. pdev->stats.tx.sgi_count[0],
  3760. pdev->stats.tx.sgi_count[1],
  3761. pdev->stats.tx.sgi_count[2],
  3762. pdev->stats.tx.sgi_count[3]);
  3763. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3764. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3765. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3766. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3767. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3768. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3769. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3770. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3771. DP_PRINT_STATS("Aggregation:\n");
  3772. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3773. pdev->stats.tx.amsdu_cnt);
  3774. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3775. pdev->stats.tx.non_amsdu_cnt);
  3776. }
  3777. /**
  3778. * dp_print_peer_stats():print peer stats
  3779. * @peer: DP_PEER handle
  3780. *
  3781. * return void
  3782. */
  3783. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3784. {
  3785. uint8_t i, mcs, pkt_type;
  3786. uint32_t index;
  3787. char nss[DP_NSS_LENGTH];
  3788. DP_PRINT_STATS("Node Tx Stats:\n");
  3789. DP_PRINT_STATS("Total Packet Completions = %d",
  3790. peer->stats.tx.comp_pkt.num);
  3791. DP_PRINT_STATS("Total Bytes Completions = %d",
  3792. peer->stats.tx.comp_pkt.bytes);
  3793. DP_PRINT_STATS("Success Packets = %d",
  3794. peer->stats.tx.tx_success.num);
  3795. DP_PRINT_STATS("Success Bytes = %d",
  3796. peer->stats.tx.tx_success.bytes);
  3797. DP_PRINT_STATS("Packets Failed = %d",
  3798. peer->stats.tx.tx_failed);
  3799. DP_PRINT_STATS("Packets In OFDMA = %d",
  3800. peer->stats.tx.ofdma);
  3801. DP_PRINT_STATS("Packets In STBC = %d",
  3802. peer->stats.tx.stbc);
  3803. DP_PRINT_STATS("Packets In LDPC = %d",
  3804. peer->stats.tx.ldpc);
  3805. DP_PRINT_STATS("Packet Retries = %d",
  3806. peer->stats.tx.retries);
  3807. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3808. peer->stats.tx.amsdu_cnt);
  3809. DP_PRINT_STATS("Last Packet RSSI = %d",
  3810. peer->stats.tx.last_ack_rssi);
  3811. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3812. peer->stats.tx.dropped.fw_rem);
  3813. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3814. peer->stats.tx.dropped.fw_rem_tx);
  3815. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3816. peer->stats.tx.dropped.fw_rem_notx);
  3817. DP_PRINT_STATS("Dropped : Age Out = %d",
  3818. peer->stats.tx.dropped.age_out);
  3819. DP_PRINT_STATS("Rate Info:");
  3820. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3821. index = 0;
  3822. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3823. if (!dp_rate_string[pkt_type][mcs].valid)
  3824. continue;
  3825. DP_PRINT_STATS(" %s = %d",
  3826. dp_rate_string[pkt_type][mcs].mcs_type,
  3827. peer->stats.tx.pkt_type[pkt_type].
  3828. mcs_count[mcs]);
  3829. }
  3830. DP_PRINT_STATS("\n");
  3831. }
  3832. DP_PRINT_STATS("SGI = "
  3833. " 0.8us %d"
  3834. " 0.4us %d"
  3835. " 1.6us %d"
  3836. " 3.2us %d",
  3837. peer->stats.tx.sgi_count[0],
  3838. peer->stats.tx.sgi_count[1],
  3839. peer->stats.tx.sgi_count[2],
  3840. peer->stats.tx.sgi_count[3]);
  3841. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3842. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3843. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3844. DP_PRINT_STATS("Aggregation:");
  3845. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3846. peer->stats.tx.amsdu_cnt);
  3847. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3848. peer->stats.tx.non_amsdu_cnt);
  3849. DP_PRINT_STATS("Node Rx Stats:");
  3850. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3851. peer->stats.rx.to_stack.num);
  3852. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3853. peer->stats.rx.to_stack.bytes);
  3854. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3855. DP_PRINT_STATS("Packets Received = %d",
  3856. peer->stats.rx.rcvd_reo[i].num);
  3857. DP_PRINT_STATS("Bytes Received = %d",
  3858. peer->stats.rx.rcvd_reo[i].bytes);
  3859. }
  3860. DP_PRINT_STATS("Multicast Packets Received = %d",
  3861. peer->stats.rx.multicast.num);
  3862. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3863. peer->stats.rx.multicast.bytes);
  3864. DP_PRINT_STATS("WDS Packets Received = %d",
  3865. peer->stats.rx.wds.num);
  3866. DP_PRINT_STATS("WDS Bytes Received = %d",
  3867. peer->stats.rx.wds.bytes);
  3868. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3869. peer->stats.rx.intra_bss.pkts.num);
  3870. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3871. peer->stats.rx.intra_bss.pkts.bytes);
  3872. DP_PRINT_STATS("Raw Packets Received = %d",
  3873. peer->stats.rx.raw.num);
  3874. DP_PRINT_STATS("Raw Bytes Received = %d",
  3875. peer->stats.rx.raw.bytes);
  3876. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3877. peer->stats.rx.err.mic_err);
  3878. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3879. peer->stats.rx.err.decrypt_err);
  3880. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3881. peer->stats.rx.non_ampdu_cnt);
  3882. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3883. peer->stats.rx.ampdu_cnt);
  3884. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3885. peer->stats.rx.non_amsdu_cnt);
  3886. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3887. peer->stats.rx.amsdu_cnt);
  3888. DP_PRINT_STATS("SGI ="
  3889. " 0.8us %d"
  3890. " 0.4us %d"
  3891. " 1.6us %d"
  3892. " 3.2us %d",
  3893. peer->stats.rx.sgi_count[0],
  3894. peer->stats.rx.sgi_count[1],
  3895. peer->stats.rx.sgi_count[2],
  3896. peer->stats.rx.sgi_count[3]);
  3897. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3898. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3899. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3900. DP_PRINT_STATS("Reception Type ="
  3901. " SU %d,"
  3902. " MU_MIMO %d,"
  3903. " MU_OFDMA %d,"
  3904. " MU_OFDMA_MIMO %d",
  3905. peer->stats.rx.reception_type[0],
  3906. peer->stats.rx.reception_type[1],
  3907. peer->stats.rx.reception_type[2],
  3908. peer->stats.rx.reception_type[3]);
  3909. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3910. index = 0;
  3911. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3912. if (!dp_rate_string[pkt_type][mcs].valid)
  3913. continue;
  3914. DP_PRINT_STATS(" %s = %d",
  3915. dp_rate_string[pkt_type][mcs].mcs_type,
  3916. peer->stats.rx.pkt_type[pkt_type].
  3917. mcs_count[mcs]);
  3918. }
  3919. DP_PRINT_STATS("\n");
  3920. }
  3921. index = 0;
  3922. for (i = 0; i < SS_COUNT; i++) {
  3923. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3924. " %d", peer->stats.rx.nss[i]);
  3925. }
  3926. DP_PRINT_STATS("NSS(0-7) = %s",
  3927. nss);
  3928. DP_PRINT_STATS("Aggregation:");
  3929. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3930. peer->stats.rx.ampdu_cnt);
  3931. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3932. peer->stats.rx.non_ampdu_cnt);
  3933. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3934. peer->stats.rx.amsdu_cnt);
  3935. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3936. peer->stats.rx.non_amsdu_cnt);
  3937. }
  3938. /**
  3939. * dp_print_host_stats()- Function to print the stats aggregated at host
  3940. * @vdev_handle: DP_VDEV handle
  3941. * @type: host stats type
  3942. *
  3943. * Available Stat types
  3944. * TXRX_CLEAR_STATS : Clear the stats
  3945. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3946. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3947. * TXRX_TX_HOST_STATS: Print Tx Stats
  3948. * TXRX_RX_HOST_STATS: Print Rx Stats
  3949. * TXRX_AST_STATS: Print AST Stats
  3950. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  3951. *
  3952. * Return: 0 on success, print error message in case of failure
  3953. */
  3954. static int
  3955. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3956. {
  3957. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3958. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3959. dp_aggregate_pdev_stats(pdev);
  3960. switch (type) {
  3961. case TXRX_CLEAR_STATS:
  3962. dp_txrx_host_stats_clr(vdev);
  3963. break;
  3964. case TXRX_RX_RATE_STATS:
  3965. dp_print_rx_rates(vdev);
  3966. break;
  3967. case TXRX_TX_RATE_STATS:
  3968. dp_print_tx_rates(vdev);
  3969. break;
  3970. case TXRX_TX_HOST_STATS:
  3971. dp_print_pdev_tx_stats(pdev);
  3972. dp_print_soc_tx_stats(pdev->soc);
  3973. break;
  3974. case TXRX_RX_HOST_STATS:
  3975. dp_print_pdev_rx_stats(pdev);
  3976. dp_print_soc_rx_stats(pdev->soc);
  3977. break;
  3978. case TXRX_AST_STATS:
  3979. dp_print_ast_stats(pdev->soc);
  3980. break;
  3981. case TXRX_SRNG_PTR_STATS:
  3982. dp_print_ring_stats(pdev);
  3983. break;
  3984. default:
  3985. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3986. break;
  3987. }
  3988. return 0;
  3989. }
  3990. /*
  3991. * dp_get_host_peer_stats()- function to print peer stats
  3992. * @pdev_handle: DP_PDEV handle
  3993. * @mac_addr: mac address of the peer
  3994. *
  3995. * Return: void
  3996. */
  3997. static void
  3998. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3999. {
  4000. struct dp_peer *peer;
  4001. uint8_t local_id;
  4002. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4003. &local_id);
  4004. if (!peer) {
  4005. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4006. "%s: Invalid peer\n", __func__);
  4007. return;
  4008. }
  4009. dp_print_peer_stats(peer);
  4010. dp_peer_rxtid_stats(peer);
  4011. return;
  4012. }
  4013. /*
  4014. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4015. * @pdev: DP_PDEV handle
  4016. *
  4017. * Return: void
  4018. */
  4019. static void
  4020. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4021. {
  4022. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4023. htt_tlv_filter.mpdu_start = 0;
  4024. htt_tlv_filter.msdu_start = 0;
  4025. htt_tlv_filter.packet = 0;
  4026. htt_tlv_filter.msdu_end = 0;
  4027. htt_tlv_filter.mpdu_end = 0;
  4028. htt_tlv_filter.packet_header = 1;
  4029. htt_tlv_filter.attention = 1;
  4030. htt_tlv_filter.ppdu_start = 1;
  4031. htt_tlv_filter.ppdu_end = 1;
  4032. htt_tlv_filter.ppdu_end_user_stats = 1;
  4033. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4034. htt_tlv_filter.ppdu_end_status_done = 1;
  4035. htt_tlv_filter.enable_fp = 1;
  4036. htt_tlv_filter.enable_md = 0;
  4037. htt_tlv_filter.enable_mo = 0;
  4038. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4039. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4040. RX_BUFFER_SIZE, &htt_tlv_filter);
  4041. }
  4042. /*
  4043. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4044. * @pdev_handle: DP_PDEV handle
  4045. *
  4046. * Return: void
  4047. */
  4048. static void
  4049. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4050. {
  4051. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4052. pdev->enhanced_stats_en = 1;
  4053. dp_ppdu_ring_cfg(pdev);
  4054. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4055. }
  4056. /*
  4057. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4058. * @pdev_handle: DP_PDEV handle
  4059. *
  4060. * Return: void
  4061. */
  4062. static void
  4063. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4064. {
  4065. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4066. pdev->enhanced_stats_en = 0;
  4067. }
  4068. /*
  4069. * dp_get_fw_peer_stats()- function to print peer stats
  4070. * @pdev_handle: DP_PDEV handle
  4071. * @mac_addr: mac address of the peer
  4072. * @cap: Type of htt stats requested
  4073. *
  4074. * Currently Supporting only MAC ID based requests Only
  4075. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4076. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4077. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4078. *
  4079. * Return: void
  4080. */
  4081. static void
  4082. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4083. uint32_t cap)
  4084. {
  4085. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4086. uint32_t config_param0 = 0;
  4087. uint32_t config_param1 = 0;
  4088. uint32_t config_param2 = 0;
  4089. uint32_t config_param3 = 0;
  4090. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4091. config_param0 |= (1 << (cap + 1));
  4092. config_param1 = 0x8f;
  4093. config_param2 |= (mac_addr[0] & 0x000000ff);
  4094. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4095. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4096. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4097. config_param3 |= (mac_addr[4] & 0x000000ff);
  4098. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4099. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4100. config_param0, config_param1, config_param2,
  4101. config_param3);
  4102. }
  4103. /*
  4104. * dp_set_vdev_param: function to set parameters in vdev
  4105. * @param: parameter type to be set
  4106. * @val: value of parameter to be set
  4107. *
  4108. * return: void
  4109. */
  4110. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4111. enum cdp_vdev_param_type param, uint32_t val)
  4112. {
  4113. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4114. switch (param) {
  4115. case CDP_ENABLE_WDS:
  4116. vdev->wds_enabled = val;
  4117. break;
  4118. case CDP_ENABLE_NAWDS:
  4119. vdev->nawds_enabled = val;
  4120. break;
  4121. case CDP_ENABLE_MCAST_EN:
  4122. vdev->mcast_enhancement_en = val;
  4123. break;
  4124. case CDP_ENABLE_PROXYSTA:
  4125. vdev->proxysta_vdev = val;
  4126. break;
  4127. case CDP_UPDATE_TDLS_FLAGS:
  4128. vdev->tdls_link_connected = val;
  4129. break;
  4130. case CDP_CFG_WDS_AGING_TIMER:
  4131. if (val == 0)
  4132. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4133. else if (val != vdev->wds_aging_timer_val)
  4134. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4135. vdev->wds_aging_timer_val = val;
  4136. break;
  4137. case CDP_ENABLE_AP_BRIDGE:
  4138. if (wlan_op_mode_sta != vdev->opmode)
  4139. vdev->ap_bridge_enabled = val;
  4140. else
  4141. vdev->ap_bridge_enabled = false;
  4142. break;
  4143. default:
  4144. break;
  4145. }
  4146. dp_tx_vdev_update_search_flags(vdev);
  4147. }
  4148. /**
  4149. * dp_peer_set_nawds: set nawds bit in peer
  4150. * @peer_handle: pointer to peer
  4151. * @value: enable/disable nawds
  4152. *
  4153. * return: void
  4154. */
  4155. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4156. {
  4157. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4158. peer->nawds_enabled = value;
  4159. }
  4160. /*
  4161. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4162. * @vdev_handle: DP_VDEV handle
  4163. * @map_id:ID of map that needs to be updated
  4164. *
  4165. * Return: void
  4166. */
  4167. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4168. uint8_t map_id)
  4169. {
  4170. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4171. vdev->dscp_tid_map_id = map_id;
  4172. return;
  4173. }
  4174. /**
  4175. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4176. * @pdev: DP_PDEV handle
  4177. * @map_id: ID of map that needs to be updated
  4178. * @tos: index value in map
  4179. * @tid: tid value passed by the user
  4180. *
  4181. * Return: void
  4182. */
  4183. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4184. uint8_t map_id, uint8_t tos, uint8_t tid)
  4185. {
  4186. uint8_t dscp;
  4187. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4188. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4189. pdev->dscp_tid_map[map_id][dscp] = tid;
  4190. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4191. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4192. map_id, dscp);
  4193. return;
  4194. }
  4195. /**
  4196. * dp_fw_stats_process(): Process TxRX FW stats request
  4197. * @vdev_handle: DP VDEV handle
  4198. * @val: value passed by user
  4199. *
  4200. * return: int
  4201. */
  4202. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4203. {
  4204. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4205. struct dp_pdev *pdev = NULL;
  4206. if (!vdev) {
  4207. DP_TRACE(NONE, "VDEV not found");
  4208. return 1;
  4209. }
  4210. pdev = vdev->pdev;
  4211. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4212. }
  4213. /*
  4214. * dp_txrx_stats() - function to map to firmware and host stats
  4215. * @vdev: virtual handle
  4216. * @stats: type of statistics requested
  4217. *
  4218. * Return: integer
  4219. */
  4220. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4221. {
  4222. int host_stats;
  4223. int fw_stats;
  4224. if (stats >= CDP_TXRX_MAX_STATS)
  4225. return 0;
  4226. /*
  4227. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4228. * has to be updated if new FW HTT stats added
  4229. */
  4230. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4231. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4232. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4233. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4234. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4235. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4236. stats, fw_stats, host_stats);
  4237. if (fw_stats != TXRX_FW_STATS_INVALID)
  4238. return dp_fw_stats_process(vdev, fw_stats);
  4239. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4240. (host_stats <= TXRX_HOST_STATS_MAX))
  4241. return dp_print_host_stats(vdev, host_stats);
  4242. else
  4243. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4244. "Wrong Input for TxRx Stats");
  4245. return 0;
  4246. }
  4247. /*
  4248. * dp_print_napi_stats(): NAPI stats
  4249. * @soc - soc handle
  4250. */
  4251. static void dp_print_napi_stats(struct dp_soc *soc)
  4252. {
  4253. hif_print_napi_stats(soc->hif_handle);
  4254. }
  4255. /*
  4256. * dp_print_per_ring_stats(): Packet count per ring
  4257. * @soc - soc handle
  4258. */
  4259. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4260. {
  4261. uint8_t core, ring;
  4262. uint64_t total_packets;
  4263. DP_TRACE(FATAL, "Reo packets per ring:");
  4264. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4265. total_packets = 0;
  4266. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4267. for (core = 0; core < NR_CPUS; core++) {
  4268. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4269. core, soc->stats.rx.ring_packets[core][ring]);
  4270. total_packets += soc->stats.rx.ring_packets[core][ring];
  4271. }
  4272. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4273. ring, total_packets);
  4274. }
  4275. }
  4276. /*
  4277. * dp_txrx_path_stats() - Function to display dump stats
  4278. * @soc - soc handle
  4279. *
  4280. * return: none
  4281. */
  4282. static void dp_txrx_path_stats(struct dp_soc *soc)
  4283. {
  4284. uint8_t error_code;
  4285. uint8_t loop_pdev;
  4286. struct dp_pdev *pdev;
  4287. uint8_t i;
  4288. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4289. pdev = soc->pdev_list[loop_pdev];
  4290. dp_aggregate_pdev_stats(pdev);
  4291. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4292. "Tx path Statistics:");
  4293. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4294. pdev->stats.tx_i.rcvd.num,
  4295. pdev->stats.tx_i.rcvd.bytes);
  4296. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4297. pdev->stats.tx_i.processed.num,
  4298. pdev->stats.tx_i.processed.bytes);
  4299. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4300. pdev->stats.tx.tx_success.num,
  4301. pdev->stats.tx.tx_success.bytes);
  4302. DP_TRACE(FATAL, "Dropped in host:");
  4303. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4304. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4305. DP_TRACE(FATAL, "Descriptor not available: %u",
  4306. pdev->stats.tx_i.dropped.desc_na);
  4307. DP_TRACE(FATAL, "Ring full: %u",
  4308. pdev->stats.tx_i.dropped.ring_full);
  4309. DP_TRACE(FATAL, "Enqueue fail: %u",
  4310. pdev->stats.tx_i.dropped.enqueue_fail);
  4311. DP_TRACE(FATAL, "DMA Error: %u",
  4312. pdev->stats.tx_i.dropped.dma_error);
  4313. DP_TRACE(FATAL, "Dropped in hardware:");
  4314. DP_TRACE(FATAL, "total packets dropped: %u",
  4315. pdev->stats.tx.tx_failed);
  4316. DP_TRACE(FATAL, "mpdu age out: %u",
  4317. pdev->stats.tx.dropped.age_out);
  4318. DP_TRACE(FATAL, "firmware removed: %u",
  4319. pdev->stats.tx.dropped.fw_rem);
  4320. DP_TRACE(FATAL, "firmware removed tx: %u",
  4321. pdev->stats.tx.dropped.fw_rem_tx);
  4322. DP_TRACE(FATAL, "firmware removed notx %u",
  4323. pdev->stats.tx.dropped.fw_rem_notx);
  4324. DP_TRACE(FATAL, "peer_invalid: %u",
  4325. pdev->soc->stats.tx.tx_invalid_peer.num);
  4326. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4327. DP_TRACE(FATAL, "Single Packet: %u",
  4328. pdev->stats.tx_comp_histogram.pkts_1);
  4329. DP_TRACE(FATAL, "2-20 Packets: %u",
  4330. pdev->stats.tx_comp_histogram.pkts_2_20);
  4331. DP_TRACE(FATAL, "21-40 Packets: %u",
  4332. pdev->stats.tx_comp_histogram.pkts_21_40);
  4333. DP_TRACE(FATAL, "41-60 Packets: %u",
  4334. pdev->stats.tx_comp_histogram.pkts_41_60);
  4335. DP_TRACE(FATAL, "61-80 Packets: %u",
  4336. pdev->stats.tx_comp_histogram.pkts_61_80);
  4337. DP_TRACE(FATAL, "81-100 Packets: %u",
  4338. pdev->stats.tx_comp_histogram.pkts_81_100);
  4339. DP_TRACE(FATAL, "101-200 Packets: %u",
  4340. pdev->stats.tx_comp_histogram.pkts_101_200);
  4341. DP_TRACE(FATAL, " 201+ Packets: %u",
  4342. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4343. DP_TRACE(FATAL, "Rx path statistics");
  4344. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4345. pdev->stats.rx.to_stack.num,
  4346. pdev->stats.rx.to_stack.bytes);
  4347. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4348. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4349. i, pdev->stats.rx.rcvd_reo[i].num,
  4350. pdev->stats.rx.rcvd_reo[i].bytes);
  4351. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4352. pdev->stats.rx.intra_bss.pkts.num,
  4353. pdev->stats.rx.intra_bss.pkts.bytes);
  4354. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4355. pdev->stats.rx.raw.num,
  4356. pdev->stats.rx.raw.bytes);
  4357. DP_TRACE(FATAL, "dropped: error %u msdus",
  4358. pdev->stats.rx.err.mic_err);
  4359. DP_TRACE(FATAL, "peer invalid %u",
  4360. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4361. DP_TRACE(FATAL, "Reo Statistics");
  4362. DP_TRACE(FATAL, "rbm error: %u msdus",
  4363. pdev->soc->stats.rx.err.invalid_rbm);
  4364. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4365. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4366. DP_TRACE(FATAL, "Reo errors");
  4367. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4368. error_code++) {
  4369. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4370. error_code,
  4371. pdev->soc->stats.rx.err.reo_error[error_code]);
  4372. }
  4373. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4374. error_code++) {
  4375. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4376. error_code,
  4377. pdev->soc->stats.rx.err
  4378. .rxdma_error[error_code]);
  4379. }
  4380. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4381. DP_TRACE(FATAL, "Single Packet: %u",
  4382. pdev->stats.rx_ind_histogram.pkts_1);
  4383. DP_TRACE(FATAL, "2-20 Packets: %u",
  4384. pdev->stats.rx_ind_histogram.pkts_2_20);
  4385. DP_TRACE(FATAL, "21-40 Packets: %u",
  4386. pdev->stats.rx_ind_histogram.pkts_21_40);
  4387. DP_TRACE(FATAL, "41-60 Packets: %u",
  4388. pdev->stats.rx_ind_histogram.pkts_41_60);
  4389. DP_TRACE(FATAL, "61-80 Packets: %u",
  4390. pdev->stats.rx_ind_histogram.pkts_61_80);
  4391. DP_TRACE(FATAL, "81-100 Packets: %u",
  4392. pdev->stats.rx_ind_histogram.pkts_81_100);
  4393. DP_TRACE(FATAL, "101-200 Packets: %u",
  4394. pdev->stats.rx_ind_histogram.pkts_101_200);
  4395. DP_TRACE(FATAL, " 201+ Packets: %u",
  4396. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4397. DP_TRACE_STATS(ERROR, "%s: tso_enable: %u lro_enable: %u rx_hash: %u napi_enable: %u",
  4398. __func__,
  4399. pdev->soc->wlan_cfg_ctx->tso_enabled,
  4400. pdev->soc->wlan_cfg_ctx->lro_enabled,
  4401. pdev->soc->wlan_cfg_ctx->rx_hash,
  4402. pdev->soc->wlan_cfg_ctx->napi_enabled);
  4403. }
  4404. }
  4405. /*
  4406. * dp_txrx_dump_stats() - Dump statistics
  4407. * @value - Statistics option
  4408. */
  4409. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4410. {
  4411. struct dp_soc *soc =
  4412. (struct dp_soc *)psoc;
  4413. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4414. if (!soc) {
  4415. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4416. "%s: soc is NULL", __func__);
  4417. return QDF_STATUS_E_INVAL;
  4418. }
  4419. switch (value) {
  4420. case CDP_TXRX_PATH_STATS:
  4421. dp_txrx_path_stats(soc);
  4422. break;
  4423. case CDP_RX_RING_STATS:
  4424. dp_print_per_ring_stats(soc);
  4425. break;
  4426. case CDP_TXRX_TSO_STATS:
  4427. /* TODO: NOT IMPLEMENTED */
  4428. break;
  4429. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4430. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4431. break;
  4432. case CDP_DP_NAPI_STATS:
  4433. dp_print_napi_stats(soc);
  4434. break;
  4435. case CDP_TXRX_DESC_STATS:
  4436. /* TODO: NOT IMPLEMENTED */
  4437. break;
  4438. default:
  4439. status = QDF_STATUS_E_INVAL;
  4440. break;
  4441. }
  4442. return status;
  4443. }
  4444. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4445. /**
  4446. * dp_update_flow_control_parameters() - API to store datapath
  4447. * config parameters
  4448. * @soc: soc handle
  4449. * @cfg: ini parameter handle
  4450. *
  4451. * Return: void
  4452. */
  4453. static inline
  4454. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4455. struct cdp_config_params *params)
  4456. {
  4457. soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold =
  4458. params->tx_flow_stop_queue_threshold;
  4459. soc->wlan_cfg_ctx->tx_flow_start_queue_offset =
  4460. params->tx_flow_start_queue_offset;
  4461. }
  4462. #else
  4463. static inline
  4464. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4465. struct cdp_config_params *params)
  4466. {
  4467. }
  4468. #endif
  4469. /**
  4470. * dp_update_config_parameters() - API to store datapath
  4471. * config parameters
  4472. * @soc: soc handle
  4473. * @cfg: ini parameter handle
  4474. *
  4475. * Return: status
  4476. */
  4477. static
  4478. QDF_STATUS dp_update_config_parameters(struct cdp_soc *psoc,
  4479. struct cdp_config_params *params)
  4480. {
  4481. struct dp_soc *soc = (struct dp_soc *)psoc;
  4482. if (!(soc)) {
  4483. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4484. "%s: Invalid handle", __func__);
  4485. return QDF_STATUS_E_INVAL;
  4486. }
  4487. soc->wlan_cfg_ctx->tso_enabled = params->tso_enable;
  4488. soc->wlan_cfg_ctx->lro_enabled = params->lro_enable;
  4489. soc->wlan_cfg_ctx->rx_hash = params->flow_steering_enable;
  4490. soc->wlan_cfg_ctx->tcp_udp_checksumoffload =
  4491. params->tcp_udp_checksumoffload;
  4492. soc->wlan_cfg_ctx->napi_enabled = params->napi_enable;
  4493. dp_update_flow_control_parameters(soc, params);
  4494. return QDF_STATUS_SUCCESS;
  4495. }
  4496. static struct cdp_wds_ops dp_ops_wds = {
  4497. .vdev_set_wds = dp_vdev_set_wds,
  4498. };
  4499. /*
  4500. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4501. * @soc - datapath soc handle
  4502. * @peer - datapath peer handle
  4503. *
  4504. * Delete the AST entries belonging to a peer
  4505. */
  4506. #ifdef FEATURE_WDS
  4507. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4508. struct dp_peer *peer)
  4509. {
  4510. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4511. qdf_spin_lock_bh(&soc->ast_lock);
  4512. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4513. if (ast_entry->next_hop) {
  4514. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4515. peer->vdev->pdev->osif_pdev,
  4516. ast_entry->mac_addr.raw);
  4517. }
  4518. dp_peer_del_ast(soc, ast_entry);
  4519. }
  4520. qdf_spin_unlock_bh(&soc->ast_lock);
  4521. }
  4522. #else
  4523. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4524. struct dp_peer *peer)
  4525. {
  4526. }
  4527. #endif
  4528. #ifdef CONFIG_WIN
  4529. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4530. {
  4531. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4532. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4533. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4534. dp_peer_delete_ast_entries(soc, peer);
  4535. }
  4536. #endif
  4537. static struct cdp_cmn_ops dp_ops_cmn = {
  4538. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4539. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4540. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4541. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4542. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4543. .txrx_peer_create = dp_peer_create_wifi3,
  4544. .txrx_peer_setup = dp_peer_setup_wifi3,
  4545. #ifdef CONFIG_WIN
  4546. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4547. #else
  4548. .txrx_peer_teardown = NULL,
  4549. #endif
  4550. .txrx_peer_delete = dp_peer_delete_wifi3,
  4551. .txrx_vdev_register = dp_vdev_register_wifi3,
  4552. .txrx_soc_detach = dp_soc_detach_wifi3,
  4553. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4554. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4555. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4556. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4557. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4558. .delba_process = dp_delba_process_wifi3,
  4559. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4560. .flush_cache_rx_queue = NULL,
  4561. /* TODO: get API's for dscp-tid need to be added*/
  4562. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4563. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4564. .txrx_stats = dp_txrx_stats,
  4565. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4566. .display_stats = dp_txrx_dump_stats,
  4567. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4568. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4569. #ifdef DP_INTR_POLL_BASED
  4570. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4571. #else
  4572. .txrx_intr_attach = dp_soc_interrupt_attach,
  4573. #endif
  4574. .txrx_intr_detach = dp_soc_interrupt_detach,
  4575. .set_pn_check = dp_set_pn_check_wifi3,
  4576. .update_config_parameters = dp_update_config_parameters,
  4577. /* TODO: Add other functions */
  4578. };
  4579. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4580. .txrx_peer_authorize = dp_peer_authorize,
  4581. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4582. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4583. #ifdef MESH_MODE_SUPPORT
  4584. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4585. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4586. #endif
  4587. .txrx_set_vdev_param = dp_set_vdev_param,
  4588. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4589. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4590. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4591. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4592. .txrx_update_filter_neighbour_peers =
  4593. dp_update_filter_neighbour_peers,
  4594. .txrx_get_sec_type = dp_get_sec_type,
  4595. /* TODO: Add other functions */
  4596. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4597. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4598. };
  4599. static struct cdp_me_ops dp_ops_me = {
  4600. #ifdef ATH_SUPPORT_IQUE
  4601. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4602. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4603. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4604. #endif
  4605. };
  4606. static struct cdp_mon_ops dp_ops_mon = {
  4607. .txrx_monitor_set_filter_ucast_data = NULL,
  4608. .txrx_monitor_set_filter_mcast_data = NULL,
  4609. .txrx_monitor_set_filter_non_data = NULL,
  4610. .txrx_monitor_get_filter_ucast_data = NULL,
  4611. .txrx_monitor_get_filter_mcast_data = NULL,
  4612. .txrx_monitor_get_filter_non_data = NULL,
  4613. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4614. };
  4615. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4616. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4617. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4618. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4619. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4620. /* TODO */
  4621. };
  4622. static struct cdp_raw_ops dp_ops_raw = {
  4623. /* TODO */
  4624. };
  4625. #ifdef CONFIG_WIN
  4626. static struct cdp_pflow_ops dp_ops_pflow = {
  4627. /* TODO */
  4628. };
  4629. #endif /* CONFIG_WIN */
  4630. #ifdef FEATURE_RUNTIME_PM
  4631. /**
  4632. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4633. * @opaque_pdev: DP pdev context
  4634. *
  4635. * DP is ready to runtime suspend if there are no pending TX packets.
  4636. *
  4637. * Return: QDF_STATUS
  4638. */
  4639. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4640. {
  4641. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4642. struct dp_soc *soc = pdev->soc;
  4643. /* Call DP TX flow control API to check if there is any
  4644. pending packets */
  4645. if (soc->intr_mode == DP_INTR_POLL)
  4646. qdf_timer_stop(&soc->int_timer);
  4647. return QDF_STATUS_SUCCESS;
  4648. }
  4649. /**
  4650. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4651. * @opaque_pdev: DP pdev context
  4652. *
  4653. * Resume DP for runtime PM.
  4654. *
  4655. * Return: QDF_STATUS
  4656. */
  4657. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4658. {
  4659. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4660. struct dp_soc *soc = pdev->soc;
  4661. void *hal_srng;
  4662. int i;
  4663. if (soc->intr_mode == DP_INTR_POLL)
  4664. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4665. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4666. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4667. if (hal_srng) {
  4668. /* We actually only need to acquire the lock */
  4669. hal_srng_access_start(soc->hal_soc, hal_srng);
  4670. /* Update SRC ring head pointer for HW to send
  4671. all pending packets */
  4672. hal_srng_access_end(soc->hal_soc, hal_srng);
  4673. }
  4674. }
  4675. return QDF_STATUS_SUCCESS;
  4676. }
  4677. #endif /* FEATURE_RUNTIME_PM */
  4678. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4679. {
  4680. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4681. struct dp_soc *soc = pdev->soc;
  4682. if (soc->intr_mode == DP_INTR_POLL)
  4683. qdf_timer_stop(&soc->int_timer);
  4684. return QDF_STATUS_SUCCESS;
  4685. }
  4686. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4687. {
  4688. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4689. struct dp_soc *soc = pdev->soc;
  4690. if (soc->intr_mode == DP_INTR_POLL)
  4691. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4692. return QDF_STATUS_SUCCESS;
  4693. }
  4694. #ifndef CONFIG_WIN
  4695. static struct cdp_misc_ops dp_ops_misc = {
  4696. .get_opmode = dp_get_opmode,
  4697. #ifdef FEATURE_RUNTIME_PM
  4698. .runtime_suspend = dp_runtime_suspend,
  4699. .runtime_resume = dp_runtime_resume,
  4700. #endif /* FEATURE_RUNTIME_PM */
  4701. };
  4702. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4703. /* WIFI 3.0 DP implement as required. */
  4704. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4705. .register_pause_cb = dp_txrx_register_pause_cb,
  4706. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4707. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4708. };
  4709. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4710. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4711. };
  4712. #ifdef IPA_OFFLOAD
  4713. static struct cdp_ipa_ops dp_ops_ipa = {
  4714. .ipa_get_resource = dp_ipa_get_resource,
  4715. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4716. .ipa_op_response = dp_ipa_op_response,
  4717. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4718. .ipa_get_stat = dp_ipa_get_stat,
  4719. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4720. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4721. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4722. .ipa_setup = dp_ipa_setup,
  4723. .ipa_cleanup = dp_ipa_cleanup,
  4724. .ipa_setup_iface = dp_ipa_setup_iface,
  4725. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4726. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4727. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4728. .ipa_set_perf_level = dp_ipa_set_perf_level
  4729. };
  4730. #endif
  4731. static struct cdp_bus_ops dp_ops_bus = {
  4732. .bus_suspend = dp_bus_suspend,
  4733. .bus_resume = dp_bus_resume
  4734. };
  4735. static struct cdp_ocb_ops dp_ops_ocb = {
  4736. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4737. };
  4738. static struct cdp_throttle_ops dp_ops_throttle = {
  4739. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4740. };
  4741. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4742. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4743. };
  4744. static struct cdp_cfg_ops dp_ops_cfg = {
  4745. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4746. };
  4747. static struct cdp_peer_ops dp_ops_peer = {
  4748. .register_peer = dp_register_peer,
  4749. .clear_peer = dp_clear_peer,
  4750. .find_peer_by_addr = dp_find_peer_by_addr,
  4751. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4752. .local_peer_id = dp_local_peer_id,
  4753. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4754. .peer_state_update = dp_peer_state_update,
  4755. .get_vdevid = dp_get_vdevid,
  4756. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4757. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4758. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4759. .get_peer_state = dp_get_peer_state,
  4760. .last_assoc_received = dp_get_last_assoc_received,
  4761. .last_disassoc_received = dp_get_last_disassoc_received,
  4762. .last_deauth_received = dp_get_last_deauth_received,
  4763. };
  4764. #endif
  4765. static struct cdp_ops dp_txrx_ops = {
  4766. .cmn_drv_ops = &dp_ops_cmn,
  4767. .ctrl_ops = &dp_ops_ctrl,
  4768. .me_ops = &dp_ops_me,
  4769. .mon_ops = &dp_ops_mon,
  4770. .host_stats_ops = &dp_ops_host_stats,
  4771. .wds_ops = &dp_ops_wds,
  4772. .raw_ops = &dp_ops_raw,
  4773. #ifdef CONFIG_WIN
  4774. .pflow_ops = &dp_ops_pflow,
  4775. #endif /* CONFIG_WIN */
  4776. #ifndef CONFIG_WIN
  4777. .misc_ops = &dp_ops_misc,
  4778. .cfg_ops = &dp_ops_cfg,
  4779. .flowctl_ops = &dp_ops_flowctl,
  4780. .l_flowctl_ops = &dp_ops_l_flowctl,
  4781. #ifdef IPA_OFFLOAD
  4782. .ipa_ops = &dp_ops_ipa,
  4783. #endif
  4784. .bus_ops = &dp_ops_bus,
  4785. .ocb_ops = &dp_ops_ocb,
  4786. .peer_ops = &dp_ops_peer,
  4787. .throttle_ops = &dp_ops_throttle,
  4788. .mob_stats_ops = &dp_ops_mob_stats,
  4789. #endif
  4790. };
  4791. /*
  4792. * dp_soc_set_txrx_ring_map()
  4793. * @dp_soc: DP handler for soc
  4794. *
  4795. * Return: Void
  4796. */
  4797. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4798. {
  4799. uint32_t i;
  4800. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4801. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4802. }
  4803. }
  4804. /*
  4805. * dp_soc_attach_wifi3() - Attach txrx SOC
  4806. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4807. * @htc_handle: Opaque HTC handle
  4808. * @hif_handle: Opaque HIF handle
  4809. * @qdf_osdev: QDF device
  4810. *
  4811. * Return: DP SOC handle on success, NULL on failure
  4812. */
  4813. /*
  4814. * Local prototype added to temporarily address warning caused by
  4815. * -Wmissing-prototypes. A more correct solution, namely to expose
  4816. * a prototype in an appropriate header file, will come later.
  4817. */
  4818. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4819. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4820. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4821. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4822. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4823. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4824. {
  4825. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4826. if (!soc) {
  4827. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4828. FL("DP SOC memory allocation failed"));
  4829. goto fail0;
  4830. }
  4831. soc->cdp_soc.ops = &dp_txrx_ops;
  4832. soc->cdp_soc.ol_ops = ol_ops;
  4833. soc->osif_soc = osif_soc;
  4834. soc->osdev = qdf_osdev;
  4835. soc->hif_handle = hif_handle;
  4836. soc->psoc = psoc;
  4837. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4838. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4839. soc->hal_soc, qdf_osdev);
  4840. if (!soc->htt_handle) {
  4841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4842. FL("HTT attach failed"));
  4843. goto fail1;
  4844. }
  4845. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4846. if (!soc->wlan_cfg_ctx) {
  4847. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4848. FL("wlan_cfg_soc_attach failed"));
  4849. goto fail2;
  4850. }
  4851. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4852. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4853. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4854. CDP_CFG_MAX_PEER_ID);
  4855. if (ret != -EINVAL) {
  4856. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4857. }
  4858. }
  4859. qdf_spinlock_create(&soc->peer_ref_mutex);
  4860. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4861. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4862. /* fill the tx/rx cpu ring map*/
  4863. dp_soc_set_txrx_ring_map(soc);
  4864. qdf_spinlock_create(&soc->htt_stats.lock);
  4865. /* initialize work queue for stats processing */
  4866. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4867. return (void *)soc;
  4868. fail2:
  4869. htt_soc_detach(soc->htt_handle);
  4870. fail1:
  4871. qdf_mem_free(soc);
  4872. fail0:
  4873. return NULL;
  4874. }
  4875. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4876. /*
  4877. * dp_set_pktlog_wifi3() - attach txrx vdev
  4878. * @pdev: Datapath PDEV handle
  4879. * @event: which event's notifications are being subscribed to
  4880. * @enable: WDI event subscribe or not. (True or False)
  4881. *
  4882. * Return: Success, NULL on failure
  4883. */
  4884. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4885. bool enable)
  4886. {
  4887. struct dp_soc *soc = pdev->soc;
  4888. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4889. if (enable) {
  4890. switch (event) {
  4891. case WDI_EVENT_RX_DESC:
  4892. if (pdev->monitor_vdev) {
  4893. /* Nothing needs to be done if monitor mode is
  4894. * enabled
  4895. */
  4896. return 0;
  4897. }
  4898. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4899. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4900. htt_tlv_filter.mpdu_start = 1;
  4901. htt_tlv_filter.msdu_start = 1;
  4902. htt_tlv_filter.msdu_end = 1;
  4903. htt_tlv_filter.mpdu_end = 1;
  4904. htt_tlv_filter.packet_header = 1;
  4905. htt_tlv_filter.attention = 1;
  4906. htt_tlv_filter.ppdu_start = 1;
  4907. htt_tlv_filter.ppdu_end = 1;
  4908. htt_tlv_filter.ppdu_end_user_stats = 1;
  4909. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4910. htt_tlv_filter.ppdu_end_status_done = 1;
  4911. htt_tlv_filter.enable_fp = 1;
  4912. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4913. pdev->pdev_id,
  4914. pdev->rxdma_mon_status_ring.hal_srng,
  4915. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4916. &htt_tlv_filter);
  4917. }
  4918. break;
  4919. case WDI_EVENT_LITE_RX:
  4920. if (pdev->monitor_vdev) {
  4921. /* Nothing needs to be done if monitor mode is
  4922. * enabled
  4923. */
  4924. return 0;
  4925. }
  4926. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4927. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4928. htt_tlv_filter.ppdu_start = 1;
  4929. htt_tlv_filter.ppdu_end = 1;
  4930. htt_tlv_filter.ppdu_end_user_stats = 1;
  4931. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4932. htt_tlv_filter.ppdu_end_status_done = 1;
  4933. htt_tlv_filter.enable_fp = 1;
  4934. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4935. pdev->pdev_id,
  4936. pdev->rxdma_mon_status_ring.hal_srng,
  4937. RXDMA_MONITOR_STATUS,
  4938. RX_BUFFER_SIZE_PKTLOG_LITE,
  4939. &htt_tlv_filter);
  4940. }
  4941. break;
  4942. case WDI_EVENT_LITE_T2H:
  4943. if (pdev->monitor_vdev) {
  4944. /* Nothing needs to be done if monitor mode is
  4945. * enabled
  4946. */
  4947. return 0;
  4948. }
  4949. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4950. * passing value 0xffff. Once these macros will define in htt
  4951. * header file will use proper macros
  4952. */
  4953. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4954. break;
  4955. default:
  4956. /* Nothing needs to be done for other pktlog types */
  4957. break;
  4958. }
  4959. } else {
  4960. switch (event) {
  4961. case WDI_EVENT_RX_DESC:
  4962. case WDI_EVENT_LITE_RX:
  4963. if (pdev->monitor_vdev) {
  4964. /* Nothing needs to be done if monitor mode is
  4965. * enabled
  4966. */
  4967. return 0;
  4968. }
  4969. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4970. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4971. /* htt_tlv_filter is initialized to 0 */
  4972. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4973. pdev->pdev_id,
  4974. pdev->rxdma_mon_status_ring.hal_srng,
  4975. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4976. &htt_tlv_filter);
  4977. }
  4978. break;
  4979. case WDI_EVENT_LITE_T2H:
  4980. if (pdev->monitor_vdev) {
  4981. /* Nothing needs to be done if monitor mode is
  4982. * enabled
  4983. */
  4984. return 0;
  4985. }
  4986. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4987. * passing value 0. Once these macros will define in htt
  4988. * header file will use proper macros
  4989. */
  4990. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4991. break;
  4992. default:
  4993. /* Nothing needs to be done for other pktlog types */
  4994. break;
  4995. }
  4996. }
  4997. return 0;
  4998. }
  4999. #endif