8fdc77b72c
New hardware header files for Napier E6. CRs-Fixed: 2033542 Change-Id: I996dbff402c2ba27c2e34ba89cdbb60101ae7d2d
408 行
12 KiB
C
可执行文件
408 行
12 KiB
C
可执行文件
/*
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* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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//
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// DO NOT EDIT! This file is automatically generated
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// These definitions are tied to a particular hardware layout
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#ifndef _TCL_GSE_CMD_H_
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#define _TCL_GSE_CMD_H_
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#if !defined(__ASSEMBLER__)
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#endif
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// ################ START SUMMARY #################
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//
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// Dword Fields
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// 0 control_buffer_addr_31_0[31:0]
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// 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], reserved_1a[31:15]
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// 2 cmd_meta_data_31_0[31:0]
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// 3 cmd_meta_data_63_32[31:0]
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// 4 reserved_4a[31:0]
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// 5 reserved_5a[31:0]
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// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
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//
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// ################ END SUMMARY #################
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#define NUM_OF_DWORDS_TCL_GSE_CMD 7
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struct tcl_gse_cmd {
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uint32_t control_buffer_addr_31_0 : 32; //[31:0]
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uint32_t control_buffer_addr_39_32 : 8, //[7:0]
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gse_ctrl : 4, //[11:8]
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gse_sel : 1, //[12]
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status_destination_ring_id : 1, //[13]
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swap : 1, //[14]
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reserved_1a : 17; //[31:15]
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uint32_t cmd_meta_data_31_0 : 32; //[31:0]
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uint32_t cmd_meta_data_63_32 : 32; //[31:0]
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uint32_t reserved_4a : 32; //[31:0]
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uint32_t reserved_5a : 32; //[31:0]
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uint32_t reserved_6a : 20, //[19:0]
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ring_id : 8, //[27:20]
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looping_count : 4; //[31:28]
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};
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/*
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control_buffer_addr_31_0
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Address (lower 32 bits) of a control buffer containing
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additional info needed for this command execution.
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<legal all>
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control_buffer_addr_39_32
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Address (upper 8 bits) of a control buffer containing
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additional info needed for this command execution.
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<legal all>
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gse_ctrl
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GSE control operations. This includes cache operations
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and table entry statistics read/clear operation.
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<enum 0 rd_stat> Report or Read statistics
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<enum 1 srch_dis> Search disable. Report only Hash
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<enum 2 Wr_bk_single> Write Back single entry
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<enum 3 wr_bk_all> Write Back entire cache entry
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<enum 4 inval_single> Invalidate single cache entry
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<enum 5 inval_all> Invalidate entire cache
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<enum 6 wr_bk_inval_single> Write back and Invalidate
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single entry in cache
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<enum 7 wr_bk_inval_all> write back and invalidate
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entire cache
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<enum 8 clr_stat_single> Clear statistics for single
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entry
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<legal 0-8>
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Rest of the values reserved.
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For all single entry control operations (write back,
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Invalidate or both)Statistics will be reported
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gse_sel
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Bit to select the ASE or FSE to do the operation mention
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by GSE_ctrl bit
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0: FSE select
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1: ASE select
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status_destination_ring_id
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The TCL status ring to which the GSE status needs to be
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send.
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<enum 0 tcl_status_0_ring>
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<enum 1 tcl_status_1_ring>
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<legal all>
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swap
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Bit to enable byte swapping of contents of buffer
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<enum 0 Byte_swap_disable >
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<enum 1 byte_swap_enable >
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<legal all>
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reserved_1a
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<legal 0>
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cmd_meta_data_31_0
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Meta data to be returned in the status descriptor
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<legal all>
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cmd_meta_data_63_32
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Meta data to be returned in the status descriptor
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<legal all>
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reserved_4a
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<legal 0>
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reserved_5a
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<legal 0>
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reserved_6a
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<legal 0>
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ring_id
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Helps with debugging when dumping ring contents.
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<legal all>
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looping_count
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A count value that indicates the number of times the
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producer of entries into the Ring has looped around the
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ring.
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At initialization time, this value is set to 0. On the
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first loop, this value is set to 1. After the max value is
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reached allowed by the number of bits for this field, the
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count value continues with 0 again.
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In case SW is the consumer of the ring entries, it can
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use this field to figure out up to where the producer of
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entries has created new entries. This eliminates the need to
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check where the head pointer' of the ring is located once
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the SW starts processing an interrupt indicating that new
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entries have been put into this ring...
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Also note that SW if it wants only needs to look at the
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LSB bit of this count value.
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<legal all>
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*/
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/* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0
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Address (lower 32 bits) of a control buffer containing
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additional info needed for this command execution.
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<legal all>
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*/
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#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
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#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0
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#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
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/* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32
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Address (upper 8 bits) of a control buffer containing
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additional info needed for this command execution.
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<legal all>
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*/
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#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
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#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0
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#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
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/* Description TCL_GSE_CMD_1_GSE_CTRL
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GSE control operations. This includes cache operations
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and table entry statistics read/clear operation.
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<enum 0 rd_stat> Report or Read statistics
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<enum 1 srch_dis> Search disable. Report only Hash
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<enum 2 Wr_bk_single> Write Back single entry
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<enum 3 wr_bk_all> Write Back entire cache entry
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<enum 4 inval_single> Invalidate single cache entry
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<enum 5 inval_all> Invalidate entire cache
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<enum 6 wr_bk_inval_single> Write back and Invalidate
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single entry in cache
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<enum 7 wr_bk_inval_all> write back and invalidate
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entire cache
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<enum 8 clr_stat_single> Clear statistics for single
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entry
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<legal 0-8>
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Rest of the values reserved.
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For all single entry control operations (write back,
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Invalidate or both)Statistics will be reported
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*/
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#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004
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#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8
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#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00
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/* Description TCL_GSE_CMD_1_GSE_SEL
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Bit to select the ASE or FSE to do the operation mention
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by GSE_ctrl bit
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0: FSE select
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1: ASE select
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*/
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#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004
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#define TCL_GSE_CMD_1_GSE_SEL_LSB 12
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#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000
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/* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID
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The TCL status ring to which the GSE status needs to be
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send.
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<enum 0 tcl_status_0_ring>
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<enum 1 tcl_status_1_ring>
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<legal all>
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*/
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#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
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#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13
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#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000
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/* Description TCL_GSE_CMD_1_SWAP
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Bit to enable byte swapping of contents of buffer
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<enum 0 Byte_swap_disable >
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<enum 1 byte_swap_enable >
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<legal all>
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*/
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#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004
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#define TCL_GSE_CMD_1_SWAP_LSB 14
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#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000
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/* Description TCL_GSE_CMD_1_RESERVED_1A
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<legal 0>
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*/
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#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004
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#define TCL_GSE_CMD_1_RESERVED_1A_LSB 15
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#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xffff8000
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/* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0
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Meta data to be returned in the status descriptor
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<legal all>
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*/
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#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008
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#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0
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#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff
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/* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32
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Meta data to be returned in the status descriptor
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<legal all>
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*/
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#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c
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#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0
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#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff
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/* Description TCL_GSE_CMD_4_RESERVED_4A
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<legal 0>
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*/
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#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010
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#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0
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#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff
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/* Description TCL_GSE_CMD_5_RESERVED_5A
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<legal 0>
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*/
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#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014
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#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0
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#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff
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/* Description TCL_GSE_CMD_6_RESERVED_6A
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<legal 0>
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*/
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#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018
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#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0
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#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff
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/* Description TCL_GSE_CMD_6_RING_ID
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Helps with debugging when dumping ring contents.
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<legal all>
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*/
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#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018
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#define TCL_GSE_CMD_6_RING_ID_LSB 20
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#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000
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/* Description TCL_GSE_CMD_6_LOOPING_COUNT
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A count value that indicates the number of times the
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producer of entries into the Ring has looped around the
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ring.
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At initialization time, this value is set to 0. On the
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first loop, this value is set to 1. After the max value is
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reached allowed by the number of bits for this field, the
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count value continues with 0 again.
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In case SW is the consumer of the ring entries, it can
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use this field to figure out up to where the producer of
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entries has created new entries. This eliminates the need to
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check where the head pointer' of the ring is located once
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the SW starts processing an interrupt indicating that new
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entries have been put into this ring...
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Also note that SW if it wants only needs to look at the
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LSB bit of this count value.
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<legal all>
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*/
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#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
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#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28
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#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000
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#endif // _TCL_GSE_CMD_H_
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