c3b68397e5
Updating hardware header files for supporting 11ax monitor mode over E6 RTL supporting platform 2 (P2) CRs-Fixed: 2054860 Change-Id: I8f5f077ca46797c766d1a3d416390469a7bfabf0
459 строки
20 KiB
C
Исполняемый файл
459 строки
20 KiB
C
Исполняемый файл
/*
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* Copyright (c) 2017 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _PHYRX_PKT_END_INFO_H_
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#define _PHYRX_PKT_END_INFO_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "rx_location_info.h"
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#include "rx_timing_offset_info.h"
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#include "receive_rssi_info.h"
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// ################ START SUMMARY #################
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//
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// Dword Fields
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// 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[31:6]
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// 1 phy_timestamp_1_lower_32[31:0]
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// 2 phy_timestamp_1_upper_32[31:0]
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// 3 phy_timestamp_2_lower_32[31:0]
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// 4 phy_timestamp_2_upper_32[31:0]
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// 5-13 struct rx_location_info rx_location_info_details;
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// 14 struct rx_timing_offset_info rx_timing_offset_info_details;
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// 15-30 struct receive_rssi_info post_rssi_info_details;
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// 31 phy_sw_status_31_0[31:0]
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// 32 phy_sw_status_63_32[31:0]
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//
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// ################ END SUMMARY #################
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#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33
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struct phyrx_pkt_end_info {
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uint32_t phy_internal_nap : 1, //[0]
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location_info_valid : 1, //[1]
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timing_info_valid : 1, //[2]
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rssi_info_valid : 1, //[3]
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rx_frame_correction_needed : 1, //[4]
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frameless_frame_received : 1, //[5]
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reserved_0a : 26; //[31:6]
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uint32_t phy_timestamp_1_lower_32 : 32; //[31:0]
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uint32_t phy_timestamp_1_upper_32 : 32; //[31:0]
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uint32_t phy_timestamp_2_lower_32 : 32; //[31:0]
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uint32_t phy_timestamp_2_upper_32 : 32; //[31:0]
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struct rx_location_info rx_location_info_details;
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struct rx_timing_offset_info rx_timing_offset_info_details;
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struct receive_rssi_info post_rssi_info_details;
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uint32_t phy_sw_status_31_0 : 32; //[31:0]
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uint32_t phy_sw_status_63_32 : 32; //[31:0]
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};
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/*
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phy_internal_nap
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When set, PHY RX entered an internal NAP state, as PHY
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determined that this reception was not destined to this
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device
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location_info_valid
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Indicates that the RX_LOCATION_INFO structure later on
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in the TLV contains valid info
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timing_info_valid
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Indicates that the RX_TIMING_OFFSET_INFO structure later
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on in the TLV contains valid info
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rssi_info_valid
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Indicates that the RECEIVE_RSSI_INFO structure later on
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in the TLV contains valid info
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rx_frame_correction_needed
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When clear, no action is needed in the MAC.
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When set, the falling edge of the rx_frame happened 4us
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too late. MAC will need to compensate for this delay in
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order to maintain proper SIFS timing and/or not to get
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de-slotted.
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PHY uses this for very short 11a frames.
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When set, PHY will have passed this TLV to the MAC up to
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8 us into the 'real SIFS' time, and thus within 4us from the
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falling edge of the rx_frame.
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<legal all>
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frameless_frame_received
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When set, PHY has received the 'frameless frame' . Can
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be used in the 'MU-RTS -CTS exchange where CTS reception can
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be problematic.
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<legal all>
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reserved_0a
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<legal 0>
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phy_timestamp_1_lower_32
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TODO PHY: cleanup descriptionThe PHY timestamp in the
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AMPI of the first rising edge of rx_clear_pri after
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TX_PHY_DESC. . This field should set to 0 by the PHY and
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should be updated by the AMPI before being forwarded to the
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rest of the MAC. This field indicates the lower 32 bits of
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the timestamp
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phy_timestamp_1_upper_32
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TODO PHY: cleanup description
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The PHY timestamp in the AMPI of the first rising edge
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of rx_clear_pri after TX_PHY_DESC. This field should set to
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0 by the PHY and should be updated by the AMPI before being
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forwarded to the rest of the MAC. This field indicates the
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upper 32 bits of the timestamp
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phy_timestamp_2_lower_32
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TODO PHY: cleanup description
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The PHY timestamp in the AMPI of the rising edge of
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rx_clear_pri after RX_RSSI_LEGACY. This field should set to
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0 by the PHY and should be updated by the AMPI before being
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forwarded to the rest of the MAC. This field indicates the
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lower 32 bits of the timestamp
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phy_timestamp_2_upper_32
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TODO PHY: cleanup description
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The PHY timestamp in the AMPI of the rising edge of
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rx_clear_pri after RX_RSSI_LEGACY. This field should set to
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0 by the PHY and should be updated by the AMPI before being
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forwarded to the rest of the MAC. This field indicates the
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upper 32 bits of the timestamp
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struct rx_location_info rx_location_info_details
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Overview of location related info
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struct rx_timing_offset_info rx_timing_offset_info_details
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Overview of timing offset related info
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struct receive_rssi_info post_rssi_info_details
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Overview of the post-RSSI values.
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phy_sw_status_31_0
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Some PHY micro code status that can be put in here.
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Details of definition within SW specification
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This field can be used for debugging, FW - SW message
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exchange, etc.
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It could for example be a pointer to a DDR memory
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location where PHY FW put some debug info.
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<legal all>
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phy_sw_status_63_32
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Some PHY micro code status that can be put in here.
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Details of definition within SW specification
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This field can be used for debugging, FW - SW message
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exchange, etc.
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It could for example be a pointer to a DDR memory
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location where PHY FW put some debug info.
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<legal all>
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*/
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/* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP
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When set, PHY RX entered an internal NAP state, as PHY
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determined that this reception was not destined to this
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device
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*/
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#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000
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#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0
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#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001
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/* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID
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Indicates that the RX_LOCATION_INFO structure later on
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in the TLV contains valid info
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*/
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#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000
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#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1
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#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002
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/* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID
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Indicates that the RX_TIMING_OFFSET_INFO structure later
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on in the TLV contains valid info
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*/
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#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000
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#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2
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#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004
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/* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID
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Indicates that the RECEIVE_RSSI_INFO structure later on
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in the TLV contains valid info
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*/
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#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000
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#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3
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#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008
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/* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED
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When clear, no action is needed in the MAC.
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When set, the falling edge of the rx_frame happened 4us
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too late. MAC will need to compensate for this delay in
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order to maintain proper SIFS timing and/or not to get
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de-slotted.
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PHY uses this for very short 11a frames.
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When set, PHY will have passed this TLV to the MAC up to
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8 us into the 'real SIFS' time, and thus within 4us from the
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falling edge of the rx_frame.
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<legal all>
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*/
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#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000
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#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4
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#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010
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/* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED
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When set, PHY has received the 'frameless frame' . Can
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be used in the 'MU-RTS -CTS exchange where CTS reception can
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be problematic.
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<legal all>
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*/
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#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
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#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5
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#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
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/* Description PHYRX_PKT_END_INFO_0_RESERVED_0A
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<legal 0>
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*/
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#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000
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#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6
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#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0xffffffc0
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/* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32
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TODO PHY: cleanup descriptionThe PHY timestamp in the
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AMPI of the first rising edge of rx_clear_pri after
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TX_PHY_DESC. . This field should set to 0 by the PHY and
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should be updated by the AMPI before being forwarded to the
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rest of the MAC. This field indicates the lower 32 bits of
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the timestamp
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*/
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#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
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#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0
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#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
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/* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32
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TODO PHY: cleanup description
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The PHY timestamp in the AMPI of the first rising edge
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of rx_clear_pri after TX_PHY_DESC. This field should set to
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0 by the PHY and should be updated by the AMPI before being
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forwarded to the rest of the MAC. This field indicates the
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upper 32 bits of the timestamp
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*/
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#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
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#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0
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#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
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/* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32
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TODO PHY: cleanup description
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The PHY timestamp in the AMPI of the rising edge of
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rx_clear_pri after RX_RSSI_LEGACY. This field should set to
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0 by the PHY and should be updated by the AMPI before being
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forwarded to the rest of the MAC. This field indicates the
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lower 32 bits of the timestamp
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*/
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#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
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#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0
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#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
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/* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32
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TODO PHY: cleanup description
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The PHY timestamp in the AMPI of the rising edge of
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rx_clear_pri after RX_RSSI_LEGACY. This field should set to
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0 by the PHY and should be updated by the AMPI before being
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forwarded to the rest of the MAC. This field indicates the
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upper 32 bits of the timestamp
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*/
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#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
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#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0
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#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000014
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#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000018
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#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000001c
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#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000020
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#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000024
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#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000028
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#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000002c
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#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000030
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#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000034
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#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_OFFSET 0x00000038
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#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000003c
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#define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000040
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#define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000044
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#define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000048
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#define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000004c
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#define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
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#define PHYRX_PKT_END_INFO_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
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#define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000050
|
||
#define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000054
|
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#define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000058
|
||
#define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000005c
|
||
#define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000060
|
||
#define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000064
|
||
#define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000068
|
||
#define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000006c
|
||
#define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000070
|
||
#define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000074
|
||
#define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
#define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000078
|
||
#define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0
|
||
#define PHYRX_PKT_END_INFO_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff
|
||
|
||
/* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0
|
||
|
||
Some PHY micro code status that can be put in here.
|
||
Details of definition within SW specification
|
||
|
||
This field can be used for debugging, FW - SW message
|
||
exchange, etc.
|
||
|
||
It could for example be a pointer to a DDR memory
|
||
location where PHY FW put some debug info.
|
||
|
||
<legal all>
|
||
*/
|
||
#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c
|
||
#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0
|
||
#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff
|
||
|
||
/* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32
|
||
|
||
Some PHY micro code status that can be put in here.
|
||
Details of definition within SW specification
|
||
|
||
This field can be used for debugging, FW - SW message
|
||
exchange, etc.
|
||
|
||
It could for example be a pointer to a DDR memory
|
||
location where PHY FW put some debug info.
|
||
|
||
<legal all>
|
||
*/
|
||
#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080
|
||
#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0
|
||
#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff
|
||
|
||
|
||
#endif // _PHYRX_PKT_END_INFO_H_
|