sdm660-common.c 94 KB

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  1. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/input.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/of_device.h>
  17. #include <sound/pcm_params.h>
  18. #include <dsp/q6afe-v2.h>
  19. #include "msm-pcm-routing-v2.h"
  20. #include "sdm660-common.h"
  21. #include "sdm660-internal.h"
  22. #include "sdm660-external.h"
  23. #include "codecs/msm-cdc-pinctrl.h"
  24. #include "codecs/sdm660_cdc/msm-analog-cdc.h"
  25. #include "codecs/wsa881x.h"
  26. #define DRV_NAME "sdm660-asoc-snd"
  27. #define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
  28. #define PMIC_INT_ANALOG_CODEC "analog-codec"
  29. #define DEV_NAME_STR_LEN 32
  30. #define DEFAULT_MCLK_RATE 9600000
  31. struct dev_config {
  32. u32 sample_rate;
  33. u32 bit_format;
  34. u32 channels;
  35. };
  36. enum {
  37. DP_RX_IDX,
  38. EXT_DISP_RX_IDX_MAX,
  39. };
  40. bool codec_reg_done;
  41. /* TDM default config */
  42. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  43. { /* PRI TDM */
  44. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  45. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  46. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  47. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  48. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  49. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  50. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  51. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  52. },
  53. { /* SEC TDM */
  54. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  55. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  56. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  57. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  58. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  59. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  60. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  61. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  62. },
  63. { /* TERT TDM */
  64. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  65. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  66. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  67. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  68. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  69. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  70. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  71. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  72. },
  73. { /* QUAT TDM */
  74. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  75. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  76. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  77. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  78. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  79. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  80. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  81. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  82. },
  83. { /* QUIN TDM */
  84. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  85. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  86. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  87. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  88. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  89. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  90. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  91. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  92. }
  93. };
  94. /* TDM default config */
  95. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  96. { /* PRI TDM */
  97. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  98. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  99. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  100. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  101. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  102. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  103. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  104. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  105. },
  106. { /* SEC TDM */
  107. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  108. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  109. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  110. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  111. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  112. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  113. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  114. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  115. },
  116. { /* TERT TDM */
  117. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  118. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  119. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  120. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  121. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  122. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  123. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  124. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  125. },
  126. { /* QUAT TDM */
  127. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  128. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  129. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  130. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  131. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  132. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  133. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  134. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  135. },
  136. { /* QUIN TDM */
  137. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  138. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  139. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  140. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  141. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  142. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  143. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  144. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  145. }
  146. };
  147. /* Default configuration of external display BE */
  148. static struct dev_config ext_disp_rx_cfg[] = {
  149. [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  150. };
  151. static struct dev_config usb_rx_cfg = {
  152. .sample_rate = SAMPLING_RATE_48KHZ,
  153. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  154. .channels = 2,
  155. };
  156. static struct dev_config usb_tx_cfg = {
  157. .sample_rate = SAMPLING_RATE_48KHZ,
  158. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  159. .channels = 1,
  160. };
  161. enum {
  162. PRIM_MI2S = 0,
  163. SEC_MI2S,
  164. TERT_MI2S,
  165. QUAT_MI2S,
  166. QUIN_MI2S,
  167. MI2S_MAX,
  168. };
  169. enum {
  170. PRIM_AUX_PCM = 0,
  171. SEC_AUX_PCM,
  172. TERT_AUX_PCM,
  173. QUAT_AUX_PCM,
  174. QUIN_AUX_PCM,
  175. AUX_PCM_MAX,
  176. };
  177. enum {
  178. PCM_I2S_SEL_PRIM = 0,
  179. PCM_I2S_SEL_SEC,
  180. PCM_I2S_SEL_TERT,
  181. PCM_I2S_SEL_QUAT,
  182. PCM_I2S_SEL_QUIN,
  183. PCM_I2S_SEL_MAX,
  184. };
  185. struct mi2s_conf {
  186. struct mutex lock;
  187. u32 ref_cnt;
  188. u32 msm_is_mi2s_master;
  189. u32 msm_is_ext_mclk;
  190. };
  191. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  192. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  193. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  194. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  195. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  196. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  197. };
  198. struct msm_wsa881x_dev_info {
  199. struct device_node *of_node;
  200. u32 index;
  201. };
  202. static struct snd_soc_aux_dev *msm_aux_dev;
  203. static struct snd_soc_codec_conf *msm_codec_conf;
  204. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active);
  205. static struct wcd_mbhc_config mbhc_cfg = {
  206. .read_fw_bin = false,
  207. .calibration = NULL,
  208. .detect_extn_cable = true,
  209. .mono_stero_detection = false,
  210. .swap_gnd_mic = NULL,
  211. .hs_ext_micbias = true,
  212. .key_code[0] = KEY_MEDIA,
  213. .key_code[1] = KEY_VOICECOMMAND,
  214. .key_code[2] = KEY_VOLUMEUP,
  215. .key_code[3] = KEY_VOLUMEDOWN,
  216. .key_code[4] = 0,
  217. .key_code[5] = 0,
  218. .key_code[6] = 0,
  219. .key_code[7] = 0,
  220. .linein_th = 5000,
  221. .moisture_en = false,
  222. .mbhc_micbias = 0,
  223. .anc_micbias = 0,
  224. .enable_anc_mic_detect = false,
  225. };
  226. static struct dev_config proxy_rx_cfg = {
  227. .sample_rate = SAMPLING_RATE_48KHZ,
  228. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  229. .channels = 2,
  230. };
  231. /* Default configuration of MI2S channels */
  232. static struct dev_config mi2s_rx_cfg[] = {
  233. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  234. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  235. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  236. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  237. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  238. };
  239. static struct dev_config mi2s_tx_cfg[] = {
  240. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  241. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  242. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  243. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  244. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  245. };
  246. static struct dev_config aux_pcm_rx_cfg[] = {
  247. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  248. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  249. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  250. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  251. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  252. };
  253. static struct dev_config aux_pcm_tx_cfg[] = {
  254. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  255. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  256. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  257. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  258. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  259. };
  260. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  261. "Six", "Seven", "Eight"};
  262. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  263. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16",
  264. "KHZ_32", "KHZ_44P1", "KHZ_48",
  265. "KHZ_96", "KHZ_192"};
  266. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  267. "Five", "Six", "Seven",
  268. "Eight"};
  269. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  270. "S32_LE"};
  271. static char const *mi2s_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  272. "S32_LE"};
  273. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  274. "Five", "Six", "Seven", "Eight"};
  275. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  276. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  277. "KHZ_44P1", "KHZ_48", "KHZ_96",
  278. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  279. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  280. "Five", "Six", "Seven",
  281. "Eight"};
  282. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  283. "KHZ_16", "KHZ_22P05",
  284. "KHZ_32", "KHZ_44P1", "KHZ_48",
  285. "KHZ_96", "KHZ_192", "KHZ_384"};
  286. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE"};
  287. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  288. "KHZ_192"};
  289. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  290. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  291. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  292. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  293. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  294. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  295. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  296. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  297. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  298. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  299. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  300. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  301. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  302. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  303. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  304. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  305. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  306. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  307. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  308. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  309. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  310. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  311. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_format, mi2s_format_text);
  312. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_format, mi2s_format_text);
  313. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_format, mi2s_format_text);
  314. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_format, mi2s_format_text);
  315. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_format, mi2s_format_text);
  316. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_format, mi2s_format_text);
  317. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_format, mi2s_format_text);
  318. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_format, mi2s_format_text);
  319. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_format, mi2s_format_text);
  320. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_format, mi2s_format_text);
  321. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  322. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  323. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  324. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  325. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  326. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  327. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  328. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  329. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  330. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  331. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  332. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  333. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  334. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  335. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  336. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  337. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  338. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  339. ext_disp_sample_rate_text);
  340. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  341. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  342. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  343. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  344. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  345. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  346. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  347. {
  348. AFE_API_VERSION_I2S_CONFIG,
  349. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  350. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  351. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  352. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  353. 0,
  354. },
  355. {
  356. AFE_API_VERSION_I2S_CONFIG,
  357. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  358. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  359. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  360. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  361. 0,
  362. },
  363. {
  364. AFE_API_VERSION_I2S_CONFIG,
  365. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  366. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  367. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  368. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  369. 0,
  370. },
  371. {
  372. AFE_API_VERSION_I2S_CONFIG,
  373. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  374. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  375. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  376. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  377. 0,
  378. },
  379. {
  380. AFE_API_VERSION_I2S_CONFIG,
  381. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  382. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  383. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  384. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  385. 0,
  386. }
  387. };
  388. static struct afe_clk_set mi2s_mclk[MI2S_MAX] = {
  389. {
  390. AFE_API_VERSION_I2S_CONFIG,
  391. Q6AFE_LPASS_CLK_ID_MCLK_3,
  392. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  393. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  394. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  395. 0,
  396. },
  397. {
  398. AFE_API_VERSION_I2S_CONFIG,
  399. Q6AFE_LPASS_CLK_ID_MCLK_2,
  400. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  401. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  402. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  403. 0,
  404. },
  405. {
  406. AFE_API_VERSION_I2S_CONFIG,
  407. Q6AFE_LPASS_CLK_ID_MCLK_1,
  408. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  409. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  410. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  411. 0,
  412. },
  413. {
  414. AFE_API_VERSION_I2S_CONFIG,
  415. Q6AFE_LPASS_CLK_ID_MCLK_1,
  416. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  417. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  418. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  419. 0,
  420. },
  421. {
  422. AFE_API_VERSION_I2S_CONFIG,
  423. Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR,
  424. Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
  425. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  426. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  427. 0,
  428. }
  429. };
  430. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  431. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  432. struct snd_ctl_elem_value *ucontrol)
  433. {
  434. pr_debug("%s: proxy_rx channels = %d\n",
  435. __func__, proxy_rx_cfg.channels);
  436. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  437. return 0;
  438. }
  439. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  440. struct snd_ctl_elem_value *ucontrol)
  441. {
  442. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  443. pr_debug("%s: proxy_rx channels = %d\n",
  444. __func__, proxy_rx_cfg.channels);
  445. return 1;
  446. }
  447. static int tdm_get_sample_rate(int value)
  448. {
  449. int sample_rate = 0;
  450. switch (value) {
  451. case 0:
  452. sample_rate = SAMPLING_RATE_8KHZ;
  453. break;
  454. case 1:
  455. sample_rate = SAMPLING_RATE_16KHZ;
  456. break;
  457. case 2:
  458. sample_rate = SAMPLING_RATE_32KHZ;
  459. break;
  460. case 3:
  461. sample_rate = SAMPLING_RATE_44P1KHZ;
  462. break;
  463. case 4:
  464. sample_rate = SAMPLING_RATE_48KHZ;
  465. break;
  466. case 5:
  467. sample_rate = SAMPLING_RATE_96KHZ;
  468. break;
  469. case 6:
  470. sample_rate = SAMPLING_RATE_192KHZ;
  471. break;
  472. case 7:
  473. sample_rate = SAMPLING_RATE_352P8KHZ;
  474. break;
  475. case 8:
  476. sample_rate = SAMPLING_RATE_384KHZ;
  477. break;
  478. default:
  479. sample_rate = SAMPLING_RATE_48KHZ;
  480. break;
  481. }
  482. return sample_rate;
  483. }
  484. static int tdm_get_sample_rate_val(int sample_rate)
  485. {
  486. int sample_rate_val = 0;
  487. switch (sample_rate) {
  488. case SAMPLING_RATE_8KHZ:
  489. sample_rate_val = 0;
  490. break;
  491. case SAMPLING_RATE_16KHZ:
  492. sample_rate_val = 1;
  493. break;
  494. case SAMPLING_RATE_32KHZ:
  495. sample_rate_val = 2;
  496. break;
  497. case SAMPLING_RATE_44P1KHZ:
  498. sample_rate_val = 3;
  499. break;
  500. case SAMPLING_RATE_48KHZ:
  501. sample_rate_val = 4;
  502. break;
  503. case SAMPLING_RATE_96KHZ:
  504. sample_rate_val = 5;
  505. break;
  506. case SAMPLING_RATE_192KHZ:
  507. sample_rate_val = 6;
  508. break;
  509. case SAMPLING_RATE_352P8KHZ:
  510. sample_rate_val = 7;
  511. break;
  512. case SAMPLING_RATE_384KHZ:
  513. sample_rate_val = 8;
  514. break;
  515. default:
  516. sample_rate_val = 4;
  517. break;
  518. }
  519. return sample_rate_val;
  520. }
  521. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  522. struct tdm_port *port)
  523. {
  524. if (port) {
  525. if (strnstr(kcontrol->id.name, "PRI",
  526. sizeof(kcontrol->id.name))) {
  527. port->mode = TDM_PRI;
  528. } else if (strnstr(kcontrol->id.name, "SEC",
  529. sizeof(kcontrol->id.name))) {
  530. port->mode = TDM_SEC;
  531. } else if (strnstr(kcontrol->id.name, "TERT",
  532. sizeof(kcontrol->id.name))) {
  533. port->mode = TDM_TERT;
  534. } else if (strnstr(kcontrol->id.name, "QUAT",
  535. sizeof(kcontrol->id.name))) {
  536. port->mode = TDM_QUAT;
  537. } else if (strnstr(kcontrol->id.name, "QUIN",
  538. sizeof(kcontrol->id.name))) {
  539. port->mode = TDM_QUIN;
  540. } else {
  541. pr_err("%s: unsupported mode in: %s",
  542. __func__, kcontrol->id.name);
  543. return -EINVAL;
  544. }
  545. if (strnstr(kcontrol->id.name, "RX_0",
  546. sizeof(kcontrol->id.name)) ||
  547. strnstr(kcontrol->id.name, "TX_0",
  548. sizeof(kcontrol->id.name))) {
  549. port->channel = TDM_0;
  550. } else if (strnstr(kcontrol->id.name, "RX_1",
  551. sizeof(kcontrol->id.name)) ||
  552. strnstr(kcontrol->id.name, "TX_1",
  553. sizeof(kcontrol->id.name))) {
  554. port->channel = TDM_1;
  555. } else if (strnstr(kcontrol->id.name, "RX_2",
  556. sizeof(kcontrol->id.name)) ||
  557. strnstr(kcontrol->id.name, "TX_2",
  558. sizeof(kcontrol->id.name))) {
  559. port->channel = TDM_2;
  560. } else if (strnstr(kcontrol->id.name, "RX_3",
  561. sizeof(kcontrol->id.name)) ||
  562. strnstr(kcontrol->id.name, "TX_3",
  563. sizeof(kcontrol->id.name))) {
  564. port->channel = TDM_3;
  565. } else if (strnstr(kcontrol->id.name, "RX_4",
  566. sizeof(kcontrol->id.name)) ||
  567. strnstr(kcontrol->id.name, "TX_4",
  568. sizeof(kcontrol->id.name))) {
  569. port->channel = TDM_4;
  570. } else if (strnstr(kcontrol->id.name, "RX_5",
  571. sizeof(kcontrol->id.name)) ||
  572. strnstr(kcontrol->id.name, "TX_5",
  573. sizeof(kcontrol->id.name))) {
  574. port->channel = TDM_5;
  575. } else if (strnstr(kcontrol->id.name, "RX_6",
  576. sizeof(kcontrol->id.name)) ||
  577. strnstr(kcontrol->id.name, "TX_6",
  578. sizeof(kcontrol->id.name))) {
  579. port->channel = TDM_6;
  580. } else if (strnstr(kcontrol->id.name, "RX_7",
  581. sizeof(kcontrol->id.name)) ||
  582. strnstr(kcontrol->id.name, "TX_7",
  583. sizeof(kcontrol->id.name))) {
  584. port->channel = TDM_7;
  585. } else {
  586. pr_err("%s: unsupported channel in: %s",
  587. __func__, kcontrol->id.name);
  588. return -EINVAL;
  589. }
  590. } else
  591. return -EINVAL;
  592. return 0;
  593. }
  594. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  595. struct snd_ctl_elem_value *ucontrol)
  596. {
  597. struct tdm_port port;
  598. int ret = tdm_get_port_idx(kcontrol, &port);
  599. if (ret) {
  600. pr_err("%s: unsupported control: %s",
  601. __func__, kcontrol->id.name);
  602. } else {
  603. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  604. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  605. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  606. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  607. ucontrol->value.enumerated.item[0]);
  608. }
  609. return ret;
  610. }
  611. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  612. struct snd_ctl_elem_value *ucontrol)
  613. {
  614. struct tdm_port port;
  615. int ret = tdm_get_port_idx(kcontrol, &port);
  616. if (ret) {
  617. pr_err("%s: unsupported control: %s",
  618. __func__, kcontrol->id.name);
  619. } else {
  620. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  621. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  622. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  623. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  624. ucontrol->value.enumerated.item[0]);
  625. }
  626. return ret;
  627. }
  628. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  629. struct snd_ctl_elem_value *ucontrol)
  630. {
  631. struct tdm_port port;
  632. int ret = tdm_get_port_idx(kcontrol, &port);
  633. if (ret) {
  634. pr_err("%s: unsupported control: %s",
  635. __func__, kcontrol->id.name);
  636. } else {
  637. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  638. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  639. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  640. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  641. ucontrol->value.enumerated.item[0]);
  642. }
  643. return ret;
  644. }
  645. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  646. struct snd_ctl_elem_value *ucontrol)
  647. {
  648. struct tdm_port port;
  649. int ret = tdm_get_port_idx(kcontrol, &port);
  650. if (ret) {
  651. pr_err("%s: unsupported control: %s",
  652. __func__, kcontrol->id.name);
  653. } else {
  654. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  655. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  656. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  657. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  658. ucontrol->value.enumerated.item[0]);
  659. }
  660. return ret;
  661. }
  662. static int tdm_get_format(int value)
  663. {
  664. int format = 0;
  665. switch (value) {
  666. case 0:
  667. format = SNDRV_PCM_FORMAT_S16_LE;
  668. break;
  669. case 1:
  670. format = SNDRV_PCM_FORMAT_S24_LE;
  671. break;
  672. case 2:
  673. format = SNDRV_PCM_FORMAT_S32_LE;
  674. break;
  675. default:
  676. format = SNDRV_PCM_FORMAT_S16_LE;
  677. break;
  678. }
  679. return format;
  680. }
  681. static int tdm_get_format_val(int format)
  682. {
  683. int value = 0;
  684. switch (format) {
  685. case SNDRV_PCM_FORMAT_S16_LE:
  686. value = 0;
  687. break;
  688. case SNDRV_PCM_FORMAT_S24_LE:
  689. value = 1;
  690. break;
  691. case SNDRV_PCM_FORMAT_S32_LE:
  692. value = 2;
  693. break;
  694. default:
  695. value = 0;
  696. break;
  697. }
  698. return value;
  699. }
  700. static int mi2s_get_format(int value)
  701. {
  702. int format = 0;
  703. switch (value) {
  704. case 0:
  705. format = SNDRV_PCM_FORMAT_S16_LE;
  706. break;
  707. case 1:
  708. format = SNDRV_PCM_FORMAT_S24_LE;
  709. break;
  710. case 2:
  711. format = SNDRV_PCM_FORMAT_S24_3LE;
  712. break;
  713. case 3:
  714. format = SNDRV_PCM_FORMAT_S32_LE;
  715. break;
  716. default:
  717. format = SNDRV_PCM_FORMAT_S16_LE;
  718. break;
  719. }
  720. return format;
  721. }
  722. static int mi2s_get_format_value(int format)
  723. {
  724. int value = 0;
  725. switch (format) {
  726. case SNDRV_PCM_FORMAT_S16_LE:
  727. value = 0;
  728. break;
  729. case SNDRV_PCM_FORMAT_S24_LE:
  730. value = 1;
  731. break;
  732. case SNDRV_PCM_FORMAT_S24_3LE:
  733. value = 2;
  734. break;
  735. case SNDRV_PCM_FORMAT_S32_LE:
  736. value = 3;
  737. break;
  738. default:
  739. value = 0;
  740. break;
  741. }
  742. return value;
  743. }
  744. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  745. struct snd_ctl_elem_value *ucontrol)
  746. {
  747. struct tdm_port port;
  748. int ret = tdm_get_port_idx(kcontrol, &port);
  749. if (ret) {
  750. pr_err("%s: unsupported control: %s",
  751. __func__, kcontrol->id.name);
  752. } else {
  753. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  754. tdm_rx_cfg[port.mode][port.channel].bit_format);
  755. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  756. tdm_rx_cfg[port.mode][port.channel].bit_format,
  757. ucontrol->value.enumerated.item[0]);
  758. }
  759. return ret;
  760. }
  761. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  762. struct snd_ctl_elem_value *ucontrol)
  763. {
  764. struct tdm_port port;
  765. int ret = tdm_get_port_idx(kcontrol, &port);
  766. if (ret) {
  767. pr_err("%s: unsupported control: %s",
  768. __func__, kcontrol->id.name);
  769. } else {
  770. tdm_rx_cfg[port.mode][port.channel].bit_format =
  771. tdm_get_format(ucontrol->value.enumerated.item[0]);
  772. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  773. tdm_rx_cfg[port.mode][port.channel].bit_format,
  774. ucontrol->value.enumerated.item[0]);
  775. }
  776. return ret;
  777. }
  778. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  779. struct snd_ctl_elem_value *ucontrol)
  780. {
  781. struct tdm_port port;
  782. int ret = tdm_get_port_idx(kcontrol, &port);
  783. if (ret) {
  784. pr_err("%s: unsupported control: %s",
  785. __func__, kcontrol->id.name);
  786. } else {
  787. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  788. tdm_tx_cfg[port.mode][port.channel].bit_format);
  789. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  790. tdm_tx_cfg[port.mode][port.channel].bit_format,
  791. ucontrol->value.enumerated.item[0]);
  792. }
  793. return ret;
  794. }
  795. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  796. struct snd_ctl_elem_value *ucontrol)
  797. {
  798. struct tdm_port port;
  799. int ret = tdm_get_port_idx(kcontrol, &port);
  800. if (ret) {
  801. pr_err("%s: unsupported control: %s",
  802. __func__, kcontrol->id.name);
  803. } else {
  804. tdm_tx_cfg[port.mode][port.channel].bit_format =
  805. tdm_get_format(ucontrol->value.enumerated.item[0]);
  806. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  807. tdm_tx_cfg[port.mode][port.channel].bit_format,
  808. ucontrol->value.enumerated.item[0]);
  809. }
  810. return ret;
  811. }
  812. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  813. struct snd_ctl_elem_value *ucontrol)
  814. {
  815. struct tdm_port port;
  816. int ret = tdm_get_port_idx(kcontrol, &port);
  817. if (ret) {
  818. pr_err("%s: unsupported control: %s",
  819. __func__, kcontrol->id.name);
  820. } else {
  821. ucontrol->value.enumerated.item[0] =
  822. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  823. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  824. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  825. ucontrol->value.enumerated.item[0]);
  826. }
  827. return ret;
  828. }
  829. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  830. struct snd_ctl_elem_value *ucontrol)
  831. {
  832. struct tdm_port port;
  833. int ret = tdm_get_port_idx(kcontrol, &port);
  834. if (ret) {
  835. pr_err("%s: unsupported control: %s",
  836. __func__, kcontrol->id.name);
  837. } else {
  838. tdm_rx_cfg[port.mode][port.channel].channels =
  839. ucontrol->value.enumerated.item[0] + 1;
  840. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  841. tdm_rx_cfg[port.mode][port.channel].channels,
  842. ucontrol->value.enumerated.item[0] + 1);
  843. }
  844. return ret;
  845. }
  846. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  847. struct snd_ctl_elem_value *ucontrol)
  848. {
  849. struct tdm_port port;
  850. int ret = tdm_get_port_idx(kcontrol, &port);
  851. if (ret) {
  852. pr_err("%s: unsupported control: %s",
  853. __func__, kcontrol->id.name);
  854. } else {
  855. ucontrol->value.enumerated.item[0] =
  856. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  857. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  858. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  859. ucontrol->value.enumerated.item[0]);
  860. }
  861. return ret;
  862. }
  863. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  864. struct snd_ctl_elem_value *ucontrol)
  865. {
  866. struct tdm_port port;
  867. int ret = tdm_get_port_idx(kcontrol, &port);
  868. if (ret) {
  869. pr_err("%s: unsupported control: %s",
  870. __func__, kcontrol->id.name);
  871. } else {
  872. tdm_tx_cfg[port.mode][port.channel].channels =
  873. ucontrol->value.enumerated.item[0] + 1;
  874. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  875. tdm_tx_cfg[port.mode][port.channel].channels,
  876. ucontrol->value.enumerated.item[0] + 1);
  877. }
  878. return ret;
  879. }
  880. static int aux_pcm_get_sample_rate(int value)
  881. {
  882. int sample_rate;
  883. switch (value) {
  884. case 1:
  885. sample_rate = SAMPLING_RATE_16KHZ;
  886. break;
  887. case 0:
  888. default:
  889. sample_rate = SAMPLING_RATE_8KHZ;
  890. break;
  891. }
  892. return sample_rate;
  893. }
  894. static int aux_pcm_get_sample_rate_val(int sample_rate)
  895. {
  896. int sample_rate_val;
  897. switch (sample_rate) {
  898. case SAMPLING_RATE_16KHZ:
  899. sample_rate_val = 1;
  900. break;
  901. case SAMPLING_RATE_8KHZ:
  902. default:
  903. sample_rate_val = 0;
  904. break;
  905. }
  906. return sample_rate_val;
  907. }
  908. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  909. {
  910. int idx;
  911. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  912. sizeof("PRIM_AUX_PCM")))
  913. idx = PRIM_AUX_PCM;
  914. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  915. sizeof("SEC_AUX_PCM")))
  916. idx = SEC_AUX_PCM;
  917. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  918. sizeof("TERT_AUX_PCM")))
  919. idx = TERT_AUX_PCM;
  920. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  921. sizeof("QUAT_AUX_PCM")))
  922. idx = QUAT_AUX_PCM;
  923. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  924. sizeof("QUIN_AUX_PCM")))
  925. idx = QUIN_AUX_PCM;
  926. else {
  927. pr_err("%s: unsupported port: %s",
  928. __func__, kcontrol->id.name);
  929. idx = -EINVAL;
  930. }
  931. return idx;
  932. }
  933. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  934. struct snd_ctl_elem_value *ucontrol)
  935. {
  936. int idx = aux_pcm_get_port_idx(kcontrol);
  937. if (idx < 0)
  938. return idx;
  939. aux_pcm_rx_cfg[idx].sample_rate =
  940. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  941. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  942. idx, aux_pcm_rx_cfg[idx].sample_rate,
  943. ucontrol->value.enumerated.item[0]);
  944. return 0;
  945. }
  946. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  947. struct snd_ctl_elem_value *ucontrol)
  948. {
  949. int idx = aux_pcm_get_port_idx(kcontrol);
  950. if (idx < 0)
  951. return idx;
  952. ucontrol->value.enumerated.item[0] =
  953. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  954. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  955. idx, aux_pcm_rx_cfg[idx].sample_rate,
  956. ucontrol->value.enumerated.item[0]);
  957. return 0;
  958. }
  959. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  960. struct snd_ctl_elem_value *ucontrol)
  961. {
  962. int idx = aux_pcm_get_port_idx(kcontrol);
  963. if (idx < 0)
  964. return idx;
  965. aux_pcm_tx_cfg[idx].sample_rate =
  966. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  967. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  968. idx, aux_pcm_tx_cfg[idx].sample_rate,
  969. ucontrol->value.enumerated.item[0]);
  970. return 0;
  971. }
  972. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  973. struct snd_ctl_elem_value *ucontrol)
  974. {
  975. int idx = aux_pcm_get_port_idx(kcontrol);
  976. if (idx < 0)
  977. return idx;
  978. ucontrol->value.enumerated.item[0] =
  979. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  980. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  981. idx, aux_pcm_tx_cfg[idx].sample_rate,
  982. ucontrol->value.enumerated.item[0]);
  983. return 0;
  984. }
  985. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  986. {
  987. int idx;
  988. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  989. sizeof("PRIM_MI2S_RX")))
  990. idx = PRIM_MI2S;
  991. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  992. sizeof("SEC_MI2S_RX")))
  993. idx = SEC_MI2S;
  994. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  995. sizeof("TERT_MI2S_RX")))
  996. idx = TERT_MI2S;
  997. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  998. sizeof("QUAT_MI2S_RX")))
  999. idx = QUAT_MI2S;
  1000. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  1001. sizeof("QUIN_MI2S_RX")))
  1002. idx = QUIN_MI2S;
  1003. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1004. sizeof("PRIM_MI2S_TX")))
  1005. idx = PRIM_MI2S;
  1006. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1007. sizeof("SEC_MI2S_TX")))
  1008. idx = SEC_MI2S;
  1009. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1010. sizeof("TERT_MI2S_TX")))
  1011. idx = TERT_MI2S;
  1012. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1013. sizeof("QUAT_MI2S_TX")))
  1014. idx = QUAT_MI2S;
  1015. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1016. sizeof("QUIN_MI2S_TX")))
  1017. idx = QUIN_MI2S;
  1018. else {
  1019. pr_err("%s: unsupported channel: %s",
  1020. __func__, kcontrol->id.name);
  1021. idx = -EINVAL;
  1022. }
  1023. return idx;
  1024. }
  1025. static int mi2s_get_sample_rate_val(int sample_rate)
  1026. {
  1027. int sample_rate_val;
  1028. switch (sample_rate) {
  1029. case SAMPLING_RATE_8KHZ:
  1030. sample_rate_val = 0;
  1031. break;
  1032. case SAMPLING_RATE_16KHZ:
  1033. sample_rate_val = 1;
  1034. break;
  1035. case SAMPLING_RATE_32KHZ:
  1036. sample_rate_val = 2;
  1037. break;
  1038. case SAMPLING_RATE_44P1KHZ:
  1039. sample_rate_val = 3;
  1040. break;
  1041. case SAMPLING_RATE_48KHZ:
  1042. sample_rate_val = 4;
  1043. break;
  1044. case SAMPLING_RATE_96KHZ:
  1045. sample_rate_val = 5;
  1046. break;
  1047. case SAMPLING_RATE_192KHZ:
  1048. sample_rate_val = 6;
  1049. break;
  1050. default:
  1051. sample_rate_val = 4;
  1052. break;
  1053. }
  1054. return sample_rate_val;
  1055. }
  1056. static int mi2s_get_sample_rate(int value)
  1057. {
  1058. int sample_rate;
  1059. switch (value) {
  1060. case 0:
  1061. sample_rate = SAMPLING_RATE_8KHZ;
  1062. break;
  1063. case 1:
  1064. sample_rate = SAMPLING_RATE_16KHZ;
  1065. break;
  1066. case 2:
  1067. sample_rate = SAMPLING_RATE_32KHZ;
  1068. break;
  1069. case 3:
  1070. sample_rate = SAMPLING_RATE_44P1KHZ;
  1071. break;
  1072. case 4:
  1073. sample_rate = SAMPLING_RATE_48KHZ;
  1074. break;
  1075. case 5:
  1076. sample_rate = SAMPLING_RATE_96KHZ;
  1077. break;
  1078. case 6:
  1079. sample_rate = SAMPLING_RATE_192KHZ;
  1080. break;
  1081. default:
  1082. sample_rate = SAMPLING_RATE_48KHZ;
  1083. break;
  1084. }
  1085. return sample_rate;
  1086. }
  1087. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1088. struct snd_ctl_elem_value *ucontrol)
  1089. {
  1090. int idx = mi2s_get_port_idx(kcontrol);
  1091. if (idx < 0)
  1092. return idx;
  1093. mi2s_rx_cfg[idx].sample_rate =
  1094. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1095. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1096. idx, mi2s_rx_cfg[idx].sample_rate,
  1097. ucontrol->value.enumerated.item[0]);
  1098. return 0;
  1099. }
  1100. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1101. struct snd_ctl_elem_value *ucontrol)
  1102. {
  1103. int idx = mi2s_get_port_idx(kcontrol);
  1104. if (idx < 0)
  1105. return idx;
  1106. ucontrol->value.enumerated.item[0] =
  1107. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1108. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1109. idx, mi2s_rx_cfg[idx].sample_rate,
  1110. ucontrol->value.enumerated.item[0]);
  1111. return 0;
  1112. }
  1113. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1114. struct snd_ctl_elem_value *ucontrol)
  1115. {
  1116. int idx = mi2s_get_port_idx(kcontrol);
  1117. if (idx < 0)
  1118. return idx;
  1119. mi2s_tx_cfg[idx].sample_rate =
  1120. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1121. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1122. idx, mi2s_tx_cfg[idx].sample_rate,
  1123. ucontrol->value.enumerated.item[0]);
  1124. return 0;
  1125. }
  1126. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1127. struct snd_ctl_elem_value *ucontrol)
  1128. {
  1129. int idx = mi2s_get_port_idx(kcontrol);
  1130. if (idx < 0)
  1131. return idx;
  1132. ucontrol->value.enumerated.item[0] =
  1133. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1134. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1135. idx, mi2s_tx_cfg[idx].sample_rate,
  1136. ucontrol->value.enumerated.item[0]);
  1137. return 0;
  1138. }
  1139. static int mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1140. struct snd_ctl_elem_value *ucontrol)
  1141. {
  1142. int idx = mi2s_get_port_idx(kcontrol);
  1143. if (idx < 0)
  1144. return idx;
  1145. mi2s_tx_cfg[idx].bit_format =
  1146. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1147. pr_debug("%s: idx[%d] _tx_format = %d, item = %d\n", __func__,
  1148. idx, mi2s_tx_cfg[idx].bit_format,
  1149. ucontrol->value.enumerated.item[0]);
  1150. return 0;
  1151. }
  1152. static int mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1153. struct snd_ctl_elem_value *ucontrol)
  1154. {
  1155. int idx = mi2s_get_port_idx(kcontrol);
  1156. if (idx < 0)
  1157. return idx;
  1158. ucontrol->value.enumerated.item[0] =
  1159. mi2s_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1160. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1161. idx, mi2s_tx_cfg[idx].bit_format,
  1162. ucontrol->value.enumerated.item[0]);
  1163. return 0;
  1164. }
  1165. static int mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1166. struct snd_ctl_elem_value *ucontrol)
  1167. {
  1168. int idx = mi2s_get_port_idx(kcontrol);
  1169. if (idx < 0)
  1170. return idx;
  1171. mi2s_rx_cfg[idx].bit_format =
  1172. mi2s_get_format(ucontrol->value.enumerated.item[0]);
  1173. pr_debug("%s: idx[%d] _rx_format = %d, item = %d\n", __func__,
  1174. idx, mi2s_rx_cfg[idx].bit_format,
  1175. ucontrol->value.enumerated.item[0]);
  1176. return 0;
  1177. }
  1178. static int mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1179. struct snd_ctl_elem_value *ucontrol)
  1180. {
  1181. int idx = mi2s_get_port_idx(kcontrol);
  1182. if (idx < 0)
  1183. return idx;
  1184. ucontrol->value.enumerated.item[0] =
  1185. mi2s_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1186. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1187. idx, mi2s_rx_cfg[idx].bit_format,
  1188. ucontrol->value.enumerated.item[0]);
  1189. return 0;
  1190. }
  1191. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1192. struct snd_ctl_elem_value *ucontrol)
  1193. {
  1194. int idx = mi2s_get_port_idx(kcontrol);
  1195. if (idx < 0)
  1196. return idx;
  1197. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1198. idx, mi2s_rx_cfg[idx].channels);
  1199. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1200. return 0;
  1201. }
  1202. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1203. struct snd_ctl_elem_value *ucontrol)
  1204. {
  1205. int idx = mi2s_get_port_idx(kcontrol);
  1206. if (idx < 0)
  1207. return idx;
  1208. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1209. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1210. idx, mi2s_rx_cfg[idx].channels);
  1211. return 1;
  1212. }
  1213. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1214. struct snd_ctl_elem_value *ucontrol)
  1215. {
  1216. int idx = mi2s_get_port_idx(kcontrol);
  1217. if (idx < 0)
  1218. return idx;
  1219. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1220. idx, mi2s_tx_cfg[idx].channels);
  1221. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1222. return 0;
  1223. }
  1224. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1225. struct snd_ctl_elem_value *ucontrol)
  1226. {
  1227. int idx = mi2s_get_port_idx(kcontrol);
  1228. if (idx < 0)
  1229. return idx;
  1230. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1231. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1232. idx, mi2s_tx_cfg[idx].channels);
  1233. return 1;
  1234. }
  1235. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1236. struct snd_ctl_elem_value *ucontrol)
  1237. {
  1238. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1239. usb_rx_cfg.channels);
  1240. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1241. return 0;
  1242. }
  1243. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1244. struct snd_ctl_elem_value *ucontrol)
  1245. {
  1246. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1247. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1248. return 1;
  1249. }
  1250. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1251. struct snd_ctl_elem_value *ucontrol)
  1252. {
  1253. int sample_rate_val;
  1254. switch (usb_rx_cfg.sample_rate) {
  1255. case SAMPLING_RATE_384KHZ:
  1256. sample_rate_val = 9;
  1257. break;
  1258. case SAMPLING_RATE_192KHZ:
  1259. sample_rate_val = 8;
  1260. break;
  1261. case SAMPLING_RATE_96KHZ:
  1262. sample_rate_val = 7;
  1263. break;
  1264. case SAMPLING_RATE_48KHZ:
  1265. sample_rate_val = 6;
  1266. break;
  1267. case SAMPLING_RATE_44P1KHZ:
  1268. sample_rate_val = 5;
  1269. break;
  1270. case SAMPLING_RATE_32KHZ:
  1271. sample_rate_val = 4;
  1272. break;
  1273. case SAMPLING_RATE_22P05KHZ:
  1274. sample_rate_val = 3;
  1275. break;
  1276. case SAMPLING_RATE_16KHZ:
  1277. sample_rate_val = 2;
  1278. break;
  1279. case SAMPLING_RATE_11P025KHZ:
  1280. sample_rate_val = 1;
  1281. break;
  1282. case SAMPLING_RATE_8KHZ:
  1283. default:
  1284. sample_rate_val = 0;
  1285. break;
  1286. }
  1287. ucontrol->value.integer.value[0] = sample_rate_val;
  1288. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1289. usb_rx_cfg.sample_rate);
  1290. return 0;
  1291. }
  1292. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1293. struct snd_ctl_elem_value *ucontrol)
  1294. {
  1295. switch (ucontrol->value.integer.value[0]) {
  1296. case 9:
  1297. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1298. break;
  1299. case 8:
  1300. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1301. break;
  1302. case 7:
  1303. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1304. break;
  1305. case 6:
  1306. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1307. break;
  1308. case 5:
  1309. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1310. break;
  1311. case 4:
  1312. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1313. break;
  1314. case 3:
  1315. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1316. break;
  1317. case 2:
  1318. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1319. break;
  1320. case 1:
  1321. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1322. break;
  1323. case 0:
  1324. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1325. break;
  1326. default:
  1327. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1328. break;
  1329. }
  1330. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1331. __func__, ucontrol->value.integer.value[0],
  1332. usb_rx_cfg.sample_rate);
  1333. return 0;
  1334. }
  1335. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1336. struct snd_ctl_elem_value *ucontrol)
  1337. {
  1338. switch (usb_rx_cfg.bit_format) {
  1339. case SNDRV_PCM_FORMAT_S32_LE:
  1340. ucontrol->value.integer.value[0] = 3;
  1341. break;
  1342. case SNDRV_PCM_FORMAT_S24_3LE:
  1343. ucontrol->value.integer.value[0] = 2;
  1344. break;
  1345. case SNDRV_PCM_FORMAT_S24_LE:
  1346. ucontrol->value.integer.value[0] = 1;
  1347. break;
  1348. case SNDRV_PCM_FORMAT_S16_LE:
  1349. default:
  1350. ucontrol->value.integer.value[0] = 0;
  1351. break;
  1352. }
  1353. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1354. __func__, usb_rx_cfg.bit_format,
  1355. ucontrol->value.integer.value[0]);
  1356. return 0;
  1357. }
  1358. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1359. struct snd_ctl_elem_value *ucontrol)
  1360. {
  1361. int rc = 0;
  1362. switch (ucontrol->value.integer.value[0]) {
  1363. case 3:
  1364. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1365. break;
  1366. case 2:
  1367. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1368. break;
  1369. case 1:
  1370. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1371. break;
  1372. case 0:
  1373. default:
  1374. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1375. break;
  1376. }
  1377. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1378. __func__, usb_rx_cfg.bit_format,
  1379. ucontrol->value.integer.value[0]);
  1380. return rc;
  1381. }
  1382. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1383. struct snd_ctl_elem_value *ucontrol)
  1384. {
  1385. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1386. usb_tx_cfg.channels);
  1387. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1388. return 0;
  1389. }
  1390. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1391. struct snd_ctl_elem_value *ucontrol)
  1392. {
  1393. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1394. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1395. return 1;
  1396. }
  1397. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1398. struct snd_ctl_elem_value *ucontrol)
  1399. {
  1400. int sample_rate_val;
  1401. switch (usb_tx_cfg.sample_rate) {
  1402. case SAMPLING_RATE_384KHZ:
  1403. sample_rate_val = 9;
  1404. break;
  1405. case SAMPLING_RATE_192KHZ:
  1406. sample_rate_val = 8;
  1407. break;
  1408. case SAMPLING_RATE_96KHZ:
  1409. sample_rate_val = 7;
  1410. break;
  1411. case SAMPLING_RATE_48KHZ:
  1412. sample_rate_val = 6;
  1413. break;
  1414. case SAMPLING_RATE_44P1KHZ:
  1415. sample_rate_val = 5;
  1416. break;
  1417. case SAMPLING_RATE_32KHZ:
  1418. sample_rate_val = 4;
  1419. break;
  1420. case SAMPLING_RATE_22P05KHZ:
  1421. sample_rate_val = 3;
  1422. break;
  1423. case SAMPLING_RATE_16KHZ:
  1424. sample_rate_val = 2;
  1425. break;
  1426. case SAMPLING_RATE_11P025KHZ:
  1427. sample_rate_val = 1;
  1428. break;
  1429. case SAMPLING_RATE_8KHZ:
  1430. sample_rate_val = 0;
  1431. break;
  1432. default:
  1433. sample_rate_val = 6;
  1434. break;
  1435. }
  1436. ucontrol->value.integer.value[0] = sample_rate_val;
  1437. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1438. usb_tx_cfg.sample_rate);
  1439. return 0;
  1440. }
  1441. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1442. struct snd_ctl_elem_value *ucontrol)
  1443. {
  1444. switch (ucontrol->value.integer.value[0]) {
  1445. case 9:
  1446. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1447. break;
  1448. case 8:
  1449. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1450. break;
  1451. case 7:
  1452. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1453. break;
  1454. case 6:
  1455. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1456. break;
  1457. case 5:
  1458. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1459. break;
  1460. case 4:
  1461. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1462. break;
  1463. case 3:
  1464. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1465. break;
  1466. case 2:
  1467. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1468. break;
  1469. case 1:
  1470. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1471. break;
  1472. case 0:
  1473. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1474. break;
  1475. default:
  1476. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1477. break;
  1478. }
  1479. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1480. __func__, ucontrol->value.integer.value[0],
  1481. usb_tx_cfg.sample_rate);
  1482. return 0;
  1483. }
  1484. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1485. struct snd_ctl_elem_value *ucontrol)
  1486. {
  1487. switch (usb_tx_cfg.bit_format) {
  1488. case SNDRV_PCM_FORMAT_S32_LE:
  1489. ucontrol->value.integer.value[0] = 3;
  1490. break;
  1491. case SNDRV_PCM_FORMAT_S24_3LE:
  1492. ucontrol->value.integer.value[0] = 2;
  1493. break;
  1494. case SNDRV_PCM_FORMAT_S24_LE:
  1495. ucontrol->value.integer.value[0] = 1;
  1496. break;
  1497. case SNDRV_PCM_FORMAT_S16_LE:
  1498. default:
  1499. ucontrol->value.integer.value[0] = 0;
  1500. break;
  1501. }
  1502. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1503. __func__, usb_tx_cfg.bit_format,
  1504. ucontrol->value.integer.value[0]);
  1505. return 0;
  1506. }
  1507. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1508. struct snd_ctl_elem_value *ucontrol)
  1509. {
  1510. int rc = 0;
  1511. switch (ucontrol->value.integer.value[0]) {
  1512. case 3:
  1513. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1514. break;
  1515. case 2:
  1516. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1517. break;
  1518. case 1:
  1519. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1520. break;
  1521. case 0:
  1522. default:
  1523. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1524. break;
  1525. }
  1526. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1527. __func__, usb_tx_cfg.bit_format,
  1528. ucontrol->value.integer.value[0]);
  1529. return rc;
  1530. }
  1531. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1532. {
  1533. int idx;
  1534. if (strnstr(kcontrol->id.name, "Display Port RX",
  1535. sizeof("Display Port RX")))
  1536. idx = DP_RX_IDX;
  1537. else {
  1538. pr_err("%s: unsupported BE: %s",
  1539. __func__, kcontrol->id.name);
  1540. idx = -EINVAL;
  1541. }
  1542. return idx;
  1543. }
  1544. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1545. struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. int idx = ext_disp_get_port_idx(kcontrol);
  1548. if (idx < 0)
  1549. return idx;
  1550. switch (ext_disp_rx_cfg[idx].bit_format) {
  1551. case SNDRV_PCM_FORMAT_S24_LE:
  1552. ucontrol->value.integer.value[0] = 1;
  1553. break;
  1554. case SNDRV_PCM_FORMAT_S16_LE:
  1555. default:
  1556. ucontrol->value.integer.value[0] = 0;
  1557. break;
  1558. }
  1559. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1560. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1561. ucontrol->value.integer.value[0]);
  1562. return 0;
  1563. }
  1564. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1565. struct snd_ctl_elem_value *ucontrol)
  1566. {
  1567. int idx = ext_disp_get_port_idx(kcontrol);
  1568. if (idx < 0)
  1569. return idx;
  1570. switch (ucontrol->value.integer.value[0]) {
  1571. case 1:
  1572. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1573. break;
  1574. case 0:
  1575. default:
  1576. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1577. break;
  1578. }
  1579. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1580. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1581. ucontrol->value.integer.value[0]);
  1582. return 0;
  1583. }
  1584. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1585. struct snd_ctl_elem_value *ucontrol)
  1586. {
  1587. int idx = ext_disp_get_port_idx(kcontrol);
  1588. if (idx < 0)
  1589. return idx;
  1590. ucontrol->value.integer.value[0] =
  1591. ext_disp_rx_cfg[idx].channels - 2;
  1592. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1593. idx, ext_disp_rx_cfg[idx].channels);
  1594. return 0;
  1595. }
  1596. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1597. struct snd_ctl_elem_value *ucontrol)
  1598. {
  1599. int idx = ext_disp_get_port_idx(kcontrol);
  1600. if (idx < 0)
  1601. return idx;
  1602. ext_disp_rx_cfg[idx].channels =
  1603. ucontrol->value.integer.value[0] + 2;
  1604. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1605. idx, ext_disp_rx_cfg[idx].channels);
  1606. return 1;
  1607. }
  1608. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1609. struct snd_ctl_elem_value *ucontrol)
  1610. {
  1611. int sample_rate_val;
  1612. int idx = ext_disp_get_port_idx(kcontrol);
  1613. if (idx < 0)
  1614. return idx;
  1615. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1616. case SAMPLING_RATE_192KHZ:
  1617. sample_rate_val = 2;
  1618. break;
  1619. case SAMPLING_RATE_96KHZ:
  1620. sample_rate_val = 1;
  1621. break;
  1622. case SAMPLING_RATE_48KHZ:
  1623. default:
  1624. sample_rate_val = 0;
  1625. break;
  1626. }
  1627. ucontrol->value.integer.value[0] = sample_rate_val;
  1628. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1629. idx, ext_disp_rx_cfg[idx].sample_rate);
  1630. return 0;
  1631. }
  1632. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1633. struct snd_ctl_elem_value *ucontrol)
  1634. {
  1635. int idx = ext_disp_get_port_idx(kcontrol);
  1636. if (idx < 0)
  1637. return idx;
  1638. switch (ucontrol->value.integer.value[0]) {
  1639. case 2:
  1640. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1641. break;
  1642. case 1:
  1643. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1644. break;
  1645. case 0:
  1646. default:
  1647. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1648. break;
  1649. }
  1650. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1651. __func__, ucontrol->value.integer.value[0], idx,
  1652. ext_disp_rx_cfg[idx].sample_rate);
  1653. return 0;
  1654. }
  1655. const struct snd_kcontrol_new msm_common_snd_controls[] = {
  1656. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  1657. proxy_rx_ch_get, proxy_rx_ch_put),
  1658. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  1659. aux_pcm_rx_sample_rate_get,
  1660. aux_pcm_rx_sample_rate_put),
  1661. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  1662. aux_pcm_rx_sample_rate_get,
  1663. aux_pcm_rx_sample_rate_put),
  1664. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  1665. aux_pcm_rx_sample_rate_get,
  1666. aux_pcm_rx_sample_rate_put),
  1667. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  1668. aux_pcm_rx_sample_rate_get,
  1669. aux_pcm_rx_sample_rate_put),
  1670. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  1671. aux_pcm_rx_sample_rate_get,
  1672. aux_pcm_rx_sample_rate_put),
  1673. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  1674. aux_pcm_tx_sample_rate_get,
  1675. aux_pcm_tx_sample_rate_put),
  1676. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  1677. aux_pcm_tx_sample_rate_get,
  1678. aux_pcm_tx_sample_rate_put),
  1679. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  1680. aux_pcm_tx_sample_rate_get,
  1681. aux_pcm_tx_sample_rate_put),
  1682. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  1683. aux_pcm_tx_sample_rate_get,
  1684. aux_pcm_tx_sample_rate_put),
  1685. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  1686. aux_pcm_tx_sample_rate_get,
  1687. aux_pcm_tx_sample_rate_put),
  1688. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  1689. mi2s_rx_sample_rate_get,
  1690. mi2s_rx_sample_rate_put),
  1691. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  1692. mi2s_rx_sample_rate_get,
  1693. mi2s_rx_sample_rate_put),
  1694. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  1695. mi2s_rx_sample_rate_get,
  1696. mi2s_rx_sample_rate_put),
  1697. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  1698. mi2s_rx_sample_rate_get,
  1699. mi2s_rx_sample_rate_put),
  1700. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  1701. mi2s_rx_sample_rate_get,
  1702. mi2s_rx_sample_rate_put),
  1703. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  1704. mi2s_tx_sample_rate_get,
  1705. mi2s_tx_sample_rate_put),
  1706. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  1707. mi2s_tx_sample_rate_get,
  1708. mi2s_tx_sample_rate_put),
  1709. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  1710. mi2s_tx_sample_rate_get,
  1711. mi2s_tx_sample_rate_put),
  1712. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  1713. mi2s_tx_sample_rate_get,
  1714. mi2s_tx_sample_rate_put),
  1715. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  1716. mi2s_tx_sample_rate_get,
  1717. mi2s_tx_sample_rate_put),
  1718. SOC_ENUM_EXT("PRIM_MI2S_RX Format", prim_mi2s_rx_format,
  1719. mi2s_rx_format_get,
  1720. mi2s_rx_format_put),
  1721. SOC_ENUM_EXT("SEC_MI2S_RX Format", sec_mi2s_rx_format,
  1722. mi2s_rx_format_get,
  1723. mi2s_rx_format_put),
  1724. SOC_ENUM_EXT("TERT_MI2S_RX Format", tert_mi2s_rx_format,
  1725. mi2s_rx_format_get,
  1726. mi2s_rx_format_put),
  1727. SOC_ENUM_EXT("QUAT_MI2S_RX Format", quat_mi2s_rx_format,
  1728. mi2s_rx_format_get,
  1729. mi2s_rx_format_put),
  1730. SOC_ENUM_EXT("QUIN_MI2S_RX Format", quin_mi2s_rx_format,
  1731. mi2s_rx_format_get,
  1732. mi2s_rx_format_put),
  1733. SOC_ENUM_EXT("PRIM_MI2S_TX Format", prim_mi2s_tx_format,
  1734. mi2s_tx_format_get,
  1735. mi2s_tx_format_put),
  1736. SOC_ENUM_EXT("SEC_MI2S_TX Format", sec_mi2s_tx_format,
  1737. mi2s_tx_format_get,
  1738. mi2s_tx_format_put),
  1739. SOC_ENUM_EXT("TERT_MI2S_TX Format", tert_mi2s_tx_format,
  1740. mi2s_tx_format_get,
  1741. mi2s_tx_format_put),
  1742. SOC_ENUM_EXT("QUAT_MI2S_TX Format", quat_mi2s_tx_format,
  1743. mi2s_tx_format_get,
  1744. mi2s_tx_format_put),
  1745. SOC_ENUM_EXT("QUIN_MI2S_TX Format", quin_mi2s_tx_format,
  1746. mi2s_tx_format_get,
  1747. mi2s_tx_format_put),
  1748. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  1749. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1750. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  1751. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1752. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  1753. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1754. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  1755. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1756. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  1757. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1758. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  1759. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1760. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  1761. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1762. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  1763. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1764. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  1765. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  1766. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  1767. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  1768. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  1769. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  1770. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  1771. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  1772. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  1773. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  1774. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  1775. usb_audio_rx_format_get, usb_audio_rx_format_put),
  1776. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  1777. usb_audio_tx_format_get, usb_audio_tx_format_put),
  1778. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  1779. ext_disp_rx_format_get, ext_disp_rx_format_put),
  1780. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  1781. usb_audio_rx_sample_rate_get,
  1782. usb_audio_rx_sample_rate_put),
  1783. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  1784. usb_audio_tx_sample_rate_get,
  1785. usb_audio_tx_sample_rate_put),
  1786. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  1787. ext_disp_rx_sample_rate_get,
  1788. ext_disp_rx_sample_rate_put),
  1789. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1790. tdm_rx_sample_rate_get,
  1791. tdm_rx_sample_rate_put),
  1792. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1793. tdm_tx_sample_rate_get,
  1794. tdm_tx_sample_rate_put),
  1795. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  1796. tdm_rx_format_get,
  1797. tdm_rx_format_put),
  1798. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  1799. tdm_tx_format_get,
  1800. tdm_tx_format_put),
  1801. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  1802. tdm_rx_ch_get,
  1803. tdm_rx_ch_put),
  1804. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  1805. tdm_tx_ch_get,
  1806. tdm_tx_ch_put),
  1807. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1808. tdm_rx_sample_rate_get,
  1809. tdm_rx_sample_rate_put),
  1810. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1811. tdm_tx_sample_rate_get,
  1812. tdm_tx_sample_rate_put),
  1813. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  1814. tdm_rx_format_get,
  1815. tdm_rx_format_put),
  1816. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  1817. tdm_tx_format_get,
  1818. tdm_tx_format_put),
  1819. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  1820. tdm_rx_ch_get,
  1821. tdm_rx_ch_put),
  1822. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  1823. tdm_tx_ch_get,
  1824. tdm_tx_ch_put),
  1825. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1826. tdm_rx_sample_rate_get,
  1827. tdm_rx_sample_rate_put),
  1828. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1829. tdm_tx_sample_rate_get,
  1830. tdm_tx_sample_rate_put),
  1831. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  1832. tdm_rx_format_get,
  1833. tdm_rx_format_put),
  1834. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  1835. tdm_tx_format_get,
  1836. tdm_tx_format_put),
  1837. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  1838. tdm_rx_ch_get,
  1839. tdm_rx_ch_put),
  1840. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  1841. tdm_tx_ch_get,
  1842. tdm_tx_ch_put),
  1843. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1844. tdm_rx_sample_rate_get,
  1845. tdm_rx_sample_rate_put),
  1846. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1847. tdm_tx_sample_rate_get,
  1848. tdm_tx_sample_rate_put),
  1849. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  1850. tdm_rx_format_get,
  1851. tdm_rx_format_put),
  1852. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  1853. tdm_tx_format_get,
  1854. tdm_tx_format_put),
  1855. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  1856. tdm_rx_ch_get,
  1857. tdm_rx_ch_put),
  1858. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  1859. tdm_tx_ch_get,
  1860. tdm_tx_ch_put),
  1861. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  1862. tdm_rx_sample_rate_get,
  1863. tdm_rx_sample_rate_put),
  1864. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  1865. tdm_tx_sample_rate_get,
  1866. tdm_tx_sample_rate_put),
  1867. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  1868. tdm_rx_format_get,
  1869. tdm_rx_format_put),
  1870. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  1871. tdm_tx_format_get,
  1872. tdm_tx_format_put),
  1873. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  1874. tdm_rx_ch_get,
  1875. tdm_rx_ch_put),
  1876. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  1877. tdm_tx_ch_get,
  1878. tdm_tx_ch_put),
  1879. };
  1880. /**
  1881. * msm_common_snd_controls_size - to return controls size
  1882. *
  1883. * Return: returns size of common controls array
  1884. */
  1885. int msm_common_snd_controls_size(void)
  1886. {
  1887. return ARRAY_SIZE(msm_common_snd_controls);
  1888. }
  1889. EXPORT_SYMBOL(msm_common_snd_controls_size);
  1890. void msm_set_codec_reg_done(bool done)
  1891. {
  1892. codec_reg_done = done;
  1893. }
  1894. EXPORT_SYMBOL(msm_set_codec_reg_done);
  1895. static inline int param_is_mask(int p)
  1896. {
  1897. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  1898. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  1899. }
  1900. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  1901. int n)
  1902. {
  1903. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  1904. }
  1905. static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit)
  1906. {
  1907. if (bit >= SNDRV_MASK_MAX)
  1908. return;
  1909. if (param_is_mask(n)) {
  1910. struct snd_mask *m = param_to_mask(p, n);
  1911. m->bits[0] = 0;
  1912. m->bits[1] = 0;
  1913. m->bits[bit >> 5] |= (1 << (bit & 31));
  1914. }
  1915. }
  1916. static int msm_ext_disp_get_idx_from_beid(int32_t id)
  1917. {
  1918. int idx;
  1919. switch (id) {
  1920. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1921. idx = DP_RX_IDX;
  1922. break;
  1923. default:
  1924. pr_err("%s: Incorrect ext_disp id %d\n", __func__, id);
  1925. idx = -EINVAL;
  1926. break;
  1927. }
  1928. return idx;
  1929. }
  1930. /**
  1931. * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params.
  1932. *
  1933. * @rtd: runtime dailink instance
  1934. * @params: HW params of associated backend dailink.
  1935. *
  1936. * Returns 0.
  1937. */
  1938. int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  1939. struct snd_pcm_hw_params *params)
  1940. {
  1941. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  1942. struct snd_interval *rate = hw_param_interval(params,
  1943. SNDRV_PCM_HW_PARAM_RATE);
  1944. struct snd_interval *channels = hw_param_interval(params,
  1945. SNDRV_PCM_HW_PARAM_CHANNELS);
  1946. int rc = 0;
  1947. int idx;
  1948. pr_debug("%s: format = %d, rate = %d\n",
  1949. __func__, params_format(params), params_rate(params));
  1950. switch (dai_link->id) {
  1951. case MSM_BACKEND_DAI_USB_RX:
  1952. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1953. usb_rx_cfg.bit_format);
  1954. rate->min = rate->max = usb_rx_cfg.sample_rate;
  1955. channels->min = channels->max = usb_rx_cfg.channels;
  1956. break;
  1957. case MSM_BACKEND_DAI_USB_TX:
  1958. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1959. usb_tx_cfg.bit_format);
  1960. rate->min = rate->max = usb_tx_cfg.sample_rate;
  1961. channels->min = channels->max = usb_tx_cfg.channels;
  1962. break;
  1963. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  1964. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  1965. if (idx < 0) {
  1966. pr_err("%s: Incorrect ext disp idx %d\n",
  1967. __func__, idx);
  1968. rc = idx;
  1969. break;
  1970. }
  1971. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1972. ext_disp_rx_cfg[idx].bit_format);
  1973. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  1974. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  1975. break;
  1976. case MSM_BACKEND_DAI_AFE_PCM_RX:
  1977. channels->min = channels->max = proxy_rx_cfg.channels;
  1978. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  1979. break;
  1980. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  1981. channels->min = channels->max =
  1982. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  1983. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1984. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  1985. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  1986. break;
  1987. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  1988. channels->min = channels->max =
  1989. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  1990. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1991. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  1992. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  1993. break;
  1994. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  1995. channels->min = channels->max =
  1996. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  1997. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  1998. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  1999. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  2000. break;
  2001. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  2002. channels->min = channels->max =
  2003. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  2004. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2005. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  2006. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  2007. break;
  2008. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  2009. channels->min = channels->max =
  2010. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  2011. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2012. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  2013. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  2014. break;
  2015. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  2016. channels->min = channels->max =
  2017. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  2018. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2019. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  2020. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  2021. break;
  2022. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  2023. channels->min = channels->max =
  2024. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  2025. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2026. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  2027. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2028. break;
  2029. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  2030. channels->min = channels->max =
  2031. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  2032. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2033. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  2034. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2035. break;
  2036. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  2037. channels->min = channels->max =
  2038. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  2039. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2040. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  2041. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2042. break;
  2043. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  2044. channels->min = channels->max =
  2045. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  2046. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2047. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  2048. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  2049. break;
  2050. case MSM_BACKEND_DAI_AUXPCM_RX:
  2051. rate->min = rate->max =
  2052. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  2053. channels->min = channels->max =
  2054. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  2055. break;
  2056. case MSM_BACKEND_DAI_AUXPCM_TX:
  2057. rate->min = rate->max =
  2058. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  2059. channels->min = channels->max =
  2060. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  2061. break;
  2062. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  2063. rate->min = rate->max =
  2064. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  2065. channels->min = channels->max =
  2066. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  2067. break;
  2068. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  2069. rate->min = rate->max =
  2070. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  2071. channels->min = channels->max =
  2072. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  2073. break;
  2074. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  2075. rate->min = rate->max =
  2076. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  2077. channels->min = channels->max =
  2078. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  2079. break;
  2080. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  2081. rate->min = rate->max =
  2082. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  2083. channels->min = channels->max =
  2084. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  2085. break;
  2086. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  2087. rate->min = rate->max =
  2088. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  2089. channels->min = channels->max =
  2090. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  2091. break;
  2092. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  2093. rate->min = rate->max =
  2094. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  2095. channels->min = channels->max =
  2096. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  2097. break;
  2098. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  2099. rate->min = rate->max =
  2100. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  2101. channels->min = channels->max =
  2102. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  2103. break;
  2104. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  2105. rate->min = rate->max =
  2106. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  2107. channels->min = channels->max =
  2108. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  2109. break;
  2110. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2111. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  2112. channels->min = channels->max =
  2113. mi2s_rx_cfg[PRIM_MI2S].channels;
  2114. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2115. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  2116. break;
  2117. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2118. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  2119. channels->min = channels->max =
  2120. mi2s_tx_cfg[PRIM_MI2S].channels;
  2121. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2122. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  2123. break;
  2124. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2125. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  2126. channels->min = channels->max =
  2127. mi2s_rx_cfg[SEC_MI2S].channels;
  2128. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2129. mi2s_rx_cfg[SEC_MI2S].bit_format);
  2130. break;
  2131. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2132. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  2133. channels->min = channels->max =
  2134. mi2s_tx_cfg[SEC_MI2S].channels;
  2135. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2136. mi2s_tx_cfg[SEC_MI2S].bit_format);
  2137. break;
  2138. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2139. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  2140. channels->min = channels->max =
  2141. mi2s_rx_cfg[TERT_MI2S].channels;
  2142. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2143. mi2s_rx_cfg[TERT_MI2S].bit_format);
  2144. break;
  2145. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2146. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  2147. channels->min = channels->max =
  2148. mi2s_tx_cfg[TERT_MI2S].channels;
  2149. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2150. mi2s_tx_cfg[TERT_MI2S].bit_format);
  2151. break;
  2152. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2153. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  2154. channels->min = channels->max =
  2155. mi2s_rx_cfg[QUAT_MI2S].channels;
  2156. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2157. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  2158. break;
  2159. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2160. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  2161. channels->min = channels->max =
  2162. mi2s_tx_cfg[QUAT_MI2S].channels;
  2163. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2164. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  2165. break;
  2166. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2167. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  2168. channels->min = channels->max =
  2169. mi2s_rx_cfg[QUIN_MI2S].channels;
  2170. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2171. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  2172. break;
  2173. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2174. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  2175. channels->min = channels->max =
  2176. mi2s_tx_cfg[QUIN_MI2S].channels;
  2177. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2178. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  2179. break;
  2180. default:
  2181. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2182. break;
  2183. }
  2184. return rc;
  2185. }
  2186. EXPORT_SYMBOL(msm_common_be_hw_params_fixup);
  2187. /**
  2188. * msm_aux_pcm_snd_startup - startup ops of auxpcm.
  2189. *
  2190. * @substream: PCM stream pointer of associated backend dailink
  2191. *
  2192. * Returns 0 on success or -EINVAL on error.
  2193. */
  2194. int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream)
  2195. {
  2196. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2197. dev_dbg(rtd->card->dev,
  2198. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2199. __func__, substream->name, substream->stream,
  2200. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2201. return 0;
  2202. }
  2203. EXPORT_SYMBOL(msm_aux_pcm_snd_startup);
  2204. /**
  2205. * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm.
  2206. *
  2207. * @substream: PCM stream pointer of associated backend dailink
  2208. */
  2209. void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream)
  2210. {
  2211. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2212. dev_dbg(rtd->card->dev,
  2213. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2214. __func__,
  2215. substream->name, substream->stream,
  2216. rtd->cpu_dai->name, rtd->cpu_dai->id);
  2217. }
  2218. EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown);
  2219. static int msm_get_port_id(int id)
  2220. {
  2221. int afe_port_id;
  2222. switch (id) {
  2223. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2224. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2225. break;
  2226. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2227. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2228. break;
  2229. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2230. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2231. break;
  2232. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2233. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2234. break;
  2235. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2236. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2237. break;
  2238. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2239. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2240. break;
  2241. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2242. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2243. break;
  2244. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2245. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2246. break;
  2247. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2248. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2249. break;
  2250. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2251. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2252. break;
  2253. default:
  2254. pr_err("%s: Invalid id: %d\n", __func__, id);
  2255. afe_port_id = -EINVAL;
  2256. }
  2257. return afe_port_id;
  2258. }
  2259. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2260. {
  2261. u32 bit_per_sample;
  2262. switch (bit_format) {
  2263. case SNDRV_PCM_FORMAT_S32_LE:
  2264. case SNDRV_PCM_FORMAT_S24_3LE:
  2265. case SNDRV_PCM_FORMAT_S24_LE:
  2266. bit_per_sample = 32;
  2267. break;
  2268. case SNDRV_PCM_FORMAT_S16_LE:
  2269. default:
  2270. bit_per_sample = 16;
  2271. break;
  2272. }
  2273. return bit_per_sample;
  2274. }
  2275. static void update_mi2s_clk_val(int dai_id, int stream)
  2276. {
  2277. u32 bit_per_sample;
  2278. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2279. bit_per_sample =
  2280. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2281. mi2s_clk[dai_id].clk_freq_in_hz =
  2282. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2283. } else {
  2284. bit_per_sample =
  2285. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2286. mi2s_clk[dai_id].clk_freq_in_hz =
  2287. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2288. }
  2289. }
  2290. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2291. {
  2292. int ret = 0;
  2293. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2294. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2295. int port_id = 0;
  2296. int index = cpu_dai->id;
  2297. port_id = msm_get_port_id(rtd->dai_link->id);
  2298. if (port_id < 0) {
  2299. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2300. ret = port_id;
  2301. goto done;
  2302. }
  2303. if (enable) {
  2304. update_mi2s_clk_val(index, substream->stream);
  2305. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2306. mi2s_clk[index].clk_freq_in_hz);
  2307. }
  2308. mi2s_clk[index].enable = enable;
  2309. ret = afe_set_lpass_clock_v2(port_id,
  2310. &mi2s_clk[index]);
  2311. if (ret < 0) {
  2312. dev_err(rtd->card->dev,
  2313. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2314. __func__, port_id, ret);
  2315. goto done;
  2316. }
  2317. done:
  2318. return ret;
  2319. }
  2320. /**
  2321. * msm_mi2s_snd_startup - startup ops of mi2s.
  2322. *
  2323. * @substream: PCM stream pointer of associated backend dailink
  2324. *
  2325. * Returns 0 on success or -EINVAL on error.
  2326. */
  2327. int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  2328. {
  2329. int ret = 0;
  2330. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2331. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2332. int port_id = msm_get_port_id(rtd->dai_link->id);
  2333. int index = cpu_dai->id;
  2334. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  2335. dev_dbg(rtd->card->dev,
  2336. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  2337. __func__, substream->name, substream->stream,
  2338. cpu_dai->name, cpu_dai->id);
  2339. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2340. ret = -EINVAL;
  2341. dev_err(rtd->card->dev,
  2342. "%s: CPU DAI id (%d) out of range\n",
  2343. __func__, cpu_dai->id);
  2344. goto done;
  2345. }
  2346. /*
  2347. * Muxtex protection in case the same MI2S
  2348. * interface using for both TX and RX so
  2349. * that the same clock won't be enable twice.
  2350. */
  2351. mutex_lock(&mi2s_intf_conf[index].lock);
  2352. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  2353. /* Check if msm needs to provide the clock to the interface */
  2354. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  2355. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  2356. fmt = SND_SOC_DAIFMT_CBM_CFM;
  2357. }
  2358. ret = msm_mi2s_set_sclk(substream, true);
  2359. if (ret < 0) {
  2360. dev_err(rtd->card->dev,
  2361. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  2362. __func__, ret);
  2363. goto clean_up;
  2364. }
  2365. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  2366. if (ret < 0) {
  2367. dev_err(rtd->card->dev,
  2368. "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  2369. __func__, index, ret);
  2370. goto clk_off;
  2371. }
  2372. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2373. mi2s_mclk[index].enable = 1;
  2374. pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
  2375. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2376. ret = afe_set_lpass_clock_v2(port_id,
  2377. &mi2s_mclk[index]);
  2378. if (ret < 0) {
  2379. pr_err("%s: afe lpass mclk failed, err:%d\n",
  2380. __func__, ret);
  2381. goto clk_off;
  2382. }
  2383. }
  2384. }
  2385. mutex_unlock(&mi2s_intf_conf[index].lock);
  2386. return 0;
  2387. clk_off:
  2388. if (ret < 0)
  2389. msm_mi2s_set_sclk(substream, false);
  2390. clean_up:
  2391. if (ret < 0)
  2392. mi2s_intf_conf[index].ref_cnt--;
  2393. mutex_unlock(&mi2s_intf_conf[index].lock);
  2394. done:
  2395. return ret;
  2396. }
  2397. EXPORT_SYMBOL(msm_mi2s_snd_startup);
  2398. /**
  2399. * msm_mi2s_snd_shutdown - shutdown ops of mi2s.
  2400. *
  2401. * @substream: PCM stream pointer of associated backend dailink
  2402. */
  2403. void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  2404. {
  2405. int ret;
  2406. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2407. int port_id = msm_get_port_id(rtd->dai_link->id);
  2408. int index = rtd->cpu_dai->id;
  2409. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  2410. substream->name, substream->stream);
  2411. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  2412. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  2413. return;
  2414. }
  2415. mutex_lock(&mi2s_intf_conf[index].lock);
  2416. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  2417. ret = msm_mi2s_set_sclk(substream, false);
  2418. if (ret < 0) {
  2419. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  2420. __func__, index, ret);
  2421. mi2s_intf_conf[index].ref_cnt++;
  2422. }
  2423. if (mi2s_intf_conf[index].msm_is_ext_mclk) {
  2424. mi2s_mclk[index].enable = 0;
  2425. pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
  2426. __func__, mi2s_mclk[index].clk_freq_in_hz);
  2427. ret = afe_set_lpass_clock_v2(port_id,
  2428. &mi2s_mclk[index]);
  2429. if (ret < 0) {
  2430. pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
  2431. __func__, index, ret);
  2432. }
  2433. }
  2434. }
  2435. mutex_unlock(&mi2s_intf_conf[index].lock);
  2436. }
  2437. EXPORT_SYMBOL(msm_mi2s_snd_shutdown);
  2438. /* Validate whether US EU switch is present or not */
  2439. static int msm_prepare_us_euro(struct snd_soc_card *card)
  2440. {
  2441. struct msm_asoc_mach_data *pdata =
  2442. snd_soc_card_get_drvdata(card);
  2443. int ret = 0;
  2444. if (pdata->us_euro_gpio >= 0) {
  2445. dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__,
  2446. pdata->us_euro_gpio);
  2447. ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO");
  2448. if (ret) {
  2449. dev_err(card->dev,
  2450. "%s: Failed to request codec US/EURO gpio %d error %d\n",
  2451. __func__, pdata->us_euro_gpio, ret);
  2452. }
  2453. }
  2454. return ret;
  2455. }
  2456. static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
  2457. {
  2458. struct snd_soc_card *card = codec->component.card;
  2459. struct msm_asoc_mach_data *pdata =
  2460. snd_soc_card_get_drvdata(card);
  2461. int value = 0;
  2462. if (pdata->us_euro_gpio_p) {
  2463. value = msm_cdc_pinctrl_get_state(pdata->us_euro_gpio_p);
  2464. if (value)
  2465. msm_cdc_pinctrl_select_sleep_state(
  2466. pdata->us_euro_gpio_p);
  2467. else
  2468. msm_cdc_pinctrl_select_active_state(
  2469. pdata->us_euro_gpio_p);
  2470. } else if (pdata->us_euro_gpio >= 0) {
  2471. value = gpio_get_value_cansleep(pdata->us_euro_gpio);
  2472. gpio_set_value_cansleep(pdata->us_euro_gpio, !value);
  2473. }
  2474. pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value);
  2475. return true;
  2476. }
  2477. static int msm_populate_dai_link_component_of_node(
  2478. struct msm_asoc_mach_data *pdata,
  2479. struct snd_soc_card *card)
  2480. {
  2481. int i, index, ret = 0;
  2482. struct device *cdev = card->dev;
  2483. struct snd_soc_dai_link *dai_link = card->dai_link;
  2484. struct device_node *phandle;
  2485. if (!cdev) {
  2486. pr_err("%s: Sound card device memory NULL\n", __func__);
  2487. return -ENODEV;
  2488. }
  2489. for (i = 0; i < card->num_links; i++) {
  2490. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  2491. continue;
  2492. /* populate platform_of_node for snd card dai links */
  2493. if (dai_link[i].platform_name &&
  2494. !dai_link[i].platform_of_node) {
  2495. index = of_property_match_string(cdev->of_node,
  2496. "asoc-platform-names",
  2497. dai_link[i].platform_name);
  2498. if (index < 0) {
  2499. pr_err("%s: No match found for platform name: %s\n",
  2500. __func__, dai_link[i].platform_name);
  2501. ret = index;
  2502. goto cpu_dai;
  2503. }
  2504. phandle = of_parse_phandle(cdev->of_node,
  2505. "asoc-platform",
  2506. index);
  2507. if (!phandle) {
  2508. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  2509. __func__, dai_link[i].platform_name,
  2510. index);
  2511. ret = -ENODEV;
  2512. goto err;
  2513. }
  2514. dai_link[i].platform_of_node = phandle;
  2515. dai_link[i].platform_name = NULL;
  2516. }
  2517. cpu_dai:
  2518. /* populate cpu_of_node for snd card dai links */
  2519. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  2520. index = of_property_match_string(cdev->of_node,
  2521. "asoc-cpu-names",
  2522. dai_link[i].cpu_dai_name);
  2523. if (index < 0)
  2524. goto codec_dai;
  2525. phandle = of_parse_phandle(cdev->of_node, "asoc-cpu",
  2526. index);
  2527. if (!phandle) {
  2528. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  2529. __func__, dai_link[i].cpu_dai_name);
  2530. ret = -ENODEV;
  2531. goto err;
  2532. }
  2533. dai_link[i].cpu_of_node = phandle;
  2534. dai_link[i].cpu_dai_name = NULL;
  2535. }
  2536. codec_dai:
  2537. /* populate codec_of_node for snd card dai links */
  2538. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  2539. index = of_property_match_string(cdev->of_node,
  2540. "asoc-codec-names",
  2541. dai_link[i].codec_name);
  2542. if (index < 0)
  2543. continue;
  2544. phandle = of_parse_phandle(cdev->of_node, "asoc-codec",
  2545. index);
  2546. if (!phandle) {
  2547. pr_err("%s: retrieving phandle for codec dai %s failed\n",
  2548. __func__, dai_link[i].codec_name);
  2549. ret = -ENODEV;
  2550. goto err;
  2551. }
  2552. dai_link[i].codec_of_node = phandle;
  2553. dai_link[i].codec_name = NULL;
  2554. }
  2555. if (pdata->snd_card_val == INT_SND_CARD) {
  2556. if ((dai_link[i].id ==
  2557. MSM_BACKEND_DAI_INT0_MI2S_RX) ||
  2558. (dai_link[i].id ==
  2559. MSM_BACKEND_DAI_INT1_MI2S_RX) ||
  2560. (dai_link[i].id ==
  2561. MSM_BACKEND_DAI_INT2_MI2S_TX) ||
  2562. (dai_link[i].id ==
  2563. MSM_BACKEND_DAI_INT3_MI2S_TX)) {
  2564. index = of_property_match_string(cdev->of_node,
  2565. "asoc-codec-names",
  2566. MSM_INT_DIGITAL_CODEC);
  2567. phandle = of_parse_phandle(cdev->of_node,
  2568. "asoc-codec",
  2569. index);
  2570. dai_link[i].codecs[DIG_CDC].of_node = phandle;
  2571. index = of_property_match_string(cdev->of_node,
  2572. "asoc-codec-names",
  2573. PMIC_INT_ANALOG_CODEC);
  2574. phandle = of_parse_phandle(cdev->of_node,
  2575. "asoc-codec",
  2576. index);
  2577. dai_link[i].codecs[ANA_CDC].of_node = phandle;
  2578. }
  2579. }
  2580. }
  2581. err:
  2582. return ret;
  2583. }
  2584. static int msm_wsa881x_init(struct snd_soc_component *component)
  2585. {
  2586. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
  2587. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
  2588. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  2589. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  2590. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  2591. struct msm_asoc_mach_data *pdata;
  2592. struct snd_soc_dapm_context *dapm =
  2593. snd_soc_codec_get_dapm(codec);
  2594. if (!codec) {
  2595. pr_err("%s codec is NULL\n", __func__);
  2596. return -EINVAL;
  2597. }
  2598. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  2599. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  2600. __func__, codec->component.name);
  2601. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  2602. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2603. &ch_rate[0]);
  2604. if (dapm->component) {
  2605. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  2606. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  2607. }
  2608. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  2609. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  2610. __func__, codec->component.name);
  2611. wsa881x_set_channel_map(codec, &spkright_ports[0],
  2612. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  2613. &ch_rate[0]);
  2614. if (dapm->component) {
  2615. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  2616. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  2617. }
  2618. } else {
  2619. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  2620. codec->component.name);
  2621. return -EINVAL;
  2622. }
  2623. pdata = snd_soc_card_get_drvdata(component->card);
  2624. if (pdata && pdata->codec_root)
  2625. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  2626. codec);
  2627. return 0;
  2628. }
  2629. static int msm_init_wsa_dev(struct platform_device *pdev,
  2630. struct snd_soc_card *card)
  2631. {
  2632. struct device_node *wsa_of_node;
  2633. u32 wsa_max_devs;
  2634. u32 wsa_dev_cnt;
  2635. char *dev_name_str = NULL;
  2636. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  2637. const char *wsa_auxdev_name_prefix[1];
  2638. int found = 0;
  2639. int i;
  2640. int ret;
  2641. /* Get maximum WSA device count for this platform */
  2642. ret = of_property_read_u32(pdev->dev.of_node,
  2643. "qcom,wsa-max-devs", &wsa_max_devs);
  2644. if (ret) {
  2645. dev_dbg(&pdev->dev,
  2646. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  2647. __func__, pdev->dev.of_node->full_name, ret);
  2648. goto err_dt;
  2649. }
  2650. if (wsa_max_devs == 0) {
  2651. dev_warn(&pdev->dev,
  2652. "%s: Max WSA devices is 0 for this target?\n",
  2653. __func__);
  2654. goto err_dt;
  2655. }
  2656. /* Get count of WSA device phandles for this platform */
  2657. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  2658. "qcom,wsa-devs", NULL);
  2659. if (wsa_dev_cnt == -ENOENT) {
  2660. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  2661. __func__);
  2662. goto err_dt;
  2663. } else if (wsa_dev_cnt <= 0) {
  2664. dev_err(&pdev->dev,
  2665. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  2666. __func__, wsa_dev_cnt);
  2667. ret = -EINVAL;
  2668. goto err_dt;
  2669. }
  2670. /*
  2671. * Expect total phandles count to be NOT less than maximum possible
  2672. * WSA count. However, if it is less, then assign same value to
  2673. * max count as well.
  2674. */
  2675. if (wsa_dev_cnt < wsa_max_devs) {
  2676. dev_dbg(&pdev->dev,
  2677. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  2678. __func__, wsa_max_devs, wsa_dev_cnt);
  2679. wsa_max_devs = wsa_dev_cnt;
  2680. }
  2681. /* Make sure prefix string passed for each WSA device */
  2682. ret = of_property_count_strings(pdev->dev.of_node,
  2683. "qcom,wsa-aux-dev-prefix");
  2684. if (ret != wsa_dev_cnt) {
  2685. dev_err(&pdev->dev,
  2686. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  2687. __func__, wsa_dev_cnt, ret);
  2688. ret = -EINVAL;
  2689. goto err_dt;
  2690. }
  2691. /*
  2692. * Alloc mem to store phandle and index info of WSA device, if already
  2693. * registered with ALSA core
  2694. */
  2695. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  2696. sizeof(struct msm_wsa881x_dev_info),
  2697. GFP_KERNEL);
  2698. if (!wsa881x_dev_info) {
  2699. ret = -ENOMEM;
  2700. goto err_mem;
  2701. }
  2702. /*
  2703. * search and check whether all WSA devices are already
  2704. * registered with ALSA core or not. If found a node, store
  2705. * the node and the index in a local array of struct for later
  2706. * use.
  2707. */
  2708. for (i = 0; i < wsa_dev_cnt; i++) {
  2709. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  2710. "qcom,wsa-devs", i);
  2711. if (unlikely(!wsa_of_node)) {
  2712. /* we should not be here */
  2713. dev_err(&pdev->dev,
  2714. "%s: wsa dev node is not present\n",
  2715. __func__);
  2716. ret = -EINVAL;
  2717. goto err_dev_node;
  2718. }
  2719. if (soc_find_component(wsa_of_node, NULL)) {
  2720. /* WSA device registered with ALSA core */
  2721. wsa881x_dev_info[found].of_node = wsa_of_node;
  2722. wsa881x_dev_info[found].index = i;
  2723. found++;
  2724. if (found == wsa_max_devs)
  2725. break;
  2726. }
  2727. }
  2728. if (found < wsa_max_devs) {
  2729. dev_dbg(&pdev->dev,
  2730. "%s: failed to find %d components. Found only %d\n",
  2731. __func__, wsa_max_devs, found);
  2732. return -EPROBE_DEFER;
  2733. }
  2734. dev_info(&pdev->dev,
  2735. "%s: found %d wsa881x devices registered with ALSA core\n",
  2736. __func__, found);
  2737. card->num_aux_devs = wsa_max_devs;
  2738. card->num_configs = wsa_max_devs;
  2739. /* Alloc array of AUX devs struct */
  2740. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2741. sizeof(struct snd_soc_aux_dev),
  2742. GFP_KERNEL);
  2743. if (!msm_aux_dev) {
  2744. ret = -ENOMEM;
  2745. goto err_auxdev_mem;
  2746. }
  2747. /* Alloc array of codec conf struct */
  2748. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  2749. sizeof(struct snd_soc_codec_conf),
  2750. GFP_KERNEL);
  2751. if (!msm_codec_conf) {
  2752. ret = -ENOMEM;
  2753. goto err_codec_conf;
  2754. }
  2755. for (i = 0; i < card->num_aux_devs; i++) {
  2756. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  2757. GFP_KERNEL);
  2758. if (!dev_name_str) {
  2759. ret = -ENOMEM;
  2760. goto err_dev_str;
  2761. }
  2762. ret = of_property_read_string_index(pdev->dev.of_node,
  2763. "qcom,wsa-aux-dev-prefix",
  2764. wsa881x_dev_info[i].index,
  2765. wsa_auxdev_name_prefix);
  2766. if (ret) {
  2767. dev_err(&pdev->dev,
  2768. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  2769. __func__, ret);
  2770. ret = -EINVAL;
  2771. goto err_dt_prop;
  2772. }
  2773. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  2774. msm_aux_dev[i].name = dev_name_str;
  2775. msm_aux_dev[i].codec_name = NULL;
  2776. msm_aux_dev[i].codec_of_node =
  2777. wsa881x_dev_info[i].of_node;
  2778. msm_aux_dev[i].init = msm_wsa881x_init;
  2779. msm_codec_conf[i].dev_name = NULL;
  2780. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  2781. msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node;
  2782. }
  2783. card->codec_conf = msm_codec_conf;
  2784. card->aux_dev = msm_aux_dev;
  2785. return 0;
  2786. err_dt_prop:
  2787. devm_kfree(&pdev->dev, dev_name_str);
  2788. err_dev_str:
  2789. devm_kfree(&pdev->dev, msm_codec_conf);
  2790. err_codec_conf:
  2791. devm_kfree(&pdev->dev, msm_aux_dev);
  2792. err_auxdev_mem:
  2793. err_dev_node:
  2794. devm_kfree(&pdev->dev, wsa881x_dev_info);
  2795. err_mem:
  2796. err_dt:
  2797. return ret;
  2798. }
  2799. static void msm_free_auxdev_mem(struct platform_device *pdev)
  2800. {
  2801. struct snd_soc_card *card = platform_get_drvdata(pdev);
  2802. int i;
  2803. if (card->num_aux_devs > 0) {
  2804. for (i = 0; i < card->num_aux_devs; i++) {
  2805. kfree(msm_aux_dev[i].codec_name);
  2806. kfree(msm_codec_conf[i].dev_name);
  2807. kfree(msm_codec_conf[i].name_prefix);
  2808. }
  2809. }
  2810. }
  2811. static void i2s_auxpcm_init(struct platform_device *pdev)
  2812. {
  2813. int count;
  2814. u32 mi2s_master_slave[MI2S_MAX];
  2815. u32 mi2s_ext_mclk[MI2S_MAX];
  2816. int ret;
  2817. for (count = 0; count < MI2S_MAX; count++) {
  2818. mutex_init(&mi2s_intf_conf[count].lock);
  2819. mi2s_intf_conf[count].ref_cnt = 0;
  2820. }
  2821. ret = of_property_read_u32_array(pdev->dev.of_node,
  2822. "qcom,msm-mi2s-master",
  2823. mi2s_master_slave, MI2S_MAX);
  2824. if (ret) {
  2825. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  2826. __func__);
  2827. } else {
  2828. for (count = 0; count < MI2S_MAX; count++) {
  2829. mi2s_intf_conf[count].msm_is_mi2s_master =
  2830. mi2s_master_slave[count];
  2831. }
  2832. }
  2833. ret = of_property_read_u32_array(pdev->dev.of_node,
  2834. "qcom,msm-mi2s-ext-mclk",
  2835. mi2s_ext_mclk, MI2S_MAX);
  2836. if (ret) {
  2837. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n",
  2838. __func__);
  2839. } else {
  2840. for (count = 0; count < MI2S_MAX; count++)
  2841. mi2s_intf_conf[count].msm_is_ext_mclk =
  2842. mi2s_ext_mclk[count];
  2843. }
  2844. }
  2845. static const struct of_device_id sdm660_asoc_machine_of_match[] = {
  2846. { .compatible = "qcom,sdm660-asoc-snd",
  2847. .data = "internal_codec"},
  2848. { .compatible = "qcom,sdm660-asoc-snd-tasha",
  2849. .data = "tasha_codec"},
  2850. { .compatible = "qcom,sdm660-asoc-snd-tavil",
  2851. .data = "tavil_codec"},
  2852. { .compatible = "qcom,sdm670-asoc-snd",
  2853. .data = "internal_codec"},
  2854. { .compatible = "qcom,sdm670-asoc-snd-tasha",
  2855. .data = "tasha_codec"},
  2856. { .compatible = "qcom,sdm670-asoc-snd-tavil",
  2857. .data = "tavil_codec"},
  2858. {},
  2859. };
  2860. static int msm_asoc_machine_probe(struct platform_device *pdev)
  2861. {
  2862. struct snd_soc_card *card = NULL;
  2863. struct msm_asoc_mach_data *pdata = NULL;
  2864. const char *mclk = "qcom,msm-mclk-freq";
  2865. int ret = -EINVAL, id;
  2866. const struct of_device_id *match;
  2867. pdata = devm_kzalloc(&pdev->dev,
  2868. sizeof(struct msm_asoc_mach_data),
  2869. GFP_KERNEL);
  2870. if (!pdata)
  2871. return -ENOMEM;
  2872. msm_set_codec_reg_done(false);
  2873. match = of_match_node(sdm660_asoc_machine_of_match,
  2874. pdev->dev.of_node);
  2875. if (!match)
  2876. goto err;
  2877. ret = of_property_read_u32(pdev->dev.of_node, mclk, &id);
  2878. if (ret) {
  2879. dev_err(&pdev->dev,
  2880. "%s: missing %s in dt node\n", __func__, mclk);
  2881. id = DEFAULT_MCLK_RATE;
  2882. }
  2883. pdata->mclk_freq = id;
  2884. if (!strcmp(match->data, "tasha_codec") ||
  2885. !strcmp(match->data, "tavil_codec")) {
  2886. if (!strcmp(match->data, "tasha_codec"))
  2887. pdata->snd_card_val = EXT_SND_CARD_TASHA;
  2888. else
  2889. pdata->snd_card_val = EXT_SND_CARD_TAVIL;
  2890. ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2891. if (ret)
  2892. goto err;
  2893. } else if (!strcmp(match->data, "internal_codec")) {
  2894. pdata->snd_card_val = INT_SND_CARD;
  2895. ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg);
  2896. if (ret)
  2897. goto err;
  2898. } else {
  2899. dev_err(&pdev->dev,
  2900. "%s: Not a matching DT sound node\n", __func__);
  2901. goto err;
  2902. }
  2903. if (!card)
  2904. goto err;
  2905. if (pdata->snd_card_val == INT_SND_CARD) {
  2906. /*reading the gpio configurations from dtsi file*/
  2907. pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2908. "qcom,cdc-pdm-gpios", 0);
  2909. pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2910. "qcom,cdc-comp-gpios", 0);
  2911. pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2912. "qcom,cdc-dmic-gpios", 0);
  2913. pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2914. "qcom,cdc-ext-spk-gpios", 0);
  2915. }
  2916. /*
  2917. * Parse US-Euro gpio info from DT. Report no error if us-euro
  2918. * entry is not found in DT file as some targets do not support
  2919. * US-Euro detection
  2920. */
  2921. pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node,
  2922. "qcom,us-euro-gpios", 0);
  2923. if (!gpio_is_valid(pdata->us_euro_gpio))
  2924. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  2925. "qcom,us-euro-gpios", 0);
  2926. if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) {
  2927. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  2928. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  2929. } else {
  2930. dev_dbg(&pdev->dev, "%s detected",
  2931. "qcom,us-euro-gpios");
  2932. mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  2933. }
  2934. ret = msm_prepare_us_euro(card);
  2935. if (ret)
  2936. dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
  2937. ret);
  2938. i2s_auxpcm_init(pdev);
  2939. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  2940. if (ret)
  2941. goto err;
  2942. ret = msm_populate_dai_link_component_of_node(pdata, card);
  2943. if (ret) {
  2944. ret = -EPROBE_DEFER;
  2945. goto err;
  2946. }
  2947. if (!of_property_read_bool(pdev->dev.of_node, "qcom,wsa-disable")) {
  2948. ret = msm_init_wsa_dev(pdev, card);
  2949. if (ret)
  2950. goto err;
  2951. }
  2952. ret = devm_snd_soc_register_card(&pdev->dev, card);
  2953. if (ret == -EPROBE_DEFER) {
  2954. if (codec_reg_done) {
  2955. /*
  2956. * return failure as EINVAL since other codec
  2957. * registered sound card successfully.
  2958. * This avoids any further probe calls.
  2959. */
  2960. ret = -EINVAL;
  2961. }
  2962. goto err;
  2963. } else if (ret) {
  2964. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  2965. ret);
  2966. goto err;
  2967. }
  2968. if (pdata->snd_card_val != INT_SND_CARD)
  2969. msm_ext_register_audio_notifier(pdev);
  2970. return 0;
  2971. err:
  2972. if (pdata->us_euro_gpio > 0) {
  2973. dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n",
  2974. __func__, pdata->us_euro_gpio);
  2975. pdata->us_euro_gpio = 0;
  2976. }
  2977. if (pdata->hph_en1_gpio > 0) {
  2978. dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n",
  2979. __func__, pdata->hph_en1_gpio);
  2980. gpio_free(pdata->hph_en1_gpio);
  2981. pdata->hph_en1_gpio = 0;
  2982. }
  2983. if (pdata->hph_en0_gpio > 0) {
  2984. dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n",
  2985. __func__, pdata->hph_en0_gpio);
  2986. gpio_free(pdata->hph_en0_gpio);
  2987. pdata->hph_en0_gpio = 0;
  2988. }
  2989. devm_kfree(&pdev->dev, pdata);
  2990. return ret;
  2991. }
  2992. static int msm_asoc_machine_remove(struct platform_device *pdev)
  2993. {
  2994. struct snd_soc_card *card = platform_get_drvdata(pdev);
  2995. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  2996. if (pdata->snd_card_val == INT_SND_CARD)
  2997. mutex_destroy(&pdata->cdc_int_mclk0_mutex);
  2998. msm_free_auxdev_mem(pdev);
  2999. gpio_free(pdata->us_euro_gpio);
  3000. gpio_free(pdata->hph_en1_gpio);
  3001. gpio_free(pdata->hph_en0_gpio);
  3002. snd_soc_unregister_card(card);
  3003. return 0;
  3004. }
  3005. static struct platform_driver sdm660_asoc_machine_driver = {
  3006. .driver = {
  3007. .name = DRV_NAME,
  3008. .owner = THIS_MODULE,
  3009. .pm = &snd_soc_pm_ops,
  3010. .of_match_table = sdm660_asoc_machine_of_match,
  3011. },
  3012. .probe = msm_asoc_machine_probe,
  3013. .remove = msm_asoc_machine_remove,
  3014. };
  3015. module_platform_driver(sdm660_asoc_machine_driver);
  3016. MODULE_DESCRIPTION("ALSA SoC msm");
  3017. MODULE_LICENSE("GPL v2");
  3018. MODULE_ALIAS("platform:" DRV_NAME);
  3019. MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);