ubwcp_main.c 89 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "%s: %s(): " fmt, KBUILD_MODNAME, __func__
  6. #include <linux/module.h>
  7. #include <linux/kernel.h>
  8. #include <linux/dma-buf.h>
  9. #include <linux/slab.h>
  10. #include <linux/cdev.h>
  11. #include <linux/hashtable.h>
  12. #include <linux/scatterlist.h>
  13. #include <linux/types.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/of_address.h>
  18. #include <linux/genalloc.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/numa.h>
  22. #include <linux/memory_hotplug.h>
  23. #include <asm/page.h>
  24. #include <linux/delay.h>
  25. #include <linux/ubwcp_dma_heap.h>
  26. #include <linux/debugfs.h>
  27. #include <linux/clk.h>
  28. #include <linux/iommu.h>
  29. #include <linux/set_memory.h>
  30. #include <linux/range.h>
  31. #include <linux/qcom_scm.h>
  32. MODULE_IMPORT_NS(DMA_BUF);
  33. #include "include/kernel/ubwcp.h"
  34. #include "ubwcp_hw.h"
  35. #include "include/uapi/ubwcp_ioctl.h"
  36. #define CREATE_TRACE_POINTS
  37. #include "ubwcp_trace.h"
  38. #define UBWCP_NUM_DEVICES 1
  39. #define UBWCP_DEVICE_NAME "ubwcp"
  40. #define UBWCP_BUFFER_DESC_OFFSET 64
  41. #define UBWCP_BUFFER_DESC_COUNT 256
  42. #define CACHE_ADDR(x) ((x) >> 6)
  43. #define PAGE_ADDR(x) ((x) >> 12)
  44. #define UBWCP_ALIGN(_x, _y) ((((_x) + (_y) - 1)/(_y))*(_y))
  45. #define DBG_BUF_ATTR(fmt, args...) do { if (unlikely(ubwcp_debug_trace_enable)) \
  46. pr_err(fmt "\n", ##args); \
  47. } while (0)
  48. #define DBG(fmt, args...) do { if (unlikely(ubwcp_debug_trace_enable)) \
  49. pr_err(fmt "\n", ##args); \
  50. } while (0)
  51. #define ERR(fmt, args...) pr_err_ratelimited("%d: ~~~ERROR~~~: " fmt "\n", __LINE__, ##args)
  52. #define META_DATA_PITCH_ALIGN 64
  53. #define META_DATA_HEIGHT_ALIGN 16
  54. #define META_DATA_SIZE_ALIGN 4096
  55. #define PIXEL_DATA_SIZE_ALIGN 4096
  56. #define UBWCP_SYNC_GRANULE 0x4000000L /* 64 MB */
  57. /* Max values for attributes */
  58. #define MAX_ATTR_WIDTH (10*1024)
  59. #define MAX_ATTR_HEIGHT (10*1024)
  60. #define MAX_ATTR_STRIDE (64*1024)
  61. #define MAX_ATTR_PLANAR_PAD 4096
  62. #define MAX_ATTR_SCANLN_HT_DELTA (32*1024)
  63. enum ula_remove_mem_status {
  64. ULA_REMOVE_MEM_SUCCESS = 0,
  65. ULA_REMOVE_MEM_ABORTED = 1
  66. };
  67. struct ubwcp_desc {
  68. int idx;
  69. void *ptr;
  70. };
  71. struct tile_dimension {
  72. u16 width;
  73. u16 height;
  74. };
  75. struct ubwcp_plane_info {
  76. u16 pixel_bytes;
  77. u16 per_pixel;
  78. struct tile_dimension tilesize_p; /* pixels */
  79. struct tile_dimension macrotilesize_p; /* pixels */
  80. };
  81. struct ubwcp_image_format_info {
  82. u16 planes;
  83. struct ubwcp_plane_info p_info[2];
  84. };
  85. enum ubwcp_std_image_format {
  86. RGBA = 0,
  87. NV12 = 1,
  88. NV124R = 2,
  89. P010 = 3,
  90. TP10 = 4,
  91. P016 = 5,
  92. INFO_FORMAT_LIST_SIZE,
  93. };
  94. enum ubwcp_state {
  95. UBWCP_STATE_READY = 0,
  96. UBWCP_STATE_INVALID = -1,
  97. UBWCP_STATE_FAULT = -2,
  98. };
  99. struct ubwcp_prefetch_tgt_ctrl {
  100. atomic_t cpu_count;
  101. bool enable;
  102. int result;
  103. };
  104. struct ubwcp_driver {
  105. /* cdev related */
  106. dev_t devt;
  107. struct class *dev_class; //sysfs dev class
  108. struct device *dev_sys; //sysfs dev
  109. struct cdev cdev; //char dev
  110. /* debugfs */
  111. struct dentry *debugfs_root;
  112. bool read_err_irq_en;
  113. bool write_err_irq_en;
  114. bool decode_err_irq_en;
  115. bool encode_err_irq_en;
  116. /* ubwcp devices */
  117. struct device *dev; //ubwcp device
  118. struct device *dev_desc_cb; //smmu dev for descriptors
  119. struct device *dev_buf_cb; //smmu dev for ubwcp buffers
  120. void __iomem *base; //ubwcp base address
  121. struct regulator *vdd;
  122. struct clk **clocks;
  123. int num_clocks;
  124. /* interrupts */
  125. int irq_range_ck_rd;
  126. int irq_range_ck_wr;
  127. int irq_encode;
  128. int irq_decode;
  129. /* ula address pool */
  130. u64 ula_pool_base;
  131. u64 ula_pool_size;
  132. struct gen_pool *ula_pool;
  133. configure_mmap mmap_config_fptr;
  134. /* HW version */
  135. u32 hw_ver_major;
  136. u32 hw_ver_minor;
  137. /* keep track of all potential buffers.
  138. * hash table index'ed using dma_buf ptr.
  139. * 2**13 = 8192 hash values
  140. */
  141. DECLARE_HASHTABLE(buf_table, 13);
  142. /* buffer descriptor */
  143. void *buffer_desc_base; /* CPU address */
  144. dma_addr_t buffer_desc_dma_handle; /* dma address */
  145. size_t buffer_desc_size;
  146. struct ubwcp_desc desc_list[UBWCP_BUFFER_DESC_COUNT];
  147. struct ubwcp_image_format_info format_info[INFO_FORMAT_LIST_SIZE];
  148. /* driver state */
  149. enum ubwcp_state state;
  150. atomic_t num_non_lin_buffers;
  151. bool mem_online;
  152. struct mutex desc_lock; /* allocate/free descriptors */
  153. spinlock_t buf_table_lock; /* add/remove dma_buf into list of managed bufffers */
  154. struct mutex mem_hotplug_lock; /* memory hotplug lock */
  155. struct mutex ula_lock; /* allocate/free ula */
  156. struct mutex ubwcp_flush_lock; /* ubwcp flush */
  157. struct mutex hw_range_ck_lock; /* range ck */
  158. struct list_head err_handler_list; /* error handler list */
  159. spinlock_t err_handler_list_lock; /* err_handler_list lock */
  160. struct dev_pagemap pgmap;
  161. /* power state tracking */
  162. int power_on;
  163. struct mutex power_ctrl_lock;
  164. struct ubwcp_prefetch_tgt_ctrl ctrl;
  165. };
  166. struct ubwcp_buf {
  167. struct hlist_node hnode;
  168. struct ubwcp_driver *ubwcp;
  169. struct ubwcp_buffer_attrs buf_attr;
  170. bool perm;
  171. struct ubwcp_desc *desc;
  172. bool buf_attr_set;
  173. enum dma_data_direction dma_dir;
  174. int lock_count;
  175. /* dma_buf info */
  176. struct dma_buf *dma_buf;
  177. struct dma_buf_attachment *attachment;
  178. struct sg_table *sgt;
  179. /* ula info */
  180. phys_addr_t ula_pa;
  181. size_t ula_size;
  182. /* meta metadata */
  183. struct ubwcp_hw_meta_metadata mmdata;
  184. struct mutex lock;
  185. };
  186. static struct ubwcp_driver *me;
  187. static u32 ubwcp_debug_trace_enable;
  188. static void prefetch_tgt_per_cpu(void *info)
  189. {
  190. int ret = 0;
  191. struct ubwcp_prefetch_tgt_ctrl *ctrl;
  192. ctrl = (struct ubwcp_prefetch_tgt_ctrl *) info;
  193. ret = qcom_scm_prefetch_tgt_ctrl(ctrl->enable);
  194. if (ret) {
  195. //ctrl->result = ret;
  196. //ERR("scm call failed, ret: %d enable: %d", ret, ctrl->enable);
  197. DBG("scm call failed, ret: %d missing the matching TZ?", ret);
  198. }
  199. atomic_dec(&ctrl->cpu_count);
  200. }
  201. /* Enable/disable generation of prefetch target opcode. smc call must be done from each core
  202. * to update the core specific register. Not thread-safe.
  203. */
  204. static int prefetch_tgt(struct ubwcp_driver *ubwcp, bool enable)
  205. {
  206. int cpu;
  207. trace_ubwcp_prefetch_tgt_start(enable);
  208. DBG("enable: %d", enable);
  209. ubwcp->ctrl.enable = enable;
  210. ubwcp->ctrl.result = 0;
  211. atomic_set(&ubwcp->ctrl.cpu_count, 0);
  212. cpus_read_lock();
  213. for_each_cpu(cpu, cpu_online_mask) {
  214. atomic_inc(&ubwcp->ctrl.cpu_count);
  215. smp_call_function_single(cpu, prefetch_tgt_per_cpu, (void *) &ubwcp->ctrl, false);
  216. }
  217. cpus_read_unlock();
  218. while (atomic_read(&ubwcp->ctrl.cpu_count))
  219. ;
  220. DBG("done");
  221. trace_ubwcp_prefetch_tgt_end(enable);
  222. return ubwcp->ctrl.result;
  223. }
  224. static struct ubwcp_driver *ubwcp_get_driver(void)
  225. {
  226. if (!me)
  227. WARN(1, "ubwcp: driver ptr requested but driver not initialized");
  228. return me;
  229. }
  230. static void image_format_init(struct ubwcp_driver *ubwcp)
  231. { /* planes, bytes/p, Tp , MTp */
  232. ubwcp->format_info[RGBA] = (struct ubwcp_image_format_info)
  233. {1, {{4, 1, {16, 4}, {64, 16}}}};
  234. ubwcp->format_info[NV12] = (struct ubwcp_image_format_info)
  235. {2, {{1, 1, {32, 8}, {128, 32}},
  236. {2, 1, {16, 8}, { 64, 32}}}};
  237. ubwcp->format_info[NV124R] = (struct ubwcp_image_format_info)
  238. {2, {{1, 1, {64, 4}, {256, 16}},
  239. {2, 1, {32, 4}, {128, 16}}}};
  240. ubwcp->format_info[P010] = (struct ubwcp_image_format_info)
  241. {2, {{2, 1, {32, 4}, {128, 16}},
  242. {4, 1, {16, 4}, { 64, 16}}}};
  243. ubwcp->format_info[TP10] = (struct ubwcp_image_format_info)
  244. {2, {{4, 3, {48, 4}, {192, 16}},
  245. {8, 3, {24, 4}, { 96, 16}}}};
  246. ubwcp->format_info[P016] = (struct ubwcp_image_format_info)
  247. {2, {{2, 1, {32, 4}, {128, 16}},
  248. {4, 1, {16, 4}, { 64, 16}}}};
  249. }
  250. static void ubwcp_buf_desc_list_init(struct ubwcp_driver *ubwcp)
  251. {
  252. int idx;
  253. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  254. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  255. desc_list[idx].idx = -1;
  256. desc_list[idx].ptr = NULL;
  257. }
  258. }
  259. static int ubwcp_init_clocks(struct ubwcp_driver *ubwcp, struct device *dev)
  260. {
  261. const char *cname;
  262. struct property *prop;
  263. int i;
  264. ubwcp->num_clocks =
  265. of_property_count_strings(dev->of_node, "clock-names");
  266. if (ubwcp->num_clocks < 1) {
  267. ubwcp->num_clocks = 0;
  268. return 0;
  269. }
  270. ubwcp->clocks = devm_kzalloc(dev,
  271. sizeof(*ubwcp->clocks) * ubwcp->num_clocks, GFP_KERNEL);
  272. if (!ubwcp->clocks)
  273. return -ENOMEM;
  274. i = 0;
  275. of_property_for_each_string(dev->of_node, "clock-names",
  276. prop, cname) {
  277. struct clk *c = devm_clk_get(dev, cname);
  278. if (IS_ERR(c)) {
  279. ERR("Couldn't get clock: %s\n", cname);
  280. return PTR_ERR(c);
  281. }
  282. ubwcp->clocks[i] = c;
  283. ++i;
  284. }
  285. return 0;
  286. }
  287. static int ubwcp_enable_clocks(struct ubwcp_driver *ubwcp)
  288. {
  289. int i, ret = 0;
  290. for (i = 0; i < ubwcp->num_clocks; ++i) {
  291. ret = clk_prepare_enable(ubwcp->clocks[i]);
  292. if (ret) {
  293. ERR("Couldn't enable clock #%d\n", i);
  294. while (i--)
  295. clk_disable_unprepare(ubwcp->clocks[i]);
  296. break;
  297. }
  298. }
  299. return ret;
  300. }
  301. static void ubwcp_disable_clocks(struct ubwcp_driver *ubwcp)
  302. {
  303. int i;
  304. for (i = ubwcp->num_clocks; i; --i)
  305. clk_disable_unprepare(ubwcp->clocks[i - 1]);
  306. }
  307. /* UBWCP Power control
  308. * Due to hw bug, ubwcp block cannot handle prefetch target opcode. Thus we disable the opcode
  309. * when ubwcp is powered on and enable it back when ubwcp is powered off.
  310. */
  311. static int ubwcp_power(struct ubwcp_driver *ubwcp, bool enable)
  312. {
  313. int ret = 0;
  314. mutex_lock(&ubwcp->power_ctrl_lock);
  315. if (enable) {
  316. ubwcp->power_on++;
  317. if (ubwcp->power_on != 1)
  318. goto done;
  319. } else {
  320. ubwcp->power_on--;
  321. if (ubwcp->power_on != 0)
  322. goto done;
  323. }
  324. if (enable) {
  325. ret = prefetch_tgt(ubwcp, 0);
  326. if (ret)
  327. goto done;
  328. ret = regulator_enable(ubwcp->vdd);
  329. if (ret) {
  330. ERR("regulator call (enable: %d) failed: %d", enable, ret);
  331. goto done;
  332. }
  333. ret = ubwcp_enable_clocks(ubwcp);
  334. if (ret) {
  335. ERR("enable clocks failed: %d", ret);
  336. regulator_disable(ubwcp->vdd);
  337. goto done;
  338. }
  339. } else {
  340. ret = regulator_disable(ubwcp->vdd);
  341. if (ret) {
  342. ERR("regulator call (enable: %d) failed: %d", enable, ret);
  343. goto done;
  344. }
  345. ubwcp_disable_clocks(ubwcp);
  346. ret = prefetch_tgt(ubwcp, 1);
  347. }
  348. done:
  349. mutex_unlock(&ubwcp->power_ctrl_lock);
  350. return ret;
  351. }
  352. /* get ubwcp_buf corresponding to the given dma_buf */
  353. static struct ubwcp_buf *dma_buf_to_ubwcp_buf(struct dma_buf *dmabuf)
  354. {
  355. struct ubwcp_buf *buf = NULL;
  356. struct ubwcp_buf *ret_buf = NULL;
  357. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  358. unsigned long flags;
  359. if (!dmabuf || !ubwcp)
  360. return NULL;
  361. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  362. /* look up ubwcp_buf corresponding to this dma_buf */
  363. hash_for_each_possible(ubwcp->buf_table, buf, hnode, (u64)dmabuf) {
  364. if (buf->dma_buf == dmabuf) {
  365. ret_buf = buf;
  366. break;
  367. }
  368. }
  369. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  370. return ret_buf;
  371. }
  372. /* return ubwcp hardware version */
  373. int ubwcp_get_hw_version(struct ubwcp_ioctl_hw_version *ver)
  374. {
  375. struct ubwcp_driver *ubwcp;
  376. if (!ver) {
  377. ERR("invalid version ptr");
  378. return -EINVAL;
  379. }
  380. ubwcp = ubwcp_get_driver();
  381. if (!ubwcp)
  382. return -1;
  383. if (ubwcp->state == UBWCP_STATE_INVALID)
  384. return -EPERM;
  385. ver->major = ubwcp->hw_ver_major;
  386. ver->minor = ubwcp->hw_ver_minor;
  387. return 0;
  388. }
  389. EXPORT_SYMBOL(ubwcp_get_hw_version);
  390. static int ula_add_mem(struct ubwcp_driver *ubwcp)
  391. {
  392. int ret = 0;
  393. int nid;
  394. void *ptr;
  395. nid = memory_add_physaddr_to_nid(ubwcp->ula_pool_base);
  396. DBG("calling memremap_pages()...");
  397. ubwcp->pgmap.type = MEMORY_DEVICE_GENERIC;
  398. ubwcp->pgmap.nr_range = 1;
  399. ubwcp->pgmap.range.start = ubwcp->ula_pool_base;
  400. ubwcp->pgmap.range.end = ubwcp->ula_pool_base + ubwcp->ula_pool_size - 1;
  401. trace_ubwcp_memremap_pages_start(ubwcp->ula_pool_size);
  402. ptr = memremap_pages(&ubwcp->pgmap, nid);
  403. trace_ubwcp_memremap_pages_end(ubwcp->ula_pool_size);
  404. if (IS_ERR(ptr)) {
  405. ret = IS_ERR(ptr);
  406. ERR("memremap_pages() failed st:0x%lx sz:0x%lx err: %d",
  407. ubwcp->ula_pool_base,
  408. ubwcp->ula_pool_size,
  409. ret);
  410. } else {
  411. DBG("memremap_pages() ula_pool_base:0x%llx, size:0x%zx, kernel addr:0x%p",
  412. ubwcp->ula_pool_base,
  413. ubwcp->ula_pool_size,
  414. page_to_virt(pfn_to_page(PFN_DOWN(ubwcp->ula_pool_base))));
  415. }
  416. return ret;
  417. }
  418. static int ula_map_uncached(u64 base, u64 size)
  419. {
  420. int ret;
  421. trace_ubwcp_set_direct_map_range_uncached_start(size);
  422. ret = set_direct_map_range_uncached((unsigned long)phys_to_virt(base), size >> PAGE_SHIFT);
  423. trace_ubwcp_set_direct_map_range_uncached_end(size);
  424. if (ret)
  425. ERR("set_direct_map_range_uncached failed st:0x%lx num pages:%lu err: %d",
  426. base, size >> PAGE_SHIFT, ret);
  427. return ret;
  428. }
  429. static void ula_unmap(struct ubwcp_driver *ubwcp)
  430. {
  431. DBG("Calling memunmap_pages() for ULA PA pool");
  432. trace_ubwcp_memunmap_pages_start(ubwcp->ula_pool_size);
  433. memunmap_pages(&ubwcp->pgmap);
  434. trace_ubwcp_memunmap_pages_end(ubwcp->ula_pool_size);
  435. }
  436. static void ula_sync_for_cpu(struct device *dev, u64 addr, unsigned long size)
  437. {
  438. trace_ubwcp_dma_sync_single_for_cpu_start(size, DMA_BIDIRECTIONAL);
  439. dma_sync_single_for_cpu(dev, addr, size, DMA_BIDIRECTIONAL);
  440. trace_ubwcp_dma_sync_single_for_cpu_end(size, DMA_BIDIRECTIONAL);
  441. }
  442. /** Remove ula memory in chunks
  443. * Abort if new buffer addition is detected
  444. * If remove succeeds or aborted, return success
  445. * status value indicates if mem was removed or aborted (not removed)
  446. * Otherwise return failure
  447. */
  448. static int ula_remove_mem(struct ubwcp_driver *ubwcp, enum ula_remove_mem_status *status)
  449. {
  450. int ret = 0;
  451. unsigned long sync_remain = ubwcp->ula_pool_size;
  452. unsigned long sync_offset = 0;
  453. unsigned long sync_size = 0;
  454. ret = ula_map_uncached(ubwcp->ula_pool_base, ubwcp->ula_pool_size);
  455. if (ret)
  456. return ret;
  457. trace_ubwcp_offline_sync_start(ubwcp->ula_pool_size);
  458. while (sync_remain > 0) {
  459. if (atomic_read(&ubwcp->num_non_lin_buffers) > 0) {
  460. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  461. ula_unmap(ubwcp);
  462. if (ula_add_mem(ubwcp)) {
  463. ERR("remove mem: failed to add back during abort");
  464. return -1;
  465. }
  466. *status = ULA_REMOVE_MEM_ABORTED;
  467. return 0;
  468. }
  469. if (UBWCP_SYNC_GRANULE > sync_remain) {
  470. sync_size = sync_remain;
  471. sync_remain = 0;
  472. } else {
  473. sync_size = UBWCP_SYNC_GRANULE;
  474. sync_remain -= UBWCP_SYNC_GRANULE;
  475. }
  476. ula_sync_for_cpu(ubwcp->dev, ubwcp->ula_pool_base + sync_offset, sync_size);
  477. sync_offset += sync_size;
  478. }
  479. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  480. ula_unmap(ubwcp);
  481. *status = ULA_REMOVE_MEM_SUCCESS;
  482. return 0;
  483. }
  484. static int inc_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  485. {
  486. atomic_inc(&ubwcp->num_non_lin_buffers);
  487. mutex_lock(&ubwcp->mem_hotplug_lock);
  488. if (!ubwcp->mem_online) {
  489. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  490. ERR("Bad state: num_non_lin_buffers should not be 0");
  491. goto err;
  492. }
  493. if (ubwcp_power(ubwcp, true))
  494. goto err;
  495. if (ula_add_mem(ubwcp))
  496. goto err_add_memory;
  497. ubwcp->mem_online = true;
  498. }
  499. mutex_unlock(&ubwcp->mem_hotplug_lock);
  500. return 0;
  501. err_add_memory:
  502. ubwcp_power(ubwcp, false);
  503. err:
  504. atomic_dec(&ubwcp->num_non_lin_buffers);
  505. mutex_unlock(&ubwcp->mem_hotplug_lock);
  506. ubwcp->state = UBWCP_STATE_FAULT;
  507. ERR("state set to fault");
  508. return -1;
  509. }
  510. static int dec_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  511. {
  512. int ret;
  513. enum ula_remove_mem_status remove_status;
  514. atomic_dec(&ubwcp->num_non_lin_buffers);
  515. mutex_lock(&ubwcp->mem_hotplug_lock);
  516. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  517. DBG("last buffer: ~~~~~~~~~~~");
  518. if (!ubwcp->mem_online) {
  519. ERR("Bad state: mem_online should not be false");
  520. goto err;
  521. }
  522. ret = ula_remove_mem(ubwcp, &remove_status);
  523. if (ret)
  524. goto err;
  525. if (remove_status == ULA_REMOVE_MEM_SUCCESS) {
  526. ubwcp->mem_online = false;
  527. if (ubwcp_power(ubwcp, false))
  528. goto err;
  529. } else if (remove_status == ULA_REMOVE_MEM_ABORTED) {
  530. DBG("ula memory offline aborted");
  531. } else {
  532. ERR("unexpected ula remove status: %d", remove_status);
  533. goto err;
  534. }
  535. }
  536. mutex_unlock(&ubwcp->mem_hotplug_lock);
  537. return 0;
  538. err:
  539. atomic_inc(&ubwcp->num_non_lin_buffers);
  540. mutex_unlock(&ubwcp->mem_hotplug_lock);
  541. ubwcp->state = UBWCP_STATE_FAULT;
  542. ERR("state set to fault");
  543. return -1;
  544. }
  545. /**
  546. *
  547. * Initialize ubwcp buffer for the given dma_buf. This
  548. * initializes ubwcp internal data structures and possibly hw to
  549. * use ubwcp for this buffer.
  550. *
  551. * @param dmabuf : ptr to the buffer to be configured for ubwcp
  552. *
  553. * @return int : 0 on success, otherwise error code
  554. */
  555. static int ubwcp_init_buffer(struct dma_buf *dmabuf)
  556. {
  557. struct ubwcp_buf *buf;
  558. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  559. unsigned long flags;
  560. trace_ubwcp_init_buffer_start(dmabuf);
  561. if (!ubwcp) {
  562. trace_ubwcp_init_buffer_end(dmabuf);
  563. return -1;
  564. }
  565. if (ubwcp->state != UBWCP_STATE_READY) {
  566. ERR("driver in invalid state: %d", ubwcp->state);
  567. trace_ubwcp_init_buffer_end(dmabuf);
  568. return -EPERM;
  569. }
  570. if (!dmabuf) {
  571. ERR("NULL dmabuf input ptr");
  572. trace_ubwcp_init_buffer_end(dmabuf);
  573. return -EINVAL;
  574. }
  575. if (dma_buf_to_ubwcp_buf(dmabuf)) {
  576. ERR("dma_buf already initialized for ubwcp");
  577. trace_ubwcp_init_buffer_end(dmabuf);
  578. return -EEXIST;
  579. }
  580. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  581. if (!buf) {
  582. ERR("failed to alloc for new ubwcp_buf");
  583. trace_ubwcp_init_buffer_end(dmabuf);
  584. return -ENOMEM;
  585. }
  586. mutex_init(&buf->lock);
  587. buf->dma_buf = dmabuf;
  588. buf->ubwcp = ubwcp;
  589. buf->buf_attr.image_format = UBWCP_LINEAR;
  590. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  591. hash_add(ubwcp->buf_table, &buf->hnode, (u64)buf->dma_buf);
  592. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  593. trace_ubwcp_init_buffer_end(dmabuf);
  594. return 0;
  595. }
  596. static void dump_attributes(struct ubwcp_buffer_attrs *attr)
  597. {
  598. DBG_BUF_ATTR("");
  599. DBG_BUF_ATTR("image_format: %d", attr->image_format);
  600. DBG_BUF_ATTR("major_ubwc_ver: %d", attr->major_ubwc_ver);
  601. DBG_BUF_ATTR("minor_ubwc_ver: %d", attr->minor_ubwc_ver);
  602. DBG_BUF_ATTR("compression_type: %d", attr->compression_type);
  603. DBG_BUF_ATTR("lossy_params: %llu", attr->lossy_params);
  604. DBG_BUF_ATTR("width: %d", attr->width);
  605. DBG_BUF_ATTR("height: %d", attr->height);
  606. DBG_BUF_ATTR("stride: %d", attr->stride);
  607. DBG_BUF_ATTR("scanlines: %d", attr->scanlines);
  608. DBG_BUF_ATTR("planar_padding: %d", attr->planar_padding);
  609. DBG_BUF_ATTR("subsample: %d", attr->subsample);
  610. DBG_BUF_ATTR("sub_system_target: %d", attr->sub_system_target);
  611. DBG_BUF_ATTR("y_offset: %d", attr->y_offset);
  612. DBG_BUF_ATTR("batch_size: %d", attr->batch_size);
  613. DBG_BUF_ATTR("");
  614. }
  615. static int to_std_format(u16 ioctl_image_format, enum ubwcp_std_image_format *format)
  616. {
  617. switch (ioctl_image_format) {
  618. case UBWCP_RGBA8888:
  619. *format = RGBA;
  620. return 0;
  621. case UBWCP_NV12:
  622. case UBWCP_NV12_Y:
  623. case UBWCP_NV12_UV:
  624. *format = NV12;
  625. return 0;
  626. case UBWCP_NV124R:
  627. case UBWCP_NV124R_Y:
  628. case UBWCP_NV124R_UV:
  629. *format = NV124R;
  630. return 0;
  631. case UBWCP_TP10:
  632. case UBWCP_TP10_Y:
  633. case UBWCP_TP10_UV:
  634. *format = TP10;
  635. return 0;
  636. case UBWCP_P010:
  637. case UBWCP_P010_Y:
  638. case UBWCP_P010_UV:
  639. *format = P010;
  640. return 0;
  641. case UBWCP_P016:
  642. case UBWCP_P016_Y:
  643. case UBWCP_P016_UV:
  644. *format = P016;
  645. return 0;
  646. default:
  647. ERR("Failed to convert ioctl image format to std format: %d", ioctl_image_format);
  648. return -1;
  649. }
  650. }
  651. static int std_to_hw_img_fmt(enum ubwcp_std_image_format format, u16 *hw_fmt)
  652. {
  653. switch (format) {
  654. case RGBA:
  655. *hw_fmt = HW_BUFFER_FORMAT_RGBA;
  656. return 0;
  657. case NV12:
  658. *hw_fmt = HW_BUFFER_FORMAT_NV12;
  659. return 0;
  660. case NV124R:
  661. *hw_fmt = HW_BUFFER_FORMAT_NV124R;
  662. return 0;
  663. case P010:
  664. *hw_fmt = HW_BUFFER_FORMAT_P010;
  665. return 0;
  666. case TP10:
  667. *hw_fmt = HW_BUFFER_FORMAT_TP10;
  668. return 0;
  669. case P016:
  670. *hw_fmt = HW_BUFFER_FORMAT_P016;
  671. return 0;
  672. default:
  673. ERR("Failed to convert std image format to hw format: %d", format);
  674. return -1;
  675. }
  676. }
  677. static int get_stride_alignment(enum ubwcp_std_image_format format, u16 *align)
  678. {
  679. switch (format) {
  680. case TP10:
  681. *align = 64;
  682. return 0;
  683. case NV12:
  684. *align = 128;
  685. return 0;
  686. case RGBA:
  687. case NV124R:
  688. case P010:
  689. case P016:
  690. *align = 256;
  691. return 0;
  692. default:
  693. return -1;
  694. }
  695. }
  696. /* returns stride of compressed image */
  697. static u32 get_compressed_stride(struct ubwcp_driver *ubwcp,
  698. enum ubwcp_std_image_format format, u32 width)
  699. {
  700. struct ubwcp_plane_info p_info;
  701. u16 macro_tile_width_p;
  702. u16 pixel_bytes;
  703. u16 per_pixel;
  704. p_info = ubwcp->format_info[format].p_info[0];
  705. macro_tile_width_p = p_info.macrotilesize_p.width;
  706. pixel_bytes = p_info.pixel_bytes;
  707. per_pixel = p_info.per_pixel;
  708. return UBWCP_ALIGN(width, macro_tile_width_p)*pixel_bytes/per_pixel;
  709. }
  710. static void
  711. ubwcp_pixel_to_bytes(struct ubwcp_driver *ubwcp,
  712. enum ubwcp_std_image_format format,
  713. u32 width_p, u32 height_p,
  714. u32 *width_b, u32 *height_b)
  715. {
  716. u16 pixel_bytes;
  717. u16 per_pixel;
  718. struct ubwcp_image_format_info f_info;
  719. struct ubwcp_plane_info p_info;
  720. f_info = ubwcp->format_info[format];
  721. p_info = f_info.p_info[0];
  722. pixel_bytes = p_info.pixel_bytes;
  723. per_pixel = p_info.per_pixel;
  724. *width_b = (width_p*pixel_bytes)/per_pixel;
  725. *height_b = (height_p*pixel_bytes)/per_pixel;
  726. }
  727. /* check if linear stride conforms to hw limitations
  728. * always returns false for linear image
  729. */
  730. static bool stride_is_valid(struct ubwcp_driver *ubwcp,
  731. enum ubwcp_std_image_format format, u32 width, u32 lin_stride)
  732. {
  733. u32 compressed_stride;
  734. u32 width_b;
  735. u32 height_b;
  736. ubwcp_pixel_to_bytes(ubwcp, format, width, 0, &width_b, &height_b);
  737. if ((lin_stride < width_b) || (lin_stride > MAX_ATTR_STRIDE)) {
  738. ERR("Invalid stride: %u width: %u width_b: %u", lin_stride, width, width_b);
  739. return false;
  740. }
  741. if (format == TP10) {
  742. if(!IS_ALIGNED(lin_stride, 64)) {
  743. ERR("stride must be aligned to 64: %d", lin_stride);
  744. return false;
  745. }
  746. } else {
  747. compressed_stride = get_compressed_stride(ubwcp, format, width);
  748. if (lin_stride != compressed_stride) {
  749. ERR("linear stride: %d must be same as compressed stride: %d",
  750. lin_stride, compressed_stride);
  751. return false;
  752. }
  753. }
  754. return true;
  755. }
  756. static bool ioctl_format_is_valid(u16 ioctl_image_format)
  757. {
  758. switch (ioctl_image_format) {
  759. case UBWCP_LINEAR:
  760. case UBWCP_RGBA8888:
  761. case UBWCP_NV12:
  762. case UBWCP_NV12_Y:
  763. case UBWCP_NV12_UV:
  764. case UBWCP_NV124R:
  765. case UBWCP_NV124R_Y:
  766. case UBWCP_NV124R_UV:
  767. case UBWCP_TP10:
  768. case UBWCP_TP10_Y:
  769. case UBWCP_TP10_UV:
  770. case UBWCP_P010:
  771. case UBWCP_P010_Y:
  772. case UBWCP_P010_UV:
  773. case UBWCP_P016:
  774. case UBWCP_P016_Y:
  775. case UBWCP_P016_UV:
  776. return true;
  777. default:
  778. return false;
  779. }
  780. }
  781. /* validate buffer attributes */
  782. static bool ubwcp_buf_attrs_valid(struct ubwcp_driver *ubwcp, struct ubwcp_buffer_attrs *attr)
  783. {
  784. enum ubwcp_std_image_format format;
  785. if (attr->unused1 || attr->unused2 || attr->unused3 || attr->unused4 || attr->unused5 ||
  786. attr->unused6 || attr->unused7 || attr->unused8 || attr->unused9) {
  787. ERR("buf attr unused values must be set to 0");
  788. goto err;
  789. }
  790. if (!attr->width || !attr->height || !attr->stride || !attr->scanlines) {
  791. ERR("width/height/stride/scanlines cannot be 0");
  792. goto err;
  793. }
  794. if (!ioctl_format_is_valid(attr->image_format)) {
  795. ERR("invalid image format: %d", attr->image_format);
  796. goto err;
  797. }
  798. /* rest of the fields are ignored for linear format */
  799. if (attr->image_format == UBWCP_LINEAR) {
  800. goto valid;
  801. }
  802. if (to_std_format(attr->image_format, &format))
  803. goto err;
  804. if (attr->major_ubwc_ver || attr->minor_ubwc_ver) {
  805. ERR("major/minor ubwc ver must be 0. major: %d minor: %d",
  806. attr->major_ubwc_ver, attr->minor_ubwc_ver);
  807. goto err;
  808. }
  809. if (attr->compression_type != UBWCP_COMPRESSION_LOSSLESS) {
  810. ERR("compression_type is not valid: %d",
  811. attr->compression_type);
  812. goto err;
  813. }
  814. if (attr->lossy_params != 0) {
  815. ERR("lossy_params is not valid: %d", attr->lossy_params);
  816. goto err;
  817. }
  818. if (attr->width > MAX_ATTR_WIDTH) {
  819. ERR("width is invalid (above upper limit): %d", attr->width);
  820. goto err;
  821. }
  822. if (attr->height > MAX_ATTR_HEIGHT) {
  823. ERR("height is invalid (above upper limit): %d", attr->height);
  824. goto err;
  825. }
  826. if(!stride_is_valid(ubwcp, format, attr->width, attr->stride)) {
  827. ERR("stride is invalid: %d", attr->stride);
  828. goto err;
  829. }
  830. if ((attr->scanlines < attr->height) ||
  831. (attr->scanlines > attr->height + MAX_ATTR_SCANLN_HT_DELTA)) {
  832. ERR("scanlines is not valid - height: %d scanlines: %d",
  833. attr->height, attr->scanlines);
  834. goto err;
  835. }
  836. if (attr->planar_padding > MAX_ATTR_PLANAR_PAD) {
  837. ERR("planar_padding is not valid: %d", attr->planar_padding);
  838. goto err;
  839. }
  840. if (attr->subsample != UBWCP_SUBSAMPLE_4_2_0) {
  841. ERR("subsample is not valid: %d", attr->subsample);
  842. goto err;
  843. }
  844. if (attr->sub_system_target & ~UBWCP_SUBSYSTEM_TARGET_CPU) {
  845. ERR("sub_system_target other that CPU is not supported: %d",
  846. attr->sub_system_target);
  847. goto err;
  848. }
  849. if (!(attr->sub_system_target & UBWCP_SUBSYSTEM_TARGET_CPU)) {
  850. ERR("sub_system_target is not set to CPU: %d",
  851. attr->sub_system_target);
  852. goto err;
  853. }
  854. if (attr->y_offset != 0) {
  855. ERR("y_offset is not valid: %d", attr->y_offset);
  856. goto err;
  857. }
  858. if (attr->batch_size != 1) {
  859. ERR("batch_size is not valid: %d", attr->batch_size);
  860. goto err;
  861. }
  862. valid:
  863. dump_attributes(attr);
  864. return true;
  865. err:
  866. dump_attributes(attr);
  867. return false;
  868. }
  869. /* calculate and return metadata buffer size for a given plane
  870. * and buffer attributes
  871. */
  872. static int metadata_buf_sz(struct ubwcp_driver *ubwcp,
  873. enum ubwcp_std_image_format format,
  874. u32 width, u32 height, u8 plane, size_t *size)
  875. {
  876. u64 pitch;
  877. u64 lines;
  878. u64 tile_width;
  879. u32 tile_height;
  880. struct ubwcp_image_format_info f_info;
  881. struct ubwcp_plane_info p_info;
  882. f_info = ubwcp->format_info[format];
  883. DBG_BUF_ATTR("");
  884. DBG_BUF_ATTR("");
  885. DBG_BUF_ATTR("Calculating metadata buffer size: format = %d, plane = %d", format, plane);
  886. if (plane >= f_info.planes) {
  887. ERR("Missing plane info: format: %d, plane: %d", format, plane);
  888. return -1;
  889. }
  890. p_info = f_info.p_info[plane];
  891. /* UV plane */
  892. if (plane == 1) {
  893. width = width/2;
  894. height = height/2;
  895. }
  896. tile_width = p_info.tilesize_p.width;
  897. tile_height = p_info.tilesize_p.height;
  898. /* pitch: # of tiles in a row
  899. * lines: # of tile rows
  900. */
  901. pitch = UBWCP_ALIGN((width + tile_width - 1)/tile_width, META_DATA_PITCH_ALIGN);
  902. lines = UBWCP_ALIGN((height + tile_height - 1)/tile_height, META_DATA_HEIGHT_ALIGN);
  903. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  904. DBG_BUF_ATTR("tile params : %d x %d (pixels)", tile_width, tile_height);
  905. DBG_BUF_ATTR("pitch : %d (%d)", pitch, width/tile_width);
  906. DBG_BUF_ATTR("lines : %d (%d)", lines, height);
  907. DBG_BUF_ATTR("size (p*l*bytes) : %d", pitch*lines*1);
  908. /* x1 below is only to clarify that we are multiplying by 1 bytes/tile */
  909. *size = UBWCP_ALIGN(pitch*lines*1, META_DATA_SIZE_ALIGN);
  910. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", *size, *size);
  911. return 0;
  912. }
  913. /* calculate and return size of pixel data buffer for a given plane
  914. * and buffer attributes
  915. */
  916. static int pixeldata_buf_sz(struct ubwcp_driver *ubwcp,
  917. u16 format, u32 width,
  918. u32 height, u8 plane, size_t *size)
  919. {
  920. u64 pitch;
  921. u64 lines;
  922. u16 pixel_bytes;
  923. u16 per_pixel;
  924. u64 macro_tile_width_p;
  925. u64 macro_tile_height_p;
  926. struct ubwcp_image_format_info f_info;
  927. struct ubwcp_plane_info p_info;
  928. f_info = ubwcp->format_info[format];
  929. DBG_BUF_ATTR("");
  930. DBG_BUF_ATTR("");
  931. DBG_BUF_ATTR("Calculating Pixeldata buffer size: format = %d, plane = %d", format, plane);
  932. if (plane >= f_info.planes) {
  933. ERR("Missing plane info: format: %d, plane: %d", format, plane);
  934. return -1;
  935. }
  936. p_info = f_info.p_info[plane];
  937. pixel_bytes = p_info.pixel_bytes;
  938. per_pixel = p_info.per_pixel;
  939. /* UV plane */
  940. if (plane == 1) {
  941. width = width/2;
  942. height = height/2;
  943. }
  944. macro_tile_width_p = p_info.macrotilesize_p.width;
  945. macro_tile_height_p = p_info.macrotilesize_p.height;
  946. /* align pixel width and height macro tile width and height */
  947. pitch = UBWCP_ALIGN(width, macro_tile_width_p);
  948. lines = UBWCP_ALIGN(height, macro_tile_height_p);
  949. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  950. DBG_BUF_ATTR("macro tile params: %d x %d (pixels)", macro_tile_width_p,
  951. macro_tile_height_p);
  952. DBG_BUF_ATTR("bytes_per_pixel : %d/%d", pixel_bytes, per_pixel);
  953. DBG_BUF_ATTR("pitch : %d", pitch);
  954. DBG_BUF_ATTR("lines : %d", lines);
  955. DBG_BUF_ATTR("size (p*l*bytes) : %d", (pitch*lines*pixel_bytes)/per_pixel);
  956. *size = UBWCP_ALIGN((pitch*lines*pixel_bytes)/per_pixel, PIXEL_DATA_SIZE_ALIGN);
  957. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", *size, *size);
  958. return 0;
  959. }
  960. static int get_tile_height(struct ubwcp_driver *ubwcp, enum ubwcp_std_image_format format,
  961. u8 plane)
  962. {
  963. struct ubwcp_image_format_info f_info;
  964. struct ubwcp_plane_info p_info;
  965. f_info = ubwcp->format_info[format];
  966. p_info = f_info.p_info[plane];
  967. return p_info.tilesize_p.height;
  968. }
  969. /*
  970. * plane: must be 0 or 1 (1st plane == 0, 2nd plane == 1)
  971. */
  972. static size_t ubwcp_ula_size(struct ubwcp_driver *ubwcp, u16 format,
  973. u32 stride_b, u32 scanlines, u8 plane,
  974. bool add_tile_pad)
  975. {
  976. size_t size;
  977. DBG_BUF_ATTR("%s(format = %d, plane = %d)", __func__, format, plane);
  978. /* UV plane */
  979. if (plane == 1)
  980. scanlines = scanlines/2;
  981. if (add_tile_pad) {
  982. int tile_height = get_tile_height(ubwcp, format, plane);
  983. /* Align plane size to plane tile height */
  984. scanlines = ((scanlines + tile_height - 1) / tile_height) * tile_height;
  985. }
  986. size = stride_b*scanlines;
  987. DBG_BUF_ATTR("Size of plane-%u: (%u * %u) = %zu (0x%zx)",
  988. plane, stride_b, scanlines, size, size);
  989. return size;
  990. }
  991. static int missing_plane_from_format(u16 ioctl_image_format)
  992. {
  993. int missing_plane;
  994. switch (ioctl_image_format) {
  995. case UBWCP_NV12_Y:
  996. missing_plane = 2;
  997. break;
  998. case UBWCP_NV12_UV:
  999. missing_plane = 1;
  1000. break;
  1001. case UBWCP_NV124R_Y:
  1002. missing_plane = 2;
  1003. break;
  1004. case UBWCP_NV124R_UV:
  1005. missing_plane = 1;
  1006. break;
  1007. case UBWCP_TP10_Y:
  1008. missing_plane = 2;
  1009. break;
  1010. case UBWCP_TP10_UV:
  1011. missing_plane = 1;
  1012. break;
  1013. case UBWCP_P010_Y:
  1014. missing_plane = 2;
  1015. break;
  1016. case UBWCP_P010_UV:
  1017. missing_plane = 1;
  1018. break;
  1019. case UBWCP_P016_Y:
  1020. missing_plane = 2;
  1021. break;
  1022. case UBWCP_P016_UV:
  1023. missing_plane = 1;
  1024. break;
  1025. default:
  1026. missing_plane = 0;
  1027. }
  1028. return missing_plane;
  1029. }
  1030. static int planes_in_format(enum ubwcp_std_image_format format)
  1031. {
  1032. if (format == RGBA)
  1033. return 1;
  1034. else
  1035. return 2;
  1036. }
  1037. static int ubwcp_validate_uv_align(struct ubwcp_driver *ubwcp,
  1038. struct ubwcp_buffer_attrs *attr,
  1039. size_t ula_y_plane_size,
  1040. size_t uv_start_offset)
  1041. {
  1042. int ret = 0;
  1043. size_t ula_y_plane_size_align;
  1044. size_t y_tile_align_bytes;
  1045. int y_tile_height;
  1046. int planes;
  1047. enum ubwcp_std_image_format format;
  1048. ret = to_std_format(attr->image_format, &format);
  1049. if (ret)
  1050. goto err;
  1051. /* Only validate UV align if there is both a Y and UV plane */
  1052. planes = planes_in_format(format);
  1053. if (planes != 2)
  1054. return 0;
  1055. /* Check it is cache line size aligned */
  1056. if ((uv_start_offset % 64) != 0) {
  1057. ret = -EINVAL;
  1058. ERR("uv_start_offset %zu not cache line aligned",
  1059. uv_start_offset);
  1060. goto err;
  1061. }
  1062. /*
  1063. * Check that UV plane does not overlap with any of the Y plane’s tiles
  1064. */
  1065. y_tile_height = get_tile_height(ubwcp, format, 0);
  1066. y_tile_align_bytes = y_tile_height * attr->stride;
  1067. ula_y_plane_size_align = ((ula_y_plane_size + y_tile_align_bytes - 1) /
  1068. y_tile_align_bytes) * y_tile_align_bytes;
  1069. if (uv_start_offset < ula_y_plane_size_align) {
  1070. ret = -EINVAL;
  1071. ERR("uv offset %zu less than y plane align %zu for y plane size %zu",
  1072. uv_start_offset, ula_y_plane_size_align,
  1073. ula_y_plane_size);
  1074. goto err;
  1075. }
  1076. return 0;
  1077. err:
  1078. return ret;
  1079. }
  1080. /* calculate ULA buffer parms */
  1081. static int ubwcp_calc_ula_params(struct ubwcp_driver *ubwcp,
  1082. struct ubwcp_buffer_attrs *attr,
  1083. size_t *ula_size,
  1084. size_t *ula_y_plane_size,
  1085. size_t *uv_start_offset)
  1086. {
  1087. size_t size;
  1088. enum ubwcp_std_image_format format;
  1089. int planes;
  1090. int missing_plane;
  1091. u32 stride;
  1092. u32 scanlines;
  1093. u32 planar_padding;
  1094. int ret;
  1095. ret = to_std_format(attr->image_format, &format);
  1096. if (ret)
  1097. return ret;
  1098. stride = attr->stride;
  1099. scanlines = attr->scanlines;
  1100. planar_padding = attr->planar_padding;
  1101. /* Number of "expected" planes in "the standard defined" image format */
  1102. planes = planes_in_format(format);
  1103. missing_plane = missing_plane_from_format(attr->image_format);
  1104. DBG_BUF_ATTR("ula params -->");
  1105. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1106. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1107. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1108. DBG_BUF_ATTR("Planar Padding : %d", planar_padding);
  1109. if (planes == 1) {
  1110. /* uv_start beyond ULA range */
  1111. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1112. *uv_start_offset = size;
  1113. *ula_y_plane_size = size;
  1114. } else {
  1115. if (!missing_plane) {
  1116. /* size for both planes and padding */
  1117. /* Don't pad out Y plane as client would not expect this padding */
  1118. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, false);
  1119. *ula_y_plane_size = size;
  1120. size += planar_padding;
  1121. *uv_start_offset = size;
  1122. size += ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1123. } else {
  1124. if (missing_plane == 2) {
  1125. /* Y-only image, set uv_start beyond ULA range */
  1126. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1127. *uv_start_offset = size;
  1128. *ula_y_plane_size = size;
  1129. } else {
  1130. /* first plane data is not there */
  1131. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1132. *uv_start_offset = 0; /* uv data is at the beginning */
  1133. *ula_y_plane_size = 0;
  1134. }
  1135. }
  1136. }
  1137. *ula_size = UBWCP_ALIGN(size, 4096);
  1138. DBG_BUF_ATTR("ULA_Size: %zu (0x%x) (before 4K align: %zu)", *ula_size, *ula_size, size);
  1139. return 0;
  1140. }
  1141. /* calculate UBWCP buffer parms */
  1142. static int ubwcp_calc_ubwcp_buf_params(struct ubwcp_driver *ubwcp,
  1143. struct ubwcp_buffer_attrs *attr,
  1144. size_t *md_p0, size_t *pd_p0,
  1145. size_t *md_p1, size_t *pd_p1,
  1146. size_t *stride_tp10_b)
  1147. {
  1148. int planes;
  1149. int missing_plane;
  1150. enum ubwcp_std_image_format format;
  1151. size_t stride_tp10_p;
  1152. int ret;
  1153. ret = to_std_format(attr->image_format, &format);
  1154. if (ret)
  1155. return ret;
  1156. missing_plane = missing_plane_from_format(attr->image_format);
  1157. planes = planes_in_format(format);
  1158. DBG_BUF_ATTR("ubwcp params -->");
  1159. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1160. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1161. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1162. *md_p0 = 0;
  1163. *pd_p0 = 0;
  1164. *md_p1 = 0;
  1165. *pd_p1 = 0;
  1166. *stride_tp10_b = 0;
  1167. if (missing_plane != 1) {
  1168. if (metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0, md_p0))
  1169. return -1;
  1170. if (pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0, pd_p0))
  1171. return -1;
  1172. }
  1173. if ((planes == 2) && (missing_plane != 2)){
  1174. if (metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1, md_p1))
  1175. return -1;
  1176. if (pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1, pd_p1))
  1177. return -1;
  1178. }
  1179. if (format == TP10) {
  1180. stride_tp10_p = UBWCP_ALIGN(attr->width, 192);
  1181. *stride_tp10_b = (stride_tp10_p/3) + stride_tp10_p;
  1182. }
  1183. return 0;
  1184. }
  1185. /* reserve ULA address space of the given size */
  1186. static phys_addr_t ubwcp_ula_alloc(struct ubwcp_driver *ubwcp, size_t size)
  1187. {
  1188. phys_addr_t pa;
  1189. mutex_lock(&ubwcp->ula_lock);
  1190. pa = gen_pool_alloc(ubwcp->ula_pool, size);
  1191. mutex_unlock(&ubwcp->ula_lock);
  1192. return pa;
  1193. }
  1194. /* free ULA address space of the given address and size */
  1195. static void ubwcp_ula_free(struct ubwcp_driver *ubwcp, phys_addr_t pa, size_t size)
  1196. {
  1197. mutex_lock(&ubwcp->ula_lock);
  1198. if (!gen_pool_has_addr(ubwcp->ula_pool, pa, size)) {
  1199. ERR("Attempt to free mem not from gen_pool: pa: %p, size: %zx", pa, size);
  1200. goto err;
  1201. }
  1202. DBG("addr: %p, size: %zx", pa, size);
  1203. gen_pool_free(ubwcp->ula_pool, pa, size);
  1204. mutex_unlock(&ubwcp->ula_lock);
  1205. return;
  1206. err:
  1207. mutex_unlock(&ubwcp->ula_lock);
  1208. }
  1209. /* free up or expand current_pa and return the new pa */
  1210. static phys_addr_t ubwcp_ula_realloc(struct ubwcp_driver *ubwcp,
  1211. phys_addr_t pa,
  1212. size_t size,
  1213. size_t new_size)
  1214. {
  1215. if (size == new_size)
  1216. return pa;
  1217. if (pa)
  1218. ubwcp_ula_free(ubwcp, pa, size);
  1219. return ubwcp_ula_alloc(ubwcp, new_size);
  1220. }
  1221. /* unmap dma buf */
  1222. static void ubwcp_dma_unmap(struct ubwcp_buf *buf)
  1223. {
  1224. if (buf->dma_buf && buf->attachment) {
  1225. DBG("Calling dma_buf_unmap_attachment()");
  1226. dma_buf_unmap_attachment(buf->attachment, buf->sgt, DMA_BIDIRECTIONAL);
  1227. buf->sgt = NULL;
  1228. dma_buf_detach(buf->dma_buf, buf->attachment);
  1229. buf->attachment = NULL;
  1230. }
  1231. }
  1232. static bool verify_dma_buf_size(struct ubwcp_buf *buf, size_t min_size)
  1233. {
  1234. size_t dma_len;
  1235. dma_len = sg_dma_len(buf->sgt->sgl);
  1236. if (dma_len < min_size) {
  1237. ERR("dma len: %zu is less than min ubwcp buffer size: %zu", dma_len, min_size);
  1238. return false;
  1239. } else
  1240. return true;
  1241. }
  1242. /* dma map ubwcp buffer */
  1243. static int ubwcp_dma_map(struct ubwcp_buf *buf,
  1244. struct device *dev,
  1245. dma_addr_t *iova)
  1246. {
  1247. int ret = 0;
  1248. struct dma_buf *dma_buf = buf->dma_buf;
  1249. struct dma_buf_attachment *attachment;
  1250. struct sg_table *sgt;
  1251. /* Map buffer to SMMU and get IOVA */
  1252. attachment = dma_buf_attach(dma_buf, dev);
  1253. if (IS_ERR(attachment)) {
  1254. ret = PTR_ERR(attachment);
  1255. ERR("dma_buf_attach() failed: %d", ret);
  1256. goto err;
  1257. }
  1258. dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
  1259. dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64));
  1260. sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL);
  1261. if (IS_ERR_OR_NULL(sgt)) {
  1262. ret = PTR_ERR(sgt);
  1263. ERR("dma_buf_map_attachment() failed: %d", ret);
  1264. goto err_detach;
  1265. }
  1266. if (sgt->nents != 1) {
  1267. ERR("nents = %d", sgt->nents);
  1268. goto err_unmap;
  1269. }
  1270. *iova = sg_dma_address(sgt->sgl);
  1271. buf->attachment = attachment;
  1272. buf->sgt = sgt;
  1273. return ret;
  1274. err_unmap:
  1275. dma_buf_unmap_attachment(attachment, sgt, DMA_BIDIRECTIONAL);
  1276. err_detach:
  1277. dma_buf_detach(dma_buf, attachment);
  1278. err:
  1279. if (!ret)
  1280. ret = -1;
  1281. return ret;
  1282. }
  1283. static void reset_buf_attrs(struct ubwcp_buf *buf)
  1284. {
  1285. struct ubwcp_hw_meta_metadata *mmdata;
  1286. struct ubwcp_driver *ubwcp;
  1287. ubwcp = buf->ubwcp;
  1288. mmdata = &buf->mmdata;
  1289. ubwcp_dma_unmap(buf);
  1290. /* reset ula params */
  1291. if (buf->ula_size) {
  1292. ubwcp_ula_free(ubwcp, buf->ula_pa, buf->ula_size);
  1293. buf->ula_size = 0;
  1294. buf->ula_pa = 0;
  1295. }
  1296. /* reset ubwcp params */
  1297. memset(mmdata, 0, sizeof(*mmdata));
  1298. buf->buf_attr_set = false;
  1299. buf->buf_attr.image_format = UBWCP_LINEAR;
  1300. }
  1301. static void print_mmdata_desc(struct ubwcp_hw_meta_metadata *mmdata)
  1302. {
  1303. DBG_BUF_ATTR("");
  1304. DBG_BUF_ATTR("--------MM_DATA DESC ---------");
  1305. DBG_BUF_ATTR("uv_start_addr : 0x%08llx (cache addr) (actual: 0x%llx)",
  1306. mmdata->uv_start_addr, mmdata->uv_start_addr << 6);
  1307. DBG_BUF_ATTR("format : 0x%08x", mmdata->format);
  1308. DBG_BUF_ATTR("stride : 0x%08x (cache addr) (actual: 0x%x)",
  1309. mmdata->stride, mmdata->stride << 6);
  1310. DBG_BUF_ATTR("stride_ubwcp : 0x%08x (cache addr) (actual: 0x%zx)",
  1311. mmdata->stride_ubwcp, mmdata->stride_ubwcp << 6);
  1312. DBG_BUF_ATTR("metadata_base_y : 0x%08x (page addr) (actual: 0x%llx)",
  1313. mmdata->metadata_base_y, mmdata->metadata_base_y << 12);
  1314. DBG_BUF_ATTR("metadata_base_uv: 0x%08x (page addr) (actual: 0x%zx)",
  1315. mmdata->metadata_base_uv, mmdata->metadata_base_uv << 12);
  1316. DBG_BUF_ATTR("buffer_y_offset : 0x%08x (page addr) (actual: 0x%zx)",
  1317. mmdata->buffer_y_offset, mmdata->buffer_y_offset << 12);
  1318. DBG_BUF_ATTR("buffer_uv_offset: 0x%08x (page addr) (actual: 0x%zx)",
  1319. mmdata->buffer_uv_offset, mmdata->buffer_uv_offset << 12);
  1320. DBG_BUF_ATTR("width_height : 0x%08x (width: 0x%x height: 0x%x)",
  1321. mmdata->width_height, mmdata->width_height >> 16, mmdata->width_height & 0xFFFF);
  1322. DBG_BUF_ATTR("");
  1323. }
  1324. /* set buffer attributes:
  1325. * Failure:
  1326. * This call may fail for multiple reasons and it will leave the buffer in an undefined state.
  1327. * In some situations it may leave the buffer in linear mapped state, and in other situations it
  1328. * may leave the buffer in previously set attributes state.
  1329. */
  1330. int ubwcp_set_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1331. {
  1332. int ret = 0;
  1333. size_t ula_size = 0;
  1334. size_t uv_start_offset = 0;
  1335. size_t ula_y_plane_size = 0;
  1336. phys_addr_t ula_pa = 0x0;
  1337. struct ubwcp_buf *buf;
  1338. struct ubwcp_driver *ubwcp;
  1339. size_t metadata_p0;
  1340. size_t pixeldata_p0;
  1341. size_t metadata_p1;
  1342. size_t pixeldata_p1;
  1343. size_t iova_min_size;
  1344. size_t stride_tp10_b;
  1345. dma_addr_t iova_base;
  1346. struct ubwcp_hw_meta_metadata *mmdata;
  1347. u64 uv_start;
  1348. u32 stride_b;
  1349. u32 width_b;
  1350. u32 height_b;
  1351. enum ubwcp_std_image_format std_image_format;
  1352. bool is_non_lin_buf;
  1353. u16 hw_img_format;
  1354. trace_ubwcp_set_buf_attrs_start(dmabuf);
  1355. if (!dmabuf) {
  1356. ERR("NULL dmabuf input ptr");
  1357. ret = -EINVAL;
  1358. goto err_validation;
  1359. }
  1360. if (!attr) {
  1361. ERR("NULL attr ptr");
  1362. ret = -EINVAL;
  1363. goto err_validation;
  1364. }
  1365. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1366. if (!buf) {
  1367. ERR("No corresponding ubwcp_buf for the passed in dma_buf");
  1368. ret = -EINVAL;
  1369. goto err_validation;
  1370. }
  1371. ubwcp = buf->ubwcp;
  1372. if (ubwcp->state != UBWCP_STATE_READY) {
  1373. ret = EPERM;
  1374. goto err_validation;
  1375. }
  1376. if (!ubwcp_buf_attrs_valid(ubwcp, attr)) {
  1377. ERR("Invalid buf attrs");
  1378. ret = -EINVAL;
  1379. goto err_validation;
  1380. }
  1381. mutex_lock(&buf->lock);
  1382. if (buf->lock_count) {
  1383. ERR("Cannot set attr when buffer is locked");
  1384. ret = -EBUSY;
  1385. goto unlock;
  1386. }
  1387. mmdata = &buf->mmdata;
  1388. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1389. /* note: this also checks if buf is mmap'ed */
  1390. ret = ubwcp->mmap_config_fptr(buf->dma_buf, true, 0, 0);
  1391. if (ret) {
  1392. ERR("dma_buf_mmap_config(0,0) failed: %d", ret);
  1393. goto unlock;
  1394. }
  1395. if (attr->image_format == UBWCP_LINEAR) {
  1396. DBG_BUF_ATTR("Linear format requested");
  1397. if (buf->buf_attr_set)
  1398. reset_buf_attrs(buf);
  1399. if (is_non_lin_buf) {
  1400. /*
  1401. * Changing buffer from ubwc to linear so decrement
  1402. * number of ubwc buffers
  1403. */
  1404. ret = dec_num_non_lin_buffers(ubwcp);
  1405. }
  1406. mutex_unlock(&buf->lock);
  1407. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1408. return ret;
  1409. }
  1410. if (to_std_format(attr->image_format, &std_image_format)) {
  1411. ERR("Unable to map ioctl image format to std image format");
  1412. goto unlock;
  1413. }
  1414. if (std_to_hw_img_fmt(std_image_format, &hw_img_format)) {
  1415. ERR("Unable to map std image format to hw image format");
  1416. goto unlock;
  1417. }
  1418. /* Calculate uncompressed-buffer size. */
  1419. ret = ubwcp_calc_ula_params(ubwcp, attr, &ula_size, &ula_y_plane_size, &uv_start_offset);
  1420. if (ret) {
  1421. ERR("ubwcp_calc_ula_params() failed: %d", ret);
  1422. goto unlock;
  1423. }
  1424. ret = ubwcp_validate_uv_align(ubwcp, attr, ula_y_plane_size, uv_start_offset);
  1425. if (ret) {
  1426. ERR("ubwcp_validate_uv_align() failed: %d", ret);
  1427. goto unlock;
  1428. }
  1429. ret = ubwcp_calc_ubwcp_buf_params(ubwcp, attr, &metadata_p0, &pixeldata_p0, &metadata_p1,
  1430. &pixeldata_p1, &stride_tp10_b);
  1431. if (ret) {
  1432. ERR("ubwcp_calc_buf_params() failed: %d", ret);
  1433. goto unlock;
  1434. }
  1435. iova_min_size = metadata_p0 + pixeldata_p0 + metadata_p1 + pixeldata_p1;
  1436. DBG_BUF_ATTR("");
  1437. DBG_BUF_ATTR("");
  1438. DBG_BUF_ATTR("------Summary ULA Calculated Params ------");
  1439. DBG_BUF_ATTR("ULA Size : %8zu (0x%8zx)", ula_size, ula_size);
  1440. DBG_BUF_ATTR("UV Start Offset : %8zu (0x%8zx)", uv_start_offset, uv_start_offset);
  1441. DBG_BUF_ATTR("------Summary UBCP Calculated Params ------");
  1442. DBG_BUF_ATTR("metadata_p0 : %8d (0x%8zx)", metadata_p0, metadata_p0);
  1443. DBG_BUF_ATTR("pixeldata_p0 : %8d (0x%8zx)", pixeldata_p0, pixeldata_p0);
  1444. DBG_BUF_ATTR("metadata_p1 : %8d (0x%8zx)", metadata_p1, metadata_p1);
  1445. DBG_BUF_ATTR("pixeldata_p1 : %8d (0x%8zx)", pixeldata_p1, pixeldata_p1);
  1446. DBG_BUF_ATTR("stride_tp10 : %8d (0x%8zx)", stride_tp10_b, stride_tp10_b);
  1447. DBG_BUF_ATTR("iova_min_size : %8d (0x%8zx)", iova_min_size, iova_min_size);
  1448. DBG_BUF_ATTR("");
  1449. if (!ula_size) {
  1450. ERR("Invalid ula_size (0)");
  1451. goto unlock;
  1452. }
  1453. /* assign ULA PA with uncompressed-size range */
  1454. ula_pa = ubwcp_ula_realloc(ubwcp, buf->ula_pa, buf->ula_size, ula_size);
  1455. if (!ula_pa) {
  1456. ERR("ubwcp_ula_alloc/realloc() failed. running out of ULA PA space?");
  1457. goto err;
  1458. }
  1459. buf->ula_size = ula_size;
  1460. buf->ula_pa = ula_pa;
  1461. DBG_BUF_ATTR("Allocated ULA_PA: 0x%p of size: 0x%zx", ula_pa, ula_size);
  1462. DBG_BUF_ATTR("");
  1463. /* dma map only the first time attribute is set */
  1464. if (!buf->buf_attr_set) {
  1465. /* linear -> ubwcp. map ubwcp buffer */
  1466. ret = ubwcp_dma_map(buf, ubwcp->dev_buf_cb, &iova_base);
  1467. if (ret) {
  1468. ERR("ubwcp_dma_map() failed: %d", ret);
  1469. goto err;
  1470. }
  1471. DBG_BUF_ATTR("dma_buf IOVA range: 0x%llx + min_size (0x%zx): 0x%llx",
  1472. iova_base, iova_min_size, iova_base + iova_min_size);
  1473. }
  1474. if(!verify_dma_buf_size(buf, iova_min_size))
  1475. goto err;
  1476. uv_start = ula_pa + uv_start_offset;
  1477. if (!IS_ALIGNED(uv_start, 64)) {
  1478. ERR("ERROR: uv_start is NOT aligned to cache line");
  1479. goto err;
  1480. }
  1481. /* Convert height and width to bytes for writing to mmdata */
  1482. if (std_image_format != TP10) {
  1483. ubwcp_pixel_to_bytes(ubwcp, std_image_format, attr->width,
  1484. attr->height, &width_b, &height_b);
  1485. } else {
  1486. /* for tp10 image compression, we need to program p010 width/height */
  1487. ubwcp_pixel_to_bytes(ubwcp, P010, attr->width,
  1488. attr->height, &width_b, &height_b);
  1489. }
  1490. stride_b = attr->stride;
  1491. /* create the mmdata descriptor */
  1492. memset(mmdata, 0, sizeof(*mmdata));
  1493. mmdata->uv_start_addr = CACHE_ADDR(uv_start);
  1494. mmdata->format = hw_img_format;
  1495. if (std_image_format != TP10) {
  1496. mmdata->stride = CACHE_ADDR(stride_b); /* uncompressed stride */
  1497. } else {
  1498. mmdata->stride = CACHE_ADDR(stride_tp10_b); /* compressed stride */
  1499. mmdata->stride_ubwcp = CACHE_ADDR(stride_b); /* uncompressed stride */
  1500. }
  1501. mmdata->metadata_base_y = PAGE_ADDR(iova_base);
  1502. mmdata->metadata_base_uv = PAGE_ADDR(iova_base + metadata_p0 + pixeldata_p0);
  1503. mmdata->buffer_y_offset = PAGE_ADDR(metadata_p0);
  1504. mmdata->buffer_uv_offset = PAGE_ADDR(metadata_p1);
  1505. /* NOTE: For version 1.1, both width & height needs to be in bytes.
  1506. * For other versions, width in bytes & height in pixels.
  1507. */
  1508. if ((ubwcp->hw_ver_major == 1) && (ubwcp->hw_ver_minor == 1))
  1509. mmdata->width_height = width_b << 16 | height_b;
  1510. else
  1511. mmdata->width_height = width_b << 16 | attr->height;
  1512. print_mmdata_desc(mmdata);
  1513. if (!is_non_lin_buf) {
  1514. /*
  1515. * Changing buffer from linear to ubwc so increment
  1516. * number of ubwc buffers
  1517. */
  1518. ret = inc_num_non_lin_buffers(ubwcp);
  1519. }
  1520. if (ret) {
  1521. ERR("inc_num_non_lin_buffers failed: %d", ret);
  1522. goto err;
  1523. }
  1524. /* inform ULA-PA to dma-heap */
  1525. DBG_BUF_ATTR("Calling mmap_config(): ULA_PA: 0x%p size: 0x%zx", ula_pa, ula_size);
  1526. ret = ubwcp->mmap_config_fptr(buf->dma_buf, false, buf->ula_pa, buf->ula_size);
  1527. if (ret) {
  1528. ERR("dma_buf_mmap_config() failed: %d", ret);
  1529. if (!is_non_lin_buf)
  1530. dec_num_non_lin_buffers(ubwcp);
  1531. goto err;
  1532. }
  1533. buf->buf_attr = *attr;
  1534. buf->buf_attr_set = true;
  1535. mutex_unlock(&buf->lock);
  1536. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1537. return 0;
  1538. err:
  1539. reset_buf_attrs(buf);
  1540. if (is_non_lin_buf) {
  1541. /*
  1542. * Changing buffer from ubwc to linear so decrement
  1543. * number of ubwc buffers
  1544. */
  1545. dec_num_non_lin_buffers(ubwcp);
  1546. }
  1547. unlock:
  1548. mutex_unlock(&buf->lock);
  1549. err_validation:
  1550. if (!ret)
  1551. ret = -1;
  1552. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1553. return ret;
  1554. }
  1555. EXPORT_SYMBOL(ubwcp_set_buf_attrs);
  1556. /* Free up the buffer descriptor */
  1557. static void ubwcp_buf_desc_free(struct ubwcp_driver *ubwcp, struct ubwcp_desc *desc)
  1558. {
  1559. int idx = desc->idx;
  1560. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1561. mutex_lock(&ubwcp->desc_lock);
  1562. desc_list[idx].idx = -1;
  1563. desc_list[idx].ptr = NULL;
  1564. DBG("freed descriptor_id: %d", idx);
  1565. mutex_unlock(&ubwcp->desc_lock);
  1566. }
  1567. /* Allocate next available buffer descriptor. */
  1568. static struct ubwcp_desc *ubwcp_buf_desc_allocate(struct ubwcp_driver *ubwcp)
  1569. {
  1570. int idx;
  1571. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1572. mutex_lock(&ubwcp->desc_lock);
  1573. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  1574. if (desc_list[idx].idx == -1) {
  1575. desc_list[idx].idx = idx;
  1576. desc_list[idx].ptr = ubwcp->buffer_desc_base +
  1577. idx*UBWCP_BUFFER_DESC_OFFSET;
  1578. DBG("allocated descriptor_id: %d", idx);
  1579. mutex_unlock(&ubwcp->desc_lock);
  1580. return &desc_list[idx];
  1581. }
  1582. }
  1583. mutex_unlock(&ubwcp->desc_lock);
  1584. return NULL;
  1585. }
  1586. static int ubwcp_flush(struct ubwcp_driver *ubwcp)
  1587. {
  1588. int ret = 0;
  1589. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1590. trace_ubwcp_hw_flush_start(0);
  1591. ret = ubwcp_hw_flush(ubwcp->base);
  1592. trace_ubwcp_hw_flush_end(0);
  1593. if (ret)
  1594. ERR("ubwcp_hw_flush() failed, ret = %d", ret);
  1595. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1596. return ret;
  1597. }
  1598. static int range_check_disable(struct ubwcp_driver *ubwcp, int idx)
  1599. {
  1600. int ret;
  1601. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1602. mutex_lock(&ubwcp->hw_range_ck_lock);
  1603. trace_ubwcp_hw_flush_start(0);
  1604. ret = ubwcp_hw_disable_range_check_with_flush(ubwcp->base, idx);
  1605. trace_ubwcp_hw_flush_end(0);
  1606. if (ret)
  1607. ERR("disable_range_check_with_flush() failed: %d", ret);
  1608. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1609. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1610. return ret;
  1611. }
  1612. static void range_check_enable(struct ubwcp_driver *ubwcp, int idx)
  1613. {
  1614. mutex_lock(&ubwcp->hw_range_ck_lock);
  1615. ubwcp_hw_enable_range_check(ubwcp->base, idx);
  1616. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1617. }
  1618. /**
  1619. * Lock buffer for CPU access. This prepares ubwcp hw to allow
  1620. * CPU access to the compressed buffer. It will perform
  1621. * necessary address translation configuration and cache maintenance ops
  1622. * so that CPU can safely access ubwcp buffer, if this call is
  1623. * successful.
  1624. * Allocate descriptor if not already,
  1625. * perform CMO and then enable range check
  1626. *
  1627. * @param dmabuf : ptr to the dma buf
  1628. * @param direction : direction of access
  1629. *
  1630. * @return int : 0 on success, otherwise error code
  1631. */
  1632. static int ubwcp_lock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1633. {
  1634. int ret = 0;
  1635. struct ubwcp_buf *buf;
  1636. struct ubwcp_driver *ubwcp;
  1637. trace_ubwcp_lock_start(dmabuf);
  1638. if (!dmabuf) {
  1639. ERR("NULL dmabuf input ptr");
  1640. trace_ubwcp_lock_end(dmabuf);
  1641. return -EINVAL;
  1642. }
  1643. if (!valid_dma_direction(dir)) {
  1644. ERR("invalid direction: %d", dir);
  1645. trace_ubwcp_lock_end(dmabuf);
  1646. return -EINVAL;
  1647. }
  1648. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1649. if (!buf) {
  1650. ERR("ubwcp_buf ptr not found");
  1651. trace_ubwcp_lock_end(dmabuf);
  1652. return -1;
  1653. }
  1654. ubwcp = buf->ubwcp;
  1655. if (ubwcp->state != UBWCP_STATE_READY) {
  1656. ERR("driver in invalid state: %d", ubwcp->state);
  1657. trace_ubwcp_lock_end(dmabuf);
  1658. return -EPERM;
  1659. }
  1660. mutex_lock(&buf->lock);
  1661. if (!buf->buf_attr_set) {
  1662. ERR("lock() called on buffer, but attr not set");
  1663. goto err;
  1664. }
  1665. if (buf->buf_attr.image_format == UBWCP_LINEAR) {
  1666. ERR("lock() called on linear buffer");
  1667. goto err;
  1668. }
  1669. if (!buf->lock_count) {
  1670. DBG("first lock on buffer");
  1671. /* buf->desc could already be allocated because of perm range xlation */
  1672. if (!buf->desc) {
  1673. /* allocate a buffer descriptor */
  1674. buf->desc = ubwcp_buf_desc_allocate(buf->ubwcp);
  1675. if (!buf->desc) {
  1676. ERR("ubwcp_allocate_buf_desc() failed");
  1677. goto err;
  1678. }
  1679. memcpy(buf->desc->ptr, &buf->mmdata, sizeof(buf->mmdata));
  1680. /* Flushing of updated mmdata:
  1681. * mmdata is iocoherent and ubwcp will get it from CPU cache -
  1682. * *as long as* it has not cached that itself during previous
  1683. * access to the same descriptor.
  1684. *
  1685. * During unlock of previous use of this descriptor,
  1686. * we do hw flush, which will get rid of this mmdata from
  1687. * ubwcp cache.
  1688. *
  1689. * In addition, we also do a hw flush after enable_range_ck().
  1690. * That will also get rid of any speculative fetch of mmdata
  1691. * by the ubwcp hw. At this time, the assumption is that ubwcp
  1692. * will cache mmdata only for active descriptor. But if ubwcp
  1693. * is speculatively fetching mmdata for all descriptors
  1694. * (irrespetive of enabled or not), the flush during lock
  1695. * will be necessary to make sure ubwcp sees updated mmdata
  1696. * that we just updated
  1697. */
  1698. /* program ULA range for this buffer */
  1699. DBG("setting range check: descriptor_id: %d, addr: %p, size: %zx",
  1700. buf->desc->idx, buf->ula_pa, buf->ula_size);
  1701. ubwcp_hw_set_range_check(ubwcp->base, buf->desc->idx, buf->ula_pa,
  1702. buf->ula_size);
  1703. }
  1704. /* enable range check */
  1705. DBG("enabling range check, descriptor_id: %d", buf->desc->idx);
  1706. range_check_enable(ubwcp, buf->desc->idx);
  1707. /* Flush/invalidate UBWCP caches */
  1708. /* Why: cpu could have done a speculative fetch before
  1709. * enable_range_ck() and ubwcp in process of returning "default" data
  1710. * we don't want that stashing of default data pending.
  1711. * we force completion of that and then we also cpu invalidate which
  1712. * will get rid of that line.
  1713. */
  1714. ret = ubwcp_flush(ubwcp);
  1715. if (ret) {
  1716. ubwcp->state = UBWCP_STATE_FAULT;
  1717. ERR("state set to fault");
  1718. goto err_flush_failed;
  1719. }
  1720. /* Only apply CMOs if there are potential CPU reads */
  1721. if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
  1722. trace_ubwcp_dma_sync_single_for_cpu_start(buf->ula_size, dir);
  1723. dma_sync_single_for_cpu(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1724. trace_ubwcp_dma_sync_single_for_cpu_end(buf->ula_size, dir);
  1725. }
  1726. buf->dma_dir = dir;
  1727. } else {
  1728. DBG("buf already locked");
  1729. /* For write locks, always upgrade direction to bi_directional.
  1730. * A previous read lock will now become write lock.
  1731. * This will ensure a flush when the last unlock comes in.
  1732. */
  1733. if (buf->dma_dir == DMA_TO_DEVICE &&
  1734. buf->dma_dir != dir) {
  1735. /*
  1736. * Locking for read would require doing a cache invalidation which
  1737. * we don't want to do while a client may be writing to the buffer
  1738. * as that could drop valid lines from the cache.
  1739. */
  1740. ret = -EINVAL;
  1741. ERR("no support for locking a write only buffer for read");
  1742. goto err;
  1743. } else if (buf->dma_dir != dir) {
  1744. buf->dma_dir = DMA_BIDIRECTIONAL;
  1745. }
  1746. }
  1747. buf->lock_count++;
  1748. DBG("new lock_count: %d", buf->lock_count);
  1749. mutex_unlock(&buf->lock);
  1750. trace_ubwcp_lock_end(dmabuf);
  1751. return ret;
  1752. err_flush_failed:
  1753. range_check_disable(ubwcp, buf->desc->idx);
  1754. ubwcp_buf_desc_free(ubwcp, buf->desc);
  1755. buf->desc = NULL;
  1756. err:
  1757. mutex_unlock(&buf->lock);
  1758. if (!ret)
  1759. ret = -1;
  1760. trace_ubwcp_lock_end(dmabuf);
  1761. return ret;
  1762. }
  1763. /* This can be called as a result of external unlock() call or
  1764. * internally if free() is called without unlock().
  1765. */
  1766. static int unlock_internal(struct ubwcp_buf *buf, enum dma_data_direction dir, bool free_buffer)
  1767. {
  1768. int ret = 0;
  1769. struct ubwcp_driver *ubwcp;
  1770. DBG("current lock_count: %d", buf->lock_count);
  1771. if (free_buffer) {
  1772. buf->lock_count = 0;
  1773. DBG("Forced lock_count: %d", buf->lock_count);
  1774. } else {
  1775. /* for write unlocks, remember the direction so we flush on last unlock */
  1776. if (buf->dma_dir != dir)
  1777. buf->dma_dir = DMA_BIDIRECTIONAL;
  1778. buf->lock_count--;
  1779. DBG("new lock_count: %d", buf->lock_count);
  1780. if (buf->lock_count) {
  1781. DBG("more than 1 lock on buffer. waiting until last unlock");
  1782. return 0;
  1783. }
  1784. }
  1785. ubwcp = buf->ubwcp;
  1786. /* Only apply CMOs if there were potential CPU writes */
  1787. if (buf->dma_dir == DMA_TO_DEVICE || buf->dma_dir == DMA_BIDIRECTIONAL) {
  1788. /* Flush/invalidate ULA PA from CPU caches */
  1789. trace_ubwcp_dma_sync_single_for_device_start(buf->ula_size, buf->dma_dir);
  1790. dma_sync_single_for_device(ubwcp->dev, buf->ula_pa, buf->ula_size, buf->dma_dir);
  1791. trace_ubwcp_dma_sync_single_for_device_end(buf->ula_size, buf->dma_dir);
  1792. }
  1793. /* disable range check */
  1794. DBG("disabling range check");
  1795. ret = range_check_disable(ubwcp, buf->desc->idx);
  1796. if (ret) {
  1797. ubwcp->state = UBWCP_STATE_FAULT;
  1798. ERR("state set to fault");
  1799. }
  1800. /* release descriptor if perm range xlation is not set */
  1801. if (!buf->perm) {
  1802. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1803. buf->desc = NULL;
  1804. }
  1805. return ret;
  1806. }
  1807. /**
  1808. * Unlock buffer from CPU access. This prepares ubwcp hw to
  1809. * safely allow for device access to the compressed buffer including any
  1810. * necessary cache maintenance ops. It may also free up certain ubwcp
  1811. * resources that could result in error when accessed by CPU in
  1812. * unlocked state.
  1813. *
  1814. * @param dmabuf : ptr to the dma buf
  1815. * @param direction : direction of access
  1816. *
  1817. * @return int : 0 on success, otherwise error code
  1818. */
  1819. static int ubwcp_unlock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1820. {
  1821. struct ubwcp_buf *buf;
  1822. int ret;
  1823. trace_ubwcp_unlock_start(dmabuf);
  1824. if (!dmabuf) {
  1825. ERR("NULL dmabuf input ptr");
  1826. trace_ubwcp_unlock_end(dmabuf);
  1827. return -EINVAL;
  1828. }
  1829. if (!valid_dma_direction(dir)) {
  1830. ERR("invalid direction: %d", dir);
  1831. trace_ubwcp_unlock_end(dmabuf);
  1832. return -EINVAL;
  1833. }
  1834. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1835. if (!buf) {
  1836. ERR("ubwcp_buf not found");
  1837. trace_ubwcp_unlock_end(dmabuf);
  1838. return -1;
  1839. }
  1840. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1841. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1842. trace_ubwcp_unlock_end(dmabuf);
  1843. return -EPERM;
  1844. }
  1845. mutex_lock(&buf->lock);
  1846. if (!buf->lock_count) {
  1847. ERR("unlock() called on buffer which not in locked state");
  1848. trace_ubwcp_unlock_end(dmabuf);
  1849. mutex_unlock(&buf->lock);
  1850. return -1;
  1851. }
  1852. ret = unlock_internal(buf, dir, false);
  1853. mutex_unlock(&buf->lock);
  1854. trace_ubwcp_unlock_end(dmabuf);
  1855. return ret;
  1856. }
  1857. /* Return buffer attributes for the given buffer */
  1858. int ubwcp_get_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1859. {
  1860. int ret = 0;
  1861. struct ubwcp_buf *buf;
  1862. if (!dmabuf) {
  1863. ERR("NULL dmabuf input ptr");
  1864. return -EINVAL;
  1865. }
  1866. if (!attr) {
  1867. ERR("NULL attr ptr");
  1868. return -EINVAL;
  1869. }
  1870. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1871. if (!buf) {
  1872. ERR("ubwcp_buf ptr not found");
  1873. return -1;
  1874. }
  1875. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1876. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1877. return -EPERM;
  1878. }
  1879. mutex_lock(&buf->lock);
  1880. if (!buf->buf_attr_set) {
  1881. ERR("buffer attributes not set");
  1882. mutex_unlock(&buf->lock);
  1883. return -1;
  1884. }
  1885. *attr = buf->buf_attr;
  1886. mutex_unlock(&buf->lock);
  1887. return ret;
  1888. }
  1889. EXPORT_SYMBOL(ubwcp_get_buf_attrs);
  1890. /* Set permanent range translation.
  1891. * enable: Descriptor will be reserved for this buffer until disabled,
  1892. * making lock/unlock quicker.
  1893. * disable: Descriptor will not be reserved for this buffer. Instead,
  1894. * descriptor will be allocated and released for each lock/unlock.
  1895. * If currently allocated but not being used, descriptor will be
  1896. * released.
  1897. */
  1898. int ubwcp_set_perm_range_translation(struct dma_buf *dmabuf, bool enable)
  1899. {
  1900. int ret = 0;
  1901. struct ubwcp_buf *buf;
  1902. if (!dmabuf) {
  1903. ERR("NULL dmabuf input ptr");
  1904. return -EINVAL;
  1905. }
  1906. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1907. if (!buf) {
  1908. ERR("ubwcp_buf not found");
  1909. return -1;
  1910. }
  1911. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1912. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1913. return -EPERM;
  1914. }
  1915. /* not implemented */
  1916. if (1) {
  1917. ERR("API not implemented yet");
  1918. return -1;
  1919. }
  1920. /* TBD: make sure we acquire buf lock while setting this so there is
  1921. * no race condition with attr_set/lock/unlock
  1922. */
  1923. buf->perm = enable;
  1924. /* if "disable" and we have allocated a desc and it is not being
  1925. * used currently, release it
  1926. */
  1927. if (!enable && buf->desc && !buf->lock_count) {
  1928. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1929. buf->desc = NULL;
  1930. /* Flush/invalidate UBWCP caches */
  1931. //TBD: need to do anything?
  1932. }
  1933. return ret;
  1934. }
  1935. EXPORT_SYMBOL(ubwcp_set_perm_range_translation);
  1936. /**
  1937. * Free up ubwcp resources for this buffer.
  1938. *
  1939. * @param dmabuf : ptr to the dma buf
  1940. *
  1941. * @return int : 0 on success, otherwise error code
  1942. */
  1943. static int ubwcp_free_buffer(struct dma_buf *dmabuf)
  1944. {
  1945. int ret = 0;
  1946. struct ubwcp_buf *buf;
  1947. struct ubwcp_driver *ubwcp;
  1948. unsigned long flags;
  1949. bool is_non_lin_buf;
  1950. trace_ubwcp_free_buffer_start(dmabuf);
  1951. if (!dmabuf) {
  1952. ERR("NULL dmabuf input ptr");
  1953. trace_ubwcp_free_buffer_end(dmabuf);
  1954. return -EINVAL;
  1955. }
  1956. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1957. if (!buf) {
  1958. ERR("ubwcp_buf ptr not found");
  1959. trace_ubwcp_free_buffer_end(dmabuf);
  1960. return -1;
  1961. }
  1962. ubwcp = buf->ubwcp;
  1963. if (ubwcp->state != UBWCP_STATE_READY) {
  1964. ERR("driver in invalid state: %d", ubwcp->state);
  1965. trace_ubwcp_free_buffer_end(dmabuf);
  1966. return -EPERM;
  1967. }
  1968. mutex_lock(&buf->lock);
  1969. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1970. if (buf->lock_count) {
  1971. DBG("free before unlock (lock_count: %d). unlock()'ing first", buf->lock_count);
  1972. ret = unlock_internal(buf, buf->dma_dir, true);
  1973. if (ret)
  1974. ERR("unlock_internal(): failed : %d, but continuing free()", ret);
  1975. }
  1976. /* if we are still holding a desc, release it. this can happen only if perm == true */
  1977. if (buf->desc) {
  1978. if (!buf->perm) {
  1979. ubwcp->state = UBWCP_STATE_FAULT;
  1980. ERR("state set to fault");
  1981. }
  1982. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1983. buf->desc = NULL;
  1984. }
  1985. if (buf->buf_attr_set)
  1986. reset_buf_attrs(buf);
  1987. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  1988. hash_del(&buf->hnode);
  1989. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  1990. mutex_unlock(&buf->lock);
  1991. kfree(buf);
  1992. if (is_non_lin_buf)
  1993. dec_num_non_lin_buffers(ubwcp);
  1994. trace_ubwcp_free_buffer_end(dmabuf);
  1995. return ret;
  1996. }
  1997. /* file open: TBD: increment ref count? */
  1998. static int ubwcp_open(struct inode *i, struct file *f)
  1999. {
  2000. return 0;
  2001. }
  2002. /* file open: TBD: decrement ref count? */
  2003. static int ubwcp_close(struct inode *i, struct file *f)
  2004. {
  2005. return 0;
  2006. }
  2007. static int ioctl_set_buf_attr(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  2008. {
  2009. int ret;
  2010. struct dma_buf *dmabuf;
  2011. struct ubwcp_ioctl_buffer_attrs buf_attr_ioctl;
  2012. if (copy_from_user(&buf_attr_ioctl, (const void __user *) ioctl_param,
  2013. sizeof(buf_attr_ioctl))) {
  2014. ERR("copy_from_user() failed");
  2015. return -EFAULT;
  2016. }
  2017. DBG("IOCTL: SET_BUF_ATTR: fd = %d", buf_attr_ioctl.fd);
  2018. dmabuf = dma_buf_get(buf_attr_ioctl.fd);
  2019. if (IS_ERR(dmabuf)) {
  2020. ERR("dmabuf ptr not found for dma_buf_fd = %d", buf_attr_ioctl.fd);
  2021. return PTR_ERR(dmabuf);
  2022. }
  2023. ret = ubwcp_set_buf_attrs(dmabuf, &buf_attr_ioctl.attr);
  2024. dma_buf_put(dmabuf);
  2025. return ret;
  2026. }
  2027. static int ioctl_get_hw_ver(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  2028. {
  2029. struct ubwcp_ioctl_hw_version hw_ver;
  2030. DBG("IOCTL: GET_HW_VER");
  2031. if (ubwcp_get_hw_version(&hw_ver))
  2032. return -EINVAL;
  2033. if (copy_to_user((void __user *)ioctl_param, &hw_ver, sizeof(hw_ver))) {
  2034. ERR("copy_to_user() failed");
  2035. return -EFAULT;
  2036. }
  2037. return 0;
  2038. }
  2039. static int ioctl_get_stride_align(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  2040. {
  2041. struct ubwcp_ioctl_stride_align stride_align_ioctl;
  2042. enum ubwcp_std_image_format format;
  2043. DBG("IOCTL: GET_STRIDE_ALIGN");
  2044. if (copy_from_user(&stride_align_ioctl, (const void __user *) ioctl_param,
  2045. sizeof(stride_align_ioctl))) {
  2046. ERR("copy_from_user() failed");
  2047. return -EFAULT;
  2048. }
  2049. if (stride_align_ioctl.unused != 0) {
  2050. ERR("unused values must be set to 0");
  2051. return -EINVAL;
  2052. }
  2053. if (!ioctl_format_is_valid(stride_align_ioctl.image_format)) {
  2054. ERR("invalid image format: %d", stride_align_ioctl.image_format);
  2055. return -EINVAL;
  2056. }
  2057. if (stride_align_ioctl.image_format == UBWCP_LINEAR) {
  2058. ERR("not supported for LINEAR format");
  2059. return -EINVAL;
  2060. }
  2061. if (to_std_format(stride_align_ioctl.image_format, &format)) {
  2062. ERR("Unable to map ioctl image format to std image format");
  2063. return -EINVAL;
  2064. }
  2065. if (get_stride_alignment(format, &stride_align_ioctl.stride_align)) {
  2066. ERR("failed for format: %d", format);
  2067. return -EFAULT;
  2068. }
  2069. if (copy_to_user((void __user *)ioctl_param, &stride_align_ioctl,
  2070. sizeof(stride_align_ioctl))) {
  2071. ERR("copy_to_user() failed");
  2072. return -EFAULT;
  2073. }
  2074. return 0;
  2075. }
  2076. static int ioctl_validate_stride(struct ubwcp_driver *ubwcp, unsigned long ioctl_param)
  2077. {
  2078. struct ubwcp_ioctl_validate_stride validate_stride_ioctl;
  2079. enum ubwcp_std_image_format format;
  2080. DBG("IOCTL: VALIDATE_STRIDE");
  2081. if (copy_from_user(&validate_stride_ioctl, (const void __user *) ioctl_param,
  2082. sizeof(validate_stride_ioctl))) {
  2083. ERR("copy_from_user() failed");
  2084. return -EFAULT;
  2085. }
  2086. if (validate_stride_ioctl.unused1 || validate_stride_ioctl.unused2) {
  2087. ERR("unused values must be set to 0");
  2088. return -EINVAL;
  2089. }
  2090. if (!ioctl_format_is_valid(validate_stride_ioctl.image_format)) {
  2091. ERR("not supported for LINEAR format");
  2092. return -EINVAL;
  2093. }
  2094. if (validate_stride_ioctl.image_format == UBWCP_LINEAR) {
  2095. ERR("not supported for LINEAR format");
  2096. return -EINVAL;
  2097. }
  2098. if (to_std_format(validate_stride_ioctl.image_format, &format)) {
  2099. ERR("Unable to map ioctl image format to std image format");
  2100. return -EINVAL;
  2101. }
  2102. validate_stride_ioctl.valid = stride_is_valid(ubwcp, format, validate_stride_ioctl.width,
  2103. validate_stride_ioctl.stride);
  2104. if (copy_to_user((void __user *)ioctl_param, &validate_stride_ioctl,
  2105. sizeof(validate_stride_ioctl))) {
  2106. ERR("copy_to_user() failed");
  2107. return -EFAULT;
  2108. }
  2109. return 0;
  2110. }
  2111. /* handle IOCTLs */
  2112. static long ubwcp_ioctl(struct file *file, unsigned int ioctl_num, unsigned long ioctl_param)
  2113. {
  2114. struct ubwcp_driver *ubwcp;
  2115. ubwcp = ubwcp_get_driver();
  2116. if (!ubwcp)
  2117. return -EINVAL;
  2118. if (ubwcp->state != UBWCP_STATE_READY) {
  2119. ERR("driver in invalid state: %d", ubwcp->state);
  2120. return -EPERM;
  2121. }
  2122. switch (ioctl_num) {
  2123. case UBWCP_IOCTL_SET_BUF_ATTR:
  2124. return ioctl_set_buf_attr(ubwcp, ioctl_param);
  2125. case UBWCP_IOCTL_GET_HW_VER:
  2126. return ioctl_get_hw_ver(ubwcp, ioctl_param);
  2127. case UBWCP_IOCTL_GET_STRIDE_ALIGN:
  2128. return ioctl_get_stride_align(ubwcp, ioctl_param);
  2129. case UBWCP_IOCTL_VALIDATE_STRIDE:
  2130. return ioctl_validate_stride(ubwcp, ioctl_param);
  2131. default:
  2132. ERR("Invalid ioctl_num = %d", ioctl_num);
  2133. return -EINVAL;
  2134. }
  2135. return 0;
  2136. }
  2137. static const struct file_operations ubwcp_fops = {
  2138. .owner = THIS_MODULE,
  2139. .open = ubwcp_open,
  2140. .release = ubwcp_close,
  2141. .unlocked_ioctl = ubwcp_ioctl,
  2142. };
  2143. static int read_err_r_op(void *data, u64 *value)
  2144. {
  2145. struct ubwcp_driver *ubwcp = data;
  2146. *value = ubwcp->read_err_irq_en;
  2147. return 0;
  2148. }
  2149. static int read_err_w_op(void *data, u64 value)
  2150. {
  2151. struct ubwcp_driver *ubwcp = data;
  2152. if (ubwcp->state != UBWCP_STATE_READY)
  2153. return -EPERM;
  2154. if (ubwcp_power(ubwcp, true))
  2155. goto err;
  2156. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, value);
  2157. ubwcp->read_err_irq_en = value;
  2158. if (ubwcp_power(ubwcp, false))
  2159. goto err;
  2160. return 0;
  2161. err:
  2162. ubwcp->state = UBWCP_STATE_FAULT;
  2163. ERR("state set to fault");
  2164. return -1;
  2165. }
  2166. static int write_err_r_op(void *data, u64 *value)
  2167. {
  2168. struct ubwcp_driver *ubwcp = data;
  2169. if (ubwcp->state != UBWCP_STATE_READY)
  2170. return -EPERM;
  2171. *value = ubwcp->write_err_irq_en;
  2172. return 0;
  2173. }
  2174. static int write_err_w_op(void *data, u64 value)
  2175. {
  2176. struct ubwcp_driver *ubwcp = data;
  2177. if (ubwcp->state != UBWCP_STATE_READY)
  2178. return -EPERM;
  2179. if (ubwcp_power(ubwcp, true))
  2180. goto err;
  2181. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, value);
  2182. ubwcp->write_err_irq_en = value;
  2183. if (ubwcp_power(ubwcp, false))
  2184. goto err;
  2185. return 0;
  2186. err:
  2187. ubwcp->state = UBWCP_STATE_FAULT;
  2188. ERR("state set to fault");
  2189. return -1;
  2190. }
  2191. static int decode_err_r_op(void *data, u64 *value)
  2192. {
  2193. struct ubwcp_driver *ubwcp = data;
  2194. if (ubwcp->state != UBWCP_STATE_READY)
  2195. return -EPERM;
  2196. *value = ubwcp->decode_err_irq_en;
  2197. return 0;
  2198. }
  2199. static int decode_err_w_op(void *data, u64 value)
  2200. {
  2201. struct ubwcp_driver *ubwcp = data;
  2202. if (ubwcp->state != UBWCP_STATE_READY)
  2203. return -EPERM;
  2204. if (ubwcp_power(ubwcp, true))
  2205. goto err;
  2206. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, value);
  2207. ubwcp->decode_err_irq_en = value;
  2208. if (ubwcp_power(ubwcp, false))
  2209. goto err;
  2210. return 0;
  2211. err:
  2212. ubwcp->state = UBWCP_STATE_FAULT;
  2213. ERR("state set to fault");
  2214. return -1;
  2215. }
  2216. static int encode_err_r_op(void *data, u64 *value)
  2217. {
  2218. struct ubwcp_driver *ubwcp = data;
  2219. if (ubwcp->state != UBWCP_STATE_READY)
  2220. return -EPERM;
  2221. *value = ubwcp->encode_err_irq_en;
  2222. return 0;
  2223. }
  2224. static int encode_err_w_op(void *data, u64 value)
  2225. {
  2226. struct ubwcp_driver *ubwcp = data;
  2227. if (ubwcp->state != UBWCP_STATE_READY)
  2228. return -EPERM;
  2229. if (ubwcp_power(ubwcp, true))
  2230. goto err;
  2231. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, value);
  2232. ubwcp->encode_err_irq_en = value;
  2233. if (ubwcp_power(ubwcp, false))
  2234. goto err;
  2235. return 0;
  2236. err:
  2237. ubwcp->state = UBWCP_STATE_FAULT;
  2238. ERR("state set to fault");
  2239. return -1;
  2240. }
  2241. static int reg_rw_trace_w_op(void *data, u64 value)
  2242. {
  2243. struct ubwcp_driver *ubwcp = data;
  2244. if (ubwcp->state != UBWCP_STATE_READY)
  2245. return -EPERM;
  2246. ubwcp_hw_trace_set(value);
  2247. return 0;
  2248. }
  2249. static int reg_rw_trace_r_op(void *data, u64 *value)
  2250. {
  2251. struct ubwcp_driver *ubwcp = data;
  2252. bool trace_status;
  2253. if (ubwcp->state != UBWCP_STATE_READY)
  2254. return -EPERM;
  2255. ubwcp_hw_trace_get(&trace_status);
  2256. *value = trace_status;
  2257. return 0;
  2258. }
  2259. DEFINE_DEBUGFS_ATTRIBUTE(read_err_fops, read_err_r_op, read_err_w_op, "%d\n");
  2260. DEFINE_DEBUGFS_ATTRIBUTE(decode_err_fops, decode_err_r_op, decode_err_w_op, "%d\n");
  2261. DEFINE_DEBUGFS_ATTRIBUTE(write_err_fops, write_err_r_op, write_err_w_op, "%d\n");
  2262. DEFINE_DEBUGFS_ATTRIBUTE(encode_err_fops, encode_err_r_op, encode_err_w_op, "%d\n");
  2263. DEFINE_DEBUGFS_ATTRIBUTE(reg_rw_trace_fops, reg_rw_trace_r_op, reg_rw_trace_w_op, "%d\n");
  2264. static void ubwcp_debugfs_init(struct ubwcp_driver *ubwcp)
  2265. {
  2266. struct dentry *debugfs_root;
  2267. struct dentry *dfile;
  2268. debugfs_root = debugfs_create_dir("ubwcp", NULL);
  2269. if (IS_ERR_OR_NULL(debugfs_root)) {
  2270. ERR("Failed to create debugfs for ubwcp\n");
  2271. return;
  2272. }
  2273. debugfs_create_u32("debug_trace_enable", 0644, debugfs_root, &ubwcp_debug_trace_enable);
  2274. dfile = debugfs_create_file("reg_rw_trace_en", 0644, debugfs_root, ubwcp, &reg_rw_trace_fops);
  2275. if (IS_ERR_OR_NULL(dfile)) {
  2276. ERR("failed to create reg_rw_trace_en debugfs file");
  2277. goto err;
  2278. }
  2279. dfile = debugfs_create_file("read_err_irq_en", 0644, debugfs_root, ubwcp, &read_err_fops);
  2280. if (IS_ERR_OR_NULL(dfile)) {
  2281. ERR("failed to create read_err_irq debugfs file");
  2282. goto err;
  2283. }
  2284. dfile = debugfs_create_file("write_err_irq_en", 0644, debugfs_root, ubwcp, &write_err_fops);
  2285. if (IS_ERR_OR_NULL(dfile)) {
  2286. ERR("failed to create write_err_irq debugfs file");
  2287. goto err;
  2288. }
  2289. dfile = debugfs_create_file("decode_err_irq_en", 0644, debugfs_root, ubwcp,
  2290. &decode_err_fops);
  2291. if (IS_ERR_OR_NULL(dfile)) {
  2292. ERR("failed to create decode_err_irq debugfs file");
  2293. goto err;
  2294. }
  2295. dfile = debugfs_create_file("encode_err_irq_en", 0644, debugfs_root, ubwcp,
  2296. &encode_err_fops);
  2297. if (IS_ERR_OR_NULL(dfile)) {
  2298. ERR("failed to create encode_err_irq debugfs file");
  2299. goto err;
  2300. }
  2301. ubwcp->debugfs_root = debugfs_root;
  2302. return;
  2303. err:
  2304. debugfs_remove_recursive(ubwcp->debugfs_root);
  2305. ubwcp->debugfs_root = NULL;
  2306. }
  2307. static void ubwcp_debugfs_deinit(struct ubwcp_driver *ubwcp)
  2308. {
  2309. debugfs_remove_recursive(ubwcp->debugfs_root);
  2310. }
  2311. /* ubwcp char device initialization */
  2312. static int ubwcp_cdev_init(struct ubwcp_driver *ubwcp)
  2313. {
  2314. int ret;
  2315. dev_t devt;
  2316. struct class *dev_class;
  2317. struct device *dev_sys;
  2318. /* allocate major device number (/proc/devices -> major_num ubwcp) */
  2319. ret = alloc_chrdev_region(&devt, 0, UBWCP_NUM_DEVICES, UBWCP_DEVICE_NAME);
  2320. if (ret) {
  2321. ERR("alloc_chrdev_region() failed: %d", ret);
  2322. return ret;
  2323. }
  2324. /* create device class (/sys/class/ubwcp_class) */
  2325. dev_class = class_create(THIS_MODULE, "ubwcp_class");
  2326. if (IS_ERR(dev_class)) {
  2327. ret = PTR_ERR(dev_class);
  2328. ERR("class_create() failed, ret: %d", ret);
  2329. goto err;
  2330. }
  2331. /* Create device and register with sysfs
  2332. * (/sys/class/ubwcp_class/ubwcp/... -> dev/power/subsystem/uevent)
  2333. */
  2334. dev_sys = device_create(dev_class, NULL, devt, NULL,
  2335. UBWCP_DEVICE_NAME);
  2336. if (IS_ERR(dev_sys)) {
  2337. ret = PTR_ERR(dev_sys);
  2338. ERR("device_create() failed, ret: %d", ret);
  2339. goto err_device_create;
  2340. }
  2341. /* register file operations and get cdev */
  2342. cdev_init(&ubwcp->cdev, &ubwcp_fops);
  2343. /* associate cdev and device major/minor with file system
  2344. * can do file ops on /dev/ubwcp after this
  2345. */
  2346. ret = cdev_add(&ubwcp->cdev, devt, 1);
  2347. if (ret) {
  2348. ERR("cdev_add() failed, ret: %d", ret);
  2349. goto err_cdev_add;
  2350. }
  2351. ubwcp->devt = devt;
  2352. ubwcp->dev_class = dev_class;
  2353. ubwcp->dev_sys = dev_sys;
  2354. return 0;
  2355. err_cdev_add:
  2356. device_destroy(dev_class, devt);
  2357. err_device_create:
  2358. class_destroy(dev_class);
  2359. err:
  2360. unregister_chrdev_region(devt, UBWCP_NUM_DEVICES);
  2361. return ret;
  2362. }
  2363. static void ubwcp_cdev_deinit(struct ubwcp_driver *ubwcp)
  2364. {
  2365. device_destroy(ubwcp->dev_class, ubwcp->devt);
  2366. class_destroy(ubwcp->dev_class);
  2367. cdev_del(&ubwcp->cdev);
  2368. unregister_chrdev_region(ubwcp->devt, UBWCP_NUM_DEVICES);
  2369. }
  2370. struct handler_node {
  2371. struct list_head list;
  2372. u32 client_id;
  2373. ubwcp_error_handler_t handler;
  2374. void *data;
  2375. };
  2376. int ubwcp_register_error_handler(u32 client_id, ubwcp_error_handler_t handler,
  2377. void *data)
  2378. {
  2379. struct handler_node *node;
  2380. unsigned long flags;
  2381. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2382. if (!ubwcp)
  2383. return -EINVAL;
  2384. if (client_id != -1)
  2385. return -EINVAL;
  2386. if (!handler)
  2387. return -EINVAL;
  2388. if (ubwcp->state != UBWCP_STATE_READY)
  2389. return -EPERM;
  2390. node = kzalloc(sizeof(*node), GFP_KERNEL);
  2391. if (!node)
  2392. return -ENOMEM;
  2393. node->client_id = client_id;
  2394. node->handler = handler;
  2395. node->data = data;
  2396. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2397. list_add_tail(&node->list, &ubwcp->err_handler_list);
  2398. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2399. return 0;
  2400. }
  2401. EXPORT_SYMBOL(ubwcp_register_error_handler);
  2402. static void ubwcp_notify_error_handlers(struct ubwcp_err_info *err)
  2403. {
  2404. struct handler_node *node;
  2405. unsigned long flags;
  2406. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2407. if (!ubwcp)
  2408. return;
  2409. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2410. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2411. node->handler(err, node->data);
  2412. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2413. }
  2414. int ubwcp_unregister_error_handler(u32 client_id)
  2415. {
  2416. int ret = -EINVAL;
  2417. struct handler_node *node;
  2418. unsigned long flags;
  2419. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2420. if (!ubwcp)
  2421. return -EINVAL;
  2422. if (ubwcp->state != UBWCP_STATE_INVALID)
  2423. return -EPERM;
  2424. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2425. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2426. if (node->client_id == client_id) {
  2427. list_del(&node->list);
  2428. kfree(node);
  2429. ret = 0;
  2430. break;
  2431. }
  2432. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2433. return ret;
  2434. }
  2435. EXPORT_SYMBOL(ubwcp_unregister_error_handler);
  2436. /* get ubwcp_buf corresponding to the ULA PA*/
  2437. static struct dma_buf *get_dma_buf_from_ulapa(phys_addr_t addr)
  2438. {
  2439. struct ubwcp_buf *buf = NULL;
  2440. struct dma_buf *ret_buf = NULL;
  2441. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2442. unsigned long flags;
  2443. u32 i;
  2444. if (!ubwcp)
  2445. return NULL;
  2446. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2447. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2448. if (buf->ula_pa <= addr && addr < buf->ula_pa + buf->ula_size) {
  2449. ret_buf = buf->dma_buf;
  2450. break;
  2451. }
  2452. }
  2453. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2454. return ret_buf;
  2455. }
  2456. /* get ubwcp_buf corresponding to the IOVA*/
  2457. static struct dma_buf *get_dma_buf_from_iova(unsigned long addr)
  2458. {
  2459. struct ubwcp_buf *buf = NULL;
  2460. struct dma_buf *ret_buf = NULL;
  2461. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2462. unsigned long flags;
  2463. u32 i;
  2464. if (!ubwcp)
  2465. return NULL;
  2466. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2467. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2468. unsigned long iova_base;
  2469. unsigned int iova_size;
  2470. if (!buf->sgt)
  2471. continue;
  2472. iova_base = sg_dma_address(buf->sgt->sgl);
  2473. iova_size = sg_dma_len(buf->sgt->sgl);
  2474. if (iova_base <= addr && addr < iova_base + iova_size) {
  2475. ret_buf = buf->dma_buf;
  2476. break;
  2477. }
  2478. }
  2479. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2480. return ret_buf;
  2481. }
  2482. int ubwcp_iommu_fault_handler(struct iommu_domain *domain, struct device *dev,
  2483. unsigned long iova, int flags, void *data)
  2484. {
  2485. int ret = 0;
  2486. struct ubwcp_err_info err;
  2487. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2488. struct device *cb_dev = (struct device *)data;
  2489. if (!ubwcp) {
  2490. ret = -EINVAL;
  2491. goto err;
  2492. }
  2493. err.err_code = UBWCP_SMMU_FAULT;
  2494. if (cb_dev == ubwcp->dev_desc_cb)
  2495. err.smmu_err.iommu_dev_id = UBWCP_DESC_CB_ID;
  2496. else if (cb_dev == ubwcp->dev_buf_cb)
  2497. err.smmu_err.iommu_dev_id = UBWCP_BUF_CB_ID;
  2498. else
  2499. err.smmu_err.iommu_dev_id = UBWCP_UNKNOWN_CB_ID;
  2500. err.smmu_err.dmabuf = get_dma_buf_from_iova(iova);
  2501. err.smmu_err.iova = iova;
  2502. err.smmu_err.iommu_fault_flags = flags;
  2503. ERR("ubwcp_err: err code: %d (smmu), iommu_dev_id: %d, iova: 0x%llx, flags: 0x%x",
  2504. err.err_code, err.smmu_err.iommu_dev_id, err.smmu_err.iova,
  2505. err.smmu_err.iommu_fault_flags);
  2506. ubwcp_notify_error_handlers(&err);
  2507. err:
  2508. return ret;
  2509. }
  2510. static irqreturn_t ubwcp_irq_handler(int irq, void *ptr)
  2511. {
  2512. struct ubwcp_driver *ubwcp;
  2513. void __iomem *base;
  2514. phys_addr_t addr;
  2515. struct ubwcp_err_info err;
  2516. ubwcp = (struct ubwcp_driver *) ptr;
  2517. base = ubwcp->base;
  2518. if (irq == ubwcp->irq_range_ck_rd) {
  2519. addr = ubwcp_hw_interrupt_src_address(base, 0) << 6;
  2520. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2521. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2522. err.translation_err.ula_pa = addr;
  2523. err.translation_err.read = true;
  2524. ERR("err_code: %d (range read), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2525. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2526. ubwcp_notify_error_handlers(&err);
  2527. ubwcp_hw_interrupt_clear(ubwcp->base, 0);
  2528. } else if (irq == ubwcp->irq_range_ck_wr) {
  2529. addr = ubwcp_hw_interrupt_src_address(base, 1) << 6;
  2530. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2531. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2532. err.translation_err.ula_pa = addr;
  2533. err.translation_err.read = false;
  2534. ERR("err_code: %d (range write), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2535. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2536. ubwcp_notify_error_handlers(&err);
  2537. ubwcp_hw_interrupt_clear(ubwcp->base, 1);
  2538. } else if (irq == ubwcp->irq_encode) {
  2539. addr = ubwcp_hw_interrupt_src_address(base, 3) << 6;
  2540. err.err_code = UBWCP_ENCODE_ERROR;
  2541. err.enc_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2542. err.enc_err.ula_pa = addr;
  2543. ERR("err_code: %d (encode), dmabuf: 0x%llx, addr: 0x%llx",
  2544. err.err_code, err.enc_err.dmabuf, addr);
  2545. ubwcp_notify_error_handlers(&err);
  2546. ubwcp_hw_interrupt_clear(ubwcp->base, 3);
  2547. } else if (irq == ubwcp->irq_decode) {
  2548. addr = ubwcp_hw_interrupt_src_address(base, 2) << 6;
  2549. err.err_code = UBWCP_DECODE_ERROR;
  2550. err.dec_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2551. err.dec_err.ula_pa = addr;
  2552. ERR("err_code: %d (decode), dmabuf: 0x%llx, addr: 0x%llx",
  2553. err.err_code, err.enc_err.dmabuf, addr);
  2554. ubwcp_notify_error_handlers(&err);
  2555. ubwcp_hw_interrupt_clear(ubwcp->base, 2);
  2556. } else {
  2557. ERR("unknown irq: %d", irq);
  2558. return IRQ_NONE;
  2559. }
  2560. return IRQ_HANDLED;
  2561. }
  2562. static int ubwcp_interrupt_register(struct platform_device *pdev, struct ubwcp_driver *ubwcp)
  2563. {
  2564. int ret = 0;
  2565. struct device *dev = &pdev->dev;
  2566. ubwcp->irq_range_ck_rd = platform_get_irq(pdev, 0);
  2567. if (ubwcp->irq_range_ck_rd < 0)
  2568. return ubwcp->irq_range_ck_rd;
  2569. ubwcp->irq_range_ck_wr = platform_get_irq(pdev, 1);
  2570. if (ubwcp->irq_range_ck_wr < 0)
  2571. return ubwcp->irq_range_ck_wr;
  2572. ubwcp->irq_encode = platform_get_irq(pdev, 2);
  2573. if (ubwcp->irq_encode < 0)
  2574. return ubwcp->irq_encode;
  2575. ubwcp->irq_decode = platform_get_irq(pdev, 3);
  2576. if (ubwcp->irq_decode < 0)
  2577. return ubwcp->irq_decode;
  2578. DBG("got irqs: %d %d %d %d", ubwcp->irq_range_ck_rd,
  2579. ubwcp->irq_range_ck_wr,
  2580. ubwcp->irq_encode,
  2581. ubwcp->irq_decode);
  2582. ret = devm_request_irq(dev, ubwcp->irq_range_ck_rd, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2583. if (ret) {
  2584. ERR("request_irq() failed. irq: %d ret: %d",
  2585. ubwcp->irq_range_ck_rd, ret);
  2586. return ret;
  2587. }
  2588. ret = devm_request_irq(dev, ubwcp->irq_range_ck_wr, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2589. if (ret) {
  2590. ERR("request_irq() failed. irq: %d ret: %d",
  2591. ubwcp->irq_range_ck_wr, ret);
  2592. return ret;
  2593. }
  2594. ret = devm_request_irq(dev, ubwcp->irq_encode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2595. if (ret) {
  2596. ERR("request_irq() failed. irq: %d ret: %d",
  2597. ubwcp->irq_encode, ret);
  2598. return ret;
  2599. }
  2600. ret = devm_request_irq(dev, ubwcp->irq_decode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2601. if (ret) {
  2602. ERR("request_irq() failed. irq: %d ret: %d",
  2603. ubwcp->irq_decode, ret);
  2604. return ret;
  2605. }
  2606. return ret;
  2607. }
  2608. /* ubwcp device probe */
  2609. static int qcom_ubwcp_probe(struct platform_device *pdev)
  2610. {
  2611. int ret = 0;
  2612. struct ubwcp_driver *ubwcp;
  2613. struct device *ubwcp_dev = &pdev->dev;
  2614. ubwcp = devm_kzalloc(ubwcp_dev, sizeof(*ubwcp), GFP_KERNEL);
  2615. if (!ubwcp) {
  2616. ERR("devm_kzalloc() failed");
  2617. return -ENOMEM;
  2618. }
  2619. ubwcp->dev = &pdev->dev;
  2620. ret = dma_set_mask_and_coherent(ubwcp->dev, DMA_BIT_MASK(64));
  2621. ubwcp->base = devm_platform_ioremap_resource(pdev, 0);
  2622. if (IS_ERR(ubwcp->base)) {
  2623. ERR("devm ioremap() failed: %d", PTR_ERR(ubwcp->base));
  2624. return PTR_ERR(ubwcp->base);
  2625. }
  2626. DBG("ubwcp->base: %p", ubwcp->base);
  2627. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 0, &ubwcp->ula_pool_base);
  2628. if (ret) {
  2629. ERR("failed reading ula_range (base): %d", ret);
  2630. return ret;
  2631. }
  2632. DBG("ubwcp: ula_range: base = 0x%lx", ubwcp->ula_pool_base);
  2633. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 1, &ubwcp->ula_pool_size);
  2634. if (ret) {
  2635. ERR("failed reading ula_range (size): %d", ret);
  2636. return ret;
  2637. }
  2638. DBG("ubwcp: ula_range: size = 0x%lx", ubwcp->ula_pool_size);
  2639. INIT_LIST_HEAD(&ubwcp->err_handler_list);
  2640. /* driver initial state */
  2641. ubwcp->state = UBWCP_STATE_INVALID;
  2642. atomic_set(&ubwcp->num_non_lin_buffers, 0);
  2643. ubwcp->mem_online = false;
  2644. mutex_init(&ubwcp->desc_lock);
  2645. spin_lock_init(&ubwcp->buf_table_lock);
  2646. mutex_init(&ubwcp->mem_hotplug_lock);
  2647. mutex_init(&ubwcp->ula_lock);
  2648. mutex_init(&ubwcp->ubwcp_flush_lock);
  2649. mutex_init(&ubwcp->hw_range_ck_lock);
  2650. mutex_init(&ubwcp->power_ctrl_lock);
  2651. spin_lock_init(&ubwcp->err_handler_list_lock);
  2652. /* Regulator */
  2653. ubwcp->vdd = devm_regulator_get(ubwcp_dev, "vdd");
  2654. if (IS_ERR_OR_NULL(ubwcp->vdd)) {
  2655. ret = PTR_ERR(ubwcp->vdd);
  2656. ERR("devm_regulator_get() failed: %d", ret);
  2657. return ret;
  2658. }
  2659. ret = ubwcp_init_clocks(ubwcp, ubwcp_dev);
  2660. if (ret) {
  2661. ERR("failed to initialize ubwcp clocks err: %d", ret);
  2662. return ret;
  2663. }
  2664. if (ubwcp_power(ubwcp, true))
  2665. return -1;
  2666. if (ubwcp_cdev_init(ubwcp))
  2667. return -1;
  2668. /* disable all interrupts (reset value has some interrupts enabled by default) */
  2669. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2670. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2671. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2672. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2673. if (ubwcp_interrupt_register(pdev, ubwcp))
  2674. return -1;
  2675. ubwcp_debugfs_init(ubwcp);
  2676. /* create ULA pool */
  2677. ubwcp->ula_pool = gen_pool_create(PAGE_SHIFT, -1);
  2678. if (!ubwcp->ula_pool) {
  2679. ERR("failed gen_pool_create()");
  2680. ret = -1;
  2681. goto err_pool_create;
  2682. }
  2683. ret = gen_pool_add(ubwcp->ula_pool, ubwcp->ula_pool_base, ubwcp->ula_pool_size, -1);
  2684. if (ret) {
  2685. ERR("failed gen_pool_add(): %d", ret);
  2686. ret = -1;
  2687. goto err_pool_add;
  2688. }
  2689. /* register the default config mmap function. */
  2690. ubwcp->mmap_config_fptr = msm_ubwcp_dma_buf_configure_mmap;
  2691. hash_init(ubwcp->buf_table);
  2692. ubwcp_buf_desc_list_init(ubwcp);
  2693. image_format_init(ubwcp);
  2694. /* one time hw init */
  2695. ubwcp_hw_one_time_init(ubwcp->base);
  2696. ubwcp_hw_version(ubwcp->base, &ubwcp->hw_ver_major, &ubwcp->hw_ver_minor);
  2697. pr_err("ubwcp: hw version: major %d, minor %d\n", ubwcp->hw_ver_major, ubwcp->hw_ver_minor);
  2698. if (ubwcp->hw_ver_major == 0) {
  2699. ERR("Failed to read HW version");
  2700. ret = -1;
  2701. goto err_pool_add;
  2702. }
  2703. /* set pdev->dev->driver_data = ubwcp */
  2704. platform_set_drvdata(pdev, ubwcp);
  2705. /* enable interrupts */
  2706. if (ubwcp->read_err_irq_en)
  2707. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, true);
  2708. if (ubwcp->write_err_irq_en)
  2709. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, true);
  2710. if (ubwcp->decode_err_irq_en)
  2711. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, true);
  2712. if (ubwcp->encode_err_irq_en)
  2713. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, true);
  2714. /* Turn OFF until buffers are allocated */
  2715. if (ubwcp_power(ubwcp, false)) {
  2716. ret = -1;
  2717. goto err_power_off;
  2718. }
  2719. ret = msm_ubwcp_set_ops(ubwcp_init_buffer, ubwcp_free_buffer, ubwcp_lock, ubwcp_unlock);
  2720. if (ret) {
  2721. ERR("msm_ubwcp_set_ops() failed: %d", ret);
  2722. goto err_power_off;
  2723. } else {
  2724. DBG("msm_ubwcp_set_ops(): success"); }
  2725. me = ubwcp;
  2726. return ret;
  2727. err_power_off:
  2728. if (!ubwcp_power(ubwcp, true)) {
  2729. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2730. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2731. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2732. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2733. ubwcp_power(ubwcp, false);
  2734. }
  2735. err_pool_add:
  2736. gen_pool_destroy(ubwcp->ula_pool);
  2737. err_pool_create:
  2738. ubwcp_debugfs_deinit(ubwcp);
  2739. ubwcp_cdev_deinit(ubwcp);
  2740. return ret;
  2741. }
  2742. /* buffer context bank device probe */
  2743. static int ubwcp_probe_cb_buf(struct platform_device *pdev)
  2744. {
  2745. struct ubwcp_driver *ubwcp;
  2746. struct iommu_domain *domain = NULL;
  2747. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2748. if (!ubwcp) {
  2749. ERR("failed to get ubwcp ptr");
  2750. return -EINVAL;
  2751. }
  2752. ubwcp->dev_buf_cb = &pdev->dev;
  2753. domain = iommu_get_domain_for_dev(ubwcp->dev_buf_cb);
  2754. if (domain)
  2755. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_buf_cb);
  2756. if (ubwcp->dev_desc_cb)
  2757. ubwcp->state = UBWCP_STATE_READY;
  2758. return 0;
  2759. }
  2760. /* descriptor context bank device probe */
  2761. static int ubwcp_probe_cb_desc(struct platform_device *pdev)
  2762. {
  2763. int ret = 0;
  2764. struct ubwcp_driver *ubwcp;
  2765. struct iommu_domain *domain = NULL;
  2766. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2767. if (!ubwcp) {
  2768. ERR("failed to get ubwcp ptr");
  2769. return -EINVAL;
  2770. }
  2771. ubwcp->buffer_desc_size = UBWCP_BUFFER_DESC_OFFSET *
  2772. UBWCP_BUFFER_DESC_COUNT;
  2773. ubwcp->dev_desc_cb = &pdev->dev;
  2774. dma_set_max_seg_size(ubwcp->dev_desc_cb, DMA_BIT_MASK(32));
  2775. dma_set_seg_boundary(ubwcp->dev_desc_cb, (unsigned long)DMA_BIT_MASK(64));
  2776. /* Allocate buffer descriptors. UBWCP is iocoherent device.
  2777. * Thus we don't need to flush after updates to buffer descriptors.
  2778. */
  2779. ubwcp->buffer_desc_base = dma_alloc_coherent(ubwcp->dev_desc_cb,
  2780. ubwcp->buffer_desc_size,
  2781. &ubwcp->buffer_desc_dma_handle,
  2782. GFP_KERNEL);
  2783. if (!ubwcp->buffer_desc_base) {
  2784. ERR("failed to allocate desc buffer");
  2785. return -ENOMEM;
  2786. }
  2787. DBG("desc_base = %p size = %zu", ubwcp->buffer_desc_base,
  2788. ubwcp->buffer_desc_size);
  2789. ret = ubwcp_power(ubwcp, true);
  2790. if (ret) {
  2791. ERR("failed to power on");
  2792. goto err;
  2793. }
  2794. ubwcp_hw_set_buf_desc(ubwcp->base, (u64) ubwcp->buffer_desc_dma_handle,
  2795. UBWCP_BUFFER_DESC_OFFSET);
  2796. ret = ubwcp_power(ubwcp, false);
  2797. if (ret) {
  2798. ERR("failed to power off");
  2799. goto err;
  2800. }
  2801. domain = iommu_get_domain_for_dev(ubwcp->dev_desc_cb);
  2802. if (domain)
  2803. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_desc_cb);
  2804. if (ubwcp->dev_buf_cb)
  2805. ubwcp->state = UBWCP_STATE_READY;
  2806. return ret;
  2807. err:
  2808. dma_free_coherent(ubwcp->dev_desc_cb,
  2809. ubwcp->buffer_desc_size,
  2810. ubwcp->buffer_desc_base,
  2811. ubwcp->buffer_desc_dma_handle);
  2812. ubwcp->buffer_desc_base = NULL;
  2813. ubwcp->buffer_desc_dma_handle = 0;
  2814. ubwcp->dev_desc_cb = NULL;
  2815. return -1;
  2816. }
  2817. /* buffer context bank device remove */
  2818. static int ubwcp_remove_cb_buf(struct platform_device *pdev)
  2819. {
  2820. struct ubwcp_driver *ubwcp;
  2821. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2822. if (!ubwcp) {
  2823. ERR("failed to get ubwcp ptr");
  2824. return -EINVAL;
  2825. }
  2826. ubwcp->state = UBWCP_STATE_INVALID;
  2827. ubwcp->dev_buf_cb = NULL;
  2828. return 0;
  2829. }
  2830. /* descriptor context bank device remove */
  2831. static int ubwcp_remove_cb_desc(struct platform_device *pdev)
  2832. {
  2833. struct ubwcp_driver *ubwcp;
  2834. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2835. if (!ubwcp) {
  2836. ERR("failed to get ubwcp ptr");
  2837. return -EINVAL;
  2838. }
  2839. if (!ubwcp->dev_desc_cb) {
  2840. ERR("ubwcp->dev_desc_cb == NULL");
  2841. return -1;
  2842. }
  2843. if (!ubwcp_power(ubwcp, true)) {
  2844. ubwcp_hw_set_buf_desc(ubwcp->base, 0x0, 0x0);
  2845. ubwcp_power(ubwcp, false);
  2846. }
  2847. ubwcp->state = UBWCP_STATE_INVALID;
  2848. dma_free_coherent(ubwcp->dev_desc_cb,
  2849. ubwcp->buffer_desc_size,
  2850. ubwcp->buffer_desc_base,
  2851. ubwcp->buffer_desc_dma_handle);
  2852. ubwcp->buffer_desc_base = NULL;
  2853. ubwcp->buffer_desc_dma_handle = 0;
  2854. return 0;
  2855. }
  2856. /* ubwcp device remove */
  2857. static int qcom_ubwcp_remove(struct platform_device *pdev)
  2858. {
  2859. size_t avail;
  2860. size_t psize;
  2861. struct ubwcp_driver *ubwcp;
  2862. /* get pdev->dev->driver_data = ubwcp */
  2863. ubwcp = platform_get_drvdata(pdev);
  2864. if (!ubwcp) {
  2865. ERR("ubwcp == NULL");
  2866. return -1;
  2867. }
  2868. if (!ubwcp_power(ubwcp, true)) {
  2869. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2870. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2871. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2872. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2873. ubwcp_power(ubwcp, false);
  2874. }
  2875. ubwcp->state = UBWCP_STATE_INVALID;
  2876. /* before destroying, make sure pool is empty. otherwise pool_destroy() panics. */
  2877. avail = gen_pool_avail(ubwcp->ula_pool);
  2878. psize = gen_pool_size(ubwcp->ula_pool);
  2879. if (psize != avail) {
  2880. ERR("gen_pool is not empty! avail: %zx size: %zx", avail, psize);
  2881. ERR("skipping pool destroy....cause it will PANIC. Fix this!!!!");
  2882. } else {
  2883. gen_pool_destroy(ubwcp->ula_pool);
  2884. }
  2885. ubwcp_debugfs_deinit(ubwcp);
  2886. ubwcp_cdev_deinit(ubwcp);
  2887. return 0;
  2888. }
  2889. /* top level ubwcp device probe function */
  2890. static int ubwcp_probe(struct platform_device *pdev)
  2891. {
  2892. const char *compatible = "";
  2893. trace_ubwcp_probe(pdev);
  2894. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2895. return qcom_ubwcp_probe(pdev);
  2896. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2897. return ubwcp_probe_cb_desc(pdev);
  2898. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2899. return ubwcp_probe_cb_buf(pdev);
  2900. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2901. ERR("unknown device: %s", compatible);
  2902. return -EINVAL;
  2903. }
  2904. /* top level ubwcp device remove function */
  2905. static int ubwcp_remove(struct platform_device *pdev)
  2906. {
  2907. const char *compatible = "";
  2908. trace_ubwcp_remove(pdev);
  2909. /* TBD: what if buffers are still allocated? locked? etc.
  2910. * also should turn off power?
  2911. */
  2912. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2913. return qcom_ubwcp_remove(pdev);
  2914. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2915. return ubwcp_remove_cb_desc(pdev);
  2916. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2917. return ubwcp_remove_cb_buf(pdev);
  2918. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2919. ERR("unknown device: %s", compatible);
  2920. return -EINVAL;
  2921. }
  2922. static const struct of_device_id ubwcp_dt_match[] = {
  2923. {.compatible = "qcom,ubwcp"},
  2924. {.compatible = "qcom,ubwcp-context-bank-desc"},
  2925. {.compatible = "qcom,ubwcp-context-bank-buf"},
  2926. {}
  2927. };
  2928. struct platform_driver ubwcp_platform_driver = {
  2929. .probe = ubwcp_probe,
  2930. .remove = ubwcp_remove,
  2931. .driver = {
  2932. .name = "qcom,ubwcp",
  2933. .of_match_table = ubwcp_dt_match,
  2934. },
  2935. };
  2936. int ubwcp_init(void)
  2937. {
  2938. int ret = 0;
  2939. DBG("+++++++++++");
  2940. ret = platform_driver_register(&ubwcp_platform_driver);
  2941. if (ret)
  2942. ERR("platform_driver_register() failed: %d", ret);
  2943. return ret;
  2944. }
  2945. void ubwcp_exit(void)
  2946. {
  2947. platform_driver_unregister(&ubwcp_platform_driver);
  2948. DBG("-----------");
  2949. }
  2950. module_init(ubwcp_init);
  2951. module_exit(ubwcp_exit);
  2952. MODULE_LICENSE("GPL");