sde_encoder.c 142 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  43. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  44. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  47. (p) ? (p)->parent->base.id : -1, \
  48. (p) ? (p)->intf_idx - INTF_0 : -1, \
  49. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  50. ##__VA_ARGS__)
  51. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  52. (p) ? (p)->parent->base.id : -1, \
  53. (p) ? (p)->intf_idx - INTF_0 : -1, \
  54. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  55. ##__VA_ARGS__)
  56. #define MISR_BUFF_SIZE 256
  57. #define IDLE_SHORT_TIMEOUT 1
  58. #define EVT_TIME_OUT_SPLIT 2
  59. /* Maximum number of VSYNC wait attempts for RSC state transition */
  60. #define MAX_RSC_WAIT 5
  61. #define TOPOLOGY_DUALPIPE_MERGE_MODE(x) \
  62. (((x) == SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE) || \
  63. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) || \
  64. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC) || \
  65. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
  66. /**
  67. * enum sde_enc_rc_events - events for resource control state machine
  68. * @SDE_ENC_RC_EVENT_KICKOFF:
  69. * This event happens at NORMAL priority.
  70. * Event that signals the start of the transfer. When this event is
  71. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  72. * Regardless of the previous state, the resource should be in ON state
  73. * at the end of this event. At the end of this event, a delayed work is
  74. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  75. * ktime.
  76. * @SDE_ENC_RC_EVENT_PRE_STOP:
  77. * This event happens at NORMAL priority.
  78. * This event, when received during the ON state, set RSC to IDLE, and
  79. * and leave the RC STATE in the PRE_OFF state.
  80. * It should be followed by the STOP event as part of encoder disable.
  81. * If received during IDLE or OFF states, it will do nothing.
  82. * @SDE_ENC_RC_EVENT_STOP:
  83. * This event happens at NORMAL priority.
  84. * When this event is received, disable all the MDP/DSI core clocks, and
  85. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  86. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  87. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  88. * Resource state should be in OFF at the end of the event.
  89. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  90. * This event happens at NORMAL priority from a work item.
  91. * Event signals that there is a seamless mode switch is in prgoress. A
  92. * client needs to turn of only irq - leave clocks ON to reduce the mode
  93. * switch latency.
  94. * @SDE_ENC_RC_EVENT_POST_MODESET:
  95. * This event happens at NORMAL priority from a work item.
  96. * Event signals that seamless mode switch is complete and resources are
  97. * acquired. Clients wants to turn on the irq again and update the rsc
  98. * with new vtotal.
  99. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  100. * This event happens at NORMAL priority from a work item.
  101. * Event signals that there were no frame updates for
  102. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  103. * and request RSC with IDLE state and change the resource state to IDLE.
  104. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  105. * This event is triggered from the input event thread when touch event is
  106. * received from the input device. On receiving this event,
  107. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  108. clocks and enable RSC.
  109. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  110. * off work since a new commit is imminent.
  111. */
  112. enum sde_enc_rc_events {
  113. SDE_ENC_RC_EVENT_KICKOFF = 1,
  114. SDE_ENC_RC_EVENT_PRE_STOP,
  115. SDE_ENC_RC_EVENT_STOP,
  116. SDE_ENC_RC_EVENT_PRE_MODESET,
  117. SDE_ENC_RC_EVENT_POST_MODESET,
  118. SDE_ENC_RC_EVENT_ENTER_IDLE,
  119. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  120. };
  121. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  122. {
  123. struct sde_encoder_virt *sde_enc;
  124. int i;
  125. sde_enc = to_sde_encoder_virt(drm_enc);
  126. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  127. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  128. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  129. SDE_EVT32(DRMID(drm_enc), enable);
  130. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  131. }
  132. }
  133. }
  134. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  135. {
  136. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  137. struct msm_drm_private *priv;
  138. struct sde_kms *sde_kms;
  139. struct device *cpu_dev;
  140. struct cpumask *cpu_mask = NULL;
  141. int cpu = 0;
  142. u32 cpu_dma_latency;
  143. priv = drm_enc->dev->dev_private;
  144. sde_kms = to_sde_kms(priv->kms);
  145. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  146. return;
  147. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  148. cpumask_clear(&sde_enc->valid_cpu_mask);
  149. if (sde_enc->mode_info.frame_rate > FPS60)
  150. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  151. if (!cpu_mask &&
  152. sde_encoder_check_curr_mode(drm_enc,
  153. MSM_DISPLAY_CMD_MODE))
  154. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  155. if (!cpu_mask)
  156. return;
  157. for_each_cpu(cpu, cpu_mask) {
  158. cpu_dev = get_cpu_device(cpu);
  159. if (!cpu_dev) {
  160. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  161. cpu);
  162. return;
  163. }
  164. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  165. dev_pm_qos_add_request(cpu_dev,
  166. &sde_enc->pm_qos_cpu_req[cpu],
  167. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  168. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  169. }
  170. }
  171. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  172. {
  173. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  174. struct device *cpu_dev;
  175. int cpu = 0;
  176. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  177. cpu_dev = get_cpu_device(cpu);
  178. if (!cpu_dev) {
  179. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  180. cpu);
  181. continue;
  182. }
  183. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  184. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  185. }
  186. cpumask_clear(&sde_enc->valid_cpu_mask);
  187. }
  188. static bool _sde_encoder_is_autorefresh_enabled(
  189. struct sde_encoder_virt *sde_enc)
  190. {
  191. struct drm_connector *drm_conn;
  192. if (!sde_enc->cur_master ||
  193. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  194. return false;
  195. drm_conn = sde_enc->cur_master->connector;
  196. if (!drm_conn || !drm_conn->state)
  197. return false;
  198. return sde_connector_get_property(drm_conn->state,
  199. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  200. }
  201. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  202. struct sde_hw_qdss *hw_qdss,
  203. struct sde_encoder_phys *phys, bool enable)
  204. {
  205. if (sde_enc->qdss_status == enable)
  206. return;
  207. sde_enc->qdss_status = enable;
  208. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  209. sde_enc->qdss_status);
  210. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  211. }
  212. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  213. s64 timeout_ms, struct sde_encoder_wait_info *info)
  214. {
  215. int rc = 0;
  216. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  217. ktime_t cur_ktime;
  218. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  219. do {
  220. rc = wait_event_timeout(*(info->wq),
  221. atomic_read(info->atomic_cnt) == info->count_check,
  222. wait_time_jiffies);
  223. cur_ktime = ktime_get();
  224. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  225. timeout_ms, atomic_read(info->atomic_cnt),
  226. info->count_check);
  227. /* If we timed out, counter is valid and time is less, wait again */
  228. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  229. (rc == 0) &&
  230. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  231. return rc;
  232. }
  233. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  234. {
  235. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  236. return sde_enc &&
  237. (sde_enc->disp_info.display_type ==
  238. SDE_CONNECTOR_PRIMARY);
  239. }
  240. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  241. {
  242. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  243. return sde_enc &&
  244. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  245. }
  246. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  247. {
  248. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  249. return sde_enc && sde_enc->cur_master &&
  250. sde_enc->cur_master->cont_splash_enabled;
  251. }
  252. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  253. enum sde_intr_idx intr_idx)
  254. {
  255. SDE_EVT32(DRMID(phys_enc->parent),
  256. phys_enc->intf_idx - INTF_0,
  257. phys_enc->hw_pp->idx - PINGPONG_0,
  258. intr_idx);
  259. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  260. if (phys_enc->parent_ops.handle_frame_done)
  261. phys_enc->parent_ops.handle_frame_done(
  262. phys_enc->parent, phys_enc,
  263. SDE_ENCODER_FRAME_EVENT_ERROR);
  264. }
  265. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  266. enum sde_intr_idx intr_idx,
  267. struct sde_encoder_wait_info *wait_info)
  268. {
  269. struct sde_encoder_irq *irq;
  270. u32 irq_status;
  271. int ret, i;
  272. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  273. SDE_ERROR("invalid params\n");
  274. return -EINVAL;
  275. }
  276. irq = &phys_enc->irq[intr_idx];
  277. /* note: do master / slave checking outside */
  278. /* return EWOULDBLOCK since we know the wait isn't necessary */
  279. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  280. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  281. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  282. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  283. return -EWOULDBLOCK;
  284. }
  285. if (irq->irq_idx < 0) {
  286. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  287. irq->name, irq->hw_idx);
  288. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  289. irq->irq_idx);
  290. return 0;
  291. }
  292. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  293. atomic_read(wait_info->atomic_cnt));
  294. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  295. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  296. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  297. /*
  298. * Some module X may disable interrupt for longer duration
  299. * and it may trigger all interrupts including timer interrupt
  300. * when module X again enable the interrupt.
  301. * That may cause interrupt wait timeout API in this API.
  302. * It is handled by split the wait timer in two halves.
  303. */
  304. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  305. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  306. irq->hw_idx,
  307. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  308. wait_info);
  309. if (ret)
  310. break;
  311. }
  312. if (ret <= 0) {
  313. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  314. irq->irq_idx, true);
  315. if (irq_status) {
  316. unsigned long flags;
  317. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  318. irq->hw_idx, irq->irq_idx,
  319. phys_enc->hw_pp->idx - PINGPONG_0,
  320. atomic_read(wait_info->atomic_cnt));
  321. SDE_DEBUG_PHYS(phys_enc,
  322. "done but irq %d not triggered\n",
  323. irq->irq_idx);
  324. local_irq_save(flags);
  325. irq->cb.func(phys_enc, irq->irq_idx);
  326. local_irq_restore(flags);
  327. ret = 0;
  328. } else {
  329. ret = -ETIMEDOUT;
  330. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  331. irq->hw_idx, irq->irq_idx,
  332. phys_enc->hw_pp->idx - PINGPONG_0,
  333. atomic_read(wait_info->atomic_cnt), irq_status,
  334. SDE_EVTLOG_ERROR);
  335. }
  336. } else {
  337. ret = 0;
  338. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  339. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  340. atomic_read(wait_info->atomic_cnt));
  341. }
  342. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  343. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  344. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  345. return ret;
  346. }
  347. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  348. enum sde_intr_idx intr_idx)
  349. {
  350. struct sde_encoder_irq *irq;
  351. int ret = 0;
  352. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  353. SDE_ERROR("invalid params\n");
  354. return -EINVAL;
  355. }
  356. irq = &phys_enc->irq[intr_idx];
  357. if (irq->irq_idx >= 0) {
  358. SDE_DEBUG_PHYS(phys_enc,
  359. "skipping already registered irq %s type %d\n",
  360. irq->name, irq->intr_type);
  361. return 0;
  362. }
  363. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  364. irq->intr_type, irq->hw_idx);
  365. if (irq->irq_idx < 0) {
  366. SDE_ERROR_PHYS(phys_enc,
  367. "failed to lookup IRQ index for %s type:%d\n",
  368. irq->name, irq->intr_type);
  369. return -EINVAL;
  370. }
  371. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  372. &irq->cb);
  373. if (ret) {
  374. SDE_ERROR_PHYS(phys_enc,
  375. "failed to register IRQ callback for %s\n",
  376. irq->name);
  377. irq->irq_idx = -EINVAL;
  378. return ret;
  379. }
  380. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  381. if (ret) {
  382. SDE_ERROR_PHYS(phys_enc,
  383. "enable IRQ for intr:%s failed, irq_idx %d\n",
  384. irq->name, irq->irq_idx);
  385. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  386. irq->irq_idx, &irq->cb);
  387. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  388. irq->irq_idx, SDE_EVTLOG_ERROR);
  389. irq->irq_idx = -EINVAL;
  390. return ret;
  391. }
  392. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  393. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  394. irq->name, irq->irq_idx);
  395. return ret;
  396. }
  397. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  398. enum sde_intr_idx intr_idx)
  399. {
  400. struct sde_encoder_irq *irq;
  401. int ret;
  402. if (!phys_enc) {
  403. SDE_ERROR("invalid encoder\n");
  404. return -EINVAL;
  405. }
  406. irq = &phys_enc->irq[intr_idx];
  407. /* silently skip irqs that weren't registered */
  408. if (irq->irq_idx < 0) {
  409. SDE_ERROR(
  410. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  411. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  412. irq->irq_idx);
  413. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  414. irq->irq_idx, SDE_EVTLOG_ERROR);
  415. return 0;
  416. }
  417. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  418. if (ret)
  419. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  420. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  421. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  422. &irq->cb);
  423. if (ret)
  424. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  425. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  426. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  427. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  428. irq->irq_idx = -EINVAL;
  429. return 0;
  430. }
  431. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  432. struct sde_encoder_hw_resources *hw_res,
  433. struct drm_connector_state *conn_state)
  434. {
  435. struct sde_encoder_virt *sde_enc = NULL;
  436. struct msm_mode_info mode_info;
  437. int i = 0;
  438. if (!hw_res || !drm_enc || !conn_state) {
  439. SDE_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
  440. !drm_enc, !hw_res, !conn_state);
  441. return;
  442. }
  443. sde_enc = to_sde_encoder_virt(drm_enc);
  444. SDE_DEBUG_ENC(sde_enc, "\n");
  445. /* Query resources used by phys encs, expected to be without overlap */
  446. memset(hw_res, 0, sizeof(*hw_res));
  447. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  448. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  449. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  450. if (phys && phys->ops.get_hw_resources)
  451. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  452. }
  453. /*
  454. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  455. * called from atomic_check phase. Use the below API to get mode
  456. * information of the temporary conn_state passed
  457. */
  458. sde_connector_state_get_mode_info(conn_state, &mode_info);
  459. hw_res->topology = mode_info.topology;
  460. hw_res->comp_info = &sde_enc->mode_info.comp_info;
  461. hw_res->display_type = sde_enc->disp_info.display_type;
  462. }
  463. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  464. {
  465. struct sde_encoder_virt *sde_enc = NULL;
  466. int i = 0;
  467. if (!drm_enc) {
  468. SDE_ERROR("invalid encoder\n");
  469. return;
  470. }
  471. sde_enc = to_sde_encoder_virt(drm_enc);
  472. SDE_DEBUG_ENC(sde_enc, "\n");
  473. mutex_lock(&sde_enc->enc_lock);
  474. sde_rsc_client_destroy(sde_enc->rsc_client);
  475. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  476. struct sde_encoder_phys *phys;
  477. phys = sde_enc->phys_vid_encs[i];
  478. if (phys && phys->ops.destroy) {
  479. phys->ops.destroy(phys);
  480. --sde_enc->num_phys_encs;
  481. sde_enc->phys_encs[i] = NULL;
  482. }
  483. phys = sde_enc->phys_cmd_encs[i];
  484. if (phys && phys->ops.destroy) {
  485. phys->ops.destroy(phys);
  486. --sde_enc->num_phys_encs;
  487. sde_enc->phys_encs[i] = NULL;
  488. }
  489. }
  490. if (sde_enc->num_phys_encs)
  491. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  492. sde_enc->num_phys_encs);
  493. sde_enc->num_phys_encs = 0;
  494. mutex_unlock(&sde_enc->enc_lock);
  495. drm_encoder_cleanup(drm_enc);
  496. mutex_destroy(&sde_enc->enc_lock);
  497. kfree(sde_enc->input_handler);
  498. sde_enc->input_handler = NULL;
  499. kfree(sde_enc);
  500. }
  501. void sde_encoder_helper_update_intf_cfg(
  502. struct sde_encoder_phys *phys_enc)
  503. {
  504. struct sde_encoder_virt *sde_enc;
  505. struct sde_hw_intf_cfg_v1 *intf_cfg;
  506. enum sde_3d_blend_mode mode_3d;
  507. if (!phys_enc || !phys_enc->hw_pp) {
  508. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  509. return;
  510. }
  511. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  512. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  513. SDE_DEBUG_ENC(sde_enc,
  514. "intf_cfg updated for %d at idx %d\n",
  515. phys_enc->intf_idx,
  516. intf_cfg->intf_count);
  517. /* setup interface configuration */
  518. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  519. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  520. return;
  521. }
  522. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  523. if (phys_enc == sde_enc->cur_master) {
  524. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  525. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  526. else
  527. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  528. }
  529. /* configure this interface as master for split display */
  530. if (phys_enc->split_role == ENC_ROLE_MASTER)
  531. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  532. /* setup which pp blk will connect to this intf */
  533. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  534. phys_enc->hw_intf->ops.bind_pingpong_blk(
  535. phys_enc->hw_intf,
  536. true,
  537. phys_enc->hw_pp->idx);
  538. /*setup merge_3d configuration */
  539. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  540. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  541. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  542. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  543. phys_enc->hw_pp->merge_3d->idx;
  544. if (phys_enc->hw_pp->ops.setup_3d_mode)
  545. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  546. mode_3d);
  547. }
  548. void sde_encoder_helper_split_config(
  549. struct sde_encoder_phys *phys_enc,
  550. enum sde_intf interface)
  551. {
  552. struct sde_encoder_virt *sde_enc;
  553. struct split_pipe_cfg *cfg;
  554. struct sde_hw_mdp *hw_mdptop;
  555. enum sde_rm_topology_name topology;
  556. struct msm_display_info *disp_info;
  557. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  558. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  559. return;
  560. }
  561. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  562. hw_mdptop = phys_enc->hw_mdptop;
  563. disp_info = &sde_enc->disp_info;
  564. cfg = &phys_enc->hw_intf->cfg;
  565. memset(cfg, 0, sizeof(*cfg));
  566. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  567. return;
  568. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  569. cfg->split_link_en = true;
  570. /**
  571. * disable split modes since encoder will be operating in as the only
  572. * encoder, either for the entire use case in the case of, for example,
  573. * single DSI, or for this frame in the case of left/right only partial
  574. * update.
  575. */
  576. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  577. if (hw_mdptop->ops.setup_split_pipe)
  578. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  579. if (hw_mdptop->ops.setup_pp_split)
  580. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  581. return;
  582. }
  583. cfg->en = true;
  584. cfg->mode = phys_enc->intf_mode;
  585. cfg->intf = interface;
  586. if (cfg->en && phys_enc->ops.needs_single_flush &&
  587. phys_enc->ops.needs_single_flush(phys_enc))
  588. cfg->split_flush_en = true;
  589. topology = sde_connector_get_topology_name(phys_enc->connector);
  590. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  591. cfg->pp_split_slave = cfg->intf;
  592. else
  593. cfg->pp_split_slave = INTF_MAX;
  594. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  595. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  596. if (hw_mdptop->ops.setup_split_pipe)
  597. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  598. } else if (sde_enc->hw_pp[0]) {
  599. /*
  600. * slave encoder
  601. * - determine split index from master index,
  602. * assume master is first pp
  603. */
  604. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  605. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  606. cfg->pp_split_index);
  607. if (hw_mdptop->ops.setup_pp_split)
  608. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  609. }
  610. }
  611. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  612. {
  613. struct sde_encoder_virt *sde_enc;
  614. int i = 0;
  615. if (!drm_enc)
  616. return false;
  617. sde_enc = to_sde_encoder_virt(drm_enc);
  618. if (!sde_enc)
  619. return false;
  620. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  621. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  622. if (phys && phys->in_clone_mode)
  623. return true;
  624. }
  625. return false;
  626. }
  627. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  628. struct drm_crtc_state *crtc_state,
  629. struct drm_connector_state *conn_state)
  630. {
  631. const struct drm_display_mode *mode;
  632. struct drm_display_mode *adj_mode;
  633. int i = 0;
  634. int ret = 0;
  635. mode = &crtc_state->mode;
  636. adj_mode = &crtc_state->adjusted_mode;
  637. /* perform atomic check on the first physical encoder (master) */
  638. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  639. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  640. if (phys && phys->ops.atomic_check)
  641. ret = phys->ops.atomic_check(phys, crtc_state,
  642. conn_state);
  643. else if (phys && phys->ops.mode_fixup)
  644. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  645. ret = -EINVAL;
  646. if (ret) {
  647. SDE_ERROR_ENC(sde_enc,
  648. "mode unsupported, phys idx %d\n", i);
  649. break;
  650. }
  651. }
  652. return ret;
  653. }
  654. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  655. struct drm_crtc_state *crtc_state,
  656. struct drm_connector_state *conn_state,
  657. struct sde_connector_state *sde_conn_state,
  658. struct sde_crtc_state *sde_crtc_state)
  659. {
  660. int ret = 0;
  661. if (crtc_state->mode_changed || crtc_state->active_changed) {
  662. struct sde_rect mode_roi, roi;
  663. mode_roi.x = 0;
  664. mode_roi.y = 0;
  665. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  666. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  667. if (sde_conn_state->rois.num_rects) {
  668. sde_kms_rect_merge_rectangles(
  669. &sde_conn_state->rois, &roi);
  670. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  671. SDE_ERROR_ENC(sde_enc,
  672. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  673. roi.x, roi.y, roi.w, roi.h);
  674. ret = -EINVAL;
  675. }
  676. }
  677. if (sde_crtc_state->user_roi_list.num_rects) {
  678. sde_kms_rect_merge_rectangles(
  679. &sde_crtc_state->user_roi_list, &roi);
  680. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  681. SDE_ERROR_ENC(sde_enc,
  682. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  683. roi.x, roi.y, roi.w, roi.h);
  684. ret = -EINVAL;
  685. }
  686. }
  687. }
  688. return ret;
  689. }
  690. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  691. struct drm_crtc_state *crtc_state,
  692. struct drm_connector_state *conn_state,
  693. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  694. struct sde_connector *sde_conn,
  695. struct sde_connector_state *sde_conn_state)
  696. {
  697. int ret = 0;
  698. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  699. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  700. struct msm_display_topology *topology = NULL;
  701. ret = sde_connector_get_mode_info(&sde_conn->base,
  702. adj_mode, &sde_conn_state->mode_info);
  703. if (ret) {
  704. SDE_ERROR_ENC(sde_enc,
  705. "failed to get mode info, rc = %d\n", ret);
  706. return ret;
  707. }
  708. if (sde_conn_state->mode_info.comp_info.comp_type &&
  709. sde_conn_state->mode_info.comp_info.comp_ratio >=
  710. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  711. SDE_ERROR_ENC(sde_enc,
  712. "invalid compression ratio: %d\n",
  713. sde_conn_state->mode_info.comp_info.comp_ratio);
  714. ret = -EINVAL;
  715. return ret;
  716. }
  717. /* Reserve dynamic resources, indicating atomic_check phase */
  718. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  719. conn_state, true);
  720. if (ret) {
  721. SDE_ERROR_ENC(sde_enc,
  722. "RM failed to reserve resources, rc = %d\n",
  723. ret);
  724. return ret;
  725. }
  726. /**
  727. * Update connector state with the topology selected for the
  728. * resource set validated. Reset the topology if we are
  729. * de-activating crtc.
  730. */
  731. if (crtc_state->active)
  732. topology = &sde_conn_state->mode_info.topology;
  733. ret = sde_rm_update_topology(conn_state, topology);
  734. if (ret) {
  735. SDE_ERROR_ENC(sde_enc,
  736. "RM failed to update topology, rc: %d\n", ret);
  737. return ret;
  738. }
  739. ret = sde_connector_set_blob_data(conn_state->connector,
  740. conn_state,
  741. CONNECTOR_PROP_SDE_INFO);
  742. if (ret) {
  743. SDE_ERROR_ENC(sde_enc,
  744. "connector failed to update info, rc: %d\n",
  745. ret);
  746. return ret;
  747. }
  748. }
  749. return ret;
  750. }
  751. static int sde_encoder_virt_atomic_check(
  752. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  753. struct drm_connector_state *conn_state)
  754. {
  755. struct sde_encoder_virt *sde_enc;
  756. struct sde_kms *sde_kms;
  757. const struct drm_display_mode *mode;
  758. struct drm_display_mode *adj_mode;
  759. struct sde_connector *sde_conn = NULL;
  760. struct sde_connector_state *sde_conn_state = NULL;
  761. struct sde_crtc_state *sde_crtc_state = NULL;
  762. enum sde_rm_topology_name old_top;
  763. int ret = 0;
  764. if (!drm_enc || !crtc_state || !conn_state) {
  765. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  766. !drm_enc, !crtc_state, !conn_state);
  767. return -EINVAL;
  768. }
  769. sde_enc = to_sde_encoder_virt(drm_enc);
  770. SDE_DEBUG_ENC(sde_enc, "\n");
  771. sde_kms = sde_encoder_get_kms(drm_enc);
  772. if (!sde_kms)
  773. return -EINVAL;
  774. mode = &crtc_state->mode;
  775. adj_mode = &crtc_state->adjusted_mode;
  776. sde_conn = to_sde_connector(conn_state->connector);
  777. sde_conn_state = to_sde_connector_state(conn_state);
  778. sde_crtc_state = to_sde_crtc_state(crtc_state);
  779. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  780. crtc_state->active_changed, crtc_state->connectors_changed);
  781. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  782. conn_state);
  783. if (ret)
  784. return ret;
  785. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  786. conn_state, sde_conn_state, sde_crtc_state);
  787. if (ret)
  788. return ret;
  789. /**
  790. * record topology in previous atomic state to be able to handle
  791. * topology transitions correctly.
  792. */
  793. old_top = sde_connector_get_property(conn_state,
  794. CONNECTOR_PROP_TOPOLOGY_NAME);
  795. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  796. if (ret)
  797. return ret;
  798. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  799. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  800. if (ret)
  801. return ret;
  802. ret = sde_connector_roi_v1_check_roi(conn_state);
  803. if (ret) {
  804. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  805. ret);
  806. return ret;
  807. }
  808. drm_mode_set_crtcinfo(adj_mode, 0);
  809. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  810. return ret;
  811. }
  812. static void _sde_encoder_get_connector_roi(
  813. struct sde_encoder_virt *sde_enc,
  814. struct sde_rect *merged_conn_roi)
  815. {
  816. struct drm_connector *drm_conn;
  817. struct sde_connector_state *c_state;
  818. if (!sde_enc || !merged_conn_roi)
  819. return;
  820. drm_conn = sde_enc->phys_encs[0]->connector;
  821. if (!drm_conn || !drm_conn->state)
  822. return;
  823. c_state = to_sde_connector_state(drm_conn->state);
  824. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  825. }
  826. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  827. {
  828. struct sde_encoder_virt *sde_enc;
  829. struct drm_connector *drm_conn;
  830. struct drm_display_mode *adj_mode;
  831. struct sde_rect roi;
  832. if (!drm_enc) {
  833. SDE_ERROR("invalid encoder parameter\n");
  834. return -EINVAL;
  835. }
  836. sde_enc = to_sde_encoder_virt(drm_enc);
  837. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  838. SDE_ERROR("invalid crtc parameter\n");
  839. return -EINVAL;
  840. }
  841. if (!sde_enc->cur_master) {
  842. SDE_ERROR("invalid cur_master parameter\n");
  843. return -EINVAL;
  844. }
  845. adj_mode = &sde_enc->cur_master->cached_mode;
  846. drm_conn = sde_enc->cur_master->connector;
  847. _sde_encoder_get_connector_roi(sde_enc, &roi);
  848. if (sde_kms_rect_is_null(&roi)) {
  849. roi.w = adj_mode->hdisplay;
  850. roi.h = adj_mode->vdisplay;
  851. }
  852. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  853. sizeof(sde_enc->prv_conn_roi));
  854. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  855. return 0;
  856. }
  857. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  858. u32 vsync_source, bool is_dummy)
  859. {
  860. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  861. struct sde_kms *sde_kms;
  862. struct sde_hw_mdp *hw_mdptop;
  863. struct sde_encoder_virt *sde_enc;
  864. int i;
  865. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  866. if (!sde_enc) {
  867. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  868. return;
  869. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  870. SDE_ERROR("invalid num phys enc %d/%d\n",
  871. sde_enc->num_phys_encs,
  872. (int) ARRAY_SIZE(sde_enc->hw_pp));
  873. return;
  874. }
  875. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  876. if (!sde_kms) {
  877. SDE_ERROR("invalid sde_kms\n");
  878. return;
  879. }
  880. hw_mdptop = sde_kms->hw_mdp;
  881. if (!hw_mdptop) {
  882. SDE_ERROR("invalid mdptop\n");
  883. return;
  884. }
  885. if (hw_mdptop->ops.setup_vsync_source) {
  886. for (i = 0; i < sde_enc->num_phys_encs; i++)
  887. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  888. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  889. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  890. vsync_cfg.vsync_source = vsync_source;
  891. vsync_cfg.is_dummy = is_dummy;
  892. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  893. }
  894. }
  895. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  896. struct msm_display_info *disp_info, bool is_dummy)
  897. {
  898. struct sde_encoder_phys *phys;
  899. int i;
  900. u32 vsync_source;
  901. if (!sde_enc || !disp_info) {
  902. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  903. sde_enc != NULL, disp_info != NULL);
  904. return;
  905. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  906. SDE_ERROR("invalid num phys enc %d/%d\n",
  907. sde_enc->num_phys_encs,
  908. (int) ARRAY_SIZE(sde_enc->hw_pp));
  909. return;
  910. }
  911. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  912. if (is_dummy)
  913. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  914. sde_enc->te_source;
  915. else if (disp_info->is_te_using_watchdog_timer)
  916. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4;
  917. else
  918. vsync_source = sde_enc->te_source;
  919. SDE_EVT32(DRMID(&sde_enc->base), vsync_source, is_dummy,
  920. disp_info->is_te_using_watchdog_timer);
  921. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  922. phys = sde_enc->phys_encs[i];
  923. if (phys && phys->ops.setup_vsync_source)
  924. phys->ops.setup_vsync_source(phys,
  925. vsync_source, is_dummy);
  926. }
  927. }
  928. }
  929. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  930. bool watchdog_te)
  931. {
  932. struct sde_encoder_virt *sde_enc;
  933. struct msm_display_info disp_info;
  934. if (!drm_enc) {
  935. pr_err("invalid drm encoder\n");
  936. return -EINVAL;
  937. }
  938. sde_enc = to_sde_encoder_virt(drm_enc);
  939. sde_encoder_control_te(drm_enc, false);
  940. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  941. disp_info.is_te_using_watchdog_timer = watchdog_te;
  942. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  943. sde_encoder_control_te(drm_enc, true);
  944. return 0;
  945. }
  946. static int _sde_encoder_rsc_client_update_vsync_wait(
  947. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  948. int wait_vblank_crtc_id)
  949. {
  950. int wait_refcount = 0, ret = 0;
  951. int pipe = -1;
  952. int wait_count = 0;
  953. struct drm_crtc *primary_crtc;
  954. struct drm_crtc *crtc;
  955. crtc = sde_enc->crtc;
  956. if (wait_vblank_crtc_id)
  957. wait_refcount =
  958. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  959. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  960. SDE_EVTLOG_FUNC_ENTRY);
  961. if (crtc->base.id != wait_vblank_crtc_id) {
  962. primary_crtc = drm_crtc_find(drm_enc->dev,
  963. NULL, wait_vblank_crtc_id);
  964. if (!primary_crtc) {
  965. SDE_ERROR_ENC(sde_enc,
  966. "failed to find primary crtc id %d\n",
  967. wait_vblank_crtc_id);
  968. return -EINVAL;
  969. }
  970. pipe = drm_crtc_index(primary_crtc);
  971. }
  972. /**
  973. * note: VBLANK is expected to be enabled at this point in
  974. * resource control state machine if on primary CRTC
  975. */
  976. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  977. if (sde_rsc_client_is_state_update_complete(
  978. sde_enc->rsc_client))
  979. break;
  980. if (crtc->base.id == wait_vblank_crtc_id)
  981. ret = sde_encoder_wait_for_event(drm_enc,
  982. MSM_ENC_VBLANK);
  983. else
  984. drm_wait_one_vblank(drm_enc->dev, pipe);
  985. if (ret) {
  986. SDE_ERROR_ENC(sde_enc,
  987. "wait for vblank failed ret:%d\n", ret);
  988. /**
  989. * rsc hardware may hang without vsync. avoid rsc hang
  990. * by generating the vsync from watchdog timer.
  991. */
  992. if (crtc->base.id == wait_vblank_crtc_id)
  993. sde_encoder_helper_switch_vsync(drm_enc, true);
  994. }
  995. }
  996. if (wait_count >= MAX_RSC_WAIT)
  997. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  998. SDE_EVTLOG_ERROR);
  999. if (wait_refcount)
  1000. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1001. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1002. SDE_EVTLOG_FUNC_EXIT);
  1003. return ret;
  1004. }
  1005. static int _sde_encoder_update_rsc_client(
  1006. struct drm_encoder *drm_enc, bool enable)
  1007. {
  1008. struct sde_encoder_virt *sde_enc;
  1009. struct drm_crtc *crtc;
  1010. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1011. struct sde_rsc_cmd_config *rsc_config;
  1012. int ret;
  1013. struct msm_display_info *disp_info;
  1014. struct msm_mode_info *mode_info;
  1015. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1016. u32 qsync_mode = 0, v_front_porch;
  1017. struct drm_display_mode *mode;
  1018. bool is_vid_mode;
  1019. struct drm_encoder *enc;
  1020. if (!drm_enc || !drm_enc->dev) {
  1021. SDE_ERROR("invalid encoder arguments\n");
  1022. return -EINVAL;
  1023. }
  1024. sde_enc = to_sde_encoder_virt(drm_enc);
  1025. mode_info = &sde_enc->mode_info;
  1026. crtc = sde_enc->crtc;
  1027. if (!sde_enc->crtc) {
  1028. SDE_ERROR("invalid crtc parameter\n");
  1029. return -EINVAL;
  1030. }
  1031. disp_info = &sde_enc->disp_info;
  1032. rsc_config = &sde_enc->rsc_config;
  1033. if (!sde_enc->rsc_client) {
  1034. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1035. return 0;
  1036. }
  1037. /**
  1038. * only primary command mode panel without Qsync can request CMD state.
  1039. * all other panels/displays can request for VID state including
  1040. * secondary command mode panel.
  1041. * Clone mode encoder can request CLK STATE only.
  1042. */
  1043. if (sde_enc->cur_master)
  1044. qsync_mode = sde_connector_get_qsync_mode(
  1045. sde_enc->cur_master->connector);
  1046. if (sde_encoder_in_clone_mode(drm_enc) ||
  1047. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1048. (disp_info->display_type && qsync_mode))
  1049. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1050. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1051. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1052. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1053. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1054. drm_for_each_encoder(enc, drm_enc->dev) {
  1055. if (enc->base.id != drm_enc->base.id &&
  1056. sde_encoder_in_cont_splash(enc))
  1057. rsc_state = SDE_RSC_CLK_STATE;
  1058. }
  1059. SDE_EVT32(rsc_state, qsync_mode);
  1060. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1061. MSM_DISPLAY_VIDEO_MODE);
  1062. mode = &sde_enc->crtc->state->mode;
  1063. v_front_porch = mode->vsync_start - mode->vdisplay;
  1064. /* compare specific items and reconfigure the rsc */
  1065. if ((rsc_config->fps != mode_info->frame_rate) ||
  1066. (rsc_config->vtotal != mode_info->vtotal) ||
  1067. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1068. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1069. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1070. rsc_config->fps = mode_info->frame_rate;
  1071. rsc_config->vtotal = mode_info->vtotal;
  1072. /*
  1073. * for video mode, prefill lines should not go beyond vertical
  1074. * front porch for RSCC configuration. This will ensure bw
  1075. * downvotes are not sent within the active region. Additional
  1076. * -1 is to give one line time for rscc mode min_threshold.
  1077. */
  1078. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1079. rsc_config->prefill_lines = v_front_porch - 1;
  1080. else
  1081. rsc_config->prefill_lines = mode_info->prefill_lines;
  1082. rsc_config->jitter_numer = mode_info->jitter_numer;
  1083. rsc_config->jitter_denom = mode_info->jitter_denom;
  1084. sde_enc->rsc_state_init = false;
  1085. }
  1086. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1087. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1088. /* update it only once */
  1089. sde_enc->rsc_state_init = true;
  1090. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1091. rsc_state, rsc_config, crtc->base.id,
  1092. &wait_vblank_crtc_id);
  1093. } else {
  1094. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1095. rsc_state, NULL, crtc->base.id,
  1096. &wait_vblank_crtc_id);
  1097. }
  1098. /**
  1099. * if RSC performed a state change that requires a VBLANK wait, it will
  1100. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1101. *
  1102. * if we are the primary display, we will need to enable and wait
  1103. * locally since we hold the commit thread
  1104. *
  1105. * if we are an external display, we must send a signal to the primary
  1106. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1107. * by the primary panel's VBLANK signals
  1108. */
  1109. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1110. if (ret) {
  1111. SDE_ERROR_ENC(sde_enc,
  1112. "sde rsc client update failed ret:%d\n", ret);
  1113. return ret;
  1114. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1115. return ret;
  1116. }
  1117. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1118. sde_enc, wait_vblank_crtc_id);
  1119. return ret;
  1120. }
  1121. static void _sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1122. {
  1123. struct sde_encoder_virt *sde_enc;
  1124. int i;
  1125. if (!drm_enc) {
  1126. SDE_ERROR("invalid encoder\n");
  1127. return;
  1128. }
  1129. sde_enc = to_sde_encoder_virt(drm_enc);
  1130. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1131. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1132. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1133. if (phys && phys->ops.irq_control)
  1134. phys->ops.irq_control(phys, enable);
  1135. }
  1136. }
  1137. /* keep track of the userspace vblank during modeset */
  1138. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1139. u32 sw_event)
  1140. {
  1141. struct sde_encoder_virt *sde_enc;
  1142. bool enable;
  1143. int i;
  1144. if (!drm_enc) {
  1145. SDE_ERROR("invalid encoder\n");
  1146. return;
  1147. }
  1148. sde_enc = to_sde_encoder_virt(drm_enc);
  1149. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1150. sw_event, sde_enc->vblank_enabled);
  1151. /* nothing to do if vblank not enabled by userspace */
  1152. if (!sde_enc->vblank_enabled)
  1153. return;
  1154. /* disable vblank on pre_modeset */
  1155. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1156. enable = false;
  1157. /* enable vblank on post_modeset */
  1158. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1159. enable = true;
  1160. else
  1161. return;
  1162. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1163. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1164. if (phys && phys->ops.control_vblank_irq)
  1165. phys->ops.control_vblank_irq(phys, enable);
  1166. }
  1167. }
  1168. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1169. {
  1170. struct sde_encoder_virt *sde_enc;
  1171. if (!drm_enc)
  1172. return NULL;
  1173. sde_enc = to_sde_encoder_virt(drm_enc);
  1174. return sde_enc->rsc_client;
  1175. }
  1176. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1177. bool enable)
  1178. {
  1179. struct sde_kms *sde_kms;
  1180. struct sde_encoder_virt *sde_enc;
  1181. int rc;
  1182. sde_enc = to_sde_encoder_virt(drm_enc);
  1183. sde_kms = sde_encoder_get_kms(drm_enc);
  1184. if (!sde_kms)
  1185. return -EINVAL;
  1186. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1187. SDE_EVT32(DRMID(drm_enc), enable);
  1188. if (!sde_enc->cur_master) {
  1189. SDE_ERROR("encoder master not set\n");
  1190. return -EINVAL;
  1191. }
  1192. if (enable) {
  1193. /* enable SDE core clks */
  1194. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1195. if (rc < 0) {
  1196. SDE_ERROR("failed to enable power resource %d\n", rc);
  1197. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1198. return rc;
  1199. }
  1200. sde_enc->elevated_ahb_vote = true;
  1201. /* enable DSI clks */
  1202. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1203. true);
  1204. if (rc) {
  1205. SDE_ERROR("failed to enable clk control %d\n", rc);
  1206. pm_runtime_put_sync(drm_enc->dev->dev);
  1207. return rc;
  1208. }
  1209. /* enable all the irq */
  1210. _sde_encoder_irq_control(drm_enc, true);
  1211. _sde_encoder_pm_qos_add_request(drm_enc);
  1212. } else {
  1213. _sde_encoder_pm_qos_remove_request(drm_enc);
  1214. /* disable all the irq */
  1215. _sde_encoder_irq_control(drm_enc, false);
  1216. /* disable DSI clks */
  1217. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1218. /* disable SDE core clks */
  1219. pm_runtime_put_sync(drm_enc->dev->dev);
  1220. }
  1221. return 0;
  1222. }
  1223. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1224. bool enable, u32 frame_count)
  1225. {
  1226. struct sde_encoder_virt *sde_enc;
  1227. int i;
  1228. if (!drm_enc) {
  1229. SDE_ERROR("invalid encoder\n");
  1230. return;
  1231. }
  1232. sde_enc = to_sde_encoder_virt(drm_enc);
  1233. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1234. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1235. if (!phys || !phys->ops.setup_misr)
  1236. continue;
  1237. phys->ops.setup_misr(phys, enable, frame_count);
  1238. }
  1239. }
  1240. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1241. unsigned int type, unsigned int code, int value)
  1242. {
  1243. struct drm_encoder *drm_enc = NULL;
  1244. struct sde_encoder_virt *sde_enc = NULL;
  1245. struct msm_drm_thread *disp_thread = NULL;
  1246. struct msm_drm_private *priv = NULL;
  1247. if (!handle || !handle->handler || !handle->handler->private) {
  1248. SDE_ERROR("invalid encoder for the input event\n");
  1249. return;
  1250. }
  1251. drm_enc = (struct drm_encoder *)handle->handler->private;
  1252. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1253. SDE_ERROR("invalid parameters\n");
  1254. return;
  1255. }
  1256. priv = drm_enc->dev->dev_private;
  1257. sde_enc = to_sde_encoder_virt(drm_enc);
  1258. if (!sde_enc->crtc || (sde_enc->crtc->index
  1259. >= ARRAY_SIZE(priv->disp_thread))) {
  1260. SDE_DEBUG_ENC(sde_enc,
  1261. "invalid cached CRTC: %d or crtc index: %d\n",
  1262. sde_enc->crtc == NULL,
  1263. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1264. return;
  1265. }
  1266. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1267. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1268. kthread_queue_work(&disp_thread->worker,
  1269. &sde_enc->input_event_work);
  1270. }
  1271. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1272. {
  1273. struct sde_encoder_virt *sde_enc;
  1274. if (!drm_enc) {
  1275. SDE_ERROR("invalid encoder\n");
  1276. return;
  1277. }
  1278. sde_enc = to_sde_encoder_virt(drm_enc);
  1279. /* return early if there is no state change */
  1280. if (sde_enc->idle_pc_enabled == enable)
  1281. return;
  1282. sde_enc->idle_pc_enabled = enable;
  1283. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1284. SDE_EVT32(sde_enc->idle_pc_enabled);
  1285. }
  1286. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1287. u32 sw_event)
  1288. {
  1289. struct drm_encoder *drm_enc = &sde_enc->base;
  1290. struct msm_drm_private *priv;
  1291. unsigned int lp, idle_pc_duration;
  1292. struct msm_drm_thread *disp_thread;
  1293. bool autorefresh_enabled = false;
  1294. autorefresh_enabled = _sde_encoder_is_autorefresh_enabled(sde_enc);
  1295. if (autorefresh_enabled)
  1296. return;
  1297. /* set idle timeout based on master connector's lp value */
  1298. if (sde_enc->cur_master)
  1299. lp = sde_connector_get_lp(
  1300. sde_enc->cur_master->connector);
  1301. else
  1302. lp = SDE_MODE_DPMS_ON;
  1303. if (lp == SDE_MODE_DPMS_LP2)
  1304. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1305. else
  1306. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1307. priv = drm_enc->dev->dev_private;
  1308. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1309. kthread_mod_delayed_work(
  1310. &disp_thread->worker,
  1311. &sde_enc->delayed_off_work,
  1312. msecs_to_jiffies(idle_pc_duration));
  1313. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1314. autorefresh_enabled,
  1315. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1316. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1317. sw_event);
  1318. }
  1319. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1320. u32 sw_event)
  1321. {
  1322. if (kthread_cancel_delayed_work_sync(
  1323. &sde_enc->delayed_off_work))
  1324. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1325. sw_event);
  1326. }
  1327. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1328. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1329. {
  1330. int ret = 0;
  1331. mutex_lock(&sde_enc->rc_lock);
  1332. /* return if the resource control is already in ON state */
  1333. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1334. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1335. sw_event);
  1336. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1337. SDE_EVTLOG_FUNC_CASE1);
  1338. goto end;
  1339. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1340. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1341. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1342. sw_event, sde_enc->rc_state);
  1343. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1344. SDE_EVTLOG_ERROR);
  1345. goto end;
  1346. }
  1347. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1348. _sde_encoder_irq_control(drm_enc, true);
  1349. } else {
  1350. /* enable all the clks and resources */
  1351. ret = _sde_encoder_resource_control_helper(drm_enc,
  1352. true);
  1353. if (ret) {
  1354. SDE_ERROR_ENC(sde_enc,
  1355. "sw_event:%d, rc in state %d\n",
  1356. sw_event, sde_enc->rc_state);
  1357. SDE_EVT32(DRMID(drm_enc), sw_event,
  1358. sde_enc->rc_state,
  1359. SDE_EVTLOG_ERROR);
  1360. goto end;
  1361. }
  1362. _sde_encoder_update_rsc_client(drm_enc, true);
  1363. }
  1364. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1365. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1366. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1367. /* restart delayed off work, if required */
  1368. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1369. end:
  1370. mutex_unlock(&sde_enc->rc_lock);
  1371. return ret;
  1372. }
  1373. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1374. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1375. {
  1376. /* cancel delayed off work, if any */
  1377. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1378. mutex_lock(&sde_enc->rc_lock);
  1379. if (is_vid_mode &&
  1380. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1381. _sde_encoder_irq_control(drm_enc, true);
  1382. }
  1383. /* skip if is already OFF or IDLE, resources are off already */
  1384. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1385. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1386. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1387. sw_event, sde_enc->rc_state);
  1388. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1389. SDE_EVTLOG_FUNC_CASE3);
  1390. goto end;
  1391. }
  1392. /**
  1393. * IRQs are still enabled currently, which allows wait for
  1394. * VBLANK which RSC may require to correctly transition to OFF
  1395. */
  1396. _sde_encoder_update_rsc_client(drm_enc, false);
  1397. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1398. SDE_ENC_RC_STATE_PRE_OFF,
  1399. SDE_EVTLOG_FUNC_CASE3);
  1400. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1401. end:
  1402. mutex_unlock(&sde_enc->rc_lock);
  1403. return 0;
  1404. }
  1405. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1406. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1407. {
  1408. int ret = 0;
  1409. /* cancel vsync event work and timer */
  1410. kthread_cancel_work_sync(&sde_enc->vsync_event_work);
  1411. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI)
  1412. del_timer_sync(&sde_enc->vsync_event_timer);
  1413. mutex_lock(&sde_enc->rc_lock);
  1414. /* return if the resource control is already in OFF state */
  1415. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1416. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1417. sw_event);
  1418. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1419. SDE_EVTLOG_FUNC_CASE4);
  1420. goto end;
  1421. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1422. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1423. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1424. sw_event, sde_enc->rc_state);
  1425. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1426. SDE_EVTLOG_ERROR);
  1427. ret = -EINVAL;
  1428. goto end;
  1429. }
  1430. /**
  1431. * expect to arrive here only if in either idle state or pre-off
  1432. * and in IDLE state the resources are already disabled
  1433. */
  1434. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1435. _sde_encoder_resource_control_helper(drm_enc, false);
  1436. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1437. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1438. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1439. end:
  1440. mutex_unlock(&sde_enc->rc_lock);
  1441. return ret;
  1442. }
  1443. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1444. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1445. {
  1446. int ret = 0;
  1447. /* cancel delayed off work, if any */
  1448. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1449. mutex_lock(&sde_enc->rc_lock);
  1450. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1451. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1452. sw_event);
  1453. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1454. SDE_EVTLOG_FUNC_CASE5);
  1455. goto end;
  1456. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1457. /* enable all the clks and resources */
  1458. ret = _sde_encoder_resource_control_helper(drm_enc,
  1459. true);
  1460. if (ret) {
  1461. SDE_ERROR_ENC(sde_enc,
  1462. "sw_event:%d, rc in state %d\n",
  1463. sw_event, sde_enc->rc_state);
  1464. SDE_EVT32(DRMID(drm_enc), sw_event,
  1465. sde_enc->rc_state,
  1466. SDE_EVTLOG_ERROR);
  1467. goto end;
  1468. }
  1469. _sde_encoder_update_rsc_client(drm_enc, true);
  1470. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1471. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1472. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1473. }
  1474. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  1475. if (ret && ret != -EWOULDBLOCK) {
  1476. SDE_ERROR_ENC(sde_enc,
  1477. "wait for commit done returned %d\n",
  1478. ret);
  1479. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1480. ret, SDE_EVTLOG_ERROR);
  1481. ret = -EINVAL;
  1482. goto end;
  1483. }
  1484. _sde_encoder_irq_control(drm_enc, false);
  1485. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1486. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1487. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1488. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1489. _sde_encoder_pm_qos_remove_request(drm_enc);
  1490. end:
  1491. mutex_unlock(&sde_enc->rc_lock);
  1492. return ret;
  1493. }
  1494. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1495. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1496. {
  1497. int ret = 0;
  1498. mutex_lock(&sde_enc->rc_lock);
  1499. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1500. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1501. sw_event);
  1502. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1503. SDE_EVTLOG_FUNC_CASE5);
  1504. goto end;
  1505. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1506. SDE_ERROR_ENC(sde_enc,
  1507. "sw_event:%d, rc:%d !MODESET state\n",
  1508. sw_event, sde_enc->rc_state);
  1509. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1510. SDE_EVTLOG_ERROR);
  1511. ret = -EINVAL;
  1512. goto end;
  1513. }
  1514. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1515. _sde_encoder_irq_control(drm_enc, true);
  1516. _sde_encoder_update_rsc_client(drm_enc, true);
  1517. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1518. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1519. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1520. _sde_encoder_pm_qos_add_request(drm_enc);
  1521. end:
  1522. mutex_unlock(&sde_enc->rc_lock);
  1523. return ret;
  1524. }
  1525. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1526. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1527. {
  1528. struct msm_drm_private *priv;
  1529. struct sde_kms *sde_kms;
  1530. struct drm_crtc *crtc = drm_enc->crtc;
  1531. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1532. priv = drm_enc->dev->dev_private;
  1533. sde_kms = to_sde_kms(priv->kms);
  1534. mutex_lock(&sde_enc->rc_lock);
  1535. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1536. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1537. sw_event, sde_enc->rc_state);
  1538. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1539. SDE_EVTLOG_ERROR);
  1540. goto end;
  1541. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1542. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1543. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1544. sde_crtc_frame_pending(sde_enc->crtc),
  1545. SDE_EVTLOG_ERROR);
  1546. _sde_encoder_rc_restart_delayed(sde_enc,
  1547. SDE_ENC_RC_EVENT_ENTER_IDLE);
  1548. goto end;
  1549. }
  1550. if (is_vid_mode) {
  1551. _sde_encoder_irq_control(drm_enc, false);
  1552. } else {
  1553. /* disable all the clks and resources */
  1554. _sde_encoder_update_rsc_client(drm_enc, false);
  1555. _sde_encoder_resource_control_helper(drm_enc, false);
  1556. if (!sde_kms->perf.bw_vote_mode)
  1557. memset(&sde_crtc->cur_perf, 0,
  1558. sizeof(struct sde_core_perf_params));
  1559. }
  1560. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1561. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1562. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1563. end:
  1564. mutex_unlock(&sde_enc->rc_lock);
  1565. return 0;
  1566. }
  1567. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1568. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1569. struct msm_drm_private *priv, bool is_vid_mode)
  1570. {
  1571. bool autorefresh_enabled = false;
  1572. struct msm_drm_thread *disp_thread;
  1573. int ret = 0;
  1574. if (!sde_enc->crtc ||
  1575. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1576. SDE_DEBUG_ENC(sde_enc,
  1577. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1578. sde_enc->crtc == NULL,
  1579. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1580. sw_event);
  1581. return -EINVAL;
  1582. }
  1583. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1584. mutex_lock(&sde_enc->rc_lock);
  1585. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1586. if (sde_enc->cur_master &&
  1587. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1588. autorefresh_enabled =
  1589. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1590. sde_enc->cur_master);
  1591. if (autorefresh_enabled) {
  1592. SDE_DEBUG_ENC(sde_enc,
  1593. "not handling early wakeup since auto refresh is enabled\n");
  1594. goto end;
  1595. }
  1596. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1597. kthread_mod_delayed_work(&disp_thread->worker,
  1598. &sde_enc->delayed_off_work,
  1599. msecs_to_jiffies(
  1600. IDLE_POWERCOLLAPSE_DURATION));
  1601. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1602. /* enable all the clks and resources */
  1603. ret = _sde_encoder_resource_control_helper(drm_enc,
  1604. true);
  1605. if (ret) {
  1606. SDE_ERROR_ENC(sde_enc,
  1607. "sw_event:%d, rc in state %d\n",
  1608. sw_event, sde_enc->rc_state);
  1609. SDE_EVT32(DRMID(drm_enc), sw_event,
  1610. sde_enc->rc_state,
  1611. SDE_EVTLOG_ERROR);
  1612. goto end;
  1613. }
  1614. _sde_encoder_update_rsc_client(drm_enc, true);
  1615. /*
  1616. * In some cases, commit comes with slight delay
  1617. * (> 80 ms)after early wake up, prevent clock switch
  1618. * off to avoid jank in next update. So, increase the
  1619. * command mode idle timeout sufficiently to prevent
  1620. * such case.
  1621. */
  1622. kthread_mod_delayed_work(&disp_thread->worker,
  1623. &sde_enc->delayed_off_work,
  1624. msecs_to_jiffies(
  1625. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1626. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1627. }
  1628. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1629. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1630. end:
  1631. mutex_unlock(&sde_enc->rc_lock);
  1632. return ret;
  1633. }
  1634. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1635. u32 sw_event)
  1636. {
  1637. struct sde_encoder_virt *sde_enc;
  1638. struct msm_drm_private *priv;
  1639. int ret = 0;
  1640. bool is_vid_mode = false;
  1641. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1642. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1643. sw_event);
  1644. return -EINVAL;
  1645. }
  1646. sde_enc = to_sde_encoder_virt(drm_enc);
  1647. priv = drm_enc->dev->dev_private;
  1648. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1649. is_vid_mode = true;
  1650. /*
  1651. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1652. * events and return early for other events (ie wb display).
  1653. */
  1654. if (!sde_enc->idle_pc_enabled &&
  1655. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1656. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1657. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1658. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1659. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1660. return 0;
  1661. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1662. sw_event, sde_enc->idle_pc_enabled);
  1663. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1664. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1665. switch (sw_event) {
  1666. case SDE_ENC_RC_EVENT_KICKOFF:
  1667. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1668. is_vid_mode);
  1669. break;
  1670. case SDE_ENC_RC_EVENT_PRE_STOP:
  1671. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1672. is_vid_mode);
  1673. break;
  1674. case SDE_ENC_RC_EVENT_STOP:
  1675. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1676. break;
  1677. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1678. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1679. break;
  1680. case SDE_ENC_RC_EVENT_POST_MODESET:
  1681. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1682. break;
  1683. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1684. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1685. is_vid_mode);
  1686. break;
  1687. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1688. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1689. priv, is_vid_mode);
  1690. break;
  1691. default:
  1692. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1693. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1694. break;
  1695. }
  1696. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1697. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1698. return ret;
  1699. }
  1700. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1701. enum sde_intf_mode intf_mode, struct drm_display_mode *adj_mode)
  1702. {
  1703. int i = 0;
  1704. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1705. if (intf_mode == INTF_MODE_CMD)
  1706. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1707. else if (intf_mode == INTF_MODE_VIDEO)
  1708. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1709. _sde_encoder_update_rsc_client(drm_enc, true);
  1710. if (intf_mode == INTF_MODE_CMD) {
  1711. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1712. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1713. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1714. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1715. msm_is_mode_seamless_poms(adj_mode),
  1716. SDE_EVTLOG_FUNC_CASE1);
  1717. } else if (intf_mode == INTF_MODE_VIDEO) {
  1718. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1719. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1720. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1721. msm_is_mode_seamless_poms(adj_mode),
  1722. SDE_EVTLOG_FUNC_CASE2);
  1723. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1724. }
  1725. }
  1726. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  1727. struct drm_display_mode *mode,
  1728. struct drm_display_mode *adj_mode)
  1729. {
  1730. struct sde_encoder_virt *sde_enc;
  1731. struct sde_kms *sde_kms;
  1732. struct drm_connector_list_iter conn_iter;
  1733. struct drm_connector *conn = NULL, *conn_search;
  1734. struct sde_rm_hw_iter dsc_iter, pp_iter, qdss_iter;
  1735. struct sde_rm_hw_iter vdc_iter;
  1736. struct sde_rm_hw_request request_hw;
  1737. enum sde_intf_mode intf_mode;
  1738. bool is_cmd_mode = false;
  1739. int i = 0, ret;
  1740. if (!drm_enc) {
  1741. SDE_ERROR("invalid encoder\n");
  1742. return;
  1743. }
  1744. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  1745. SDE_ERROR("power resource is not enabled\n");
  1746. return;
  1747. }
  1748. sde_enc = to_sde_encoder_virt(drm_enc);
  1749. SDE_DEBUG_ENC(sde_enc, "\n");
  1750. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1751. is_cmd_mode = true;
  1752. sde_kms = sde_encoder_get_kms(drm_enc);
  1753. if (!sde_kms)
  1754. return;
  1755. SDE_EVT32(DRMID(drm_enc));
  1756. /*
  1757. * cache the crtc in sde_enc on enable for duration of use case
  1758. * for correctly servicing asynchronous irq events and timers
  1759. */
  1760. if (!drm_enc->crtc) {
  1761. SDE_ERROR("invalid crtc\n");
  1762. return;
  1763. }
  1764. sde_enc->crtc = drm_enc->crtc;
  1765. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  1766. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1767. if (conn_search->encoder == drm_enc) {
  1768. conn = conn_search;
  1769. break;
  1770. }
  1771. }
  1772. drm_connector_list_iter_end(&conn_iter);
  1773. if (!conn) {
  1774. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  1775. return;
  1776. } else if (!conn->state) {
  1777. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  1778. return;
  1779. }
  1780. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  1781. /* store the mode_info */
  1782. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  1783. /* release resources before seamless mode change */
  1784. if (msm_is_mode_seamless_dms(adj_mode) ||
  1785. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1786. is_cmd_mode)) {
  1787. /* restore resource state before releasing them */
  1788. ret = sde_encoder_resource_control(drm_enc,
  1789. SDE_ENC_RC_EVENT_PRE_MODESET);
  1790. if (ret) {
  1791. SDE_ERROR_ENC(sde_enc,
  1792. "sde resource control failed: %d\n",
  1793. ret);
  1794. return;
  1795. }
  1796. /*
  1797. * Disable dce before switch the mode and after pre_modeset,
  1798. * to guarantee that previous kickoff finished.
  1799. */
  1800. sde_encoder_dce_disable(sde_enc);
  1801. } else if (msm_is_mode_seamless_poms(adj_mode)) {
  1802. _sde_encoder_modeset_helper_locked(drm_enc,
  1803. SDE_ENC_RC_EVENT_PRE_MODESET);
  1804. sde_encoder_virt_mode_switch(drm_enc, intf_mode, adj_mode);
  1805. }
  1806. /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
  1807. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  1808. conn->state, false);
  1809. if (ret) {
  1810. SDE_ERROR_ENC(sde_enc,
  1811. "failed to reserve hw resources, %d\n", ret);
  1812. return;
  1813. }
  1814. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1815. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1816. sde_enc->hw_pp[i] = NULL;
  1817. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1818. break;
  1819. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1820. }
  1821. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1822. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1823. if (phys) {
  1824. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1825. SDE_HW_BLK_QDSS);
  1826. for (i = 0; i < QDSS_MAX; i++) {
  1827. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1828. phys->hw_qdss =
  1829. (struct sde_hw_qdss *)qdss_iter.hw;
  1830. break;
  1831. }
  1832. }
  1833. }
  1834. }
  1835. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1836. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1837. sde_enc->hw_dsc[i] = NULL;
  1838. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1839. break;
  1840. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1841. }
  1842. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  1843. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1844. sde_enc->hw_vdc[i] = NULL;
  1845. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  1846. break;
  1847. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  1848. }
  1849. /* Get PP for DSC configuration */
  1850. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1851. struct sde_hw_pingpong *pp = NULL;
  1852. unsigned long features = 0;
  1853. if (!sde_enc->hw_dsc[i])
  1854. continue;
  1855. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1856. request_hw.type = SDE_HW_BLK_PINGPONG;
  1857. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1858. break;
  1859. pp = (struct sde_hw_pingpong *) request_hw.hw;
  1860. features = pp->ops.get_hw_caps(pp);
  1861. if (test_bit(SDE_PINGPONG_DSC, &features))
  1862. sde_enc->hw_dsc_pp[i] = pp;
  1863. else
  1864. sde_enc->hw_dsc_pp[i] = NULL;
  1865. }
  1866. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1867. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1868. if (phys) {
  1869. if (!sde_enc->hw_pp[i] && sde_enc->topology.num_intf) {
  1870. SDE_ERROR_ENC(sde_enc,
  1871. "invalid pingpong block for the encoder\n");
  1872. return;
  1873. }
  1874. phys->hw_pp = sde_enc->hw_pp[i];
  1875. phys->connector = conn->state->connector;
  1876. if (phys->ops.mode_set)
  1877. phys->ops.mode_set(phys, mode, adj_mode);
  1878. }
  1879. }
  1880. /* update resources after seamless mode change */
  1881. if (msm_is_mode_seamless_dms(adj_mode) ||
  1882. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1883. is_cmd_mode))
  1884. sde_encoder_resource_control(&sde_enc->base,
  1885. SDE_ENC_RC_EVENT_POST_MODESET);
  1886. else if (msm_is_mode_seamless_poms(adj_mode))
  1887. _sde_encoder_modeset_helper_locked(drm_enc,
  1888. SDE_ENC_RC_EVENT_POST_MODESET);
  1889. }
  1890. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  1891. {
  1892. struct sde_encoder_virt *sde_enc;
  1893. struct sde_encoder_phys *phys;
  1894. int i;
  1895. if (!drm_enc) {
  1896. SDE_ERROR("invalid parameters\n");
  1897. return;
  1898. }
  1899. sde_enc = to_sde_encoder_virt(drm_enc);
  1900. if (!sde_enc) {
  1901. SDE_ERROR("invalid sde encoder\n");
  1902. return;
  1903. }
  1904. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1905. phys = sde_enc->phys_encs[i];
  1906. if (phys && phys->ops.control_te)
  1907. phys->ops.control_te(phys, enable);
  1908. }
  1909. }
  1910. static int _sde_encoder_input_connect(struct input_handler *handler,
  1911. struct input_dev *dev, const struct input_device_id *id)
  1912. {
  1913. struct input_handle *handle;
  1914. int rc = 0;
  1915. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1916. if (!handle)
  1917. return -ENOMEM;
  1918. handle->dev = dev;
  1919. handle->handler = handler;
  1920. handle->name = handler->name;
  1921. rc = input_register_handle(handle);
  1922. if (rc) {
  1923. pr_err("failed to register input handle\n");
  1924. goto error;
  1925. }
  1926. rc = input_open_device(handle);
  1927. if (rc) {
  1928. pr_err("failed to open input device\n");
  1929. goto error_unregister;
  1930. }
  1931. return 0;
  1932. error_unregister:
  1933. input_unregister_handle(handle);
  1934. error:
  1935. kfree(handle);
  1936. return rc;
  1937. }
  1938. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  1939. {
  1940. input_close_device(handle);
  1941. input_unregister_handle(handle);
  1942. kfree(handle);
  1943. }
  1944. /**
  1945. * Structure for specifying event parameters on which to receive callbacks.
  1946. * This structure will trigger a callback in case of a touch event (specified by
  1947. * EV_ABS) where there is a change in X and Y coordinates,
  1948. */
  1949. static const struct input_device_id sde_input_ids[] = {
  1950. {
  1951. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  1952. .evbit = { BIT_MASK(EV_ABS) },
  1953. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  1954. BIT_MASK(ABS_MT_POSITION_X) |
  1955. BIT_MASK(ABS_MT_POSITION_Y) },
  1956. },
  1957. { },
  1958. };
  1959. static void _sde_encoder_input_handler_register(
  1960. struct drm_encoder *drm_enc)
  1961. {
  1962. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1963. int rc;
  1964. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1965. return;
  1966. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  1967. sde_enc->input_handler->private = sde_enc;
  1968. /* register input handler if not already registered */
  1969. rc = input_register_handler(sde_enc->input_handler);
  1970. if (rc) {
  1971. SDE_ERROR("input_handler_register failed, rc= %d\n",
  1972. rc);
  1973. kfree(sde_enc->input_handler);
  1974. }
  1975. }
  1976. }
  1977. static void _sde_encoder_input_handler_unregister(
  1978. struct drm_encoder *drm_enc)
  1979. {
  1980. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1981. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1982. return;
  1983. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  1984. input_unregister_handler(sde_enc->input_handler);
  1985. sde_enc->input_handler->private = NULL;
  1986. }
  1987. }
  1988. static int _sde_encoder_input_handler(
  1989. struct sde_encoder_virt *sde_enc)
  1990. {
  1991. struct input_handler *input_handler = NULL;
  1992. int rc = 0;
  1993. if (sde_enc->input_handler) {
  1994. SDE_ERROR_ENC(sde_enc,
  1995. "input_handle is active. unexpected\n");
  1996. return -EINVAL;
  1997. }
  1998. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  1999. if (!input_handler)
  2000. return -ENOMEM;
  2001. input_handler->event = sde_encoder_input_event_handler;
  2002. input_handler->connect = _sde_encoder_input_connect;
  2003. input_handler->disconnect = _sde_encoder_input_disconnect;
  2004. input_handler->name = "sde";
  2005. input_handler->id_table = sde_input_ids;
  2006. sde_enc->input_handler = input_handler;
  2007. return rc;
  2008. }
  2009. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2010. {
  2011. struct sde_encoder_virt *sde_enc = NULL;
  2012. struct sde_kms *sde_kms;
  2013. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2014. SDE_ERROR("invalid parameters\n");
  2015. return;
  2016. }
  2017. sde_kms = sde_encoder_get_kms(drm_enc);
  2018. if (!sde_kms)
  2019. return;
  2020. sde_enc = to_sde_encoder_virt(drm_enc);
  2021. if (!sde_enc || !sde_enc->cur_master) {
  2022. SDE_DEBUG("invalid sde encoder/master\n");
  2023. return;
  2024. }
  2025. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2026. sde_enc->cur_master->hw_mdptop &&
  2027. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2028. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2029. sde_enc->cur_master->hw_mdptop);
  2030. if (sde_enc->cur_master->hw_mdptop &&
  2031. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  2032. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2033. sde_enc->cur_master->hw_mdptop,
  2034. sde_kms->catalog);
  2035. if (sde_enc->cur_master->hw_ctl &&
  2036. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2037. !sde_enc->cur_master->cont_splash_enabled)
  2038. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2039. sde_enc->cur_master->hw_ctl,
  2040. &sde_enc->cur_master->intf_cfg_v1);
  2041. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  2042. sde_encoder_control_te(drm_enc, true);
  2043. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2044. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2045. }
  2046. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2047. {
  2048. void *dither_cfg = NULL;
  2049. int ret = 0, i = 0;
  2050. size_t len = 0;
  2051. enum sde_rm_topology_name topology;
  2052. struct drm_encoder *drm_enc;
  2053. struct msm_display_dsc_info *dsc = NULL;
  2054. struct sde_encoder_virt *sde_enc;
  2055. struct sde_hw_pingpong *hw_pp;
  2056. u32 bpp, bpc;
  2057. if (!phys || !phys->connector || !phys->hw_pp ||
  2058. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2059. return;
  2060. topology = sde_connector_get_topology_name(phys->connector);
  2061. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2062. (phys->split_role == ENC_ROLE_SLAVE))
  2063. return;
  2064. drm_enc = phys->parent;
  2065. sde_enc = to_sde_encoder_virt(drm_enc);
  2066. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2067. bpc = dsc->config.bits_per_component;
  2068. bpp = dsc->config.bits_per_pixel;
  2069. /* disable dither for 10 bpp or 10bpc dsc config */
  2070. if (bpp == 10 || bpc == 10) {
  2071. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2072. return;
  2073. }
  2074. ret = sde_connector_get_dither_cfg(phys->connector,
  2075. phys->connector->state, &dither_cfg,
  2076. &len, sde_enc->idle_pc_restore);
  2077. /* skip reg writes when return values are invalid or no data */
  2078. if (ret && ret == -ENODATA)
  2079. return;
  2080. if (TOPOLOGY_DUALPIPE_MERGE_MODE(topology)) {
  2081. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2082. hw_pp = sde_enc->hw_pp[i];
  2083. phys->hw_pp->ops.setup_dither(hw_pp,
  2084. dither_cfg, len);
  2085. }
  2086. } else {
  2087. phys->hw_pp->ops.setup_dither(phys->hw_pp,
  2088. dither_cfg, len);
  2089. }
  2090. }
  2091. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2092. {
  2093. struct sde_encoder_virt *sde_enc = NULL;
  2094. int i;
  2095. if (!drm_enc) {
  2096. SDE_ERROR("invalid encoder\n");
  2097. return;
  2098. }
  2099. sde_enc = to_sde_encoder_virt(drm_enc);
  2100. if (!sde_enc->cur_master) {
  2101. SDE_DEBUG("virt encoder has no master\n");
  2102. return;
  2103. }
  2104. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2105. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2106. sde_enc->idle_pc_restore = true;
  2107. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2108. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2109. if (!phys)
  2110. continue;
  2111. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2112. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2113. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2114. phys->ops.restore(phys);
  2115. _sde_encoder_setup_dither(phys);
  2116. }
  2117. if (sde_enc->cur_master->ops.restore)
  2118. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2119. _sde_encoder_virt_enable_helper(drm_enc);
  2120. }
  2121. static void sde_encoder_off_work(struct kthread_work *work)
  2122. {
  2123. struct sde_encoder_virt *sde_enc = container_of(work,
  2124. struct sde_encoder_virt, delayed_off_work.work);
  2125. struct drm_encoder *drm_enc;
  2126. if (!sde_enc) {
  2127. SDE_ERROR("invalid sde encoder\n");
  2128. return;
  2129. }
  2130. drm_enc = &sde_enc->base;
  2131. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2132. sde_encoder_idle_request(drm_enc);
  2133. SDE_ATRACE_END("sde_encoder_off_work");
  2134. }
  2135. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2136. {
  2137. struct sde_encoder_virt *sde_enc = NULL;
  2138. int i, ret = 0;
  2139. struct msm_compression_info *comp_info = NULL;
  2140. struct drm_display_mode *cur_mode = NULL;
  2141. struct msm_display_info *disp_info;
  2142. if (!drm_enc) {
  2143. SDE_ERROR("invalid encoder\n");
  2144. return;
  2145. }
  2146. sde_enc = to_sde_encoder_virt(drm_enc);
  2147. disp_info = &sde_enc->disp_info;
  2148. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2149. SDE_ERROR("power resource is not enabled\n");
  2150. return;
  2151. }
  2152. if (drm_enc->crtc && !sde_enc->crtc)
  2153. sde_enc->crtc = drm_enc->crtc;
  2154. comp_info = &sde_enc->mode_info.comp_info;
  2155. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2156. SDE_DEBUG_ENC(sde_enc, "\n");
  2157. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2158. sde_enc->cur_master = NULL;
  2159. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2160. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2161. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2162. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2163. sde_enc->cur_master = phys;
  2164. break;
  2165. }
  2166. }
  2167. if (!sde_enc->cur_master) {
  2168. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2169. return;
  2170. }
  2171. _sde_encoder_input_handler_register(drm_enc);
  2172. if (!(msm_is_mode_seamless_vrr(cur_mode)
  2173. || msm_is_mode_seamless_dms(cur_mode)
  2174. || msm_is_mode_seamless_dyn_clk(cur_mode)))
  2175. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2176. sde_encoder_off_work);
  2177. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2178. if (ret) {
  2179. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2180. ret);
  2181. return;
  2182. }
  2183. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2184. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2185. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2186. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2187. if (!phys)
  2188. continue;
  2189. phys->comp_type = comp_info->comp_type;
  2190. phys->comp_ratio = comp_info->comp_ratio;
  2191. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2192. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2193. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2194. phys->dsc_extra_pclk_cycle_cnt =
  2195. comp_info->dsc_info.pclk_per_line;
  2196. phys->dsc_extra_disp_width =
  2197. comp_info->dsc_info.extra_width;
  2198. phys->dce_bytes_per_line =
  2199. comp_info->dsc_info.bytes_per_pkt *
  2200. comp_info->dsc_info.pkt_per_line;
  2201. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2202. phys->dce_bytes_per_line =
  2203. comp_info->vdc_info.bytes_per_pkt *
  2204. comp_info->vdc_info.pkt_per_line;
  2205. }
  2206. if (phys != sde_enc->cur_master) {
  2207. /**
  2208. * on DMS request, the encoder will be enabled
  2209. * already. Invoke restore to reconfigure the
  2210. * new mode.
  2211. */
  2212. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2213. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2214. phys->ops.restore)
  2215. phys->ops.restore(phys);
  2216. else if (phys->ops.enable)
  2217. phys->ops.enable(phys);
  2218. }
  2219. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2220. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2221. phys->ops.setup_misr(phys, true,
  2222. sde_enc->misr_frame_count);
  2223. }
  2224. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2225. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2226. sde_enc->cur_master->ops.restore)
  2227. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2228. else if (sde_enc->cur_master->ops.enable)
  2229. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2230. _sde_encoder_virt_enable_helper(drm_enc);
  2231. }
  2232. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2233. {
  2234. struct sde_encoder_virt *sde_enc = NULL;
  2235. struct sde_kms *sde_kms;
  2236. enum sde_intf_mode intf_mode;
  2237. int i = 0;
  2238. if (!drm_enc) {
  2239. SDE_ERROR("invalid encoder\n");
  2240. return;
  2241. } else if (!drm_enc->dev) {
  2242. SDE_ERROR("invalid dev\n");
  2243. return;
  2244. } else if (!drm_enc->dev->dev_private) {
  2245. SDE_ERROR("invalid dev_private\n");
  2246. return;
  2247. }
  2248. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2249. SDE_ERROR("power resource is not enabled\n");
  2250. return;
  2251. }
  2252. sde_enc = to_sde_encoder_virt(drm_enc);
  2253. SDE_DEBUG_ENC(sde_enc, "\n");
  2254. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2255. if (!sde_kms)
  2256. return;
  2257. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2258. SDE_EVT32(DRMID(drm_enc));
  2259. /* wait for idle */
  2260. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2261. _sde_encoder_input_handler_unregister(drm_enc);
  2262. /*
  2263. * For primary command mode and video mode encoders, execute the
  2264. * resource control pre-stop operations before the physical encoders
  2265. * are disabled, to allow the rsc to transition its states properly.
  2266. *
  2267. * For other encoder types, rsc should not be enabled until after
  2268. * they have been fully disabled, so delay the pre-stop operations
  2269. * until after the physical disable calls have returned.
  2270. */
  2271. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2272. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2273. sde_encoder_resource_control(drm_enc,
  2274. SDE_ENC_RC_EVENT_PRE_STOP);
  2275. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2276. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2277. if (phys && phys->ops.disable)
  2278. phys->ops.disable(phys);
  2279. }
  2280. } else {
  2281. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2282. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2283. if (phys && phys->ops.disable)
  2284. phys->ops.disable(phys);
  2285. }
  2286. sde_encoder_resource_control(drm_enc,
  2287. SDE_ENC_RC_EVENT_PRE_STOP);
  2288. }
  2289. /*
  2290. * disable dce after the transfer is complete (for command mode)
  2291. * and after physical encoder is disabled, to make sure timing
  2292. * engine is already disabled (for video mode).
  2293. */
  2294. sde_encoder_dce_disable(sde_enc);
  2295. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2296. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2297. if (sde_enc->phys_encs[i]) {
  2298. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2299. sde_enc->phys_encs[i]->connector = NULL;
  2300. }
  2301. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2302. }
  2303. sde_enc->cur_master = NULL;
  2304. /*
  2305. * clear the cached crtc in sde_enc on use case finish, after all the
  2306. * outstanding events and timers have been completed
  2307. */
  2308. sde_enc->crtc = NULL;
  2309. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2310. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2311. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2312. }
  2313. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2314. struct sde_encoder_phys_wb *wb_enc)
  2315. {
  2316. struct sde_encoder_virt *sde_enc;
  2317. phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
  2318. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2319. if (wb_enc) {
  2320. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2321. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2322. false, phys_enc->hw_pp->idx);
  2323. if (phys_enc->hw_ctl->ops.update_bitmask)
  2324. phys_enc->hw_ctl->ops.update_bitmask(
  2325. phys_enc->hw_ctl,
  2326. SDE_HW_FLUSH_WB,
  2327. wb_enc->hw_wb->idx, true);
  2328. }
  2329. } else {
  2330. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2331. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2332. phys_enc->hw_intf, false,
  2333. phys_enc->hw_pp->idx);
  2334. if (phys_enc->hw_ctl->ops.update_bitmask)
  2335. phys_enc->hw_ctl->ops.update_bitmask(
  2336. phys_enc->hw_ctl,
  2337. SDE_HW_FLUSH_INTF,
  2338. phys_enc->hw_intf->idx, true);
  2339. }
  2340. }
  2341. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2342. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2343. if (phys_enc->hw_ctl->ops.update_bitmask &&
  2344. phys_enc->hw_pp->merge_3d)
  2345. phys_enc->hw_ctl->ops.update_bitmask(
  2346. phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  2347. phys_enc->hw_pp->merge_3d->idx, true);
  2348. }
  2349. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2350. phys_enc->hw_pp) {
  2351. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2352. false, phys_enc->hw_pp->idx);
  2353. if (phys_enc->hw_ctl->ops.update_bitmask)
  2354. phys_enc->hw_ctl->ops.update_bitmask(
  2355. phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,
  2356. phys_enc->hw_cdm->idx, true);
  2357. }
  2358. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2359. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2360. phys_enc->hw_ctl->ops.reset_post_disable)
  2361. phys_enc->hw_ctl->ops.reset_post_disable(
  2362. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2363. phys_enc->hw_pp->merge_3d ?
  2364. phys_enc->hw_pp->merge_3d->idx : 0);
  2365. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2366. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2367. }
  2368. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2369. enum sde_intf_type type, u32 controller_id)
  2370. {
  2371. int i = 0;
  2372. for (i = 0; i < catalog->intf_count; i++) {
  2373. if (catalog->intf[i].type == type
  2374. && catalog->intf[i].controller_id == controller_id) {
  2375. return catalog->intf[i].id;
  2376. }
  2377. }
  2378. return INTF_MAX;
  2379. }
  2380. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2381. enum sde_intf_type type, u32 controller_id)
  2382. {
  2383. if (controller_id < catalog->wb_count)
  2384. return catalog->wb[controller_id].id;
  2385. return WB_MAX;
  2386. }
  2387. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2388. struct drm_crtc *crtc)
  2389. {
  2390. struct sde_hw_uidle *uidle;
  2391. struct sde_uidle_cntr cntr;
  2392. struct sde_uidle_status status;
  2393. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2394. pr_err("invalid params %d %d\n",
  2395. !sde_kms, !crtc);
  2396. return;
  2397. }
  2398. /* check if perf counters are enabled and setup */
  2399. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2400. return;
  2401. uidle = sde_kms->hw_uidle;
  2402. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2403. && uidle->ops.uidle_get_status) {
  2404. uidle->ops.uidle_get_status(uidle, &status);
  2405. trace_sde_perf_uidle_status(
  2406. crtc->base.id,
  2407. status.uidle_danger_status_0,
  2408. status.uidle_danger_status_1,
  2409. status.uidle_safe_status_0,
  2410. status.uidle_safe_status_1,
  2411. status.uidle_idle_status_0,
  2412. status.uidle_idle_status_1,
  2413. status.uidle_fal_status_0,
  2414. status.uidle_fal_status_1,
  2415. status.uidle_status,
  2416. status.uidle_en_fal10);
  2417. }
  2418. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2419. && uidle->ops.uidle_get_cntr) {
  2420. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2421. trace_sde_perf_uidle_cntr(
  2422. crtc->base.id,
  2423. cntr.fal1_gate_cntr,
  2424. cntr.fal10_gate_cntr,
  2425. cntr.fal_wait_gate_cntr,
  2426. cntr.fal1_num_transitions_cntr,
  2427. cntr.fal10_num_transitions_cntr,
  2428. cntr.min_gate_cntr,
  2429. cntr.max_gate_cntr);
  2430. }
  2431. }
  2432. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2433. struct sde_encoder_phys *phy_enc)
  2434. {
  2435. struct sde_encoder_virt *sde_enc = NULL;
  2436. unsigned long lock_flags;
  2437. if (!drm_enc || !phy_enc)
  2438. return;
  2439. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2440. sde_enc = to_sde_encoder_virt(drm_enc);
  2441. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2442. if (sde_enc->crtc_vblank_cb)
  2443. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2444. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2445. if (phy_enc->sde_kms &&
  2446. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2447. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2448. atomic_inc(&phy_enc->vsync_cnt);
  2449. SDE_ATRACE_END("encoder_vblank_callback");
  2450. }
  2451. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2452. struct sde_encoder_phys *phy_enc)
  2453. {
  2454. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2455. if (!phy_enc)
  2456. return;
  2457. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2458. atomic_inc(&phy_enc->underrun_cnt);
  2459. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2460. if (sde_enc->cur_master->ops.get_underrun_line_count)
  2461. sde_enc->cur_master->ops.get_underrun_line_count(
  2462. sde_enc->cur_master);
  2463. trace_sde_encoder_underrun(DRMID(drm_enc),
  2464. atomic_read(&phy_enc->underrun_cnt));
  2465. SDE_DBG_CTRL("stop_ftrace");
  2466. SDE_DBG_CTRL("panic_underrun");
  2467. SDE_ATRACE_END("encoder_underrun_callback");
  2468. }
  2469. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2470. void (*vbl_cb)(void *), void *vbl_data)
  2471. {
  2472. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2473. unsigned long lock_flags;
  2474. bool enable;
  2475. int i;
  2476. enable = vbl_cb ? true : false;
  2477. if (!drm_enc) {
  2478. SDE_ERROR("invalid encoder\n");
  2479. return;
  2480. }
  2481. SDE_DEBUG_ENC(sde_enc, "\n");
  2482. SDE_EVT32(DRMID(drm_enc), enable);
  2483. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2484. sde_enc->crtc_vblank_cb = vbl_cb;
  2485. sde_enc->crtc_vblank_cb_data = vbl_data;
  2486. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2487. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2488. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2489. if (phys && phys->ops.control_vblank_irq)
  2490. phys->ops.control_vblank_irq(phys, enable);
  2491. }
  2492. sde_enc->vblank_enabled = enable;
  2493. }
  2494. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2495. void (*frame_event_cb)(void *, u32 event),
  2496. struct drm_crtc *crtc)
  2497. {
  2498. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2499. unsigned long lock_flags;
  2500. bool enable;
  2501. enable = frame_event_cb ? true : false;
  2502. if (!drm_enc) {
  2503. SDE_ERROR("invalid encoder\n");
  2504. return;
  2505. }
  2506. SDE_DEBUG_ENC(sde_enc, "\n");
  2507. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2508. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2509. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2510. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2511. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2512. }
  2513. static void sde_encoder_frame_done_callback(
  2514. struct drm_encoder *drm_enc,
  2515. struct sde_encoder_phys *ready_phys, u32 event)
  2516. {
  2517. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2518. unsigned int i;
  2519. bool trigger = true;
  2520. bool is_cmd_mode = false;
  2521. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2522. if (!drm_enc || !sde_enc->cur_master) {
  2523. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2524. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2525. return;
  2526. }
  2527. sde_enc->crtc_frame_event_cb_data.connector =
  2528. sde_enc->cur_master->connector;
  2529. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2530. is_cmd_mode = true;
  2531. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2532. | SDE_ENCODER_FRAME_EVENT_ERROR
  2533. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2534. if (ready_phys->connector)
  2535. topology = sde_connector_get_topology_name(
  2536. ready_phys->connector);
  2537. /* One of the physical encoders has become idle */
  2538. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2539. if (sde_enc->phys_encs[i] == ready_phys) {
  2540. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2541. atomic_read(&sde_enc->frame_done_cnt[i]));
  2542. if (!atomic_add_unless(
  2543. &sde_enc->frame_done_cnt[i], 1, 1)) {
  2544. SDE_EVT32(DRMID(drm_enc), event,
  2545. ready_phys->intf_idx,
  2546. SDE_EVTLOG_ERROR);
  2547. SDE_ERROR_ENC(sde_enc,
  2548. "intf idx:%d, event:%d\n",
  2549. ready_phys->intf_idx, event);
  2550. return;
  2551. }
  2552. }
  2553. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2554. atomic_read(&sde_enc->frame_done_cnt[i]) != 1)
  2555. trigger = false;
  2556. }
  2557. if (trigger) {
  2558. if (sde_enc->crtc_frame_event_cb)
  2559. sde_enc->crtc_frame_event_cb(
  2560. &sde_enc->crtc_frame_event_cb_data,
  2561. event);
  2562. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2563. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2564. }
  2565. } else if (sde_enc->crtc_frame_event_cb) {
  2566. sde_enc->crtc_frame_event_cb(
  2567. &sde_enc->crtc_frame_event_cb_data, event);
  2568. }
  2569. }
  2570. static void sde_encoder_get_qsync_fps_callback(
  2571. struct drm_encoder *drm_enc,
  2572. u32 *qsync_fps)
  2573. {
  2574. struct msm_display_info *disp_info;
  2575. struct sde_encoder_virt *sde_enc;
  2576. if (!qsync_fps)
  2577. return;
  2578. *qsync_fps = 0;
  2579. if (!drm_enc) {
  2580. SDE_ERROR("invalid drm encoder\n");
  2581. return;
  2582. }
  2583. sde_enc = to_sde_encoder_virt(drm_enc);
  2584. disp_info = &sde_enc->disp_info;
  2585. *qsync_fps = disp_info->qsync_min_fps;
  2586. }
  2587. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2588. {
  2589. struct sde_encoder_virt *sde_enc;
  2590. if (!drm_enc) {
  2591. SDE_ERROR("invalid drm encoder\n");
  2592. return -EINVAL;
  2593. }
  2594. sde_enc = to_sde_encoder_virt(drm_enc);
  2595. sde_encoder_resource_control(&sde_enc->base,
  2596. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2597. return 0;
  2598. }
  2599. /**
  2600. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2601. * drm_enc: Pointer to drm encoder structure
  2602. * phys: Pointer to physical encoder structure
  2603. * extra_flush: Additional bit mask to include in flush trigger
  2604. */
  2605. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2606. struct sde_encoder_phys *phys,
  2607. struct sde_ctl_flush_cfg *extra_flush)
  2608. {
  2609. struct sde_hw_ctl *ctl;
  2610. unsigned long lock_flags;
  2611. struct sde_encoder_virt *sde_enc;
  2612. int pend_ret_fence_cnt;
  2613. struct sde_connector *c_conn;
  2614. if (!drm_enc || !phys) {
  2615. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2616. !drm_enc, !phys);
  2617. return;
  2618. }
  2619. sde_enc = to_sde_encoder_virt(drm_enc);
  2620. c_conn = to_sde_connector(phys->connector);
  2621. if (!phys->hw_pp) {
  2622. SDE_ERROR("invalid pingpong hw\n");
  2623. return;
  2624. }
  2625. ctl = phys->hw_ctl;
  2626. if (!ctl || !phys->ops.trigger_flush) {
  2627. SDE_ERROR("missing ctl/trigger cb\n");
  2628. return;
  2629. }
  2630. if (phys->split_role == ENC_ROLE_SKIP) {
  2631. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2632. "skip flush pp%d ctl%d\n",
  2633. phys->hw_pp->idx - PINGPONG_0,
  2634. ctl->idx - CTL_0);
  2635. return;
  2636. }
  2637. /* update pending counts and trigger kickoff ctl flush atomically */
  2638. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2639. if (phys->ops.is_master && phys->ops.is_master(phys))
  2640. atomic_inc(&phys->pending_retire_fence_cnt);
  2641. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2642. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2643. ctl->ops.update_bitmask) {
  2644. /* perform peripheral flush on every frame update for dp dsc */
  2645. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2646. phys->comp_ratio && c_conn->ops.update_pps) {
  2647. c_conn->ops.update_pps(phys->connector, NULL,
  2648. c_conn->display);
  2649. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2650. phys->hw_intf->idx, 1);
  2651. }
  2652. if (sde_enc->dynamic_hdr_updated)
  2653. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2654. phys->hw_intf->idx, 1);
  2655. }
  2656. if ((extra_flush && extra_flush->pending_flush_mask)
  2657. && ctl->ops.update_pending_flush)
  2658. ctl->ops.update_pending_flush(ctl, extra_flush);
  2659. phys->ops.trigger_flush(phys);
  2660. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2661. if (ctl->ops.get_pending_flush) {
  2662. struct sde_ctl_flush_cfg pending_flush = {0,};
  2663. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2664. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2665. ctl->idx - CTL_0,
  2666. pending_flush.pending_flush_mask,
  2667. pend_ret_fence_cnt);
  2668. } else {
  2669. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2670. ctl->idx - CTL_0,
  2671. pend_ret_fence_cnt);
  2672. }
  2673. }
  2674. /**
  2675. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2676. * phys: Pointer to physical encoder structure
  2677. */
  2678. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2679. {
  2680. struct sde_hw_ctl *ctl;
  2681. struct sde_encoder_virt *sde_enc;
  2682. if (!phys) {
  2683. SDE_ERROR("invalid argument(s)\n");
  2684. return;
  2685. }
  2686. if (!phys->hw_pp) {
  2687. SDE_ERROR("invalid pingpong hw\n");
  2688. return;
  2689. }
  2690. if (!phys->parent) {
  2691. SDE_ERROR("invalid parent\n");
  2692. return;
  2693. }
  2694. /* avoid ctrl start for encoder in clone mode */
  2695. if (phys->in_clone_mode)
  2696. return;
  2697. ctl = phys->hw_ctl;
  2698. sde_enc = to_sde_encoder_virt(phys->parent);
  2699. if (phys->split_role == ENC_ROLE_SKIP) {
  2700. SDE_DEBUG_ENC(sde_enc,
  2701. "skip start pp%d ctl%d\n",
  2702. phys->hw_pp->idx - PINGPONG_0,
  2703. ctl->idx - CTL_0);
  2704. return;
  2705. }
  2706. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2707. phys->ops.trigger_start(phys);
  2708. }
  2709. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  2710. {
  2711. struct sde_hw_ctl *ctl;
  2712. if (!phys_enc) {
  2713. SDE_ERROR("invalid encoder\n");
  2714. return;
  2715. }
  2716. ctl = phys_enc->hw_ctl;
  2717. if (ctl && ctl->ops.trigger_flush)
  2718. ctl->ops.trigger_flush(ctl);
  2719. }
  2720. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  2721. {
  2722. struct sde_hw_ctl *ctl;
  2723. if (!phys_enc) {
  2724. SDE_ERROR("invalid encoder\n");
  2725. return;
  2726. }
  2727. ctl = phys_enc->hw_ctl;
  2728. if (ctl && ctl->ops.trigger_start) {
  2729. ctl->ops.trigger_start(ctl);
  2730. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  2731. }
  2732. }
  2733. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  2734. {
  2735. struct sde_encoder_virt *sde_enc;
  2736. struct sde_connector *sde_con;
  2737. void *sde_con_disp;
  2738. struct sde_hw_ctl *ctl;
  2739. int rc;
  2740. if (!phys_enc) {
  2741. SDE_ERROR("invalid encoder\n");
  2742. return;
  2743. }
  2744. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2745. ctl = phys_enc->hw_ctl;
  2746. if (!ctl || !ctl->ops.reset)
  2747. return;
  2748. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  2749. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  2750. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  2751. phys_enc->connector) {
  2752. sde_con = to_sde_connector(phys_enc->connector);
  2753. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  2754. if (sde_con->ops.soft_reset) {
  2755. rc = sde_con->ops.soft_reset(sde_con_disp);
  2756. if (rc) {
  2757. SDE_ERROR_ENC(sde_enc,
  2758. "connector soft reset failure\n");
  2759. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  2760. "panic");
  2761. }
  2762. }
  2763. }
  2764. phys_enc->enable_state = SDE_ENC_ENABLED;
  2765. }
  2766. /**
  2767. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  2768. * Iterate through the physical encoders and perform consolidated flush
  2769. * and/or control start triggering as needed. This is done in the virtual
  2770. * encoder rather than the individual physical ones in order to handle
  2771. * use cases that require visibility into multiple physical encoders at
  2772. * a time.
  2773. * sde_enc: Pointer to virtual encoder structure
  2774. */
  2775. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
  2776. {
  2777. struct sde_hw_ctl *ctl;
  2778. uint32_t i;
  2779. struct sde_ctl_flush_cfg pending_flush = {0,};
  2780. u32 pending_kickoff_cnt;
  2781. struct msm_drm_private *priv = NULL;
  2782. struct sde_kms *sde_kms = NULL;
  2783. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  2784. bool is_regdma_blocking = false, is_vid_mode = false;
  2785. if (!sde_enc) {
  2786. SDE_ERROR("invalid encoder\n");
  2787. return;
  2788. }
  2789. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2790. is_vid_mode = true;
  2791. is_regdma_blocking = (is_vid_mode ||
  2792. _sde_encoder_is_autorefresh_enabled(sde_enc));
  2793. /* don't perform flush/start operations for slave encoders */
  2794. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2795. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2796. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2797. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2798. continue;
  2799. ctl = phys->hw_ctl;
  2800. if (!ctl)
  2801. continue;
  2802. if (phys->connector)
  2803. topology = sde_connector_get_topology_name(
  2804. phys->connector);
  2805. if (!phys->ops.needs_single_flush ||
  2806. !phys->ops.needs_single_flush(phys)) {
  2807. if (ctl->ops.reg_dma_flush)
  2808. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2809. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
  2810. } else if (ctl->ops.get_pending_flush) {
  2811. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2812. }
  2813. }
  2814. /* for split flush, combine pending flush masks and send to master */
  2815. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  2816. ctl = sde_enc->cur_master->hw_ctl;
  2817. if (ctl->ops.reg_dma_flush)
  2818. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2819. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  2820. &pending_flush);
  2821. }
  2822. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  2823. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2824. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2825. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2826. continue;
  2827. if (!phys->ops.needs_single_flush ||
  2828. !phys->ops.needs_single_flush(phys)) {
  2829. pending_kickoff_cnt =
  2830. sde_encoder_phys_inc_pending(phys);
  2831. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  2832. } else {
  2833. pending_kickoff_cnt =
  2834. sde_encoder_phys_inc_pending(phys);
  2835. SDE_EVT32(pending_kickoff_cnt,
  2836. pending_flush.pending_flush_mask,
  2837. SDE_EVTLOG_FUNC_CASE2);
  2838. }
  2839. }
  2840. if (sde_enc->misr_enable)
  2841. sde_encoder_misr_configure(&sde_enc->base, true,
  2842. sde_enc->misr_frame_count);
  2843. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  2844. if (crtc_misr_info.misr_enable)
  2845. sde_crtc_misr_setup(sde_enc->crtc, true,
  2846. crtc_misr_info.misr_frame_count);
  2847. _sde_encoder_trigger_start(sde_enc->cur_master);
  2848. if (sde_enc->elevated_ahb_vote) {
  2849. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2850. priv = sde_enc->base.dev->dev_private;
  2851. if (sde_kms != NULL) {
  2852. sde_power_scale_reg_bus(&priv->phandle,
  2853. VOTE_INDEX_LOW,
  2854. false);
  2855. }
  2856. sde_enc->elevated_ahb_vote = false;
  2857. }
  2858. }
  2859. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  2860. struct drm_encoder *drm_enc,
  2861. unsigned long *affected_displays,
  2862. int num_active_phys)
  2863. {
  2864. struct sde_encoder_virt *sde_enc;
  2865. struct sde_encoder_phys *master;
  2866. enum sde_rm_topology_name topology;
  2867. bool is_right_only;
  2868. if (!drm_enc || !affected_displays)
  2869. return;
  2870. sde_enc = to_sde_encoder_virt(drm_enc);
  2871. master = sde_enc->cur_master;
  2872. if (!master || !master->connector)
  2873. return;
  2874. topology = sde_connector_get_topology_name(master->connector);
  2875. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  2876. return;
  2877. /*
  2878. * For pingpong split, the slave pingpong won't generate IRQs. For
  2879. * right-only updates, we can't swap pingpongs, or simply swap the
  2880. * master/slave assignment, we actually have to swap the interfaces
  2881. * so that the master physical encoder will use a pingpong/interface
  2882. * that generates irqs on which to wait.
  2883. */
  2884. is_right_only = !test_bit(0, affected_displays) &&
  2885. test_bit(1, affected_displays);
  2886. if (is_right_only && !sde_enc->intfs_swapped) {
  2887. /* right-only update swap interfaces */
  2888. swap(sde_enc->phys_encs[0]->intf_idx,
  2889. sde_enc->phys_encs[1]->intf_idx);
  2890. sde_enc->intfs_swapped = true;
  2891. } else if (!is_right_only && sde_enc->intfs_swapped) {
  2892. /* left-only or full update, swap back */
  2893. swap(sde_enc->phys_encs[0]->intf_idx,
  2894. sde_enc->phys_encs[1]->intf_idx);
  2895. sde_enc->intfs_swapped = false;
  2896. }
  2897. SDE_DEBUG_ENC(sde_enc,
  2898. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  2899. is_right_only, sde_enc->intfs_swapped,
  2900. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2901. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  2902. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  2903. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2904. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  2905. *affected_displays);
  2906. /* ppsplit always uses master since ppslave invalid for irqs*/
  2907. if (num_active_phys == 1)
  2908. *affected_displays = BIT(0);
  2909. }
  2910. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  2911. struct sde_encoder_kickoff_params *params)
  2912. {
  2913. struct sde_encoder_virt *sde_enc;
  2914. struct sde_encoder_phys *phys;
  2915. int i, num_active_phys;
  2916. bool master_assigned = false;
  2917. if (!drm_enc || !params)
  2918. return;
  2919. sde_enc = to_sde_encoder_virt(drm_enc);
  2920. if (sde_enc->num_phys_encs <= 1)
  2921. return;
  2922. /* count bits set */
  2923. num_active_phys = hweight_long(params->affected_displays);
  2924. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  2925. params->affected_displays, num_active_phys);
  2926. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  2927. num_active_phys);
  2928. /* for left/right only update, ppsplit master switches interface */
  2929. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  2930. &params->affected_displays, num_active_phys);
  2931. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2932. enum sde_enc_split_role prv_role, new_role;
  2933. bool active = false;
  2934. phys = sde_enc->phys_encs[i];
  2935. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  2936. continue;
  2937. active = test_bit(i, &params->affected_displays);
  2938. prv_role = phys->split_role;
  2939. if (active && num_active_phys == 1)
  2940. new_role = ENC_ROLE_SOLO;
  2941. else if (active && !master_assigned)
  2942. new_role = ENC_ROLE_MASTER;
  2943. else if (active)
  2944. new_role = ENC_ROLE_SLAVE;
  2945. else
  2946. new_role = ENC_ROLE_SKIP;
  2947. phys->ops.update_split_role(phys, new_role);
  2948. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  2949. sde_enc->cur_master = phys;
  2950. master_assigned = true;
  2951. }
  2952. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  2953. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2954. phys->split_role, active);
  2955. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  2956. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2957. phys->split_role, active, num_active_phys);
  2958. }
  2959. }
  2960. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  2961. {
  2962. struct sde_encoder_virt *sde_enc;
  2963. struct msm_display_info *disp_info;
  2964. if (!drm_enc) {
  2965. SDE_ERROR("invalid encoder\n");
  2966. return false;
  2967. }
  2968. sde_enc = to_sde_encoder_virt(drm_enc);
  2969. disp_info = &sde_enc->disp_info;
  2970. return (disp_info->curr_panel_mode == mode);
  2971. }
  2972. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  2973. {
  2974. struct sde_encoder_virt *sde_enc;
  2975. struct sde_encoder_phys *phys;
  2976. unsigned int i;
  2977. struct sde_hw_ctl *ctl;
  2978. if (!drm_enc) {
  2979. SDE_ERROR("invalid encoder\n");
  2980. return;
  2981. }
  2982. sde_enc = to_sde_encoder_virt(drm_enc);
  2983. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2984. phys = sde_enc->phys_encs[i];
  2985. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  2986. sde_encoder_check_curr_mode(drm_enc,
  2987. MSM_DISPLAY_CMD_MODE)) {
  2988. ctl = phys->hw_ctl;
  2989. if (ctl->ops.trigger_pending)
  2990. /* update only for command mode primary ctl */
  2991. ctl->ops.trigger_pending(ctl);
  2992. }
  2993. }
  2994. sde_enc->idle_pc_restore = false;
  2995. }
  2996. static u32 _sde_encoder_calculate_linetime(struct sde_encoder_virt *sde_enc,
  2997. struct drm_display_mode *mode)
  2998. {
  2999. u64 pclk_rate;
  3000. u32 pclk_period;
  3001. u32 line_time;
  3002. /*
  3003. * For linetime calculation, only operate on master encoder.
  3004. */
  3005. if (!sde_enc->cur_master)
  3006. return 0;
  3007. if (!sde_enc->cur_master->ops.get_line_count) {
  3008. SDE_ERROR("get_line_count function not defined\n");
  3009. return 0;
  3010. }
  3011. pclk_rate = mode->clock; /* pixel clock in kHz */
  3012. if (pclk_rate == 0) {
  3013. SDE_ERROR("pclk is 0, cannot calculate line time\n");
  3014. return 0;
  3015. }
  3016. pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
  3017. if (pclk_period == 0) {
  3018. SDE_ERROR("pclk period is 0\n");
  3019. return 0;
  3020. }
  3021. /*
  3022. * Line time calculation based on Pixel clock and HTOTAL.
  3023. * Final unit is in ns.
  3024. */
  3025. line_time = (pclk_period * mode->htotal) / 1000;
  3026. if (line_time == 0) {
  3027. SDE_ERROR("line time calculation is 0\n");
  3028. return 0;
  3029. }
  3030. SDE_DEBUG_ENC(sde_enc,
  3031. "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
  3032. pclk_rate, pclk_period, line_time);
  3033. return line_time;
  3034. }
  3035. static int _sde_encoder_wakeup_time(struct drm_encoder *drm_enc,
  3036. ktime_t *wakeup_time)
  3037. {
  3038. struct drm_display_mode *mode;
  3039. struct sde_encoder_virt *sde_enc;
  3040. u32 cur_line;
  3041. u32 line_time;
  3042. u32 vtotal, time_to_vsync;
  3043. ktime_t cur_time;
  3044. sde_enc = to_sde_encoder_virt(drm_enc);
  3045. if (!sde_enc || !sde_enc->cur_master) {
  3046. SDE_ERROR("invalid sde encoder/master\n");
  3047. return -EINVAL;
  3048. }
  3049. mode = &sde_enc->cur_master->cached_mode;
  3050. line_time = _sde_encoder_calculate_linetime(sde_enc, mode);
  3051. if (!line_time)
  3052. return -EINVAL;
  3053. cur_line = sde_enc->cur_master->ops.get_line_count(sde_enc->cur_master);
  3054. vtotal = mode->vtotal;
  3055. if (cur_line >= vtotal)
  3056. time_to_vsync = line_time * vtotal;
  3057. else
  3058. time_to_vsync = line_time * (vtotal - cur_line);
  3059. if (time_to_vsync == 0) {
  3060. SDE_ERROR("time to vsync should not be zero, vtotal=%d\n",
  3061. vtotal);
  3062. return -EINVAL;
  3063. }
  3064. cur_time = ktime_get();
  3065. *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
  3066. SDE_DEBUG_ENC(sde_enc,
  3067. "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
  3068. cur_line, vtotal, time_to_vsync,
  3069. ktime_to_ms(cur_time),
  3070. ktime_to_ms(*wakeup_time));
  3071. return 0;
  3072. }
  3073. static void sde_encoder_vsync_event_handler(struct timer_list *t)
  3074. {
  3075. struct drm_encoder *drm_enc;
  3076. struct sde_encoder_virt *sde_enc =
  3077. from_timer(sde_enc, t, vsync_event_timer);
  3078. struct msm_drm_private *priv;
  3079. struct msm_drm_thread *event_thread;
  3080. if (!sde_enc || !sde_enc->crtc) {
  3081. SDE_ERROR("invalid encoder parameters %d\n", !sde_enc);
  3082. return;
  3083. }
  3084. drm_enc = &sde_enc->base;
  3085. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  3086. SDE_ERROR("invalid encoder parameters\n");
  3087. return;
  3088. }
  3089. priv = drm_enc->dev->dev_private;
  3090. if (sde_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  3091. SDE_ERROR("invalid crtc index:%u\n",
  3092. sde_enc->crtc->index);
  3093. return;
  3094. }
  3095. event_thread = &priv->event_thread[sde_enc->crtc->index];
  3096. if (!event_thread) {
  3097. SDE_ERROR("event_thread not found for crtc:%d\n",
  3098. sde_enc->crtc->index);
  3099. return;
  3100. }
  3101. kthread_queue_work(&event_thread->worker,
  3102. &sde_enc->vsync_event_work);
  3103. }
  3104. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3105. {
  3106. struct sde_encoder_virt *sde_enc = container_of(work,
  3107. struct sde_encoder_virt, esd_trigger_work);
  3108. if (!sde_enc) {
  3109. SDE_ERROR("invalid sde encoder\n");
  3110. return;
  3111. }
  3112. sde_encoder_resource_control(&sde_enc->base,
  3113. SDE_ENC_RC_EVENT_KICKOFF);
  3114. }
  3115. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3116. {
  3117. struct sde_encoder_virt *sde_enc = container_of(work,
  3118. struct sde_encoder_virt, input_event_work);
  3119. if (!sde_enc) {
  3120. SDE_ERROR("invalid sde encoder\n");
  3121. return;
  3122. }
  3123. sde_encoder_resource_control(&sde_enc->base,
  3124. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3125. }
  3126. static void sde_encoder_vsync_event_work_handler(struct kthread_work *work)
  3127. {
  3128. struct sde_encoder_virt *sde_enc = container_of(work,
  3129. struct sde_encoder_virt, vsync_event_work);
  3130. bool autorefresh_enabled = false;
  3131. int rc = 0;
  3132. ktime_t wakeup_time;
  3133. struct drm_encoder *drm_enc;
  3134. if (!sde_enc) {
  3135. SDE_ERROR("invalid sde encoder\n");
  3136. return;
  3137. }
  3138. drm_enc = &sde_enc->base;
  3139. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3140. if (rc < 0) {
  3141. SDE_ERROR_ENC(sde_enc, "sde enc power enabled failed:%d\n", rc);
  3142. return;
  3143. }
  3144. if (sde_enc->cur_master &&
  3145. sde_enc->cur_master->ops.is_autorefresh_enabled)
  3146. autorefresh_enabled =
  3147. sde_enc->cur_master->ops.is_autorefresh_enabled(
  3148. sde_enc->cur_master);
  3149. /* Update timer if autorefresh is enabled else return */
  3150. if (!autorefresh_enabled)
  3151. goto exit;
  3152. rc = _sde_encoder_wakeup_time(&sde_enc->base, &wakeup_time);
  3153. if (rc)
  3154. goto exit;
  3155. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3156. mod_timer(&sde_enc->vsync_event_timer,
  3157. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3158. exit:
  3159. pm_runtime_put_sync(drm_enc->dev->dev);
  3160. }
  3161. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3162. {
  3163. static const uint64_t timeout_us = 50000;
  3164. static const uint64_t sleep_us = 20;
  3165. struct sde_encoder_virt *sde_enc;
  3166. ktime_t cur_ktime, exp_ktime;
  3167. uint32_t line_count, tmp, i;
  3168. if (!drm_enc) {
  3169. SDE_ERROR("invalid encoder\n");
  3170. return -EINVAL;
  3171. }
  3172. sde_enc = to_sde_encoder_virt(drm_enc);
  3173. if (!sde_enc->cur_master ||
  3174. !sde_enc->cur_master->ops.get_line_count) {
  3175. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3176. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3177. return -EINVAL;
  3178. }
  3179. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3180. line_count = sde_enc->cur_master->ops.get_line_count(
  3181. sde_enc->cur_master);
  3182. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3183. tmp = line_count;
  3184. line_count = sde_enc->cur_master->ops.get_line_count(
  3185. sde_enc->cur_master);
  3186. if (line_count < tmp) {
  3187. SDE_EVT32(DRMID(drm_enc), line_count);
  3188. return 0;
  3189. }
  3190. cur_ktime = ktime_get();
  3191. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3192. break;
  3193. usleep_range(sleep_us / 2, sleep_us);
  3194. }
  3195. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3196. return -ETIMEDOUT;
  3197. }
  3198. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3199. {
  3200. struct drm_encoder *drm_enc;
  3201. struct sde_rm_hw_iter rm_iter;
  3202. bool lm_valid = false;
  3203. bool intf_valid = false;
  3204. if (!phys_enc || !phys_enc->parent) {
  3205. SDE_ERROR("invalid encoder\n");
  3206. return -EINVAL;
  3207. }
  3208. drm_enc = phys_enc->parent;
  3209. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3210. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3211. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3212. phys_enc->has_intf_te)) {
  3213. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3214. SDE_HW_BLK_INTF);
  3215. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3216. struct sde_hw_intf *hw_intf =
  3217. (struct sde_hw_intf *)rm_iter.hw;
  3218. if (!hw_intf)
  3219. continue;
  3220. if (phys_enc->hw_ctl->ops.update_bitmask)
  3221. phys_enc->hw_ctl->ops.update_bitmask(
  3222. phys_enc->hw_ctl,
  3223. SDE_HW_FLUSH_INTF,
  3224. hw_intf->idx, 1);
  3225. intf_valid = true;
  3226. }
  3227. if (!intf_valid) {
  3228. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3229. "intf not found to flush\n");
  3230. return -EFAULT;
  3231. }
  3232. } else {
  3233. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3234. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3235. struct sde_hw_mixer *hw_lm =
  3236. (struct sde_hw_mixer *)rm_iter.hw;
  3237. if (!hw_lm)
  3238. continue;
  3239. /* update LM flush for HW without INTF TE */
  3240. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3241. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3242. phys_enc->hw_ctl,
  3243. hw_lm->idx, 1);
  3244. lm_valid = true;
  3245. }
  3246. if (!lm_valid) {
  3247. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3248. "lm not found to flush\n");
  3249. return -EFAULT;
  3250. }
  3251. }
  3252. return 0;
  3253. }
  3254. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3255. struct sde_encoder_virt *sde_enc)
  3256. {
  3257. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3258. struct sde_hw_mdp *mdptop = NULL;
  3259. sde_enc->dynamic_hdr_updated = false;
  3260. if (sde_enc->cur_master) {
  3261. mdptop = sde_enc->cur_master->hw_mdptop;
  3262. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3263. sde_enc->cur_master->connector);
  3264. }
  3265. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3266. return;
  3267. if (mdptop->ops.set_hdr_plus_metadata) {
  3268. sde_enc->dynamic_hdr_updated = true;
  3269. mdptop->ops.set_hdr_plus_metadata(
  3270. mdptop, dhdr_meta->dynamic_hdr_payload,
  3271. dhdr_meta->dynamic_hdr_payload_size,
  3272. sde_enc->cur_master->intf_idx == INTF_0 ?
  3273. 0 : 1);
  3274. }
  3275. }
  3276. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3277. {
  3278. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3279. struct sde_encoder_phys *phys;
  3280. int i;
  3281. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3282. phys = sde_enc->phys_encs[i];
  3283. if (phys && phys->ops.hw_reset)
  3284. phys->ops.hw_reset(phys);
  3285. }
  3286. }
  3287. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3288. struct sde_encoder_kickoff_params *params)
  3289. {
  3290. struct sde_encoder_virt *sde_enc;
  3291. struct sde_encoder_phys *phys;
  3292. struct sde_kms *sde_kms = NULL;
  3293. struct sde_crtc *sde_crtc;
  3294. bool needs_hw_reset = false, is_cmd_mode;
  3295. int i, rc, ret = 0;
  3296. struct msm_display_info *disp_info;
  3297. if (!drm_enc || !params || !drm_enc->dev ||
  3298. !drm_enc->dev->dev_private) {
  3299. SDE_ERROR("invalid args\n");
  3300. return -EINVAL;
  3301. }
  3302. sde_enc = to_sde_encoder_virt(drm_enc);
  3303. sde_kms = sde_encoder_get_kms(drm_enc);
  3304. if (!sde_kms)
  3305. return -EINVAL;
  3306. disp_info = &sde_enc->disp_info;
  3307. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3308. SDE_DEBUG_ENC(sde_enc, "\n");
  3309. SDE_EVT32(DRMID(drm_enc));
  3310. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3311. MSM_DISPLAY_CMD_MODE);
  3312. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3313. && is_cmd_mode)
  3314. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3315. sde_enc->cur_master->connector->state,
  3316. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3317. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3318. /* prepare for next kickoff, may include waiting on previous kickoff */
  3319. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3320. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3321. phys = sde_enc->phys_encs[i];
  3322. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3323. params->recovery_events_enabled =
  3324. sde_enc->recovery_events_enabled;
  3325. if (phys) {
  3326. if (phys->ops.prepare_for_kickoff) {
  3327. rc = phys->ops.prepare_for_kickoff(
  3328. phys, params);
  3329. if (rc)
  3330. ret = rc;
  3331. }
  3332. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3333. needs_hw_reset = true;
  3334. _sde_encoder_setup_dither(phys);
  3335. if (sde_enc->cur_master &&
  3336. sde_connector_is_qsync_updated(
  3337. sde_enc->cur_master->connector)) {
  3338. _helper_flush_qsync(phys);
  3339. }
  3340. }
  3341. }
  3342. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3343. if (rc) {
  3344. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3345. ret = rc;
  3346. goto end;
  3347. }
  3348. /* if any phys needs reset, reset all phys, in-order */
  3349. if (needs_hw_reset)
  3350. sde_encoder_needs_hw_reset(drm_enc);
  3351. _sde_encoder_update_master(drm_enc, params);
  3352. _sde_encoder_update_roi(drm_enc);
  3353. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3354. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3355. if (rc) {
  3356. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3357. sde_enc->cur_master->connector->base.id,
  3358. rc);
  3359. ret = rc;
  3360. }
  3361. }
  3362. if (sde_enc->cur_master &&
  3363. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3364. !sde_enc->cur_master->cont_splash_enabled)) {
  3365. rc = sde_encoder_dce_setup(sde_enc, params);
  3366. if (rc) {
  3367. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3368. ret = rc;
  3369. }
  3370. }
  3371. sde_encoder_dce_flush(sde_enc);
  3372. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3373. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3374. sde_enc->cur_master, sde_kms->qdss_enabled);
  3375. end:
  3376. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3377. return ret;
  3378. }
  3379. /**
  3380. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3381. * with the specified encoder, and unstage all pipes from it
  3382. * @encoder: encoder pointer
  3383. * Returns: 0 on success
  3384. */
  3385. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3386. {
  3387. struct sde_encoder_virt *sde_enc;
  3388. struct sde_encoder_phys *phys;
  3389. unsigned int i;
  3390. int rc = 0;
  3391. if (!drm_enc) {
  3392. SDE_ERROR("invalid encoder\n");
  3393. return -EINVAL;
  3394. }
  3395. sde_enc = to_sde_encoder_virt(drm_enc);
  3396. SDE_ATRACE_BEGIN("encoder_release_lm");
  3397. SDE_DEBUG_ENC(sde_enc, "\n");
  3398. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3399. phys = sde_enc->phys_encs[i];
  3400. if (!phys)
  3401. continue;
  3402. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3403. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3404. if (rc)
  3405. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3406. }
  3407. SDE_ATRACE_END("encoder_release_lm");
  3408. return rc;
  3409. }
  3410. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error)
  3411. {
  3412. struct sde_encoder_virt *sde_enc;
  3413. struct sde_encoder_phys *phys;
  3414. ktime_t wakeup_time;
  3415. unsigned int i;
  3416. if (!drm_enc) {
  3417. SDE_ERROR("invalid encoder\n");
  3418. return;
  3419. }
  3420. SDE_ATRACE_BEGIN("encoder_kickoff");
  3421. sde_enc = to_sde_encoder_virt(drm_enc);
  3422. SDE_DEBUG_ENC(sde_enc, "\n");
  3423. /* create a 'no pipes' commit to release buffers on errors */
  3424. if (is_error)
  3425. _sde_encoder_reset_ctl_hw(drm_enc);
  3426. /* All phys encs are ready to go, trigger the kickoff */
  3427. _sde_encoder_kickoff_phys(sde_enc);
  3428. /* allow phys encs to handle any post-kickoff business */
  3429. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3430. phys = sde_enc->phys_encs[i];
  3431. if (phys && phys->ops.handle_post_kickoff)
  3432. phys->ops.handle_post_kickoff(phys);
  3433. }
  3434. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
  3435. !_sde_encoder_wakeup_time(drm_enc, &wakeup_time)) {
  3436. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3437. mod_timer(&sde_enc->vsync_event_timer,
  3438. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3439. }
  3440. SDE_ATRACE_END("encoder_kickoff");
  3441. }
  3442. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3443. struct sde_hw_pp_vsync_info *info)
  3444. {
  3445. struct sde_encoder_virt *sde_enc;
  3446. struct sde_encoder_phys *phys;
  3447. int i, ret;
  3448. if (!drm_enc || !info)
  3449. return;
  3450. sde_enc = to_sde_encoder_virt(drm_enc);
  3451. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3452. phys = sde_enc->phys_encs[i];
  3453. if (phys && phys->hw_intf && phys->hw_pp
  3454. && phys->hw_intf->ops.get_vsync_info) {
  3455. ret = phys->hw_intf->ops.get_vsync_info(
  3456. phys->hw_intf, &info[i]);
  3457. if (!ret) {
  3458. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3459. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3460. }
  3461. }
  3462. }
  3463. }
  3464. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3465. struct drm_framebuffer *fb)
  3466. {
  3467. struct drm_encoder *drm_enc;
  3468. struct sde_hw_mixer_cfg mixer;
  3469. struct sde_rm_hw_iter lm_iter;
  3470. bool lm_valid = false;
  3471. if (!phys_enc || !phys_enc->parent) {
  3472. SDE_ERROR("invalid encoder\n");
  3473. return -EINVAL;
  3474. }
  3475. drm_enc = phys_enc->parent;
  3476. memset(&mixer, 0, sizeof(mixer));
  3477. /* reset associated CTL/LMs */
  3478. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3479. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3480. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3481. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3482. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3483. if (!hw_lm)
  3484. continue;
  3485. /* need to flush LM to remove it */
  3486. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3487. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3488. phys_enc->hw_ctl,
  3489. hw_lm->idx, 1);
  3490. if (fb) {
  3491. /* assume a single LM if targeting a frame buffer */
  3492. if (lm_valid)
  3493. continue;
  3494. mixer.out_height = fb->height;
  3495. mixer.out_width = fb->width;
  3496. if (hw_lm->ops.setup_mixer_out)
  3497. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3498. }
  3499. lm_valid = true;
  3500. /* only enable border color on LM */
  3501. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3502. phys_enc->hw_ctl->ops.setup_blendstage(
  3503. phys_enc->hw_ctl, hw_lm->idx, NULL, NULL);
  3504. }
  3505. if (!lm_valid) {
  3506. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3507. return -EFAULT;
  3508. }
  3509. return 0;
  3510. }
  3511. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3512. {
  3513. struct sde_encoder_virt *sde_enc;
  3514. struct sde_encoder_phys *phys;
  3515. int i, rc = 0, ret = 0;
  3516. struct sde_hw_ctl *ctl;
  3517. if (!drm_enc) {
  3518. SDE_ERROR("invalid encoder\n");
  3519. return -EINVAL;
  3520. }
  3521. sde_enc = to_sde_encoder_virt(drm_enc);
  3522. /* update the qsync parameters for the current frame */
  3523. if (sde_enc->cur_master)
  3524. sde_connector_set_qsync_params(
  3525. sde_enc->cur_master->connector);
  3526. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3527. phys = sde_enc->phys_encs[i];
  3528. if (phys && phys->ops.prepare_commit)
  3529. phys->ops.prepare_commit(phys);
  3530. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3531. ret = -ETIMEDOUT;
  3532. if (phys && phys->hw_ctl) {
  3533. ctl = phys->hw_ctl;
  3534. /*
  3535. * avoid clearing the pending flush during the first
  3536. * frame update after idle power collpase as the
  3537. * restore path would have updated the pending flush
  3538. */
  3539. if (!sde_enc->idle_pc_restore &&
  3540. ctl->ops.clear_pending_flush)
  3541. ctl->ops.clear_pending_flush(ctl);
  3542. }
  3543. }
  3544. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3545. rc = sde_connector_prepare_commit(
  3546. sde_enc->cur_master->connector);
  3547. if (rc)
  3548. SDE_ERROR_ENC(sde_enc,
  3549. "prepare commit failed conn %d rc %d\n",
  3550. sde_enc->cur_master->connector->base.id,
  3551. rc);
  3552. }
  3553. return ret;
  3554. }
  3555. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3556. bool enable, u32 frame_count)
  3557. {
  3558. if (!phys_enc)
  3559. return;
  3560. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3561. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3562. enable, frame_count);
  3563. }
  3564. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3565. bool nonblock, u32 *misr_value)
  3566. {
  3567. if (!phys_enc)
  3568. return -EINVAL;
  3569. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3570. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3571. nonblock, misr_value) : -ENOTSUPP;
  3572. }
  3573. #ifdef CONFIG_DEBUG_FS
  3574. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3575. {
  3576. struct sde_encoder_virt *sde_enc;
  3577. int i;
  3578. if (!s || !s->private)
  3579. return -EINVAL;
  3580. sde_enc = s->private;
  3581. mutex_lock(&sde_enc->enc_lock);
  3582. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3583. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3584. if (!phys)
  3585. continue;
  3586. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3587. phys->intf_idx - INTF_0,
  3588. atomic_read(&phys->vsync_cnt),
  3589. atomic_read(&phys->underrun_cnt));
  3590. switch (phys->intf_mode) {
  3591. case INTF_MODE_VIDEO:
  3592. seq_puts(s, "mode: video\n");
  3593. break;
  3594. case INTF_MODE_CMD:
  3595. seq_puts(s, "mode: command\n");
  3596. break;
  3597. case INTF_MODE_WB_BLOCK:
  3598. seq_puts(s, "mode: wb block\n");
  3599. break;
  3600. case INTF_MODE_WB_LINE:
  3601. seq_puts(s, "mode: wb line\n");
  3602. break;
  3603. default:
  3604. seq_puts(s, "mode: ???\n");
  3605. break;
  3606. }
  3607. }
  3608. mutex_unlock(&sde_enc->enc_lock);
  3609. return 0;
  3610. }
  3611. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3612. struct file *file)
  3613. {
  3614. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3615. }
  3616. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3617. const char __user *user_buf, size_t count, loff_t *ppos)
  3618. {
  3619. struct sde_encoder_virt *sde_enc;
  3620. int rc;
  3621. char buf[MISR_BUFF_SIZE + 1];
  3622. size_t buff_copy;
  3623. u32 frame_count, enable;
  3624. struct sde_kms *sde_kms = NULL;
  3625. struct drm_encoder *drm_enc;
  3626. if (!file || !file->private_data)
  3627. return -EINVAL;
  3628. sde_enc = file->private_data;
  3629. if (!sde_enc)
  3630. return -EINVAL;
  3631. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3632. if (!sde_kms)
  3633. return -EINVAL;
  3634. drm_enc = &sde_enc->base;
  3635. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3636. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3637. return -ENOTSUPP;
  3638. }
  3639. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3640. if (copy_from_user(buf, user_buf, buff_copy))
  3641. return -EINVAL;
  3642. buf[buff_copy] = 0; /* end of string */
  3643. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3644. return -EINVAL;
  3645. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3646. if (rc < 0)
  3647. return rc;
  3648. sde_enc->misr_enable = enable;
  3649. sde_enc->misr_frame_count = frame_count;
  3650. sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
  3651. pm_runtime_put_sync(drm_enc->dev->dev);
  3652. return count;
  3653. }
  3654. static ssize_t _sde_encoder_misr_read(struct file *file,
  3655. char __user *user_buff, size_t count, loff_t *ppos)
  3656. {
  3657. struct sde_encoder_virt *sde_enc;
  3658. struct sde_kms *sde_kms = NULL;
  3659. struct drm_encoder *drm_enc;
  3660. int i = 0, len = 0;
  3661. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3662. int rc;
  3663. if (*ppos)
  3664. return 0;
  3665. if (!file || !file->private_data)
  3666. return -EINVAL;
  3667. sde_enc = file->private_data;
  3668. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3669. if (!sde_kms)
  3670. return -EINVAL;
  3671. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3672. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3673. return -ENOTSUPP;
  3674. }
  3675. drm_enc = &sde_enc->base;
  3676. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3677. if (rc < 0)
  3678. return rc;
  3679. if (!sde_enc->misr_enable) {
  3680. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3681. "disabled\n");
  3682. goto buff_check;
  3683. }
  3684. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3685. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3686. u32 misr_value = 0;
  3687. if (!phys || !phys->ops.collect_misr) {
  3688. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3689. "invalid\n");
  3690. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3691. continue;
  3692. }
  3693. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3694. if (rc) {
  3695. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3696. "invalid\n");
  3697. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3698. rc);
  3699. continue;
  3700. } else {
  3701. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3702. "Intf idx:%d\n",
  3703. phys->intf_idx - INTF_0);
  3704. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3705. "0x%x\n", misr_value);
  3706. }
  3707. }
  3708. buff_check:
  3709. if (count <= len) {
  3710. len = 0;
  3711. goto end;
  3712. }
  3713. if (copy_to_user(user_buff, buf, len)) {
  3714. len = -EFAULT;
  3715. goto end;
  3716. }
  3717. *ppos += len; /* increase offset */
  3718. end:
  3719. pm_runtime_put_sync(drm_enc->dev->dev);
  3720. return len;
  3721. }
  3722. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3723. {
  3724. struct sde_encoder_virt *sde_enc;
  3725. struct sde_kms *sde_kms;
  3726. int i;
  3727. static const struct file_operations debugfs_status_fops = {
  3728. .open = _sde_encoder_debugfs_status_open,
  3729. .read = seq_read,
  3730. .llseek = seq_lseek,
  3731. .release = single_release,
  3732. };
  3733. static const struct file_operations debugfs_misr_fops = {
  3734. .open = simple_open,
  3735. .read = _sde_encoder_misr_read,
  3736. .write = _sde_encoder_misr_setup,
  3737. };
  3738. char name[SDE_NAME_SIZE];
  3739. if (!drm_enc) {
  3740. SDE_ERROR("invalid encoder\n");
  3741. return -EINVAL;
  3742. }
  3743. sde_enc = to_sde_encoder_virt(drm_enc);
  3744. sde_kms = sde_encoder_get_kms(drm_enc);
  3745. if (!sde_kms) {
  3746. SDE_ERROR("invalid sde_kms\n");
  3747. return -EINVAL;
  3748. }
  3749. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3750. /* create overall sub-directory for the encoder */
  3751. sde_enc->debugfs_root = debugfs_create_dir(name,
  3752. drm_enc->dev->primary->debugfs_root);
  3753. if (!sde_enc->debugfs_root)
  3754. return -ENOMEM;
  3755. /* don't error check these */
  3756. debugfs_create_file("status", 0400,
  3757. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3758. debugfs_create_file("misr_data", 0600,
  3759. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3760. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  3761. &sde_enc->idle_pc_enabled);
  3762. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  3763. &sde_enc->frame_trigger_mode);
  3764. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3765. if (sde_enc->phys_encs[i] &&
  3766. sde_enc->phys_encs[i]->ops.late_register)
  3767. sde_enc->phys_encs[i]->ops.late_register(
  3768. sde_enc->phys_encs[i],
  3769. sde_enc->debugfs_root);
  3770. return 0;
  3771. }
  3772. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3773. {
  3774. struct sde_encoder_virt *sde_enc;
  3775. if (!drm_enc)
  3776. return;
  3777. sde_enc = to_sde_encoder_virt(drm_enc);
  3778. debugfs_remove_recursive(sde_enc->debugfs_root);
  3779. }
  3780. #else
  3781. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3782. {
  3783. return 0;
  3784. }
  3785. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3786. {
  3787. }
  3788. #endif
  3789. static int sde_encoder_late_register(struct drm_encoder *encoder)
  3790. {
  3791. return _sde_encoder_init_debugfs(encoder);
  3792. }
  3793. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  3794. {
  3795. _sde_encoder_destroy_debugfs(encoder);
  3796. }
  3797. static int sde_encoder_virt_add_phys_encs(
  3798. struct msm_display_info *disp_info,
  3799. struct sde_encoder_virt *sde_enc,
  3800. struct sde_enc_phys_init_params *params)
  3801. {
  3802. struct sde_encoder_phys *enc = NULL;
  3803. u32 display_caps = disp_info->capabilities;
  3804. SDE_DEBUG_ENC(sde_enc, "\n");
  3805. /*
  3806. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  3807. * in this function, check up-front.
  3808. */
  3809. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  3810. ARRAY_SIZE(sde_enc->phys_encs)) {
  3811. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3812. sde_enc->num_phys_encs);
  3813. return -EINVAL;
  3814. }
  3815. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  3816. enc = sde_encoder_phys_vid_init(params);
  3817. if (IS_ERR_OR_NULL(enc)) {
  3818. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  3819. PTR_ERR(enc));
  3820. return !enc ? -EINVAL : PTR_ERR(enc);
  3821. }
  3822. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  3823. }
  3824. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  3825. enc = sde_encoder_phys_cmd_init(params);
  3826. if (IS_ERR_OR_NULL(enc)) {
  3827. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  3828. PTR_ERR(enc));
  3829. return !enc ? -EINVAL : PTR_ERR(enc);
  3830. }
  3831. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  3832. }
  3833. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  3834. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3835. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  3836. else
  3837. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3838. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  3839. ++sde_enc->num_phys_encs;
  3840. return 0;
  3841. }
  3842. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  3843. struct sde_enc_phys_init_params *params)
  3844. {
  3845. struct sde_encoder_phys *enc = NULL;
  3846. if (!sde_enc) {
  3847. SDE_ERROR("invalid encoder\n");
  3848. return -EINVAL;
  3849. }
  3850. SDE_DEBUG_ENC(sde_enc, "\n");
  3851. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  3852. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3853. sde_enc->num_phys_encs);
  3854. return -EINVAL;
  3855. }
  3856. enc = sde_encoder_phys_wb_init(params);
  3857. if (IS_ERR_OR_NULL(enc)) {
  3858. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  3859. PTR_ERR(enc));
  3860. return !enc ? -EINVAL : PTR_ERR(enc);
  3861. }
  3862. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  3863. ++sde_enc->num_phys_encs;
  3864. return 0;
  3865. }
  3866. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  3867. struct sde_kms *sde_kms,
  3868. struct msm_display_info *disp_info,
  3869. int *drm_enc_mode)
  3870. {
  3871. int ret = 0;
  3872. int i = 0;
  3873. enum sde_intf_type intf_type;
  3874. struct sde_encoder_virt_ops parent_ops = {
  3875. sde_encoder_vblank_callback,
  3876. sde_encoder_underrun_callback,
  3877. sde_encoder_frame_done_callback,
  3878. sde_encoder_get_qsync_fps_callback,
  3879. };
  3880. struct sde_enc_phys_init_params phys_params;
  3881. if (!sde_enc || !sde_kms) {
  3882. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  3883. !sde_enc, !sde_kms);
  3884. return -EINVAL;
  3885. }
  3886. memset(&phys_params, 0, sizeof(phys_params));
  3887. phys_params.sde_kms = sde_kms;
  3888. phys_params.parent = &sde_enc->base;
  3889. phys_params.parent_ops = parent_ops;
  3890. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  3891. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  3892. SDE_DEBUG("\n");
  3893. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  3894. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  3895. intf_type = INTF_DSI;
  3896. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  3897. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3898. intf_type = INTF_HDMI;
  3899. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  3900. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  3901. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  3902. else
  3903. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3904. intf_type = INTF_DP;
  3905. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  3906. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  3907. intf_type = INTF_WB;
  3908. } else {
  3909. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  3910. return -EINVAL;
  3911. }
  3912. WARN_ON(disp_info->num_of_h_tiles < 1);
  3913. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  3914. sde_enc->te_source = disp_info->te_source;
  3915. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  3916. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  3917. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  3918. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  3919. mutex_lock(&sde_enc->enc_lock);
  3920. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  3921. /*
  3922. * Left-most tile is at index 0, content is controller id
  3923. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  3924. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  3925. */
  3926. u32 controller_id = disp_info->h_tile_instance[i];
  3927. if (disp_info->num_of_h_tiles > 1) {
  3928. if (i == 0)
  3929. phys_params.split_role = ENC_ROLE_MASTER;
  3930. else
  3931. phys_params.split_role = ENC_ROLE_SLAVE;
  3932. } else {
  3933. phys_params.split_role = ENC_ROLE_SOLO;
  3934. }
  3935. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  3936. i, controller_id, phys_params.split_role);
  3937. if (sde_enc->ops.phys_init) {
  3938. struct sde_encoder_phys *enc;
  3939. enc = sde_enc->ops.phys_init(intf_type,
  3940. controller_id,
  3941. &phys_params);
  3942. if (enc) {
  3943. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3944. enc;
  3945. ++sde_enc->num_phys_encs;
  3946. } else
  3947. SDE_ERROR_ENC(sde_enc,
  3948. "failed to add phys encs\n");
  3949. continue;
  3950. }
  3951. if (intf_type == INTF_WB) {
  3952. phys_params.intf_idx = INTF_MAX;
  3953. phys_params.wb_idx = sde_encoder_get_wb(
  3954. sde_kms->catalog,
  3955. intf_type, controller_id);
  3956. if (phys_params.wb_idx == WB_MAX) {
  3957. SDE_ERROR_ENC(sde_enc,
  3958. "could not get wb: type %d, id %d\n",
  3959. intf_type, controller_id);
  3960. ret = -EINVAL;
  3961. }
  3962. } else {
  3963. phys_params.wb_idx = WB_MAX;
  3964. phys_params.intf_idx = sde_encoder_get_intf(
  3965. sde_kms->catalog, intf_type,
  3966. controller_id);
  3967. if (phys_params.intf_idx == INTF_MAX) {
  3968. SDE_ERROR_ENC(sde_enc,
  3969. "could not get wb: type %d, id %d\n",
  3970. intf_type, controller_id);
  3971. ret = -EINVAL;
  3972. }
  3973. }
  3974. if (!ret) {
  3975. if (intf_type == INTF_WB)
  3976. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  3977. &phys_params);
  3978. else
  3979. ret = sde_encoder_virt_add_phys_encs(
  3980. disp_info,
  3981. sde_enc,
  3982. &phys_params);
  3983. if (ret)
  3984. SDE_ERROR_ENC(sde_enc,
  3985. "failed to add phys encs\n");
  3986. }
  3987. }
  3988. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3989. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  3990. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  3991. if (vid_phys) {
  3992. atomic_set(&vid_phys->vsync_cnt, 0);
  3993. atomic_set(&vid_phys->underrun_cnt, 0);
  3994. }
  3995. if (cmd_phys) {
  3996. atomic_set(&cmd_phys->vsync_cnt, 0);
  3997. atomic_set(&cmd_phys->underrun_cnt, 0);
  3998. }
  3999. }
  4000. mutex_unlock(&sde_enc->enc_lock);
  4001. return ret;
  4002. }
  4003. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  4004. .mode_set = sde_encoder_virt_mode_set,
  4005. .disable = sde_encoder_virt_disable,
  4006. .enable = sde_encoder_virt_enable,
  4007. .atomic_check = sde_encoder_virt_atomic_check,
  4008. };
  4009. static const struct drm_encoder_funcs sde_encoder_funcs = {
  4010. .destroy = sde_encoder_destroy,
  4011. .late_register = sde_encoder_late_register,
  4012. .early_unregister = sde_encoder_early_unregister,
  4013. };
  4014. struct drm_encoder *sde_encoder_init_with_ops(
  4015. struct drm_device *dev,
  4016. struct msm_display_info *disp_info,
  4017. const struct sde_encoder_ops *ops)
  4018. {
  4019. struct msm_drm_private *priv = dev->dev_private;
  4020. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  4021. struct drm_encoder *drm_enc = NULL;
  4022. struct sde_encoder_virt *sde_enc = NULL;
  4023. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  4024. char name[SDE_NAME_SIZE];
  4025. int ret = 0, i, intf_index = INTF_MAX;
  4026. struct sde_encoder_phys *phys = NULL;
  4027. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  4028. if (!sde_enc) {
  4029. ret = -ENOMEM;
  4030. goto fail;
  4031. }
  4032. if (ops)
  4033. sde_enc->ops = *ops;
  4034. mutex_init(&sde_enc->enc_lock);
  4035. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  4036. &drm_enc_mode);
  4037. if (ret)
  4038. goto fail;
  4039. sde_enc->cur_master = NULL;
  4040. spin_lock_init(&sde_enc->enc_spinlock);
  4041. mutex_init(&sde_enc->vblank_ctl_lock);
  4042. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4043. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  4044. drm_enc = &sde_enc->base;
  4045. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4046. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4047. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI)
  4048. timer_setup(&sde_enc->vsync_event_timer,
  4049. sde_encoder_vsync_event_handler, 0);
  4050. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4051. phys = sde_enc->phys_encs[i];
  4052. if (!phys)
  4053. continue;
  4054. if (phys->ops.is_master && phys->ops.is_master(phys))
  4055. intf_index = phys->intf_idx - INTF_0;
  4056. }
  4057. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4058. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4059. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4060. SDE_RSC_PRIMARY_DISP_CLIENT :
  4061. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4062. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4063. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4064. PTR_ERR(sde_enc->rsc_client));
  4065. sde_enc->rsc_client = NULL;
  4066. }
  4067. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
  4068. ret = _sde_encoder_input_handler(sde_enc);
  4069. if (ret)
  4070. SDE_ERROR(
  4071. "input handler registration failed, rc = %d\n", ret);
  4072. }
  4073. mutex_init(&sde_enc->rc_lock);
  4074. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4075. sde_encoder_off_work);
  4076. sde_enc->vblank_enabled = false;
  4077. sde_enc->qdss_status = false;
  4078. kthread_init_work(&sde_enc->vsync_event_work,
  4079. sde_encoder_vsync_event_work_handler);
  4080. kthread_init_work(&sde_enc->input_event_work,
  4081. sde_encoder_input_event_work_handler);
  4082. kthread_init_work(&sde_enc->esd_trigger_work,
  4083. sde_encoder_esd_trigger_work_handler);
  4084. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4085. SDE_DEBUG_ENC(sde_enc, "created\n");
  4086. return drm_enc;
  4087. fail:
  4088. SDE_ERROR("failed to create encoder\n");
  4089. if (drm_enc)
  4090. sde_encoder_destroy(drm_enc);
  4091. return ERR_PTR(ret);
  4092. }
  4093. struct drm_encoder *sde_encoder_init(
  4094. struct drm_device *dev,
  4095. struct msm_display_info *disp_info)
  4096. {
  4097. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  4098. }
  4099. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4100. enum msm_event_wait event)
  4101. {
  4102. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4103. struct sde_encoder_virt *sde_enc = NULL;
  4104. int i, ret = 0;
  4105. char atrace_buf[32];
  4106. if (!drm_enc) {
  4107. SDE_ERROR("invalid encoder\n");
  4108. return -EINVAL;
  4109. }
  4110. sde_enc = to_sde_encoder_virt(drm_enc);
  4111. SDE_DEBUG_ENC(sde_enc, "\n");
  4112. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4113. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4114. switch (event) {
  4115. case MSM_ENC_COMMIT_DONE:
  4116. fn_wait = phys->ops.wait_for_commit_done;
  4117. break;
  4118. case MSM_ENC_TX_COMPLETE:
  4119. fn_wait = phys->ops.wait_for_tx_complete;
  4120. break;
  4121. case MSM_ENC_VBLANK:
  4122. fn_wait = phys->ops.wait_for_vblank;
  4123. break;
  4124. case MSM_ENC_ACTIVE_REGION:
  4125. fn_wait = phys->ops.wait_for_active;
  4126. break;
  4127. default:
  4128. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4129. event);
  4130. return -EINVAL;
  4131. }
  4132. if (phys && fn_wait) {
  4133. snprintf(atrace_buf, sizeof(atrace_buf),
  4134. "wait_completion_event_%d", event);
  4135. SDE_ATRACE_BEGIN(atrace_buf);
  4136. ret = fn_wait(phys);
  4137. SDE_ATRACE_END(atrace_buf);
  4138. if (ret)
  4139. return ret;
  4140. }
  4141. }
  4142. return ret;
  4143. }
  4144. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4145. u64 *l_bound, u64 *u_bound)
  4146. {
  4147. struct sde_encoder_virt *sde_enc;
  4148. u64 jitter_ns, frametime_ns;
  4149. struct msm_mode_info *info;
  4150. if (!drm_enc) {
  4151. SDE_ERROR("invalid encoder\n");
  4152. return;
  4153. }
  4154. sde_enc = to_sde_encoder_virt(drm_enc);
  4155. info = &sde_enc->mode_info;
  4156. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4157. jitter_ns = info->jitter_numer * frametime_ns;
  4158. do_div(jitter_ns, info->jitter_denom * 100);
  4159. *l_bound = frametime_ns - jitter_ns;
  4160. *u_bound = frametime_ns + jitter_ns;
  4161. }
  4162. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4163. {
  4164. struct sde_encoder_virt *sde_enc;
  4165. if (!drm_enc) {
  4166. SDE_ERROR("invalid encoder\n");
  4167. return 0;
  4168. }
  4169. sde_enc = to_sde_encoder_virt(drm_enc);
  4170. return sde_enc->mode_info.frame_rate;
  4171. }
  4172. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4173. {
  4174. struct sde_encoder_virt *sde_enc = NULL;
  4175. int i;
  4176. if (!encoder) {
  4177. SDE_ERROR("invalid encoder\n");
  4178. return INTF_MODE_NONE;
  4179. }
  4180. sde_enc = to_sde_encoder_virt(encoder);
  4181. if (sde_enc->cur_master)
  4182. return sde_enc->cur_master->intf_mode;
  4183. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4184. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4185. if (phys)
  4186. return phys->intf_mode;
  4187. }
  4188. return INTF_MODE_NONE;
  4189. }
  4190. static void _sde_encoder_cache_hw_res_cont_splash(
  4191. struct drm_encoder *encoder,
  4192. struct sde_kms *sde_kms)
  4193. {
  4194. int i, idx;
  4195. struct sde_encoder_virt *sde_enc;
  4196. struct sde_encoder_phys *phys_enc;
  4197. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4198. sde_enc = to_sde_encoder_virt(encoder);
  4199. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4200. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4201. sde_enc->hw_pp[i] = NULL;
  4202. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4203. break;
  4204. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4205. }
  4206. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4207. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4208. sde_enc->hw_dsc[i] = NULL;
  4209. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4210. break;
  4211. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4212. }
  4213. /*
  4214. * If we have multiple phys encoders with one controller, make
  4215. * sure to populate the controller pointer in both phys encoders.
  4216. */
  4217. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4218. phys_enc = sde_enc->phys_encs[idx];
  4219. phys_enc->hw_ctl = NULL;
  4220. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4221. SDE_HW_BLK_CTL);
  4222. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4223. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4224. phys_enc->hw_ctl =
  4225. (struct sde_hw_ctl *) ctl_iter.hw;
  4226. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4227. phys_enc->intf_idx, phys_enc->hw_ctl);
  4228. }
  4229. }
  4230. }
  4231. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4232. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4233. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4234. phys->hw_intf = NULL;
  4235. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4236. break;
  4237. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4238. }
  4239. }
  4240. /**
  4241. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4242. * device bootup when cont_splash is enabled
  4243. * @drm_enc: Pointer to drm encoder structure
  4244. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4245. * @enable: boolean indicates enable or displae state of splash
  4246. * @Return: true if successful in updating the encoder structure
  4247. */
  4248. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4249. struct sde_splash_display *splash_display, bool enable)
  4250. {
  4251. struct sde_encoder_virt *sde_enc;
  4252. struct msm_drm_private *priv;
  4253. struct sde_kms *sde_kms;
  4254. struct drm_connector *conn = NULL;
  4255. struct sde_connector *sde_conn = NULL;
  4256. struct sde_connector_state *sde_conn_state = NULL;
  4257. struct drm_display_mode *drm_mode = NULL;
  4258. struct sde_encoder_phys *phys_enc;
  4259. int ret = 0, i;
  4260. if (!encoder) {
  4261. SDE_ERROR("invalid drm enc\n");
  4262. return -EINVAL;
  4263. }
  4264. sde_enc = to_sde_encoder_virt(encoder);
  4265. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4266. if (!sde_kms) {
  4267. SDE_ERROR("invalid sde_kms\n");
  4268. return -EINVAL;
  4269. }
  4270. priv = encoder->dev->dev_private;
  4271. if (!priv->num_connectors) {
  4272. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4273. return -EINVAL;
  4274. }
  4275. SDE_DEBUG_ENC(sde_enc,
  4276. "num of connectors: %d\n", priv->num_connectors);
  4277. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4278. if (!enable) {
  4279. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4280. phys_enc = sde_enc->phys_encs[i];
  4281. if (phys_enc)
  4282. phys_enc->cont_splash_enabled = false;
  4283. }
  4284. return ret;
  4285. }
  4286. if (!splash_display) {
  4287. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4288. return -EINVAL;
  4289. }
  4290. for (i = 0; i < priv->num_connectors; i++) {
  4291. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4292. priv->connectors[i]->base.id);
  4293. sde_conn = to_sde_connector(priv->connectors[i]);
  4294. if (!sde_conn->encoder) {
  4295. SDE_DEBUG_ENC(sde_enc,
  4296. "encoder not attached to connector\n");
  4297. continue;
  4298. }
  4299. if (sde_conn->encoder->base.id
  4300. == encoder->base.id) {
  4301. conn = (priv->connectors[i]);
  4302. break;
  4303. }
  4304. }
  4305. if (!conn || !conn->state) {
  4306. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4307. return -EINVAL;
  4308. }
  4309. sde_conn_state = to_sde_connector_state(conn->state);
  4310. if (!sde_conn->ops.get_mode_info) {
  4311. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4312. return -EINVAL;
  4313. }
  4314. ret = sde_connector_get_mode_info(&sde_conn->base,
  4315. &encoder->crtc->state->adjusted_mode,
  4316. &sde_conn_state->mode_info);
  4317. if (ret) {
  4318. SDE_ERROR_ENC(sde_enc,
  4319. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4320. return ret;
  4321. }
  4322. if (sde_conn->encoder) {
  4323. conn->state->best_encoder = sde_conn->encoder;
  4324. SDE_DEBUG_ENC(sde_enc,
  4325. "configured cstate->best_encoder to ID = %d\n",
  4326. conn->state->best_encoder->base.id);
  4327. } else {
  4328. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4329. conn->base.id);
  4330. }
  4331. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4332. conn->state, false);
  4333. if (ret) {
  4334. SDE_ERROR_ENC(sde_enc,
  4335. "failed to reserve hw resources, %d\n", ret);
  4336. return ret;
  4337. }
  4338. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4339. sde_connector_get_topology_name(conn));
  4340. drm_mode = &encoder->crtc->state->adjusted_mode;
  4341. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4342. drm_mode->hdisplay, drm_mode->vdisplay);
  4343. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4344. if (encoder->bridge) {
  4345. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4346. /*
  4347. * For cont-splash use case, we update the mode
  4348. * configurations manually. This will skip the
  4349. * usually mode set call when actual frame is
  4350. * pushed from framework. The bridge needs to
  4351. * be updated with the current drm mode by
  4352. * calling the bridge mode set ops.
  4353. */
  4354. if (encoder->bridge->funcs) {
  4355. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4356. encoder->bridge->funcs->mode_set(encoder->bridge,
  4357. drm_mode, drm_mode);
  4358. }
  4359. } else {
  4360. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4361. }
  4362. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4363. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4364. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4365. if (!phys) {
  4366. SDE_ERROR_ENC(sde_enc,
  4367. "phys encoders not initialized\n");
  4368. return -EINVAL;
  4369. }
  4370. /* update connector for master and slave phys encoders */
  4371. phys->connector = conn;
  4372. phys->cont_splash_enabled = true;
  4373. phys->hw_pp = sde_enc->hw_pp[i];
  4374. if (phys->ops.cont_splash_mode_set)
  4375. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4376. if (phys->ops.is_master && phys->ops.is_master(phys))
  4377. sde_enc->cur_master = phys;
  4378. }
  4379. return ret;
  4380. }
  4381. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4382. bool skip_pre_kickoff)
  4383. {
  4384. struct msm_drm_thread *event_thread = NULL;
  4385. struct msm_drm_private *priv = NULL;
  4386. struct sde_encoder_virt *sde_enc = NULL;
  4387. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4388. SDE_ERROR("invalid parameters\n");
  4389. return -EINVAL;
  4390. }
  4391. priv = enc->dev->dev_private;
  4392. sde_enc = to_sde_encoder_virt(enc);
  4393. if (!sde_enc->crtc || (sde_enc->crtc->index
  4394. >= ARRAY_SIZE(priv->event_thread))) {
  4395. SDE_DEBUG_ENC(sde_enc,
  4396. "invalid cached CRTC: %d or crtc index: %d\n",
  4397. sde_enc->crtc == NULL,
  4398. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4399. return -EINVAL;
  4400. }
  4401. SDE_EVT32_VERBOSE(DRMID(enc));
  4402. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4403. if (!skip_pre_kickoff) {
  4404. kthread_queue_work(&event_thread->worker,
  4405. &sde_enc->esd_trigger_work);
  4406. kthread_flush_work(&sde_enc->esd_trigger_work);
  4407. }
  4408. /*
  4409. * panel may stop generating te signal (vsync) during esd failure. rsc
  4410. * hardware may hang without vsync. Avoid rsc hang by generating the
  4411. * vsync from watchdog timer instead of panel.
  4412. */
  4413. sde_encoder_helper_switch_vsync(enc, true);
  4414. if (!skip_pre_kickoff)
  4415. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4416. return 0;
  4417. }
  4418. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4419. {
  4420. struct sde_encoder_virt *sde_enc;
  4421. if (!encoder) {
  4422. SDE_ERROR("invalid drm enc\n");
  4423. return false;
  4424. }
  4425. sde_enc = to_sde_encoder_virt(encoder);
  4426. return sde_enc->recovery_events_enabled;
  4427. }
  4428. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4429. bool enabled)
  4430. {
  4431. struct sde_encoder_virt *sde_enc;
  4432. if (!encoder) {
  4433. SDE_ERROR("invalid drm enc\n");
  4434. return;
  4435. }
  4436. sde_enc = to_sde_encoder_virt(encoder);
  4437. sde_enc->recovery_events_enabled = enabled;
  4438. }