cam_packet_util.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/types.h>
  7. #include <linux/slab.h>
  8. #include "cam_mem_mgr.h"
  9. #include "cam_packet_util.h"
  10. #include "cam_debug_util.h"
  11. #include "cam_common_util.h"
  12. #define CAM_UNIQUE_SRC_HDL_MAX 50
  13. #define CAM_PRESIL_UNIQUE_HDL_MAX 50
  14. struct cam_patch_unique_src_buf_tbl {
  15. int32_t hdl;
  16. dma_addr_t iova;
  17. size_t buf_size;
  18. uint32_t flags;
  19. };
  20. int cam_packet_util_get_packet_addr(struct cam_packet **packet,
  21. uint64_t packet_handle, uint32_t offset)
  22. {
  23. uintptr_t packet_addr;
  24. size_t len;
  25. int rc = 0;
  26. if (!packet) {
  27. CAM_ERR(CAM_UTIL, "Invalid parameter packet is NULL");
  28. return -EINVAL;
  29. }
  30. rc = cam_mem_get_cpu_buf(packet_handle, &packet_addr,
  31. &len);
  32. if (rc) {
  33. CAM_ERR(CAM_UTIL, "Failed to get packet address from handle: 0x%llx rc: %d",
  34. packet_handle, rc);
  35. *packet = NULL;
  36. return rc;
  37. }
  38. *packet = (struct cam_packet *)((uint8_t *)packet_addr + offset);
  39. return rc;
  40. }
  41. int cam_packet_util_get_cmd_mem_addr(int handle, uint32_t **buf_addr,
  42. size_t *len)
  43. {
  44. int rc = 0;
  45. uintptr_t kmd_buf_addr = 0;
  46. rc = cam_mem_get_cpu_buf(handle, &kmd_buf_addr, len);
  47. if (rc) {
  48. CAM_ERR(CAM_UTIL, "Unable to get the virtual address %d", rc);
  49. } else {
  50. if (kmd_buf_addr && *len) {
  51. *buf_addr = (uint32_t *)kmd_buf_addr;
  52. } else {
  53. CAM_ERR(CAM_UTIL, "Invalid addr and length :%zd", *len);
  54. rc = -ENOMEM;
  55. }
  56. }
  57. return rc;
  58. }
  59. int cam_packet_util_validate_cmd_desc(struct cam_cmd_buf_desc *cmd_desc)
  60. {
  61. if (!cmd_desc) {
  62. CAM_ERR(CAM_UTIL, "Invalid cmd desc");
  63. return -EINVAL;
  64. }
  65. if ((cmd_desc->length > cmd_desc->size) ||
  66. (cmd_desc->mem_handle <= 0)) {
  67. CAM_ERR(CAM_UTIL, "invalid cmd arg %d %d %d %d",
  68. cmd_desc->offset, cmd_desc->length,
  69. cmd_desc->mem_handle, cmd_desc->size);
  70. return -EINVAL;
  71. }
  72. return 0;
  73. }
  74. int cam_packet_util_validate_packet(struct cam_packet *packet,
  75. size_t remain_len)
  76. {
  77. size_t sum_cmd_desc = 0;
  78. size_t sum_io_cfgs = 0;
  79. size_t sum_patch_desc = 0;
  80. size_t pkt_wo_payload = 0;
  81. if (!packet)
  82. return -EINVAL;
  83. if ((size_t)packet->header.size > remain_len) {
  84. CAM_ERR(CAM_UTIL,
  85. "Invalid packet size: %zu, CPU buf length: %zu",
  86. (size_t)packet->header.size, remain_len);
  87. return -EINVAL;
  88. }
  89. CAM_DBG(CAM_UTIL, "num cmd buf:%d num of io config:%d kmd buf index:%d",
  90. packet->num_cmd_buf, packet->num_io_configs,
  91. packet->kmd_cmd_buf_index);
  92. sum_cmd_desc = packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc);
  93. sum_io_cfgs = packet->num_io_configs * sizeof(struct cam_buf_io_cfg);
  94. sum_patch_desc = packet->num_patches * sizeof(struct cam_patch_desc);
  95. pkt_wo_payload = offsetof(struct cam_packet, payload);
  96. if ((!packet->header.size) ||
  97. ((size_t)packet->header.size <= pkt_wo_payload) ||
  98. ((pkt_wo_payload + (size_t)packet->cmd_buf_offset +
  99. sum_cmd_desc) > (size_t)packet->header.size) ||
  100. ((pkt_wo_payload + (size_t)packet->io_configs_offset +
  101. sum_io_cfgs) > (size_t)packet->header.size) ||
  102. ((pkt_wo_payload + (size_t)packet->patch_offset +
  103. sum_patch_desc) > (size_t)packet->header.size)) {
  104. CAM_ERR(CAM_UTIL, "params not within mem len:%zu %zu %zu %zu",
  105. (size_t)packet->header.size, sum_cmd_desc,
  106. sum_io_cfgs, sum_patch_desc);
  107. return -EINVAL;
  108. }
  109. return 0;
  110. }
  111. int cam_packet_util_get_kmd_buffer(struct cam_packet *packet,
  112. struct cam_kmd_buf_info *kmd_buf)
  113. {
  114. int rc = 0;
  115. size_t len = 0;
  116. size_t remain_len = 0;
  117. struct cam_cmd_buf_desc *cmd_desc;
  118. uint32_t *cpu_addr;
  119. if (!packet || !kmd_buf) {
  120. CAM_ERR(CAM_UTIL, "Invalid arg %pK %pK", packet, kmd_buf);
  121. return -EINVAL;
  122. }
  123. if (!packet->num_cmd_buf) {
  124. CAM_ERR(CAM_UTIL, "Invalid num_cmd_buf = %d", packet->num_cmd_buf);
  125. return -EINVAL;
  126. }
  127. if ((packet->kmd_cmd_buf_index < 0) ||
  128. (packet->kmd_cmd_buf_index >= packet->num_cmd_buf)) {
  129. CAM_ERR(CAM_UTIL, "Invalid kmd buf index: %d",
  130. packet->kmd_cmd_buf_index);
  131. return -EINVAL;
  132. }
  133. /* Take first command descriptor and add offset to it for kmd*/
  134. cmd_desc = (struct cam_cmd_buf_desc *) ((uint8_t *)
  135. &packet->payload + packet->cmd_buf_offset);
  136. cmd_desc += packet->kmd_cmd_buf_index;
  137. rc = cam_packet_util_validate_cmd_desc(cmd_desc);
  138. if (rc)
  139. return rc;
  140. rc = cam_packet_util_get_cmd_mem_addr(cmd_desc->mem_handle, &cpu_addr,
  141. &len);
  142. if (rc)
  143. return rc;
  144. remain_len = len;
  145. if (((size_t)cmd_desc->offset >= len) ||
  146. ((size_t)cmd_desc->size > (len - (size_t)cmd_desc->offset))) {
  147. CAM_ERR(CAM_UTIL, "invalid memory len:%zd and cmd desc size:%d",
  148. len, cmd_desc->size);
  149. return -EINVAL;
  150. }
  151. remain_len -= (size_t)cmd_desc->offset;
  152. if ((size_t)packet->kmd_cmd_buf_offset >= remain_len) {
  153. CAM_ERR(CAM_UTIL, "Invalid kmd cmd buf offset: %zu",
  154. (size_t)packet->kmd_cmd_buf_offset);
  155. return -EINVAL;
  156. }
  157. cpu_addr += (cmd_desc->offset / 4) + (packet->kmd_cmd_buf_offset / 4);
  158. CAM_DBG(CAM_UTIL, "total size %d, cmd size: %d, KMD buffer size: %d",
  159. cmd_desc->size, cmd_desc->length,
  160. cmd_desc->size - cmd_desc->length);
  161. CAM_DBG(CAM_UTIL, "hdl 0x%x, cmd offset %d, kmd offset %d, addr 0x%pK",
  162. cmd_desc->mem_handle, cmd_desc->offset,
  163. packet->kmd_cmd_buf_offset, cpu_addr);
  164. kmd_buf->cpu_addr = cpu_addr;
  165. kmd_buf->handle = cmd_desc->mem_handle;
  166. kmd_buf->offset = cmd_desc->offset + packet->kmd_cmd_buf_offset;
  167. kmd_buf->size = cmd_desc->size - cmd_desc->length;
  168. kmd_buf->used_bytes = 0;
  169. return rc;
  170. }
  171. void cam_packet_util_dump_patch_info(struct cam_packet *packet,
  172. int32_t iommu_hdl, int32_t sec_iommu_hdl, struct cam_hw_dump_pf_args *pf_args)
  173. {
  174. struct cam_patch_desc *patch_desc = NULL;
  175. struct cam_context_pf_info *pf_context_info = NULL;
  176. dma_addr_t iova_addr;
  177. size_t dst_buf_len;
  178. size_t src_buf_size;
  179. int i, rc = 0;
  180. int32_t hdl;
  181. uintptr_t cpu_addr = 0;
  182. uint32_t *dst_cpu_addr;
  183. uint32_t flags, buf_fd;
  184. uint32_t value = 0;
  185. if (!packet) {
  186. CAM_ERR(CAM_UTIL, "Invalid packet");
  187. return;
  188. }
  189. patch_desc = (struct cam_patch_desc *)
  190. ((uint32_t *) &packet->payload +
  191. packet->patch_offset/4);
  192. if (pf_args) {
  193. pf_context_info = &(pf_args->pf_context_info);
  194. buf_fd = pf_args->pf_smmu_info->buf_info;
  195. }
  196. CAM_INFO(CAM_UTIL, "Total num of patches : %d",
  197. packet->num_patches);
  198. for (i = 0; i < packet->num_patches; i++) {
  199. hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ?
  200. sec_iommu_hdl : iommu_hdl;
  201. rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl,
  202. hdl, &iova_addr, &src_buf_size, &flags);
  203. if (rc < 0) {
  204. CAM_ERR(CAM_UTIL,
  205. "unable to get src buf address for hdl 0x%x",
  206. hdl);
  207. return;
  208. }
  209. if (pf_args &&
  210. GET_FD_FROM_HANDLE(patch_desc[i].src_buf_hdl) == buf_fd &&
  211. pf_context_info->mem_type == CAM_FAULT_BUF_NOT_FOUND) {
  212. /* found PF at this hdl */
  213. pf_context_info->mem_type = CAM_FAULT_PATCH_BUF;
  214. pf_context_info->patch_idx = i;
  215. pf_context_info->buf_hdl = patch_desc[i].src_buf_hdl;
  216. pf_context_info->offset = patch_desc[i].src_offset;
  217. pf_context_info->mem_flag = flags;
  218. pf_context_info->delta =
  219. CAM_SMMU_GET_IOVA_DELTA(pf_args->pf_smmu_info->iova, iova_addr);
  220. pf_context_info->req_id = packet->header.request_id;
  221. pf_context_info->ctx_found = true;
  222. CAM_ERR(CAM_UTIL, "Found PF at patch: %d src buf hdl: 0x%llx",
  223. i, patch_desc[i].src_buf_hdl);
  224. }
  225. rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl,
  226. &cpu_addr, &dst_buf_len);
  227. if (rc < 0 || !cpu_addr || (dst_buf_len == 0)) {
  228. CAM_ERR(CAM_UTIL, "unable to get dst buf address");
  229. return;
  230. }
  231. dst_cpu_addr = (uint32_t *)cpu_addr;
  232. dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr +
  233. patch_desc[i].dst_offset);
  234. value = *dst_cpu_addr;
  235. CAM_INFO(CAM_UTIL,
  236. "i = %d src_buf 0x%llx src_hdl 0x%x src_buf_with_offset 0x%llx src_size 0x%llx src_flags: %x dst %p dst_offset %u dst_hdl 0x%x value 0x%x",
  237. i, iova_addr, patch_desc[i].src_buf_hdl,
  238. (iova_addr + patch_desc[i].src_offset),
  239. src_buf_size, flags, dst_cpu_addr,
  240. patch_desc[i].dst_offset,
  241. patch_desc[i].dst_buf_hdl, value);
  242. if (!(*dst_cpu_addr))
  243. CAM_ERR(CAM_ICP, "Null at dst addr %p", dst_cpu_addr);
  244. }
  245. }
  246. static int cam_packet_util_get_patch_iova(
  247. struct cam_patch_unique_src_buf_tbl *tbl,
  248. int32_t hdl, uint32_t buf_hdl, dma_addr_t *iova,
  249. size_t *buf_size, uint32_t *flags)
  250. {
  251. int idx = 0;
  252. int rc = 0;
  253. size_t src_buf_size;
  254. dma_addr_t iova_addr;
  255. bool is_found = false;
  256. for (idx = 0; idx < CAM_UNIQUE_SRC_HDL_MAX; idx++) {
  257. if (buf_hdl == tbl[idx].hdl) {
  258. CAM_DBG(CAM_UTIL,
  259. "Matched entry for src_buf_hdl: 0x%x with src_hdl[%d]: 0x%x",
  260. buf_hdl, idx, tbl[idx].hdl);
  261. *iova = tbl[idx].iova;
  262. *buf_size = tbl[idx].buf_size;
  263. *flags = tbl[idx].flags;
  264. is_found = true;
  265. break;
  266. } else if ((tbl[idx].hdl == 0) || (tbl[idx].iova == 0)) {
  267. CAM_DBG(CAM_UTIL, "New src handle detected 0x%x", buf_hdl);
  268. is_found = false;
  269. break;
  270. }
  271. CAM_DBG(CAM_UTIL,
  272. "Index: %d is filled with differnt src_hdl: 0x%x",
  273. idx, buf_hdl);
  274. }
  275. if (!is_found) {
  276. CAM_DBG(CAM_UTIL, "src_hdl 0x%x not found in table entries",
  277. buf_hdl);
  278. rc = cam_mem_get_io_buf(buf_hdl, hdl, &iova_addr, &src_buf_size, flags);
  279. if (rc < 0) {
  280. CAM_ERR(CAM_UTIL,
  281. "unable to get iova for src_hdl: 0x%x",
  282. buf_hdl);
  283. return rc;
  284. }
  285. /* Update the table entry with unique src buf handle */
  286. if (idx < CAM_UNIQUE_SRC_HDL_MAX && tbl[idx].hdl == 0) {
  287. tbl[idx].buf_size = src_buf_size;
  288. tbl[idx].iova = iova_addr;
  289. tbl[idx].hdl = buf_hdl;
  290. tbl[idx].flags = *flags;
  291. CAM_DBG(CAM_UTIL,
  292. "Updated table index: %d with src_buf_hdl: 0x%x flags: %x",
  293. idx, tbl[idx].hdl, *flags);
  294. }
  295. *iova = iova_addr;
  296. *buf_size = src_buf_size;
  297. }
  298. return rc;
  299. }
  300. int cam_packet_util_process_patches(struct cam_packet *packet,
  301. int32_t iommu_hdl, int32_t sec_mmu_hdl, bool exp_mem)
  302. {
  303. struct cam_patch_desc *patch_desc = NULL;
  304. dma_addr_t iova_addr;
  305. uintptr_t cpu_addr = 0;
  306. dma_addr_t temp;
  307. uint32_t *dst_cpu_addr;
  308. size_t dst_buf_len;
  309. size_t src_buf_size;
  310. int i = 0;
  311. int rc = 0;
  312. uint32_t flags = 0;
  313. int32_t hdl;
  314. struct cam_patch_unique_src_buf_tbl
  315. tbl[CAM_UNIQUE_SRC_HDL_MAX];
  316. memset(tbl, 0, CAM_UNIQUE_SRC_HDL_MAX *
  317. sizeof(struct cam_patch_unique_src_buf_tbl));
  318. /* process patch descriptor */
  319. patch_desc = (struct cam_patch_desc *)
  320. ((uint32_t *) &packet->payload +
  321. packet->patch_offset/4);
  322. CAM_DBG(CAM_UTIL, "packet = %pK patch_desc = %pK size = %lu",
  323. (void *)packet, (void *)patch_desc,
  324. sizeof(struct cam_patch_desc));
  325. for (i = 0; i < packet->num_patches; i++) {
  326. hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ?
  327. sec_mmu_hdl : iommu_hdl;
  328. rc = cam_packet_util_get_patch_iova(&tbl[0], hdl,
  329. patch_desc[i].src_buf_hdl, &iova_addr, &src_buf_size, &flags);
  330. if (rc) {
  331. CAM_ERR(CAM_UTIL,
  332. "get_iova failed for patch[%d], src_buf_hdl: 0x%x: rc: %d",
  333. i, patch_desc[i].src_buf_hdl, rc);
  334. return rc;
  335. }
  336. if ((size_t)patch_desc[i].src_offset >= src_buf_size) {
  337. CAM_ERR(CAM_UTIL,
  338. "Invalid src buf patch offset: patch:src_offset: 0x%x, src_buf_size: %zu",
  339. patch_desc[i].src_offset, src_buf_size);
  340. return -EINVAL;
  341. }
  342. temp = iova_addr;
  343. rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl,
  344. &cpu_addr, &dst_buf_len);
  345. if (rc < 0 || !cpu_addr || (dst_buf_len == 0)) {
  346. CAM_ERR(CAM_UTIL, "unable to get dst buf address");
  347. return rc;
  348. }
  349. dst_cpu_addr = (uint32_t *)cpu_addr;
  350. CAM_DBG(CAM_UTIL, "i = %d patch info = %x %x %x %x", i,
  351. patch_desc[i].dst_buf_hdl, patch_desc[i].dst_offset,
  352. patch_desc[i].src_buf_hdl, patch_desc[i].src_offset);
  353. if ((dst_buf_len < sizeof(void *)) ||
  354. ((dst_buf_len - sizeof(void *)) <
  355. (size_t)patch_desc[i].dst_offset)) {
  356. CAM_ERR(CAM_UTIL,
  357. "Invalid dst buf patch offset");
  358. return -EINVAL;
  359. }
  360. dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr +
  361. patch_desc[i].dst_offset);
  362. temp += patch_desc[i].src_offset;
  363. if (exp_mem && cam_smmu_is_expanded_memory()) {
  364. if ((flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  365. (flags & CAM_MEM_FLAG_CMD_BUF_TYPE)) {
  366. *dst_cpu_addr = temp;
  367. } else {
  368. if (CAM_36BIT_INTF_GET_IOVA_OFFSET(temp))
  369. CAM_ERR(CAM_UTIL,
  370. "Buffer address 0x%lx not aligned to 256bytes",
  371. temp);
  372. *dst_cpu_addr = CAM_36BIT_INTF_GET_IOVA_BASE(temp);
  373. }
  374. } else {
  375. *dst_cpu_addr = temp;
  376. }
  377. CAM_DBG(CAM_UTIL,
  378. "patch is done for dst %pK with base iova 0x%lx final iova 0x%lx patched value 0x%x, shared=%s, cmd=%s, HwAndCDM %s",
  379. dst_cpu_addr, iova_addr, temp, *dst_cpu_addr,
  380. CAM_BOOL_TO_YESNO(flags & CAM_MEM_FLAG_HW_SHARED_ACCESS),
  381. CAM_BOOL_TO_YESNO(flags & CAM_MEM_FLAG_CMD_BUF_TYPE),
  382. CAM_BOOL_TO_YESNO(flags & CAM_MEM_FLAG_HW_AND_CDM_OR_SHARED));
  383. }
  384. return rc;
  385. }
  386. void cam_packet_util_dump_io_bufs(struct cam_packet *packet,
  387. int32_t iommu_hdl, int32_t sec_mmu_hdl,
  388. struct cam_hw_dump_pf_args *pf_args, bool res_id_support)
  389. {
  390. struct cam_buf_io_cfg *io_cfg;
  391. struct cam_context_pf_info *pf_context_info;
  392. int32_t mmu_hdl, buf_fd;
  393. dma_addr_t iova_addr;
  394. size_t src_buf_size;
  395. int i, j, rc = 0;
  396. uint32_t resource_type;
  397. if (!packet) {
  398. CAM_ERR(CAM_UTIL, "Invalid packet");
  399. return;
  400. }
  401. io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload +
  402. packet->io_configs_offset / 4);
  403. buf_fd = pf_args->pf_smmu_info->buf_info;
  404. pf_context_info = &(pf_args->pf_context_info);
  405. resource_type = pf_context_info->resource_type;
  406. for (i = 0; i < packet->num_io_configs; i++) {
  407. if (res_id_support && io_cfg[i].resource_type !=
  408. pf_context_info->resource_type)
  409. continue;
  410. for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) {
  411. if (!io_cfg[i].mem_handle[j])
  412. break;
  413. CAM_INFO(CAM_UTIL, "port: 0x%x f: %u format: %d dir %d",
  414. io_cfg[i].resource_type,
  415. io_cfg[i].fence,
  416. io_cfg[i].format,
  417. io_cfg[i].direction);
  418. mmu_hdl = cam_mem_is_secure_buf(
  419. io_cfg[i].mem_handle[j]) ? sec_mmu_hdl :
  420. iommu_hdl;
  421. rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j],
  422. mmu_hdl, &iova_addr, &src_buf_size, NULL);
  423. if (rc < 0) {
  424. CAM_ERR(CAM_UTIL,
  425. "get src buf address fail mem_handle 0x%x",
  426. io_cfg[i].mem_handle[j]);
  427. continue;
  428. }
  429. if (GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == buf_fd) {
  430. pf_context_info->mem_type = CAM_FAULT_IO_CFG_BUF;
  431. pf_context_info->buf_hdl = io_cfg[i].mem_handle[j];
  432. pf_context_info->offset = io_cfg[i].offsets[j];
  433. pf_context_info->resource_type = io_cfg[i].resource_type;
  434. pf_context_info->delta =
  435. CAM_SMMU_GET_IOVA_DELTA(pf_args->pf_smmu_info->iova,
  436. iova_addr);
  437. pf_context_info->req_id = packet->header.request_id;
  438. pf_context_info->ctx_found = true;
  439. resource_type = pf_context_info->resource_type;
  440. CAM_INFO(CAM_UTIL,
  441. "Found PF at port: 0x%x mem 0x%x fd: %d plane id: %d delta: %llu",
  442. io_cfg[i].resource_type,
  443. io_cfg[i].mem_handle[j],
  444. buf_fd,
  445. j, pf_context_info->delta);
  446. }
  447. CAM_INFO(CAM_UTIL,
  448. "pln %d w %d h %d s %u size %zu addr 0x%llx end_addr 0x%llx offset %u memh 0x%x",
  449. j, io_cfg[i].planes[j].width,
  450. io_cfg[i].planes[j].height,
  451. io_cfg[i].planes[j].plane_stride,
  452. src_buf_size, iova_addr,
  453. iova_addr + src_buf_size,
  454. io_cfg[i].offsets[j],
  455. io_cfg[i].mem_handle[j]);
  456. }
  457. if (res_id_support)
  458. return;
  459. }
  460. if (res_id_support)
  461. CAM_ERR(CAM_UTIL,
  462. "getting io port for mid resource id failed req id: %llu res id: 0x%x",
  463. packet->header.request_id, resource_type);
  464. }
  465. int cam_packet_util_process_generic_cmd_buffer(
  466. struct cam_cmd_buf_desc *cmd_buf,
  467. cam_packet_generic_blob_handler blob_handler_cb, void *user_data)
  468. {
  469. int rc = 0;
  470. uintptr_t cpu_addr = 0;
  471. size_t buf_size;
  472. size_t remain_len = 0;
  473. uint32_t *blob_ptr;
  474. uint32_t blob_type, blob_size, blob_block_size, len_read;
  475. if (!cmd_buf || !blob_handler_cb) {
  476. CAM_ERR(CAM_UTIL, "Invalid args %pK %pK",
  477. cmd_buf, blob_handler_cb);
  478. return -EINVAL;
  479. }
  480. if (!cmd_buf->length || !cmd_buf->size) {
  481. CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d",
  482. cmd_buf->length, cmd_buf->size);
  483. return -EINVAL;
  484. }
  485. rc = cam_mem_get_cpu_buf(cmd_buf->mem_handle, &cpu_addr, &buf_size);
  486. if (rc || !cpu_addr || (buf_size == 0)) {
  487. CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK",
  488. rc, (void *)cpu_addr);
  489. return rc;
  490. }
  491. remain_len = buf_size;
  492. if ((buf_size < sizeof(uint32_t)) ||
  493. ((size_t)cmd_buf->offset > (buf_size - sizeof(uint32_t)))) {
  494. CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu",
  495. (size_t)cmd_buf->offset);
  496. return -EINVAL;
  497. }
  498. remain_len -= (size_t)cmd_buf->offset;
  499. if (remain_len < (size_t)cmd_buf->length) {
  500. CAM_ERR(CAM_UTIL, "Invalid length for cmd buf: %zu",
  501. (size_t)cmd_buf->length);
  502. return -EINVAL;
  503. }
  504. blob_ptr = (uint32_t *)(((uint8_t *)cpu_addr) +
  505. cmd_buf->offset);
  506. CAM_DBG(CAM_UTIL,
  507. "GenericCmdBuffer cpuaddr=%pK, blobptr=%pK, len=%d",
  508. (void *)cpu_addr, (void *)blob_ptr, cmd_buf->length);
  509. len_read = 0;
  510. while (len_read < cmd_buf->length) {
  511. blob_type =
  512. ((*blob_ptr) & CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK) >>
  513. CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT;
  514. blob_size =
  515. ((*blob_ptr) & CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK) >>
  516. CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT;
  517. blob_block_size = sizeof(uint32_t) +
  518. (((blob_size + sizeof(uint32_t) - 1) /
  519. sizeof(uint32_t)) * sizeof(uint32_t));
  520. CAM_DBG(CAM_UTIL,
  521. "Blob type=%d size=%d block_size=%d len_read=%d total=%d",
  522. blob_type, blob_size, blob_block_size, len_read,
  523. cmd_buf->length);
  524. if (len_read + blob_block_size > cmd_buf->length) {
  525. CAM_ERR(CAM_UTIL, "Invalid Blob %d %d %d %d",
  526. blob_type, blob_size, len_read,
  527. cmd_buf->length);
  528. rc = -EINVAL;
  529. goto end;
  530. }
  531. len_read += blob_block_size;
  532. rc = blob_handler_cb(user_data, blob_type, blob_size,
  533. (uint8_t *)(blob_ptr + 1));
  534. if (rc) {
  535. CAM_ERR(CAM_UTIL, "Error in handling blob type %d %d",
  536. blob_type, blob_size);
  537. goto end;
  538. }
  539. blob_ptr += (blob_block_size / sizeof(uint32_t));
  540. }
  541. end:
  542. return rc;
  543. }
  544. int cam_presil_retrieve_buffers_from_packet(struct cam_packet *packet, int iommu_hdl,
  545. int out_res_id)
  546. {
  547. int rc = 0, i, j;
  548. struct cam_buf_io_cfg *io_cfg = NULL;
  549. dma_addr_t io_addr[CAM_PACKET_MAX_PLANES];
  550. size_t size;
  551. if (!packet || (iommu_hdl < 0)) {
  552. CAM_ERR(CAM_PRESIL, "Invalid params packet %pK iommu_hdl: %d", packet, iommu_hdl);
  553. return -EINVAL;
  554. }
  555. CAM_DBG(CAM_PRESIL, "Retrieving output buffer corresponding to res: 0x%x", out_res_id);
  556. io_cfg = (struct cam_buf_io_cfg *)((uint8_t *)&packet->payload + packet->io_configs_offset);
  557. for (i = 0; i < packet->num_io_configs; i++) {
  558. if ((io_cfg[i].direction != CAM_BUF_OUTPUT) ||
  559. (io_cfg[i].resource_type != out_res_id))
  560. continue;
  561. memset(io_addr, 0, sizeof(io_addr));
  562. for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) {
  563. if (!io_cfg[i].mem_handle[j])
  564. break;
  565. rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], iommu_hdl, &io_addr[j],
  566. &size, NULL);
  567. if (rc) {
  568. CAM_ERR(CAM_PRESIL, "no io addr for plane%d", j);
  569. rc = -ENOMEM;
  570. return rc;
  571. }
  572. /* For presil, address should be within 32 bit */
  573. if (io_addr[j] >> 32) {
  574. CAM_ERR(CAM_PRESIL,
  575. "Invalid address, presil mapped address should be 32 bit");
  576. rc = -EINVAL;
  577. return rc;
  578. }
  579. CAM_INFO(CAM_PRESIL,
  580. "Retrieving IO CFG buffer:%d addr: 0x%x offset 0x%x res_id: 0x%x",
  581. io_cfg[i].mem_handle[j], io_addr[j], io_cfg[i].offsets[j],
  582. io_cfg[i].resource_type);
  583. cam_mem_mgr_retrieve_buffer_from_presil(io_cfg[i].mem_handle[j], size,
  584. io_cfg[i].offsets[j], iommu_hdl);
  585. }
  586. }
  587. return rc;
  588. }
  589. static void cam_presil_add_unique_buf_hdl_to_list(int32_t buf_hdl,
  590. int32_t *hdl_list, int *num_hdls, int max_handles)
  591. {
  592. int k;
  593. bool hdl_found = false;
  594. if (!buf_hdl)
  595. return;
  596. if (*num_hdls >= max_handles) {
  597. CAM_ERR(CAM_PRESIL, "Failed to add entry num_hdls: %d max_handles:%d", *num_hdls,
  598. max_handles);
  599. return;
  600. }
  601. for (k = 0; k < *num_hdls; k++) {
  602. if (hdl_list[k] == buf_hdl) {
  603. hdl_found = true;
  604. break;
  605. }
  606. }
  607. if (!hdl_found)
  608. hdl_list[(*num_hdls)++] = buf_hdl;
  609. }
  610. int cam_presil_send_buffers_from_packet(struct cam_packet *packet, int img_iommu_hdl,
  611. int cdm_iommu_hdl)
  612. {
  613. struct cam_buf_io_cfg *io_cfg = NULL;
  614. struct cam_cmd_buf_desc *cmd_desc = NULL;
  615. struct cam_patch_desc *patch_desc = NULL;
  616. int i, j, rc = 0;
  617. int32_t unique_img_buffers[CAM_PRESIL_UNIQUE_HDL_MAX] = {0};
  618. int32_t unique_cmd_buffers[CAM_PRESIL_UNIQUE_HDL_MAX] = {0};
  619. int num_img_handles = 0, num_cmd_handles = 0;
  620. if(!packet) {
  621. CAM_ERR(CAM_PRESIL, "Packet is NULL");
  622. return -EINVAL;
  623. }
  624. if (img_iommu_hdl == -1) {
  625. goto send_cmd_buffers;
  626. }
  627. /* Adding IO config buffer handles to list*/
  628. io_cfg = (struct cam_buf_io_cfg *)((uint8_t *)&packet->payload + packet->io_configs_offset);
  629. for (i = 0; i < packet->num_io_configs; i++) {
  630. if (io_cfg[i].direction == CAM_BUF_OUTPUT)
  631. continue;
  632. for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) {
  633. if (!io_cfg[i].mem_handle[j])
  634. break;
  635. CAM_DBG(CAM_PRESIL, "Adding IO CFG buffer:%d", io_cfg[i].mem_handle[j]);
  636. cam_presil_add_unique_buf_hdl_to_list(io_cfg[i].mem_handle[j],
  637. unique_img_buffers, &num_img_handles, CAM_PRESIL_UNIQUE_HDL_MAX);
  638. }
  639. }
  640. for (i = 0; i < num_img_handles; i++) {
  641. CAM_DBG(CAM_PRESIL, "Sending Image buffer i:%d mem_handle:%d", i,
  642. unique_img_buffers[i]);
  643. rc = cam_mem_mgr_send_buffer_to_presil(img_iommu_hdl,
  644. unique_img_buffers[i]);
  645. if (rc) {
  646. CAM_ERR(CAM_PRESIL, "Failed to send buffer i:%d mem_handle:%d rc:%d",
  647. i, unique_img_buffers[i], rc);
  648. return rc;
  649. }
  650. }
  651. send_cmd_buffers:
  652. if (cdm_iommu_hdl == -1) {
  653. goto end;
  654. }
  655. /* Adding CMD buffer handles to list*/
  656. cmd_desc = (struct cam_cmd_buf_desc *) ((uint8_t *)&packet->payload +
  657. packet->cmd_buf_offset);
  658. for (i = 0; i < packet->num_cmd_buf; i++) {
  659. CAM_DBG(CAM_PRESIL, "Adding CMD buffer:%d", cmd_desc[i].mem_handle);
  660. cam_presil_add_unique_buf_hdl_to_list(cmd_desc[i].mem_handle,
  661. unique_cmd_buffers, &num_cmd_handles, CAM_PRESIL_UNIQUE_HDL_MAX);
  662. }
  663. /* Adding Patch src buffer handles to list */
  664. patch_desc = (struct cam_patch_desc *) ((uint8_t *)&packet->payload + packet->patch_offset);
  665. for (i = 0; i < packet->num_patches; i++) {
  666. CAM_DBG(CAM_PRESIL, "Adding Patch src buffer:%d", patch_desc[i].src_buf_hdl);
  667. cam_presil_add_unique_buf_hdl_to_list(patch_desc[i].src_buf_hdl,
  668. unique_cmd_buffers, &num_cmd_handles, CAM_PRESIL_UNIQUE_HDL_MAX);
  669. }
  670. for (i = 0; i < num_cmd_handles; i++) {
  671. CAM_DBG(CAM_PRESIL, "Sending Command buffer i:%d mem_handle:%d", i,
  672. unique_cmd_buffers[i]);
  673. rc = cam_mem_mgr_send_buffer_to_presil(cdm_iommu_hdl,
  674. unique_cmd_buffers[i]);
  675. if (rc) {
  676. CAM_ERR(CAM_PRESIL, "Failed to send buffer i:%d mem_handle:%d rc:%d",
  677. i, unique_cmd_buffers[i], rc);
  678. return rc;
  679. }
  680. }
  681. end:
  682. return rc;
  683. }