wcd937x.c 84 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include "internal.h"
  20. #include "wcd937x.h"
  21. #include <asoc/wcdcal-hwdep.h>
  22. #include "wcd937x-registers.h"
  23. #include <asoc/msm-cdc-pinctrl.h>
  24. #include <dt-bindings/sound/audio-codec-port-types.h>
  25. #include <asoc/msm-cdc-supply.h>
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. enum {
  35. CODEC_TX = 0,
  36. CODEC_RX,
  37. };
  38. enum {
  39. ALLOW_BUCK_DISABLE,
  40. HPH_COMP_DELAY,
  41. HPH_PA_DELAY,
  42. };
  43. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  44. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  45. static int wcd937x_handle_post_irq(void *data);
  46. static int wcd937x_reset(struct device *dev);
  47. static int wcd937x_reset_low(struct device *dev);
  48. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  49. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  50. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  69. };
  70. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  71. .name = "wcd937x",
  72. .irqs = wcd937x_irqs,
  73. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  74. .num_regs = 3,
  75. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  76. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  77. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  78. .use_ack = 1,
  79. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  80. .runtime_pm = false,
  81. .handle_post_irq = wcd937x_handle_post_irq,
  82. .irq_drv_data = NULL,
  83. };
  84. static int wcd937x_handle_post_irq(void *data)
  85. {
  86. struct wcd937x_priv *wcd937x = data;
  87. u32 status1 = 0, status2 = 0, status3 = 0;
  88. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  89. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  90. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  91. wcd937x->tx_swr_dev->slave_irq_pending =
  92. ((status1 || status2 || status3) ? true : false);
  93. return IRQ_HANDLED;
  94. }
  95. static int wcd937x_init_reg(struct snd_soc_component *component)
  96. {
  97. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  98. 0x0E, 0x0E);
  99. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  100. 0x80, 0x80);
  101. usleep_range(1000, 1010);
  102. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  103. 0x40, 0x40);
  104. usleep_range(1000, 1010);
  105. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  106. 0x10, 0x00);
  107. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  108. 0xF0, 0x80);
  109. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  110. 0x80, 0x80);
  111. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  112. 0x40, 0x40);
  113. usleep_range(10000, 10010);
  114. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  115. 0x40, 0x00);
  116. snd_soc_component_update_bits(component,
  117. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  118. 0xFF, 0xD9);
  119. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  120. 0xFF, 0xFA);
  121. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  122. 0xFF, 0xFA);
  123. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  124. 0xFF, 0xFA);
  125. return 0;
  126. }
  127. static int wcd937x_set_port_params(struct snd_soc_component *component,
  128. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  129. u8 *ch_mask, u32 *ch_rate,
  130. u8 *port_type, u8 path)
  131. {
  132. int i, j;
  133. u8 num_ports = 0;
  134. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  135. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  136. switch (path) {
  137. case CODEC_RX:
  138. map = &wcd937x->rx_port_mapping;
  139. num_ports = wcd937x->num_rx_ports;
  140. break;
  141. case CODEC_TX:
  142. map = &wcd937x->tx_port_mapping;
  143. num_ports = wcd937x->num_tx_ports;
  144. break;
  145. }
  146. for (i = 0; i <= num_ports; i++) {
  147. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  148. if ((*map)[i][j].slave_port_type == slv_prt_type)
  149. goto found;
  150. }
  151. }
  152. found:
  153. if (i > num_ports || j == MAX_CH_PER_PORT) {
  154. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  155. __func__, slv_prt_type);
  156. return -EINVAL;
  157. }
  158. *port_id = i;
  159. *num_ch = (*map)[i][j].num_ch;
  160. *ch_mask = (*map)[i][j].ch_mask;
  161. *ch_rate = (*map)[i][j].ch_rate;
  162. *port_type = (*map)[i][j].master_port_type;
  163. return 0;
  164. }
  165. static int wcd937x_parse_port_mapping(struct device *dev,
  166. char *prop, u8 path)
  167. {
  168. u32 *dt_array, map_size, map_length;
  169. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  170. u32 slave_port_type, master_port_type;
  171. u32 i, ch_iter = 0;
  172. int ret = 0;
  173. u8 *num_ports = NULL;
  174. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  175. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  176. switch (path) {
  177. case CODEC_RX:
  178. map = &wcd937x->rx_port_mapping;
  179. num_ports = &wcd937x->num_rx_ports;
  180. break;
  181. case CODEC_TX:
  182. map = &wcd937x->tx_port_mapping;
  183. num_ports = &wcd937x->num_tx_ports;
  184. break;
  185. }
  186. if (!of_find_property(dev->of_node, prop,
  187. &map_size)) {
  188. dev_err(dev, "missing port mapping prop %s\n", prop);
  189. ret = -EINVAL;
  190. goto err;
  191. }
  192. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  193. dt_array = kzalloc(map_size, GFP_KERNEL);
  194. if (!dt_array) {
  195. ret = -ENOMEM;
  196. goto err;
  197. }
  198. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  199. NUM_SWRS_DT_PARAMS * map_length);
  200. if (ret) {
  201. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  202. __func__, prop);
  203. ret = -EINVAL;
  204. goto err_pdata_fail;
  205. }
  206. for (i = 0; i < map_length; i++) {
  207. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  208. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  209. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  210. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  211. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  212. if (port_num != old_port_num)
  213. ch_iter = 0;
  214. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  215. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  216. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  217. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  218. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  219. old_port_num = port_num;
  220. }
  221. *num_ports = port_num;
  222. kfree(dt_array);
  223. return 0;
  224. err_pdata_fail:
  225. kfree(dt_array);
  226. err:
  227. return ret;
  228. }
  229. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  230. u8 slv_port_type, u8 enable)
  231. {
  232. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  233. u8 port_id;
  234. u8 num_ch;
  235. u8 ch_mask;
  236. u32 ch_rate;
  237. u8 port_type;
  238. u8 num_port = 1;
  239. int ret = 0;
  240. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  241. &num_ch, &ch_mask, &ch_rate,
  242. &port_type, CODEC_TX);
  243. if (ret)
  244. return ret;
  245. if (enable)
  246. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  247. num_port, &ch_mask, &ch_rate,
  248. &num_ch, &port_type);
  249. else
  250. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  251. num_port, &ch_mask, &port_type);
  252. return ret;
  253. }
  254. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  255. u8 slv_port_type, u8 enable)
  256. {
  257. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  258. u8 port_id;
  259. u8 num_ch;
  260. u8 ch_mask;
  261. u32 ch_rate;
  262. u8 port_type;
  263. u8 num_port = 1;
  264. int ret = 0;
  265. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  266. &num_ch, &ch_mask, &ch_rate,
  267. &port_type, CODEC_RX);
  268. if (ret)
  269. return ret;
  270. if (enable)
  271. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  272. num_port, &ch_mask, &ch_rate,
  273. &num_ch, &port_type);
  274. else
  275. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  276. num_port, &ch_mask, &port_type);
  277. return ret;
  278. }
  279. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  280. {
  281. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  282. if (wcd937x->rx_clk_cnt == 0) {
  283. snd_soc_component_update_bits(component,
  284. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  285. snd_soc_component_update_bits(component,
  286. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  287. snd_soc_component_update_bits(component,
  288. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  289. snd_soc_component_update_bits(component,
  290. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  291. snd_soc_component_update_bits(component,
  292. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  293. snd_soc_component_update_bits(component,
  294. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  295. snd_soc_component_update_bits(component,
  296. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  297. }
  298. wcd937x->rx_clk_cnt++;
  299. return 0;
  300. }
  301. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  302. {
  303. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  304. if (wcd937x->rx_clk_cnt == 0) {
  305. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  306. return 0;
  307. }
  308. wcd937x->rx_clk_cnt--;
  309. if (wcd937x->rx_clk_cnt == 0) {
  310. snd_soc_component_update_bits(component,
  311. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  312. snd_soc_component_update_bits(component,
  313. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  314. 0x02, 0x00);
  315. snd_soc_component_update_bits(component,
  316. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  317. 0x01, 0x00);
  318. }
  319. return 0;
  320. }
  321. /*
  322. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  323. * @component: handle to snd_soc_component *
  324. *
  325. * return wcd937x_mbhc handle or error code in case of failure
  326. */
  327. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  328. {
  329. struct wcd937x_priv *wcd937x;
  330. if (!component) {
  331. pr_err("%s: Invalid params, NULL component\n", __func__);
  332. return NULL;
  333. }
  334. wcd937x = snd_soc_component_get_drvdata(component);
  335. if (!wcd937x) {
  336. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  337. return NULL;
  338. }
  339. return wcd937x->mbhc;
  340. }
  341. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  342. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  343. struct snd_kcontrol *kcontrol,
  344. int event)
  345. {
  346. struct snd_soc_component *component =
  347. snd_soc_dapm_to_component(w->dapm);
  348. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  349. int hph_mode = wcd937x->hph_mode;
  350. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  351. w->name, event);
  352. switch (event) {
  353. case SND_SOC_DAPM_PRE_PMU:
  354. wcd937x_rx_clk_enable(component);
  355. snd_soc_component_update_bits(component,
  356. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  357. 0x01, 0x01);
  358. snd_soc_component_update_bits(component,
  359. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  360. 0x04, 0x04);
  361. snd_soc_component_update_bits(component,
  362. WCD937X_HPH_RDAC_CLK_CTL1,
  363. 0x80, 0x00);
  364. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  365. break;
  366. case SND_SOC_DAPM_POST_PMU:
  367. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  368. snd_soc_component_update_bits(component,
  369. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  370. 0x0F, 0x02);
  371. else if (hph_mode == CLS_H_LOHIFI)
  372. snd_soc_component_update_bits(component,
  373. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  374. 0x0F, 0x06);
  375. if (wcd937x->comp1_enable) {
  376. snd_soc_component_update_bits(component,
  377. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  378. 0x02, 0x02);
  379. snd_soc_component_update_bits(component,
  380. WCD937X_HPH_L_EN, 0x20, 0x00);
  381. if (wcd937x->comp2_enable) {
  382. snd_soc_component_update_bits(component,
  383. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  384. 0x01, 0x01);
  385. snd_soc_component_update_bits(component,
  386. WCD937X_HPH_R_EN, 0x20, 0x00);
  387. }
  388. /*
  389. * 5ms sleep is required after COMP is enabled as per
  390. * HW requirement
  391. */
  392. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  393. usleep_range(5000, 5100);
  394. clear_bit(HPH_COMP_DELAY,
  395. &wcd937x->status_mask);
  396. }
  397. } else {
  398. snd_soc_component_update_bits(component,
  399. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  400. 0x02, 0x00);
  401. snd_soc_component_update_bits(component,
  402. WCD937X_HPH_L_EN, 0x20, 0x20);
  403. }
  404. snd_soc_component_update_bits(component,
  405. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  406. break;
  407. case SND_SOC_DAPM_POST_PMD:
  408. snd_soc_component_update_bits(component,
  409. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  410. 0x0F, 0x01);
  411. break;
  412. }
  413. return 0;
  414. }
  415. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  416. struct snd_kcontrol *kcontrol,
  417. int event)
  418. {
  419. struct snd_soc_component *component =
  420. snd_soc_dapm_to_component(w->dapm);
  421. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  422. int hph_mode = wcd937x->hph_mode;
  423. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  424. w->name, event);
  425. switch (event) {
  426. case SND_SOC_DAPM_PRE_PMU:
  427. wcd937x_rx_clk_enable(component);
  428. snd_soc_component_update_bits(component,
  429. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  430. snd_soc_component_update_bits(component,
  431. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  432. snd_soc_component_update_bits(component,
  433. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  434. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  435. break;
  436. case SND_SOC_DAPM_POST_PMU:
  437. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  438. snd_soc_component_update_bits(component,
  439. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  440. 0x0F, 0x02);
  441. else if (hph_mode == CLS_H_LOHIFI)
  442. snd_soc_component_update_bits(component,
  443. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  444. 0x0F, 0x06);
  445. if (wcd937x->comp2_enable) {
  446. snd_soc_component_update_bits(component,
  447. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  448. 0x01, 0x01);
  449. snd_soc_component_update_bits(component,
  450. WCD937X_HPH_R_EN, 0x20, 0x00);
  451. if (wcd937x->comp1_enable) {
  452. snd_soc_component_update_bits(component,
  453. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  454. 0x02, 0x02);
  455. snd_soc_component_update_bits(component,
  456. WCD937X_HPH_L_EN, 0x20, 0x00);
  457. }
  458. /*
  459. * 5ms sleep is required after COMP is enabled as per
  460. * HW requirement
  461. */
  462. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  463. usleep_range(5000, 5100);
  464. clear_bit(HPH_COMP_DELAY,
  465. &wcd937x->status_mask);
  466. }
  467. } else {
  468. snd_soc_component_update_bits(component,
  469. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  470. 0x01, 0x00);
  471. snd_soc_component_update_bits(component,
  472. WCD937X_HPH_R_EN, 0x20, 0x20);
  473. }
  474. snd_soc_component_update_bits(component,
  475. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  476. break;
  477. case SND_SOC_DAPM_POST_PMD:
  478. snd_soc_component_update_bits(component,
  479. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  480. 0x0F, 0x01);
  481. break;
  482. }
  483. return 0;
  484. }
  485. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  486. struct snd_kcontrol *kcontrol,
  487. int event)
  488. {
  489. struct snd_soc_component *component =
  490. snd_soc_dapm_to_component(w->dapm);
  491. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  492. int hph_mode = wcd937x->hph_mode;
  493. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  494. w->name, event);
  495. switch (event) {
  496. case SND_SOC_DAPM_PRE_PMU:
  497. wcd937x_rx_clk_enable(component);
  498. snd_soc_component_update_bits(component,
  499. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  500. 0x04, 0x04);
  501. snd_soc_component_update_bits(component,
  502. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  503. 0x01, 0x01);
  504. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  505. snd_soc_component_update_bits(component,
  506. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  507. 0x0F, 0x02);
  508. else if (hph_mode == CLS_H_LOHIFI)
  509. snd_soc_component_update_bits(component,
  510. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  511. 0x0F, 0x06);
  512. snd_soc_component_update_bits(component,
  513. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  514. 0x02, 0x02);
  515. usleep_range(5000, 5010);
  516. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  517. 0x04, 0x00);
  518. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  519. WCD_CLSH_EVENT_PRE_DAC,
  520. WCD_CLSH_STATE_EAR,
  521. hph_mode);
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  525. hph_mode == CLS_H_HIFI)
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  528. 0x0F, 0x01);
  529. break;
  530. };
  531. return 0;
  532. }
  533. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  534. struct snd_kcontrol *kcontrol,
  535. int event)
  536. {
  537. struct snd_soc_component *component =
  538. snd_soc_dapm_to_component(w->dapm);
  539. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  540. int hph_mode = wcd937x->hph_mode;
  541. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  542. w->name, event);
  543. switch (event) {
  544. case SND_SOC_DAPM_PRE_PMU:
  545. wcd937x_rx_clk_enable(component);
  546. snd_soc_component_update_bits(component,
  547. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  548. 0x04, 0x04);
  549. snd_soc_component_update_bits(component,
  550. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  551. 0x04, 0x04);
  552. snd_soc_component_update_bits(component,
  553. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  554. 0x01, 0x01);
  555. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  556. WCD_CLSH_EVENT_PRE_DAC,
  557. WCD_CLSH_STATE_AUX,
  558. hph_mode);
  559. break;
  560. case SND_SOC_DAPM_POST_PMD:
  561. wcd937x_rx_clk_disable(component);
  562. snd_soc_component_update_bits(component,
  563. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  564. 0x04, 0x00);
  565. break;
  566. };
  567. return 0;
  568. }
  569. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  570. struct snd_kcontrol *kcontrol,
  571. int event)
  572. {
  573. struct snd_soc_component *component =
  574. snd_soc_dapm_to_component(w->dapm);
  575. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  576. int ret = 0;
  577. int hph_mode = wcd937x->hph_mode;
  578. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  579. w->name, event);
  580. switch (event) {
  581. case SND_SOC_DAPM_PRE_PMU:
  582. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  583. wcd937x->rx_swr_dev->dev_num,
  584. true);
  585. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  586. WCD_CLSH_EVENT_PRE_DAC,
  587. WCD_CLSH_STATE_HPHR,
  588. hph_mode);
  589. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  590. 0x10, 0x10);
  591. usleep_range(100, 110);
  592. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  593. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  594. wcd937x->rx_swr_dev->dev_num,
  595. true);
  596. snd_soc_component_update_bits(component,
  597. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  598. break;
  599. case SND_SOC_DAPM_POST_PMU:
  600. /*
  601. * 7ms sleep is required after PA is enabled as per
  602. * HW requirement. If compander is disabled, then
  603. * 20ms delay is required.
  604. */
  605. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  606. if (!wcd937x->comp2_enable)
  607. usleep_range(20000, 20100);
  608. else
  609. usleep_range(7000, 7100);
  610. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  611. }
  612. snd_soc_component_update_bits(component,
  613. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  614. 0x02, 0x02);
  615. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  616. snd_soc_component_update_bits(component,
  617. WCD937X_ANA_RX_SUPPLIES,
  618. 0x02, 0x02);
  619. if (wcd937x->update_wcd_event)
  620. wcd937x->update_wcd_event(wcd937x->handle,
  621. WCD_BOLERO_EVT_RX_MUTE,
  622. (WCD_RX2 << 0x10));
  623. wcd_enable_irq(&wcd937x->irq_info,
  624. WCD937X_IRQ_HPHR_PDM_WD_INT);
  625. break;
  626. case SND_SOC_DAPM_PRE_PMD:
  627. wcd_disable_irq(&wcd937x->irq_info,
  628. WCD937X_IRQ_HPHR_PDM_WD_INT);
  629. if (wcd937x->update_wcd_event)
  630. wcd937x->update_wcd_event(wcd937x->handle,
  631. WCD_BOLERO_EVT_RX_MUTE,
  632. (WCD_RX2 << 0x10 | 0x1));
  633. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  634. WCD_EVENT_PRE_HPHR_PA_OFF,
  635. &wcd937x->mbhc->wcd_mbhc);
  636. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  637. break;
  638. case SND_SOC_DAPM_POST_PMD:
  639. /*
  640. * 7ms sleep is required after PA is disabled as per
  641. * HW requirement. If compander is disabled, then
  642. * 20ms delay is required.
  643. */
  644. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  645. if (!wcd937x->comp2_enable)
  646. usleep_range(20000, 20100);
  647. else
  648. usleep_range(7000, 7100);
  649. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  650. }
  651. snd_soc_component_update_bits(component,
  652. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  653. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  654. WCD_EVENT_POST_HPHR_PA_OFF,
  655. &wcd937x->mbhc->wcd_mbhc);
  656. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  657. 0x10, 0x00);
  658. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  659. WCD_CLSH_EVENT_POST_PA,
  660. WCD_CLSH_STATE_HPHR,
  661. hph_mode);
  662. break;
  663. };
  664. return ret;
  665. }
  666. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  667. struct snd_kcontrol *kcontrol,
  668. int event)
  669. {
  670. struct snd_soc_component *component =
  671. snd_soc_dapm_to_component(w->dapm);
  672. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  673. int ret = 0;
  674. int hph_mode = wcd937x->hph_mode;
  675. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  676. w->name, event);
  677. switch (event) {
  678. case SND_SOC_DAPM_PRE_PMU:
  679. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  680. wcd937x->rx_swr_dev->dev_num,
  681. true);
  682. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  683. WCD_CLSH_EVENT_PRE_DAC,
  684. WCD_CLSH_STATE_HPHL,
  685. hph_mode);
  686. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  687. 0x20, 0x20);
  688. usleep_range(100, 110);
  689. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  690. snd_soc_component_update_bits(component,
  691. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  692. break;
  693. case SND_SOC_DAPM_POST_PMU:
  694. /*
  695. * 7ms sleep is required after PA is enabled as per
  696. * HW requirement. If compander is disabled, then
  697. * 20ms delay is required.
  698. */
  699. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  700. if (!wcd937x->comp1_enable)
  701. usleep_range(20000, 20100);
  702. else
  703. usleep_range(7000, 7100);
  704. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  705. }
  706. snd_soc_component_update_bits(component,
  707. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  708. 0x02, 0x02);
  709. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  710. snd_soc_component_update_bits(component,
  711. WCD937X_ANA_RX_SUPPLIES,
  712. 0x02, 0x02);
  713. if (wcd937x->update_wcd_event)
  714. wcd937x->update_wcd_event(wcd937x->handle,
  715. WCD_BOLERO_EVT_RX_MUTE,
  716. (WCD_RX1 << 0x10));
  717. wcd_enable_irq(&wcd937x->irq_info,
  718. WCD937X_IRQ_HPHL_PDM_WD_INT);
  719. break;
  720. case SND_SOC_DAPM_PRE_PMD:
  721. wcd_disable_irq(&wcd937x->irq_info,
  722. WCD937X_IRQ_HPHL_PDM_WD_INT);
  723. if (wcd937x->update_wcd_event)
  724. wcd937x->update_wcd_event(wcd937x->handle,
  725. WCD_BOLERO_EVT_RX_MUTE,
  726. (WCD_RX1 << 0x10 | 0x1));
  727. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  728. WCD_EVENT_PRE_HPHL_PA_OFF,
  729. &wcd937x->mbhc->wcd_mbhc);
  730. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  731. break;
  732. case SND_SOC_DAPM_POST_PMD:
  733. /*
  734. * 7ms sleep is required after PA is disabled as per
  735. * HW requirement. If compander is disabled, then
  736. * 20ms delay is required.
  737. */
  738. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  739. if (!wcd937x->comp1_enable)
  740. usleep_range(20000, 20100);
  741. else
  742. usleep_range(7000, 7100);
  743. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  744. }
  745. snd_soc_component_update_bits(component,
  746. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  747. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  748. WCD_EVENT_POST_HPHL_PA_OFF,
  749. &wcd937x->mbhc->wcd_mbhc);
  750. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  751. 0x20, 0x00);
  752. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  753. WCD_CLSH_EVENT_POST_PA,
  754. WCD_CLSH_STATE_HPHL,
  755. hph_mode);
  756. break;
  757. };
  758. return ret;
  759. }
  760. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  761. struct snd_kcontrol *kcontrol,
  762. int event)
  763. {
  764. struct snd_soc_component *component =
  765. snd_soc_dapm_to_component(w->dapm);
  766. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  767. int hph_mode = wcd937x->hph_mode;
  768. int ret = 0;
  769. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  770. w->name, event);
  771. switch (event) {
  772. case SND_SOC_DAPM_PRE_PMU:
  773. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  774. wcd937x->rx_swr_dev->dev_num,
  775. true);
  776. snd_soc_component_update_bits(component,
  777. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  778. break;
  779. case SND_SOC_DAPM_POST_PMU:
  780. usleep_range(1000, 1010);
  781. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  782. snd_soc_component_update_bits(component,
  783. WCD937X_ANA_RX_SUPPLIES,
  784. 0x02, 0x02);
  785. if (wcd937x->update_wcd_event)
  786. wcd937x->update_wcd_event(wcd937x->handle,
  787. WCD_BOLERO_EVT_RX_MUTE,
  788. (WCD_RX3 << 0x10));
  789. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  790. break;
  791. case SND_SOC_DAPM_PRE_PMD:
  792. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  793. if (wcd937x->update_wcd_event)
  794. wcd937x->update_wcd_event(wcd937x->handle,
  795. WCD_BOLERO_EVT_RX_MUTE,
  796. (WCD_RX3 << 0x10 | 0x1));
  797. break;
  798. case SND_SOC_DAPM_POST_PMD:
  799. /* Add delay as per hw requirement */
  800. usleep_range(2000, 2010);
  801. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  802. WCD_CLSH_EVENT_POST_PA,
  803. WCD_CLSH_STATE_AUX,
  804. hph_mode);
  805. snd_soc_component_update_bits(component,
  806. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  807. break;
  808. };
  809. return ret;
  810. }
  811. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  812. struct snd_kcontrol *kcontrol,
  813. int event)
  814. {
  815. struct snd_soc_component *component =
  816. snd_soc_dapm_to_component(w->dapm);
  817. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  818. int hph_mode = wcd937x->hph_mode;
  819. int ret = 0;
  820. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  821. w->name, event);
  822. switch (event) {
  823. case SND_SOC_DAPM_PRE_PMU:
  824. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  825. wcd937x->rx_swr_dev->dev_num,
  826. true);
  827. /*
  828. * Enable watchdog interrupt for HPHL or AUX
  829. * depending on mux value
  830. */
  831. wcd937x->ear_rx_path =
  832. snd_soc_component_read32(
  833. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  834. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  835. snd_soc_component_update_bits(component,
  836. WCD937X_DIGITAL_PDM_WD_CTL2,
  837. 0x05, 0x05);
  838. else
  839. snd_soc_component_update_bits(component,
  840. WCD937X_DIGITAL_PDM_WD_CTL0,
  841. 0x17, 0x13);
  842. if (!wcd937x->comp1_enable)
  843. snd_soc_component_update_bits(component,
  844. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  845. break;
  846. case SND_SOC_DAPM_POST_PMU:
  847. usleep_range(6000, 6010);
  848. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  849. snd_soc_component_update_bits(component,
  850. WCD937X_ANA_RX_SUPPLIES,
  851. 0x02, 0x02);
  852. if (wcd937x->update_wcd_event)
  853. wcd937x->update_wcd_event(wcd937x->handle,
  854. WCD_BOLERO_EVT_RX_MUTE,
  855. (WCD_RX1 << 0x10));
  856. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  857. wcd_enable_irq(&wcd937x->irq_info,
  858. WCD937X_IRQ_AUX_PDM_WD_INT);
  859. else
  860. wcd_enable_irq(&wcd937x->irq_info,
  861. WCD937X_IRQ_HPHL_PDM_WD_INT);
  862. break;
  863. case SND_SOC_DAPM_PRE_PMD:
  864. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  865. wcd_disable_irq(&wcd937x->irq_info,
  866. WCD937X_IRQ_AUX_PDM_WD_INT);
  867. else
  868. wcd_disable_irq(&wcd937x->irq_info,
  869. WCD937X_IRQ_HPHL_PDM_WD_INT);
  870. if (wcd937x->update_wcd_event)
  871. wcd937x->update_wcd_event(wcd937x->handle,
  872. WCD_BOLERO_EVT_RX_MUTE,
  873. (WCD_RX1 << 0x10 | 0x1));
  874. break;
  875. case SND_SOC_DAPM_POST_PMD:
  876. if (!wcd937x->comp1_enable)
  877. snd_soc_component_update_bits(component,
  878. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  879. usleep_range(7000, 7010);
  880. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  881. WCD_CLSH_EVENT_POST_PA,
  882. WCD_CLSH_STATE_EAR,
  883. hph_mode);
  884. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  885. 0x04, 0x04);
  886. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  887. snd_soc_component_update_bits(component,
  888. WCD937X_DIGITAL_PDM_WD_CTL2,
  889. 0x05, 0x00);
  890. else
  891. snd_soc_component_update_bits(component,
  892. WCD937X_DIGITAL_PDM_WD_CTL0,
  893. 0x17, 0x00);
  894. break;
  895. };
  896. return ret;
  897. }
  898. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  899. struct snd_kcontrol *kcontrol,
  900. int event)
  901. {
  902. struct snd_soc_component *component =
  903. snd_soc_dapm_to_component(w->dapm);
  904. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  905. int mode = wcd937x->hph_mode;
  906. int ret = 0;
  907. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  908. w->name, event);
  909. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  910. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  911. wcd937x_rx_connect_port(component, CLSH,
  912. SND_SOC_DAPM_EVENT_ON(event));
  913. }
  914. if (SND_SOC_DAPM_EVENT_OFF(event))
  915. ret = swr_slvdev_datapath_control(
  916. wcd937x->rx_swr_dev,
  917. wcd937x->rx_swr_dev->dev_num,
  918. false);
  919. return ret;
  920. }
  921. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  922. struct snd_kcontrol *kcontrol,
  923. int event)
  924. {
  925. struct snd_soc_component *component =
  926. snd_soc_dapm_to_component(w->dapm);
  927. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  928. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  929. w->name, event);
  930. switch (event) {
  931. case SND_SOC_DAPM_PRE_PMU:
  932. wcd937x_rx_connect_port(component, HPH_L, true);
  933. if (wcd937x->comp1_enable)
  934. wcd937x_rx_connect_port(component, COMP_L, true);
  935. break;
  936. case SND_SOC_DAPM_POST_PMD:
  937. wcd937x_rx_connect_port(component, HPH_L, false);
  938. if (wcd937x->comp1_enable)
  939. wcd937x_rx_connect_port(component, COMP_L, false);
  940. wcd937x_rx_clk_disable(component);
  941. snd_soc_component_update_bits(component,
  942. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  943. 0x01, 0x00);
  944. break;
  945. };
  946. return 0;
  947. }
  948. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  949. struct snd_kcontrol *kcontrol, int event)
  950. {
  951. struct snd_soc_component *component =
  952. snd_soc_dapm_to_component(w->dapm);
  953. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  954. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  955. w->name, event);
  956. switch (event) {
  957. case SND_SOC_DAPM_PRE_PMU:
  958. wcd937x_rx_connect_port(component, HPH_R, true);
  959. if (wcd937x->comp2_enable)
  960. wcd937x_rx_connect_port(component, COMP_R, true);
  961. break;
  962. case SND_SOC_DAPM_POST_PMD:
  963. wcd937x_rx_connect_port(component, HPH_R, false);
  964. if (wcd937x->comp2_enable)
  965. wcd937x_rx_connect_port(component, COMP_R, false);
  966. wcd937x_rx_clk_disable(component);
  967. snd_soc_component_update_bits(component,
  968. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  969. 0x02, 0x00);
  970. break;
  971. };
  972. return 0;
  973. }
  974. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  975. struct snd_kcontrol *kcontrol,
  976. int event)
  977. {
  978. struct snd_soc_component *component =
  979. snd_soc_dapm_to_component(w->dapm);
  980. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  981. w->name, event);
  982. switch (event) {
  983. case SND_SOC_DAPM_PRE_PMU:
  984. wcd937x_rx_connect_port(component, LO, true);
  985. break;
  986. case SND_SOC_DAPM_POST_PMD:
  987. wcd937x_rx_connect_port(component, LO, false);
  988. usleep_range(6000, 6010);
  989. wcd937x_rx_clk_disable(component);
  990. snd_soc_component_update_bits(component,
  991. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  992. break;
  993. }
  994. return 0;
  995. }
  996. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  997. struct snd_kcontrol *kcontrol,
  998. int event)
  999. {
  1000. struct snd_soc_component *component =
  1001. snd_soc_dapm_to_component(w->dapm);
  1002. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1003. u16 dmic_clk_reg;
  1004. s32 *dmic_clk_cnt;
  1005. unsigned int dmic;
  1006. char *wname;
  1007. int ret = 0;
  1008. wname = strpbrk(w->name, "012345");
  1009. if (!wname) {
  1010. dev_err(component->dev, "%s: widget not found\n", __func__);
  1011. return -EINVAL;
  1012. }
  1013. ret = kstrtouint(wname, 10, &dmic);
  1014. if (ret < 0) {
  1015. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1016. __func__);
  1017. return -EINVAL;
  1018. }
  1019. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1020. w->name, event);
  1021. switch (dmic) {
  1022. case 0:
  1023. case 1:
  1024. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1025. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1026. break;
  1027. case 2:
  1028. case 3:
  1029. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1030. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1031. break;
  1032. case 4:
  1033. case 5:
  1034. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1035. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1036. break;
  1037. default:
  1038. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1039. __func__);
  1040. return -EINVAL;
  1041. };
  1042. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1043. __func__, event, dmic, *dmic_clk_cnt);
  1044. switch (event) {
  1045. case SND_SOC_DAPM_PRE_PMU:
  1046. snd_soc_component_update_bits(component,
  1047. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1048. snd_soc_component_update_bits(component,
  1049. dmic_clk_reg, 0x07, 0x02);
  1050. snd_soc_component_update_bits(component,
  1051. dmic_clk_reg, 0x08, 0x08);
  1052. snd_soc_component_update_bits(component,
  1053. dmic_clk_reg, 0x70, 0x20);
  1054. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1055. break;
  1056. case SND_SOC_DAPM_POST_PMD:
  1057. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1058. break;
  1059. };
  1060. return 0;
  1061. }
  1062. /*
  1063. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1064. * @micb_mv: micbias in mv
  1065. *
  1066. * return register value converted
  1067. */
  1068. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1069. {
  1070. /* min micbias voltage is 1V and maximum is 2.85V */
  1071. if (micb_mv < 1000 || micb_mv > 2850) {
  1072. pr_err("%s: unsupported micbias voltage\n", __func__);
  1073. return -EINVAL;
  1074. }
  1075. return (micb_mv - 1000) / 50;
  1076. }
  1077. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1078. /*
  1079. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1080. * @component: handle to snd_soc_component *
  1081. * @req_volt: micbias voltage to be set
  1082. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1083. *
  1084. * return 0 if adjustment is success or error code in case of failure
  1085. */
  1086. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1087. int req_volt, int micb_num)
  1088. {
  1089. struct wcd937x_priv *wcd937x =
  1090. snd_soc_component_get_drvdata(component);
  1091. int cur_vout_ctl, req_vout_ctl;
  1092. int micb_reg, micb_val, micb_en;
  1093. int ret = 0;
  1094. switch (micb_num) {
  1095. case MIC_BIAS_1:
  1096. micb_reg = WCD937X_ANA_MICB1;
  1097. break;
  1098. case MIC_BIAS_2:
  1099. micb_reg = WCD937X_ANA_MICB2;
  1100. break;
  1101. case MIC_BIAS_3:
  1102. micb_reg = WCD937X_ANA_MICB3;
  1103. break;
  1104. default:
  1105. return -EINVAL;
  1106. }
  1107. mutex_lock(&wcd937x->micb_lock);
  1108. /*
  1109. * If requested micbias voltage is same as current micbias
  1110. * voltage, then just return. Otherwise, adjust voltage as
  1111. * per requested value. If micbias is already enabled, then
  1112. * to avoid slow micbias ramp-up or down enable pull-up
  1113. * momentarily, change the micbias value and then re-enable
  1114. * micbias.
  1115. */
  1116. micb_val = snd_soc_component_read32(component, micb_reg);
  1117. micb_en = (micb_val & 0xC0) >> 6;
  1118. cur_vout_ctl = micb_val & 0x3F;
  1119. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1120. if (req_vout_ctl < 0) {
  1121. ret = -EINVAL;
  1122. goto exit;
  1123. }
  1124. if (cur_vout_ctl == req_vout_ctl) {
  1125. ret = 0;
  1126. goto exit;
  1127. }
  1128. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1129. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1130. req_volt, micb_en);
  1131. if (micb_en == 0x1)
  1132. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1133. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1134. if (micb_en == 0x1) {
  1135. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1136. /*
  1137. * Add 2ms delay as per HW requirement after enabling
  1138. * micbias
  1139. */
  1140. usleep_range(2000, 2100);
  1141. }
  1142. exit:
  1143. mutex_unlock(&wcd937x->micb_lock);
  1144. return ret;
  1145. }
  1146. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1147. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1148. struct snd_kcontrol *kcontrol,
  1149. int event)
  1150. {
  1151. struct snd_soc_component *component =
  1152. snd_soc_dapm_to_component(w->dapm);
  1153. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1154. int ret = 0;
  1155. switch (event) {
  1156. case SND_SOC_DAPM_PRE_PMU:
  1157. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1158. wcd937x->tx_swr_dev->dev_num,
  1159. true);
  1160. break;
  1161. case SND_SOC_DAPM_POST_PMD:
  1162. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1163. wcd937x->tx_swr_dev->dev_num,
  1164. false);
  1165. break;
  1166. };
  1167. return ret;
  1168. }
  1169. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1170. struct snd_kcontrol *kcontrol,
  1171. int event){
  1172. struct snd_soc_component *component =
  1173. snd_soc_dapm_to_component(w->dapm);
  1174. struct wcd937x_priv *wcd937x =
  1175. snd_soc_component_get_drvdata(component);
  1176. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1177. w->name, event);
  1178. switch (event) {
  1179. case SND_SOC_DAPM_PRE_PMU:
  1180. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1181. wcd937x->ana_clk_count++;
  1182. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1183. snd_soc_component_update_bits(component,
  1184. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1185. snd_soc_component_update_bits(component,
  1186. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1187. snd_soc_component_update_bits(component,
  1188. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1189. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1190. break;
  1191. case SND_SOC_DAPM_POST_PMD:
  1192. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1193. snd_soc_component_update_bits(component,
  1194. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1195. break;
  1196. };
  1197. return 0;
  1198. }
  1199. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1200. struct snd_kcontrol *kcontrol, int event)
  1201. {
  1202. struct snd_soc_component *component =
  1203. snd_soc_dapm_to_component(w->dapm);
  1204. struct wcd937x_priv *wcd937x =
  1205. snd_soc_component_get_drvdata(component);
  1206. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1207. w->name, event);
  1208. switch (event) {
  1209. case SND_SOC_DAPM_PRE_PMU:
  1210. snd_soc_component_update_bits(component,
  1211. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1212. snd_soc_component_update_bits(component,
  1213. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1214. snd_soc_component_update_bits(component,
  1215. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1216. snd_soc_component_update_bits(component,
  1217. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1218. snd_soc_component_update_bits(component,
  1219. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1220. snd_soc_component_update_bits(component,
  1221. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1222. snd_soc_component_update_bits(component,
  1223. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1224. break;
  1225. case SND_SOC_DAPM_POST_PMD:
  1226. snd_soc_component_update_bits(component,
  1227. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1228. snd_soc_component_update_bits(component,
  1229. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1230. snd_soc_component_update_bits(component,
  1231. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1232. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1233. wcd937x->ana_clk_count--;
  1234. if (wcd937x->ana_clk_count <= 0) {
  1235. snd_soc_component_update_bits(component,
  1236. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1237. wcd937x->ana_clk_count = 0;
  1238. }
  1239. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1240. snd_soc_component_update_bits(component,
  1241. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1242. break;
  1243. };
  1244. return 0;
  1245. }
  1246. int wcd937x_micbias_control(struct snd_soc_component *component,
  1247. int micb_num, int req, bool is_dapm)
  1248. {
  1249. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1250. int micb_index = micb_num - 1;
  1251. u16 micb_reg;
  1252. int pre_off_event = 0, post_off_event = 0;
  1253. int post_on_event = 0, post_dapm_off = 0;
  1254. int post_dapm_on = 0;
  1255. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1256. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1257. __func__, micb_index);
  1258. return -EINVAL;
  1259. }
  1260. switch (micb_num) {
  1261. case MIC_BIAS_1:
  1262. micb_reg = WCD937X_ANA_MICB1;
  1263. break;
  1264. case MIC_BIAS_2:
  1265. micb_reg = WCD937X_ANA_MICB2;
  1266. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1267. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1268. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1269. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1270. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1271. break;
  1272. case MIC_BIAS_3:
  1273. micb_reg = WCD937X_ANA_MICB3;
  1274. break;
  1275. default:
  1276. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1277. __func__, micb_num);
  1278. return -EINVAL;
  1279. };
  1280. mutex_lock(&wcd937x->micb_lock);
  1281. switch (req) {
  1282. case MICB_PULLUP_ENABLE:
  1283. wcd937x->pullup_ref[micb_index]++;
  1284. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1285. (wcd937x->micb_ref[micb_index] == 0))
  1286. snd_soc_component_update_bits(component, micb_reg,
  1287. 0xC0, 0x80);
  1288. break;
  1289. case MICB_PULLUP_DISABLE:
  1290. if (wcd937x->pullup_ref[micb_index] > 0)
  1291. wcd937x->pullup_ref[micb_index]--;
  1292. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1293. (wcd937x->micb_ref[micb_index] == 0))
  1294. snd_soc_component_update_bits(component, micb_reg,
  1295. 0xC0, 0x00);
  1296. break;
  1297. case MICB_ENABLE:
  1298. wcd937x->micb_ref[micb_index]++;
  1299. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1300. wcd937x->ana_clk_count++;
  1301. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1302. if (wcd937x->micb_ref[micb_index] == 1) {
  1303. snd_soc_component_update_bits(component,
  1304. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1305. snd_soc_component_update_bits(component,
  1306. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1307. snd_soc_component_update_bits(component,
  1308. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1309. snd_soc_component_update_bits(component,
  1310. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1311. snd_soc_component_update_bits(component,
  1312. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1313. snd_soc_component_update_bits(component,
  1314. micb_reg, 0xC0, 0x40);
  1315. if (post_on_event)
  1316. blocking_notifier_call_chain(
  1317. &wcd937x->mbhc->notifier, post_on_event,
  1318. &wcd937x->mbhc->wcd_mbhc);
  1319. }
  1320. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1321. blocking_notifier_call_chain(
  1322. &wcd937x->mbhc->notifier, post_dapm_on,
  1323. &wcd937x->mbhc->wcd_mbhc);
  1324. break;
  1325. case MICB_DISABLE:
  1326. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1327. wcd937x->ana_clk_count--;
  1328. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1329. if (wcd937x->micb_ref[micb_index] > 0)
  1330. wcd937x->micb_ref[micb_index]--;
  1331. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1332. (wcd937x->pullup_ref[micb_index] > 0))
  1333. snd_soc_component_update_bits(component, micb_reg,
  1334. 0xC0, 0x80);
  1335. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1336. (wcd937x->pullup_ref[micb_index] == 0)) {
  1337. if (pre_off_event && wcd937x->mbhc)
  1338. blocking_notifier_call_chain(
  1339. &wcd937x->mbhc->notifier, pre_off_event,
  1340. &wcd937x->mbhc->wcd_mbhc);
  1341. snd_soc_component_update_bits(component, micb_reg,
  1342. 0xC0, 0x00);
  1343. if (post_off_event && wcd937x->mbhc)
  1344. blocking_notifier_call_chain(
  1345. &wcd937x->mbhc->notifier,
  1346. post_off_event,
  1347. &wcd937x->mbhc->wcd_mbhc);
  1348. }
  1349. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1350. if (wcd937x->ana_clk_count <= 0) {
  1351. snd_soc_component_update_bits(component,
  1352. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1353. 0x10, 0x00);
  1354. wcd937x->ana_clk_count = 0;
  1355. }
  1356. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1357. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1358. blocking_notifier_call_chain(
  1359. &wcd937x->mbhc->notifier, post_dapm_off,
  1360. &wcd937x->mbhc->wcd_mbhc);
  1361. break;
  1362. };
  1363. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1364. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1365. wcd937x->pullup_ref[micb_index]);
  1366. mutex_unlock(&wcd937x->micb_lock);
  1367. return 0;
  1368. }
  1369. EXPORT_SYMBOL(wcd937x_micbias_control);
  1370. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1371. {
  1372. int ret = 0;
  1373. uint8_t devnum = 0;
  1374. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1375. if (ret) {
  1376. dev_err(&swr_dev->dev,
  1377. "%s get devnum %d for dev addr %lx failed\n",
  1378. __func__, devnum, swr_dev->addr);
  1379. return ret;
  1380. }
  1381. swr_dev->dev_num = devnum;
  1382. return 0;
  1383. }
  1384. static int wcd937x_event_notify(struct notifier_block *block,
  1385. unsigned long val,
  1386. void *data)
  1387. {
  1388. u16 event = (val & 0xffff);
  1389. u16 amic = (val >> 0x10);
  1390. u16 mask = 0x40, reg = 0x0;
  1391. int ret = 0;
  1392. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1393. struct snd_soc_component *component = wcd937x->component;
  1394. struct wcd_mbhc *mbhc;
  1395. switch (event) {
  1396. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1397. if (amic == 0x1 || amic == 0x2)
  1398. reg = WCD937X_ANA_TX_CH2;
  1399. else if (amic == 0x3)
  1400. reg = WCD937X_ANA_TX_CH3_HPF;
  1401. else
  1402. return 0;
  1403. if (amic == 0x2)
  1404. mask = 0x20;
  1405. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1406. break;
  1407. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1408. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1409. 0xC0, 0x00);
  1410. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1411. 0x80, 0x00);
  1412. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1413. 0x80, 0x00);
  1414. break;
  1415. case BOLERO_WCD_EVT_SSR_DOWN:
  1416. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1417. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1418. wcd937x_reset_low(wcd937x->dev);
  1419. break;
  1420. case BOLERO_WCD_EVT_SSR_UP:
  1421. wcd937x_reset(wcd937x->dev);
  1422. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1423. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1424. regcache_mark_dirty(wcd937x->regmap);
  1425. regcache_sync(wcd937x->regmap);
  1426. /* Enable surge protection */
  1427. snd_soc_component_update_bits(component,
  1428. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  1429. 0xFF, 0xD9);
  1430. /* Initialize MBHC module */
  1431. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1432. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1433. if (ret) {
  1434. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1435. __func__);
  1436. } else {
  1437. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1438. }
  1439. break;
  1440. default:
  1441. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1442. event);
  1443. break;
  1444. }
  1445. return 0;
  1446. }
  1447. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1448. int event)
  1449. {
  1450. struct snd_soc_component *component =
  1451. snd_soc_dapm_to_component(w->dapm);
  1452. int micb_num;
  1453. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1454. __func__, w->name, event);
  1455. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1456. micb_num = MIC_BIAS_1;
  1457. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1458. micb_num = MIC_BIAS_2;
  1459. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1460. micb_num = MIC_BIAS_3;
  1461. else
  1462. return -EINVAL;
  1463. switch (event) {
  1464. case SND_SOC_DAPM_PRE_PMU:
  1465. wcd937x_micbias_control(component, micb_num,
  1466. MICB_ENABLE, true);
  1467. break;
  1468. case SND_SOC_DAPM_POST_PMU:
  1469. usleep_range(1000, 1100);
  1470. break;
  1471. case SND_SOC_DAPM_POST_PMD:
  1472. wcd937x_micbias_control(component, micb_num,
  1473. MICB_DISABLE, true);
  1474. break;
  1475. };
  1476. return 0;
  1477. }
  1478. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1479. struct snd_kcontrol *kcontrol,
  1480. int event)
  1481. {
  1482. return __wcd937x_codec_enable_micbias(w, event);
  1483. }
  1484. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1485. struct snd_ctl_elem_value *ucontrol)
  1486. {
  1487. struct snd_soc_component *component =
  1488. snd_soc_kcontrol_component(kcontrol);
  1489. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1490. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1491. return 0;
  1492. }
  1493. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1494. struct snd_ctl_elem_value *ucontrol)
  1495. {
  1496. struct snd_soc_component *component =
  1497. snd_soc_kcontrol_component(kcontrol);
  1498. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1499. u32 mode_val;
  1500. mode_val = ucontrol->value.enumerated.item[0];
  1501. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1502. if (mode_val == 0) {
  1503. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1504. __func__);
  1505. mode_val = 3; /* enum will be updated later */
  1506. }
  1507. wcd937x->hph_mode = mode_val;
  1508. return 0;
  1509. }
  1510. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_value *ucontrol)
  1512. {
  1513. u8 ear_pa_gain = 0;
  1514. struct snd_soc_component *component =
  1515. snd_soc_kcontrol_component(kcontrol);
  1516. ear_pa_gain = snd_soc_component_read32(component,
  1517. WCD937X_ANA_EAR_COMPANDER_CTL);
  1518. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1519. ucontrol->value.integer.value[0] = ear_pa_gain;
  1520. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1521. ear_pa_gain);
  1522. return 0;
  1523. }
  1524. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1525. struct snd_ctl_elem_value *ucontrol)
  1526. {
  1527. u8 ear_pa_gain = 0;
  1528. struct snd_soc_component *component =
  1529. snd_soc_kcontrol_component(kcontrol);
  1530. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1531. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1532. __func__, ucontrol->value.integer.value[0]);
  1533. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1534. if (!wcd937x->comp1_enable) {
  1535. snd_soc_component_update_bits(component,
  1536. WCD937X_ANA_EAR_COMPANDER_CTL,
  1537. 0x7C, ear_pa_gain);
  1538. }
  1539. return 0;
  1540. }
  1541. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1542. struct snd_ctl_elem_value *ucontrol)
  1543. {
  1544. struct snd_soc_component *component =
  1545. snd_soc_kcontrol_component(kcontrol);
  1546. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1547. bool hphr;
  1548. struct soc_multi_mixer_control *mc;
  1549. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1550. hphr = mc->shift;
  1551. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1552. wcd937x->comp1_enable;
  1553. return 0;
  1554. }
  1555. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1556. struct snd_ctl_elem_value *ucontrol)
  1557. {
  1558. struct snd_soc_component *component =
  1559. snd_soc_kcontrol_component(kcontrol);
  1560. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1561. int value = ucontrol->value.integer.value[0];
  1562. bool hphr;
  1563. struct soc_multi_mixer_control *mc;
  1564. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1565. hphr = mc->shift;
  1566. if (hphr)
  1567. wcd937x->comp2_enable = value;
  1568. else
  1569. wcd937x->comp1_enable = value;
  1570. return 0;
  1571. }
  1572. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1573. struct snd_kcontrol *kcontrol,
  1574. int event)
  1575. {
  1576. struct snd_soc_component *component =
  1577. snd_soc_dapm_to_component(w->dapm);
  1578. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1579. struct wcd937x_pdata *pdata = NULL;
  1580. int ret = 0;
  1581. pdata = dev_get_platdata(wcd937x->dev);
  1582. if (!pdata) {
  1583. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1584. return -EINVAL;
  1585. }
  1586. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1587. w->name, event);
  1588. switch (event) {
  1589. case SND_SOC_DAPM_PRE_PMU:
  1590. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1591. dev_dbg(component->dev,
  1592. "%s: buck already in enabled state\n",
  1593. __func__);
  1594. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1595. return 0;
  1596. }
  1597. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1598. wcd937x->supplies,
  1599. pdata->regulator,
  1600. pdata->num_supplies,
  1601. "cdc-vdd-buck");
  1602. if (ret == -EINVAL) {
  1603. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1604. __func__);
  1605. return ret;
  1606. }
  1607. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1608. /*
  1609. * 200us sleep is required after LDO15 is enabled as per
  1610. * HW requirement
  1611. */
  1612. usleep_range(200, 250);
  1613. break;
  1614. case SND_SOC_DAPM_POST_PMD:
  1615. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1616. break;
  1617. }
  1618. return 0;
  1619. }
  1620. static const char * const rx_hph_mode_mux_text[] = {
  1621. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1622. "CLS_H_ULP", "CLS_AB_HIFI",
  1623. };
  1624. static const char * const wcd937x_ear_pa_gain_text[] = {
  1625. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1626. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1627. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1628. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1629. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1630. };
  1631. static const struct soc_enum rx_hph_mode_mux_enum =
  1632. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1633. rx_hph_mode_mux_text);
  1634. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1635. wcd937x_ear_pa_gain_text);
  1636. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1637. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1638. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1639. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1640. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1641. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1642. wcd937x_get_compander, wcd937x_set_compander),
  1643. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1644. wcd937x_get_compander, wcd937x_set_compander),
  1645. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1646. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1647. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1648. analog_gain),
  1649. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1650. analog_gain),
  1651. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1652. analog_gain),
  1653. };
  1654. static const struct snd_kcontrol_new adc1_switch[] = {
  1655. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1656. };
  1657. static const struct snd_kcontrol_new adc2_switch[] = {
  1658. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1659. };
  1660. static const struct snd_kcontrol_new adc3_switch[] = {
  1661. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1662. };
  1663. static const struct snd_kcontrol_new dmic1_switch[] = {
  1664. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1665. };
  1666. static const struct snd_kcontrol_new dmic2_switch[] = {
  1667. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1668. };
  1669. static const struct snd_kcontrol_new dmic3_switch[] = {
  1670. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1671. };
  1672. static const struct snd_kcontrol_new dmic4_switch[] = {
  1673. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1674. };
  1675. static const struct snd_kcontrol_new dmic5_switch[] = {
  1676. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1677. };
  1678. static const struct snd_kcontrol_new dmic6_switch[] = {
  1679. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1680. };
  1681. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1682. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1683. };
  1684. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1685. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1686. };
  1687. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1688. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1689. };
  1690. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1691. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1692. };
  1693. static const char * const adc2_mux_text[] = {
  1694. "INP2", "INP3"
  1695. };
  1696. static const char * const rdac3_mux_text[] = {
  1697. "RX1", "RX3"
  1698. };
  1699. static const struct soc_enum adc2_enum =
  1700. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1701. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1702. static const struct soc_enum rdac3_enum =
  1703. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1704. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1705. static const struct snd_kcontrol_new tx_adc2_mux =
  1706. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1707. static const struct snd_kcontrol_new rx_rdac3_mux =
  1708. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1709. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1710. /*input widgets*/
  1711. SND_SOC_DAPM_INPUT("AMIC1"),
  1712. SND_SOC_DAPM_INPUT("AMIC2"),
  1713. SND_SOC_DAPM_INPUT("AMIC3"),
  1714. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1715. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1716. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1717. /*tx widgets*/
  1718. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1719. wcd937x_codec_enable_adc,
  1720. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1721. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1722. wcd937x_codec_enable_adc,
  1723. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1724. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1725. NULL, 0, wcd937x_enable_req,
  1726. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1727. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1728. NULL, 0, wcd937x_enable_req,
  1729. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1730. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1731. &tx_adc2_mux),
  1732. /*tx mixers*/
  1733. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1734. adc1_switch, ARRAY_SIZE(adc1_switch),
  1735. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1736. SND_SOC_DAPM_POST_PMD),
  1737. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1738. adc2_switch, ARRAY_SIZE(adc2_switch),
  1739. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1740. SND_SOC_DAPM_POST_PMD),
  1741. /* micbias widgets*/
  1742. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1743. wcd937x_codec_enable_micbias,
  1744. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1745. SND_SOC_DAPM_POST_PMD),
  1746. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1747. wcd937x_codec_enable_micbias,
  1748. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1749. SND_SOC_DAPM_POST_PMD),
  1750. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1751. wcd937x_codec_enable_micbias,
  1752. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1753. SND_SOC_DAPM_POST_PMD),
  1754. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  1755. wcd937x_codec_enable_vdd_buck,
  1756. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1757. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1758. wcd937x_enable_clsh,
  1759. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1760. /*rx widgets*/
  1761. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  1762. wcd937x_codec_enable_ear_pa,
  1763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1764. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1765. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  1766. wcd937x_codec_enable_aux_pa,
  1767. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1768. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1769. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  1770. wcd937x_codec_enable_hphl_pa,
  1771. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1772. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1773. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  1774. wcd937x_codec_enable_hphr_pa,
  1775. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1776. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1777. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1778. wcd937x_codec_hphl_dac_event,
  1779. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1780. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1781. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1782. wcd937x_codec_hphr_dac_event,
  1783. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1784. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1785. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1786. wcd937x_codec_ear_dac_event,
  1787. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1788. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1789. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1790. wcd937x_codec_aux_dac_event,
  1791. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1792. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1793. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1794. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1795. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1796. SND_SOC_DAPM_POST_PMD),
  1797. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1798. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1799. SND_SOC_DAPM_POST_PMD),
  1800. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1801. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1802. SND_SOC_DAPM_POST_PMD),
  1803. /* rx mixer widgets*/
  1804. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1805. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1806. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1807. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1808. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1809. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1810. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1811. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1812. /*output widgets tx*/
  1813. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1814. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1815. /*output widgets rx*/
  1816. SND_SOC_DAPM_OUTPUT("EAR"),
  1817. SND_SOC_DAPM_OUTPUT("AUX"),
  1818. SND_SOC_DAPM_OUTPUT("HPHL"),
  1819. SND_SOC_DAPM_OUTPUT("HPHR"),
  1820. };
  1821. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  1822. /*input widgets*/
  1823. SND_SOC_DAPM_INPUT("AMIC4"),
  1824. /*tx widgets*/
  1825. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1826. wcd937x_codec_enable_adc,
  1827. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1828. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  1829. NULL, 0, wcd937x_enable_req,
  1830. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1831. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1832. wcd937x_codec_enable_dmic,
  1833. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1834. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1835. wcd937x_codec_enable_dmic,
  1836. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1837. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1838. wcd937x_codec_enable_dmic,
  1839. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1840. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1841. wcd937x_codec_enable_dmic,
  1842. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1843. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1844. wcd937x_codec_enable_dmic,
  1845. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1846. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1847. wcd937x_codec_enable_dmic,
  1848. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1849. /*tx mixer widgets*/
  1850. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1851. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1852. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1853. SND_SOC_DAPM_POST_PMD),
  1854. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1855. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1856. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1857. SND_SOC_DAPM_POST_PMD),
  1858. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1859. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1860. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1861. SND_SOC_DAPM_POST_PMD),
  1862. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1863. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1864. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1865. SND_SOC_DAPM_POST_PMD),
  1866. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1867. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1868. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1869. SND_SOC_DAPM_POST_PMD),
  1870. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1871. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1872. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1873. SND_SOC_DAPM_POST_PMD),
  1874. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1875. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  1876. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1877. /*output widgets*/
  1878. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1879. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1880. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1881. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1882. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1883. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1884. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1885. };
  1886. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  1887. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1888. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1889. {"ADC1 REQ", NULL, "ADC1"},
  1890. {"ADC1", NULL, "AMIC1"},
  1891. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1892. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1893. {"ADC2 REQ", NULL, "ADC2"},
  1894. {"ADC2", NULL, "ADC2 MUX"},
  1895. {"ADC2 MUX", "INP3", "AMIC3"},
  1896. {"ADC2 MUX", "INP2", "AMIC2"},
  1897. {"IN1_HPHL", NULL, "VDD_BUCK"},
  1898. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  1899. {"RX1", NULL, "IN1_HPHL"},
  1900. {"RDAC1", NULL, "RX1"},
  1901. {"HPHL_RDAC", "Switch", "RDAC1"},
  1902. {"HPHL PGA", NULL, "HPHL_RDAC"},
  1903. {"HPHL", NULL, "HPHL PGA"},
  1904. {"IN2_HPHR", NULL, "VDD_BUCK"},
  1905. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  1906. {"RX2", NULL, "IN2_HPHR"},
  1907. {"RDAC2", NULL, "RX2"},
  1908. {"HPHR_RDAC", "Switch", "RDAC2"},
  1909. {"HPHR PGA", NULL, "HPHR_RDAC"},
  1910. {"HPHR", NULL, "HPHR PGA"},
  1911. {"IN3_AUX", NULL, "VDD_BUCK"},
  1912. {"IN3_AUX", NULL, "CLS_H_PORT"},
  1913. {"RX3", NULL, "IN3_AUX"},
  1914. {"RDAC4", NULL, "RX3"},
  1915. {"AUX_RDAC", "Switch", "RDAC4"},
  1916. {"AUX PGA", NULL, "AUX_RDAC"},
  1917. {"AUX", NULL, "AUX PGA"},
  1918. {"RDAC3_MUX", "RX3", "RX3"},
  1919. {"RDAC3_MUX", "RX1", "RX1"},
  1920. {"RDAC3", NULL, "RDAC3_MUX"},
  1921. {"EAR_RDAC", "Switch", "RDAC3"},
  1922. {"EAR PGA", NULL, "EAR_RDAC"},
  1923. {"EAR", NULL, "EAR PGA"},
  1924. };
  1925. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  1926. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1927. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1928. {"ADC3 REQ", NULL, "ADC3"},
  1929. {"ADC3", NULL, "AMIC4"},
  1930. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  1931. {"DMIC1_MIXER", "Switch", "DMIC1"},
  1932. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  1933. {"DMIC2_MIXER", "Switch", "DMIC2"},
  1934. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  1935. {"DMIC3_MIXER", "Switch", "DMIC3"},
  1936. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  1937. {"DMIC4_MIXER", "Switch", "DMIC4"},
  1938. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  1939. {"DMIC5_MIXER", "Switch", "DMIC5"},
  1940. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  1941. {"DMIC6_MIXER", "Switch", "DMIC6"},
  1942. };
  1943. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  1944. void *file_private_data,
  1945. struct file *file,
  1946. char __user *buf, size_t count,
  1947. loff_t pos)
  1948. {
  1949. struct wcd937x_priv *priv;
  1950. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  1951. int len = 0;
  1952. priv = (struct wcd937x_priv *) entry->private_data;
  1953. if (!priv) {
  1954. pr_err("%s: wcd937x priv is null\n", __func__);
  1955. return -EINVAL;
  1956. }
  1957. switch (priv->version) {
  1958. case WCD937X_VERSION_1_0:
  1959. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  1960. break;
  1961. default:
  1962. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1963. }
  1964. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1965. }
  1966. static struct snd_info_entry_ops wcd937x_info_ops = {
  1967. .read = wcd937x_version_read,
  1968. };
  1969. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  1970. void *file_private_data,
  1971. struct file *file,
  1972. char __user *buf, size_t count,
  1973. loff_t pos)
  1974. {
  1975. struct wcd937x_priv *priv;
  1976. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  1977. int len = 0;
  1978. priv = (struct wcd937x_priv *) entry->private_data;
  1979. if (!priv) {
  1980. pr_err("%s: wcd937x priv is null\n", __func__);
  1981. return -EINVAL;
  1982. }
  1983. switch (priv->variant) {
  1984. case WCD9370_VARIANT:
  1985. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  1986. break;
  1987. case WCD9375_VARIANT:
  1988. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  1989. break;
  1990. default:
  1991. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  1992. }
  1993. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  1994. }
  1995. static struct snd_info_entry_ops wcd937x_variant_ops = {
  1996. .read = wcd937x_variant_read,
  1997. };
  1998. /*
  1999. * wcd937x_info_create_codec_entry - creates wcd937x module
  2000. * @codec_root: The parent directory
  2001. * @component: component instance
  2002. *
  2003. * Creates wcd937x module, variant and version entry under the given
  2004. * parent directory.
  2005. *
  2006. * Return: 0 on success or negative error code on failure.
  2007. */
  2008. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2009. struct snd_soc_component *component)
  2010. {
  2011. struct snd_info_entry *version_entry;
  2012. struct snd_info_entry *variant_entry;
  2013. struct wcd937x_priv *priv;
  2014. struct snd_soc_card *card;
  2015. if (!codec_root || !component)
  2016. return -EINVAL;
  2017. priv = snd_soc_component_get_drvdata(component);
  2018. if (priv->entry) {
  2019. dev_dbg(priv->dev,
  2020. "%s:wcd937x module already created\n", __func__);
  2021. return 0;
  2022. }
  2023. card = component->card;
  2024. priv->entry = snd_info_create_subdir(codec_root->module,
  2025. "wcd937x", codec_root);
  2026. if (!priv->entry) {
  2027. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2028. __func__);
  2029. return -ENOMEM;
  2030. }
  2031. version_entry = snd_info_create_card_entry(card->snd_card,
  2032. "version",
  2033. priv->entry);
  2034. if (!version_entry) {
  2035. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2036. __func__);
  2037. return -ENOMEM;
  2038. }
  2039. version_entry->private_data = priv;
  2040. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2041. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2042. version_entry->c.ops = &wcd937x_info_ops;
  2043. if (snd_info_register(version_entry) < 0) {
  2044. snd_info_free_entry(version_entry);
  2045. return -ENOMEM;
  2046. }
  2047. priv->version_entry = version_entry;
  2048. variant_entry = snd_info_create_card_entry(card->snd_card,
  2049. "variant",
  2050. priv->entry);
  2051. if (!variant_entry) {
  2052. dev_dbg(codec->dev, "%s: failed to create wcd937x variant entry\n",
  2053. __func__);
  2054. return -ENOMEM;
  2055. }
  2056. variant_entry->private_data = priv;
  2057. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2058. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2059. variant_entry->c.ops = &wcd937x_variant_ops;
  2060. if (snd_info_register(variant_entry) < 0) {
  2061. snd_info_free_entry(variant_entry);
  2062. return -ENOMEM;
  2063. }
  2064. priv->variant_entry = variant_entry;
  2065. return 0;
  2066. }
  2067. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2068. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2069. struct wcd937x_pdata *pdata)
  2070. {
  2071. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2072. int rc = 0;
  2073. if (!pdata) {
  2074. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2075. return -ENODEV;
  2076. }
  2077. /* set micbias voltage */
  2078. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2079. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2080. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2081. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2082. rc = -EINVAL;
  2083. goto done;
  2084. }
  2085. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2086. vout_ctl_1);
  2087. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2088. vout_ctl_2);
  2089. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2090. vout_ctl_3);
  2091. done:
  2092. return rc;
  2093. }
  2094. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2095. {
  2096. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2097. struct snd_soc_dapm_context *dapm =
  2098. snd_soc_component_get_dapm(component);
  2099. int variant;
  2100. int ret = -EINVAL;
  2101. dev_info(component->dev, "%s()\n", __func__);
  2102. wcd937x = snd_soc_component_get_drvdata(component);
  2103. if (!wcd937x)
  2104. return -EINVAL;
  2105. wcd937x->component = component;
  2106. variant = (snd_soc_component_read32(
  2107. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2108. wcd937x->variant = variant;
  2109. wcd937x->fw_data = devm_kzalloc(component->dev,
  2110. sizeof(*(wcd937x->fw_data)),
  2111. GFP_KERNEL);
  2112. if (!wcd937x->fw_data) {
  2113. dev_err(component->dev, "Failed to allocate fw_data\n");
  2114. ret = -ENOMEM;
  2115. goto err;
  2116. }
  2117. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2118. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2119. WCD9XXX_CODEC_HWDEP_NODE, component);
  2120. if (ret < 0) {
  2121. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2122. goto err_hwdep;
  2123. }
  2124. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2125. if (ret) {
  2126. pr_err("%s: mbhc initialization failed\n", __func__);
  2127. goto err_hwdep;
  2128. }
  2129. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2130. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2131. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2132. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2133. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2134. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2135. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2136. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2137. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2138. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2139. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2140. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2141. snd_soc_dapm_sync(dapm);
  2142. wcd_cls_h_init(&wcd937x->clsh_info);
  2143. wcd937x_init_reg(component);
  2144. if (wcd937x->variant == WCD9375_VARIANT) {
  2145. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2146. ARRAY_SIZE(wcd9375_dapm_widgets));
  2147. if (ret < 0) {
  2148. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2149. __func__);
  2150. goto err_hwdep;
  2151. }
  2152. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2153. ARRAY_SIZE(wcd9375_audio_map));
  2154. if (ret < 0) {
  2155. dev_err(component->dev, "%s: Failed to add routes\n",
  2156. __func__);
  2157. goto err_hwdep;
  2158. }
  2159. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2160. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2161. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2162. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2163. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2164. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2165. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2166. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2167. snd_soc_dapm_sync(dapm);
  2168. }
  2169. wcd937x->version = WCD937X_VERSION_1_0;
  2170. /* Register event notifier */
  2171. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2172. if (wcd937x->register_notifier) {
  2173. ret = wcd937x->register_notifier(wcd937x->handle,
  2174. &wcd937x->nblock,
  2175. true);
  2176. if (ret) {
  2177. dev_err(component->dev,
  2178. "%s: Failed to register notifier %d\n",
  2179. __func__, ret);
  2180. return ret;
  2181. }
  2182. }
  2183. return ret;
  2184. err_hwdep:
  2185. wcd937x->fw_data = NULL;
  2186. err:
  2187. return ret;
  2188. }
  2189. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2190. {
  2191. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2192. if (!wcd937x)
  2193. return;
  2194. if (wcd937x->register_notifier)
  2195. wcd937x->register_notifier(wcd937x->handle,
  2196. &wcd937x->nblock,
  2197. false);
  2198. return;
  2199. }
  2200. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2201. .name = DRV_NAME,
  2202. .probe = wcd937x_soc_codec_probe,
  2203. .remove = wcd937x_soc_codec_remove,
  2204. .controls = wcd937x_snd_controls,
  2205. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2206. .dapm_widgets = wcd937x_dapm_widgets,
  2207. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2208. .dapm_routes = wcd937x_audio_map,
  2209. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2210. };
  2211. #ifdef CONFIG_PM_SLEEP
  2212. static int wcd937x_suspend(struct device *dev)
  2213. {
  2214. struct wcd937x_priv *wcd937x = NULL;
  2215. int ret = 0;
  2216. struct wcd937x_pdata *pdata = NULL;
  2217. if (!dev)
  2218. return -ENODEV;
  2219. wcd937x = dev_get_drvdata(dev);
  2220. if (!wcd937x)
  2221. return -EINVAL;
  2222. pdata = dev_get_platdata(wcd937x->dev);
  2223. if (!pdata) {
  2224. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2225. return -EINVAL;
  2226. }
  2227. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2228. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2229. wcd937x->supplies,
  2230. pdata->regulator,
  2231. pdata->num_supplies,
  2232. "cdc-vdd-buck");
  2233. if (ret == -EINVAL) {
  2234. dev_err(dev, "%s: vdd buck is not disabled\n",
  2235. __func__);
  2236. return 0;
  2237. }
  2238. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2239. }
  2240. return 0;
  2241. }
  2242. static int wcd937x_resume(struct device *dev)
  2243. {
  2244. return 0;
  2245. }
  2246. #endif
  2247. static int wcd937x_reset(struct device *dev)
  2248. {
  2249. struct wcd937x_priv *wcd937x = NULL;
  2250. int rc = 0;
  2251. int value = 0;
  2252. if (!dev)
  2253. return -ENODEV;
  2254. wcd937x = dev_get_drvdata(dev);
  2255. if (!wcd937x)
  2256. return -EINVAL;
  2257. if (!wcd937x->rst_np) {
  2258. dev_err(dev, "%s: reset gpio device node not specified\n",
  2259. __func__);
  2260. return -EINVAL;
  2261. }
  2262. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2263. if (value > 0)
  2264. return 0;
  2265. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2266. if (rc) {
  2267. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2268. __func__);
  2269. return rc;
  2270. }
  2271. /* 20ms sleep required after pulling the reset gpio to LOW */
  2272. usleep_range(20, 30);
  2273. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2274. if (rc) {
  2275. dev_err(dev, "%s: wcd active state request fail!\n",
  2276. __func__);
  2277. return rc;
  2278. }
  2279. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2280. usleep_range(20, 30);
  2281. return rc;
  2282. }
  2283. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2284. u32 *val)
  2285. {
  2286. int rc = 0;
  2287. rc = of_property_read_u32(dev->of_node, name, val);
  2288. if (rc)
  2289. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2290. __func__, name, dev->of_node->full_name);
  2291. return rc;
  2292. }
  2293. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2294. struct wcd937x_micbias_setting *mb)
  2295. {
  2296. u32 prop_val = 0;
  2297. int rc = 0;
  2298. /* MB1 */
  2299. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2300. NULL)) {
  2301. rc = wcd937x_read_of_property_u32(dev,
  2302. "qcom,cdc-micbias1-mv",
  2303. &prop_val);
  2304. if (!rc)
  2305. mb->micb1_mv = prop_val;
  2306. } else {
  2307. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2308. __func__);
  2309. }
  2310. /* MB2 */
  2311. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2312. NULL)) {
  2313. rc = wcd937x_read_of_property_u32(dev,
  2314. "qcom,cdc-micbias2-mv",
  2315. &prop_val);
  2316. if (!rc)
  2317. mb->micb2_mv = prop_val;
  2318. } else {
  2319. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2320. __func__);
  2321. }
  2322. /* MB3 */
  2323. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2324. NULL)) {
  2325. rc = wcd937x_read_of_property_u32(dev,
  2326. "qcom,cdc-micbias3-mv",
  2327. &prop_val);
  2328. if (!rc)
  2329. mb->micb3_mv = prop_val;
  2330. } else {
  2331. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2332. __func__);
  2333. }
  2334. }
  2335. static int wcd937x_reset_low(struct device *dev)
  2336. {
  2337. struct wcd937x_priv *wcd937x = NULL;
  2338. int rc = 0;
  2339. if (!dev)
  2340. return -ENODEV;
  2341. wcd937x = dev_get_drvdata(dev);
  2342. if (!wcd937x)
  2343. return -EINVAL;
  2344. if (!wcd937x->rst_np) {
  2345. dev_err(dev, "%s: reset gpio device node not specified\n",
  2346. __func__);
  2347. return -EINVAL;
  2348. }
  2349. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2350. if (rc) {
  2351. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2352. __func__);
  2353. return rc;
  2354. }
  2355. /* 20ms sleep required after pulling the reset gpio to LOW */
  2356. usleep_range(20, 30);
  2357. return rc;
  2358. }
  2359. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2360. {
  2361. struct wcd937x_pdata *pdata = NULL;
  2362. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2363. GFP_KERNEL);
  2364. if (!pdata)
  2365. return NULL;
  2366. pdata->rst_np = of_parse_phandle(dev->of_node,
  2367. "qcom,wcd-rst-gpio-node", 0);
  2368. if (!pdata->rst_np) {
  2369. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2370. __func__, "qcom,wcd-rst-gpio-node",
  2371. dev->of_node->full_name);
  2372. return NULL;
  2373. }
  2374. /* Parse power supplies */
  2375. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2376. &pdata->num_supplies);
  2377. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2378. dev_err(dev, "%s: no power supplies defined for codec\n",
  2379. __func__);
  2380. return NULL;
  2381. }
  2382. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2383. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2384. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2385. return pdata;
  2386. }
  2387. static int wcd937x_wakeup(void *handle, bool enable)
  2388. {
  2389. struct wcd937x_priv *priv;
  2390. if (!handle) {
  2391. pr_err("%s: NULL handle\n", __func__);
  2392. return -EINVAL;
  2393. }
  2394. priv = (struct wcd937x_priv *)handle;
  2395. if (!priv->tx_swr_dev) {
  2396. pr_err("%s: tx swr dev is NULL\n", __func__);
  2397. return -EINVAL;
  2398. }
  2399. if (enable)
  2400. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2401. else
  2402. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2403. }
  2404. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2405. {
  2406. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2407. __func__, irq);
  2408. return IRQ_HANDLED;
  2409. }
  2410. static int wcd937x_bind(struct device *dev)
  2411. {
  2412. int ret = 0, i = 0;
  2413. struct wcd937x_priv *wcd937x = NULL;
  2414. struct wcd937x_pdata *pdata = NULL;
  2415. struct wcd_ctrl_platform_data *plat_data = NULL;
  2416. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2417. if (!wcd937x)
  2418. return -ENOMEM;
  2419. dev_set_drvdata(dev, wcd937x);
  2420. pdata = wcd937x_populate_dt_data(dev);
  2421. if (!pdata) {
  2422. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2423. return -EINVAL;
  2424. }
  2425. wcd937x->dev = dev;
  2426. wcd937x->dev->platform_data = pdata;
  2427. wcd937x->rst_np = pdata->rst_np;
  2428. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2429. pdata->regulator, pdata->num_supplies);
  2430. if (!wcd937x->supplies) {
  2431. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2432. __func__);
  2433. goto err_bind_all;
  2434. }
  2435. plat_data = dev_get_platdata(dev->parent);
  2436. if (!plat_data) {
  2437. dev_err(dev, "%s: platform data from parent is NULL\n",
  2438. __func__);
  2439. ret = -EINVAL;
  2440. goto err_bind_all;
  2441. }
  2442. wcd937x->handle = (void *)plat_data->handle;
  2443. if (!wcd937x->handle) {
  2444. dev_err(dev, "%s: handle is NULL\n", __func__);
  2445. ret = -EINVAL;
  2446. goto err_bind_all;
  2447. }
  2448. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2449. if (!wcd937x->update_wcd_event) {
  2450. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2451. __func__);
  2452. ret = -EINVAL;
  2453. goto err_bind_all;
  2454. }
  2455. wcd937x->register_notifier = plat_data->register_notifier;
  2456. if (!wcd937x->register_notifier) {
  2457. dev_err(dev, "%s: register_notifier api is null!\n",
  2458. __func__);
  2459. ret = -EINVAL;
  2460. goto err_bind_all;
  2461. }
  2462. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2463. pdata->regulator,
  2464. pdata->num_supplies);
  2465. if (ret) {
  2466. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2467. __func__);
  2468. goto err_bind_all;
  2469. }
  2470. wcd937x_reset(dev);
  2471. /*
  2472. * Add 5msec delay to provide sufficient time for
  2473. * soundwire auto enumeration of slave devices as
  2474. * as per HW requirement.
  2475. */
  2476. usleep_range(5000, 5010);
  2477. wcd937x->wakeup = wcd937x_wakeup;
  2478. ret = component_bind_all(dev, wcd937x);
  2479. if (ret) {
  2480. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2481. __func__, ret);
  2482. goto err_bind_all;
  2483. }
  2484. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2485. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2486. if (ret) {
  2487. dev_err(dev, "Failed to read port mapping\n");
  2488. goto err;
  2489. }
  2490. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2491. if (!wcd937x->rx_swr_dev) {
  2492. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2493. __func__);
  2494. ret = -ENODEV;
  2495. goto err;
  2496. }
  2497. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2498. if (!wcd937x->tx_swr_dev) {
  2499. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2500. __func__);
  2501. ret = -ENODEV;
  2502. goto err;
  2503. }
  2504. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2505. &wcd937x_regmap_config);
  2506. if (!wcd937x->regmap) {
  2507. dev_err(dev, "%s: Regmap init failed\n",
  2508. __func__);
  2509. goto err;
  2510. }
  2511. /* Set all interupts as edge triggered */
  2512. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2513. regmap_write(wcd937x->regmap,
  2514. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2515. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2516. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2517. wcd937x->irq_info.codec_name = "WCD937X";
  2518. wcd937x->irq_info.regmap = wcd937x->regmap;
  2519. wcd937x->irq_info.dev = dev;
  2520. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2521. if (ret) {
  2522. dev_err(dev, "%s: IRQ init failed: %d\n",
  2523. __func__, ret);
  2524. goto err;
  2525. }
  2526. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2527. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2528. if (ret < 0) {
  2529. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2530. goto err_irq;
  2531. }
  2532. mutex_init(&wcd937x->micb_lock);
  2533. mutex_init(&wcd937x->ana_tx_clk_lock);
  2534. /* Request for watchdog interrupt */
  2535. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2536. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2537. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2538. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2539. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2540. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2541. /* Disable watchdog interrupt for HPH and AUX */
  2542. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2543. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2544. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2545. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2546. NULL, 0);
  2547. if (ret) {
  2548. dev_err(dev, "%s: Codec registration failed\n",
  2549. __func__);
  2550. goto err_irq;
  2551. }
  2552. return ret;
  2553. err_irq:
  2554. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2555. err:
  2556. component_unbind_all(dev, wcd937x);
  2557. err_bind_all:
  2558. dev_set_drvdata(dev, NULL);
  2559. kfree(pdata);
  2560. kfree(wcd937x);
  2561. return ret;
  2562. }
  2563. static void wcd937x_unbind(struct device *dev)
  2564. {
  2565. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2566. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2567. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2568. snd_soc_unregister_component(dev);
  2569. component_unbind_all(dev, wcd937x);
  2570. mutex_destroy(&wcd937x->micb_lock);
  2571. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2572. dev_set_drvdata(dev, NULL);
  2573. kfree(pdata);
  2574. kfree(wcd937x);
  2575. }
  2576. static const struct of_device_id wcd937x_dt_match[] = {
  2577. { .compatible = "qcom,wcd937x-codec" },
  2578. {}
  2579. };
  2580. static const struct component_master_ops wcd937x_comp_ops = {
  2581. .bind = wcd937x_bind,
  2582. .unbind = wcd937x_unbind,
  2583. };
  2584. static int wcd937x_compare_of(struct device *dev, void *data)
  2585. {
  2586. return dev->of_node == data;
  2587. }
  2588. static void wcd937x_release_of(struct device *dev, void *data)
  2589. {
  2590. of_node_put(data);
  2591. }
  2592. static int wcd937x_add_slave_components(struct device *dev,
  2593. struct component_match **matchptr)
  2594. {
  2595. struct device_node *np, *rx_node, *tx_node;
  2596. np = dev->of_node;
  2597. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2598. if (!rx_node) {
  2599. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2600. return -ENODEV;
  2601. }
  2602. of_node_get(rx_node);
  2603. component_match_add_release(dev, matchptr,
  2604. wcd937x_release_of,
  2605. wcd937x_compare_of,
  2606. rx_node);
  2607. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2608. if (!tx_node) {
  2609. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2610. return -ENODEV;
  2611. }
  2612. of_node_get(tx_node);
  2613. component_match_add_release(dev, matchptr,
  2614. wcd937x_release_of,
  2615. wcd937x_compare_of,
  2616. tx_node);
  2617. return 0;
  2618. }
  2619. static int wcd937x_probe(struct platform_device *pdev)
  2620. {
  2621. struct component_match *match = NULL;
  2622. int ret;
  2623. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2624. if (ret)
  2625. return ret;
  2626. return component_master_add_with_match(&pdev->dev,
  2627. &wcd937x_comp_ops, match);
  2628. }
  2629. static int wcd937x_remove(struct platform_device *pdev)
  2630. {
  2631. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2632. dev_set_drvdata(&pdev->dev, NULL);
  2633. return 0;
  2634. }
  2635. #ifdef CONFIG_PM_SLEEP
  2636. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2637. SET_SYSTEM_SLEEP_PM_OPS(
  2638. wcd937x_suspend,
  2639. wcd937x_resume
  2640. )
  2641. };
  2642. #endif
  2643. static struct platform_driver wcd937x_codec_driver = {
  2644. .probe = wcd937x_probe,
  2645. .remove = wcd937x_remove,
  2646. .driver = {
  2647. .name = "wcd937x_codec",
  2648. .owner = THIS_MODULE,
  2649. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2650. #ifdef CONFIG_PM_SLEEP
  2651. .pm = &wcd937x_dev_pm_ops,
  2652. #endif
  2653. .suppress_bind_attrs = true,
  2654. },
  2655. };
  2656. module_platform_driver(wcd937x_codec_driver);
  2657. MODULE_DESCRIPTION("WCD937X Codec driver");
  2658. MODULE_LICENSE("GPL v2");