bengal.c 186 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <linux/nvmem-consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <soc/snd_event.h>
  24. #include <dsp/audio_notifier.h>
  25. #include <soc/swr-common.h>
  26. #include <dsp/q6afe-v2.h>
  27. #include <dsp/q6core.h>
  28. #include "device_event.h"
  29. #include "msm-pcm-routing-v2.h"
  30. #include "asoc/msm-cdc-pinctrl.h"
  31. #include "asoc/wcd-mbhc-v2.h"
  32. #include "codecs/wcd937x/wcd937x-mbhc.h"
  33. #include "codecs/wsa881x-analog.h"
  34. #include "codecs/wcd937x/wcd937x.h"
  35. #include "codecs/bolero/bolero-cdc.h"
  36. #include <dt-bindings/sound/audio-codec-port-types.h>
  37. #include "bengal-port-config.h"
  38. #define DRV_NAME "bengal-asoc-snd"
  39. #define __CHIPSET__ "BENGAL "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define MSM_LL_QOS_VALUE 300
  64. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  65. #define WCN_CDC_SLIM_RX_CH_MAX 2
  66. #define WCN_CDC_SLIM_TX_CH_MAX 3
  67. enum {
  68. TDM_0 = 0,
  69. TDM_1,
  70. TDM_2,
  71. TDM_3,
  72. TDM_4,
  73. TDM_5,
  74. TDM_6,
  75. TDM_7,
  76. TDM_PORT_MAX,
  77. };
  78. enum {
  79. TDM_PRI = 0,
  80. TDM_SEC,
  81. TDM_TERT,
  82. TDM_QUAT,
  83. TDM_INTERFACE_MAX,
  84. };
  85. enum {
  86. PRIM_AUX_PCM = 0,
  87. SEC_AUX_PCM,
  88. TERT_AUX_PCM,
  89. QUAT_AUX_PCM,
  90. AUX_PCM_MAX,
  91. };
  92. enum {
  93. PRIM_MI2S = 0,
  94. SEC_MI2S,
  95. TERT_MI2S,
  96. QUAT_MI2S,
  97. MI2S_MAX,
  98. };
  99. enum {
  100. RX_CDC_DMA_RX_0 = 0,
  101. RX_CDC_DMA_RX_1,
  102. RX_CDC_DMA_RX_2,
  103. RX_CDC_DMA_RX_3,
  104. RX_CDC_DMA_RX_5,
  105. CDC_DMA_RX_MAX,
  106. };
  107. enum {
  108. TX_CDC_DMA_TX_0 = 0,
  109. TX_CDC_DMA_TX_3,
  110. TX_CDC_DMA_TX_4,
  111. VA_CDC_DMA_TX_0,
  112. VA_CDC_DMA_TX_1,
  113. VA_CDC_DMA_TX_2,
  114. CDC_DMA_TX_MAX,
  115. };
  116. enum {
  117. SLIM_RX_7 = 0,
  118. SLIM_RX_MAX,
  119. };
  120. enum {
  121. SLIM_TX_7 = 0,
  122. SLIM_TX_8,
  123. SLIM_TX_MAX,
  124. };
  125. enum {
  126. AFE_LOOPBACK_TX_IDX = 0,
  127. AFE_LOOPBACK_TX_IDX_MAX,
  128. };
  129. struct msm_asoc_mach_data {
  130. struct snd_info_entry *codec_root;
  131. int usbc_en2_gpio; /* used by gpio driver API */
  132. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  133. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  134. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  135. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  136. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  137. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  138. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  139. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  140. bool is_afe_config_done;
  141. struct device_node *fsa_handle;
  142. };
  143. struct tdm_port {
  144. u32 mode;
  145. u32 channel;
  146. };
  147. enum {
  148. EXT_DISP_RX_IDX_DP = 0,
  149. EXT_DISP_RX_IDX_DP1,
  150. EXT_DISP_RX_IDX_MAX,
  151. };
  152. struct msm_wsa881x_dev_info {
  153. struct device_node *of_node;
  154. u32 index;
  155. };
  156. struct aux_codec_dev_info {
  157. struct device_node *of_node;
  158. u32 index;
  159. };
  160. struct dev_config {
  161. u32 sample_rate;
  162. u32 bit_format;
  163. u32 channels;
  164. };
  165. /* Default configuration of slimbus channels */
  166. static struct dev_config slim_rx_cfg[] = {
  167. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  168. };
  169. static struct dev_config slim_tx_cfg[] = {
  170. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  171. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  172. };
  173. static struct dev_config usb_rx_cfg = {
  174. .sample_rate = SAMPLING_RATE_48KHZ,
  175. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  176. .channels = 2,
  177. };
  178. static struct dev_config usb_tx_cfg = {
  179. .sample_rate = SAMPLING_RATE_48KHZ,
  180. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  181. .channels = 1,
  182. };
  183. static struct dev_config proxy_rx_cfg = {
  184. .sample_rate = SAMPLING_RATE_48KHZ,
  185. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  186. .channels = 2,
  187. };
  188. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  189. {
  190. AFE_API_VERSION_I2S_CONFIG,
  191. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  192. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  193. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  194. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  195. 0,
  196. },
  197. {
  198. AFE_API_VERSION_I2S_CONFIG,
  199. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  200. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  201. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  202. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  203. 0,
  204. },
  205. {
  206. AFE_API_VERSION_I2S_CONFIG,
  207. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  208. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  209. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  210. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  211. 0,
  212. },
  213. {
  214. AFE_API_VERSION_I2S_CONFIG,
  215. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  216. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  217. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  218. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  219. 0,
  220. },
  221. };
  222. struct mi2s_conf {
  223. struct mutex lock;
  224. u32 ref_cnt;
  225. u32 msm_is_mi2s_master;
  226. };
  227. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  228. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  229. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  230. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  231. };
  232. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  233. static bool va_disable;
  234. /* Default configuration of TDM channels */
  235. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  236. { /* PRI TDM */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  245. },
  246. { /* SEC TDM */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  249. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  255. },
  256. { /* TERT TDM */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  265. },
  266. { /* QUAT TDM */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  275. },
  276. };
  277. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  278. { /* PRI TDM */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  287. },
  288. { /* SEC TDM */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  297. },
  298. { /* TERT TDM */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  307. },
  308. { /* QUAT TDM */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  317. },
  318. };
  319. /* Default configuration of AUX PCM channels */
  320. static struct dev_config aux_pcm_rx_cfg[] = {
  321. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  323. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  324. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  325. };
  326. static struct dev_config aux_pcm_tx_cfg[] = {
  327. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  328. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  329. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. };
  332. /* Default configuration of MI2S channels */
  333. static struct dev_config mi2s_rx_cfg[] = {
  334. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  335. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  336. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  337. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  338. };
  339. static struct dev_config mi2s_tx_cfg[] = {
  340. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  341. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  342. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  343. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  344. };
  345. /* Default configuration of Codec DMA Interface RX */
  346. static struct dev_config cdc_dma_rx_cfg[] = {
  347. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  349. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  350. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  351. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  352. };
  353. /* Default configuration of Codec DMA Interface TX */
  354. static struct dev_config cdc_dma_tx_cfg[] = {
  355. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  356. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  357. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  358. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  359. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  360. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  361. };
  362. static struct dev_config afe_loopback_tx_cfg[] = {
  363. [AFE_LOOPBACK_TX_IDX] = {
  364. SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  365. };
  366. static int msm_vi_feed_tx_ch = 2;
  367. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  368. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  369. "S32_LE"};
  370. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  371. "Six", "Seven", "Eight"};
  372. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  373. "KHZ_16", "KHZ_22P05",
  374. "KHZ_32", "KHZ_44P1", "KHZ_48",
  375. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  376. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  377. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  378. "Five", "Six", "Seven",
  379. "Eight"};
  380. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  381. "KHZ_48", "KHZ_176P4",
  382. "KHZ_352P8"};
  383. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  384. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  385. "Five", "Six", "Seven", "Eight"};
  386. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  387. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  388. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  389. "KHZ_48", "KHZ_96", "KHZ_192"};
  390. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  391. "Five", "Six", "Seven",
  392. "Eight"};
  393. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  394. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  395. "Five", "Six", "Seven",
  396. "Eight"};
  397. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  398. "KHZ_16", "KHZ_22P05",
  399. "KHZ_32", "KHZ_44P1", "KHZ_48",
  400. "KHZ_88P2", "KHZ_96",
  401. "KHZ_176P4", "KHZ_192",
  402. "KHZ_352P8", "KHZ_384"};
  403. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  404. "KHZ_44P1", "KHZ_48",
  405. "KHZ_88P2", "KHZ_96"};
  406. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  407. "KHZ_44P1", "KHZ_48",
  408. "KHZ_88P2", "KHZ_96"};
  409. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  410. "KHZ_44P1", "KHZ_48",
  411. "KHZ_88P2", "KHZ_96"};
  412. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  413. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  414. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  415. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  416. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  417. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  418. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  419. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  420. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  421. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  422. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  423. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  424. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  425. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  426. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  427. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  478. cdc_dma_sample_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  480. cdc_dma_sample_rate_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  482. cdc_dma_sample_rate_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  484. cdc_dma_sample_rate_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  486. cdc_dma_sample_rate_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  488. cdc_dma_sample_rate_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  490. cdc_dma_sample_rate_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  492. cdc_dma_sample_rate_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  494. cdc_dma_sample_rate_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  496. cdc_dma_sample_rate_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  498. cdc_dma_sample_rate_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  503. static bool is_initial_boot;
  504. static bool codec_reg_done;
  505. static struct snd_soc_aux_dev *msm_aux_dev;
  506. static struct snd_soc_codec_conf *msm_codec_conf;
  507. static struct snd_soc_card snd_soc_card_bengal_msm;
  508. static int dmic_0_1_gpio_cnt;
  509. static int dmic_2_3_gpio_cnt;
  510. static void *def_wcd_mbhc_cal(void);
  511. /*
  512. * Need to report LINEIN
  513. * if R/L channel impedance is larger than 5K ohm
  514. */
  515. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  516. .read_fw_bin = false,
  517. .calibration = NULL,
  518. .detect_extn_cable = true,
  519. .mono_stero_detection = false,
  520. .swap_gnd_mic = NULL,
  521. .hs_ext_micbias = true,
  522. .key_code[0] = KEY_MEDIA,
  523. .key_code[1] = KEY_VOICECOMMAND,
  524. .key_code[2] = KEY_VOLUMEUP,
  525. .key_code[3] = KEY_VOLUMEDOWN,
  526. .key_code[4] = 0,
  527. .key_code[5] = 0,
  528. .key_code[6] = 0,
  529. .key_code[7] = 0,
  530. .linein_th = 5000,
  531. .moisture_en = false,
  532. .mbhc_micbias = MIC_BIAS_2,
  533. .anc_micbias = MIC_BIAS_2,
  534. .enable_anc_mic_detect = false,
  535. .moisture_duty_cycle_en = true,
  536. };
  537. static inline int param_is_mask(int p)
  538. {
  539. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  540. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  541. }
  542. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  543. int n)
  544. {
  545. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  546. }
  547. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  548. unsigned int bit)
  549. {
  550. if (bit >= SNDRV_MASK_MAX)
  551. return;
  552. if (param_is_mask(n)) {
  553. struct snd_mask *m = param_to_mask(p, n);
  554. m->bits[0] = 0;
  555. m->bits[1] = 0;
  556. m->bits[bit >> 5] |= (1 << (bit & 31));
  557. }
  558. }
  559. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  560. struct snd_ctl_elem_value *ucontrol)
  561. {
  562. int sample_rate_val = 0;
  563. switch (usb_rx_cfg.sample_rate) {
  564. case SAMPLING_RATE_384KHZ:
  565. sample_rate_val = 12;
  566. break;
  567. case SAMPLING_RATE_352P8KHZ:
  568. sample_rate_val = 11;
  569. break;
  570. case SAMPLING_RATE_192KHZ:
  571. sample_rate_val = 10;
  572. break;
  573. case SAMPLING_RATE_176P4KHZ:
  574. sample_rate_val = 9;
  575. break;
  576. case SAMPLING_RATE_96KHZ:
  577. sample_rate_val = 8;
  578. break;
  579. case SAMPLING_RATE_88P2KHZ:
  580. sample_rate_val = 7;
  581. break;
  582. case SAMPLING_RATE_48KHZ:
  583. sample_rate_val = 6;
  584. break;
  585. case SAMPLING_RATE_44P1KHZ:
  586. sample_rate_val = 5;
  587. break;
  588. case SAMPLING_RATE_32KHZ:
  589. sample_rate_val = 4;
  590. break;
  591. case SAMPLING_RATE_22P05KHZ:
  592. sample_rate_val = 3;
  593. break;
  594. case SAMPLING_RATE_16KHZ:
  595. sample_rate_val = 2;
  596. break;
  597. case SAMPLING_RATE_11P025KHZ:
  598. sample_rate_val = 1;
  599. break;
  600. case SAMPLING_RATE_8KHZ:
  601. default:
  602. sample_rate_val = 0;
  603. break;
  604. }
  605. ucontrol->value.integer.value[0] = sample_rate_val;
  606. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  607. usb_rx_cfg.sample_rate);
  608. return 0;
  609. }
  610. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  611. struct snd_ctl_elem_value *ucontrol)
  612. {
  613. switch (ucontrol->value.integer.value[0]) {
  614. case 12:
  615. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  616. break;
  617. case 11:
  618. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  619. break;
  620. case 10:
  621. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  622. break;
  623. case 9:
  624. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  625. break;
  626. case 8:
  627. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  628. break;
  629. case 7:
  630. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  631. break;
  632. case 6:
  633. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  634. break;
  635. case 5:
  636. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  637. break;
  638. case 4:
  639. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  640. break;
  641. case 3:
  642. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  643. break;
  644. case 2:
  645. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  646. break;
  647. case 1:
  648. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  649. break;
  650. case 0:
  651. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  652. break;
  653. default:
  654. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  655. break;
  656. }
  657. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  658. __func__, ucontrol->value.integer.value[0],
  659. usb_rx_cfg.sample_rate);
  660. return 0;
  661. }
  662. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  663. struct snd_ctl_elem_value *ucontrol)
  664. {
  665. int sample_rate_val = 0;
  666. switch (usb_tx_cfg.sample_rate) {
  667. case SAMPLING_RATE_384KHZ:
  668. sample_rate_val = 12;
  669. break;
  670. case SAMPLING_RATE_352P8KHZ:
  671. sample_rate_val = 11;
  672. break;
  673. case SAMPLING_RATE_192KHZ:
  674. sample_rate_val = 10;
  675. break;
  676. case SAMPLING_RATE_176P4KHZ:
  677. sample_rate_val = 9;
  678. break;
  679. case SAMPLING_RATE_96KHZ:
  680. sample_rate_val = 8;
  681. break;
  682. case SAMPLING_RATE_88P2KHZ:
  683. sample_rate_val = 7;
  684. break;
  685. case SAMPLING_RATE_48KHZ:
  686. sample_rate_val = 6;
  687. break;
  688. case SAMPLING_RATE_44P1KHZ:
  689. sample_rate_val = 5;
  690. break;
  691. case SAMPLING_RATE_32KHZ:
  692. sample_rate_val = 4;
  693. break;
  694. case SAMPLING_RATE_22P05KHZ:
  695. sample_rate_val = 3;
  696. break;
  697. case SAMPLING_RATE_16KHZ:
  698. sample_rate_val = 2;
  699. break;
  700. case SAMPLING_RATE_11P025KHZ:
  701. sample_rate_val = 1;
  702. break;
  703. case SAMPLING_RATE_8KHZ:
  704. sample_rate_val = 0;
  705. break;
  706. default:
  707. sample_rate_val = 6;
  708. break;
  709. }
  710. ucontrol->value.integer.value[0] = sample_rate_val;
  711. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  712. usb_tx_cfg.sample_rate);
  713. return 0;
  714. }
  715. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  716. struct snd_ctl_elem_value *ucontrol)
  717. {
  718. switch (ucontrol->value.integer.value[0]) {
  719. case 12:
  720. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  721. break;
  722. case 11:
  723. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  724. break;
  725. case 10:
  726. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  727. break;
  728. case 9:
  729. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  730. break;
  731. case 8:
  732. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  733. break;
  734. case 7:
  735. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  736. break;
  737. case 6:
  738. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  739. break;
  740. case 5:
  741. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  742. break;
  743. case 4:
  744. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  745. break;
  746. case 3:
  747. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  748. break;
  749. case 2:
  750. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  751. break;
  752. case 1:
  753. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  754. break;
  755. case 0:
  756. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  757. break;
  758. default:
  759. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  760. break;
  761. }
  762. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  763. __func__, ucontrol->value.integer.value[0],
  764. usb_tx_cfg.sample_rate);
  765. return 0;
  766. }
  767. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  768. struct snd_ctl_elem_value *ucontrol)
  769. {
  770. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  771. afe_loopback_tx_cfg[0].channels);
  772. ucontrol->value.enumerated.item[0] =
  773. afe_loopback_tx_cfg[0].channels - 1;
  774. return 0;
  775. }
  776. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  777. struct snd_ctl_elem_value *ucontrol)
  778. {
  779. afe_loopback_tx_cfg[0].channels =
  780. ucontrol->value.enumerated.item[0] + 1;
  781. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  782. afe_loopback_tx_cfg[0].channels);
  783. return 1;
  784. }
  785. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  786. struct snd_ctl_elem_value *ucontrol)
  787. {
  788. switch (usb_rx_cfg.bit_format) {
  789. case SNDRV_PCM_FORMAT_S32_LE:
  790. ucontrol->value.integer.value[0] = 3;
  791. break;
  792. case SNDRV_PCM_FORMAT_S24_3LE:
  793. ucontrol->value.integer.value[0] = 2;
  794. break;
  795. case SNDRV_PCM_FORMAT_S24_LE:
  796. ucontrol->value.integer.value[0] = 1;
  797. break;
  798. case SNDRV_PCM_FORMAT_S16_LE:
  799. default:
  800. ucontrol->value.integer.value[0] = 0;
  801. break;
  802. }
  803. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  804. __func__, usb_rx_cfg.bit_format,
  805. ucontrol->value.integer.value[0]);
  806. return 0;
  807. }
  808. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  809. struct snd_ctl_elem_value *ucontrol)
  810. {
  811. int rc = 0;
  812. switch (ucontrol->value.integer.value[0]) {
  813. case 3:
  814. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  815. break;
  816. case 2:
  817. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  818. break;
  819. case 1:
  820. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  821. break;
  822. case 0:
  823. default:
  824. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  825. break;
  826. }
  827. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  828. __func__, usb_rx_cfg.bit_format,
  829. ucontrol->value.integer.value[0]);
  830. return rc;
  831. }
  832. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  833. struct snd_ctl_elem_value *ucontrol)
  834. {
  835. switch (usb_tx_cfg.bit_format) {
  836. case SNDRV_PCM_FORMAT_S32_LE:
  837. ucontrol->value.integer.value[0] = 3;
  838. break;
  839. case SNDRV_PCM_FORMAT_S24_3LE:
  840. ucontrol->value.integer.value[0] = 2;
  841. break;
  842. case SNDRV_PCM_FORMAT_S24_LE:
  843. ucontrol->value.integer.value[0] = 1;
  844. break;
  845. case SNDRV_PCM_FORMAT_S16_LE:
  846. default:
  847. ucontrol->value.integer.value[0] = 0;
  848. break;
  849. }
  850. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  851. __func__, usb_tx_cfg.bit_format,
  852. ucontrol->value.integer.value[0]);
  853. return 0;
  854. }
  855. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  856. struct snd_ctl_elem_value *ucontrol)
  857. {
  858. int rc = 0;
  859. switch (ucontrol->value.integer.value[0]) {
  860. case 3:
  861. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  862. break;
  863. case 2:
  864. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  865. break;
  866. case 1:
  867. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  868. break;
  869. case 0:
  870. default:
  871. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  872. break;
  873. }
  874. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  875. __func__, usb_tx_cfg.bit_format,
  876. ucontrol->value.integer.value[0]);
  877. return rc;
  878. }
  879. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  880. struct snd_ctl_elem_value *ucontrol)
  881. {
  882. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  883. usb_rx_cfg.channels);
  884. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  885. return 0;
  886. }
  887. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  888. struct snd_ctl_elem_value *ucontrol)
  889. {
  890. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  891. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  892. return 1;
  893. }
  894. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  895. struct snd_ctl_elem_value *ucontrol)
  896. {
  897. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  898. usb_tx_cfg.channels);
  899. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  900. return 0;
  901. }
  902. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  906. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  907. return 1;
  908. }
  909. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  910. struct snd_ctl_elem_value *ucontrol)
  911. {
  912. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  913. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  914. ucontrol->value.integer.value[0]);
  915. return 0;
  916. }
  917. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  918. struct snd_ctl_elem_value *ucontrol)
  919. {
  920. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  921. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  922. return 1;
  923. }
  924. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  925. struct snd_ctl_elem_value *ucontrol)
  926. {
  927. pr_debug("%s: proxy_rx channels = %d\n",
  928. __func__, proxy_rx_cfg.channels);
  929. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  930. return 0;
  931. }
  932. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  933. struct snd_ctl_elem_value *ucontrol)
  934. {
  935. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  936. pr_debug("%s: proxy_rx channels = %d\n",
  937. __func__, proxy_rx_cfg.channels);
  938. return 1;
  939. }
  940. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  941. struct tdm_port *port)
  942. {
  943. if (port) {
  944. if (strnstr(kcontrol->id.name, "PRI",
  945. sizeof(kcontrol->id.name))) {
  946. port->mode = TDM_PRI;
  947. } else if (strnstr(kcontrol->id.name, "SEC",
  948. sizeof(kcontrol->id.name))) {
  949. port->mode = TDM_SEC;
  950. } else if (strnstr(kcontrol->id.name, "TERT",
  951. sizeof(kcontrol->id.name))) {
  952. port->mode = TDM_TERT;
  953. } else if (strnstr(kcontrol->id.name, "QUAT",
  954. sizeof(kcontrol->id.name))) {
  955. port->mode = TDM_QUAT;
  956. } else {
  957. pr_err("%s: unsupported mode in: %s\n",
  958. __func__, kcontrol->id.name);
  959. return -EINVAL;
  960. }
  961. if (strnstr(kcontrol->id.name, "RX_0",
  962. sizeof(kcontrol->id.name)) ||
  963. strnstr(kcontrol->id.name, "TX_0",
  964. sizeof(kcontrol->id.name))) {
  965. port->channel = TDM_0;
  966. } else if (strnstr(kcontrol->id.name, "RX_1",
  967. sizeof(kcontrol->id.name)) ||
  968. strnstr(kcontrol->id.name, "TX_1",
  969. sizeof(kcontrol->id.name))) {
  970. port->channel = TDM_1;
  971. } else if (strnstr(kcontrol->id.name, "RX_2",
  972. sizeof(kcontrol->id.name)) ||
  973. strnstr(kcontrol->id.name, "TX_2",
  974. sizeof(kcontrol->id.name))) {
  975. port->channel = TDM_2;
  976. } else if (strnstr(kcontrol->id.name, "RX_3",
  977. sizeof(kcontrol->id.name)) ||
  978. strnstr(kcontrol->id.name, "TX_3",
  979. sizeof(kcontrol->id.name))) {
  980. port->channel = TDM_3;
  981. } else if (strnstr(kcontrol->id.name, "RX_4",
  982. sizeof(kcontrol->id.name)) ||
  983. strnstr(kcontrol->id.name, "TX_4",
  984. sizeof(kcontrol->id.name))) {
  985. port->channel = TDM_4;
  986. } else if (strnstr(kcontrol->id.name, "RX_5",
  987. sizeof(kcontrol->id.name)) ||
  988. strnstr(kcontrol->id.name, "TX_5",
  989. sizeof(kcontrol->id.name))) {
  990. port->channel = TDM_5;
  991. } else if (strnstr(kcontrol->id.name, "RX_6",
  992. sizeof(kcontrol->id.name)) ||
  993. strnstr(kcontrol->id.name, "TX_6",
  994. sizeof(kcontrol->id.name))) {
  995. port->channel = TDM_6;
  996. } else if (strnstr(kcontrol->id.name, "RX_7",
  997. sizeof(kcontrol->id.name)) ||
  998. strnstr(kcontrol->id.name, "TX_7",
  999. sizeof(kcontrol->id.name))) {
  1000. port->channel = TDM_7;
  1001. } else {
  1002. pr_err("%s: unsupported channel in: %s\n",
  1003. __func__, kcontrol->id.name);
  1004. return -EINVAL;
  1005. }
  1006. } else {
  1007. return -EINVAL;
  1008. }
  1009. return 0;
  1010. }
  1011. static int tdm_get_sample_rate(int value)
  1012. {
  1013. int sample_rate = 0;
  1014. switch (value) {
  1015. case 0:
  1016. sample_rate = SAMPLING_RATE_8KHZ;
  1017. break;
  1018. case 1:
  1019. sample_rate = SAMPLING_RATE_16KHZ;
  1020. break;
  1021. case 2:
  1022. sample_rate = SAMPLING_RATE_32KHZ;
  1023. break;
  1024. case 3:
  1025. sample_rate = SAMPLING_RATE_48KHZ;
  1026. break;
  1027. case 4:
  1028. sample_rate = SAMPLING_RATE_176P4KHZ;
  1029. break;
  1030. case 5:
  1031. sample_rate = SAMPLING_RATE_352P8KHZ;
  1032. break;
  1033. default:
  1034. sample_rate = SAMPLING_RATE_48KHZ;
  1035. break;
  1036. }
  1037. return sample_rate;
  1038. }
  1039. static int tdm_get_sample_rate_val(int sample_rate)
  1040. {
  1041. int sample_rate_val = 0;
  1042. switch (sample_rate) {
  1043. case SAMPLING_RATE_8KHZ:
  1044. sample_rate_val = 0;
  1045. break;
  1046. case SAMPLING_RATE_16KHZ:
  1047. sample_rate_val = 1;
  1048. break;
  1049. case SAMPLING_RATE_32KHZ:
  1050. sample_rate_val = 2;
  1051. break;
  1052. case SAMPLING_RATE_48KHZ:
  1053. sample_rate_val = 3;
  1054. break;
  1055. case SAMPLING_RATE_176P4KHZ:
  1056. sample_rate_val = 4;
  1057. break;
  1058. case SAMPLING_RATE_352P8KHZ:
  1059. sample_rate_val = 5;
  1060. break;
  1061. default:
  1062. sample_rate_val = 3;
  1063. break;
  1064. }
  1065. return sample_rate_val;
  1066. }
  1067. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1068. struct snd_ctl_elem_value *ucontrol)
  1069. {
  1070. struct tdm_port port;
  1071. int ret = tdm_get_port_idx(kcontrol, &port);
  1072. if (ret) {
  1073. pr_err("%s: unsupported control: %s\n",
  1074. __func__, kcontrol->id.name);
  1075. } else {
  1076. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1077. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1078. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1079. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1080. ucontrol->value.enumerated.item[0]);
  1081. }
  1082. return ret;
  1083. }
  1084. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1085. struct snd_ctl_elem_value *ucontrol)
  1086. {
  1087. struct tdm_port port;
  1088. int ret = tdm_get_port_idx(kcontrol, &port);
  1089. if (ret) {
  1090. pr_err("%s: unsupported control: %s\n",
  1091. __func__, kcontrol->id.name);
  1092. } else {
  1093. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1094. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1095. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1096. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1097. ucontrol->value.enumerated.item[0]);
  1098. }
  1099. return ret;
  1100. }
  1101. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1102. struct snd_ctl_elem_value *ucontrol)
  1103. {
  1104. struct tdm_port port;
  1105. int ret = tdm_get_port_idx(kcontrol, &port);
  1106. if (ret) {
  1107. pr_err("%s: unsupported control: %s\n",
  1108. __func__, kcontrol->id.name);
  1109. } else {
  1110. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1111. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1112. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1113. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1114. ucontrol->value.enumerated.item[0]);
  1115. }
  1116. return ret;
  1117. }
  1118. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1119. struct snd_ctl_elem_value *ucontrol)
  1120. {
  1121. struct tdm_port port;
  1122. int ret = tdm_get_port_idx(kcontrol, &port);
  1123. if (ret) {
  1124. pr_err("%s: unsupported control: %s\n",
  1125. __func__, kcontrol->id.name);
  1126. } else {
  1127. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1128. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1129. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1130. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1131. ucontrol->value.enumerated.item[0]);
  1132. }
  1133. return ret;
  1134. }
  1135. static int tdm_get_format(int value)
  1136. {
  1137. int format = 0;
  1138. switch (value) {
  1139. case 0:
  1140. format = SNDRV_PCM_FORMAT_S16_LE;
  1141. break;
  1142. case 1:
  1143. format = SNDRV_PCM_FORMAT_S24_LE;
  1144. break;
  1145. case 2:
  1146. format = SNDRV_PCM_FORMAT_S32_LE;
  1147. break;
  1148. default:
  1149. format = SNDRV_PCM_FORMAT_S16_LE;
  1150. break;
  1151. }
  1152. return format;
  1153. }
  1154. static int tdm_get_format_val(int format)
  1155. {
  1156. int value = 0;
  1157. switch (format) {
  1158. case SNDRV_PCM_FORMAT_S16_LE:
  1159. value = 0;
  1160. break;
  1161. case SNDRV_PCM_FORMAT_S24_LE:
  1162. value = 1;
  1163. break;
  1164. case SNDRV_PCM_FORMAT_S32_LE:
  1165. value = 2;
  1166. break;
  1167. default:
  1168. value = 0;
  1169. break;
  1170. }
  1171. return value;
  1172. }
  1173. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1174. struct snd_ctl_elem_value *ucontrol)
  1175. {
  1176. struct tdm_port port;
  1177. int ret = tdm_get_port_idx(kcontrol, &port);
  1178. if (ret) {
  1179. pr_err("%s: unsupported control: %s\n",
  1180. __func__, kcontrol->id.name);
  1181. } else {
  1182. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1183. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1184. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1185. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1186. ucontrol->value.enumerated.item[0]);
  1187. }
  1188. return ret;
  1189. }
  1190. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1191. struct snd_ctl_elem_value *ucontrol)
  1192. {
  1193. struct tdm_port port;
  1194. int ret = tdm_get_port_idx(kcontrol, &port);
  1195. if (ret) {
  1196. pr_err("%s: unsupported control: %s\n",
  1197. __func__, kcontrol->id.name);
  1198. } else {
  1199. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1200. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1201. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1202. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1203. ucontrol->value.enumerated.item[0]);
  1204. }
  1205. return ret;
  1206. }
  1207. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1208. struct snd_ctl_elem_value *ucontrol)
  1209. {
  1210. struct tdm_port port;
  1211. int ret = tdm_get_port_idx(kcontrol, &port);
  1212. if (ret) {
  1213. pr_err("%s: unsupported control: %s\n",
  1214. __func__, kcontrol->id.name);
  1215. } else {
  1216. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1217. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1218. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1219. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1220. ucontrol->value.enumerated.item[0]);
  1221. }
  1222. return ret;
  1223. }
  1224. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1225. struct snd_ctl_elem_value *ucontrol)
  1226. {
  1227. struct tdm_port port;
  1228. int ret = tdm_get_port_idx(kcontrol, &port);
  1229. if (ret) {
  1230. pr_err("%s: unsupported control: %s\n",
  1231. __func__, kcontrol->id.name);
  1232. } else {
  1233. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1234. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1235. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1236. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1237. ucontrol->value.enumerated.item[0]);
  1238. }
  1239. return ret;
  1240. }
  1241. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1242. struct snd_ctl_elem_value *ucontrol)
  1243. {
  1244. struct tdm_port port;
  1245. int ret = tdm_get_port_idx(kcontrol, &port);
  1246. if (ret) {
  1247. pr_err("%s: unsupported control: %s\n",
  1248. __func__, kcontrol->id.name);
  1249. } else {
  1250. ucontrol->value.enumerated.item[0] =
  1251. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1252. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1253. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1254. ucontrol->value.enumerated.item[0]);
  1255. }
  1256. return ret;
  1257. }
  1258. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1259. struct snd_ctl_elem_value *ucontrol)
  1260. {
  1261. struct tdm_port port;
  1262. int ret = tdm_get_port_idx(kcontrol, &port);
  1263. if (ret) {
  1264. pr_err("%s: unsupported control: %s\n",
  1265. __func__, kcontrol->id.name);
  1266. } else {
  1267. tdm_rx_cfg[port.mode][port.channel].channels =
  1268. ucontrol->value.enumerated.item[0] + 1;
  1269. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1270. tdm_rx_cfg[port.mode][port.channel].channels,
  1271. ucontrol->value.enumerated.item[0] + 1);
  1272. }
  1273. return ret;
  1274. }
  1275. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1276. struct snd_ctl_elem_value *ucontrol)
  1277. {
  1278. struct tdm_port port;
  1279. int ret = tdm_get_port_idx(kcontrol, &port);
  1280. if (ret) {
  1281. pr_err("%s: unsupported control: %s\n",
  1282. __func__, kcontrol->id.name);
  1283. } else {
  1284. ucontrol->value.enumerated.item[0] =
  1285. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1286. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1287. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1288. ucontrol->value.enumerated.item[0]);
  1289. }
  1290. return ret;
  1291. }
  1292. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1293. struct snd_ctl_elem_value *ucontrol)
  1294. {
  1295. struct tdm_port port;
  1296. int ret = tdm_get_port_idx(kcontrol, &port);
  1297. if (ret) {
  1298. pr_err("%s: unsupported control: %s\n",
  1299. __func__, kcontrol->id.name);
  1300. } else {
  1301. tdm_tx_cfg[port.mode][port.channel].channels =
  1302. ucontrol->value.enumerated.item[0] + 1;
  1303. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1304. tdm_tx_cfg[port.mode][port.channel].channels,
  1305. ucontrol->value.enumerated.item[0] + 1);
  1306. }
  1307. return ret;
  1308. }
  1309. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1310. {
  1311. int idx = 0;
  1312. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1313. sizeof("PRIM_AUX_PCM"))) {
  1314. idx = PRIM_AUX_PCM;
  1315. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1316. sizeof("SEC_AUX_PCM"))) {
  1317. idx = SEC_AUX_PCM;
  1318. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1319. sizeof("TERT_AUX_PCM"))) {
  1320. idx = TERT_AUX_PCM;
  1321. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1322. sizeof("QUAT_AUX_PCM"))) {
  1323. idx = QUAT_AUX_PCM;
  1324. } else {
  1325. pr_err("%s: unsupported port: %s\n",
  1326. __func__, kcontrol->id.name);
  1327. idx = -EINVAL;
  1328. }
  1329. return idx;
  1330. }
  1331. static int aux_pcm_get_sample_rate(int value)
  1332. {
  1333. int sample_rate = 0;
  1334. switch (value) {
  1335. case 1:
  1336. sample_rate = SAMPLING_RATE_16KHZ;
  1337. break;
  1338. case 0:
  1339. default:
  1340. sample_rate = SAMPLING_RATE_8KHZ;
  1341. break;
  1342. }
  1343. return sample_rate;
  1344. }
  1345. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1346. {
  1347. int sample_rate_val = 0;
  1348. switch (sample_rate) {
  1349. case SAMPLING_RATE_16KHZ:
  1350. sample_rate_val = 1;
  1351. break;
  1352. case SAMPLING_RATE_8KHZ:
  1353. default:
  1354. sample_rate_val = 0;
  1355. break;
  1356. }
  1357. return sample_rate_val;
  1358. }
  1359. static int mi2s_auxpcm_get_format(int value)
  1360. {
  1361. int format = 0;
  1362. switch (value) {
  1363. case 0:
  1364. format = SNDRV_PCM_FORMAT_S16_LE;
  1365. break;
  1366. case 1:
  1367. format = SNDRV_PCM_FORMAT_S24_LE;
  1368. break;
  1369. case 2:
  1370. format = SNDRV_PCM_FORMAT_S24_3LE;
  1371. break;
  1372. case 3:
  1373. format = SNDRV_PCM_FORMAT_S32_LE;
  1374. break;
  1375. default:
  1376. format = SNDRV_PCM_FORMAT_S16_LE;
  1377. break;
  1378. }
  1379. return format;
  1380. }
  1381. static int mi2s_auxpcm_get_format_value(int format)
  1382. {
  1383. int value = 0;
  1384. switch (format) {
  1385. case SNDRV_PCM_FORMAT_S16_LE:
  1386. value = 0;
  1387. break;
  1388. case SNDRV_PCM_FORMAT_S24_LE:
  1389. value = 1;
  1390. break;
  1391. case SNDRV_PCM_FORMAT_S24_3LE:
  1392. value = 2;
  1393. break;
  1394. case SNDRV_PCM_FORMAT_S32_LE:
  1395. value = 3;
  1396. break;
  1397. default:
  1398. value = 0;
  1399. break;
  1400. }
  1401. return value;
  1402. }
  1403. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1404. struct snd_ctl_elem_value *ucontrol)
  1405. {
  1406. int idx = aux_pcm_get_port_idx(kcontrol);
  1407. if (idx < 0)
  1408. return idx;
  1409. ucontrol->value.enumerated.item[0] =
  1410. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1411. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1412. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1413. ucontrol->value.enumerated.item[0]);
  1414. return 0;
  1415. }
  1416. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1417. struct snd_ctl_elem_value *ucontrol)
  1418. {
  1419. int idx = aux_pcm_get_port_idx(kcontrol);
  1420. if (idx < 0)
  1421. return idx;
  1422. aux_pcm_rx_cfg[idx].sample_rate =
  1423. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1424. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1425. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1426. ucontrol->value.enumerated.item[0]);
  1427. return 0;
  1428. }
  1429. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1430. struct snd_ctl_elem_value *ucontrol)
  1431. {
  1432. int idx = aux_pcm_get_port_idx(kcontrol);
  1433. if (idx < 0)
  1434. return idx;
  1435. ucontrol->value.enumerated.item[0] =
  1436. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1437. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1438. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1439. ucontrol->value.enumerated.item[0]);
  1440. return 0;
  1441. }
  1442. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1443. struct snd_ctl_elem_value *ucontrol)
  1444. {
  1445. int idx = aux_pcm_get_port_idx(kcontrol);
  1446. if (idx < 0)
  1447. return idx;
  1448. aux_pcm_tx_cfg[idx].sample_rate =
  1449. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1450. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1451. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1452. ucontrol->value.enumerated.item[0]);
  1453. return 0;
  1454. }
  1455. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1456. struct snd_ctl_elem_value *ucontrol)
  1457. {
  1458. int idx = aux_pcm_get_port_idx(kcontrol);
  1459. if (idx < 0)
  1460. return idx;
  1461. ucontrol->value.enumerated.item[0] =
  1462. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1463. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1464. idx, aux_pcm_rx_cfg[idx].bit_format,
  1465. ucontrol->value.enumerated.item[0]);
  1466. return 0;
  1467. }
  1468. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1469. struct snd_ctl_elem_value *ucontrol)
  1470. {
  1471. int idx = aux_pcm_get_port_idx(kcontrol);
  1472. if (idx < 0)
  1473. return idx;
  1474. aux_pcm_rx_cfg[idx].bit_format =
  1475. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1476. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1477. idx, aux_pcm_rx_cfg[idx].bit_format,
  1478. ucontrol->value.enumerated.item[0]);
  1479. return 0;
  1480. }
  1481. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1482. struct snd_ctl_elem_value *ucontrol)
  1483. {
  1484. int idx = aux_pcm_get_port_idx(kcontrol);
  1485. if (idx < 0)
  1486. return idx;
  1487. ucontrol->value.enumerated.item[0] =
  1488. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1489. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1490. idx, aux_pcm_tx_cfg[idx].bit_format,
  1491. ucontrol->value.enumerated.item[0]);
  1492. return 0;
  1493. }
  1494. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1495. struct snd_ctl_elem_value *ucontrol)
  1496. {
  1497. int idx = aux_pcm_get_port_idx(kcontrol);
  1498. if (idx < 0)
  1499. return idx;
  1500. aux_pcm_tx_cfg[idx].bit_format =
  1501. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1502. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1503. idx, aux_pcm_tx_cfg[idx].bit_format,
  1504. ucontrol->value.enumerated.item[0]);
  1505. return 0;
  1506. }
  1507. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1508. {
  1509. int idx = 0;
  1510. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1511. sizeof("PRIM_MI2S_RX"))) {
  1512. idx = PRIM_MI2S;
  1513. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1514. sizeof("SEC_MI2S_RX"))) {
  1515. idx = SEC_MI2S;
  1516. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1517. sizeof("TERT_MI2S_RX"))) {
  1518. idx = TERT_MI2S;
  1519. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1520. sizeof("QUAT_MI2S_RX"))) {
  1521. idx = QUAT_MI2S;
  1522. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1523. sizeof("PRIM_MI2S_TX"))) {
  1524. idx = PRIM_MI2S;
  1525. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1526. sizeof("SEC_MI2S_TX"))) {
  1527. idx = SEC_MI2S;
  1528. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1529. sizeof("TERT_MI2S_TX"))) {
  1530. idx = TERT_MI2S;
  1531. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1532. sizeof("QUAT_MI2S_TX"))) {
  1533. idx = QUAT_MI2S;
  1534. } else {
  1535. pr_err("%s: unsupported channel: %s\n",
  1536. __func__, kcontrol->id.name);
  1537. idx = -EINVAL;
  1538. }
  1539. return idx;
  1540. }
  1541. static int mi2s_get_sample_rate(int value)
  1542. {
  1543. int sample_rate = 0;
  1544. switch (value) {
  1545. case 0:
  1546. sample_rate = SAMPLING_RATE_8KHZ;
  1547. break;
  1548. case 1:
  1549. sample_rate = SAMPLING_RATE_11P025KHZ;
  1550. break;
  1551. case 2:
  1552. sample_rate = SAMPLING_RATE_16KHZ;
  1553. break;
  1554. case 3:
  1555. sample_rate = SAMPLING_RATE_22P05KHZ;
  1556. break;
  1557. case 4:
  1558. sample_rate = SAMPLING_RATE_32KHZ;
  1559. break;
  1560. case 5:
  1561. sample_rate = SAMPLING_RATE_44P1KHZ;
  1562. break;
  1563. case 6:
  1564. sample_rate = SAMPLING_RATE_48KHZ;
  1565. break;
  1566. case 7:
  1567. sample_rate = SAMPLING_RATE_96KHZ;
  1568. break;
  1569. case 8:
  1570. sample_rate = SAMPLING_RATE_192KHZ;
  1571. break;
  1572. default:
  1573. sample_rate = SAMPLING_RATE_48KHZ;
  1574. break;
  1575. }
  1576. return sample_rate;
  1577. }
  1578. static int mi2s_get_sample_rate_val(int sample_rate)
  1579. {
  1580. int sample_rate_val = 0;
  1581. switch (sample_rate) {
  1582. case SAMPLING_RATE_8KHZ:
  1583. sample_rate_val = 0;
  1584. break;
  1585. case SAMPLING_RATE_11P025KHZ:
  1586. sample_rate_val = 1;
  1587. break;
  1588. case SAMPLING_RATE_16KHZ:
  1589. sample_rate_val = 2;
  1590. break;
  1591. case SAMPLING_RATE_22P05KHZ:
  1592. sample_rate_val = 3;
  1593. break;
  1594. case SAMPLING_RATE_32KHZ:
  1595. sample_rate_val = 4;
  1596. break;
  1597. case SAMPLING_RATE_44P1KHZ:
  1598. sample_rate_val = 5;
  1599. break;
  1600. case SAMPLING_RATE_48KHZ:
  1601. sample_rate_val = 6;
  1602. break;
  1603. case SAMPLING_RATE_96KHZ:
  1604. sample_rate_val = 7;
  1605. break;
  1606. case SAMPLING_RATE_192KHZ:
  1607. sample_rate_val = 8;
  1608. break;
  1609. default:
  1610. sample_rate_val = 6;
  1611. break;
  1612. }
  1613. return sample_rate_val;
  1614. }
  1615. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1616. struct snd_ctl_elem_value *ucontrol)
  1617. {
  1618. int idx = mi2s_get_port_idx(kcontrol);
  1619. if (idx < 0)
  1620. return idx;
  1621. ucontrol->value.enumerated.item[0] =
  1622. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1623. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1624. idx, mi2s_rx_cfg[idx].sample_rate,
  1625. ucontrol->value.enumerated.item[0]);
  1626. return 0;
  1627. }
  1628. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1629. struct snd_ctl_elem_value *ucontrol)
  1630. {
  1631. int idx = mi2s_get_port_idx(kcontrol);
  1632. if (idx < 0)
  1633. return idx;
  1634. mi2s_rx_cfg[idx].sample_rate =
  1635. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1636. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1637. idx, mi2s_rx_cfg[idx].sample_rate,
  1638. ucontrol->value.enumerated.item[0]);
  1639. return 0;
  1640. }
  1641. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1642. struct snd_ctl_elem_value *ucontrol)
  1643. {
  1644. int idx = mi2s_get_port_idx(kcontrol);
  1645. if (idx < 0)
  1646. return idx;
  1647. ucontrol->value.enumerated.item[0] =
  1648. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1649. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1650. idx, mi2s_tx_cfg[idx].sample_rate,
  1651. ucontrol->value.enumerated.item[0]);
  1652. return 0;
  1653. }
  1654. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1655. struct snd_ctl_elem_value *ucontrol)
  1656. {
  1657. int idx = mi2s_get_port_idx(kcontrol);
  1658. if (idx < 0)
  1659. return idx;
  1660. mi2s_tx_cfg[idx].sample_rate =
  1661. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1662. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1663. idx, mi2s_tx_cfg[idx].sample_rate,
  1664. ucontrol->value.enumerated.item[0]);
  1665. return 0;
  1666. }
  1667. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1668. struct snd_ctl_elem_value *ucontrol)
  1669. {
  1670. int idx = mi2s_get_port_idx(kcontrol);
  1671. if (idx < 0)
  1672. return idx;
  1673. ucontrol->value.enumerated.item[0] =
  1674. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1675. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1676. idx, mi2s_rx_cfg[idx].bit_format,
  1677. ucontrol->value.enumerated.item[0]);
  1678. return 0;
  1679. }
  1680. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1681. struct snd_ctl_elem_value *ucontrol)
  1682. {
  1683. int idx = mi2s_get_port_idx(kcontrol);
  1684. if (idx < 0)
  1685. return idx;
  1686. mi2s_rx_cfg[idx].bit_format =
  1687. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1688. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1689. idx, mi2s_rx_cfg[idx].bit_format,
  1690. ucontrol->value.enumerated.item[0]);
  1691. return 0;
  1692. }
  1693. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1694. struct snd_ctl_elem_value *ucontrol)
  1695. {
  1696. int idx = mi2s_get_port_idx(kcontrol);
  1697. if (idx < 0)
  1698. return idx;
  1699. ucontrol->value.enumerated.item[0] =
  1700. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  1701. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1702. idx, mi2s_tx_cfg[idx].bit_format,
  1703. ucontrol->value.enumerated.item[0]);
  1704. return 0;
  1705. }
  1706. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  1707. struct snd_ctl_elem_value *ucontrol)
  1708. {
  1709. int idx = mi2s_get_port_idx(kcontrol);
  1710. if (idx < 0)
  1711. return idx;
  1712. mi2s_tx_cfg[idx].bit_format =
  1713. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1714. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1715. idx, mi2s_tx_cfg[idx].bit_format,
  1716. ucontrol->value.enumerated.item[0]);
  1717. return 0;
  1718. }
  1719. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  1720. struct snd_ctl_elem_value *ucontrol)
  1721. {
  1722. int idx = mi2s_get_port_idx(kcontrol);
  1723. if (idx < 0)
  1724. return idx;
  1725. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1726. idx, mi2s_rx_cfg[idx].channels);
  1727. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  1728. return 0;
  1729. }
  1730. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  1731. struct snd_ctl_elem_value *ucontrol)
  1732. {
  1733. int idx = mi2s_get_port_idx(kcontrol);
  1734. if (idx < 0)
  1735. return idx;
  1736. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1737. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  1738. idx, mi2s_rx_cfg[idx].channels);
  1739. return 1;
  1740. }
  1741. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  1742. struct snd_ctl_elem_value *ucontrol)
  1743. {
  1744. int idx = mi2s_get_port_idx(kcontrol);
  1745. if (idx < 0)
  1746. return idx;
  1747. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1748. idx, mi2s_tx_cfg[idx].channels);
  1749. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  1750. return 0;
  1751. }
  1752. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  1753. struct snd_ctl_elem_value *ucontrol)
  1754. {
  1755. int idx = mi2s_get_port_idx(kcontrol);
  1756. if (idx < 0)
  1757. return idx;
  1758. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  1759. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  1760. idx, mi2s_tx_cfg[idx].channels);
  1761. return 1;
  1762. }
  1763. static int msm_get_port_id(int be_id)
  1764. {
  1765. int afe_port_id = 0;
  1766. switch (be_id) {
  1767. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  1768. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  1769. break;
  1770. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  1771. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  1772. break;
  1773. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  1774. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  1775. break;
  1776. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  1777. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  1778. break;
  1779. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  1780. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  1781. break;
  1782. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  1783. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  1784. break;
  1785. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  1786. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  1787. break;
  1788. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  1789. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  1790. break;
  1791. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  1792. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  1793. break;
  1794. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  1795. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  1796. break;
  1797. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  1798. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  1799. break;
  1800. default:
  1801. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  1802. afe_port_id = -EINVAL;
  1803. }
  1804. return afe_port_id;
  1805. }
  1806. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  1807. {
  1808. u32 bit_per_sample = 0;
  1809. switch (bit_format) {
  1810. case SNDRV_PCM_FORMAT_S32_LE:
  1811. case SNDRV_PCM_FORMAT_S24_3LE:
  1812. case SNDRV_PCM_FORMAT_S24_LE:
  1813. bit_per_sample = 32;
  1814. break;
  1815. case SNDRV_PCM_FORMAT_S16_LE:
  1816. default:
  1817. bit_per_sample = 16;
  1818. break;
  1819. }
  1820. return bit_per_sample;
  1821. }
  1822. static void update_mi2s_clk_val(int dai_id, int stream)
  1823. {
  1824. u32 bit_per_sample = 0;
  1825. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1826. bit_per_sample =
  1827. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  1828. mi2s_clk[dai_id].clk_freq_in_hz =
  1829. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1830. } else {
  1831. bit_per_sample =
  1832. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  1833. mi2s_clk[dai_id].clk_freq_in_hz =
  1834. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  1835. }
  1836. }
  1837. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  1838. {
  1839. int ret = 0;
  1840. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1841. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  1842. int port_id = 0;
  1843. int index = cpu_dai->id;
  1844. port_id = msm_get_port_id(rtd->dai_link->id);
  1845. if (port_id < 0) {
  1846. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  1847. ret = port_id;
  1848. goto err;
  1849. }
  1850. if (enable) {
  1851. update_mi2s_clk_val(index, substream->stream);
  1852. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  1853. mi2s_clk[index].clk_freq_in_hz);
  1854. }
  1855. mi2s_clk[index].enable = enable;
  1856. ret = afe_set_lpass_clock_v2(port_id,
  1857. &mi2s_clk[index]);
  1858. if (ret < 0) {
  1859. dev_err(rtd->card->dev,
  1860. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  1861. __func__, port_id, ret);
  1862. goto err;
  1863. }
  1864. err:
  1865. return ret;
  1866. }
  1867. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1868. {
  1869. int idx = 0;
  1870. if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  1871. sizeof("RX_CDC_DMA_RX_0")))
  1872. idx = RX_CDC_DMA_RX_0;
  1873. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  1874. sizeof("RX_CDC_DMA_RX_1")))
  1875. idx = RX_CDC_DMA_RX_1;
  1876. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  1877. sizeof("RX_CDC_DMA_RX_2")))
  1878. idx = RX_CDC_DMA_RX_2;
  1879. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  1880. sizeof("RX_CDC_DMA_RX_3")))
  1881. idx = RX_CDC_DMA_RX_3;
  1882. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  1883. sizeof("RX_CDC_DMA_RX_5")))
  1884. idx = RX_CDC_DMA_RX_5;
  1885. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  1886. sizeof("TX_CDC_DMA_TX_0")))
  1887. idx = TX_CDC_DMA_TX_0;
  1888. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  1889. sizeof("TX_CDC_DMA_TX_3")))
  1890. idx = TX_CDC_DMA_TX_3;
  1891. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  1892. sizeof("TX_CDC_DMA_TX_4")))
  1893. idx = TX_CDC_DMA_TX_4;
  1894. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1895. sizeof("VA_CDC_DMA_TX_0")))
  1896. idx = VA_CDC_DMA_TX_0;
  1897. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1898. sizeof("VA_CDC_DMA_TX_1")))
  1899. idx = VA_CDC_DMA_TX_1;
  1900. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  1901. sizeof("VA_CDC_DMA_TX_2")))
  1902. idx = VA_CDC_DMA_TX_2;
  1903. else {
  1904. pr_err("%s: unsupported channel: %s\n",
  1905. __func__, kcontrol->id.name);
  1906. return -EINVAL;
  1907. }
  1908. return idx;
  1909. }
  1910. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1911. struct snd_ctl_elem_value *ucontrol)
  1912. {
  1913. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1914. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1915. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1916. return ch_num;
  1917. }
  1918. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1919. cdc_dma_rx_cfg[ch_num].channels - 1);
  1920. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1921. return 0;
  1922. }
  1923. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1924. struct snd_ctl_elem_value *ucontrol)
  1925. {
  1926. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1927. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1928. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1929. return ch_num;
  1930. }
  1931. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1932. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1933. cdc_dma_rx_cfg[ch_num].channels);
  1934. return 1;
  1935. }
  1936. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1937. struct snd_ctl_elem_value *ucontrol)
  1938. {
  1939. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1940. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1941. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1942. return ch_num;
  1943. }
  1944. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1945. case SNDRV_PCM_FORMAT_S32_LE:
  1946. ucontrol->value.integer.value[0] = 3;
  1947. break;
  1948. case SNDRV_PCM_FORMAT_S24_3LE:
  1949. ucontrol->value.integer.value[0] = 2;
  1950. break;
  1951. case SNDRV_PCM_FORMAT_S24_LE:
  1952. ucontrol->value.integer.value[0] = 1;
  1953. break;
  1954. case SNDRV_PCM_FORMAT_S16_LE:
  1955. default:
  1956. ucontrol->value.integer.value[0] = 0;
  1957. break;
  1958. }
  1959. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1960. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1961. ucontrol->value.integer.value[0]);
  1962. return 0;
  1963. }
  1964. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1965. struct snd_ctl_elem_value *ucontrol)
  1966. {
  1967. int rc = 0;
  1968. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1969. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  1970. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  1971. return ch_num;
  1972. }
  1973. switch (ucontrol->value.integer.value[0]) {
  1974. case 3:
  1975. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1976. break;
  1977. case 2:
  1978. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1979. break;
  1980. case 1:
  1981. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1982. break;
  1983. case 0:
  1984. default:
  1985. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1986. break;
  1987. }
  1988. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1989. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1990. ucontrol->value.integer.value[0]);
  1991. return rc;
  1992. }
  1993. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1994. {
  1995. int sample_rate_val = 0;
  1996. switch (sample_rate) {
  1997. case SAMPLING_RATE_8KHZ:
  1998. sample_rate_val = 0;
  1999. break;
  2000. case SAMPLING_RATE_11P025KHZ:
  2001. sample_rate_val = 1;
  2002. break;
  2003. case SAMPLING_RATE_16KHZ:
  2004. sample_rate_val = 2;
  2005. break;
  2006. case SAMPLING_RATE_22P05KHZ:
  2007. sample_rate_val = 3;
  2008. break;
  2009. case SAMPLING_RATE_32KHZ:
  2010. sample_rate_val = 4;
  2011. break;
  2012. case SAMPLING_RATE_44P1KHZ:
  2013. sample_rate_val = 5;
  2014. break;
  2015. case SAMPLING_RATE_48KHZ:
  2016. sample_rate_val = 6;
  2017. break;
  2018. case SAMPLING_RATE_88P2KHZ:
  2019. sample_rate_val = 7;
  2020. break;
  2021. case SAMPLING_RATE_96KHZ:
  2022. sample_rate_val = 8;
  2023. break;
  2024. case SAMPLING_RATE_176P4KHZ:
  2025. sample_rate_val = 9;
  2026. break;
  2027. case SAMPLING_RATE_192KHZ:
  2028. sample_rate_val = 10;
  2029. break;
  2030. case SAMPLING_RATE_352P8KHZ:
  2031. sample_rate_val = 11;
  2032. break;
  2033. case SAMPLING_RATE_384KHZ:
  2034. sample_rate_val = 12;
  2035. break;
  2036. default:
  2037. sample_rate_val = 6;
  2038. break;
  2039. }
  2040. return sample_rate_val;
  2041. }
  2042. static int cdc_dma_get_sample_rate(int value)
  2043. {
  2044. int sample_rate = 0;
  2045. switch (value) {
  2046. case 0:
  2047. sample_rate = SAMPLING_RATE_8KHZ;
  2048. break;
  2049. case 1:
  2050. sample_rate = SAMPLING_RATE_11P025KHZ;
  2051. break;
  2052. case 2:
  2053. sample_rate = SAMPLING_RATE_16KHZ;
  2054. break;
  2055. case 3:
  2056. sample_rate = SAMPLING_RATE_22P05KHZ;
  2057. break;
  2058. case 4:
  2059. sample_rate = SAMPLING_RATE_32KHZ;
  2060. break;
  2061. case 5:
  2062. sample_rate = SAMPLING_RATE_44P1KHZ;
  2063. break;
  2064. case 6:
  2065. sample_rate = SAMPLING_RATE_48KHZ;
  2066. break;
  2067. case 7:
  2068. sample_rate = SAMPLING_RATE_88P2KHZ;
  2069. break;
  2070. case 8:
  2071. sample_rate = SAMPLING_RATE_96KHZ;
  2072. break;
  2073. case 9:
  2074. sample_rate = SAMPLING_RATE_176P4KHZ;
  2075. break;
  2076. case 10:
  2077. sample_rate = SAMPLING_RATE_192KHZ;
  2078. break;
  2079. case 11:
  2080. sample_rate = SAMPLING_RATE_352P8KHZ;
  2081. break;
  2082. case 12:
  2083. sample_rate = SAMPLING_RATE_384KHZ;
  2084. break;
  2085. default:
  2086. sample_rate = SAMPLING_RATE_48KHZ;
  2087. break;
  2088. }
  2089. return sample_rate;
  2090. }
  2091. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2092. struct snd_ctl_elem_value *ucontrol)
  2093. {
  2094. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2095. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2096. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2097. return ch_num;
  2098. }
  2099. ucontrol->value.enumerated.item[0] =
  2100. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2101. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2102. cdc_dma_rx_cfg[ch_num].sample_rate);
  2103. return 0;
  2104. }
  2105. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2106. struct snd_ctl_elem_value *ucontrol)
  2107. {
  2108. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2109. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2110. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2111. return ch_num;
  2112. }
  2113. cdc_dma_rx_cfg[ch_num].sample_rate =
  2114. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2115. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2116. __func__, ucontrol->value.enumerated.item[0],
  2117. cdc_dma_rx_cfg[ch_num].sample_rate);
  2118. return 0;
  2119. }
  2120. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2121. struct snd_ctl_elem_value *ucontrol)
  2122. {
  2123. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2124. if (ch_num < 0) {
  2125. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2126. return ch_num;
  2127. }
  2128. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2129. cdc_dma_tx_cfg[ch_num].channels);
  2130. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2131. return 0;
  2132. }
  2133. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2134. struct snd_ctl_elem_value *ucontrol)
  2135. {
  2136. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2137. if (ch_num < 0) {
  2138. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2139. return ch_num;
  2140. }
  2141. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2142. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2143. cdc_dma_tx_cfg[ch_num].channels);
  2144. return 1;
  2145. }
  2146. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2147. struct snd_ctl_elem_value *ucontrol)
  2148. {
  2149. int sample_rate_val;
  2150. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2151. if (ch_num < 0) {
  2152. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2153. return ch_num;
  2154. }
  2155. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2156. case SAMPLING_RATE_384KHZ:
  2157. sample_rate_val = 12;
  2158. break;
  2159. case SAMPLING_RATE_352P8KHZ:
  2160. sample_rate_val = 11;
  2161. break;
  2162. case SAMPLING_RATE_192KHZ:
  2163. sample_rate_val = 10;
  2164. break;
  2165. case SAMPLING_RATE_176P4KHZ:
  2166. sample_rate_val = 9;
  2167. break;
  2168. case SAMPLING_RATE_96KHZ:
  2169. sample_rate_val = 8;
  2170. break;
  2171. case SAMPLING_RATE_88P2KHZ:
  2172. sample_rate_val = 7;
  2173. break;
  2174. case SAMPLING_RATE_48KHZ:
  2175. sample_rate_val = 6;
  2176. break;
  2177. case SAMPLING_RATE_44P1KHZ:
  2178. sample_rate_val = 5;
  2179. break;
  2180. case SAMPLING_RATE_32KHZ:
  2181. sample_rate_val = 4;
  2182. break;
  2183. case SAMPLING_RATE_22P05KHZ:
  2184. sample_rate_val = 3;
  2185. break;
  2186. case SAMPLING_RATE_16KHZ:
  2187. sample_rate_val = 2;
  2188. break;
  2189. case SAMPLING_RATE_11P025KHZ:
  2190. sample_rate_val = 1;
  2191. break;
  2192. case SAMPLING_RATE_8KHZ:
  2193. sample_rate_val = 0;
  2194. break;
  2195. default:
  2196. sample_rate_val = 6;
  2197. break;
  2198. }
  2199. ucontrol->value.integer.value[0] = sample_rate_val;
  2200. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2201. cdc_dma_tx_cfg[ch_num].sample_rate);
  2202. return 0;
  2203. }
  2204. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2205. struct snd_ctl_elem_value *ucontrol)
  2206. {
  2207. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2208. if (ch_num < 0) {
  2209. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2210. return ch_num;
  2211. }
  2212. switch (ucontrol->value.integer.value[0]) {
  2213. case 12:
  2214. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2215. break;
  2216. case 11:
  2217. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2218. break;
  2219. case 10:
  2220. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2221. break;
  2222. case 9:
  2223. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2224. break;
  2225. case 8:
  2226. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2227. break;
  2228. case 7:
  2229. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2230. break;
  2231. case 6:
  2232. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2233. break;
  2234. case 5:
  2235. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2236. break;
  2237. case 4:
  2238. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2239. break;
  2240. case 3:
  2241. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2242. break;
  2243. case 2:
  2244. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2245. break;
  2246. case 1:
  2247. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2248. break;
  2249. case 0:
  2250. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2251. break;
  2252. default:
  2253. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2254. break;
  2255. }
  2256. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2257. __func__, ucontrol->value.integer.value[0],
  2258. cdc_dma_tx_cfg[ch_num].sample_rate);
  2259. return 0;
  2260. }
  2261. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2262. struct snd_ctl_elem_value *ucontrol)
  2263. {
  2264. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2265. if (ch_num < 0) {
  2266. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2267. return ch_num;
  2268. }
  2269. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2270. case SNDRV_PCM_FORMAT_S32_LE:
  2271. ucontrol->value.integer.value[0] = 3;
  2272. break;
  2273. case SNDRV_PCM_FORMAT_S24_3LE:
  2274. ucontrol->value.integer.value[0] = 2;
  2275. break;
  2276. case SNDRV_PCM_FORMAT_S24_LE:
  2277. ucontrol->value.integer.value[0] = 1;
  2278. break;
  2279. case SNDRV_PCM_FORMAT_S16_LE:
  2280. default:
  2281. ucontrol->value.integer.value[0] = 0;
  2282. break;
  2283. }
  2284. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2285. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2286. ucontrol->value.integer.value[0]);
  2287. return 0;
  2288. }
  2289. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2290. struct snd_ctl_elem_value *ucontrol)
  2291. {
  2292. int rc = 0;
  2293. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2294. if (ch_num < 0) {
  2295. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2296. return ch_num;
  2297. }
  2298. switch (ucontrol->value.integer.value[0]) {
  2299. case 3:
  2300. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2301. break;
  2302. case 2:
  2303. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2304. break;
  2305. case 1:
  2306. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2307. break;
  2308. case 0:
  2309. default:
  2310. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2311. break;
  2312. }
  2313. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2314. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2315. ucontrol->value.integer.value[0]);
  2316. return rc;
  2317. }
  2318. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2319. {
  2320. int idx = 0;
  2321. switch (be_id) {
  2322. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2323. idx = RX_CDC_DMA_RX_0;
  2324. break;
  2325. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2326. idx = RX_CDC_DMA_RX_1;
  2327. break;
  2328. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2329. idx = RX_CDC_DMA_RX_2;
  2330. break;
  2331. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2332. idx = RX_CDC_DMA_RX_3;
  2333. break;
  2334. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2335. idx = RX_CDC_DMA_RX_5;
  2336. break;
  2337. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2338. idx = TX_CDC_DMA_TX_0;
  2339. break;
  2340. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2341. idx = TX_CDC_DMA_TX_3;
  2342. break;
  2343. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2344. idx = TX_CDC_DMA_TX_4;
  2345. break;
  2346. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2347. idx = VA_CDC_DMA_TX_0;
  2348. break;
  2349. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2350. idx = VA_CDC_DMA_TX_1;
  2351. break;
  2352. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2353. idx = VA_CDC_DMA_TX_2;
  2354. break;
  2355. default:
  2356. idx = RX_CDC_DMA_RX_0;
  2357. break;
  2358. }
  2359. return idx;
  2360. }
  2361. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2362. struct snd_ctl_elem_value *ucontrol)
  2363. {
  2364. /*
  2365. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2366. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2367. * value.
  2368. */
  2369. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2370. case SAMPLING_RATE_96KHZ:
  2371. ucontrol->value.integer.value[0] = 5;
  2372. break;
  2373. case SAMPLING_RATE_88P2KHZ:
  2374. ucontrol->value.integer.value[0] = 4;
  2375. break;
  2376. case SAMPLING_RATE_48KHZ:
  2377. ucontrol->value.integer.value[0] = 3;
  2378. break;
  2379. case SAMPLING_RATE_44P1KHZ:
  2380. ucontrol->value.integer.value[0] = 2;
  2381. break;
  2382. case SAMPLING_RATE_16KHZ:
  2383. ucontrol->value.integer.value[0] = 1;
  2384. break;
  2385. case SAMPLING_RATE_8KHZ:
  2386. default:
  2387. ucontrol->value.integer.value[0] = 0;
  2388. break;
  2389. }
  2390. pr_debug("%s: sample rate = %d\n", __func__,
  2391. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2392. return 0;
  2393. }
  2394. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2395. struct snd_ctl_elem_value *ucontrol)
  2396. {
  2397. switch (ucontrol->value.integer.value[0]) {
  2398. case 1:
  2399. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2400. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2401. break;
  2402. case 2:
  2403. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2404. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2405. break;
  2406. case 3:
  2407. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2408. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2409. break;
  2410. case 4:
  2411. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2412. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2413. break;
  2414. case 5:
  2415. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2416. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2417. break;
  2418. case 0:
  2419. default:
  2420. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2421. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2422. break;
  2423. }
  2424. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2425. __func__,
  2426. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2427. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2428. ucontrol->value.enumerated.item[0]);
  2429. return 0;
  2430. }
  2431. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2432. struct snd_ctl_elem_value *ucontrol)
  2433. {
  2434. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2435. case SAMPLING_RATE_96KHZ:
  2436. ucontrol->value.integer.value[0] = 5;
  2437. break;
  2438. case SAMPLING_RATE_88P2KHZ:
  2439. ucontrol->value.integer.value[0] = 4;
  2440. break;
  2441. case SAMPLING_RATE_48KHZ:
  2442. ucontrol->value.integer.value[0] = 3;
  2443. break;
  2444. case SAMPLING_RATE_44P1KHZ:
  2445. ucontrol->value.integer.value[0] = 2;
  2446. break;
  2447. case SAMPLING_RATE_16KHZ:
  2448. ucontrol->value.integer.value[0] = 1;
  2449. break;
  2450. case SAMPLING_RATE_8KHZ:
  2451. default:
  2452. ucontrol->value.integer.value[0] = 0;
  2453. break;
  2454. }
  2455. pr_debug("%s: sample rate rx = %d\n", __func__,
  2456. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2457. return 0;
  2458. }
  2459. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2460. struct snd_ctl_elem_value *ucontrol)
  2461. {
  2462. switch (ucontrol->value.integer.value[0]) {
  2463. case 1:
  2464. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2465. break;
  2466. case 2:
  2467. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2468. break;
  2469. case 3:
  2470. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2471. break;
  2472. case 4:
  2473. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2474. break;
  2475. case 5:
  2476. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2477. break;
  2478. case 0:
  2479. default:
  2480. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2481. break;
  2482. }
  2483. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2484. __func__,
  2485. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2486. ucontrol->value.enumerated.item[0]);
  2487. return 0;
  2488. }
  2489. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2490. struct snd_ctl_elem_value *ucontrol)
  2491. {
  2492. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2493. case SAMPLING_RATE_96KHZ:
  2494. ucontrol->value.integer.value[0] = 5;
  2495. break;
  2496. case SAMPLING_RATE_88P2KHZ:
  2497. ucontrol->value.integer.value[0] = 4;
  2498. break;
  2499. case SAMPLING_RATE_48KHZ:
  2500. ucontrol->value.integer.value[0] = 3;
  2501. break;
  2502. case SAMPLING_RATE_44P1KHZ:
  2503. ucontrol->value.integer.value[0] = 2;
  2504. break;
  2505. case SAMPLING_RATE_16KHZ:
  2506. ucontrol->value.integer.value[0] = 1;
  2507. break;
  2508. case SAMPLING_RATE_8KHZ:
  2509. default:
  2510. ucontrol->value.integer.value[0] = 0;
  2511. break;
  2512. }
  2513. pr_debug("%s: sample rate tx = %d\n", __func__,
  2514. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2515. return 0;
  2516. }
  2517. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2518. struct snd_ctl_elem_value *ucontrol)
  2519. {
  2520. switch (ucontrol->value.integer.value[0]) {
  2521. case 1:
  2522. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2523. break;
  2524. case 2:
  2525. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2526. break;
  2527. case 3:
  2528. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2529. break;
  2530. case 4:
  2531. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2532. break;
  2533. case 5:
  2534. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2535. break;
  2536. case 0:
  2537. default:
  2538. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2539. break;
  2540. }
  2541. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2542. __func__,
  2543. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2544. ucontrol->value.enumerated.item[0]);
  2545. return 0;
  2546. }
  2547. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2548. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2549. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2550. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2551. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2552. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2553. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2554. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2555. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2556. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2557. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2558. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2559. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2560. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2561. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2562. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2563. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2564. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2565. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2566. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2567. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2568. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2569. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2570. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2571. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2572. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2573. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2574. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2575. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2576. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2577. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2578. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2579. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2580. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2581. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2582. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2583. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2584. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2585. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2586. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2587. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2588. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2589. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2590. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2591. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2592. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2593. rx_cdc_dma_rx_0_sample_rate,
  2594. cdc_dma_rx_sample_rate_get,
  2595. cdc_dma_rx_sample_rate_put),
  2596. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2597. rx_cdc_dma_rx_1_sample_rate,
  2598. cdc_dma_rx_sample_rate_get,
  2599. cdc_dma_rx_sample_rate_put),
  2600. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2601. rx_cdc_dma_rx_2_sample_rate,
  2602. cdc_dma_rx_sample_rate_get,
  2603. cdc_dma_rx_sample_rate_put),
  2604. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2605. rx_cdc_dma_rx_3_sample_rate,
  2606. cdc_dma_rx_sample_rate_get,
  2607. cdc_dma_rx_sample_rate_put),
  2608. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2609. rx_cdc_dma_rx_5_sample_rate,
  2610. cdc_dma_rx_sample_rate_get,
  2611. cdc_dma_rx_sample_rate_put),
  2612. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2613. tx_cdc_dma_tx_0_sample_rate,
  2614. cdc_dma_tx_sample_rate_get,
  2615. cdc_dma_tx_sample_rate_put),
  2616. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2617. tx_cdc_dma_tx_3_sample_rate,
  2618. cdc_dma_tx_sample_rate_get,
  2619. cdc_dma_tx_sample_rate_put),
  2620. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  2621. tx_cdc_dma_tx_4_sample_rate,
  2622. cdc_dma_tx_sample_rate_get,
  2623. cdc_dma_tx_sample_rate_put),
  2624. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2625. va_cdc_dma_tx_0_sample_rate,
  2626. cdc_dma_tx_sample_rate_get,
  2627. cdc_dma_tx_sample_rate_put),
  2628. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2629. va_cdc_dma_tx_1_sample_rate,
  2630. cdc_dma_tx_sample_rate_get,
  2631. cdc_dma_tx_sample_rate_put),
  2632. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  2633. va_cdc_dma_tx_2_sample_rate,
  2634. cdc_dma_tx_sample_rate_get,
  2635. cdc_dma_tx_sample_rate_put),
  2636. };
  2637. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  2638. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2639. usb_audio_rx_sample_rate_get,
  2640. usb_audio_rx_sample_rate_put),
  2641. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2642. usb_audio_tx_sample_rate_get,
  2643. usb_audio_tx_sample_rate_put),
  2644. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2645. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2646. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2647. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2648. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2649. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2650. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2651. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2652. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2653. proxy_rx_ch_get, proxy_rx_ch_put),
  2654. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2655. msm_bt_sample_rate_get,
  2656. msm_bt_sample_rate_put),
  2657. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  2658. msm_bt_sample_rate_rx_get,
  2659. msm_bt_sample_rate_rx_put),
  2660. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  2661. msm_bt_sample_rate_tx_get,
  2662. msm_bt_sample_rate_tx_put),
  2663. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  2664. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  2665. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2666. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2667. };
  2668. static const struct snd_kcontrol_new msm_tdm_snd_controls[] = {
  2669. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2670. tdm_rx_sample_rate_get,
  2671. tdm_rx_sample_rate_put),
  2672. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2673. tdm_rx_sample_rate_get,
  2674. tdm_rx_sample_rate_put),
  2675. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2676. tdm_rx_sample_rate_get,
  2677. tdm_rx_sample_rate_put),
  2678. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2679. tdm_rx_sample_rate_get,
  2680. tdm_rx_sample_rate_put),
  2681. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2682. tdm_tx_sample_rate_get,
  2683. tdm_tx_sample_rate_put),
  2684. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2685. tdm_tx_sample_rate_get,
  2686. tdm_tx_sample_rate_put),
  2687. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2688. tdm_tx_sample_rate_get,
  2689. tdm_tx_sample_rate_put),
  2690. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2691. tdm_tx_sample_rate_get,
  2692. tdm_tx_sample_rate_put),
  2693. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2694. tdm_rx_format_get,
  2695. tdm_rx_format_put),
  2696. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2697. tdm_rx_format_get,
  2698. tdm_rx_format_put),
  2699. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2700. tdm_rx_format_get,
  2701. tdm_rx_format_put),
  2702. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2703. tdm_rx_format_get,
  2704. tdm_rx_format_put),
  2705. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2706. tdm_tx_format_get,
  2707. tdm_tx_format_put),
  2708. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2709. tdm_tx_format_get,
  2710. tdm_tx_format_put),
  2711. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2712. tdm_tx_format_get,
  2713. tdm_tx_format_put),
  2714. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2715. tdm_tx_format_get,
  2716. tdm_tx_format_put),
  2717. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2718. tdm_rx_ch_get,
  2719. tdm_rx_ch_put),
  2720. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2721. tdm_rx_ch_get,
  2722. tdm_rx_ch_put),
  2723. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2724. tdm_rx_ch_get,
  2725. tdm_rx_ch_put),
  2726. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2727. tdm_rx_ch_get,
  2728. tdm_rx_ch_put),
  2729. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2730. tdm_tx_ch_get,
  2731. tdm_tx_ch_put),
  2732. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2733. tdm_tx_ch_get,
  2734. tdm_tx_ch_put),
  2735. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2736. tdm_tx_ch_get,
  2737. tdm_tx_ch_put),
  2738. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2739. tdm_tx_ch_get,
  2740. tdm_tx_ch_put),
  2741. };
  2742. static const struct snd_kcontrol_new msm_auxpcm_snd_controls[] = {
  2743. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2744. aux_pcm_rx_sample_rate_get,
  2745. aux_pcm_rx_sample_rate_put),
  2746. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2747. aux_pcm_rx_sample_rate_get,
  2748. aux_pcm_rx_sample_rate_put),
  2749. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2750. aux_pcm_rx_sample_rate_get,
  2751. aux_pcm_rx_sample_rate_put),
  2752. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2753. aux_pcm_rx_sample_rate_get,
  2754. aux_pcm_rx_sample_rate_put),
  2755. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2756. aux_pcm_tx_sample_rate_get,
  2757. aux_pcm_tx_sample_rate_put),
  2758. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2759. aux_pcm_tx_sample_rate_get,
  2760. aux_pcm_tx_sample_rate_put),
  2761. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2762. aux_pcm_tx_sample_rate_get,
  2763. aux_pcm_tx_sample_rate_put),
  2764. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2765. aux_pcm_tx_sample_rate_get,
  2766. aux_pcm_tx_sample_rate_put),
  2767. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2768. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2769. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2770. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2771. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2772. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2773. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2774. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2775. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2776. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2777. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2778. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2779. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2780. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2781. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2782. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2783. };
  2784. static const struct snd_kcontrol_new msm_mi2s_snd_controls[] = {
  2785. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2786. mi2s_rx_sample_rate_get,
  2787. mi2s_rx_sample_rate_put),
  2788. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2789. mi2s_rx_sample_rate_get,
  2790. mi2s_rx_sample_rate_put),
  2791. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2792. mi2s_rx_sample_rate_get,
  2793. mi2s_rx_sample_rate_put),
  2794. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2795. mi2s_rx_sample_rate_get,
  2796. mi2s_tx_sample_rate_put),
  2797. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2798. mi2s_tx_sample_rate_get,
  2799. mi2s_tx_sample_rate_put),
  2800. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2801. mi2s_tx_sample_rate_get,
  2802. mi2s_tx_sample_rate_put),
  2803. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2804. mi2s_tx_sample_rate_get,
  2805. mi2s_tx_sample_rate_put),
  2806. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2807. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2808. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2809. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2810. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2811. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2812. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2813. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2814. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2815. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2816. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2817. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2818. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2819. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2820. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2821. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2822. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2823. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2824. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2825. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2826. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2827. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2828. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2829. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2830. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2831. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2832. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2833. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2834. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2835. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2836. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2837. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2838. };
  2839. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2840. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2841. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2842. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2843. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2844. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2845. aux_pcm_rx_sample_rate_get,
  2846. aux_pcm_rx_sample_rate_put),
  2847. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2848. aux_pcm_tx_sample_rate_get,
  2849. aux_pcm_tx_sample_rate_put),
  2850. };
  2851. static int bengal_send_island_va_config(int32_t be_id)
  2852. {
  2853. int rc = 0;
  2854. int port_id = 0xFFFF;
  2855. port_id = msm_get_port_id(be_id);
  2856. if (port_id < 0) {
  2857. pr_err("%s: Invalid island interface, be_id: %d\n",
  2858. __func__, be_id);
  2859. rc = -EINVAL;
  2860. } else {
  2861. /*
  2862. * send island mode config
  2863. * This should be the first configuration
  2864. */
  2865. rc = afe_send_port_island_mode(port_id);
  2866. if (rc)
  2867. pr_err("%s: afe send island mode failed %d\n",
  2868. __func__, rc);
  2869. }
  2870. return rc;
  2871. }
  2872. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  2873. struct snd_pcm_hw_params *params)
  2874. {
  2875. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  2876. struct snd_interval *rate = hw_param_interval(params,
  2877. SNDRV_PCM_HW_PARAM_RATE);
  2878. struct snd_interval *channels = hw_param_interval(params,
  2879. SNDRV_PCM_HW_PARAM_CHANNELS);
  2880. int idx = 0;
  2881. pr_debug("%s: format = %d, rate = %d\n",
  2882. __func__, params_format(params), params_rate(params));
  2883. switch (dai_link->id) {
  2884. case MSM_BACKEND_DAI_USB_RX:
  2885. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2886. usb_rx_cfg.bit_format);
  2887. rate->min = rate->max = usb_rx_cfg.sample_rate;
  2888. channels->min = channels->max = usb_rx_cfg.channels;
  2889. break;
  2890. case MSM_BACKEND_DAI_USB_TX:
  2891. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2892. usb_tx_cfg.bit_format);
  2893. rate->min = rate->max = usb_tx_cfg.sample_rate;
  2894. channels->min = channels->max = usb_tx_cfg.channels;
  2895. break;
  2896. case MSM_BACKEND_DAI_AFE_PCM_RX:
  2897. channels->min = channels->max = proxy_rx_cfg.channels;
  2898. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  2899. break;
  2900. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  2901. channels->min = channels->max =
  2902. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  2903. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2904. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  2905. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  2906. break;
  2907. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  2908. channels->min = channels->max =
  2909. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  2910. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2911. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  2912. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  2913. break;
  2914. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  2915. channels->min = channels->max =
  2916. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  2917. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2918. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  2919. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  2920. break;
  2921. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  2922. channels->min = channels->max =
  2923. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  2924. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2925. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  2926. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  2927. break;
  2928. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  2929. channels->min = channels->max =
  2930. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  2931. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2932. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  2933. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  2934. break;
  2935. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  2936. channels->min = channels->max =
  2937. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  2938. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2939. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  2940. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  2941. break;
  2942. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  2943. channels->min = channels->max =
  2944. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  2945. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2946. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  2947. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2948. break;
  2949. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  2950. channels->min = channels->max =
  2951. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  2952. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2953. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  2954. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  2955. break;
  2956. case MSM_BACKEND_DAI_AUXPCM_RX:
  2957. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2958. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  2959. rate->min = rate->max =
  2960. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  2961. channels->min = channels->max =
  2962. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  2963. break;
  2964. case MSM_BACKEND_DAI_AUXPCM_TX:
  2965. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2966. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  2967. rate->min = rate->max =
  2968. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  2969. channels->min = channels->max =
  2970. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  2971. break;
  2972. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  2973. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2974. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  2975. rate->min = rate->max =
  2976. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  2977. channels->min = channels->max =
  2978. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  2979. break;
  2980. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  2981. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2982. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  2983. rate->min = rate->max =
  2984. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  2985. channels->min = channels->max =
  2986. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  2987. break;
  2988. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  2989. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2990. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  2991. rate->min = rate->max =
  2992. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  2993. channels->min = channels->max =
  2994. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  2995. break;
  2996. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  2997. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  2998. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  2999. rate->min = rate->max =
  3000. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3001. channels->min = channels->max =
  3002. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3003. break;
  3004. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3005. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3006. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3007. rate->min = rate->max =
  3008. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3009. channels->min = channels->max =
  3010. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3011. break;
  3012. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3013. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3014. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3015. rate->min = rate->max =
  3016. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3017. channels->min = channels->max =
  3018. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3019. break;
  3020. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3021. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3022. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3023. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3024. channels->min = channels->max =
  3025. mi2s_rx_cfg[PRIM_MI2S].channels;
  3026. break;
  3027. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3028. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3029. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3030. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3031. channels->min = channels->max =
  3032. mi2s_tx_cfg[PRIM_MI2S].channels;
  3033. break;
  3034. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3035. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3036. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3037. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3038. channels->min = channels->max =
  3039. mi2s_rx_cfg[SEC_MI2S].channels;
  3040. break;
  3041. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3042. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3043. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3044. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3045. channels->min = channels->max =
  3046. mi2s_tx_cfg[SEC_MI2S].channels;
  3047. break;
  3048. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3049. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3050. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3051. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3052. channels->min = channels->max =
  3053. mi2s_rx_cfg[TERT_MI2S].channels;
  3054. break;
  3055. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3056. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3057. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3058. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3059. channels->min = channels->max =
  3060. mi2s_tx_cfg[TERT_MI2S].channels;
  3061. break;
  3062. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3063. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3064. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3065. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3066. channels->min = channels->max =
  3067. mi2s_rx_cfg[QUAT_MI2S].channels;
  3068. break;
  3069. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3070. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3071. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3072. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3073. channels->min = channels->max =
  3074. mi2s_tx_cfg[QUAT_MI2S].channels;
  3075. break;
  3076. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3077. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3078. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3079. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3080. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3081. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3082. cdc_dma_rx_cfg[idx].bit_format);
  3083. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3084. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3085. break;
  3086. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3087. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3088. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3089. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3090. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3091. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3092. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3093. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3094. cdc_dma_tx_cfg[idx].bit_format);
  3095. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3096. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3097. break;
  3098. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3099. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3100. slim_rx_cfg[SLIM_RX_7].bit_format);
  3101. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3102. channels->min = channels->max =
  3103. slim_rx_cfg[SLIM_RX_7].channels;
  3104. break;
  3105. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3106. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3107. slim_tx_cfg[SLIM_TX_7].bit_format);
  3108. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3109. channels->min = channels->max =
  3110. slim_tx_cfg[SLIM_TX_7].channels;
  3111. break;
  3112. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3113. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3114. channels->min = channels->max =
  3115. slim_tx_cfg[SLIM_TX_8].channels;
  3116. break;
  3117. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3118. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3119. afe_loopback_tx_cfg[idx].bit_format);
  3120. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3121. channels->min = channels->max =
  3122. afe_loopback_tx_cfg[idx].channels;
  3123. break;
  3124. default:
  3125. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3126. break;
  3127. }
  3128. return 0;
  3129. }
  3130. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component,
  3131. bool active)
  3132. {
  3133. struct snd_soc_card *card = component->card;
  3134. struct msm_asoc_mach_data *pdata =
  3135. snd_soc_card_get_drvdata(card);
  3136. if (!pdata->fsa_handle)
  3137. return false;
  3138. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3139. }
  3140. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3141. {
  3142. int value = 0;
  3143. bool ret = false;
  3144. struct snd_soc_card *card;
  3145. struct msm_asoc_mach_data *pdata;
  3146. if (!component) {
  3147. pr_err("%s component is NULL\n", __func__);
  3148. return false;
  3149. }
  3150. card = component->card;
  3151. pdata = snd_soc_card_get_drvdata(card);
  3152. if (!pdata)
  3153. return false;
  3154. if (wcd_mbhc_cfg.enable_usbc_analog)
  3155. return msm_usbc_swap_gnd_mic(component, active);
  3156. /* if usbc is not defined, swap using us_euro_gpio_p */
  3157. if (pdata->us_euro_gpio_p) {
  3158. value = msm_cdc_pinctrl_get_state(
  3159. pdata->us_euro_gpio_p);
  3160. if (value)
  3161. msm_cdc_pinctrl_select_sleep_state(
  3162. pdata->us_euro_gpio_p);
  3163. else
  3164. msm_cdc_pinctrl_select_active_state(
  3165. pdata->us_euro_gpio_p);
  3166. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3167. __func__, value, !value);
  3168. ret = true;
  3169. }
  3170. return ret;
  3171. }
  3172. static int bengal_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3173. struct snd_pcm_hw_params *params)
  3174. {
  3175. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3176. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3177. int ret = 0;
  3178. int slot_width = 32;
  3179. int channels, slots;
  3180. unsigned int slot_mask, rate, clk_freq;
  3181. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3182. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3183. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3184. switch (cpu_dai->id) {
  3185. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3186. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3187. break;
  3188. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3189. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3190. break;
  3191. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3192. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3193. break;
  3194. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3195. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3196. break;
  3197. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3198. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3199. break;
  3200. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3201. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3202. break;
  3203. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3204. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3205. break;
  3206. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3207. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3208. break;
  3209. default:
  3210. pr_err("%s: dai id 0x%x not supported\n",
  3211. __func__, cpu_dai->id);
  3212. return -EINVAL;
  3213. }
  3214. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3215. /*2 slot config - bits 0 and 1 set for the first two slots */
  3216. slot_mask = 0x0000FFFF >> (16 - slots);
  3217. channels = slots;
  3218. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3219. __func__, slot_width, slots);
  3220. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3221. slots, slot_width);
  3222. if (ret < 0) {
  3223. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3224. __func__, ret);
  3225. goto end;
  3226. }
  3227. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3228. 0, NULL, channels, slot_offset);
  3229. if (ret < 0) {
  3230. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3231. __func__, ret);
  3232. goto end;
  3233. }
  3234. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3235. /*2 slot config - bits 0 and 1 set for the first two slots */
  3236. slot_mask = 0x0000FFFF >> (16 - slots);
  3237. channels = slots;
  3238. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3239. __func__, slot_width, slots);
  3240. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3241. slots, slot_width);
  3242. if (ret < 0) {
  3243. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3244. __func__, ret);
  3245. goto end;
  3246. }
  3247. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3248. channels, slot_offset, 0, NULL);
  3249. if (ret < 0) {
  3250. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3251. __func__, ret);
  3252. goto end;
  3253. }
  3254. } else {
  3255. ret = -EINVAL;
  3256. pr_err("%s: invalid use case, err:%d\n",
  3257. __func__, ret);
  3258. goto end;
  3259. }
  3260. rate = params_rate(params);
  3261. clk_freq = rate * slot_width * slots;
  3262. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3263. if (ret < 0)
  3264. pr_err("%s: failed to set tdm clk, err:%d\n",
  3265. __func__, ret);
  3266. end:
  3267. return ret;
  3268. }
  3269. static int msm_get_tdm_mode(u32 port_id)
  3270. {
  3271. int tdm_mode;
  3272. switch (port_id) {
  3273. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3274. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3275. tdm_mode = TDM_PRI;
  3276. break;
  3277. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3278. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3279. tdm_mode = TDM_SEC;
  3280. break;
  3281. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3282. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3283. tdm_mode = TDM_TERT;
  3284. break;
  3285. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3286. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3287. tdm_mode = TDM_QUAT;
  3288. break;
  3289. default:
  3290. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3291. tdm_mode = -EINVAL;
  3292. }
  3293. return tdm_mode;
  3294. }
  3295. static int bengal_tdm_snd_startup(struct snd_pcm_substream *substream)
  3296. {
  3297. int ret = 0;
  3298. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3299. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3300. struct snd_soc_card *card = rtd->card;
  3301. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3302. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3303. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3304. ret = -EINVAL;
  3305. pr_err("%s: Invalid TDM interface %d\n",
  3306. __func__, ret);
  3307. return ret;
  3308. }
  3309. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3310. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3311. == 0) {
  3312. ret = msm_cdc_pinctrl_select_active_state(
  3313. pdata->mi2s_gpio_p[tdm_mode]);
  3314. if (ret) {
  3315. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3316. __func__, ret);
  3317. goto done;
  3318. }
  3319. }
  3320. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3321. }
  3322. done:
  3323. return ret;
  3324. }
  3325. static void bengal_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3326. {
  3327. int ret = 0;
  3328. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3329. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3330. struct snd_soc_card *card = rtd->card;
  3331. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3332. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3333. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3334. ret = -EINVAL;
  3335. pr_err("%s: Invalid TDM interface %d\n",
  3336. __func__, ret);
  3337. return;
  3338. }
  3339. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3340. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3341. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3342. == 0) {
  3343. ret = msm_cdc_pinctrl_select_sleep_state(
  3344. pdata->mi2s_gpio_p[tdm_mode]);
  3345. if (ret)
  3346. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3347. __func__, ret);
  3348. }
  3349. }
  3350. }
  3351. static int bengal_aux_snd_startup(struct snd_pcm_substream *substream)
  3352. {
  3353. int ret = 0;
  3354. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3355. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3356. struct snd_soc_card *card = rtd->card;
  3357. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3358. u32 aux_mode = cpu_dai->id - 1;
  3359. if (aux_mode >= AUX_PCM_MAX) {
  3360. ret = -EINVAL;
  3361. pr_err("%s: Invalid AUX interface %d\n",
  3362. __func__, ret);
  3363. return ret;
  3364. }
  3365. if (pdata->mi2s_gpio_p[aux_mode]) {
  3366. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3367. == 0) {
  3368. ret = msm_cdc_pinctrl_select_active_state(
  3369. pdata->mi2s_gpio_p[aux_mode]);
  3370. if (ret) {
  3371. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  3372. __func__, ret);
  3373. goto done;
  3374. }
  3375. }
  3376. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3377. }
  3378. done:
  3379. return ret;
  3380. }
  3381. static void bengal_aux_snd_shutdown(struct snd_pcm_substream *substream)
  3382. {
  3383. int ret = 0;
  3384. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3385. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3386. struct snd_soc_card *card = rtd->card;
  3387. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3388. u32 aux_mode = cpu_dai->id - 1;
  3389. if (aux_mode >= AUX_PCM_MAX) {
  3390. pr_err("%s: Invalid AUX interface %d\n",
  3391. __func__, ret);
  3392. return;
  3393. }
  3394. if (pdata->mi2s_gpio_p[aux_mode]) {
  3395. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3396. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3397. == 0) {
  3398. ret = msm_cdc_pinctrl_select_sleep_state(
  3399. pdata->mi2s_gpio_p[aux_mode]);
  3400. if (ret)
  3401. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  3402. __func__, ret);
  3403. }
  3404. }
  3405. }
  3406. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  3407. {
  3408. int ret = 0;
  3409. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3410. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3411. switch (dai_link->id) {
  3412. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3413. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3414. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3415. if (va_disable)
  3416. break;
  3417. ret = bengal_send_island_va_config(dai_link->id);
  3418. if (ret)
  3419. pr_err("%s: send island va cfg failed, err: %d\n",
  3420. __func__, ret);
  3421. break;
  3422. }
  3423. return ret;
  3424. }
  3425. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3426. struct snd_pcm_hw_params *params)
  3427. {
  3428. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3429. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3430. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3431. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3432. int ret = 0;
  3433. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3434. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3435. u32 user_set_tx_ch = 0;
  3436. u32 user_set_rx_ch = 0;
  3437. u32 ch_id;
  3438. ret = snd_soc_dai_get_channel_map(codec_dai,
  3439. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3440. &rx_ch_cdc_dma);
  3441. if (ret < 0) {
  3442. pr_err("%s: failed to get codec chan map, err:%d\n",
  3443. __func__, ret);
  3444. goto err;
  3445. }
  3446. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3447. switch (dai_link->id) {
  3448. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3449. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3450. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3451. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3452. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  3453. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  3454. {
  3455. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3456. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3457. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3458. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3459. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3460. user_set_rx_ch, &rx_ch_cdc_dma);
  3461. if (ret < 0) {
  3462. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3463. __func__, ret);
  3464. goto err;
  3465. }
  3466. }
  3467. break;
  3468. }
  3469. } else {
  3470. switch (dai_link->id) {
  3471. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3472. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3473. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3474. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3475. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3476. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3477. {
  3478. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3479. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3480. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3481. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3482. }
  3483. break;
  3484. }
  3485. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3486. &tx_ch_cdc_dma, 0, 0);
  3487. if (ret < 0) {
  3488. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3489. __func__, ret);
  3490. goto err;
  3491. }
  3492. }
  3493. err:
  3494. return ret;
  3495. }
  3496. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  3497. {
  3498. cpumask_t mask;
  3499. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  3500. pm_qos_remove_request(&substream->latency_pm_qos_req);
  3501. cpumask_clear(&mask);
  3502. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  3503. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  3504. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  3505. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  3506. pm_qos_add_request(&substream->latency_pm_qos_req,
  3507. PM_QOS_CPU_DMA_LATENCY,
  3508. MSM_LL_QOS_VALUE);
  3509. return 0;
  3510. }
  3511. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  3512. {
  3513. int ret = 0;
  3514. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3515. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3516. int index = cpu_dai->id;
  3517. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  3518. struct snd_soc_card *card = rtd->card;
  3519. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3520. dev_dbg(rtd->card->dev,
  3521. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  3522. __func__, substream->name, substream->stream,
  3523. cpu_dai->name, cpu_dai->id);
  3524. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3525. ret = -EINVAL;
  3526. dev_err(rtd->card->dev,
  3527. "%s: CPU DAI id (%d) out of range\n",
  3528. __func__, cpu_dai->id);
  3529. goto err;
  3530. }
  3531. /*
  3532. * Mutex protection in case the same MI2S
  3533. * interface using for both TX and RX so
  3534. * that the same clock won't be enable twice.
  3535. */
  3536. mutex_lock(&mi2s_intf_conf[index].lock);
  3537. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  3538. /* Check if msm needs to provide the clock to the interface */
  3539. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  3540. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  3541. fmt = SND_SOC_DAIFMT_CBM_CFM;
  3542. }
  3543. ret = msm_mi2s_set_sclk(substream, true);
  3544. if (ret < 0) {
  3545. dev_err(rtd->card->dev,
  3546. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  3547. __func__, ret);
  3548. goto clean_up;
  3549. }
  3550. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  3551. if (ret < 0) {
  3552. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  3553. __func__, index, ret);
  3554. goto clk_off;
  3555. }
  3556. if (pdata->mi2s_gpio_p[index]) {
  3557. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  3558. == 0) {
  3559. ret = msm_cdc_pinctrl_select_active_state(
  3560. pdata->mi2s_gpio_p[index]);
  3561. if (ret) {
  3562. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  3563. __func__, ret);
  3564. goto clk_off;
  3565. }
  3566. }
  3567. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  3568. }
  3569. }
  3570. clk_off:
  3571. if (ret < 0)
  3572. msm_mi2s_set_sclk(substream, false);
  3573. clean_up:
  3574. if (ret < 0)
  3575. mi2s_intf_conf[index].ref_cnt--;
  3576. mutex_unlock(&mi2s_intf_conf[index].lock);
  3577. err:
  3578. return ret;
  3579. }
  3580. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  3581. {
  3582. int ret = 0;
  3583. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3584. int index = rtd->cpu_dai->id;
  3585. struct snd_soc_card *card = rtd->card;
  3586. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3587. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  3588. substream->name, substream->stream);
  3589. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  3590. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  3591. return;
  3592. }
  3593. mutex_lock(&mi2s_intf_conf[index].lock);
  3594. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  3595. if (pdata->mi2s_gpio_p[index]) {
  3596. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  3597. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  3598. == 0) {
  3599. ret = msm_cdc_pinctrl_select_sleep_state(
  3600. pdata->mi2s_gpio_p[index]);
  3601. if (ret)
  3602. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  3603. __func__, ret);
  3604. }
  3605. }
  3606. ret = msm_mi2s_set_sclk(substream, false);
  3607. if (ret < 0)
  3608. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  3609. __func__, index, ret);
  3610. }
  3611. mutex_unlock(&mi2s_intf_conf[index].lock);
  3612. }
  3613. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3614. struct snd_pcm_hw_params *params)
  3615. {
  3616. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3617. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3618. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3619. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3620. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3621. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3622. int ret = 0;
  3623. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3624. codec_dai->name, codec_dai->id);
  3625. ret = snd_soc_dai_get_channel_map(codec_dai,
  3626. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3627. if (ret) {
  3628. dev_err(rtd->dev,
  3629. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3630. __func__, ret);
  3631. goto err;
  3632. }
  3633. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3634. __func__, tx_ch_cnt, dai_link->id);
  3635. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3636. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3637. if (ret)
  3638. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3639. __func__, ret);
  3640. err:
  3641. return ret;
  3642. }
  3643. static struct snd_soc_ops bengal_aux_be_ops = {
  3644. .startup = bengal_aux_snd_startup,
  3645. .shutdown = bengal_aux_snd_shutdown
  3646. };
  3647. static struct snd_soc_ops bengal_tdm_be_ops = {
  3648. .hw_params = bengal_tdm_snd_hw_params,
  3649. .startup = bengal_tdm_snd_startup,
  3650. .shutdown = bengal_tdm_snd_shutdown
  3651. };
  3652. static struct snd_soc_ops msm_mi2s_be_ops = {
  3653. .startup = msm_mi2s_snd_startup,
  3654. .shutdown = msm_mi2s_snd_shutdown,
  3655. };
  3656. static struct snd_soc_ops msm_fe_qos_ops = {
  3657. .prepare = msm_fe_qos_prepare,
  3658. };
  3659. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  3660. .startup = msm_snd_cdc_dma_startup,
  3661. .hw_params = msm_snd_cdc_dma_hw_params,
  3662. };
  3663. static struct snd_soc_ops msm_wcn_ops = {
  3664. .hw_params = msm_wcn_hw_params,
  3665. };
  3666. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  3667. struct snd_kcontrol *kcontrol, int event)
  3668. {
  3669. struct msm_asoc_mach_data *pdata = NULL;
  3670. struct snd_soc_component *component =
  3671. snd_soc_dapm_to_component(w->dapm);
  3672. int ret = 0;
  3673. u32 dmic_idx;
  3674. int *dmic_gpio_cnt;
  3675. struct device_node *dmic_gpio;
  3676. char *wname;
  3677. wname = strpbrk(w->name, "0123");
  3678. if (!wname) {
  3679. dev_err(component->dev, "%s: widget not found\n", __func__);
  3680. return -EINVAL;
  3681. }
  3682. ret = kstrtouint(wname, 10, &dmic_idx);
  3683. if (ret < 0) {
  3684. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  3685. __func__);
  3686. return -EINVAL;
  3687. }
  3688. pdata = snd_soc_card_get_drvdata(component->card);
  3689. switch (dmic_idx) {
  3690. case 0:
  3691. case 1:
  3692. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  3693. dmic_gpio = pdata->dmic01_gpio_p;
  3694. break;
  3695. case 2:
  3696. case 3:
  3697. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  3698. dmic_gpio = pdata->dmic23_gpio_p;
  3699. break;
  3700. default:
  3701. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  3702. __func__);
  3703. return -EINVAL;
  3704. }
  3705. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  3706. __func__, event, dmic_idx, *dmic_gpio_cnt);
  3707. switch (event) {
  3708. case SND_SOC_DAPM_PRE_PMU:
  3709. (*dmic_gpio_cnt)++;
  3710. if (*dmic_gpio_cnt == 1) {
  3711. ret = msm_cdc_pinctrl_select_active_state(
  3712. dmic_gpio);
  3713. if (ret < 0) {
  3714. pr_err("%s: gpio set cannot be activated %sd",
  3715. __func__, "dmic_gpio");
  3716. return ret;
  3717. }
  3718. }
  3719. break;
  3720. case SND_SOC_DAPM_POST_PMD:
  3721. (*dmic_gpio_cnt)--;
  3722. if (*dmic_gpio_cnt == 0) {
  3723. ret = msm_cdc_pinctrl_select_sleep_state(
  3724. dmic_gpio);
  3725. if (ret < 0) {
  3726. pr_err("%s: gpio set cannot be de-activated %sd",
  3727. __func__, "dmic_gpio");
  3728. return ret;
  3729. }
  3730. }
  3731. break;
  3732. default:
  3733. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  3734. return -EINVAL;
  3735. }
  3736. return 0;
  3737. }
  3738. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  3739. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  3740. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  3741. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  3742. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  3743. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3744. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3745. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3746. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3747. };
  3748. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3749. {
  3750. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3751. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3752. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3753. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3754. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3755. }
  3756. #ifndef CONFIG_TDM_DISABLE
  3757. static void msm_add_tdm_snd_controls(struct snd_soc_component *component)
  3758. {
  3759. snd_soc_add_component_controls(component, msm_tdm_snd_controls,
  3760. ARRAY_SIZE(msm_tdm_snd_controls));
  3761. }
  3762. #else
  3763. static void msm_add_tdm_snd_controls(struct snd_soc_component *component)
  3764. {
  3765. return;
  3766. }
  3767. #endif
  3768. #ifndef CONFIG_MI2S_DISABLE
  3769. static void msm_add_mi2s_snd_controls(struct snd_soc_component *component)
  3770. {
  3771. snd_soc_add_component_controls(component, msm_mi2s_snd_controls,
  3772. ARRAY_SIZE(msm_mi2s_snd_controls));
  3773. }
  3774. #else
  3775. static void msm_add_mi2s_snd_controls(struct snd_soc_component *component)
  3776. {
  3777. return;
  3778. }
  3779. #endif
  3780. #ifndef CONFIG_AUXPCM_DISABLE
  3781. static void msm_add_auxpcm_snd_controls(struct snd_soc_component *component)
  3782. {
  3783. snd_soc_add_component_controls(component, msm_auxpcm_snd_controls,
  3784. ARRAY_SIZE(msm_auxpcm_snd_controls));
  3785. }
  3786. #else
  3787. static void msm_add_auxpcm_snd_controls(struct snd_soc_component *component)
  3788. {
  3789. return;
  3790. }
  3791. #endif
  3792. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3793. {
  3794. int ret = -EINVAL;
  3795. struct snd_soc_component *component;
  3796. struct snd_soc_dapm_context *dapm;
  3797. struct snd_card *card;
  3798. struct snd_info_entry *entry;
  3799. struct msm_asoc_mach_data *pdata =
  3800. snd_soc_card_get_drvdata(rtd->card);
  3801. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  3802. if (!component) {
  3803. pr_err("%s: could not find component for bolero_codec\n",
  3804. __func__);
  3805. return ret;
  3806. }
  3807. dapm = snd_soc_component_get_dapm(component);
  3808. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  3809. ARRAY_SIZE(msm_int_snd_controls));
  3810. if (ret < 0) {
  3811. pr_err("%s: add_component_controls failed: %d\n",
  3812. __func__, ret);
  3813. return ret;
  3814. }
  3815. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  3816. ARRAY_SIZE(msm_common_snd_controls));
  3817. if (ret < 0) {
  3818. pr_err("%s: add common snd controls failed: %d\n",
  3819. __func__, ret);
  3820. return ret;
  3821. }
  3822. msm_add_tdm_snd_controls(component);
  3823. msm_add_mi2s_snd_controls(component);
  3824. msm_add_auxpcm_snd_controls(component);
  3825. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  3826. ARRAY_SIZE(msm_int_dapm_widgets));
  3827. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3828. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3829. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3830. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3831. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  3832. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  3833. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3834. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3835. snd_soc_dapm_sync(dapm);
  3836. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  3837. sm_port_map);
  3838. card = rtd->card->snd_card;
  3839. if (!pdata->codec_root) {
  3840. entry = snd_info_create_subdir(card->module, "codecs",
  3841. card->proc_root);
  3842. if (!entry) {
  3843. pr_debug("%s: Cannot create codecs module entry\n",
  3844. __func__);
  3845. ret = 0;
  3846. goto err;
  3847. }
  3848. pdata->codec_root = entry;
  3849. }
  3850. bolero_info_create_codec_entry(pdata->codec_root, component);
  3851. bolero_register_wake_irq(component, false);
  3852. codec_reg_done = true;
  3853. return 0;
  3854. err:
  3855. return ret;
  3856. }
  3857. static void *def_wcd_mbhc_cal(void)
  3858. {
  3859. void *wcd_mbhc_cal;
  3860. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  3861. u16 *btn_high;
  3862. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  3863. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  3864. if (!wcd_mbhc_cal)
  3865. return NULL;
  3866. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  3867. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  3868. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  3869. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  3870. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  3871. btn_high[0] = 75;
  3872. btn_high[1] = 150;
  3873. btn_high[2] = 237;
  3874. btn_high[3] = 500;
  3875. btn_high[4] = 500;
  3876. btn_high[5] = 500;
  3877. btn_high[6] = 500;
  3878. btn_high[7] = 500;
  3879. return wcd_mbhc_cal;
  3880. }
  3881. /* Digital audio interface glue - connects codec <---> CPU */
  3882. static struct snd_soc_dai_link msm_common_dai_links[] = {
  3883. /* FrontEnd DAI Links */
  3884. {/* hw:x,0 */
  3885. .name = MSM_DAILINK_NAME(Media1),
  3886. .stream_name = "MultiMedia1",
  3887. .cpu_dai_name = "MultiMedia1",
  3888. .platform_name = "msm-pcm-dsp.0",
  3889. .dynamic = 1,
  3890. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3891. .dpcm_playback = 1,
  3892. .dpcm_capture = 1,
  3893. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3894. SND_SOC_DPCM_TRIGGER_POST},
  3895. .codec_dai_name = "snd-soc-dummy-dai",
  3896. .codec_name = "snd-soc-dummy",
  3897. .ignore_suspend = 1,
  3898. /* this dainlink has playback support */
  3899. .ignore_pmdown_time = 1,
  3900. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  3901. },
  3902. {/* hw:x,1 */
  3903. .name = MSM_DAILINK_NAME(Media2),
  3904. .stream_name = "MultiMedia2",
  3905. .cpu_dai_name = "MultiMedia2",
  3906. .platform_name = "msm-pcm-dsp.0",
  3907. .dynamic = 1,
  3908. .dpcm_playback = 1,
  3909. .dpcm_capture = 1,
  3910. .codec_dai_name = "snd-soc-dummy-dai",
  3911. .codec_name = "snd-soc-dummy",
  3912. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3913. SND_SOC_DPCM_TRIGGER_POST},
  3914. .ignore_suspend = 1,
  3915. /* this dainlink has playback support */
  3916. .ignore_pmdown_time = 1,
  3917. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  3918. },
  3919. {/* hw:x,2 */
  3920. .name = "VoiceMMode1",
  3921. .stream_name = "VoiceMMode1",
  3922. .cpu_dai_name = "VoiceMMode1",
  3923. .platform_name = "msm-pcm-voice",
  3924. .dynamic = 1,
  3925. .dpcm_playback = 1,
  3926. .dpcm_capture = 1,
  3927. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3928. SND_SOC_DPCM_TRIGGER_POST},
  3929. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  3930. .ignore_suspend = 1,
  3931. .ignore_pmdown_time = 1,
  3932. .codec_dai_name = "snd-soc-dummy-dai",
  3933. .codec_name = "snd-soc-dummy",
  3934. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  3935. },
  3936. {/* hw:x,3 */
  3937. .name = "MSM VoIP",
  3938. .stream_name = "VoIP",
  3939. .cpu_dai_name = "VoIP",
  3940. .platform_name = "msm-voip-dsp",
  3941. .dynamic = 1,
  3942. .dpcm_playback = 1,
  3943. .dpcm_capture = 1,
  3944. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3945. SND_SOC_DPCM_TRIGGER_POST},
  3946. .codec_dai_name = "snd-soc-dummy-dai",
  3947. .codec_name = "snd-soc-dummy",
  3948. .ignore_suspend = 1,
  3949. /* this dainlink has playback support */
  3950. .ignore_pmdown_time = 1,
  3951. .id = MSM_FRONTEND_DAI_VOIP,
  3952. },
  3953. {/* hw:x,4 */
  3954. .name = MSM_DAILINK_NAME(ULL),
  3955. .stream_name = "MultiMedia3",
  3956. .cpu_dai_name = "MultiMedia3",
  3957. .platform_name = "msm-pcm-dsp.2",
  3958. .dynamic = 1,
  3959. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  3960. .dpcm_playback = 1,
  3961. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  3962. SND_SOC_DPCM_TRIGGER_POST},
  3963. .codec_dai_name = "snd-soc-dummy-dai",
  3964. .codec_name = "snd-soc-dummy",
  3965. .ignore_suspend = 1,
  3966. /* this dainlink has playback support */
  3967. .ignore_pmdown_time = 1,
  3968. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  3969. },
  3970. {/* hw:x,5 */
  3971. .name = "MSM AFE-PCM RX",
  3972. .stream_name = "AFE-PROXY RX",
  3973. .cpu_dai_name = "msm-dai-q6-dev.241",
  3974. .codec_name = "msm-stub-codec.1",
  3975. .codec_dai_name = "msm-stub-rx",
  3976. .platform_name = "msm-pcm-afe",
  3977. .dpcm_playback = 1,
  3978. .ignore_suspend = 1,
  3979. /* this dainlink has playback support */
  3980. .ignore_pmdown_time = 1,
  3981. },
  3982. {/* hw:x,6 */
  3983. .name = "MSM AFE-PCM TX",
  3984. .stream_name = "AFE-PROXY TX",
  3985. .cpu_dai_name = "msm-dai-q6-dev.240",
  3986. .codec_name = "msm-stub-codec.1",
  3987. .codec_dai_name = "msm-stub-tx",
  3988. .platform_name = "msm-pcm-afe",
  3989. .dpcm_capture = 1,
  3990. .ignore_suspend = 1,
  3991. },
  3992. {/* hw:x,7 */
  3993. .name = MSM_DAILINK_NAME(Compress1),
  3994. .stream_name = "Compress1",
  3995. .cpu_dai_name = "MultiMedia4",
  3996. .platform_name = "msm-compress-dsp",
  3997. .dynamic = 1,
  3998. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  3999. .dpcm_playback = 1,
  4000. .dpcm_capture = 1,
  4001. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4002. SND_SOC_DPCM_TRIGGER_POST},
  4003. .codec_dai_name = "snd-soc-dummy-dai",
  4004. .codec_name = "snd-soc-dummy",
  4005. .ignore_suspend = 1,
  4006. .ignore_pmdown_time = 1,
  4007. /* this dainlink has playback support */
  4008. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4009. },
  4010. /* Hostless PCM purpose */
  4011. {/* hw:x,8 */
  4012. .name = "AUXPCM Hostless",
  4013. .stream_name = "AUXPCM Hostless",
  4014. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4015. .platform_name = "msm-pcm-hostless",
  4016. .dynamic = 1,
  4017. .dpcm_playback = 1,
  4018. .dpcm_capture = 1,
  4019. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4020. SND_SOC_DPCM_TRIGGER_POST},
  4021. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4022. .ignore_suspend = 1,
  4023. /* this dainlink has playback support */
  4024. .ignore_pmdown_time = 1,
  4025. .codec_dai_name = "snd-soc-dummy-dai",
  4026. .codec_name = "snd-soc-dummy",
  4027. },
  4028. {/* hw:x,9 */
  4029. .name = MSM_DAILINK_NAME(LowLatency),
  4030. .stream_name = "MultiMedia5",
  4031. .cpu_dai_name = "MultiMedia5",
  4032. .platform_name = "msm-pcm-dsp.1",
  4033. .dynamic = 1,
  4034. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4035. .dpcm_playback = 1,
  4036. .dpcm_capture = 1,
  4037. .codec_dai_name = "snd-soc-dummy-dai",
  4038. .codec_name = "snd-soc-dummy",
  4039. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4040. SND_SOC_DPCM_TRIGGER_POST},
  4041. .ignore_suspend = 1,
  4042. /* this dainlink has playback support */
  4043. .ignore_pmdown_time = 1,
  4044. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4045. .ops = &msm_fe_qos_ops,
  4046. },
  4047. {/* hw:x,10 */
  4048. .name = "Listen 1 Audio Service",
  4049. .stream_name = "Listen 1 Audio Service",
  4050. .cpu_dai_name = "LSM1",
  4051. .platform_name = "msm-lsm-client",
  4052. .dynamic = 1,
  4053. .dpcm_capture = 1,
  4054. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4055. SND_SOC_DPCM_TRIGGER_POST },
  4056. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4057. .ignore_suspend = 1,
  4058. .codec_dai_name = "snd-soc-dummy-dai",
  4059. .codec_name = "snd-soc-dummy",
  4060. .id = MSM_FRONTEND_DAI_LSM1,
  4061. },
  4062. /* Multiple Tunnel instances */
  4063. {/* hw:x,11 */
  4064. .name = MSM_DAILINK_NAME(Compress2),
  4065. .stream_name = "Compress2",
  4066. .cpu_dai_name = "MultiMedia7",
  4067. .platform_name = "msm-compress-dsp",
  4068. .dynamic = 1,
  4069. .dpcm_playback = 1,
  4070. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4071. SND_SOC_DPCM_TRIGGER_POST},
  4072. .codec_dai_name = "snd-soc-dummy-dai",
  4073. .codec_name = "snd-soc-dummy",
  4074. .ignore_suspend = 1,
  4075. .ignore_pmdown_time = 1,
  4076. /* this dainlink has playback support */
  4077. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4078. },
  4079. {/* hw:x,12 */
  4080. .name = MSM_DAILINK_NAME(MultiMedia10),
  4081. .stream_name = "MultiMedia10",
  4082. .cpu_dai_name = "MultiMedia10",
  4083. .platform_name = "msm-pcm-dsp.1",
  4084. .dynamic = 1,
  4085. .dpcm_playback = 1,
  4086. .dpcm_capture = 1,
  4087. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4088. SND_SOC_DPCM_TRIGGER_POST},
  4089. .codec_dai_name = "snd-soc-dummy-dai",
  4090. .codec_name = "snd-soc-dummy",
  4091. .ignore_suspend = 1,
  4092. .ignore_pmdown_time = 1,
  4093. /* this dainlink has playback support */
  4094. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4095. },
  4096. {/* hw:x,13 */
  4097. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4098. .stream_name = "MM_NOIRQ",
  4099. .cpu_dai_name = "MultiMedia8",
  4100. .platform_name = "msm-pcm-dsp-noirq",
  4101. .dynamic = 1,
  4102. .dpcm_playback = 1,
  4103. .dpcm_capture = 1,
  4104. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4105. SND_SOC_DPCM_TRIGGER_POST},
  4106. .codec_dai_name = "snd-soc-dummy-dai",
  4107. .codec_name = "snd-soc-dummy",
  4108. .ignore_suspend = 1,
  4109. .ignore_pmdown_time = 1,
  4110. /* this dainlink has playback support */
  4111. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4112. .ops = &msm_fe_qos_ops,
  4113. },
  4114. /* HDMI Hostless */
  4115. {/* hw:x,14 */
  4116. .name = "HDMI_RX_HOSTLESS",
  4117. .stream_name = "HDMI_RX_HOSTLESS",
  4118. .cpu_dai_name = "HDMI_HOSTLESS",
  4119. .platform_name = "msm-pcm-hostless",
  4120. .dynamic = 1,
  4121. .dpcm_playback = 1,
  4122. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4123. SND_SOC_DPCM_TRIGGER_POST},
  4124. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4125. .ignore_suspend = 1,
  4126. .ignore_pmdown_time = 1,
  4127. .codec_dai_name = "snd-soc-dummy-dai",
  4128. .codec_name = "snd-soc-dummy",
  4129. },
  4130. {/* hw:x,15 */
  4131. .name = "VoiceMMode2",
  4132. .stream_name = "VoiceMMode2",
  4133. .cpu_dai_name = "VoiceMMode2",
  4134. .platform_name = "msm-pcm-voice",
  4135. .dynamic = 1,
  4136. .dpcm_playback = 1,
  4137. .dpcm_capture = 1,
  4138. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4139. SND_SOC_DPCM_TRIGGER_POST},
  4140. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4141. .ignore_suspend = 1,
  4142. .ignore_pmdown_time = 1,
  4143. .codec_dai_name = "snd-soc-dummy-dai",
  4144. .codec_name = "snd-soc-dummy",
  4145. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4146. },
  4147. /* LSM FE */
  4148. {/* hw:x,16 */
  4149. .name = "Listen 2 Audio Service",
  4150. .stream_name = "Listen 2 Audio Service",
  4151. .cpu_dai_name = "LSM2",
  4152. .platform_name = "msm-lsm-client",
  4153. .dynamic = 1,
  4154. .dpcm_capture = 1,
  4155. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4156. SND_SOC_DPCM_TRIGGER_POST },
  4157. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4158. .ignore_suspend = 1,
  4159. .codec_dai_name = "snd-soc-dummy-dai",
  4160. .codec_name = "snd-soc-dummy",
  4161. .id = MSM_FRONTEND_DAI_LSM2,
  4162. },
  4163. {/* hw:x,17 */
  4164. .name = "Listen 3 Audio Service",
  4165. .stream_name = "Listen 3 Audio Service",
  4166. .cpu_dai_name = "LSM3",
  4167. .platform_name = "msm-lsm-client",
  4168. .dynamic = 1,
  4169. .dpcm_capture = 1,
  4170. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4171. SND_SOC_DPCM_TRIGGER_POST },
  4172. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4173. .ignore_suspend = 1,
  4174. .codec_dai_name = "snd-soc-dummy-dai",
  4175. .codec_name = "snd-soc-dummy",
  4176. .id = MSM_FRONTEND_DAI_LSM3,
  4177. },
  4178. {/* hw:x,18 */
  4179. .name = "Listen 4 Audio Service",
  4180. .stream_name = "Listen 4 Audio Service",
  4181. .cpu_dai_name = "LSM4",
  4182. .platform_name = "msm-lsm-client",
  4183. .dynamic = 1,
  4184. .dpcm_capture = 1,
  4185. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4186. SND_SOC_DPCM_TRIGGER_POST },
  4187. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4188. .ignore_suspend = 1,
  4189. .codec_dai_name = "snd-soc-dummy-dai",
  4190. .codec_name = "snd-soc-dummy",
  4191. .id = MSM_FRONTEND_DAI_LSM4,
  4192. },
  4193. {/* hw:x,19 */
  4194. .name = "Listen 5 Audio Service",
  4195. .stream_name = "Listen 5 Audio Service",
  4196. .cpu_dai_name = "LSM5",
  4197. .platform_name = "msm-lsm-client",
  4198. .dynamic = 1,
  4199. .dpcm_capture = 1,
  4200. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4201. SND_SOC_DPCM_TRIGGER_POST },
  4202. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4203. .ignore_suspend = 1,
  4204. .codec_dai_name = "snd-soc-dummy-dai",
  4205. .codec_name = "snd-soc-dummy",
  4206. .id = MSM_FRONTEND_DAI_LSM5,
  4207. },
  4208. {/* hw:x,20 */
  4209. .name = "Listen 6 Audio Service",
  4210. .stream_name = "Listen 6 Audio Service",
  4211. .cpu_dai_name = "LSM6",
  4212. .platform_name = "msm-lsm-client",
  4213. .dynamic = 1,
  4214. .dpcm_capture = 1,
  4215. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4216. SND_SOC_DPCM_TRIGGER_POST },
  4217. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4218. .ignore_suspend = 1,
  4219. .codec_dai_name = "snd-soc-dummy-dai",
  4220. .codec_name = "snd-soc-dummy",
  4221. .id = MSM_FRONTEND_DAI_LSM6,
  4222. },
  4223. {/* hw:x,21 */
  4224. .name = "Listen 7 Audio Service",
  4225. .stream_name = "Listen 7 Audio Service",
  4226. .cpu_dai_name = "LSM7",
  4227. .platform_name = "msm-lsm-client",
  4228. .dynamic = 1,
  4229. .dpcm_capture = 1,
  4230. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4231. SND_SOC_DPCM_TRIGGER_POST },
  4232. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4233. .ignore_suspend = 1,
  4234. .codec_dai_name = "snd-soc-dummy-dai",
  4235. .codec_name = "snd-soc-dummy",
  4236. .id = MSM_FRONTEND_DAI_LSM7,
  4237. },
  4238. {/* hw:x,22 */
  4239. .name = "Listen 8 Audio Service",
  4240. .stream_name = "Listen 8 Audio Service",
  4241. .cpu_dai_name = "LSM8",
  4242. .platform_name = "msm-lsm-client",
  4243. .dynamic = 1,
  4244. .dpcm_capture = 1,
  4245. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4246. SND_SOC_DPCM_TRIGGER_POST },
  4247. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4248. .ignore_suspend = 1,
  4249. .codec_dai_name = "snd-soc-dummy-dai",
  4250. .codec_name = "snd-soc-dummy",
  4251. .id = MSM_FRONTEND_DAI_LSM8,
  4252. },
  4253. {/* hw:x,23 */
  4254. .name = MSM_DAILINK_NAME(Media9),
  4255. .stream_name = "MultiMedia9",
  4256. .cpu_dai_name = "MultiMedia9",
  4257. .platform_name = "msm-pcm-dsp.0",
  4258. .dynamic = 1,
  4259. .dpcm_playback = 1,
  4260. .dpcm_capture = 1,
  4261. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4262. SND_SOC_DPCM_TRIGGER_POST},
  4263. .codec_dai_name = "snd-soc-dummy-dai",
  4264. .codec_name = "snd-soc-dummy",
  4265. .ignore_suspend = 1,
  4266. /* this dainlink has playback support */
  4267. .ignore_pmdown_time = 1,
  4268. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4269. },
  4270. {/* hw:x,24 */
  4271. .name = MSM_DAILINK_NAME(Compress4),
  4272. .stream_name = "Compress4",
  4273. .cpu_dai_name = "MultiMedia11",
  4274. .platform_name = "msm-compress-dsp",
  4275. .dynamic = 1,
  4276. .dpcm_playback = 1,
  4277. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4278. SND_SOC_DPCM_TRIGGER_POST},
  4279. .codec_dai_name = "snd-soc-dummy-dai",
  4280. .codec_name = "snd-soc-dummy",
  4281. .ignore_suspend = 1,
  4282. .ignore_pmdown_time = 1,
  4283. /* this dainlink has playback support */
  4284. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4285. },
  4286. {/* hw:x,25 */
  4287. .name = MSM_DAILINK_NAME(Compress5),
  4288. .stream_name = "Compress5",
  4289. .cpu_dai_name = "MultiMedia12",
  4290. .platform_name = "msm-compress-dsp",
  4291. .dynamic = 1,
  4292. .dpcm_playback = 1,
  4293. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4294. SND_SOC_DPCM_TRIGGER_POST},
  4295. .codec_dai_name = "snd-soc-dummy-dai",
  4296. .codec_name = "snd-soc-dummy",
  4297. .ignore_suspend = 1,
  4298. .ignore_pmdown_time = 1,
  4299. /* this dainlink has playback support */
  4300. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4301. },
  4302. {/* hw:x,26 */
  4303. .name = MSM_DAILINK_NAME(Compress6),
  4304. .stream_name = "Compress6",
  4305. .cpu_dai_name = "MultiMedia13",
  4306. .platform_name = "msm-compress-dsp",
  4307. .dynamic = 1,
  4308. .dpcm_playback = 1,
  4309. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4310. SND_SOC_DPCM_TRIGGER_POST},
  4311. .codec_dai_name = "snd-soc-dummy-dai",
  4312. .codec_name = "snd-soc-dummy",
  4313. .ignore_suspend = 1,
  4314. .ignore_pmdown_time = 1,
  4315. /* this dainlink has playback support */
  4316. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4317. },
  4318. {/* hw:x,27 */
  4319. .name = MSM_DAILINK_NAME(Compress7),
  4320. .stream_name = "Compress7",
  4321. .cpu_dai_name = "MultiMedia14",
  4322. .platform_name = "msm-compress-dsp",
  4323. .dynamic = 1,
  4324. .dpcm_playback = 1,
  4325. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4326. SND_SOC_DPCM_TRIGGER_POST},
  4327. .codec_dai_name = "snd-soc-dummy-dai",
  4328. .codec_name = "snd-soc-dummy",
  4329. .ignore_suspend = 1,
  4330. .ignore_pmdown_time = 1,
  4331. /* this dainlink has playback support */
  4332. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4333. },
  4334. {/* hw:x,28 */
  4335. .name = MSM_DAILINK_NAME(Compress8),
  4336. .stream_name = "Compress8",
  4337. .cpu_dai_name = "MultiMedia15",
  4338. .platform_name = "msm-compress-dsp",
  4339. .dynamic = 1,
  4340. .dpcm_playback = 1,
  4341. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4342. SND_SOC_DPCM_TRIGGER_POST},
  4343. .codec_dai_name = "snd-soc-dummy-dai",
  4344. .codec_name = "snd-soc-dummy",
  4345. .ignore_suspend = 1,
  4346. .ignore_pmdown_time = 1,
  4347. /* this dainlink has playback support */
  4348. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  4349. },
  4350. {/* hw:x,29 */
  4351. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  4352. .stream_name = "MM_NOIRQ_2",
  4353. .cpu_dai_name = "MultiMedia16",
  4354. .platform_name = "msm-pcm-dsp-noirq",
  4355. .dynamic = 1,
  4356. .dpcm_playback = 1,
  4357. .dpcm_capture = 1,
  4358. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4359. SND_SOC_DPCM_TRIGGER_POST},
  4360. .codec_dai_name = "snd-soc-dummy-dai",
  4361. .codec_name = "snd-soc-dummy",
  4362. .ignore_suspend = 1,
  4363. .ignore_pmdown_time = 1,
  4364. /* this dainlink has playback support */
  4365. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  4366. .ops = &msm_fe_qos_ops,
  4367. },
  4368. {/* hw:x,30 */
  4369. .name = "CDC_DMA Hostless",
  4370. .stream_name = "CDC_DMA Hostless",
  4371. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  4372. .platform_name = "msm-pcm-hostless",
  4373. .dynamic = 1,
  4374. .dpcm_playback = 1,
  4375. .dpcm_capture = 1,
  4376. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4377. SND_SOC_DPCM_TRIGGER_POST},
  4378. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4379. .ignore_suspend = 1,
  4380. /* this dailink has playback support */
  4381. .ignore_pmdown_time = 1,
  4382. .codec_dai_name = "snd-soc-dummy-dai",
  4383. .codec_name = "snd-soc-dummy",
  4384. },
  4385. {/* hw:x,31 */
  4386. .name = "TX3_CDC_DMA Hostless",
  4387. .stream_name = "TX3_CDC_DMA Hostless",
  4388. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  4389. .platform_name = "msm-pcm-hostless",
  4390. .dynamic = 1,
  4391. .dpcm_capture = 1,
  4392. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4393. SND_SOC_DPCM_TRIGGER_POST},
  4394. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4395. .ignore_suspend = 1,
  4396. .codec_dai_name = "snd-soc-dummy-dai",
  4397. .codec_name = "snd-soc-dummy",
  4398. },
  4399. {/* hw:x,32 */
  4400. .name = "Tertiary MI2S TX_Hostless",
  4401. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  4402. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  4403. .platform_name = "msm-pcm-hostless",
  4404. .dynamic = 1,
  4405. .dpcm_capture = 1,
  4406. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4407. SND_SOC_DPCM_TRIGGER_POST},
  4408. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4409. .ignore_suspend = 1,
  4410. .ignore_pmdown_time = 1,
  4411. .codec_dai_name = "snd-soc-dummy-dai",
  4412. .codec_name = "snd-soc-dummy",
  4413. },
  4414. };
  4415. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  4416. {/* hw:x,33 */
  4417. .name = MSM_DAILINK_NAME(ASM Loopback),
  4418. .stream_name = "MultiMedia6",
  4419. .cpu_dai_name = "MultiMedia6",
  4420. .platform_name = "msm-pcm-loopback",
  4421. .dynamic = 1,
  4422. .dpcm_playback = 1,
  4423. .dpcm_capture = 1,
  4424. .codec_dai_name = "snd-soc-dummy-dai",
  4425. .codec_name = "snd-soc-dummy",
  4426. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4427. SND_SOC_DPCM_TRIGGER_POST},
  4428. .ignore_suspend = 1,
  4429. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4430. .ignore_pmdown_time = 1,
  4431. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  4432. },
  4433. {/* hw:x,34 */
  4434. .name = "USB Audio Hostless",
  4435. .stream_name = "USB Audio Hostless",
  4436. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  4437. .platform_name = "msm-pcm-hostless",
  4438. .dynamic = 1,
  4439. .dpcm_playback = 1,
  4440. .dpcm_capture = 1,
  4441. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4442. SND_SOC_DPCM_TRIGGER_POST},
  4443. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4444. .ignore_suspend = 1,
  4445. .ignore_pmdown_time = 1,
  4446. .codec_dai_name = "snd-soc-dummy-dai",
  4447. .codec_name = "snd-soc-dummy",
  4448. },
  4449. {/* hw:x,35 */
  4450. .name = "SLIMBUS_7 Hostless",
  4451. .stream_name = "SLIMBUS_7 Hostless",
  4452. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  4453. .platform_name = "msm-pcm-hostless",
  4454. .dynamic = 1,
  4455. .dpcm_capture = 1,
  4456. .dpcm_playback = 1,
  4457. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4458. SND_SOC_DPCM_TRIGGER_POST},
  4459. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4460. .ignore_suspend = 1,
  4461. .ignore_pmdown_time = 1,
  4462. .codec_dai_name = "snd-soc-dummy-dai",
  4463. .codec_name = "snd-soc-dummy",
  4464. },
  4465. {/* hw:x,36 */
  4466. .name = "Compress Capture",
  4467. .stream_name = "Compress9",
  4468. .cpu_dai_name = "MultiMedia17",
  4469. .platform_name = "msm-compress-dsp",
  4470. .dynamic = 1,
  4471. .dpcm_capture = 1,
  4472. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4473. SND_SOC_DPCM_TRIGGER_POST},
  4474. .codec_dai_name = "snd-soc-dummy-dai",
  4475. .codec_name = "snd-soc-dummy",
  4476. .ignore_suspend = 1,
  4477. .ignore_pmdown_time = 1,
  4478. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  4479. },
  4480. {/* hw:x,37 */
  4481. .name = "SLIMBUS_8 Hostless",
  4482. .stream_name = "SLIMBUS_8 Hostless",
  4483. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  4484. .platform_name = "msm-pcm-hostless",
  4485. .dynamic = 1,
  4486. .dpcm_capture = 1,
  4487. .dpcm_playback = 1,
  4488. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4489. SND_SOC_DPCM_TRIGGER_POST},
  4490. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4491. .ignore_suspend = 1,
  4492. .ignore_pmdown_time = 1,
  4493. .codec_dai_name = "snd-soc-dummy-dai",
  4494. .codec_name = "snd-soc-dummy",
  4495. },
  4496. {/* hw:x,38 */
  4497. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  4498. .stream_name = "TX CDC DMA5 Capture",
  4499. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  4500. .platform_name = "msm-pcm-hostless",
  4501. .codec_name = "bolero_codec",
  4502. .codec_dai_name = "tx_macro_tx3",
  4503. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  4504. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4505. .ignore_suspend = 1,
  4506. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4507. .ops = &msm_cdc_dma_be_ops,
  4508. },
  4509. };
  4510. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  4511. /* Backend AFE DAI Links */
  4512. {
  4513. .name = LPASS_BE_AFE_PCM_RX,
  4514. .stream_name = "AFE Playback",
  4515. .cpu_dai_name = "msm-dai-q6-dev.224",
  4516. .platform_name = "msm-pcm-routing",
  4517. .codec_name = "msm-stub-codec.1",
  4518. .codec_dai_name = "msm-stub-rx",
  4519. .no_pcm = 1,
  4520. .dpcm_playback = 1,
  4521. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  4522. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4523. /* this dainlink has playback support */
  4524. .ignore_pmdown_time = 1,
  4525. .ignore_suspend = 1,
  4526. },
  4527. {
  4528. .name = LPASS_BE_AFE_PCM_TX,
  4529. .stream_name = "AFE Capture",
  4530. .cpu_dai_name = "msm-dai-q6-dev.225",
  4531. .platform_name = "msm-pcm-routing",
  4532. .codec_name = "msm-stub-codec.1",
  4533. .codec_dai_name = "msm-stub-tx",
  4534. .no_pcm = 1,
  4535. .dpcm_capture = 1,
  4536. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  4537. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4538. .ignore_suspend = 1,
  4539. },
  4540. /* Incall Record Uplink BACK END DAI Link */
  4541. {
  4542. .name = LPASS_BE_INCALL_RECORD_TX,
  4543. .stream_name = "Voice Uplink Capture",
  4544. .cpu_dai_name = "msm-dai-q6-dev.32772",
  4545. .platform_name = "msm-pcm-routing",
  4546. .codec_name = "msm-stub-codec.1",
  4547. .codec_dai_name = "msm-stub-tx",
  4548. .no_pcm = 1,
  4549. .dpcm_capture = 1,
  4550. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  4551. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4552. .ignore_suspend = 1,
  4553. },
  4554. /* Incall Record Downlink BACK END DAI Link */
  4555. {
  4556. .name = LPASS_BE_INCALL_RECORD_RX,
  4557. .stream_name = "Voice Downlink Capture",
  4558. .cpu_dai_name = "msm-dai-q6-dev.32771",
  4559. .platform_name = "msm-pcm-routing",
  4560. .codec_name = "msm-stub-codec.1",
  4561. .codec_dai_name = "msm-stub-tx",
  4562. .no_pcm = 1,
  4563. .dpcm_capture = 1,
  4564. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  4565. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4566. .ignore_suspend = 1,
  4567. },
  4568. /* Incall Music BACK END DAI Link */
  4569. {
  4570. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  4571. .stream_name = "Voice Farend Playback",
  4572. .cpu_dai_name = "msm-dai-q6-dev.32773",
  4573. .platform_name = "msm-pcm-routing",
  4574. .codec_name = "msm-stub-codec.1",
  4575. .codec_dai_name = "msm-stub-rx",
  4576. .no_pcm = 1,
  4577. .dpcm_playback = 1,
  4578. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  4579. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4580. .ignore_suspend = 1,
  4581. .ignore_pmdown_time = 1,
  4582. },
  4583. /* Incall Music 2 BACK END DAI Link */
  4584. {
  4585. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  4586. .stream_name = "Voice2 Farend Playback",
  4587. .cpu_dai_name = "msm-dai-q6-dev.32770",
  4588. .platform_name = "msm-pcm-routing",
  4589. .codec_name = "msm-stub-codec.1",
  4590. .codec_dai_name = "msm-stub-rx",
  4591. .no_pcm = 1,
  4592. .dpcm_playback = 1,
  4593. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  4594. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4595. .ignore_suspend = 1,
  4596. .ignore_pmdown_time = 1,
  4597. },
  4598. {
  4599. .name = LPASS_BE_USB_AUDIO_RX,
  4600. .stream_name = "USB Audio Playback",
  4601. .cpu_dai_name = "msm-dai-q6-dev.28672",
  4602. .platform_name = "msm-pcm-routing",
  4603. .codec_name = "msm-stub-codec.1",
  4604. .codec_dai_name = "msm-stub-rx",
  4605. .dynamic_be = 1,
  4606. .no_pcm = 1,
  4607. .dpcm_playback = 1,
  4608. .id = MSM_BACKEND_DAI_USB_RX,
  4609. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4610. .ignore_pmdown_time = 1,
  4611. .ignore_suspend = 1,
  4612. },
  4613. {
  4614. .name = LPASS_BE_USB_AUDIO_TX,
  4615. .stream_name = "USB Audio Capture",
  4616. .cpu_dai_name = "msm-dai-q6-dev.28673",
  4617. .platform_name = "msm-pcm-routing",
  4618. .codec_name = "msm-stub-codec.1",
  4619. .codec_dai_name = "msm-stub-tx",
  4620. .no_pcm = 1,
  4621. .dpcm_capture = 1,
  4622. .id = MSM_BACKEND_DAI_USB_TX,
  4623. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4624. .ignore_suspend = 1,
  4625. },
  4626. };
  4627. static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
  4628. {
  4629. .name = LPASS_BE_PRI_TDM_RX_0,
  4630. .stream_name = "Primary TDM0 Playback",
  4631. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  4632. .platform_name = "msm-pcm-routing",
  4633. .codec_name = "msm-stub-codec.1",
  4634. .codec_dai_name = "msm-stub-rx",
  4635. .no_pcm = 1,
  4636. .dpcm_playback = 1,
  4637. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  4638. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4639. .ops = &bengal_tdm_be_ops,
  4640. .ignore_suspend = 1,
  4641. .ignore_pmdown_time = 1,
  4642. },
  4643. {
  4644. .name = LPASS_BE_PRI_TDM_TX_0,
  4645. .stream_name = "Primary TDM0 Capture",
  4646. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  4647. .platform_name = "msm-pcm-routing",
  4648. .codec_name = "msm-stub-codec.1",
  4649. .codec_dai_name = "msm-stub-tx",
  4650. .no_pcm = 1,
  4651. .dpcm_capture = 1,
  4652. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  4653. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4654. .ops = &bengal_tdm_be_ops,
  4655. .ignore_suspend = 1,
  4656. },
  4657. {
  4658. .name = LPASS_BE_SEC_TDM_RX_0,
  4659. .stream_name = "Secondary TDM0 Playback",
  4660. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  4661. .platform_name = "msm-pcm-routing",
  4662. .codec_name = "msm-stub-codec.1",
  4663. .codec_dai_name = "msm-stub-rx",
  4664. .no_pcm = 1,
  4665. .dpcm_playback = 1,
  4666. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  4667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4668. .ops = &bengal_tdm_be_ops,
  4669. .ignore_suspend = 1,
  4670. .ignore_pmdown_time = 1,
  4671. },
  4672. {
  4673. .name = LPASS_BE_SEC_TDM_TX_0,
  4674. .stream_name = "Secondary TDM0 Capture",
  4675. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  4676. .platform_name = "msm-pcm-routing",
  4677. .codec_name = "msm-stub-codec.1",
  4678. .codec_dai_name = "msm-stub-tx",
  4679. .no_pcm = 1,
  4680. .dpcm_capture = 1,
  4681. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  4682. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4683. .ops = &bengal_tdm_be_ops,
  4684. .ignore_suspend = 1,
  4685. },
  4686. {
  4687. .name = LPASS_BE_TERT_TDM_RX_0,
  4688. .stream_name = "Tertiary TDM0 Playback",
  4689. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  4690. .platform_name = "msm-pcm-routing",
  4691. .codec_name = "msm-stub-codec.1",
  4692. .codec_dai_name = "msm-stub-rx",
  4693. .no_pcm = 1,
  4694. .dpcm_playback = 1,
  4695. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  4696. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4697. .ops = &bengal_tdm_be_ops,
  4698. .ignore_suspend = 1,
  4699. .ignore_pmdown_time = 1,
  4700. },
  4701. {
  4702. .name = LPASS_BE_TERT_TDM_TX_0,
  4703. .stream_name = "Tertiary TDM0 Capture",
  4704. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  4705. .platform_name = "msm-pcm-routing",
  4706. .codec_name = "msm-stub-codec.1",
  4707. .codec_dai_name = "msm-stub-tx",
  4708. .no_pcm = 1,
  4709. .dpcm_capture = 1,
  4710. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  4711. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4712. .ops = &bengal_tdm_be_ops,
  4713. .ignore_suspend = 1,
  4714. },
  4715. {
  4716. .name = LPASS_BE_QUAT_TDM_RX_0,
  4717. .stream_name = "Quaternary TDM0 Playback",
  4718. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  4719. .platform_name = "msm-pcm-routing",
  4720. .codec_name = "msm-stub-codec.1",
  4721. .codec_dai_name = "msm-stub-rx",
  4722. .no_pcm = 1,
  4723. .dpcm_playback = 1,
  4724. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  4725. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4726. .ops = &bengal_tdm_be_ops,
  4727. .ignore_suspend = 1,
  4728. .ignore_pmdown_time = 1,
  4729. },
  4730. {
  4731. .name = LPASS_BE_QUAT_TDM_TX_0,
  4732. .stream_name = "Quaternary TDM0 Capture",
  4733. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  4734. .platform_name = "msm-pcm-routing",
  4735. .codec_name = "msm-stub-codec.1",
  4736. .codec_dai_name = "msm-stub-tx",
  4737. .no_pcm = 1,
  4738. .dpcm_capture = 1,
  4739. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  4740. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4741. .ops = &bengal_tdm_be_ops,
  4742. .ignore_suspend = 1,
  4743. },
  4744. };
  4745. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  4746. {
  4747. .name = LPASS_BE_SLIMBUS_7_RX,
  4748. .stream_name = "Slimbus7 Playback",
  4749. .cpu_dai_name = "msm-dai-q6-dev.16398",
  4750. .platform_name = "msm-pcm-routing",
  4751. .codec_name = "btfmslim_slave",
  4752. /* BT codec driver determines capabilities based on
  4753. * dai name, bt codecdai name should always contains
  4754. * supported usecase information
  4755. */
  4756. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  4757. .no_pcm = 1,
  4758. .dpcm_playback = 1,
  4759. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  4760. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4761. .init = &msm_wcn_init,
  4762. .ops = &msm_wcn_ops,
  4763. /* dai link has playback support */
  4764. .ignore_pmdown_time = 1,
  4765. .ignore_suspend = 1,
  4766. },
  4767. {
  4768. .name = LPASS_BE_SLIMBUS_7_TX,
  4769. .stream_name = "Slimbus7 Capture",
  4770. .cpu_dai_name = "msm-dai-q6-dev.16399",
  4771. .platform_name = "msm-pcm-routing",
  4772. .codec_name = "btfmslim_slave",
  4773. .codec_dai_name = "btfm_bt_sco_slim_tx",
  4774. .no_pcm = 1,
  4775. .dpcm_capture = 1,
  4776. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  4777. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4778. .ops = &msm_wcn_ops,
  4779. .ignore_suspend = 1,
  4780. },
  4781. {
  4782. .name = LPASS_BE_SLIMBUS_8_TX,
  4783. .stream_name = "Slimbus8 Capture",
  4784. .cpu_dai_name = "msm-dai-q6-dev.16401",
  4785. .platform_name = "msm-pcm-routing",
  4786. .codec_name = "btfmslim_slave",
  4787. .codec_dai_name = "btfm_fm_slim_tx",
  4788. .no_pcm = 1,
  4789. .dpcm_capture = 1,
  4790. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  4791. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4792. .ops = &msm_wcn_ops,
  4793. .ignore_suspend = 1,
  4794. },
  4795. };
  4796. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  4797. {
  4798. .name = LPASS_BE_PRI_MI2S_RX,
  4799. .stream_name = "Primary MI2S Playback",
  4800. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4801. .platform_name = "msm-pcm-routing",
  4802. .codec_name = "msm-stub-codec.1",
  4803. .codec_dai_name = "msm-stub-rx",
  4804. .no_pcm = 1,
  4805. .dpcm_playback = 1,
  4806. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  4807. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4808. .ops = &msm_mi2s_be_ops,
  4809. .ignore_suspend = 1,
  4810. .ignore_pmdown_time = 1,
  4811. },
  4812. {
  4813. .name = LPASS_BE_PRI_MI2S_TX,
  4814. .stream_name = "Primary MI2S Capture",
  4815. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  4816. .platform_name = "msm-pcm-routing",
  4817. .codec_name = "msm-stub-codec.1",
  4818. .codec_dai_name = "msm-stub-tx",
  4819. .no_pcm = 1,
  4820. .dpcm_capture = 1,
  4821. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  4822. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4823. .ops = &msm_mi2s_be_ops,
  4824. .ignore_suspend = 1,
  4825. },
  4826. {
  4827. .name = LPASS_BE_SEC_MI2S_RX,
  4828. .stream_name = "Secondary MI2S Playback",
  4829. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4830. .platform_name = "msm-pcm-routing",
  4831. .codec_name = "msm-stub-codec.1",
  4832. .codec_dai_name = "msm-stub-rx",
  4833. .no_pcm = 1,
  4834. .dpcm_playback = 1,
  4835. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  4836. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4837. .ops = &msm_mi2s_be_ops,
  4838. .ignore_suspend = 1,
  4839. .ignore_pmdown_time = 1,
  4840. },
  4841. {
  4842. .name = LPASS_BE_SEC_MI2S_TX,
  4843. .stream_name = "Secondary MI2S Capture",
  4844. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  4845. .platform_name = "msm-pcm-routing",
  4846. .codec_name = "msm-stub-codec.1",
  4847. .codec_dai_name = "msm-stub-tx",
  4848. .no_pcm = 1,
  4849. .dpcm_capture = 1,
  4850. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  4851. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4852. .ops = &msm_mi2s_be_ops,
  4853. .ignore_suspend = 1,
  4854. },
  4855. {
  4856. .name = LPASS_BE_TERT_MI2S_RX,
  4857. .stream_name = "Tertiary MI2S Playback",
  4858. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4859. .platform_name = "msm-pcm-routing",
  4860. .codec_name = "msm-stub-codec.1",
  4861. .codec_dai_name = "msm-stub-rx",
  4862. .no_pcm = 1,
  4863. .dpcm_playback = 1,
  4864. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  4865. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4866. .ops = &msm_mi2s_be_ops,
  4867. .ignore_suspend = 1,
  4868. .ignore_pmdown_time = 1,
  4869. },
  4870. {
  4871. .name = LPASS_BE_TERT_MI2S_TX,
  4872. .stream_name = "Tertiary MI2S Capture",
  4873. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  4874. .platform_name = "msm-pcm-routing",
  4875. .codec_name = "msm-stub-codec.1",
  4876. .codec_dai_name = "msm-stub-tx",
  4877. .no_pcm = 1,
  4878. .dpcm_capture = 1,
  4879. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  4880. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4881. .ops = &msm_mi2s_be_ops,
  4882. .ignore_suspend = 1,
  4883. },
  4884. {
  4885. .name = LPASS_BE_QUAT_MI2S_RX,
  4886. .stream_name = "Quaternary MI2S Playback",
  4887. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  4888. .platform_name = "msm-pcm-routing",
  4889. .codec_name = "msm-stub-codec.1",
  4890. .codec_dai_name = "msm-stub-rx",
  4891. .no_pcm = 1,
  4892. .dpcm_playback = 1,
  4893. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  4894. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4895. .ops = &msm_mi2s_be_ops,
  4896. .ignore_suspend = 1,
  4897. .ignore_pmdown_time = 1,
  4898. },
  4899. {
  4900. .name = LPASS_BE_QUAT_MI2S_TX,
  4901. .stream_name = "Quaternary MI2S Capture",
  4902. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  4903. .platform_name = "msm-pcm-routing",
  4904. .codec_name = "msm-stub-codec.1",
  4905. .codec_dai_name = "msm-stub-tx",
  4906. .no_pcm = 1,
  4907. .dpcm_capture = 1,
  4908. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  4909. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4910. .ops = &msm_mi2s_be_ops,
  4911. .ignore_suspend = 1,
  4912. },
  4913. };
  4914. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  4915. /* Primary AUX PCM Backend DAI Links */
  4916. {
  4917. .name = LPASS_BE_AUXPCM_RX,
  4918. .stream_name = "AUX PCM Playback",
  4919. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4920. .platform_name = "msm-pcm-routing",
  4921. .codec_name = "msm-stub-codec.1",
  4922. .codec_dai_name = "msm-stub-rx",
  4923. .no_pcm = 1,
  4924. .dpcm_playback = 1,
  4925. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  4926. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4927. .ops = &bengal_aux_be_ops,
  4928. .ignore_pmdown_time = 1,
  4929. .ignore_suspend = 1,
  4930. },
  4931. {
  4932. .name = LPASS_BE_AUXPCM_TX,
  4933. .stream_name = "AUX PCM Capture",
  4934. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  4935. .platform_name = "msm-pcm-routing",
  4936. .codec_name = "msm-stub-codec.1",
  4937. .codec_dai_name = "msm-stub-tx",
  4938. .no_pcm = 1,
  4939. .dpcm_capture = 1,
  4940. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  4941. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4942. .ops = &bengal_aux_be_ops,
  4943. .ignore_suspend = 1,
  4944. },
  4945. /* Secondary AUX PCM Backend DAI Links */
  4946. {
  4947. .name = LPASS_BE_SEC_AUXPCM_RX,
  4948. .stream_name = "Sec AUX PCM Playback",
  4949. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4950. .platform_name = "msm-pcm-routing",
  4951. .codec_name = "msm-stub-codec.1",
  4952. .codec_dai_name = "msm-stub-rx",
  4953. .no_pcm = 1,
  4954. .dpcm_playback = 1,
  4955. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  4956. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4957. .ops = &bengal_aux_be_ops,
  4958. .ignore_pmdown_time = 1,
  4959. .ignore_suspend = 1,
  4960. },
  4961. {
  4962. .name = LPASS_BE_SEC_AUXPCM_TX,
  4963. .stream_name = "Sec AUX PCM Capture",
  4964. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  4965. .platform_name = "msm-pcm-routing",
  4966. .codec_name = "msm-stub-codec.1",
  4967. .codec_dai_name = "msm-stub-tx",
  4968. .no_pcm = 1,
  4969. .dpcm_capture = 1,
  4970. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  4971. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4972. .ops = &bengal_aux_be_ops,
  4973. .ignore_suspend = 1,
  4974. },
  4975. /* Tertiary AUX PCM Backend DAI Links */
  4976. {
  4977. .name = LPASS_BE_TERT_AUXPCM_RX,
  4978. .stream_name = "Tert AUX PCM Playback",
  4979. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4980. .platform_name = "msm-pcm-routing",
  4981. .codec_name = "msm-stub-codec.1",
  4982. .codec_dai_name = "msm-stub-rx",
  4983. .no_pcm = 1,
  4984. .dpcm_playback = 1,
  4985. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  4986. .be_hw_params_fixup = msm_be_hw_params_fixup,
  4987. .ops = &bengal_aux_be_ops,
  4988. .ignore_suspend = 1,
  4989. },
  4990. {
  4991. .name = LPASS_BE_TERT_AUXPCM_TX,
  4992. .stream_name = "Tert AUX PCM Capture",
  4993. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  4994. .platform_name = "msm-pcm-routing",
  4995. .codec_name = "msm-stub-codec.1",
  4996. .codec_dai_name = "msm-stub-tx",
  4997. .no_pcm = 1,
  4998. .dpcm_capture = 1,
  4999. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5000. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5001. .ops = &bengal_aux_be_ops,
  5002. .ignore_suspend = 1,
  5003. },
  5004. /* Quaternary AUX PCM Backend DAI Links */
  5005. {
  5006. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5007. .stream_name = "Quat AUX PCM Playback",
  5008. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5009. .platform_name = "msm-pcm-routing",
  5010. .codec_name = "msm-stub-codec.1",
  5011. .codec_dai_name = "msm-stub-rx",
  5012. .no_pcm = 1,
  5013. .dpcm_playback = 1,
  5014. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5015. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5016. .ops = &bengal_aux_be_ops,
  5017. .ignore_suspend = 1,
  5018. },
  5019. {
  5020. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5021. .stream_name = "Quat AUX PCM Capture",
  5022. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5023. .platform_name = "msm-pcm-routing",
  5024. .codec_name = "msm-stub-codec.1",
  5025. .codec_dai_name = "msm-stub-tx",
  5026. .no_pcm = 1,
  5027. .dpcm_capture = 1,
  5028. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5029. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5030. .ops = &bengal_aux_be_ops,
  5031. .ignore_suspend = 1,
  5032. },
  5033. };
  5034. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5035. /* RX CDC DMA Backend DAI Links */
  5036. {
  5037. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5038. .stream_name = "RX CDC DMA0 Playback",
  5039. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  5040. .platform_name = "msm-pcm-routing",
  5041. .codec_name = "bolero_codec",
  5042. .codec_dai_name = "rx_macro_rx1",
  5043. .dynamic_be = 1,
  5044. .no_pcm = 1,
  5045. .dpcm_playback = 1,
  5046. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5047. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5048. .ignore_pmdown_time = 1,
  5049. .ignore_suspend = 1,
  5050. .ops = &msm_cdc_dma_be_ops,
  5051. },
  5052. {
  5053. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5054. .stream_name = "RX CDC DMA1 Playback",
  5055. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  5056. .platform_name = "msm-pcm-routing",
  5057. .codec_name = "bolero_codec",
  5058. .codec_dai_name = "rx_macro_rx2",
  5059. .dynamic_be = 1,
  5060. .no_pcm = 1,
  5061. .dpcm_playback = 1,
  5062. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  5063. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5064. .ignore_pmdown_time = 1,
  5065. .ignore_suspend = 1,
  5066. .ops = &msm_cdc_dma_be_ops,
  5067. },
  5068. {
  5069. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  5070. .stream_name = "RX CDC DMA2 Playback",
  5071. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  5072. .platform_name = "msm-pcm-routing",
  5073. .codec_name = "bolero_codec",
  5074. .codec_dai_name = "rx_macro_rx3",
  5075. .dynamic_be = 1,
  5076. .no_pcm = 1,
  5077. .dpcm_playback = 1,
  5078. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  5079. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5080. .ignore_pmdown_time = 1,
  5081. .ignore_suspend = 1,
  5082. .ops = &msm_cdc_dma_be_ops,
  5083. },
  5084. {
  5085. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  5086. .stream_name = "RX CDC DMA3 Playback",
  5087. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  5088. .platform_name = "msm-pcm-routing",
  5089. .codec_name = "bolero_codec",
  5090. .codec_dai_name = "rx_macro_rx4",
  5091. .dynamic_be = 1,
  5092. .no_pcm = 1,
  5093. .dpcm_playback = 1,
  5094. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  5095. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5096. .ignore_pmdown_time = 1,
  5097. .ignore_suspend = 1,
  5098. .ops = &msm_cdc_dma_be_ops,
  5099. },
  5100. /* TX CDC DMA Backend DAI Links */
  5101. {
  5102. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  5103. .stream_name = "TX CDC DMA3 Capture",
  5104. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  5105. .platform_name = "msm-pcm-routing",
  5106. .codec_name = "bolero_codec",
  5107. .codec_dai_name = "tx_macro_tx1",
  5108. .no_pcm = 1,
  5109. .dpcm_capture = 1,
  5110. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  5111. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5112. .ignore_suspend = 1,
  5113. .ops = &msm_cdc_dma_be_ops,
  5114. },
  5115. {
  5116. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  5117. .stream_name = "TX CDC DMA4 Capture",
  5118. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  5119. .platform_name = "msm-pcm-routing",
  5120. .codec_name = "bolero_codec",
  5121. .codec_dai_name = "tx_macro_tx2",
  5122. .no_pcm = 1,
  5123. .dpcm_capture = 1,
  5124. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  5125. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5126. .ignore_suspend = 1,
  5127. .ops = &msm_cdc_dma_be_ops,
  5128. },
  5129. };
  5130. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  5131. {
  5132. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  5133. .stream_name = "VA CDC DMA0 Capture",
  5134. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  5135. .platform_name = "msm-pcm-routing",
  5136. .codec_name = "bolero_codec",
  5137. .codec_dai_name = "va_macro_tx1",
  5138. .no_pcm = 1,
  5139. .dpcm_capture = 1,
  5140. .init = &msm_int_audrx_init,
  5141. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  5142. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5143. .ignore_suspend = 1,
  5144. .ops = &msm_cdc_dma_be_ops,
  5145. },
  5146. {
  5147. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  5148. .stream_name = "VA CDC DMA1 Capture",
  5149. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  5150. .platform_name = "msm-pcm-routing",
  5151. .codec_name = "bolero_codec",
  5152. .codec_dai_name = "va_macro_tx2",
  5153. .no_pcm = 1,
  5154. .dpcm_capture = 1,
  5155. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  5156. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5157. .ignore_suspend = 1,
  5158. .ops = &msm_cdc_dma_be_ops,
  5159. },
  5160. {
  5161. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  5162. .stream_name = "VA CDC DMA2 Capture",
  5163. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  5164. .platform_name = "msm-pcm-routing",
  5165. .codec_name = "bolero_codec",
  5166. .codec_dai_name = "va_macro_tx3",
  5167. .no_pcm = 1,
  5168. .dpcm_capture = 1,
  5169. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  5170. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5171. .ignore_suspend = 1,
  5172. .ops = &msm_cdc_dma_be_ops,
  5173. },
  5174. };
  5175. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  5176. {
  5177. .name = LPASS_BE_AFE_LOOPBACK_TX,
  5178. .stream_name = "AFE Loopback Capture",
  5179. .cpu_dai_name = "msm-dai-q6-dev.24577",
  5180. .platform_name = "msm-pcm-routing",
  5181. .codec_name = "msm-stub-codec.1",
  5182. .codec_dai_name = "msm-stub-tx",
  5183. .no_pcm = 1,
  5184. .dpcm_capture = 1,
  5185. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  5186. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5187. .ignore_pmdown_time = 1,
  5188. .ignore_suspend = 1,
  5189. },
  5190. };
  5191. static struct snd_soc_dai_link msm_bengal_dai_links[
  5192. ARRAY_SIZE(msm_common_dai_links) +
  5193. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  5194. ARRAY_SIZE(msm_common_be_dai_links) +
  5195. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  5196. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  5197. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  5198. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  5199. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  5200. ARRAY_SIZE(msm_wcn_btfm_be_dai_links) +
  5201. ARRAY_SIZE(msm_tdm_be_dai_links)];
  5202. static int msm_populate_dai_link_component_of_node(
  5203. struct snd_soc_card *card)
  5204. {
  5205. int i, index, ret = 0;
  5206. struct device *cdev = card->dev;
  5207. struct snd_soc_dai_link *dai_link = card->dai_link;
  5208. struct device_node *np;
  5209. if (!cdev) {
  5210. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  5211. return -ENODEV;
  5212. }
  5213. for (i = 0; i < card->num_links; i++) {
  5214. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  5215. continue;
  5216. /* populate platform_of_node for snd card dai links */
  5217. if (dai_link[i].platform_name &&
  5218. !dai_link[i].platform_of_node) {
  5219. index = of_property_match_string(cdev->of_node,
  5220. "asoc-platform-names",
  5221. dai_link[i].platform_name);
  5222. if (index < 0) {
  5223. dev_err(cdev,
  5224. "%s: No match found for platform name: %s\n",
  5225. __func__, dai_link[i].platform_name);
  5226. ret = index;
  5227. goto err;
  5228. }
  5229. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  5230. index);
  5231. if (!np) {
  5232. dev_err(cdev,
  5233. "%s: retrieving phandle for platform %s, index %d failed\n",
  5234. __func__, dai_link[i].platform_name,
  5235. index);
  5236. ret = -ENODEV;
  5237. goto err;
  5238. }
  5239. dai_link[i].platform_of_node = np;
  5240. dai_link[i].platform_name = NULL;
  5241. }
  5242. /* populate cpu_of_node for snd card dai links */
  5243. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  5244. index = of_property_match_string(cdev->of_node,
  5245. "asoc-cpu-names",
  5246. dai_link[i].cpu_dai_name);
  5247. if (index >= 0) {
  5248. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  5249. index);
  5250. if (!np) {
  5251. dev_err(cdev,
  5252. "%s: retrieving phandle for cpu dai %s failed\n",
  5253. __func__,
  5254. dai_link[i].cpu_dai_name);
  5255. ret = -ENODEV;
  5256. goto err;
  5257. }
  5258. dai_link[i].cpu_of_node = np;
  5259. dai_link[i].cpu_dai_name = NULL;
  5260. }
  5261. }
  5262. /* populate codec_of_node for snd card dai links */
  5263. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  5264. index = of_property_match_string(cdev->of_node,
  5265. "asoc-codec-names",
  5266. dai_link[i].codec_name);
  5267. if (index < 0)
  5268. continue;
  5269. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  5270. index);
  5271. if (!np) {
  5272. dev_err(cdev,
  5273. "%s: retrieving phandle for codec %s failed\n",
  5274. __func__, dai_link[i].codec_name);
  5275. ret = -ENODEV;
  5276. goto err;
  5277. }
  5278. dai_link[i].codec_of_node = np;
  5279. dai_link[i].codec_name = NULL;
  5280. }
  5281. }
  5282. err:
  5283. return ret;
  5284. }
  5285. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  5286. {
  5287. int ret = -EINVAL;
  5288. struct snd_soc_component *component =
  5289. snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  5290. if (!component) {
  5291. pr_err("* %s: No match for msm-stub-codec component\n",
  5292. __func__);
  5293. return ret;
  5294. }
  5295. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  5296. ARRAY_SIZE(msm_snd_controls));
  5297. if (ret < 0) {
  5298. dev_err(component->dev,
  5299. "%s: add_codec_controls failed, err = %d\n",
  5300. __func__, ret);
  5301. return ret;
  5302. }
  5303. return ret;
  5304. }
  5305. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  5306. struct snd_pcm_hw_params *params)
  5307. {
  5308. return 0;
  5309. }
  5310. static struct snd_soc_ops msm_stub_be_ops = {
  5311. .hw_params = msm_snd_stub_hw_params,
  5312. };
  5313. struct snd_soc_card snd_soc_card_stub_msm = {
  5314. .name = "bengal-stub-snd-card",
  5315. };
  5316. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  5317. /* FrontEnd DAI Links */
  5318. {
  5319. .name = "MSMSTUB Media1",
  5320. .stream_name = "MultiMedia1",
  5321. .cpu_dai_name = "MultiMedia1",
  5322. .platform_name = "msm-pcm-dsp.0",
  5323. .dynamic = 1,
  5324. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  5325. .dpcm_playback = 1,
  5326. .dpcm_capture = 1,
  5327. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5328. SND_SOC_DPCM_TRIGGER_POST},
  5329. .codec_dai_name = "snd-soc-dummy-dai",
  5330. .codec_name = "snd-soc-dummy",
  5331. .ignore_suspend = 1,
  5332. /* this dainlink has playback support */
  5333. .ignore_pmdown_time = 1,
  5334. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  5335. },
  5336. };
  5337. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  5338. /* Backend DAI Links */
  5339. {
  5340. .name = LPASS_BE_AUXPCM_RX,
  5341. .stream_name = "AUX PCM Playback",
  5342. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5343. .platform_name = "msm-pcm-routing",
  5344. .codec_name = "msm-stub-codec.1",
  5345. .codec_dai_name = "msm-stub-rx",
  5346. .no_pcm = 1,
  5347. .dpcm_playback = 1,
  5348. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5349. .init = &msm_audrx_stub_init,
  5350. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5351. .ignore_pmdown_time = 1,
  5352. .ignore_suspend = 1,
  5353. .ops = &msm_stub_be_ops,
  5354. },
  5355. {
  5356. .name = LPASS_BE_AUXPCM_TX,
  5357. .stream_name = "AUX PCM Capture",
  5358. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5359. .platform_name = "msm-pcm-routing",
  5360. .codec_name = "msm-stub-codec.1",
  5361. .codec_dai_name = "msm-stub-tx",
  5362. .no_pcm = 1,
  5363. .dpcm_capture = 1,
  5364. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5365. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5366. .ignore_suspend = 1,
  5367. .ops = &msm_stub_be_ops,
  5368. },
  5369. };
  5370. static struct snd_soc_dai_link msm_stub_dai_links[
  5371. ARRAY_SIZE(msm_stub_fe_dai_links) +
  5372. ARRAY_SIZE(msm_stub_be_dai_links)];
  5373. static const struct of_device_id bengal_asoc_machine_of_match[] = {
  5374. { .compatible = "qcom,bengal-asoc-snd",
  5375. .data = "codec"},
  5376. { .compatible = "qcom,bengal-asoc-snd-stub",
  5377. .data = "stub_codec"},
  5378. {},
  5379. };
  5380. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  5381. {
  5382. struct snd_soc_card *card = NULL;
  5383. struct snd_soc_dai_link *dailink = NULL;
  5384. int len_1 = 0;
  5385. int len_2 = 0;
  5386. int total_links = 0;
  5387. int rc = 0;
  5388. u32 mi2s_audio_intf = 0;
  5389. u32 auxpcm_audio_intf = 0;
  5390. u32 rxtx_bolero_codec = 0;
  5391. u32 va_bolero_codec = 0;
  5392. u32 val = 0;
  5393. u32 wcn_btfm_intf = 0;
  5394. const struct of_device_id *match;
  5395. match = of_match_node(bengal_asoc_machine_of_match, dev->of_node);
  5396. if (!match) {
  5397. dev_err(dev, "%s: No DT match found for sound card\n",
  5398. __func__);
  5399. return NULL;
  5400. }
  5401. if (!strcmp(match->data, "codec")) {
  5402. card = &snd_soc_card_bengal_msm;
  5403. memcpy(msm_bengal_dai_links + total_links,
  5404. msm_common_dai_links,
  5405. sizeof(msm_common_dai_links));
  5406. total_links += ARRAY_SIZE(msm_common_dai_links);
  5407. memcpy(msm_bengal_dai_links + total_links,
  5408. msm_common_misc_fe_dai_links,
  5409. sizeof(msm_common_misc_fe_dai_links));
  5410. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  5411. memcpy(msm_bengal_dai_links + total_links,
  5412. msm_common_be_dai_links,
  5413. sizeof(msm_common_be_dai_links));
  5414. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  5415. rc = of_property_read_u32(dev->of_node,
  5416. "qcom,rxtx-bolero-codec",
  5417. &rxtx_bolero_codec);
  5418. if (rc) {
  5419. dev_dbg(dev, "%s: No DT match RXTX Macro codec\n",
  5420. __func__);
  5421. } else {
  5422. if (rxtx_bolero_codec) {
  5423. memcpy(msm_bengal_dai_links + total_links,
  5424. msm_rx_tx_cdc_dma_be_dai_links,
  5425. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  5426. total_links +=
  5427. ARRAY_SIZE(
  5428. msm_rx_tx_cdc_dma_be_dai_links);
  5429. }
  5430. }
  5431. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  5432. &va_bolero_codec);
  5433. if (rc) {
  5434. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  5435. __func__);
  5436. } else {
  5437. if (va_bolero_codec) {
  5438. memcpy(msm_bengal_dai_links + total_links,
  5439. msm_va_cdc_dma_be_dai_links,
  5440. sizeof(msm_va_cdc_dma_be_dai_links));
  5441. total_links +=
  5442. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  5443. }
  5444. }
  5445. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  5446. &mi2s_audio_intf);
  5447. if (rc) {
  5448. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  5449. __func__);
  5450. } else {
  5451. if (mi2s_audio_intf) {
  5452. memcpy(msm_bengal_dai_links + total_links,
  5453. msm_mi2s_be_dai_links,
  5454. sizeof(msm_mi2s_be_dai_links));
  5455. total_links +=
  5456. ARRAY_SIZE(msm_mi2s_be_dai_links);
  5457. }
  5458. }
  5459. rc = of_property_read_u32(dev->of_node,
  5460. "qcom,auxpcm-audio-intf",
  5461. &auxpcm_audio_intf);
  5462. if (rc) {
  5463. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  5464. __func__);
  5465. } else {
  5466. if (auxpcm_audio_intf) {
  5467. memcpy(msm_bengal_dai_links + total_links,
  5468. msm_auxpcm_be_dai_links,
  5469. sizeof(msm_auxpcm_be_dai_links));
  5470. total_links +=
  5471. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  5472. }
  5473. }
  5474. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  5475. &val);
  5476. if (!rc && val) {
  5477. memcpy(msm_bengal_dai_links + total_links,
  5478. msm_afe_rxtx_lb_be_dai_link,
  5479. sizeof(msm_afe_rxtx_lb_be_dai_link));
  5480. total_links +=
  5481. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  5482. }
  5483. rc = of_property_read_u32(dev->of_node, "qcom,tdm-audio-intf",
  5484. &val);
  5485. if (!rc && val) {
  5486. memcpy(msm_bengal_dai_links + total_links,
  5487. msm_tdm_be_dai_links,
  5488. sizeof(msm_tdm_be_dai_links));
  5489. total_links +=
  5490. ARRAY_SIZE(msm_tdm_be_dai_links);
  5491. }
  5492. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  5493. &wcn_btfm_intf);
  5494. if (rc) {
  5495. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  5496. __func__);
  5497. } else {
  5498. if (wcn_btfm_intf) {
  5499. memcpy(msm_bengal_dai_links + total_links,
  5500. msm_wcn_btfm_be_dai_links,
  5501. sizeof(msm_wcn_btfm_be_dai_links));
  5502. total_links +=
  5503. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  5504. }
  5505. }
  5506. dailink = msm_bengal_dai_links;
  5507. } else if (!strcmp(match->data, "stub_codec")) {
  5508. card = &snd_soc_card_stub_msm;
  5509. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  5510. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  5511. memcpy(msm_stub_dai_links,
  5512. msm_stub_fe_dai_links,
  5513. sizeof(msm_stub_fe_dai_links));
  5514. memcpy(msm_stub_dai_links + len_1,
  5515. msm_stub_be_dai_links,
  5516. sizeof(msm_stub_be_dai_links));
  5517. dailink = msm_stub_dai_links;
  5518. total_links = len_2;
  5519. }
  5520. if (card) {
  5521. card->dai_link = dailink;
  5522. card->num_links = total_links;
  5523. }
  5524. return card;
  5525. }
  5526. static int msm_aux_codec_init(struct snd_soc_component *component)
  5527. {
  5528. struct snd_soc_dapm_context *dapm =
  5529. snd_soc_component_get_dapm(component);
  5530. int ret = 0;
  5531. void *mbhc_calibration;
  5532. struct snd_info_entry *entry;
  5533. struct snd_card *card = component->card->snd_card;
  5534. struct msm_asoc_mach_data *pdata;
  5535. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  5536. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  5537. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  5538. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  5539. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  5540. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  5541. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  5542. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  5543. snd_soc_dapm_sync(dapm);
  5544. pdata = snd_soc_card_get_drvdata(component->card);
  5545. if (!pdata->codec_root) {
  5546. entry = snd_info_create_subdir(card->module, "codecs",
  5547. card->proc_root);
  5548. if (!entry) {
  5549. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5550. __func__);
  5551. ret = 0;
  5552. goto mbhc_cfg_cal;
  5553. }
  5554. pdata->codec_root = entry;
  5555. }
  5556. wcd937x_info_create_codec_entry(pdata->codec_root, component);
  5557. mbhc_cfg_cal:
  5558. mbhc_calibration = def_wcd_mbhc_cal();
  5559. if (!mbhc_calibration)
  5560. return -ENOMEM;
  5561. wcd_mbhc_cfg.calibration = mbhc_calibration;
  5562. ret = wcd937x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  5563. if (ret) {
  5564. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  5565. __func__, ret);
  5566. goto err_hs_detect;
  5567. }
  5568. return 0;
  5569. err_hs_detect:
  5570. kfree(mbhc_calibration);
  5571. return ret;
  5572. }
  5573. static int msm_init_aux_dev(struct platform_device *pdev,
  5574. struct snd_soc_card *card)
  5575. {
  5576. struct device_node *wsa_of_node;
  5577. struct device_node *aux_codec_of_node;
  5578. u32 wsa_max_devs;
  5579. u32 wsa_dev_cnt;
  5580. u32 codec_max_aux_devs = 0;
  5581. u32 codec_aux_dev_cnt = 0;
  5582. int i;
  5583. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  5584. struct aux_codec_dev_info *aux_cdc_dev_info;
  5585. const char *auxdev_name_prefix[1];
  5586. char *dev_name_str = NULL;
  5587. int found = 0;
  5588. int codecs_found = 0;
  5589. int ret = 0;
  5590. /* Get maximum WSA device count for this platform */
  5591. ret = of_property_read_u32(pdev->dev.of_node,
  5592. "qcom,wsa-max-devs", &wsa_max_devs);
  5593. if (ret) {
  5594. dev_info(&pdev->dev,
  5595. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  5596. __func__, pdev->dev.of_node->full_name, ret);
  5597. wsa_max_devs = 0;
  5598. goto codec_aux_dev;
  5599. }
  5600. if (wsa_max_devs == 0) {
  5601. dev_warn(&pdev->dev,
  5602. "%s: Max WSA devices is 0 for this target?\n",
  5603. __func__);
  5604. goto codec_aux_dev;
  5605. }
  5606. /* Get count of WSA device phandles for this platform */
  5607. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  5608. "qcom,wsa-devs", NULL);
  5609. if (wsa_dev_cnt == -ENOENT) {
  5610. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  5611. __func__);
  5612. goto err;
  5613. } else if (wsa_dev_cnt <= 0) {
  5614. dev_err(&pdev->dev,
  5615. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  5616. __func__, wsa_dev_cnt);
  5617. ret = -EINVAL;
  5618. goto err;
  5619. }
  5620. /*
  5621. * Expect total phandles count to be NOT less than maximum possible
  5622. * WSA count. However, if it is less, then assign same value to
  5623. * max count as well.
  5624. */
  5625. if (wsa_dev_cnt < wsa_max_devs) {
  5626. dev_dbg(&pdev->dev,
  5627. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  5628. __func__, wsa_max_devs, wsa_dev_cnt);
  5629. wsa_max_devs = wsa_dev_cnt;
  5630. }
  5631. /* Make sure prefix string passed for each WSA device */
  5632. ret = of_property_count_strings(pdev->dev.of_node,
  5633. "qcom,wsa-aux-dev-prefix");
  5634. if (ret != wsa_dev_cnt) {
  5635. dev_err(&pdev->dev,
  5636. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  5637. __func__, wsa_dev_cnt, ret);
  5638. ret = -EINVAL;
  5639. goto err;
  5640. }
  5641. /*
  5642. * Alloc mem to store phandle and index info of WSA device, if already
  5643. * registered with ALSA core
  5644. */
  5645. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  5646. sizeof(struct msm_wsa881x_dev_info),
  5647. GFP_KERNEL);
  5648. if (!wsa881x_dev_info) {
  5649. ret = -ENOMEM;
  5650. goto err;
  5651. }
  5652. /*
  5653. * search and check whether all WSA devices are already
  5654. * registered with ALSA core or not. If found a node, store
  5655. * the node and the index in a local array of struct for later
  5656. * use.
  5657. */
  5658. for (i = 0; i < wsa_dev_cnt; i++) {
  5659. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  5660. "qcom,wsa-devs", i);
  5661. if (unlikely(!wsa_of_node)) {
  5662. /* we should not be here */
  5663. dev_err(&pdev->dev,
  5664. "%s: wsa dev node is not present\n",
  5665. __func__);
  5666. ret = -EINVAL;
  5667. goto err;
  5668. }
  5669. if (soc_find_component(wsa_of_node, NULL)) {
  5670. /* WSA device registered with ALSA core */
  5671. wsa881x_dev_info[found].of_node = wsa_of_node;
  5672. wsa881x_dev_info[found].index = i;
  5673. found++;
  5674. if (found == wsa_max_devs)
  5675. break;
  5676. }
  5677. }
  5678. if (found < wsa_max_devs) {
  5679. dev_dbg(&pdev->dev,
  5680. "%s: failed to find %d components. Found only %d\n",
  5681. __func__, wsa_max_devs, found);
  5682. return -EPROBE_DEFER;
  5683. }
  5684. dev_info(&pdev->dev,
  5685. "%s: found %d wsa881x devices registered with ALSA core\n",
  5686. __func__, found);
  5687. codec_aux_dev:
  5688. /* Get maximum aux codec device count for this platform */
  5689. ret = of_property_read_u32(pdev->dev.of_node,
  5690. "qcom,codec-max-aux-devs",
  5691. &codec_max_aux_devs);
  5692. if (ret) {
  5693. dev_err(&pdev->dev,
  5694. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  5695. __func__, pdev->dev.of_node->full_name, ret);
  5696. codec_max_aux_devs = 0;
  5697. goto aux_dev_register;
  5698. }
  5699. if (codec_max_aux_devs == 0) {
  5700. dev_dbg(&pdev->dev,
  5701. "%s: Max aux codec devices is 0 for this target?\n",
  5702. __func__);
  5703. goto aux_dev_register;
  5704. }
  5705. /* Get count of aux codec device phandles for this platform */
  5706. codec_aux_dev_cnt = of_count_phandle_with_args(
  5707. pdev->dev.of_node,
  5708. "qcom,codec-aux-devs", NULL);
  5709. if (codec_aux_dev_cnt == -ENOENT) {
  5710. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  5711. __func__);
  5712. goto err;
  5713. } else if (codec_aux_dev_cnt <= 0) {
  5714. dev_err(&pdev->dev,
  5715. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  5716. __func__, codec_aux_dev_cnt);
  5717. ret = -EINVAL;
  5718. goto err;
  5719. }
  5720. /*
  5721. * Expect total phandles count to be NOT less than maximum possible
  5722. * AUX device count. However, if it is less, then assign same value to
  5723. * max count as well.
  5724. */
  5725. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  5726. dev_dbg(&pdev->dev,
  5727. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  5728. __func__, codec_max_aux_devs,
  5729. codec_aux_dev_cnt);
  5730. codec_max_aux_devs = codec_aux_dev_cnt;
  5731. }
  5732. /*
  5733. * Alloc mem to store phandle and index info of aux codec
  5734. * if already registered with ALSA core
  5735. */
  5736. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  5737. sizeof(struct aux_codec_dev_info),
  5738. GFP_KERNEL);
  5739. if (!aux_cdc_dev_info) {
  5740. ret = -ENOMEM;
  5741. goto err;
  5742. }
  5743. /*
  5744. * search and check whether all aux codecs are already
  5745. * registered with ALSA core or not. If found a node, store
  5746. * the node and the index in a local array of struct for later
  5747. * use.
  5748. */
  5749. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5750. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  5751. "qcom,codec-aux-devs", i);
  5752. if (unlikely(!aux_codec_of_node)) {
  5753. /* we should not be here */
  5754. dev_err(&pdev->dev,
  5755. "%s: aux codec dev node is not present\n",
  5756. __func__);
  5757. ret = -EINVAL;
  5758. goto err;
  5759. }
  5760. if (soc_find_component(aux_codec_of_node, NULL)) {
  5761. /* AUX codec registered with ALSA core */
  5762. aux_cdc_dev_info[codecs_found].of_node =
  5763. aux_codec_of_node;
  5764. aux_cdc_dev_info[codecs_found].index = i;
  5765. codecs_found++;
  5766. }
  5767. }
  5768. if (codecs_found < codec_aux_dev_cnt) {
  5769. dev_dbg(&pdev->dev,
  5770. "%s: failed to find %d components. Found only %d\n",
  5771. __func__, codec_aux_dev_cnt, codecs_found);
  5772. return -EPROBE_DEFER;
  5773. }
  5774. dev_info(&pdev->dev,
  5775. "%s: found %d AUX codecs registered with ALSA core\n",
  5776. __func__, codecs_found);
  5777. aux_dev_register:
  5778. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  5779. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  5780. /* Alloc array of AUX devs struct */
  5781. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  5782. sizeof(struct snd_soc_aux_dev),
  5783. GFP_KERNEL);
  5784. if (!msm_aux_dev) {
  5785. ret = -ENOMEM;
  5786. goto err;
  5787. }
  5788. /* Alloc array of codec conf struct */
  5789. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  5790. sizeof(struct snd_soc_codec_conf),
  5791. GFP_KERNEL);
  5792. if (!msm_codec_conf) {
  5793. ret = -ENOMEM;
  5794. goto err;
  5795. }
  5796. for (i = 0; i < wsa_max_devs; i++) {
  5797. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  5798. GFP_KERNEL);
  5799. if (!dev_name_str) {
  5800. ret = -ENOMEM;
  5801. goto err;
  5802. }
  5803. ret = of_property_read_string_index(pdev->dev.of_node,
  5804. "qcom,wsa-aux-dev-prefix",
  5805. wsa881x_dev_info[i].index,
  5806. auxdev_name_prefix);
  5807. if (ret) {
  5808. dev_err(&pdev->dev,
  5809. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  5810. __func__, ret);
  5811. ret = -EINVAL;
  5812. goto err;
  5813. }
  5814. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  5815. msm_aux_dev[i].name = dev_name_str;
  5816. msm_aux_dev[i].codec_name = NULL;
  5817. msm_aux_dev[i].codec_of_node =
  5818. wsa881x_dev_info[i].of_node;
  5819. msm_aux_dev[i].init = NULL;
  5820. msm_codec_conf[i].dev_name = NULL;
  5821. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  5822. msm_codec_conf[i].of_node =
  5823. wsa881x_dev_info[i].of_node;
  5824. }
  5825. for (i = 0; i < codec_aux_dev_cnt; i++) {
  5826. msm_aux_dev[wsa_max_devs + i].name = NULL;
  5827. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  5828. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  5829. aux_cdc_dev_info[i].of_node;
  5830. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  5831. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  5832. msm_codec_conf[wsa_max_devs + i].name_prefix =
  5833. NULL;
  5834. msm_codec_conf[wsa_max_devs + i].of_node =
  5835. aux_cdc_dev_info[i].of_node;
  5836. }
  5837. card->codec_conf = msm_codec_conf;
  5838. card->aux_dev = msm_aux_dev;
  5839. err:
  5840. return ret;
  5841. }
  5842. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  5843. {
  5844. int count = 0;
  5845. u32 mi2s_master_slave[MI2S_MAX];
  5846. int ret = 0;
  5847. for (count = 0; count < MI2S_MAX; count++) {
  5848. mutex_init(&mi2s_intf_conf[count].lock);
  5849. mi2s_intf_conf[count].ref_cnt = 0;
  5850. }
  5851. ret = of_property_read_u32_array(pdev->dev.of_node,
  5852. "qcom,msm-mi2s-master",
  5853. mi2s_master_slave, MI2S_MAX);
  5854. if (ret) {
  5855. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  5856. __func__);
  5857. } else {
  5858. for (count = 0; count < MI2S_MAX; count++) {
  5859. mi2s_intf_conf[count].msm_is_mi2s_master =
  5860. mi2s_master_slave[count];
  5861. }
  5862. }
  5863. }
  5864. static void msm_i2s_auxpcm_deinit(void)
  5865. {
  5866. int count = 0;
  5867. for (count = 0; count < MI2S_MAX; count++) {
  5868. mutex_destroy(&mi2s_intf_conf[count].lock);
  5869. mi2s_intf_conf[count].ref_cnt = 0;
  5870. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  5871. }
  5872. }
  5873. static int bengal_ssr_enable(struct device *dev, void *data)
  5874. {
  5875. struct platform_device *pdev = to_platform_device(dev);
  5876. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5877. int ret = 0;
  5878. if (!card) {
  5879. dev_err(dev, "%s: card is NULL\n", __func__);
  5880. ret = -EINVAL;
  5881. goto err;
  5882. }
  5883. if (!strcmp(card->name, "bengal-stub-snd-card")) {
  5884. /* TODO */
  5885. dev_dbg(dev, "%s: TODO\n", __func__);
  5886. }
  5887. snd_soc_card_change_online_state(card, 1);
  5888. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  5889. err:
  5890. return ret;
  5891. }
  5892. static void bengal_ssr_disable(struct device *dev, void *data)
  5893. {
  5894. struct platform_device *pdev = to_platform_device(dev);
  5895. struct snd_soc_card *card = platform_get_drvdata(pdev);
  5896. if (!card) {
  5897. dev_err(dev, "%s: card is NULL\n", __func__);
  5898. return;
  5899. }
  5900. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  5901. snd_soc_card_change_online_state(card, 0);
  5902. if (!strcmp(card->name, "bengal-stub-snd-card")) {
  5903. /* TODO */
  5904. dev_dbg(dev, "%s: TODO\n", __func__);
  5905. }
  5906. }
  5907. static const struct snd_event_ops bengal_ssr_ops = {
  5908. .enable = bengal_ssr_enable,
  5909. .disable = bengal_ssr_disable,
  5910. };
  5911. static int msm_audio_ssr_compare(struct device *dev, void *data)
  5912. {
  5913. struct device_node *node = data;
  5914. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  5915. __func__, dev->of_node, node);
  5916. return (dev->of_node && dev->of_node == node);
  5917. }
  5918. static int msm_audio_ssr_register(struct device *dev)
  5919. {
  5920. struct device_node *np = dev->of_node;
  5921. struct snd_event_clients *ssr_clients = NULL;
  5922. struct device_node *node = NULL;
  5923. int ret = 0;
  5924. int i = 0;
  5925. for (i = 0; ; i++) {
  5926. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  5927. if (!node)
  5928. break;
  5929. snd_event_mstr_add_client(&ssr_clients,
  5930. msm_audio_ssr_compare, node);
  5931. }
  5932. ret = snd_event_master_register(dev, &bengal_ssr_ops,
  5933. ssr_clients, NULL);
  5934. if (!ret)
  5935. snd_event_notify(dev, SND_EVENT_UP);
  5936. return ret;
  5937. }
  5938. static int msm_asoc_machine_probe(struct platform_device *pdev)
  5939. {
  5940. struct snd_soc_card *card = NULL;
  5941. struct msm_asoc_mach_data *pdata = NULL;
  5942. const char *mbhc_audio_jack_type = NULL;
  5943. int ret = 0;
  5944. uint index = 0;
  5945. struct nvmem_cell *cell;
  5946. size_t len;
  5947. u32 *buf;
  5948. u32 adsp_var_idx = 0;
  5949. if (!pdev->dev.of_node) {
  5950. dev_err(&pdev->dev,
  5951. "%s: No platform supplied from device tree\n",
  5952. __func__);
  5953. return -EINVAL;
  5954. }
  5955. pdata = devm_kzalloc(&pdev->dev,
  5956. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  5957. if (!pdata)
  5958. return -ENOMEM;
  5959. card = populate_snd_card_dailinks(&pdev->dev);
  5960. if (!card) {
  5961. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  5962. ret = -EINVAL;
  5963. goto err;
  5964. }
  5965. card->dev = &pdev->dev;
  5966. platform_set_drvdata(pdev, card);
  5967. snd_soc_card_set_drvdata(card, pdata);
  5968. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  5969. if (ret) {
  5970. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  5971. __func__, ret);
  5972. goto err;
  5973. }
  5974. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  5975. if (ret) {
  5976. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  5977. __func__, ret);
  5978. goto err;
  5979. }
  5980. ret = msm_populate_dai_link_component_of_node(card);
  5981. if (ret) {
  5982. ret = -EPROBE_DEFER;
  5983. goto err;
  5984. }
  5985. ret = msm_init_aux_dev(pdev, card);
  5986. if (ret)
  5987. goto err;
  5988. ret = devm_snd_soc_register_card(&pdev->dev, card);
  5989. if (ret == -EPROBE_DEFER) {
  5990. if (codec_reg_done)
  5991. ret = -EINVAL;
  5992. goto err;
  5993. } else if (ret) {
  5994. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  5995. __func__, ret);
  5996. goto err;
  5997. }
  5998. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  5999. __func__, card->name);
  6000. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6001. "qcom,hph-en1-gpio", 0);
  6002. if (!pdata->hph_en1_gpio_p) {
  6003. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6004. __func__, "qcom,hph-en1-gpio",
  6005. pdev->dev.of_node->full_name);
  6006. }
  6007. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6008. "qcom,hph-en0-gpio", 0);
  6009. if (!pdata->hph_en0_gpio_p) {
  6010. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6011. __func__, "qcom,hph-en0-gpio",
  6012. pdev->dev.of_node->full_name);
  6013. }
  6014. ret = of_property_read_string(pdev->dev.of_node,
  6015. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  6016. if (ret) {
  6017. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  6018. __func__, "qcom,mbhc-audio-jack-type",
  6019. pdev->dev.of_node->full_name);
  6020. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  6021. } else {
  6022. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  6023. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6024. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  6025. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  6026. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6027. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  6028. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  6029. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6030. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  6031. } else {
  6032. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6033. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  6034. }
  6035. }
  6036. /*
  6037. * Parse US-Euro gpio info from DT. Report no error if us-euro
  6038. * entry is not found in DT file as some targets do not support
  6039. * US-Euro detection
  6040. */
  6041. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6042. "qcom,us-euro-gpios", 0);
  6043. if (!pdata->us_euro_gpio_p) {
  6044. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  6045. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  6046. } else {
  6047. dev_dbg(&pdev->dev, "%s detected\n",
  6048. "qcom,us-euro-gpios");
  6049. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  6050. }
  6051. if (wcd_mbhc_cfg.enable_usbc_analog)
  6052. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  6053. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  6054. "fsa4480-i2c-handle", 0);
  6055. if (!pdata->fsa_handle)
  6056. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  6057. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  6058. msm_i2s_auxpcm_init(pdev);
  6059. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6060. "qcom,cdc-dmic01-gpios",
  6061. 0);
  6062. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6063. "qcom,cdc-dmic23-gpios",
  6064. 0);
  6065. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6066. "qcom,pri-mi2s-gpios", 0);
  6067. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6068. "qcom,sec-mi2s-gpios", 0);
  6069. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6070. "qcom,tert-mi2s-gpios", 0);
  6071. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  6072. "qcom,quat-mi2s-gpios", 0);
  6073. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  6074. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  6075. ret = msm_audio_ssr_register(&pdev->dev);
  6076. if (ret)
  6077. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  6078. __func__, ret);
  6079. is_initial_boot = true;
  6080. /* get adsp variant idx */
  6081. cell = nvmem_cell_get(&pdev->dev, "adsp_variant");
  6082. if (IS_ERR_OR_NULL(cell)) {
  6083. dev_dbg(&pdev->dev, "%s: FAILED to get nvmem cell \n", __func__);
  6084. goto ret;
  6085. }
  6086. buf = nvmem_cell_read(cell, &len);
  6087. nvmem_cell_put(cell);
  6088. if (IS_ERR_OR_NULL(buf) || len <= 0 || len > sizeof(32)) {
  6089. dev_dbg(&pdev->dev, "%s: FAILED to read nvmem cell \n", __func__);
  6090. goto ret;
  6091. }
  6092. memcpy(&adsp_var_idx, buf, len);
  6093. kfree(buf);
  6094. va_disable = adsp_var_idx;
  6095. ret:
  6096. return 0;
  6097. err:
  6098. devm_kfree(&pdev->dev, pdata);
  6099. return ret;
  6100. }
  6101. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6102. {
  6103. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6104. snd_event_master_deregister(&pdev->dev);
  6105. snd_soc_unregister_card(card);
  6106. msm_i2s_auxpcm_deinit();
  6107. return 0;
  6108. }
  6109. static struct platform_driver bengal_asoc_machine_driver = {
  6110. .driver = {
  6111. .name = DRV_NAME,
  6112. .owner = THIS_MODULE,
  6113. .pm = &snd_soc_pm_ops,
  6114. .of_match_table = bengal_asoc_machine_of_match,
  6115. .suppress_bind_attrs = true,
  6116. },
  6117. .probe = msm_asoc_machine_probe,
  6118. .remove = msm_asoc_machine_remove,
  6119. };
  6120. module_platform_driver(bengal_asoc_machine_driver);
  6121. MODULE_DESCRIPTION("ALSA SoC msm");
  6122. MODULE_LICENSE("GPL v2");
  6123. MODULE_ALIAS("platform:" DRV_NAME);
  6124. MODULE_DEVICE_TABLE(of, bengal_asoc_machine_of_match);