46e9caf0d0
git-subtree-dir: qcom/opensource/mm-sys-kernel git-subtree-mainline:99d06628dbgit-subtree-split:88eb9646a4Change-Id: repo: https://git.codelinaro.org/clo/la/platform/vendor/opensource/mm-sys-kernel tag: LA.VENDOR.14.3.0.r1-17300-lanai.QSSI15.0
74 lines
2.4 KiB
C
74 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __UBWCP_HW_H_
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#define __UBWCP_HW_H_
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#define HW_BUFFER_FORMAT_RGBA 0x0
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#define HW_BUFFER_FORMAT_NV12 0x2
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#define HW_BUFFER_FORMAT_NV124R 0x4
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#define HW_BUFFER_FORMAT_P010 0x6
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#define HW_BUFFER_FORMAT_TP10 0x8
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#define HW_BUFFER_FORMAT_P016 0xA
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#define HW_BUFFER_FORMAT_LINEAR 0xF
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/* interrupt id. also bit location for set/clear */
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#define INTERRUPT_READ_ERROR 0
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#define INTERRUPT_WRITE_ERROR 1
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#define INTERRUPT_DECODE_ERROR 2
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#define INTERRUPT_ENCODE_ERROR 3
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/**
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* struct msm_ubwcp_- UBWCP hardware instance
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* dev:UBWCP device
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* irq:Interrupt number
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* clk:The bus clock for this IOMMU hardware instance
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* pclk:The clock for the IOMMU IOMMU bus interconnect
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*/
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struct ubwcp_dev {
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void __iomem *base;
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struct device *dev;
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int irq;
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struct clk *clk;
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struct clk *pclk;
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/* TBD:
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* struct list_head dev_node;
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* struct list_head dom_node;
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* struct list_head ctx_list;
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* DECLARE_BITMAP(context_map, IOMMU_MAX_CBS)
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* struct iommu_device iommu;
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*/
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};
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struct __packed ubwcp_hw_meta_metadata {
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u64 uv_start_addr : 48; /* uv start address */
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u16 format : 16; /* format */
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u16 stride; /* image stride (bytes) */
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u16 stride_ubwcp; /* p010 stride for tp10 image (bytes) */
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u32 metadata_base_y; /* 24-bit page address */
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u32 metadata_base_uv; /* 24-bit page address */
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u16 buffer_y_offset; /* 4KB offset from meta_data_base_y */
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u16 buffer_uv_offset; /* 4KB offset from meta_data_base_y */
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u32 width_height; /* image width (bytes) */
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};
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void ubwcp_hw_version(void __iomem *base, u32 *major, u32 *minor);
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void ubwcp_hw_set_buf_desc(void __iomem *base, u64 desc_addr, u16 desc_stride);
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void ubwcp_hw_enable_range_check(void __iomem *base, u16 index);
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int ubwcp_hw_disable_range_check_with_flush(void __iomem *base, u16 index);
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void ubwcp_hw_set_range_check(void __iomem *base, u16 index, phys_addr_t pa, size_t size);
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u64 ubwcp_hw_interrupt_src_address(void __iomem *base, u16 interrupt);
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void ubwcp_hw_interrupt_clear(void __iomem *base, u16 interrupt);
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void ubwcp_hw_interrupt_enable(void __iomem *base, u16 interrupt, bool enable);
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void ubwcp_hw_power_on(void __iomem *pwr_ctrl, bool power_on);
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void ubwcp_hw_one_time_init(void __iomem *base);
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int ubwcp_hw_flush(void __iomem *base);
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void ubwcp_hw_trace_set(bool value);
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void ubwcp_hw_trace_get(bool *value);
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void ubwcp_hw_single_tile(void __iomem *base, bool en);
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#endif /* __UBWCP_HW_H_ */
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