dsi_display.c 208 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762676367646765676667676768676967706771677267736774677567766777677867796780678167826783678467856786678767886789679067916792679367946795679667976798679968006801680268036804680568066807680868096810681168126813681468156816681768186819682068216822682368246825682668276828682968306831683268336834683568366837683868396840684168426843684468456846684768486849685068516852685368546855685668576858685968606861686268636864686568666867686868696870687168726873687468756876687768786879688068816882688368846885688668876888688968906891689268936894689568966897689868996900690169026903690469056906690769086909691069116912691369146915691669176918691969206921692269236924692569266927692869296930693169326933693469356936693769386939694069416942694369446945694669476948694969506951695269536954695569566957695869596960696169626963696469656966696769686969697069716972697369746975697669776978697969806981698269836984698569866987698869896990699169926993699469956996699769986999700070017002700370047005700670077008700970107011701270137014701570167017701870197020702170227023702470257026702770287029703070317032703370347035703670377038703970407041704270437044704570467047704870497050705170527053705470557056705770587059706070617062706370647065706670677068706970707071707270737074707570767077707870797080708170827083708470857086708770887089709070917092709370947095709670977098709971007101710271037104710571067107710871097110711171127113711471157116711771187119712071217122712371247125712671277128712971307131713271337134713571367137713871397140714171427143714471457146714771487149715071517152715371547155715671577158715971607161716271637164716571667167716871697170717171727173717471757176717771787179718071817182718371847185718671877188718971907191719271937194719571967197719871997200720172027203720472057206720772087209721072117212721372147215721672177218721972207221722272237224722572267227722872297230723172327233723472357236723772387239724072417242724372447245724672477248724972507251725272537254725572567257725872597260726172627263726472657266726772687269727072717272727372747275727672777278727972807281728272837284728572867287728872897290729172927293729472957296729772987299730073017302730373047305730673077308730973107311731273137314731573167317731873197320732173227323732473257326732773287329733073317332733373347335733673377338733973407341734273437344734573467347734873497350735173527353735473557356735773587359736073617362736373647365736673677368736973707371737273737374737573767377737873797380738173827383738473857386738773887389739073917392739373947395739673977398739974007401740274037404740574067407740874097410741174127413741474157416741774187419742074217422742374247425742674277428742974307431743274337434743574367437743874397440744174427443744474457446744774487449745074517452745374547455745674577458745974607461746274637464746574667467746874697470747174727473747474757476747774787479748074817482748374847485748674877488748974907491749274937494749574967497749874997500750175027503750475057506750775087509751075117512751375147515751675177518751975207521752275237524752575267527752875297530753175327533753475357536753775387539754075417542754375447545754675477548754975507551755275537554755575567557755875597560756175627563756475657566756775687569757075717572757375747575757675777578757975807581758275837584758575867587758875897590759175927593759475957596759775987599760076017602760376047605760676077608760976107611761276137614761576167617761876197620762176227623762476257626762776287629763076317632763376347635763676377638763976407641764276437644764576467647764876497650765176527653765476557656765776587659766076617662766376647665766676677668766976707671767276737674767576767677767876797680768176827683768476857686768776887689769076917692769376947695769676977698769977007701770277037704770577067707770877097710771177127713771477157716771777187719772077217722772377247725772677277728772977307731773277337734773577367737773877397740774177427743774477457746774777487749775077517752775377547755775677577758775977607761776277637764776577667767776877697770777177727773777477757776777777787779778077817782778377847785778677877788778977907791779277937794779577967797779877997800780178027803780478057806780778087809781078117812781378147815781678177818781978207821782278237824782578267827782878297830783178327833783478357836783778387839784078417842784378447845784678477848784978507851785278537854785578567857785878597860786178627863786478657866786778687869787078717872787378747875787678777878787978807881788278837884788578867887788878897890789178927893789478957896789778987899790079017902790379047905790679077908790979107911791279137914791579167917791879197920792179227923792479257926792779287929793079317932793379347935793679377938793979407941794279437944794579467947794879497950795179527953795479557956795779587959796079617962796379647965796679677968796979707971797279737974797579767977797879797980798179827983798479857986798779887989799079917992799379947995799679977998799980008001800280038004800580068007800880098010801180128013801480158016801780188019802080218022802380248025802680278028802980308031803280338034803580368037803880398040804180428043804480458046804780488049805080518052805380548055805680578058805980608061806280638064806580668067806880698070807180728073807480758076807780788079808080818082808380848085808680878088808980908091809280938094809580968097809880998100810181028103810481058106810781088109811081118112811381148115811681178118811981208121812281238124812581268127812881298130813181328133813481358136813781388139814081418142814381448145814681478148814981508151815281538154815581568157815881598160816181628163816481658166816781688169817081718172817381748175817681778178817981808181818281838184818581868187818881898190819181928193819481958196819781988199820082018202820382048205820682078208820982108211821282138214821582168217821882198220822182228223822482258226822782288229823082318232823382348235823682378238823982408241824282438244824582468247824882498250825182528253825482558256825782588259826082618262826382648265826682678268826982708271827282738274827582768277827882798280828182828283828482858286828782888289829082918292829382948295829682978298829983008301830283038304830583068307830883098310831183128313831483158316831783188319832083218322832383248325832683278328832983308331833283338334833583368337833883398340834183428343834483458346834783488349835083518352835383548355835683578358835983608361836283638364836583668367836883698370837183728373837483758376837783788379838083818382838383848385838683878388838983908391839283938394839583968397839883998400840184028403840484058406840784088409841084118412841384148415841684178418841984208421842284238424842584268427842884298430843184328433843484358436843784388439844084418442844384448445844684478448844984508451845284538454845584568457845884598460846184628463846484658466
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. #define SEC_PANEL_NAME_MAX_LEN 256
  31. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  32. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  33. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  34. {.boot_param = dsi_display_primary},
  35. {.boot_param = dsi_display_secondary},
  36. };
  37. static const struct of_device_id dsi_display_dt_match[] = {
  38. {.compatible = "qcom,dsi-display"},
  39. {}
  40. };
  41. bool is_skip_op_required(struct dsi_display *display)
  42. {
  43. if (!display)
  44. return false;
  45. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  46. }
  47. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  48. u32 mask, bool enable)
  49. {
  50. int i;
  51. struct dsi_display_ctrl *ctrl;
  52. if (!display)
  53. return;
  54. display_for_each_ctrl(i, display) {
  55. ctrl = &display->ctrl[i];
  56. if (!ctrl)
  57. continue;
  58. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  59. }
  60. }
  61. static int dsi_display_config_clk_gating(struct dsi_display *display,
  62. bool enable)
  63. {
  64. int rc = 0, i = 0;
  65. struct dsi_display_ctrl *mctrl, *ctrl;
  66. enum dsi_clk_gate_type clk_selection;
  67. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  68. if (!display) {
  69. DSI_ERR("Invalid params\n");
  70. return -EINVAL;
  71. }
  72. if (display->panel->host_config.force_hs_clk_lane) {
  73. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  74. return 0;
  75. }
  76. mctrl = &display->ctrl[display->clk_master_idx];
  77. if (!mctrl) {
  78. DSI_ERR("Invalid controller\n");
  79. return -EINVAL;
  80. }
  81. clk_selection = display->clk_gating_config;
  82. if (!enable) {
  83. /* for disable path, make sure to disable all clk gating */
  84. clk_selection = DSI_CLK_ALL;
  85. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  86. /* Default selection, no overrides */
  87. clk_selection = default_clk_select;
  88. } else if (clk_selection == DSI_CLK_NONE) {
  89. clk_selection = 0;
  90. }
  91. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  92. enable ? "Enabling" : "Disabling",
  93. clk_selection & BYTE_CLK ? "yes" : "no",
  94. clk_selection & PIXEL_CLK ? "yes" : "no",
  95. clk_selection & DSI_PHY ? "yes" : "no");
  96. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  97. if (rc) {
  98. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  99. display->name, enable ? "enable" : "disable",
  100. clk_selection, rc);
  101. return rc;
  102. }
  103. display_for_each_ctrl(i, display) {
  104. ctrl = &display->ctrl[i];
  105. if (!ctrl->ctrl || (ctrl == mctrl))
  106. continue;
  107. /**
  108. * In Split DSI usecase we should not enable clock gating on
  109. * DSI PHY1 to ensure no display atrifacts are seen.
  110. */
  111. clk_selection &= ~DSI_PHY;
  112. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  113. clk_selection);
  114. if (rc) {
  115. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  116. display->name, enable ? "enable" : "disable",
  117. clk_selection, rc);
  118. return rc;
  119. }
  120. }
  121. return 0;
  122. }
  123. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  124. bool enable)
  125. {
  126. int i;
  127. struct dsi_display_ctrl *ctrl;
  128. if (!display)
  129. return;
  130. display_for_each_ctrl(i, display) {
  131. ctrl = &display->ctrl[i];
  132. if (!ctrl)
  133. continue;
  134. ctrl->ctrl->esd_check_underway = enable;
  135. }
  136. }
  137. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  138. {
  139. int i;
  140. struct dsi_display_ctrl *ctrl;
  141. if (!display)
  142. return;
  143. display_for_each_ctrl(i, display) {
  144. ctrl = &display->ctrl[i];
  145. if (!ctrl)
  146. continue;
  147. dsi_ctrl_irq_update(ctrl->ctrl, en);
  148. }
  149. }
  150. void dsi_rect_intersect(const struct dsi_rect *r1,
  151. const struct dsi_rect *r2,
  152. struct dsi_rect *result)
  153. {
  154. int l, t, r, b;
  155. if (!r1 || !r2 || !result)
  156. return;
  157. l = max(r1->x, r2->x);
  158. t = max(r1->y, r2->y);
  159. r = min((r1->x + r1->w), (r2->x + r2->w));
  160. b = min((r1->y + r1->h), (r2->y + r2->h));
  161. if (r <= l || b <= t) {
  162. memset(result, 0, sizeof(*result));
  163. } else {
  164. result->x = l;
  165. result->y = t;
  166. result->w = r - l;
  167. result->h = b - t;
  168. }
  169. }
  170. int dsi_display_set_backlight(struct drm_connector *connector,
  171. void *display, u32 bl_lvl)
  172. {
  173. struct dsi_display *dsi_display = display;
  174. struct dsi_panel *panel;
  175. u32 bl_scale, bl_scale_sv;
  176. u64 bl_temp;
  177. int rc = 0;
  178. if (dsi_display == NULL || dsi_display->panel == NULL)
  179. return -EINVAL;
  180. panel = dsi_display->panel;
  181. mutex_lock(&panel->panel_lock);
  182. if (!dsi_panel_initialized(panel)) {
  183. rc = -EINVAL;
  184. goto error;
  185. }
  186. panel->bl_config.bl_level = bl_lvl;
  187. /* scale backlight */
  188. bl_scale = panel->bl_config.bl_scale;
  189. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  190. bl_scale_sv = panel->bl_config.bl_scale_sv;
  191. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  192. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  193. bl_scale, bl_scale_sv, (u32)bl_temp);
  194. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  195. DSI_CORE_CLK, DSI_CLK_ON);
  196. if (rc) {
  197. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  198. dsi_display->name, rc);
  199. goto error;
  200. }
  201. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  202. if (rc)
  203. DSI_ERR("unable to set backlight\n");
  204. rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  205. DSI_CORE_CLK, DSI_CLK_OFF);
  206. if (rc) {
  207. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  208. dsi_display->name, rc);
  209. goto error;
  210. }
  211. error:
  212. mutex_unlock(&panel->panel_lock);
  213. return rc;
  214. }
  215. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  216. {
  217. int rc = 0;
  218. int i;
  219. struct dsi_display_ctrl *m_ctrl, *ctrl;
  220. bool skip_op = is_skip_op_required(display);
  221. m_ctrl = &display->ctrl[display->cmd_master_idx];
  222. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  223. if (display->cmd_engine_refcount > 0) {
  224. display->cmd_engine_refcount++;
  225. goto done;
  226. }
  227. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  228. DSI_CTRL_ENGINE_ON, skip_op);
  229. if (rc) {
  230. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  231. display->name, skip_op, rc);
  232. goto done;
  233. }
  234. display_for_each_ctrl(i, display) {
  235. ctrl = &display->ctrl[i];
  236. if (!ctrl->ctrl || (ctrl == m_ctrl))
  237. continue;
  238. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  239. DSI_CTRL_ENGINE_ON, skip_op);
  240. if (rc) {
  241. DSI_ERR(
  242. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  243. display->name, skip_op, rc);
  244. goto error_disable_master;
  245. }
  246. }
  247. display->cmd_engine_refcount++;
  248. goto done;
  249. error_disable_master:
  250. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  251. DSI_CTRL_ENGINE_OFF, skip_op);
  252. done:
  253. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  254. return rc;
  255. }
  256. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  257. {
  258. int rc = 0;
  259. int i;
  260. struct dsi_display_ctrl *m_ctrl, *ctrl;
  261. bool skip_op = is_skip_op_required(display);
  262. m_ctrl = &display->ctrl[display->cmd_master_idx];
  263. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  264. if (display->cmd_engine_refcount == 0) {
  265. DSI_ERR("[%s] Invalid refcount\n", display->name);
  266. goto done;
  267. } else if (display->cmd_engine_refcount > 1) {
  268. display->cmd_engine_refcount--;
  269. goto done;
  270. }
  271. display_for_each_ctrl(i, display) {
  272. ctrl = &display->ctrl[i];
  273. if (!ctrl->ctrl || (ctrl == m_ctrl))
  274. continue;
  275. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  276. DSI_CTRL_ENGINE_OFF, skip_op);
  277. if (rc)
  278. DSI_ERR(
  279. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  280. display->name, skip_op, rc);
  281. }
  282. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  283. DSI_CTRL_ENGINE_OFF, skip_op);
  284. if (rc) {
  285. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  286. display->name, skip_op, rc);
  287. goto error;
  288. }
  289. error:
  290. display->cmd_engine_refcount = 0;
  291. done:
  292. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  293. return rc;
  294. }
  295. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  296. {
  297. struct dsi_display *display;
  298. struct dsi_display_ctrl *display_ctrl;
  299. int rc, cnt;
  300. if (!cb_data) {
  301. DSI_ERR("aspace cb called with invalid cb_data\n");
  302. return;
  303. }
  304. display = (struct dsi_display *)cb_data;
  305. /*
  306. * acquire panel_lock to make sure no commands are in-progress
  307. * while detaching the non-secure context banks
  308. */
  309. dsi_panel_acquire_panel_lock(display->panel);
  310. if (is_detach) {
  311. /* invalidate the stored iova */
  312. display->cmd_buffer_iova = 0;
  313. /* return the virtual address mapping */
  314. msm_gem_put_vaddr(display->tx_cmd_buf);
  315. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  316. } else {
  317. rc = msm_gem_get_iova(display->tx_cmd_buf,
  318. display->aspace, &(display->cmd_buffer_iova));
  319. if (rc) {
  320. DSI_ERR("failed to get the iova rc %d\n", rc);
  321. goto end;
  322. }
  323. display->vaddr =
  324. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  325. if (IS_ERR_OR_NULL(display->vaddr)) {
  326. DSI_ERR("failed to get va rc %d\n", rc);
  327. goto end;
  328. }
  329. }
  330. display_for_each_ctrl(cnt, display) {
  331. display_ctrl = &display->ctrl[cnt];
  332. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  333. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  334. display_ctrl->ctrl->vaddr = display->vaddr;
  335. display_ctrl->ctrl->secure_mode = is_detach;
  336. }
  337. end:
  338. /* release panel_lock */
  339. dsi_panel_release_panel_lock(display->panel);
  340. }
  341. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  342. {
  343. struct dsi_display *display = (struct dsi_display *)data;
  344. /*
  345. * This irq handler is used for sole purpose of identifying
  346. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  347. * in case of display not being initialized yet
  348. */
  349. if (!display)
  350. return IRQ_HANDLED;
  351. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  352. complete_all(&display->esd_te_gate);
  353. return IRQ_HANDLED;
  354. }
  355. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  356. bool enable)
  357. {
  358. if (!display) {
  359. DSI_ERR("Invalid params\n");
  360. return;
  361. }
  362. /* Handle unbalanced irq enable/disable calls */
  363. if (enable && !display->is_te_irq_enabled) {
  364. enable_irq(gpio_to_irq(display->disp_te_gpio));
  365. display->is_te_irq_enabled = true;
  366. } else if (!enable && display->is_te_irq_enabled) {
  367. disable_irq(gpio_to_irq(display->disp_te_gpio));
  368. display->is_te_irq_enabled = false;
  369. }
  370. }
  371. static void dsi_display_register_te_irq(struct dsi_display *display)
  372. {
  373. int rc = 0;
  374. struct platform_device *pdev;
  375. struct device *dev;
  376. unsigned int te_irq;
  377. pdev = display->pdev;
  378. if (!pdev) {
  379. DSI_ERR("invalid platform device\n");
  380. return;
  381. }
  382. dev = &pdev->dev;
  383. if (!dev) {
  384. DSI_ERR("invalid device\n");
  385. return;
  386. }
  387. if (display->trusted_vm_env) {
  388. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  389. return;
  390. }
  391. if (!gpio_is_valid(display->disp_te_gpio)) {
  392. rc = -EINVAL;
  393. goto error;
  394. }
  395. init_completion(&display->esd_te_gate);
  396. te_irq = gpio_to_irq(display->disp_te_gpio);
  397. /* Avoid deferred spurious irqs with disable_irq() */
  398. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  399. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  400. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  401. "TE_GPIO", display);
  402. if (rc) {
  403. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  404. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  405. goto error;
  406. }
  407. disable_irq(te_irq);
  408. display->is_te_irq_enabled = false;
  409. return;
  410. error:
  411. /* disable the TE based ESD check */
  412. DSI_WARN("Unable to register for TE IRQ\n");
  413. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  414. display->panel->esd_config.esd_enabled = false;
  415. }
  416. /* Allocate memory for cmd dma tx buffer */
  417. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  418. {
  419. int rc = 0, cnt = 0;
  420. struct dsi_display_ctrl *display_ctrl;
  421. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  422. SZ_4K,
  423. MSM_BO_UNCACHED);
  424. if ((display->tx_cmd_buf) == NULL) {
  425. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  426. rc = -ENOMEM;
  427. goto error;
  428. }
  429. display->cmd_buffer_size = SZ_4K;
  430. display->aspace = msm_gem_smmu_address_space_get(
  431. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  432. if (PTR_ERR(display->aspace) == -ENODEV) {
  433. display->aspace = NULL;
  434. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  435. } else if (IS_ERR_OR_NULL(display->aspace)) {
  436. rc = PTR_ERR(display->aspace);
  437. display->aspace = NULL;
  438. DSI_ERR("failed to get aspace %d\n", rc);
  439. goto free_gem;
  440. } else if (display->aspace) {
  441. /* register to aspace */
  442. rc = msm_gem_address_space_register_cb(display->aspace,
  443. dsi_display_aspace_cb_locked, (void *)display);
  444. if (rc) {
  445. DSI_ERR("failed to register callback %d\n", rc);
  446. goto free_gem;
  447. }
  448. }
  449. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  450. &(display->cmd_buffer_iova));
  451. if (rc) {
  452. DSI_ERR("failed to get the iova rc %d\n", rc);
  453. goto free_aspace_cb;
  454. }
  455. display->vaddr =
  456. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  457. if (IS_ERR_OR_NULL(display->vaddr)) {
  458. DSI_ERR("failed to get va rc %d\n", rc);
  459. rc = -EINVAL;
  460. goto put_iova;
  461. }
  462. display_for_each_ctrl(cnt, display) {
  463. display_ctrl = &display->ctrl[cnt];
  464. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  465. display_ctrl->ctrl->cmd_buffer_iova =
  466. display->cmd_buffer_iova;
  467. display_ctrl->ctrl->vaddr = display->vaddr;
  468. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  469. }
  470. return rc;
  471. put_iova:
  472. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  473. free_aspace_cb:
  474. msm_gem_address_space_unregister_cb(display->aspace,
  475. dsi_display_aspace_cb_locked, display);
  476. free_gem:
  477. mutex_lock(&display->drm_dev->struct_mutex);
  478. msm_gem_free_object(display->tx_cmd_buf);
  479. mutex_unlock(&display->drm_dev->struct_mutex);
  480. error:
  481. return rc;
  482. }
  483. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  484. {
  485. int i, j = 0;
  486. int len = 0, *lenp;
  487. int group = 0, count = 0;
  488. struct drm_panel_esd_config *config;
  489. if (!panel)
  490. return false;
  491. config = &(panel->esd_config);
  492. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  493. count = config->status_cmd.count;
  494. for (i = 0; i < count; i++)
  495. len += lenp[i];
  496. for (i = 0; i < len; i++)
  497. j += len;
  498. for (j = 0; j < config->groups; ++j) {
  499. for (i = 0; i < len; ++i) {
  500. if (config->return_buf[i] !=
  501. config->status_value[group + i]) {
  502. DRM_ERROR("mismatch: 0x%x\n",
  503. config->return_buf[i]);
  504. break;
  505. }
  506. }
  507. if (i == len)
  508. return true;
  509. group += len;
  510. }
  511. return false;
  512. }
  513. static void dsi_display_parse_te_data(struct dsi_display *display)
  514. {
  515. struct platform_device *pdev;
  516. struct device *dev;
  517. int rc = 0;
  518. u32 val = 0;
  519. pdev = display->pdev;
  520. if (!pdev) {
  521. DSI_ERR("Invalid platform device\n");
  522. return;
  523. }
  524. dev = &pdev->dev;
  525. if (!dev) {
  526. DSI_ERR("Invalid platform device\n");
  527. return;
  528. }
  529. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  530. "qcom,platform-te-gpio", 0);
  531. if (display->fw)
  532. rc = dsi_parser_read_u32(display->parser_node,
  533. "qcom,panel-te-source", &val);
  534. else
  535. rc = of_property_read_u32(dev->of_node,
  536. "qcom,panel-te-source", &val);
  537. if (rc || (val > MAX_TE_SOURCE_ID)) {
  538. DSI_ERR("invalid vsync source selection\n");
  539. val = 0;
  540. }
  541. display->te_source = val;
  542. }
  543. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  544. struct dsi_panel *panel)
  545. {
  546. int i, rc = 0, count = 0, start = 0, *lenp;
  547. struct drm_panel_esd_config *config;
  548. struct dsi_cmd_desc *cmds;
  549. u32 flags = 0;
  550. if (!panel || !ctrl || !ctrl->ctrl)
  551. return -EINVAL;
  552. /*
  553. * When DSI controller is not in initialized state, we do not want to
  554. * report a false ESD failure and hence we defer until next read
  555. * happen.
  556. */
  557. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  558. return 1;
  559. config = &(panel->esd_config);
  560. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  561. count = config->status_cmd.count;
  562. cmds = config->status_cmd.cmds;
  563. flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);
  564. if (ctrl->ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE)
  565. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  566. for (i = 0; i < count; ++i) {
  567. memset(config->status_buf, 0x0, SZ_4K);
  568. if (cmds[i].last_command) {
  569. cmds[i].msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  570. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  571. }
  572. if ((cmds[i].msg.flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  573. (panel->panel_initialized))
  574. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  575. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  576. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  577. cmds[i].msg.rx_buf = config->status_buf;
  578. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  579. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i].msg, &flags);
  580. if (rc <= 0) {
  581. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  582. return rc;
  583. }
  584. memcpy(config->return_buf + start,
  585. config->status_buf, lenp[i]);
  586. start += lenp[i];
  587. }
  588. return rc;
  589. }
  590. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  591. struct dsi_panel *panel)
  592. {
  593. int rc = 0;
  594. rc = dsi_display_read_status(ctrl, panel);
  595. if (rc <= 0) {
  596. goto exit;
  597. } else {
  598. /*
  599. * panel status read successfully.
  600. * check for validity of the data read back.
  601. */
  602. rc = dsi_display_validate_reg_read(panel);
  603. if (!rc) {
  604. rc = -EINVAL;
  605. goto exit;
  606. }
  607. }
  608. exit:
  609. return rc;
  610. }
  611. static int dsi_display_status_reg_read(struct dsi_display *display)
  612. {
  613. int rc = 0, i;
  614. struct dsi_display_ctrl *m_ctrl, *ctrl;
  615. DSI_DEBUG(" ++\n");
  616. m_ctrl = &display->ctrl[display->cmd_master_idx];
  617. if (display->tx_cmd_buf == NULL) {
  618. rc = dsi_host_alloc_cmd_tx_buffer(display);
  619. if (rc) {
  620. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  621. goto done;
  622. }
  623. }
  624. rc = dsi_display_cmd_engine_enable(display);
  625. if (rc) {
  626. DSI_ERR("cmd engine enable failed\n");
  627. return -EPERM;
  628. }
  629. rc = dsi_display_validate_status(m_ctrl, display->panel);
  630. if (rc <= 0) {
  631. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  632. display->name, rc);
  633. goto exit;
  634. }
  635. if (!display->panel->sync_broadcast_en)
  636. goto exit;
  637. display_for_each_ctrl(i, display) {
  638. ctrl = &display->ctrl[i];
  639. if (ctrl == m_ctrl)
  640. continue;
  641. rc = dsi_display_validate_status(ctrl, display->panel);
  642. if (rc <= 0) {
  643. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  644. display->name, rc);
  645. goto exit;
  646. }
  647. }
  648. exit:
  649. dsi_display_cmd_engine_disable(display);
  650. done:
  651. return rc;
  652. }
  653. static int dsi_display_status_bta_request(struct dsi_display *display)
  654. {
  655. int rc = 0;
  656. DSI_DEBUG(" ++\n");
  657. /* TODO: trigger SW BTA and wait for acknowledgment */
  658. return rc;
  659. }
  660. static int dsi_display_status_check_te(struct dsi_display *display,
  661. int rechecks)
  662. {
  663. int rc = 1, i = 0;
  664. int const esd_te_timeout = msecs_to_jiffies(3*20);
  665. dsi_display_change_te_irq_status(display, true);
  666. for (i = 0; i < rechecks; i++) {
  667. reinit_completion(&display->esd_te_gate);
  668. if (!wait_for_completion_timeout(&display->esd_te_gate,
  669. esd_te_timeout)) {
  670. DSI_ERR("TE check failed\n");
  671. dsi_display_change_te_irq_status(display, false);
  672. return -EINVAL;
  673. }
  674. }
  675. dsi_display_change_te_irq_status(display, false);
  676. return rc;
  677. }
  678. int dsi_display_check_status(struct drm_connector *connector, void *display,
  679. bool te_check_override)
  680. {
  681. struct dsi_display *dsi_display = display;
  682. struct dsi_panel *panel;
  683. u32 status_mode;
  684. int rc = 0x1, ret;
  685. u32 mask;
  686. int te_rechecks = 1;
  687. if (!dsi_display || !dsi_display->panel)
  688. return -EINVAL;
  689. panel = dsi_display->panel;
  690. dsi_panel_acquire_panel_lock(panel);
  691. if (!panel->panel_initialized) {
  692. DSI_DEBUG("Panel not initialized\n");
  693. goto release_panel_lock;
  694. }
  695. /* Prevent another ESD check,when ESD recovery is underway */
  696. if (atomic_read(&panel->esd_recovery_pending))
  697. goto release_panel_lock;
  698. status_mode = panel->esd_config.status_mode;
  699. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) ||
  700. (dsi_display->sw_te_using_wd))
  701. goto release_panel_lock;
  702. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  703. rc = -EINVAL;
  704. goto release_panel_lock;
  705. }
  706. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  707. if (te_check_override)
  708. te_rechecks = MAX_TE_RECHECKS;
  709. if (panel->panel_mode == DSI_OP_VIDEO_MODE)
  710. te_rechecks = 0;
  711. ret = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  712. DSI_ALL_CLKS, DSI_CLK_ON);
  713. if (ret)
  714. goto release_panel_lock;
  715. /* Mask error interrupts before attempting ESD read */
  716. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  717. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  718. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask, true);
  719. if (status_mode == ESD_MODE_REG_READ) {
  720. rc = dsi_display_status_reg_read(dsi_display);
  721. } else if (status_mode == ESD_MODE_SW_BTA) {
  722. rc = dsi_display_status_bta_request(dsi_display);
  723. } else if (status_mode == ESD_MODE_PANEL_TE) {
  724. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  725. te_check_override = false;
  726. } else {
  727. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  728. panel->esd_config.esd_enabled = false;
  729. }
  730. if (rc <= 0 && te_check_override)
  731. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  732. /* Unmask error interrupts if check passed*/
  733. if (rc > 0) {
  734. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  735. dsi_display_mask_ctrl_error_interrupts(dsi_display, mask,
  736. false);
  737. if (te_check_override && panel->esd_config.esd_enabled == false)
  738. rc = dsi_display_status_check_te(dsi_display,
  739. te_rechecks);
  740. }
  741. dsi_display_clk_ctrl(dsi_display->dsi_clk_handle,
  742. DSI_ALL_CLKS, DSI_CLK_OFF);
  743. /* Handle Panel failures during display disable sequence */
  744. if (rc <=0)
  745. atomic_set(&panel->esd_recovery_pending, 1);
  746. release_panel_lock:
  747. dsi_panel_release_panel_lock(panel);
  748. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  749. return rc;
  750. }
  751. static int dsi_display_cmd_prepare(const char *cmd_buf, u32 cmd_buf_len,
  752. struct dsi_cmd_desc *cmd, u8 *payload, u32 payload_len)
  753. {
  754. int i;
  755. memset(cmd, 0x00, sizeof(*cmd));
  756. cmd->msg.type = cmd_buf[0];
  757. cmd->last_command = (cmd_buf[1] == 1);
  758. cmd->msg.channel = cmd_buf[2];
  759. cmd->msg.flags = cmd_buf[3];
  760. cmd->msg.ctrl = 0;
  761. cmd->post_wait_ms = cmd->msg.wait_ms = cmd_buf[4];
  762. cmd->msg.tx_len = ((cmd_buf[5] << 8) | (cmd_buf[6]));
  763. if (cmd->msg.tx_len > payload_len) {
  764. DSI_ERR("Incorrect payload length tx_len %zu, payload_len %d\n",
  765. cmd->msg.tx_len, payload_len);
  766. return -EINVAL;
  767. }
  768. if (cmd->last_command)
  769. cmd->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND;
  770. for (i = 0; i < cmd->msg.tx_len; i++)
  771. payload[i] = cmd_buf[7 + i];
  772. cmd->msg.tx_buf = payload;
  773. return 0;
  774. }
  775. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  776. bool *state)
  777. {
  778. struct dsi_display_ctrl *ctrl;
  779. int i, rc = -EINVAL;
  780. display_for_each_ctrl(i, dsi_display) {
  781. ctrl = &dsi_display->ctrl[i];
  782. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  783. if (rc)
  784. break;
  785. }
  786. return rc;
  787. }
  788. static int dsi_display_cmd_rx(struct dsi_display *display,
  789. struct dsi_cmd_desc *cmd)
  790. {
  791. struct dsi_display_ctrl *m_ctrl = NULL;
  792. u32 mask = 0, flags = 0;
  793. int rc = 0;
  794. if (!display || !display->panel)
  795. return -EINVAL;
  796. m_ctrl = &display->ctrl[display->cmd_master_idx];
  797. if (!m_ctrl || !m_ctrl->ctrl)
  798. return -EINVAL;
  799. /* acquire panel_lock to make sure no commands are in progress */
  800. dsi_panel_acquire_panel_lock(display->panel);
  801. if (!display->panel->panel_initialized) {
  802. DSI_DEBUG("panel not initialized\n");
  803. goto release_panel_lock;
  804. }
  805. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  806. DSI_ALL_CLKS, DSI_CLK_ON);
  807. if (rc)
  808. goto release_panel_lock;
  809. mask = BIT(DSI_FIFO_OVERFLOW) | BIT(DSI_FIFO_UNDERFLOW);
  810. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  811. rc = dsi_display_cmd_engine_enable(display);
  812. if (rc) {
  813. DSI_ERR("cmd engine enable failed rc = %d\n", rc);
  814. goto error;
  815. }
  816. flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ);
  817. if ((m_ctrl->ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE) ||
  818. ((cmd->msg.flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  819. (display->panel->panel_initialized)))
  820. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  821. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmd->msg, &flags);
  822. if (rc <= 0)
  823. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  824. dsi_display_cmd_engine_disable(display);
  825. error:
  826. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  827. dsi_display_clk_ctrl(display->dsi_clk_handle,
  828. DSI_ALL_CLKS, DSI_CLK_OFF);
  829. release_panel_lock:
  830. dsi_panel_release_panel_lock(display->panel);
  831. return rc;
  832. }
  833. int dsi_display_cmd_transfer(struct drm_connector *connector,
  834. void *display, const char *cmd_buf,
  835. u32 cmd_buf_len)
  836. {
  837. struct dsi_display *dsi_display = display;
  838. struct dsi_cmd_desc cmd;
  839. u8 cmd_payload[MAX_CMD_PAYLOAD_SIZE];
  840. int rc = 0;
  841. bool state = false;
  842. if (!dsi_display || !cmd_buf) {
  843. DSI_ERR("[DSI] invalid params\n");
  844. return -EINVAL;
  845. }
  846. DSI_DEBUG("[DSI] Display command transfer\n");
  847. rc = dsi_display_cmd_prepare(cmd_buf, cmd_buf_len,
  848. &cmd, cmd_payload, MAX_CMD_PAYLOAD_SIZE);
  849. if (rc) {
  850. DSI_ERR("[DSI] command prepare failed. rc %d\n", rc);
  851. return rc;
  852. }
  853. mutex_lock(&dsi_display->display_lock);
  854. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  855. /**
  856. * Handle scenario where a command transfer is initiated through
  857. * sysfs interface when device is in suepnd state.
  858. */
  859. if (!rc && !state) {
  860. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  861. );
  862. rc = -EPERM;
  863. goto end;
  864. }
  865. if (rc || !state) {
  866. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  867. state, rc);
  868. rc = -EPERM;
  869. goto end;
  870. }
  871. rc = dsi_display->host.ops->transfer(&dsi_display->host,
  872. &cmd.msg);
  873. end:
  874. mutex_unlock(&dsi_display->display_lock);
  875. return rc;
  876. }
  877. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  878. bool enable)
  879. {
  880. int i;
  881. struct dsi_display_ctrl *ctrl;
  882. if (!display || !display->panel->host_config.force_hs_clk_lane)
  883. return;
  884. display_for_each_ctrl(i, display) {
  885. ctrl = &display->ctrl[i];
  886. /*
  887. * For phy ver 4.0 chipsets, configure DSI controller and
  888. * DSI PHY to force clk lane to HS mode always whereas
  889. * for other phy ver chipsets, configure DSI controller only.
  890. */
  891. if (ctrl->phy->hw.ops.set_continuous_clk) {
  892. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  893. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  894. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  895. } else {
  896. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  897. }
  898. }
  899. }
  900. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  901. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  902. {
  903. struct dsi_display *dsi_display = display;
  904. struct dsi_cmd_desc cmd = {};
  905. u8 cmd_payload[MAX_CMD_PAYLOAD_SIZE] = {0};
  906. bool state = false;
  907. int rc = -1;
  908. if (!dsi_display || !cmd_buf || !recv_buf) {
  909. DSI_ERR("[DSI] invalid params\n");
  910. return -EINVAL;
  911. }
  912. rc = dsi_display_cmd_prepare(cmd_buf, cmd_buf_len,
  913. &cmd, cmd_payload, MAX_CMD_PAYLOAD_SIZE);
  914. if (rc) {
  915. DSI_ERR("[DSI] command prepare failed, rc = %d\n", rc);
  916. return rc;
  917. }
  918. cmd.msg.rx_buf = recv_buf;
  919. cmd.msg.rx_len = recv_buf_len;
  920. mutex_lock(&dsi_display->display_lock);
  921. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  922. if (rc || !state) {
  923. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  924. state, rc);
  925. rc = -EPERM;
  926. goto end;
  927. }
  928. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  929. if (rc <= 0)
  930. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  931. end:
  932. mutex_unlock(&dsi_display->display_lock);
  933. return rc;
  934. }
  935. int dsi_display_soft_reset(void *display)
  936. {
  937. struct dsi_display *dsi_display;
  938. struct dsi_display_ctrl *ctrl;
  939. int rc = 0;
  940. int i;
  941. if (!display)
  942. return -EINVAL;
  943. dsi_display = display;
  944. display_for_each_ctrl(i, dsi_display) {
  945. ctrl = &dsi_display->ctrl[i];
  946. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  947. if (rc) {
  948. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  949. dsi_display->name, i, rc);
  950. break;
  951. }
  952. }
  953. return rc;
  954. }
  955. enum dsi_pixel_format dsi_display_get_dst_format(
  956. struct drm_connector *connector,
  957. void *display)
  958. {
  959. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  960. struct dsi_display *dsi_display = (struct dsi_display *)display;
  961. if (!dsi_display || !dsi_display->panel) {
  962. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  963. dsi_display,
  964. ((dsi_display) ? dsi_display->panel : NULL));
  965. return format;
  966. }
  967. format = dsi_display->panel->host_config.dst_format;
  968. return format;
  969. }
  970. static void _dsi_display_setup_misr(struct dsi_display *display)
  971. {
  972. int i;
  973. display_for_each_ctrl(i, display) {
  974. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  975. display->misr_enable,
  976. display->misr_frame_count);
  977. }
  978. }
  979. int dsi_display_set_power(struct drm_connector *connector,
  980. int power_mode, void *disp)
  981. {
  982. struct dsi_display *display = disp;
  983. int rc = 0;
  984. if (!display || !display->panel) {
  985. DSI_ERR("invalid display/panel\n");
  986. return -EINVAL;
  987. }
  988. switch (power_mode) {
  989. case SDE_MODE_DPMS_LP1:
  990. rc = dsi_panel_set_lp1(display->panel);
  991. break;
  992. case SDE_MODE_DPMS_LP2:
  993. rc = dsi_panel_set_lp2(display->panel);
  994. break;
  995. case SDE_MODE_DPMS_ON:
  996. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  997. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  998. rc = dsi_panel_set_nolp(display->panel);
  999. break;
  1000. case SDE_MODE_DPMS_OFF:
  1001. default:
  1002. return rc;
  1003. }
  1004. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1005. DSI_DEBUG("Power mode transition from %d to %d %s",
  1006. display->panel->power_mode, power_mode,
  1007. rc ? "failed" : "successful");
  1008. if (!rc)
  1009. display->panel->power_mode = power_mode;
  1010. return rc;
  1011. }
  1012. #ifdef CONFIG_DEBUG_FS
  1013. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1014. {
  1015. u32 status_mode = 0;
  1016. if (!display->panel) {
  1017. DSI_ERR("Invalid panel data\n");
  1018. return false;
  1019. }
  1020. status_mode = display->panel->esd_config.status_mode;
  1021. if (status_mode == ESD_MODE_PANEL_TE &&
  1022. gpio_is_valid(display->disp_te_gpio))
  1023. return true;
  1024. return false;
  1025. }
  1026. static ssize_t debugfs_dump_info_read(struct file *file,
  1027. char __user *user_buf,
  1028. size_t user_len,
  1029. loff_t *ppos)
  1030. {
  1031. struct dsi_display *display = file->private_data;
  1032. char *buf;
  1033. u32 len = 0;
  1034. int i;
  1035. if (!display)
  1036. return -ENODEV;
  1037. if (*ppos)
  1038. return 0;
  1039. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1040. if (!buf)
  1041. return -ENOMEM;
  1042. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1043. len += snprintf(buf + len, (SZ_4K - len),
  1044. "\tResolution = %dx%d\n",
  1045. display->config.video_timing.h_active,
  1046. display->config.video_timing.v_active);
  1047. display_for_each_ctrl(i, display) {
  1048. len += snprintf(buf + len, (SZ_4K - len),
  1049. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1050. i, display->ctrl[i].ctrl->name,
  1051. display->ctrl[i].phy->name);
  1052. }
  1053. len += snprintf(buf + len, (SZ_4K - len),
  1054. "\tPanel = %s\n", display->panel->name);
  1055. len += snprintf(buf + len, (SZ_4K - len),
  1056. "\tClock master = %s\n",
  1057. display->ctrl[display->clk_master_idx].ctrl->name);
  1058. if (len > user_len)
  1059. len = user_len;
  1060. if (copy_to_user(user_buf, buf, len)) {
  1061. kfree(buf);
  1062. return -EFAULT;
  1063. }
  1064. *ppos += len;
  1065. kfree(buf);
  1066. return len;
  1067. }
  1068. static ssize_t debugfs_misr_setup(struct file *file,
  1069. const char __user *user_buf,
  1070. size_t user_len,
  1071. loff_t *ppos)
  1072. {
  1073. struct dsi_display *display = file->private_data;
  1074. char *buf;
  1075. int rc = 0;
  1076. size_t len;
  1077. u32 enable, frame_count;
  1078. if (!display)
  1079. return -ENODEV;
  1080. if (*ppos)
  1081. return 0;
  1082. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1083. if (!buf)
  1084. return -ENOMEM;
  1085. /* leave room for termination char */
  1086. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1087. if (copy_from_user(buf, user_buf, len)) {
  1088. rc = -EINVAL;
  1089. goto error;
  1090. }
  1091. buf[len] = '\0'; /* terminate the string */
  1092. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1093. rc = -EINVAL;
  1094. goto error;
  1095. }
  1096. display->misr_enable = enable;
  1097. display->misr_frame_count = frame_count;
  1098. mutex_lock(&display->display_lock);
  1099. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1100. DSI_CORE_CLK, DSI_CLK_ON);
  1101. if (rc) {
  1102. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1103. display->name, rc);
  1104. goto unlock;
  1105. }
  1106. _dsi_display_setup_misr(display);
  1107. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1108. DSI_CORE_CLK, DSI_CLK_OFF);
  1109. if (rc) {
  1110. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1111. display->name, rc);
  1112. goto unlock;
  1113. }
  1114. rc = user_len;
  1115. unlock:
  1116. mutex_unlock(&display->display_lock);
  1117. error:
  1118. kfree(buf);
  1119. return rc;
  1120. }
  1121. static ssize_t debugfs_misr_read(struct file *file,
  1122. char __user *user_buf,
  1123. size_t user_len,
  1124. loff_t *ppos)
  1125. {
  1126. struct dsi_display *display = file->private_data;
  1127. char *buf;
  1128. u32 len = 0;
  1129. int rc = 0;
  1130. struct dsi_ctrl *dsi_ctrl;
  1131. int i;
  1132. u32 misr;
  1133. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1134. if (!display)
  1135. return -ENODEV;
  1136. if (*ppos)
  1137. return 0;
  1138. buf = kzalloc(max_len, GFP_KERNEL);
  1139. if (ZERO_OR_NULL_PTR(buf))
  1140. return -ENOMEM;
  1141. mutex_lock(&display->display_lock);
  1142. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1143. DSI_CORE_CLK, DSI_CLK_ON);
  1144. if (rc) {
  1145. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1146. display->name, rc);
  1147. goto error;
  1148. }
  1149. display_for_each_ctrl(i, display) {
  1150. dsi_ctrl = display->ctrl[i].ctrl;
  1151. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1152. len += snprintf((buf + len), max_len - len,
  1153. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1154. if (len >= max_len)
  1155. break;
  1156. }
  1157. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1158. DSI_CORE_CLK, DSI_CLK_OFF);
  1159. if (rc) {
  1160. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1161. display->name, rc);
  1162. goto error;
  1163. }
  1164. if (copy_to_user(user_buf, buf, max_len)) {
  1165. rc = -EFAULT;
  1166. goto error;
  1167. }
  1168. *ppos += len;
  1169. error:
  1170. mutex_unlock(&display->display_lock);
  1171. kfree(buf);
  1172. return len;
  1173. }
  1174. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1175. const char __user *user_buf,
  1176. size_t user_len,
  1177. loff_t *ppos)
  1178. {
  1179. struct dsi_display *display = file->private_data;
  1180. char *buf;
  1181. int rc = 0;
  1182. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1183. u32 esd_trigger;
  1184. size_t len;
  1185. if (!display)
  1186. return -ENODEV;
  1187. if (*ppos)
  1188. return 0;
  1189. if (user_len > sizeof(u32))
  1190. return -EINVAL;
  1191. if (!user_len || !user_buf)
  1192. return -EINVAL;
  1193. if (!display->panel ||
  1194. atomic_read(&display->panel->esd_recovery_pending))
  1195. return user_len;
  1196. if (!esd_config->esd_enabled) {
  1197. DSI_ERR("ESD feature is not enabled\n");
  1198. return -EINVAL;
  1199. }
  1200. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1201. if (!buf)
  1202. return -ENOMEM;
  1203. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1204. if (copy_from_user(buf, user_buf, len)) {
  1205. rc = -EINVAL;
  1206. goto error;
  1207. }
  1208. buf[len] = '\0'; /* terminate the string */
  1209. if (kstrtouint(buf, 10, &esd_trigger)) {
  1210. rc = -EINVAL;
  1211. goto error;
  1212. }
  1213. if (esd_trigger != 1) {
  1214. rc = -EINVAL;
  1215. goto error;
  1216. }
  1217. display->esd_trigger = esd_trigger;
  1218. if (display->esd_trigger) {
  1219. DSI_INFO("ESD attack triggered by user\n");
  1220. rc = dsi_panel_trigger_esd_attack(display->panel);
  1221. if (rc) {
  1222. DSI_ERR("Failed to trigger ESD attack\n");
  1223. goto error;
  1224. }
  1225. }
  1226. rc = len;
  1227. error:
  1228. kfree(buf);
  1229. return rc;
  1230. }
  1231. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1232. const char __user *user_buf,
  1233. size_t user_len,
  1234. loff_t *ppos)
  1235. {
  1236. struct dsi_display *display = file->private_data;
  1237. struct drm_panel_esd_config *esd_config;
  1238. char *buf;
  1239. int rc = 0;
  1240. size_t len;
  1241. if (!display)
  1242. return -ENODEV;
  1243. if (*ppos)
  1244. return 0;
  1245. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1246. if (ZERO_OR_NULL_PTR(buf))
  1247. return -ENOMEM;
  1248. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1249. if (copy_from_user(buf, user_buf, len)) {
  1250. rc = -EINVAL;
  1251. goto error;
  1252. }
  1253. buf[len] = '\0'; /* terminate the string */
  1254. if (!display->panel) {
  1255. rc = -EINVAL;
  1256. goto error;
  1257. }
  1258. esd_config = &display->panel->esd_config;
  1259. if (!esd_config) {
  1260. DSI_ERR("Invalid panel esd config\n");
  1261. rc = -EINVAL;
  1262. goto error;
  1263. }
  1264. if (!esd_config->esd_enabled) {
  1265. rc = -EINVAL;
  1266. goto error;
  1267. }
  1268. if (!strcmp(buf, "te_signal_check\n")) {
  1269. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1270. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1271. rc = -EINVAL;
  1272. goto error;
  1273. }
  1274. DSI_INFO("ESD check is switched to TE mode by user\n");
  1275. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1276. dsi_display_change_te_irq_status(display, true);
  1277. }
  1278. if (!strcmp(buf, "reg_read\n")) {
  1279. DSI_INFO("ESD check is switched to reg read by user\n");
  1280. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1281. if (rc) {
  1282. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1283. rc);
  1284. rc = user_len;
  1285. goto error;
  1286. }
  1287. esd_config->status_mode = ESD_MODE_REG_READ;
  1288. if (dsi_display_is_te_based_esd(display))
  1289. dsi_display_change_te_irq_status(display, false);
  1290. }
  1291. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1292. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1293. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1294. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1295. rc = len;
  1296. error:
  1297. kfree(buf);
  1298. return rc;
  1299. }
  1300. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1301. char __user *user_buf,
  1302. size_t user_len,
  1303. loff_t *ppos)
  1304. {
  1305. struct dsi_display *display = file->private_data;
  1306. struct drm_panel_esd_config *esd_config;
  1307. char *buf;
  1308. int rc = 0;
  1309. size_t len = 0;
  1310. if (!display)
  1311. return -ENODEV;
  1312. if (*ppos)
  1313. return 0;
  1314. if (!display->panel) {
  1315. DSI_ERR("invalid panel data\n");
  1316. return -EINVAL;
  1317. }
  1318. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1319. if (ZERO_OR_NULL_PTR(buf))
  1320. return -ENOMEM;
  1321. esd_config = &display->panel->esd_config;
  1322. if (!esd_config) {
  1323. DSI_ERR("Invalid panel esd config\n");
  1324. rc = -EINVAL;
  1325. goto error;
  1326. }
  1327. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1328. if (!esd_config->esd_enabled) {
  1329. rc = snprintf(buf, len, "ESD feature not enabled");
  1330. goto output_mode;
  1331. }
  1332. switch (esd_config->status_mode) {
  1333. case ESD_MODE_REG_READ:
  1334. rc = snprintf(buf, len, "reg_read");
  1335. break;
  1336. case ESD_MODE_PANEL_TE:
  1337. rc = snprintf(buf, len, "te_signal_check");
  1338. break;
  1339. case ESD_MODE_SW_SIM_FAILURE:
  1340. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1341. break;
  1342. case ESD_MODE_SW_SIM_SUCCESS:
  1343. rc = snprintf(buf, len, "esd_sw_sim_success");
  1344. break;
  1345. default:
  1346. rc = snprintf(buf, len, "invalid");
  1347. break;
  1348. }
  1349. output_mode:
  1350. if (!rc) {
  1351. rc = -EINVAL;
  1352. goto error;
  1353. }
  1354. if (copy_to_user(user_buf, buf, len)) {
  1355. rc = -EFAULT;
  1356. goto error;
  1357. }
  1358. *ppos += len;
  1359. error:
  1360. kfree(buf);
  1361. return len;
  1362. }
  1363. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1364. const char __user *user_buf,
  1365. size_t user_len,
  1366. loff_t *ppos)
  1367. {
  1368. struct dsi_display *display = file->private_data;
  1369. struct dsi_display_ctrl *display_ctrl;
  1370. char *buf;
  1371. int rc = 0;
  1372. u32 line = 0, window = 0;
  1373. size_t len;
  1374. int i;
  1375. if (!display)
  1376. return -ENODEV;
  1377. if (*ppos)
  1378. return 0;
  1379. buf = kzalloc(256, GFP_KERNEL);
  1380. if (ZERO_OR_NULL_PTR(buf))
  1381. return -ENOMEM;
  1382. len = min_t(size_t, user_len, 255);
  1383. if (copy_from_user(buf, user_buf, len)) {
  1384. rc = -EINVAL;
  1385. goto error;
  1386. }
  1387. buf[len] = '\0'; /* terminate the string */
  1388. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1389. return -EFAULT;
  1390. display_for_each_ctrl(i, display) {
  1391. struct dsi_ctrl *ctrl;
  1392. display_ctrl = &display->ctrl[i];
  1393. if (!display_ctrl->ctrl)
  1394. continue;
  1395. ctrl = display_ctrl->ctrl;
  1396. ctrl->host_config.common_config.dma_sched_line = line;
  1397. ctrl->host_config.common_config.dma_sched_window = window;
  1398. }
  1399. rc = len;
  1400. error:
  1401. kfree(buf);
  1402. return rc;
  1403. }
  1404. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1405. char __user *user_buf,
  1406. size_t user_len,
  1407. loff_t *ppos)
  1408. {
  1409. struct dsi_display *display = file->private_data;
  1410. struct dsi_display_ctrl *m_ctrl;
  1411. struct dsi_ctrl *ctrl;
  1412. char *buf;
  1413. u32 len = 0;
  1414. int rc = 0;
  1415. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1416. if (!display)
  1417. return -ENODEV;
  1418. if (*ppos)
  1419. return 0;
  1420. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1421. ctrl = m_ctrl->ctrl;
  1422. buf = kzalloc(max_len, GFP_KERNEL);
  1423. if (ZERO_OR_NULL_PTR(buf))
  1424. return -ENOMEM;
  1425. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1426. ctrl->host_config.common_config.dma_sched_line);
  1427. len += scnprintf((buf + len), max_len - len,
  1428. "Schedule command window width: %d\n",
  1429. ctrl->host_config.common_config.dma_sched_window);
  1430. if (len > max_len)
  1431. len = max_len;
  1432. if (copy_to_user(user_buf, buf, len)) {
  1433. rc = -EFAULT;
  1434. goto error;
  1435. }
  1436. *ppos += len;
  1437. error:
  1438. kfree(buf);
  1439. return len;
  1440. }
  1441. static const struct file_operations dump_info_fops = {
  1442. .open = simple_open,
  1443. .read = debugfs_dump_info_read,
  1444. };
  1445. static const struct file_operations misr_data_fops = {
  1446. .open = simple_open,
  1447. .read = debugfs_misr_read,
  1448. .write = debugfs_misr_setup,
  1449. };
  1450. static const struct file_operations esd_trigger_fops = {
  1451. .open = simple_open,
  1452. .write = debugfs_esd_trigger_check,
  1453. };
  1454. static const struct file_operations esd_check_mode_fops = {
  1455. .open = simple_open,
  1456. .write = debugfs_alter_esd_check_mode,
  1457. .read = debugfs_read_esd_check_mode,
  1458. };
  1459. static const struct file_operations dsi_command_scheduling_fops = {
  1460. .open = simple_open,
  1461. .write = debugfs_update_cmd_scheduling_params,
  1462. .read = debugfs_read_cmd_scheduling_params,
  1463. };
  1464. static int dsi_display_debugfs_init(struct dsi_display *display)
  1465. {
  1466. int rc = 0;
  1467. struct dentry *dir, *dump_file, *misr_data;
  1468. char name[MAX_NAME_SIZE];
  1469. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1470. char secondary_panel_str[] = "_secondary";
  1471. int i;
  1472. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1473. if (strcmp(display->display_type, "secondary") == 0)
  1474. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1475. dir = debugfs_create_dir(panel_name, NULL);
  1476. if (IS_ERR_OR_NULL(dir)) {
  1477. rc = PTR_ERR(dir);
  1478. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1479. display->name, rc);
  1480. goto error;
  1481. }
  1482. dump_file = debugfs_create_file("dump_info",
  1483. 0400,
  1484. dir,
  1485. display,
  1486. &dump_info_fops);
  1487. if (IS_ERR_OR_NULL(dump_file)) {
  1488. rc = PTR_ERR(dump_file);
  1489. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1490. display->name, rc);
  1491. goto error_remove_dir;
  1492. }
  1493. dump_file = debugfs_create_file("esd_trigger",
  1494. 0644,
  1495. dir,
  1496. display,
  1497. &esd_trigger_fops);
  1498. if (IS_ERR_OR_NULL(dump_file)) {
  1499. rc = PTR_ERR(dump_file);
  1500. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1501. display->name, rc);
  1502. goto error_remove_dir;
  1503. }
  1504. dump_file = debugfs_create_file("esd_check_mode",
  1505. 0644,
  1506. dir,
  1507. display,
  1508. &esd_check_mode_fops);
  1509. if (IS_ERR_OR_NULL(dump_file)) {
  1510. rc = PTR_ERR(dump_file);
  1511. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1512. display->name, rc);
  1513. goto error_remove_dir;
  1514. }
  1515. dump_file = debugfs_create_file("cmd_sched_params",
  1516. 0644,
  1517. dir,
  1518. display,
  1519. &dsi_command_scheduling_fops);
  1520. if (IS_ERR_OR_NULL(dump_file)) {
  1521. rc = PTR_ERR(dump_file);
  1522. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1523. display->name, rc);
  1524. goto error_remove_dir;
  1525. }
  1526. misr_data = debugfs_create_file("misr_data",
  1527. 0600,
  1528. dir,
  1529. display,
  1530. &misr_data_fops);
  1531. if (IS_ERR_OR_NULL(misr_data)) {
  1532. rc = PTR_ERR(misr_data);
  1533. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1534. display->name, rc);
  1535. goto error_remove_dir;
  1536. }
  1537. display_for_each_ctrl(i, display) {
  1538. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1539. if (!phy || !phy->name)
  1540. continue;
  1541. snprintf(name, ARRAY_SIZE(name),
  1542. "%s_allow_phy_power_off", phy->name);
  1543. dump_file = debugfs_create_bool(name, 0600, dir,
  1544. &phy->allow_phy_power_off);
  1545. if (IS_ERR_OR_NULL(dump_file)) {
  1546. rc = PTR_ERR(dump_file);
  1547. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1548. display->name, name, rc);
  1549. goto error_remove_dir;
  1550. }
  1551. snprintf(name, ARRAY_SIZE(name),
  1552. "%s_regulator_min_datarate_bps", phy->name);
  1553. dump_file = debugfs_create_u32(name, 0600, dir,
  1554. &phy->regulator_min_datarate_bps);
  1555. if (IS_ERR_OR_NULL(dump_file)) {
  1556. rc = PTR_ERR(dump_file);
  1557. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1558. display->name, name, rc);
  1559. goto error_remove_dir;
  1560. }
  1561. }
  1562. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1563. &display->panel->ulps_feature_enabled)) {
  1564. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1565. display->name);
  1566. goto error_remove_dir;
  1567. }
  1568. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1569. &display->panel->ulps_suspend_enabled)) {
  1570. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1571. display->name);
  1572. goto error_remove_dir;
  1573. }
  1574. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1575. &display->ulps_enabled)) {
  1576. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1577. display->name);
  1578. goto error_remove_dir;
  1579. }
  1580. if (!debugfs_create_u32("clk_gating_config", 0600, dir,
  1581. &display->clk_gating_config)) {
  1582. DSI_ERR("[%s] debugfs create clk gating config failed\n",
  1583. display->name);
  1584. goto error_remove_dir;
  1585. }
  1586. display->root = dir;
  1587. dsi_parser_dbg_init(display->parser, dir);
  1588. return rc;
  1589. error_remove_dir:
  1590. debugfs_remove(dir);
  1591. error:
  1592. return rc;
  1593. }
  1594. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1595. {
  1596. debugfs_remove_recursive(display->root);
  1597. return 0;
  1598. }
  1599. #else
  1600. static int dsi_display_debugfs_init(struct dsi_display *display)
  1601. {
  1602. return 0;
  1603. }
  1604. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1605. {
  1606. return 0;
  1607. }
  1608. #endif /* CONFIG_DEBUG_FS */
  1609. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1610. struct dsi_display_mode *mode)
  1611. {
  1612. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1613. bool is_split_link = host->split_link.split_link_enabled;
  1614. u32 sublinks_count = host->split_link.num_sublinks;
  1615. if (is_split_link && sublinks_count > 1) {
  1616. mode->timing.h_active /= sublinks_count;
  1617. mode->timing.h_front_porch /= sublinks_count;
  1618. mode->timing.h_sync_width /= sublinks_count;
  1619. mode->timing.h_back_porch /= sublinks_count;
  1620. mode->timing.h_skew /= sublinks_count;
  1621. mode->pixel_clk_khz /= sublinks_count;
  1622. } else {
  1623. if (mode->priv_info->dsc_enabled)
  1624. mode->priv_info->dsc.config.pic_width =
  1625. mode->timing.h_active;
  1626. mode->timing.h_active /= display->ctrl_count;
  1627. mode->timing.h_front_porch /= display->ctrl_count;
  1628. mode->timing.h_sync_width /= display->ctrl_count;
  1629. mode->timing.h_back_porch /= display->ctrl_count;
  1630. mode->timing.h_skew /= display->ctrl_count;
  1631. mode->pixel_clk_khz /= display->ctrl_count;
  1632. }
  1633. }
  1634. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1635. bool enable)
  1636. {
  1637. /* TODO: make checks based on cont. splash */
  1638. DSI_DEBUG("checking ulps req validity\n");
  1639. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1640. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1641. return false;
  1642. }
  1643. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1644. !display->panel->ulps_suspend_enabled) {
  1645. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1646. return false;
  1647. }
  1648. if (!dsi_panel_initialized(display->panel) &&
  1649. !display->panel->ulps_suspend_enabled) {
  1650. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1651. return false;
  1652. }
  1653. if (enable && display->ulps_enabled) {
  1654. DSI_DEBUG("ULPS already enabled\n");
  1655. return false;
  1656. } else if (!enable && !display->ulps_enabled) {
  1657. DSI_DEBUG("ULPS already disabled\n");
  1658. return false;
  1659. }
  1660. /*
  1661. * No need to enter ULPS when transitioning from splash screen to
  1662. * boot animation or trusted vm environments since it is expected
  1663. * that the clocks would be turned right back on.
  1664. */
  1665. if (enable && is_skip_op_required(display))
  1666. return false;
  1667. return true;
  1668. }
  1669. /**
  1670. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1671. * @dsi_display: DSI display handle.
  1672. * @enable: enable/disable ULPS.
  1673. *
  1674. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1675. *
  1676. * Return: error code.
  1677. */
  1678. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1679. {
  1680. int rc = 0;
  1681. int i = 0;
  1682. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1683. if (!display) {
  1684. DSI_ERR("Invalid params\n");
  1685. return -EINVAL;
  1686. }
  1687. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1688. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1689. __func__, enable);
  1690. return 0;
  1691. }
  1692. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1693. /*
  1694. * ULPS entry-exit can be either through the DSI controller or
  1695. * the DSI PHY depending on hardware variation. For some chipsets,
  1696. * both controller version and phy version ulps entry-exit ops can
  1697. * be present. To handle such cases, send ulps request through PHY,
  1698. * if ulps request is handled in PHY, then no need to send request
  1699. * through controller.
  1700. */
  1701. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1702. display->clamp_enabled);
  1703. if (rc == DSI_PHY_ULPS_ERROR) {
  1704. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1705. return -EINVAL;
  1706. }
  1707. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1708. display_for_each_ctrl(i, display) {
  1709. ctrl = &display->ctrl[i];
  1710. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1711. continue;
  1712. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1713. enable, display->clamp_enabled);
  1714. if (rc == DSI_PHY_ULPS_ERROR) {
  1715. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1716. enable);
  1717. return -EINVAL;
  1718. }
  1719. }
  1720. }
  1721. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1722. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1723. if (rc) {
  1724. DSI_ERR("Ulps controller state change(%d) failed\n",
  1725. enable);
  1726. return rc;
  1727. }
  1728. display_for_each_ctrl(i, display) {
  1729. ctrl = &display->ctrl[i];
  1730. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1731. continue;
  1732. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1733. if (rc) {
  1734. DSI_ERR("Ulps controller state change(%d) failed\n",
  1735. enable);
  1736. return rc;
  1737. }
  1738. }
  1739. }
  1740. display->ulps_enabled = enable;
  1741. return 0;
  1742. }
  1743. /**
  1744. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1745. * @dsi_display: DSI display handle.
  1746. * @enable: enable/disable clamping.
  1747. *
  1748. * Return: error code.
  1749. */
  1750. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1751. {
  1752. int rc = 0;
  1753. int i = 0;
  1754. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1755. bool ulps_enabled = false;
  1756. if (!display) {
  1757. DSI_ERR("Invalid params\n");
  1758. return -EINVAL;
  1759. }
  1760. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1761. ulps_enabled = display->ulps_enabled;
  1762. /*
  1763. * Clamp control can be either through the DSI controller or
  1764. * the DSI PHY depending on hardware variation
  1765. */
  1766. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1767. if (rc) {
  1768. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1769. return rc;
  1770. }
  1771. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1772. if (rc) {
  1773. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1774. return rc;
  1775. }
  1776. display_for_each_ctrl(i, display) {
  1777. ctrl = &display->ctrl[i];
  1778. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1779. continue;
  1780. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1781. if (rc) {
  1782. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1783. return rc;
  1784. }
  1785. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1786. if (rc) {
  1787. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1788. enable);
  1789. return rc;
  1790. }
  1791. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1792. enable ? "enabled" : "disabled", i);
  1793. }
  1794. display->clamp_enabled = enable;
  1795. return 0;
  1796. }
  1797. /**
  1798. * dsi_display_setup_ctrl() - setup DSI controller.
  1799. * @dsi_display: DSI display handle.
  1800. *
  1801. * Return: error code.
  1802. */
  1803. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1804. {
  1805. int rc = 0;
  1806. int i = 0;
  1807. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1808. if (!display) {
  1809. DSI_ERR("Invalid params\n");
  1810. return -EINVAL;
  1811. }
  1812. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1813. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1814. if (rc) {
  1815. DSI_ERR("DSI controller setup failed\n");
  1816. return rc;
  1817. }
  1818. display_for_each_ctrl(i, display) {
  1819. ctrl = &display->ctrl[i];
  1820. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1821. continue;
  1822. rc = dsi_ctrl_setup(ctrl->ctrl);
  1823. if (rc) {
  1824. DSI_ERR("DSI controller setup failed\n");
  1825. return rc;
  1826. }
  1827. }
  1828. return 0;
  1829. }
  1830. static int dsi_display_phy_enable(struct dsi_display *display);
  1831. /**
  1832. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1833. * @dsi_display: DSI display handle.
  1834. * @mmss_clamp: True if clamp is enabled.
  1835. *
  1836. * Return: error code.
  1837. */
  1838. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1839. bool mmss_clamp)
  1840. {
  1841. int rc = 0;
  1842. int i = 0;
  1843. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1844. if (!display) {
  1845. DSI_ERR("Invalid params\n");
  1846. return -EINVAL;
  1847. }
  1848. if (mmss_clamp && !display->phy_idle_power_off) {
  1849. dsi_display_phy_enable(display);
  1850. return 0;
  1851. }
  1852. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1853. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1854. if (rc) {
  1855. DSI_ERR("DSI controller setup failed\n");
  1856. return rc;
  1857. }
  1858. display_for_each_ctrl(i, display) {
  1859. ctrl = &display->ctrl[i];
  1860. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1861. continue;
  1862. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1863. if (rc) {
  1864. DSI_ERR("DSI controller setup failed\n");
  1865. return rc;
  1866. }
  1867. }
  1868. display->phy_idle_power_off = false;
  1869. return 0;
  1870. }
  1871. /**
  1872. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1873. * @dsi_display: DSI display handle.
  1874. *
  1875. * Return: error code.
  1876. */
  1877. static int dsi_display_phy_idle_off(struct dsi_display *display)
  1878. {
  1879. int rc = 0;
  1880. int i = 0;
  1881. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1882. if (!display) {
  1883. DSI_ERR("Invalid params\n");
  1884. return -EINVAL;
  1885. }
  1886. display_for_each_ctrl(i, display) {
  1887. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1888. if (!phy)
  1889. continue;
  1890. if (!phy->allow_phy_power_off) {
  1891. DSI_DEBUG("phy doesn't support this feature\n");
  1892. return 0;
  1893. }
  1894. }
  1895. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1896. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  1897. if (rc) {
  1898. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  1899. display->name, rc);
  1900. return rc;
  1901. }
  1902. display_for_each_ctrl(i, display) {
  1903. ctrl = &display->ctrl[i];
  1904. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1905. continue;
  1906. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  1907. if (rc) {
  1908. DSI_ERR("DSI controller setup failed\n");
  1909. return rc;
  1910. }
  1911. }
  1912. display->phy_idle_power_off = true;
  1913. return 0;
  1914. }
  1915. void dsi_display_enable_event(struct drm_connector *connector,
  1916. struct dsi_display *display,
  1917. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  1918. bool enable)
  1919. {
  1920. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  1921. int i;
  1922. if (!display) {
  1923. DSI_ERR("invalid display\n");
  1924. return;
  1925. }
  1926. if (event_info)
  1927. event_info->event_idx = event_idx;
  1928. switch (event_idx) {
  1929. case SDE_CONN_EVENT_VID_DONE:
  1930. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  1931. break;
  1932. case SDE_CONN_EVENT_CMD_DONE:
  1933. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  1934. break;
  1935. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  1936. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  1937. if (event_info) {
  1938. display_for_each_ctrl(i, display)
  1939. display->ctrl[i].ctrl->recovery_cb =
  1940. *event_info;
  1941. }
  1942. break;
  1943. case SDE_CONN_EVENT_PANEL_ID:
  1944. if (event_info)
  1945. display_for_each_ctrl(i, display)
  1946. display->ctrl[i].ctrl->panel_id_cb
  1947. = *event_info;
  1948. break;
  1949. default:
  1950. /* nothing to do */
  1951. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  1952. return;
  1953. }
  1954. if (enable) {
  1955. display_for_each_ctrl(i, display)
  1956. dsi_ctrl_enable_status_interrupt(
  1957. display->ctrl[i].ctrl, irq_status_idx,
  1958. event_info);
  1959. } else {
  1960. display_for_each_ctrl(i, display)
  1961. dsi_ctrl_disable_status_interrupt(
  1962. display->ctrl[i].ctrl, irq_status_idx);
  1963. }
  1964. }
  1965. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  1966. {
  1967. int rc = 0;
  1968. int i;
  1969. struct dsi_display_ctrl *ctrl;
  1970. /* Sequence does not matter for split dsi usecases */
  1971. display_for_each_ctrl(i, display) {
  1972. ctrl = &display->ctrl[i];
  1973. if (!ctrl->ctrl)
  1974. continue;
  1975. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  1976. DSI_CTRL_POWER_VREG_ON);
  1977. if (rc) {
  1978. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  1979. ctrl->ctrl->name, rc);
  1980. goto error;
  1981. }
  1982. }
  1983. return rc;
  1984. error:
  1985. for (i = i - 1; i >= 0; i--) {
  1986. ctrl = &display->ctrl[i];
  1987. if (!ctrl->ctrl)
  1988. continue;
  1989. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  1990. DSI_CTRL_POWER_VREG_OFF);
  1991. }
  1992. return rc;
  1993. }
  1994. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  1995. {
  1996. int rc = 0;
  1997. int i;
  1998. struct dsi_display_ctrl *ctrl;
  1999. /* Sequence does not matter for split dsi usecases */
  2000. display_for_each_ctrl(i, display) {
  2001. ctrl = &display->ctrl[i];
  2002. if (!ctrl->ctrl)
  2003. continue;
  2004. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2005. DSI_CTRL_POWER_VREG_OFF);
  2006. if (rc) {
  2007. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2008. ctrl->ctrl->name, rc);
  2009. goto error;
  2010. }
  2011. }
  2012. error:
  2013. return rc;
  2014. }
  2015. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2016. unsigned int display_type)
  2017. {
  2018. char *boot_str = NULL;
  2019. char *str = NULL;
  2020. char *sw_te = NULL;
  2021. unsigned long cmdline_topology = NO_OVERRIDE;
  2022. unsigned long cmdline_timing = NO_OVERRIDE;
  2023. unsigned long panel_id = NO_OVERRIDE;
  2024. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2025. DSI_ERR("display_type=%d not supported\n", display_type);
  2026. goto end;
  2027. }
  2028. if (display_type == DSI_PRIMARY)
  2029. boot_str = dsi_display_primary;
  2030. else
  2031. boot_str = dsi_display_secondary;
  2032. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2033. if (sw_te)
  2034. display->sw_te_using_wd = true;
  2035. str = strnstr(boot_str, ":panelid", strlen(boot_str));
  2036. if (str) {
  2037. if (kstrtol(str + strlen(":panelid"), INT_BASE_10,
  2038. (unsigned long *)&panel_id)) {
  2039. DSI_INFO("panel id not found: %s\n", boot_str);
  2040. } else {
  2041. DSI_INFO("panel id found: %lx\n", panel_id);
  2042. display->panel_id = panel_id;
  2043. }
  2044. }
  2045. str = strnstr(boot_str, ":config", strlen(boot_str));
  2046. if (str) {
  2047. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2048. DSI_ERR("invalid config index override: %s\n",
  2049. boot_str);
  2050. goto end;
  2051. }
  2052. }
  2053. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2054. if (str) {
  2055. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2056. DSI_ERR("invalid timing index override: %s\n",
  2057. boot_str);
  2058. cmdline_topology = NO_OVERRIDE;
  2059. goto end;
  2060. }
  2061. }
  2062. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2063. end:
  2064. display->cmdline_topology = cmdline_topology;
  2065. display->cmdline_timing = cmdline_timing;
  2066. }
  2067. /**
  2068. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2069. *
  2070. * Return: returns error status
  2071. */
  2072. static int dsi_display_parse_boot_display_selection(void)
  2073. {
  2074. char *pos = NULL;
  2075. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2076. int i, j;
  2077. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2078. strlcpy(disp_buf, boot_displays[i].boot_param,
  2079. MAX_CMDLINE_PARAM_LEN);
  2080. pos = strnstr(disp_buf, ":", MAX_CMDLINE_PARAM_LEN);
  2081. /* Use ':' as a delimiter to retrieve the display name */
  2082. if (!pos) {
  2083. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2084. continue;
  2085. }
  2086. for (j = 0; (disp_buf + j) < pos; j++)
  2087. boot_displays[i].name[j] = *(disp_buf + j);
  2088. boot_displays[i].name[j] = '\0';
  2089. boot_displays[i].boot_disp_en = true;
  2090. }
  2091. return 0;
  2092. }
  2093. static int dsi_display_phy_power_on(struct dsi_display *display)
  2094. {
  2095. int rc = 0;
  2096. int i;
  2097. struct dsi_display_ctrl *ctrl;
  2098. /* Sequence does not matter for split dsi usecases */
  2099. display_for_each_ctrl(i, display) {
  2100. ctrl = &display->ctrl[i];
  2101. if (!ctrl->ctrl)
  2102. continue;
  2103. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2104. if (rc) {
  2105. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2106. ctrl->phy->name, rc);
  2107. goto error;
  2108. }
  2109. }
  2110. return rc;
  2111. error:
  2112. for (i = i - 1; i >= 0; i--) {
  2113. ctrl = &display->ctrl[i];
  2114. if (!ctrl->phy)
  2115. continue;
  2116. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2117. }
  2118. return rc;
  2119. }
  2120. static int dsi_display_phy_power_off(struct dsi_display *display)
  2121. {
  2122. int rc = 0;
  2123. int i;
  2124. struct dsi_display_ctrl *ctrl;
  2125. /* Sequence does not matter for split dsi usecases */
  2126. display_for_each_ctrl(i, display) {
  2127. ctrl = &display->ctrl[i];
  2128. if (!ctrl->phy)
  2129. continue;
  2130. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2131. if (rc) {
  2132. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2133. ctrl->ctrl->name, rc);
  2134. goto error;
  2135. }
  2136. }
  2137. error:
  2138. return rc;
  2139. }
  2140. static int dsi_display_set_clk_src(struct dsi_display *display)
  2141. {
  2142. int rc = 0;
  2143. int i;
  2144. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2145. /*
  2146. * For CPHY mode, the parent of mux_clks need to be set
  2147. * to Cphy_clks to have correct dividers for byte and
  2148. * pixel clocks.
  2149. */
  2150. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {
  2151. rc = dsi_clk_update_parent(&display->clock_info.cphy_clks,
  2152. &display->clock_info.mux_clks);
  2153. if (rc) {
  2154. DSI_ERR("failed update mux parent to shadow\n");
  2155. return rc;
  2156. }
  2157. }
  2158. /*
  2159. * In case of split DSI usecases, the clock for master controller should
  2160. * be enabled before the other controller. Master controller in the
  2161. * clock context refers to the controller that sources the clock.
  2162. */
  2163. m_ctrl = &display->ctrl[display->clk_master_idx];
  2164. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
  2165. &display->clock_info.mux_clks);
  2166. if (rc) {
  2167. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n",
  2168. display->name, rc);
  2169. return rc;
  2170. }
  2171. /* Turn on rest of the controllers */
  2172. display_for_each_ctrl(i, display) {
  2173. ctrl = &display->ctrl[i];
  2174. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2175. continue;
  2176. rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
  2177. &display->clock_info.mux_clks);
  2178. if (rc) {
  2179. DSI_ERR("[%s] failed to set source clocks, rc=%d\n",
  2180. display->name, rc);
  2181. return rc;
  2182. }
  2183. }
  2184. return 0;
  2185. }
  2186. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2187. bool enable)
  2188. {
  2189. int rc = 0;
  2190. int i;
  2191. struct dsi_display_ctrl *ctrl;
  2192. display_for_each_ctrl(i, display) {
  2193. ctrl = &display->ctrl[i];
  2194. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2195. if (rc) {
  2196. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2197. display->name, enable ? "mask" : "unmask", rc);
  2198. return rc;
  2199. }
  2200. }
  2201. return 0;
  2202. }
  2203. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2204. {
  2205. struct dsi_display_ctrl *ctrl;
  2206. int i;
  2207. if (!display)
  2208. return;
  2209. display_for_each_ctrl(i, display) {
  2210. ctrl = &display->ctrl[i];
  2211. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2212. }
  2213. /*
  2214. * After retime buffer synchronization we need to turn of clk_en_sel
  2215. * bit on each phy. Avoid this for Cphy.
  2216. */
  2217. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2218. return;
  2219. display_for_each_ctrl(i, display) {
  2220. ctrl = &display->ctrl[i];
  2221. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2222. }
  2223. }
  2224. static int dsi_display_ctrl_update(struct dsi_display *display)
  2225. {
  2226. int rc = 0;
  2227. int i;
  2228. struct dsi_display_ctrl *ctrl;
  2229. display_for_each_ctrl(i, display) {
  2230. ctrl = &display->ctrl[i];
  2231. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2232. if (rc) {
  2233. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2234. display->name, i, rc);
  2235. goto error_host_deinit;
  2236. }
  2237. }
  2238. return 0;
  2239. error_host_deinit:
  2240. for (i = i - 1; i >= 0; i--) {
  2241. ctrl = &display->ctrl[i];
  2242. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2243. }
  2244. return rc;
  2245. }
  2246. static int dsi_display_ctrl_init(struct dsi_display *display)
  2247. {
  2248. int rc = 0;
  2249. int i;
  2250. struct dsi_display_ctrl *ctrl;
  2251. bool skip_op = is_skip_op_required(display);
  2252. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2253. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2254. * we will programe DSI controller as part of core clock enable.
  2255. * After that we should not re-configure DSI controller again here for
  2256. * usecases where we are resuming from ulps suspend as it might put
  2257. * the HW in bad state.
  2258. */
  2259. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2260. display_for_each_ctrl(i, display) {
  2261. ctrl = &display->ctrl[i];
  2262. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2263. if (rc) {
  2264. DSI_ERR(
  2265. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2266. display->name, i, skip_op, rc);
  2267. goto error_host_deinit;
  2268. }
  2269. }
  2270. } else {
  2271. display_for_each_ctrl(i, display) {
  2272. ctrl = &display->ctrl[i];
  2273. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2274. DSI_CTRL_OP_HOST_INIT,
  2275. true);
  2276. if (rc)
  2277. DSI_DEBUG("host init update failed rc=%d\n",
  2278. rc);
  2279. }
  2280. }
  2281. return rc;
  2282. error_host_deinit:
  2283. for (i = i - 1; i >= 0; i--) {
  2284. ctrl = &display->ctrl[i];
  2285. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2286. }
  2287. return rc;
  2288. }
  2289. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2290. {
  2291. int rc = 0;
  2292. int i;
  2293. struct dsi_display_ctrl *ctrl;
  2294. display_for_each_ctrl(i, display) {
  2295. ctrl = &display->ctrl[i];
  2296. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2297. if (rc) {
  2298. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2299. display->name, i, rc);
  2300. }
  2301. }
  2302. return rc;
  2303. }
  2304. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2305. {
  2306. int rc = 0;
  2307. int i;
  2308. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2309. bool skip_op = is_skip_op_required(display);
  2310. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2311. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2312. DSI_CTRL_ENGINE_ON, skip_op);
  2313. if (rc) {
  2314. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2315. display->name, skip_op, rc);
  2316. goto error;
  2317. }
  2318. display_for_each_ctrl(i, display) {
  2319. ctrl = &display->ctrl[i];
  2320. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2321. continue;
  2322. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2323. DSI_CTRL_ENGINE_ON, skip_op);
  2324. if (rc) {
  2325. DSI_ERR(
  2326. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2327. display->name, skip_op, rc);
  2328. goto error_disable_master;
  2329. }
  2330. }
  2331. return rc;
  2332. error_disable_master:
  2333. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2334. DSI_CTRL_ENGINE_OFF, skip_op);
  2335. error:
  2336. return rc;
  2337. }
  2338. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2339. {
  2340. int rc = 0;
  2341. int i;
  2342. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2343. bool skip_op = is_skip_op_required(display);
  2344. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2345. /*
  2346. * For platforms where ULPS is controlled by DSI controller block,
  2347. * do not disable dsi controller block if lanes are to be
  2348. * kept in ULPS during suspend. So just update the SW state
  2349. * and return early.
  2350. */
  2351. if (display->panel->ulps_suspend_enabled &&
  2352. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2353. display_for_each_ctrl(i, display) {
  2354. ctrl = &display->ctrl[i];
  2355. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2356. DSI_CTRL_OP_HOST_ENGINE,
  2357. false);
  2358. if (rc)
  2359. DSI_DEBUG("host state update failed %d\n", rc);
  2360. }
  2361. return rc;
  2362. }
  2363. display_for_each_ctrl(i, display) {
  2364. ctrl = &display->ctrl[i];
  2365. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2366. continue;
  2367. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2368. DSI_CTRL_ENGINE_OFF, skip_op);
  2369. if (rc)
  2370. DSI_ERR(
  2371. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2372. display->name, skip_op, rc);
  2373. }
  2374. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2375. DSI_CTRL_ENGINE_OFF, skip_op);
  2376. if (rc) {
  2377. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2378. display->name, skip_op, rc);
  2379. goto error;
  2380. }
  2381. error:
  2382. return rc;
  2383. }
  2384. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2385. {
  2386. int rc = 0;
  2387. int i;
  2388. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2389. bool skip_op = is_skip_op_required(display);
  2390. m_ctrl = &display->ctrl[display->video_master_idx];
  2391. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2392. DSI_CTRL_ENGINE_ON, skip_op);
  2393. if (rc) {
  2394. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2395. display->name, skip_op, rc);
  2396. goto error;
  2397. }
  2398. display_for_each_ctrl(i, display) {
  2399. ctrl = &display->ctrl[i];
  2400. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2401. continue;
  2402. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2403. DSI_CTRL_ENGINE_ON, skip_op);
  2404. if (rc) {
  2405. DSI_ERR(
  2406. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2407. display->name, skip_op, rc);
  2408. goto error_disable_master;
  2409. }
  2410. }
  2411. return rc;
  2412. error_disable_master:
  2413. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2414. DSI_CTRL_ENGINE_OFF, skip_op);
  2415. error:
  2416. return rc;
  2417. }
  2418. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2419. {
  2420. int rc = 0;
  2421. int i;
  2422. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2423. bool skip_op = is_skip_op_required(display);
  2424. m_ctrl = &display->ctrl[display->video_master_idx];
  2425. display_for_each_ctrl(i, display) {
  2426. ctrl = &display->ctrl[i];
  2427. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2428. continue;
  2429. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2430. DSI_CTRL_ENGINE_OFF, skip_op);
  2431. if (rc)
  2432. DSI_ERR(
  2433. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2434. display->name, skip_op, rc);
  2435. }
  2436. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2437. DSI_CTRL_ENGINE_OFF, skip_op);
  2438. if (rc)
  2439. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2440. display->name, skip_op, rc);
  2441. return rc;
  2442. }
  2443. static int dsi_display_phy_enable(struct dsi_display *display)
  2444. {
  2445. int rc = 0;
  2446. int i;
  2447. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2448. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2449. bool skip_op = is_skip_op_required(display);
  2450. m_ctrl = &display->ctrl[display->clk_master_idx];
  2451. if (display->ctrl_count > 1)
  2452. m_src = DSI_PLL_SOURCE_NATIVE;
  2453. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2454. m_src, true, skip_op);
  2455. if (rc) {
  2456. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2457. display->name, skip_op, rc);
  2458. goto error;
  2459. }
  2460. display_for_each_ctrl(i, display) {
  2461. ctrl = &display->ctrl[i];
  2462. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2463. continue;
  2464. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2465. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2466. if (rc) {
  2467. DSI_ERR(
  2468. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2469. display->name, skip_op, rc);
  2470. goto error_disable_master;
  2471. }
  2472. }
  2473. return rc;
  2474. error_disable_master:
  2475. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2476. error:
  2477. return rc;
  2478. }
  2479. static int dsi_display_phy_disable(struct dsi_display *display)
  2480. {
  2481. int rc = 0;
  2482. int i;
  2483. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2484. bool skip_op = is_skip_op_required(display);
  2485. m_ctrl = &display->ctrl[display->clk_master_idx];
  2486. display_for_each_ctrl(i, display) {
  2487. ctrl = &display->ctrl[i];
  2488. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2489. continue;
  2490. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2491. if (rc)
  2492. DSI_ERR(
  2493. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2494. display->name, skip_op, rc);
  2495. }
  2496. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2497. if (rc)
  2498. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2499. display->name, skip_op, rc);
  2500. return rc;
  2501. }
  2502. static int dsi_display_wake_up(struct dsi_display *display)
  2503. {
  2504. return 0;
  2505. }
  2506. static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags,
  2507. bool enable)
  2508. {
  2509. struct dsi_display_ctrl *ctrl;
  2510. int i;
  2511. if (!(flags & DSI_CTRL_CMD_LAST_COMMAND))
  2512. return;
  2513. display_for_each_ctrl(i, display) {
  2514. ctrl = &display->ctrl[i];
  2515. if (!ctrl)
  2516. continue;
  2517. dsi_ctrl_mask_overflow(ctrl->ctrl, enable);
  2518. }
  2519. }
  2520. static int dsi_display_broadcast_cmd(struct dsi_display *display,
  2521. const struct mipi_dsi_msg *msg)
  2522. {
  2523. int rc = 0;
  2524. u32 flags, m_flags;
  2525. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2526. int i;
  2527. m_flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_BROADCAST_MASTER |
  2528. DSI_CTRL_CMD_DEFER_TRIGGER | DSI_CTRL_CMD_FETCH_MEMORY);
  2529. flags = (DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER |
  2530. DSI_CTRL_CMD_FETCH_MEMORY);
  2531. if ((msg->flags & MIPI_DSI_MSG_LASTCOMMAND)) {
  2532. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2533. m_flags |= DSI_CTRL_CMD_LAST_COMMAND;
  2534. }
  2535. if ((msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  2536. (display->panel->panel_initialized)) {
  2537. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2538. m_flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2539. }
  2540. if (display->queue_cmd_waits ||
  2541. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE) {
  2542. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2543. m_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2544. }
  2545. /*
  2546. * 1. Setup commands in FIFO
  2547. * 2. Trigger commands
  2548. */
  2549. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2550. dsi_display_mask_overflow(display, m_flags, true);
  2551. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, &m_flags);
  2552. if (rc) {
  2553. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2554. display->name, rc);
  2555. goto error;
  2556. }
  2557. display_for_each_ctrl(i, display) {
  2558. ctrl = &display->ctrl[i];
  2559. if (ctrl == m_ctrl)
  2560. continue;
  2561. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, msg, &flags);
  2562. if (rc) {
  2563. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2564. display->name, rc);
  2565. goto error;
  2566. }
  2567. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, flags);
  2568. if (rc) {
  2569. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2570. display->name, rc);
  2571. goto error;
  2572. }
  2573. }
  2574. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, m_flags);
  2575. if (rc) {
  2576. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2577. display->name, rc);
  2578. goto error;
  2579. }
  2580. error:
  2581. dsi_display_mask_overflow(display, m_flags, false);
  2582. return rc;
  2583. }
  2584. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2585. {
  2586. int rc = 0;
  2587. int i;
  2588. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2589. /*
  2590. * For continuous splash and trusted vm environment,
  2591. * ctrl states are updated separately and hence we do
  2592. * an early return
  2593. */
  2594. if (is_skip_op_required(display)) {
  2595. DSI_DEBUG(
  2596. "cont splash/trusted vm use case, phy sw reset not required\n");
  2597. return 0;
  2598. }
  2599. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2600. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2601. if (rc) {
  2602. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2603. goto error;
  2604. }
  2605. display_for_each_ctrl(i, display) {
  2606. ctrl = &display->ctrl[i];
  2607. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2608. continue;
  2609. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2610. if (rc) {
  2611. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2612. display->name, rc);
  2613. goto error;
  2614. }
  2615. }
  2616. error:
  2617. return rc;
  2618. }
  2619. static int dsi_host_attach(struct mipi_dsi_host *host,
  2620. struct mipi_dsi_device *dsi)
  2621. {
  2622. return 0;
  2623. }
  2624. static int dsi_host_detach(struct mipi_dsi_host *host,
  2625. struct mipi_dsi_device *dsi)
  2626. {
  2627. return 0;
  2628. }
  2629. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
  2630. const struct mipi_dsi_msg *msg)
  2631. {
  2632. struct dsi_display *display;
  2633. int rc = 0, ret = 0;
  2634. if (!host || !msg) {
  2635. DSI_ERR("Invalid params\n");
  2636. return 0;
  2637. }
  2638. display = to_dsi_display(host);
  2639. /* Avoid sending DCS commands when ESD recovery is pending */
  2640. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2641. DSI_DEBUG("ESD recovery pending\n");
  2642. return 0;
  2643. }
  2644. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2645. DSI_ALL_CLKS, DSI_CLK_ON);
  2646. if (rc) {
  2647. DSI_ERR("[%s] failed to enable all DSI clocks, rc=%d\n",
  2648. display->name, rc);
  2649. goto error;
  2650. }
  2651. rc = dsi_display_wake_up(display);
  2652. if (rc) {
  2653. DSI_ERR("[%s] failed to wake up display, rc=%d\n",
  2654. display->name, rc);
  2655. goto error_disable_clks;
  2656. }
  2657. rc = dsi_display_cmd_engine_enable(display);
  2658. if (rc) {
  2659. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  2660. display->name, rc);
  2661. goto error_disable_clks;
  2662. }
  2663. if (display->tx_cmd_buf == NULL) {
  2664. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2665. if (rc) {
  2666. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2667. goto error_disable_cmd_engine;
  2668. }
  2669. }
  2670. if (display->ctrl_count > 1 && !(msg->flags & MIPI_DSI_MSG_UNICAST)) {
  2671. rc = dsi_display_broadcast_cmd(display, msg);
  2672. if (rc) {
  2673. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n",
  2674. display->name, rc);
  2675. goto error_disable_cmd_engine;
  2676. }
  2677. } else {
  2678. int ctrl_idx = (msg->flags & MIPI_DSI_MSG_UNICAST) ?
  2679. msg->ctrl : 0;
  2680. u32 cmd_flags = DSI_CTRL_CMD_FETCH_MEMORY;
  2681. if (display->queue_cmd_waits ||
  2682. msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  2683. cmd_flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  2684. if ((msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED) &&
  2685. (display->panel->panel_initialized))
  2686. cmd_flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  2687. rc = dsi_ctrl_cmd_transfer(display->ctrl[ctrl_idx].ctrl, msg,
  2688. &cmd_flags);
  2689. if (rc) {
  2690. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2691. display->name, rc);
  2692. goto error_disable_cmd_engine;
  2693. }
  2694. }
  2695. error_disable_cmd_engine:
  2696. ret = dsi_display_cmd_engine_disable(display);
  2697. if (ret) {
  2698. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  2699. display->name, ret);
  2700. }
  2701. error_disable_clks:
  2702. ret = dsi_display_clk_ctrl(display->dsi_clk_handle,
  2703. DSI_ALL_CLKS, DSI_CLK_OFF);
  2704. if (ret) {
  2705. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  2706. display->name, ret);
  2707. }
  2708. error:
  2709. return rc;
  2710. }
  2711. static struct mipi_dsi_host_ops dsi_host_ops = {
  2712. .attach = dsi_host_attach,
  2713. .detach = dsi_host_detach,
  2714. .transfer = dsi_host_transfer,
  2715. };
  2716. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2717. {
  2718. int rc = 0;
  2719. struct mipi_dsi_host *host = &display->host;
  2720. host->dev = &display->pdev->dev;
  2721. host->ops = &dsi_host_ops;
  2722. rc = mipi_dsi_host_register(host);
  2723. if (rc) {
  2724. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2725. display->name, rc);
  2726. goto error;
  2727. }
  2728. error:
  2729. return rc;
  2730. }
  2731. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2732. {
  2733. int rc = 0;
  2734. struct mipi_dsi_host *host = &display->host;
  2735. mipi_dsi_host_unregister(host);
  2736. host->dev = NULL;
  2737. host->ops = NULL;
  2738. return rc;
  2739. }
  2740. static int dsi_display_clocks_deinit(struct dsi_display *display)
  2741. {
  2742. int rc = 0;
  2743. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2744. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2745. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2746. if (src->byte_clk) {
  2747. devm_clk_put(&display->pdev->dev, src->byte_clk);
  2748. src->byte_clk = NULL;
  2749. }
  2750. if (src->pixel_clk) {
  2751. devm_clk_put(&display->pdev->dev, src->pixel_clk);
  2752. src->pixel_clk = NULL;
  2753. }
  2754. if (mux->byte_clk) {
  2755. devm_clk_put(&display->pdev->dev, mux->byte_clk);
  2756. mux->byte_clk = NULL;
  2757. }
  2758. if (mux->pixel_clk) {
  2759. devm_clk_put(&display->pdev->dev, mux->pixel_clk);
  2760. mux->pixel_clk = NULL;
  2761. }
  2762. if (shadow->byte_clk) {
  2763. devm_clk_put(&display->pdev->dev, shadow->byte_clk);
  2764. shadow->byte_clk = NULL;
  2765. }
  2766. if (shadow->pixel_clk) {
  2767. devm_clk_put(&display->pdev->dev, shadow->pixel_clk);
  2768. shadow->pixel_clk = NULL;
  2769. }
  2770. return rc;
  2771. }
  2772. static bool dsi_display_check_prefix(const char *clk_prefix,
  2773. const char *clk_name)
  2774. {
  2775. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2776. }
  2777. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2778. char *dsi_clk_name)
  2779. {
  2780. if (display->fw)
  2781. return dsi_parser_count_strings(display->parser_node,
  2782. dsi_clk_name);
  2783. else
  2784. return of_property_count_strings(display->panel_node,
  2785. dsi_clk_name);
  2786. }
  2787. static void dsi_display_get_clock_name(struct dsi_display *display,
  2788. char *dsi_clk_name, int index,
  2789. const char **clk_name)
  2790. {
  2791. if (display->fw)
  2792. dsi_parser_read_string_index(display->parser_node,
  2793. dsi_clk_name, index, clk_name);
  2794. else
  2795. of_property_read_string_index(display->panel_node,
  2796. dsi_clk_name, index, clk_name);
  2797. }
  2798. static int dsi_display_clocks_init(struct dsi_display *display)
  2799. {
  2800. int i, rc = 0, num_clk = 0;
  2801. const char *clk_name;
  2802. const char *src_byte = "src_byte", *src_pixel = "src_pixel";
  2803. const char *mux_byte = "mux_byte", *mux_pixel = "mux_pixel";
  2804. const char *cphy_byte = "cphy_byte", *cphy_pixel = "cphy_pixel";
  2805. const char *shadow_byte = "shadow_byte", *shadow_pixel = "shadow_pixel";
  2806. const char *shadow_cphybyte = "shadow_cphybyte",
  2807. *shadow_cphypixel = "shadow_cphypixel";
  2808. struct clk *dsi_clk;
  2809. struct dsi_clk_link_set *src = &display->clock_info.src_clks;
  2810. struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
  2811. struct dsi_clk_link_set *cphy = &display->clock_info.cphy_clks;
  2812. struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
  2813. struct dsi_clk_link_set *shadow_cphy =
  2814. &display->clock_info.shadow_cphy_clks;
  2815. struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);
  2816. char *dsi_clock_name;
  2817. if (!strcmp(display->display_type, "primary"))
  2818. dsi_clock_name = "qcom,dsi-select-clocks";
  2819. else
  2820. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2821. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2822. DSI_DEBUG("clk count=%d\n", num_clk);
  2823. for (i = 0; i < num_clk; i++) {
  2824. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2825. &clk_name);
  2826. DSI_DEBUG("clock name:%s\n", clk_name);
  2827. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2828. if (IS_ERR_OR_NULL(dsi_clk)) {
  2829. rc = PTR_ERR(dsi_clk);
  2830. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2831. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2832. mux->byte_clk = NULL;
  2833. goto error;
  2834. }
  2835. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2836. mux->pixel_clk = NULL;
  2837. goto error;
  2838. }
  2839. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2840. cphy->byte_clk = NULL;
  2841. goto error;
  2842. }
  2843. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2844. cphy->pixel_clk = NULL;
  2845. goto error;
  2846. }
  2847. if (dyn_clk_caps->dyn_clk_support &&
  2848. (display->panel->panel_mode ==
  2849. DSI_OP_VIDEO_MODE)) {
  2850. if (dsi_display_check_prefix(src_byte,
  2851. clk_name))
  2852. src->byte_clk = NULL;
  2853. if (dsi_display_check_prefix(src_pixel,
  2854. clk_name))
  2855. src->pixel_clk = NULL;
  2856. if (dsi_display_check_prefix(shadow_byte,
  2857. clk_name))
  2858. shadow->byte_clk = NULL;
  2859. if (dsi_display_check_prefix(shadow_pixel,
  2860. clk_name))
  2861. shadow->pixel_clk = NULL;
  2862. if (dsi_display_check_prefix(shadow_cphybyte,
  2863. clk_name))
  2864. shadow_cphy->byte_clk = NULL;
  2865. if (dsi_display_check_prefix(shadow_cphypixel,
  2866. clk_name))
  2867. shadow_cphy->pixel_clk = NULL;
  2868. dyn_clk_caps->dyn_clk_support = false;
  2869. }
  2870. }
  2871. if (dsi_display_check_prefix(src_byte, clk_name)) {
  2872. src->byte_clk = dsi_clk;
  2873. continue;
  2874. }
  2875. if (dsi_display_check_prefix(src_pixel, clk_name)) {
  2876. src->pixel_clk = dsi_clk;
  2877. continue;
  2878. }
  2879. if (dsi_display_check_prefix(cphy_byte, clk_name)) {
  2880. cphy->byte_clk = dsi_clk;
  2881. continue;
  2882. }
  2883. if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
  2884. cphy->pixel_clk = dsi_clk;
  2885. continue;
  2886. }
  2887. if (dsi_display_check_prefix(mux_byte, clk_name)) {
  2888. mux->byte_clk = dsi_clk;
  2889. continue;
  2890. }
  2891. if (dsi_display_check_prefix(mux_pixel, clk_name)) {
  2892. mux->pixel_clk = dsi_clk;
  2893. continue;
  2894. }
  2895. if (dsi_display_check_prefix(shadow_byte, clk_name)) {
  2896. shadow->byte_clk = dsi_clk;
  2897. continue;
  2898. }
  2899. if (dsi_display_check_prefix(shadow_pixel, clk_name)) {
  2900. shadow->pixel_clk = dsi_clk;
  2901. continue;
  2902. }
  2903. if (dsi_display_check_prefix(shadow_cphybyte, clk_name)) {
  2904. shadow_cphy->byte_clk = dsi_clk;
  2905. continue;
  2906. }
  2907. if (dsi_display_check_prefix(shadow_cphypixel, clk_name)) {
  2908. shadow_cphy->pixel_clk = dsi_clk;
  2909. continue;
  2910. }
  2911. }
  2912. return 0;
  2913. error:
  2914. (void)dsi_display_clocks_deinit(display);
  2915. return rc;
  2916. }
  2917. static int dsi_display_clk_ctrl_cb(void *priv,
  2918. struct dsi_clk_ctrl_info clk_state_info)
  2919. {
  2920. int rc = 0;
  2921. struct dsi_display *display = NULL;
  2922. void *clk_handle = NULL;
  2923. if (!priv) {
  2924. DSI_ERR("Invalid params\n");
  2925. return -EINVAL;
  2926. }
  2927. display = priv;
  2928. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2929. clk_handle = display->mdp_clk_handle;
  2930. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2931. clk_handle = display->dsi_clk_handle;
  2932. } else {
  2933. DSI_ERR("invalid clk handle, return error\n");
  2934. return -EINVAL;
  2935. }
  2936. /*
  2937. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2938. * to turn off DSI clocks.
  2939. */
  2940. rc = dsi_display_clk_ctrl(clk_handle,
  2941. clk_state_info.clk_type, clk_state_info.clk_state);
  2942. if (rc) {
  2943. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2944. display->name, clk_state_info.clk_state,
  2945. clk_state_info.clk_type, rc);
  2946. return rc;
  2947. }
  2948. return 0;
  2949. }
  2950. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2951. {
  2952. int i;
  2953. struct dsi_display_ctrl *ctrl;
  2954. if (!display)
  2955. return;
  2956. display_for_each_ctrl(i, display) {
  2957. ctrl = &display->ctrl[i];
  2958. if (!ctrl)
  2959. continue;
  2960. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  2961. }
  2962. }
  2963. int dsi_pre_clkoff_cb(void *priv,
  2964. enum dsi_clk_type clk,
  2965. enum dsi_lclk_type l_type,
  2966. enum dsi_clk_state new_state)
  2967. {
  2968. int rc = 0, i;
  2969. struct dsi_display *display = priv;
  2970. struct dsi_display_ctrl *ctrl;
  2971. /*
  2972. * If Idle Power Collapse occurs immediately after a CMD
  2973. * transfer with an asynchronous wait for DMA done, ensure
  2974. * that the work queued is scheduled and completed before turning
  2975. * off the clocks and disabling interrupts to validate the command
  2976. * transfer.
  2977. */
  2978. display_for_each_ctrl(i, display) {
  2979. ctrl = &display->ctrl[i];
  2980. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  2981. continue;
  2982. flush_workqueue(display->dma_cmd_workq);
  2983. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  2984. ctrl->ctrl->dma_wait_queued = false;
  2985. }
  2986. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2987. (l_type & DSI_LINK_LP_CLK)) {
  2988. /*
  2989. * If continuous clock is enabled then disable it
  2990. * before entering into ULPS Mode.
  2991. */
  2992. if (display->panel->host_config.force_hs_clk_lane)
  2993. _dsi_display_continuous_clk_ctrl(display, false);
  2994. /*
  2995. * If ULPS feature is enabled, enter ULPS first.
  2996. * However, when blanking the panel, we should enter ULPS
  2997. * only if ULPS during suspend feature is enabled.
  2998. */
  2999. if (!dsi_panel_initialized(display->panel)) {
  3000. if (display->panel->ulps_suspend_enabled)
  3001. rc = dsi_display_set_ulps(display, true);
  3002. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  3003. rc = dsi_display_set_ulps(display, true);
  3004. }
  3005. if (rc)
  3006. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  3007. __func__, rc);
  3008. }
  3009. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  3010. (l_type & DSI_LINK_HS_CLK)) {
  3011. /*
  3012. * PHY clock gating should be disabled before the PLL and the
  3013. * branch clocks are turned off. Otherwise, it is possible that
  3014. * the clock RCGs may not be turned off correctly resulting
  3015. * in clock warnings.
  3016. */
  3017. rc = dsi_display_config_clk_gating(display, false);
  3018. if (rc)
  3019. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  3020. display->name, rc);
  3021. }
  3022. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3023. /*
  3024. * Enable DSI clamps only if entering idle power collapse or
  3025. * when ULPS during suspend is enabled..
  3026. */
  3027. if (dsi_panel_initialized(display->panel) ||
  3028. display->panel->ulps_suspend_enabled) {
  3029. dsi_display_phy_idle_off(display);
  3030. rc = dsi_display_set_clamp(display, true);
  3031. if (rc)
  3032. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3033. __func__, rc);
  3034. rc = dsi_display_phy_reset_config(display, false);
  3035. if (rc)
  3036. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3037. __func__, rc);
  3038. } else {
  3039. /* Make sure that controller is not in ULPS state when
  3040. * the DSI link is not active.
  3041. */
  3042. rc = dsi_display_set_ulps(display, false);
  3043. if (rc)
  3044. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3045. __func__, rc);
  3046. }
  3047. /* dsi will not be able to serve irqs from here on */
  3048. dsi_display_ctrl_irq_update(display, false);
  3049. /* cache the MISR values */
  3050. display_for_each_ctrl(i, display) {
  3051. ctrl = &display->ctrl[i];
  3052. if (!ctrl->ctrl)
  3053. continue;
  3054. dsi_ctrl_cache_misr(ctrl->ctrl);
  3055. }
  3056. }
  3057. return rc;
  3058. }
  3059. int dsi_post_clkon_cb(void *priv,
  3060. enum dsi_clk_type clk,
  3061. enum dsi_lclk_type l_type,
  3062. enum dsi_clk_state curr_state)
  3063. {
  3064. int rc = 0;
  3065. struct dsi_display *display = priv;
  3066. bool mmss_clamp = false;
  3067. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3068. mmss_clamp = display->clamp_enabled;
  3069. /*
  3070. * controller setup is needed if coming out of idle
  3071. * power collapse with clamps enabled.
  3072. */
  3073. if (mmss_clamp)
  3074. dsi_display_ctrl_setup(display);
  3075. /*
  3076. * Phy setup is needed if coming out of idle
  3077. * power collapse with clamps enabled.
  3078. */
  3079. if (display->phy_idle_power_off || mmss_clamp)
  3080. dsi_display_phy_idle_on(display, mmss_clamp);
  3081. if (display->ulps_enabled && mmss_clamp) {
  3082. /*
  3083. * ULPS Entry Request. This is needed if the lanes were
  3084. * in ULPS prior to power collapse, since after
  3085. * power collapse and reset, the DSI controller resets
  3086. * back to idle state and not ULPS. This ulps entry
  3087. * request will transition the state of the DSI
  3088. * controller to ULPS which will match the state of the
  3089. * DSI phy. This needs to be done prior to disabling
  3090. * the DSI clamps.
  3091. *
  3092. * Also, reset the ulps flag so that ulps_config
  3093. * function would reconfigure the controller state to
  3094. * ULPS.
  3095. */
  3096. display->ulps_enabled = false;
  3097. rc = dsi_display_set_ulps(display, true);
  3098. if (rc) {
  3099. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3100. __func__, rc);
  3101. goto error;
  3102. }
  3103. }
  3104. rc = dsi_display_phy_reset_config(display, true);
  3105. if (rc) {
  3106. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3107. __func__, rc);
  3108. goto error;
  3109. }
  3110. rc = dsi_display_set_clamp(display, false);
  3111. if (rc) {
  3112. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3113. __func__, rc);
  3114. goto error;
  3115. }
  3116. }
  3117. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3118. /*
  3119. * Toggle the resync FIFO everytime clock changes, except
  3120. * when cont-splash screen transition is going on.
  3121. * Toggling resync FIFO during cont splash transition
  3122. * can lead to blinks on the display.
  3123. */
  3124. if (!display->is_cont_splash_enabled)
  3125. dsi_display_toggle_resync_fifo(display);
  3126. if (display->ulps_enabled) {
  3127. rc = dsi_display_set_ulps(display, false);
  3128. if (rc) {
  3129. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3130. __func__, rc);
  3131. goto error;
  3132. }
  3133. }
  3134. if (display->panel->host_config.force_hs_clk_lane)
  3135. _dsi_display_continuous_clk_ctrl(display, true);
  3136. rc = dsi_display_config_clk_gating(display, true);
  3137. if (rc) {
  3138. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3139. display->name, rc);
  3140. goto error;
  3141. }
  3142. }
  3143. /* enable dsi to serve irqs */
  3144. if (clk & DSI_CORE_CLK)
  3145. dsi_display_ctrl_irq_update(display, true);
  3146. error:
  3147. return rc;
  3148. }
  3149. int dsi_post_clkoff_cb(void *priv,
  3150. enum dsi_clk_type clk_type,
  3151. enum dsi_lclk_type l_type,
  3152. enum dsi_clk_state curr_state)
  3153. {
  3154. int rc = 0;
  3155. struct dsi_display *display = priv;
  3156. if (!display) {
  3157. DSI_ERR("%s: Invalid arg\n", __func__);
  3158. return -EINVAL;
  3159. }
  3160. if ((clk_type & DSI_CORE_CLK) &&
  3161. (curr_state == DSI_CLK_OFF)) {
  3162. rc = dsi_display_phy_power_off(display);
  3163. if (rc)
  3164. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3165. display->name, rc);
  3166. rc = dsi_display_ctrl_power_off(display);
  3167. if (rc)
  3168. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3169. display->name, rc);
  3170. }
  3171. return rc;
  3172. }
  3173. int dsi_pre_clkon_cb(void *priv,
  3174. enum dsi_clk_type clk_type,
  3175. enum dsi_lclk_type l_type,
  3176. enum dsi_clk_state new_state)
  3177. {
  3178. int rc = 0;
  3179. struct dsi_display *display = priv;
  3180. if (!display) {
  3181. DSI_ERR("%s: invalid input\n", __func__);
  3182. return -EINVAL;
  3183. }
  3184. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3185. /*
  3186. * Enable DSI core power
  3187. * 1.> PANEL_PM are controlled as part of
  3188. * panel_power_ctrl. Needed not be handled here.
  3189. * 2.> CTRL_PM need to be enabled/disabled
  3190. * only during unblank/blank. Their state should
  3191. * not be changed during static screen.
  3192. */
  3193. DSI_DEBUG("updating power states for ctrl and phy\n");
  3194. rc = dsi_display_ctrl_power_on(display);
  3195. if (rc) {
  3196. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3197. display->name, rc);
  3198. return rc;
  3199. }
  3200. rc = dsi_display_phy_power_on(display);
  3201. if (rc) {
  3202. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3203. display->name, rc);
  3204. return rc;
  3205. }
  3206. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3207. }
  3208. return rc;
  3209. }
  3210. static void __set_lane_map_v2(u8 *lane_map_v2,
  3211. enum dsi_phy_data_lanes lane0,
  3212. enum dsi_phy_data_lanes lane1,
  3213. enum dsi_phy_data_lanes lane2,
  3214. enum dsi_phy_data_lanes lane3)
  3215. {
  3216. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3217. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3218. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3219. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3220. }
  3221. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3222. {
  3223. int rc = 0, i = 0;
  3224. const char *data;
  3225. u8 temp[DSI_LANE_MAX - 1];
  3226. if (!display) {
  3227. DSI_ERR("invalid params\n");
  3228. return -EINVAL;
  3229. }
  3230. /* lane-map-v2 supersedes lane-map-v1 setting */
  3231. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3232. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3233. if (!rc) {
  3234. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3235. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3236. return 0;
  3237. } else if (rc != EINVAL) {
  3238. DSI_DEBUG("Incorrect mapping, configure default\n");
  3239. goto set_default;
  3240. }
  3241. /* lane-map older version, for DSI controller version < 2.0 */
  3242. data = of_get_property(display->pdev->dev.of_node,
  3243. "qcom,lane-map", NULL);
  3244. if (!data)
  3245. goto set_default;
  3246. if (!strcmp(data, "lane_map_3012")) {
  3247. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3248. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3249. DSI_PHYSICAL_LANE_1,
  3250. DSI_PHYSICAL_LANE_2,
  3251. DSI_PHYSICAL_LANE_3,
  3252. DSI_PHYSICAL_LANE_0);
  3253. } else if (!strcmp(data, "lane_map_2301")) {
  3254. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3255. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3256. DSI_PHYSICAL_LANE_2,
  3257. DSI_PHYSICAL_LANE_3,
  3258. DSI_PHYSICAL_LANE_0,
  3259. DSI_PHYSICAL_LANE_1);
  3260. } else if (!strcmp(data, "lane_map_1230")) {
  3261. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3262. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3263. DSI_PHYSICAL_LANE_3,
  3264. DSI_PHYSICAL_LANE_0,
  3265. DSI_PHYSICAL_LANE_1,
  3266. DSI_PHYSICAL_LANE_2);
  3267. } else if (!strcmp(data, "lane_map_0321")) {
  3268. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3269. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3270. DSI_PHYSICAL_LANE_0,
  3271. DSI_PHYSICAL_LANE_3,
  3272. DSI_PHYSICAL_LANE_2,
  3273. DSI_PHYSICAL_LANE_1);
  3274. } else if (!strcmp(data, "lane_map_1032")) {
  3275. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3276. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3277. DSI_PHYSICAL_LANE_1,
  3278. DSI_PHYSICAL_LANE_0,
  3279. DSI_PHYSICAL_LANE_3,
  3280. DSI_PHYSICAL_LANE_2);
  3281. } else if (!strcmp(data, "lane_map_2103")) {
  3282. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3283. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3284. DSI_PHYSICAL_LANE_2,
  3285. DSI_PHYSICAL_LANE_1,
  3286. DSI_PHYSICAL_LANE_0,
  3287. DSI_PHYSICAL_LANE_3);
  3288. } else if (!strcmp(data, "lane_map_3210")) {
  3289. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3290. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3291. DSI_PHYSICAL_LANE_3,
  3292. DSI_PHYSICAL_LANE_2,
  3293. DSI_PHYSICAL_LANE_1,
  3294. DSI_PHYSICAL_LANE_0);
  3295. } else {
  3296. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3297. __func__, data);
  3298. goto set_default;
  3299. }
  3300. return 0;
  3301. set_default:
  3302. /* default lane mapping */
  3303. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3304. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3305. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3306. return 0;
  3307. }
  3308. static int dsi_display_get_phandle_index(
  3309. struct dsi_display *display,
  3310. const char *propname, int count, int index)
  3311. {
  3312. struct device_node *disp_node = display->panel_node;
  3313. u32 *val = NULL;
  3314. int rc = 0;
  3315. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3316. if (ZERO_OR_NULL_PTR(val)) {
  3317. rc = -ENOMEM;
  3318. goto end;
  3319. }
  3320. if (index >= count)
  3321. goto end;
  3322. if (display->fw)
  3323. rc = dsi_parser_read_u32_array(display->parser_node,
  3324. propname, val, count);
  3325. else
  3326. rc = of_property_read_u32_array(disp_node, propname,
  3327. val, count);
  3328. if (rc)
  3329. goto end;
  3330. rc = val[index];
  3331. DSI_DEBUG("%s index=%d\n", propname, rc);
  3332. end:
  3333. kfree(val);
  3334. return rc;
  3335. }
  3336. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3337. const char *propname)
  3338. {
  3339. if (display->fw)
  3340. return dsi_parser_count_u32_elems(display->parser_node,
  3341. propname);
  3342. else
  3343. return of_property_count_u32_elems(display->panel_node,
  3344. propname);
  3345. }
  3346. static int dsi_display_parse_dt(struct dsi_display *display)
  3347. {
  3348. int i, rc = 0;
  3349. u32 phy_count = 0;
  3350. struct device_node *of_node = display->pdev->dev.of_node;
  3351. char *dsi_ctrl_name, *dsi_phy_name;
  3352. if (!strcmp(display->display_type, "primary")) {
  3353. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3354. dsi_phy_name = "qcom,dsi-phy-num";
  3355. } else {
  3356. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3357. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3358. }
  3359. display->ctrl_count = dsi_display_get_phandle_count(display,
  3360. dsi_ctrl_name);
  3361. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3362. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3363. display->ctrl_count, phy_count);
  3364. if (!phy_count || !display->ctrl_count) {
  3365. DSI_ERR("no ctrl/phys found\n");
  3366. rc = -ENODEV;
  3367. goto error;
  3368. }
  3369. if (phy_count != display->ctrl_count) {
  3370. DSI_ERR("different ctrl and phy counts\n");
  3371. rc = -ENODEV;
  3372. goto error;
  3373. }
  3374. display_for_each_ctrl(i, display) {
  3375. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3376. int index;
  3377. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3378. display->ctrl_count, i);
  3379. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3380. "qcom,dsi-ctrl", index);
  3381. of_node_put(ctrl->ctrl_of_node);
  3382. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3383. display->ctrl_count, i);
  3384. ctrl->phy_of_node = of_parse_phandle(of_node,
  3385. "qcom,dsi-phy", index);
  3386. of_node_put(ctrl->phy_of_node);
  3387. }
  3388. /* Parse TE data */
  3389. dsi_display_parse_te_data(display);
  3390. /* Parse all external bridges from port 0 */
  3391. display_for_each_ctrl(i, display) {
  3392. display->ext_bridge[i].node_of =
  3393. of_graph_get_remote_node(of_node, 0, i);
  3394. if (display->ext_bridge[i].node_of)
  3395. display->ext_bridge_cnt++;
  3396. else
  3397. break;
  3398. }
  3399. DSI_DEBUG("success\n");
  3400. error:
  3401. return rc;
  3402. }
  3403. static int dsi_display_res_init(struct dsi_display *display)
  3404. {
  3405. int rc = 0;
  3406. int i;
  3407. struct dsi_display_ctrl *ctrl;
  3408. display_for_each_ctrl(i, display) {
  3409. ctrl = &display->ctrl[i];
  3410. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3411. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3412. rc = PTR_ERR(ctrl->ctrl);
  3413. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3414. ctrl->ctrl = NULL;
  3415. goto error_ctrl_put;
  3416. }
  3417. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3418. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3419. rc = PTR_ERR(ctrl->phy);
  3420. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3421. dsi_ctrl_put(ctrl->ctrl);
  3422. ctrl->phy = NULL;
  3423. goto error_ctrl_put;
  3424. }
  3425. }
  3426. display->panel = dsi_panel_get(&display->pdev->dev,
  3427. display->panel_node,
  3428. display->parser_node,
  3429. display->display_type,
  3430. display->cmdline_topology,
  3431. display->trusted_vm_env);
  3432. if (IS_ERR_OR_NULL(display->panel)) {
  3433. rc = PTR_ERR(display->panel);
  3434. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3435. display->panel = NULL;
  3436. goto error_ctrl_put;
  3437. }
  3438. display_for_each_ctrl(i, display) {
  3439. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3440. phy->cfg.force_clk_lane_hs =
  3441. display->panel->host_config.force_hs_clk_lane;
  3442. phy->cfg.phy_type =
  3443. display->panel->host_config.phy_type;
  3444. }
  3445. rc = dsi_display_parse_lane_map(display);
  3446. if (rc) {
  3447. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3448. goto error_ctrl_put;
  3449. }
  3450. rc = dsi_display_clocks_init(display);
  3451. if (rc) {
  3452. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3453. goto error_ctrl_put;
  3454. }
  3455. /**
  3456. * In trusted vm, the connectors will not be enabled
  3457. * until the HW resources are assigned and accepted.
  3458. */
  3459. if (display->trusted_vm_env)
  3460. display->is_active = false;
  3461. else
  3462. display->is_active = true;
  3463. return 0;
  3464. error_ctrl_put:
  3465. for (i = i - 1; i >= 0; i--) {
  3466. ctrl = &display->ctrl[i];
  3467. dsi_ctrl_put(ctrl->ctrl);
  3468. dsi_phy_put(ctrl->phy);
  3469. }
  3470. return rc;
  3471. }
  3472. static int dsi_display_res_deinit(struct dsi_display *display)
  3473. {
  3474. int rc = 0;
  3475. int i;
  3476. struct dsi_display_ctrl *ctrl;
  3477. rc = dsi_display_clocks_deinit(display);
  3478. if (rc)
  3479. DSI_ERR("clocks deinit failed, rc=%d\n", rc);
  3480. display_for_each_ctrl(i, display) {
  3481. ctrl = &display->ctrl[i];
  3482. dsi_phy_put(ctrl->phy);
  3483. dsi_ctrl_put(ctrl->ctrl);
  3484. }
  3485. if (display->panel)
  3486. dsi_panel_put(display->panel);
  3487. return rc;
  3488. }
  3489. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3490. struct dsi_display_mode *mode,
  3491. u32 flags)
  3492. {
  3493. int rc = 0;
  3494. int i;
  3495. struct dsi_display_ctrl *ctrl;
  3496. /*
  3497. * To set a mode:
  3498. * 1. Controllers should be turned off.
  3499. * 2. Link clocks should be off.
  3500. * 3. Phy should be disabled.
  3501. */
  3502. display_for_each_ctrl(i, display) {
  3503. ctrl = &display->ctrl[i];
  3504. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3505. (ctrl->phy_enabled)) {
  3506. rc = -EINVAL;
  3507. goto error;
  3508. }
  3509. }
  3510. error:
  3511. return rc;
  3512. }
  3513. static bool dsi_display_is_seamless_dfps_possible(
  3514. const struct dsi_display *display,
  3515. const struct dsi_display_mode *tgt,
  3516. const enum dsi_dfps_type dfps_type)
  3517. {
  3518. struct dsi_display_mode *cur;
  3519. if (!display || !tgt || !display->panel) {
  3520. DSI_ERR("Invalid params\n");
  3521. return false;
  3522. }
  3523. cur = display->panel->cur_mode;
  3524. if (cur->timing.h_active != tgt->timing.h_active) {
  3525. DSI_DEBUG("timing.h_active differs %d %d\n",
  3526. cur->timing.h_active, tgt->timing.h_active);
  3527. return false;
  3528. }
  3529. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3530. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3531. cur->timing.h_back_porch,
  3532. tgt->timing.h_back_porch);
  3533. return false;
  3534. }
  3535. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3536. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3537. cur->timing.h_sync_width,
  3538. tgt->timing.h_sync_width);
  3539. return false;
  3540. }
  3541. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3542. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3543. cur->timing.h_front_porch,
  3544. tgt->timing.h_front_porch);
  3545. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3546. return false;
  3547. }
  3548. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3549. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3550. cur->timing.h_skew,
  3551. tgt->timing.h_skew);
  3552. return false;
  3553. }
  3554. /* skip polarity comparison */
  3555. if (cur->timing.v_active != tgt->timing.v_active) {
  3556. DSI_DEBUG("timing.v_active differs %d %d\n",
  3557. cur->timing.v_active,
  3558. tgt->timing.v_active);
  3559. return false;
  3560. }
  3561. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3562. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3563. cur->timing.v_back_porch,
  3564. tgt->timing.v_back_porch);
  3565. return false;
  3566. }
  3567. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3568. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3569. cur->timing.v_sync_width,
  3570. tgt->timing.v_sync_width);
  3571. return false;
  3572. }
  3573. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3574. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3575. cur->timing.v_front_porch,
  3576. tgt->timing.v_front_porch);
  3577. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3578. return false;
  3579. }
  3580. /* skip polarity comparison */
  3581. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3582. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3583. cur->timing.refresh_rate,
  3584. tgt->timing.refresh_rate);
  3585. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3586. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3587. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3588. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3589. DSI_DEBUG("flags differs %d %d\n",
  3590. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3591. return true;
  3592. }
  3593. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3594. {
  3595. struct dsi_host_common_cfg *config;
  3596. struct dsi_display_ctrl *m_ctrl;
  3597. int phy_ver;
  3598. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3599. config = &display->panel->host_config;
  3600. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3601. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3602. config->byte_intf_clk_div = 1;
  3603. else
  3604. config->byte_intf_clk_div = 2;
  3605. }
  3606. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3607. u32 bit_clk_rate)
  3608. {
  3609. int rc = 0;
  3610. int i;
  3611. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3612. if (!display->panel) {
  3613. DSI_ERR("Invalid params\n");
  3614. return -EINVAL;
  3615. }
  3616. if (bit_clk_rate == 0) {
  3617. DSI_ERR("Invalid bit clock rate\n");
  3618. return -EINVAL;
  3619. }
  3620. display->config.bit_clk_rate_hz = bit_clk_rate;
  3621. display_for_each_ctrl(i, display) {
  3622. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3623. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3624. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3625. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3626. byte_intf_clk_rate;
  3627. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3628. struct dsi_host_common_cfg *host_cfg;
  3629. mutex_lock(&ctrl->ctrl_lock);
  3630. host_cfg = &display->panel->host_config;
  3631. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3632. num_of_lanes++;
  3633. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3634. num_of_lanes++;
  3635. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3636. num_of_lanes++;
  3637. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3638. num_of_lanes++;
  3639. if (num_of_lanes == 0) {
  3640. DSI_ERR("Invalid lane count\n");
  3641. rc = -EINVAL;
  3642. goto error;
  3643. }
  3644. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3645. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3646. bit_rate_per_lane = bit_rate;
  3647. do_div(bit_rate_per_lane, num_of_lanes);
  3648. pclk_rate = bit_rate;
  3649. do_div(pclk_rate, bpp);
  3650. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3651. bit_rate_per_lane = bit_rate;
  3652. do_div(bit_rate_per_lane, num_of_lanes);
  3653. byte_clk_rate = bit_rate_per_lane;
  3654. do_div(byte_clk_rate, 8);
  3655. byte_intf_clk_rate = byte_clk_rate;
  3656. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3657. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3658. } else {
  3659. bit_rate_per_lane = bit_clk_rate;
  3660. pclk_rate *= bits_per_symbol;
  3661. do_div(pclk_rate, num_of_symbols);
  3662. byte_clk_rate = bit_clk_rate;
  3663. do_div(byte_clk_rate, num_of_symbols);
  3664. /* For CPHY, byte_intf_clk is same as byte_clk */
  3665. byte_intf_clk_rate = byte_clk_rate;
  3666. }
  3667. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3668. bit_rate, bit_rate_per_lane);
  3669. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3670. byte_clk_rate, byte_intf_clk_rate);
  3671. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3672. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3673. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3674. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3675. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3676. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3677. ctrl->clk_freq, ctrl->cell_index);
  3678. if (rc) {
  3679. DSI_ERR("Failed to update link frequencies\n");
  3680. goto error;
  3681. }
  3682. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3683. error:
  3684. mutex_unlock(&ctrl->ctrl_lock);
  3685. /* TODO: recover ctrl->clk_freq in case of failure */
  3686. if (rc)
  3687. return rc;
  3688. }
  3689. return 0;
  3690. }
  3691. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3692. struct dsi_dyn_clk_delay *delay,
  3693. struct dsi_display_mode *mode)
  3694. {
  3695. u32 esc_clk_rate_hz;
  3696. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3697. u32 hsync_period = 0;
  3698. struct dsi_display_ctrl *m_ctrl;
  3699. struct dsi_ctrl *dsi_ctrl;
  3700. struct dsi_phy_cfg *cfg;
  3701. int phy_ver;
  3702. m_ctrl = &display->ctrl[display->clk_master_idx];
  3703. dsi_ctrl = m_ctrl->ctrl;
  3704. cfg = &(m_ctrl->phy->cfg);
  3705. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3706. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3707. esc_clk_rate_hz);
  3708. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3709. esc_clk_rate_hz);
  3710. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3711. esc_clk_rate_hz);
  3712. hsync_period = dsi_h_total_dce(&mode->timing);
  3713. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3714. if (!display->panel->video_config.eof_bllp_lp11_en)
  3715. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3716. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3717. (display->config.common_config.t_clk_post + 1)) /
  3718. byte_to_esc_ratio) +
  3719. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3720. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3721. ((cfg->timing.lane_v3[3] * 4) +
  3722. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3723. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3724. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3725. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3726. hr_bit_to_esc_ratio);
  3727. delay->pipe_delay2 = 0;
  3728. if (display->panel->host_config.force_hs_clk_lane)
  3729. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3730. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3731. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3732. hr_bit_to_esc_ratio);
  3733. /*
  3734. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3735. * 25us pll delay recommended for phy ver 4.0
  3736. */
  3737. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3738. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3739. delay->pll_delay = 100;
  3740. else
  3741. delay->pll_delay = 25;
  3742. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3743. }
  3744. /*
  3745. * dsi_display_is_type_cphy - check if panel type is cphy
  3746. * @display: Pointer to private display structure
  3747. * Returns: True if panel type is cphy
  3748. */
  3749. static inline bool dsi_display_is_type_cphy(struct dsi_display *display)
  3750. {
  3751. return (display->panel->host_config.phy_type ==
  3752. DSI_PHY_TYPE_CPHY) ? true : false;
  3753. }
  3754. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3755. struct link_clk_freq *bkp_freq)
  3756. {
  3757. int rc = 0, i;
  3758. u8 ctrl_version;
  3759. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3760. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3761. struct dsi_clk_link_set *parent_clk, *enable_clk;
  3762. m_ctrl = &display->ctrl[display->clk_master_idx];
  3763. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3764. ctrl_version = m_ctrl->ctrl->version;
  3765. if (dsi_display_is_type_cphy(display)) {
  3766. enable_clk = &display->clock_info.cphy_clks;
  3767. parent_clk = &display->clock_info.shadow_cphy_clks;
  3768. } else {
  3769. enable_clk = &display->clock_info.src_clks;
  3770. parent_clk = &display->clock_info.shadow_clks;
  3771. }
  3772. dsi_clk_prepare_enable(enable_clk);
  3773. rc = dsi_clk_update_parent(parent_clk,
  3774. &display->clock_info.mux_clks);
  3775. if (rc) {
  3776. DSI_ERR("failed to update mux parent\n");
  3777. goto exit;
  3778. }
  3779. display_for_each_ctrl(i, display) {
  3780. ctrl = &display->ctrl[i];
  3781. if (!ctrl->ctrl)
  3782. continue;
  3783. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3784. ctrl->ctrl->clk_freq.byte_clk_rate,
  3785. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3786. if (rc) {
  3787. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3788. goto recover_byte_clk;
  3789. }
  3790. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3791. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3792. if (rc) {
  3793. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3794. goto recover_pix_clk;
  3795. }
  3796. }
  3797. display_for_each_ctrl(i, display) {
  3798. ctrl = &display->ctrl[i];
  3799. if (ctrl == m_ctrl)
  3800. continue;
  3801. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3802. }
  3803. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3804. /*
  3805. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3806. * and with constant fps, as dynamic refresh will applied with
  3807. * next mdp intf ctrl flush.
  3808. */
  3809. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3810. (dyn_clk_caps->maintain_const_fps))
  3811. goto defer_dfps_wait;
  3812. /* wait for dynamic refresh done */
  3813. display_for_each_ctrl(i, display) {
  3814. ctrl = &display->ctrl[i];
  3815. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3816. if (rc) {
  3817. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3818. goto recover_pix_clk;
  3819. } else {
  3820. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3821. i ? "slave" : "master");
  3822. }
  3823. }
  3824. display_for_each_ctrl(i, display) {
  3825. ctrl = &display->ctrl[i];
  3826. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3827. }
  3828. defer_dfps_wait:
  3829. rc = dsi_clk_update_parent(enable_clk,
  3830. &display->clock_info.mux_clks);
  3831. if (rc)
  3832. DSI_ERR("could not switch back to src clks %d\n", rc);
  3833. dsi_clk_disable_unprepare(enable_clk);
  3834. return rc;
  3835. recover_pix_clk:
  3836. display_for_each_ctrl(i, display) {
  3837. ctrl = &display->ctrl[i];
  3838. if (!ctrl->ctrl)
  3839. continue;
  3840. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3841. bkp_freq->pix_clk_rate, i);
  3842. }
  3843. recover_byte_clk:
  3844. display_for_each_ctrl(i, display) {
  3845. ctrl = &display->ctrl[i];
  3846. if (!ctrl->ctrl)
  3847. continue;
  3848. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3849. bkp_freq->byte_clk_rate,
  3850. bkp_freq->byte_intf_clk_rate, i);
  3851. }
  3852. exit:
  3853. dsi_clk_disable_unprepare(&display->clock_info.src_clks);
  3854. return rc;
  3855. }
  3856. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3857. struct dsi_display_mode *mode)
  3858. {
  3859. int rc = 0, mask, i;
  3860. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3861. struct dsi_dyn_clk_delay delay;
  3862. struct link_clk_freq bkp_freq;
  3863. dsi_panel_acquire_panel_lock(display->panel);
  3864. m_ctrl = &display->ctrl[display->clk_master_idx];
  3865. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3866. /* mask PLL unlock, FIFO overflow and underflow errors */
  3867. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3868. BIT(DSI_FIFO_OVERFLOW);
  3869. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3870. /* update the phy timings based on new mode */
  3871. display_for_each_ctrl(i, display) {
  3872. ctrl = &display->ctrl[i];
  3873. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3874. }
  3875. /* back up existing rates to handle failure case */
  3876. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3877. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3878. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3879. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3880. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3881. if (rc) {
  3882. DSI_ERR("failed set link frequencies %d\n", rc);
  3883. goto exit;
  3884. }
  3885. /* calculate pipe delays */
  3886. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3887. /* configure dynamic refresh ctrl registers */
  3888. display_for_each_ctrl(i, display) {
  3889. ctrl = &display->ctrl[i];
  3890. if (!ctrl->phy)
  3891. continue;
  3892. if (ctrl == m_ctrl)
  3893. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3894. else
  3895. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3896. false);
  3897. }
  3898. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3899. exit:
  3900. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3901. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3902. DSI_CLK_OFF);
  3903. /* store newly calculated phy timings in mode private info */
  3904. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3905. mode->priv_info->phy_timing_val,
  3906. mode->priv_info->phy_timing_len);
  3907. dsi_panel_release_panel_lock(display->panel);
  3908. return rc;
  3909. }
  3910. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3911. int clk_rate)
  3912. {
  3913. int rc = 0;
  3914. if (clk_rate <= 0) {
  3915. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3916. return -EINVAL;
  3917. }
  3918. if (clk_rate == display->cached_clk_rate) {
  3919. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3920. return rc;
  3921. }
  3922. display->cached_clk_rate = clk_rate;
  3923. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3924. if (!rc) {
  3925. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  3926. __func__, clk_rate);
  3927. atomic_set(&display->clkrate_change_pending, 1);
  3928. } else {
  3929. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  3930. __func__, clk_rate, rc);
  3931. /* Caching clock failed, so don't go on doing so. */
  3932. atomic_set(&display->clkrate_change_pending, 0);
  3933. display->cached_clk_rate = 0;
  3934. }
  3935. return rc;
  3936. }
  3937. static int dsi_display_dfps_update(struct dsi_display *display,
  3938. struct dsi_display_mode *dsi_mode)
  3939. {
  3940. struct dsi_mode_info *timing;
  3941. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3942. struct dsi_display_mode *panel_mode;
  3943. struct dsi_dfps_capabilities dfps_caps;
  3944. int rc = 0;
  3945. int i = 0;
  3946. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3947. if (!display || !dsi_mode || !display->panel) {
  3948. DSI_ERR("Invalid params\n");
  3949. return -EINVAL;
  3950. }
  3951. timing = &dsi_mode->timing;
  3952. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3953. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3954. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  3955. DSI_ERR("dfps or constant fps not supported\n");
  3956. return -ENOTSUPP;
  3957. }
  3958. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  3959. DSI_ERR("dfps clock method not supported\n");
  3960. return -ENOTSUPP;
  3961. }
  3962. /* For split DSI, update the clock master first */
  3963. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  3964. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  3965. m_ctrl = &display->ctrl[display->clk_master_idx];
  3966. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  3967. if (rc) {
  3968. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3969. display->name, i, rc);
  3970. goto error;
  3971. }
  3972. /* Update the rest of the controllers */
  3973. display_for_each_ctrl(i, display) {
  3974. ctrl = &display->ctrl[i];
  3975. if (!ctrl->ctrl || (ctrl == m_ctrl))
  3976. continue;
  3977. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  3978. if (rc) {
  3979. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3980. display->name, i, rc);
  3981. goto error;
  3982. }
  3983. }
  3984. panel_mode = display->panel->cur_mode;
  3985. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  3986. /*
  3987. * dsi_mode_flags flags are used to communicate with other drm driver
  3988. * components, and are transient. They aren't inherently part of the
  3989. * display panel's mode and shouldn't be saved into the cached currently
  3990. * active mode.
  3991. */
  3992. panel_mode->dsi_mode_flags = 0;
  3993. error:
  3994. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  3995. return rc;
  3996. }
  3997. static int dsi_display_dfps_calc_front_porch(
  3998. u32 old_fps,
  3999. u32 new_fps,
  4000. u32 a_total,
  4001. u32 b_total,
  4002. u32 b_fp,
  4003. u32 *b_fp_out)
  4004. {
  4005. s32 b_fp_new;
  4006. int add_porches, diff;
  4007. if (!b_fp_out) {
  4008. DSI_ERR("Invalid params\n");
  4009. return -EINVAL;
  4010. }
  4011. if (!a_total || !new_fps) {
  4012. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  4013. return -EINVAL;
  4014. }
  4015. /*
  4016. * Keep clock, other porches constant, use new fps, calc front porch
  4017. * new_vtotal = old_vtotal * (old_fps / new_fps )
  4018. * new_vfp - old_vfp = new_vtotal - old_vtotal
  4019. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  4020. */
  4021. diff = abs(old_fps - new_fps);
  4022. add_porches = mult_frac(b_total, diff, new_fps);
  4023. if (old_fps > new_fps)
  4024. b_fp_new = b_fp + add_porches;
  4025. else
  4026. b_fp_new = b_fp - add_porches;
  4027. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4028. new_fps, a_total, b_total, b_fp, b_fp_new);
  4029. if (b_fp_new < 0) {
  4030. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4031. return -EINVAL;
  4032. }
  4033. /**
  4034. * TODO: To differentiate from clock method when communicating to the
  4035. * other components, perhaps we should set clk here to original value
  4036. */
  4037. *b_fp_out = b_fp_new;
  4038. return 0;
  4039. }
  4040. /**
  4041. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4042. * @display: DSI display handle.
  4043. * @adj_mode: Mode value structure to be changed.
  4044. * It contains old timing values and latest fps value.
  4045. * New timing values are updated based on new fps.
  4046. * @curr_refresh_rate: Current fps rate.
  4047. * If zero , current fps rate is taken from
  4048. * display->panel->cur_mode.
  4049. * Return: error code.
  4050. */
  4051. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4052. struct dsi_display_mode *adj_mode,
  4053. u32 curr_refresh_rate)
  4054. {
  4055. struct dsi_dfps_capabilities dfps_caps;
  4056. struct dsi_display_mode per_ctrl_mode;
  4057. struct dsi_mode_info *timing;
  4058. struct dsi_ctrl *m_ctrl;
  4059. int rc = 0;
  4060. if (!display || !adj_mode) {
  4061. DSI_ERR("Invalid params\n");
  4062. return -EINVAL;
  4063. }
  4064. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4065. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4066. if (!dfps_caps.dfps_support) {
  4067. DSI_ERR("dfps not supported by panel\n");
  4068. return -EINVAL;
  4069. }
  4070. per_ctrl_mode = *adj_mode;
  4071. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4072. if (!curr_refresh_rate) {
  4073. if (!dsi_display_is_seamless_dfps_possible(display,
  4074. &per_ctrl_mode, dfps_caps.type)) {
  4075. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4076. return -EINVAL;
  4077. }
  4078. if (display->panel->cur_mode) {
  4079. curr_refresh_rate =
  4080. display->panel->cur_mode->timing.refresh_rate;
  4081. } else {
  4082. DSI_ERR("cur_mode is not initialized\n");
  4083. return -EINVAL;
  4084. }
  4085. }
  4086. /* TODO: Remove this direct reference to the dsi_ctrl */
  4087. timing = &per_ctrl_mode.timing;
  4088. switch (dfps_caps.type) {
  4089. case DSI_DFPS_IMMEDIATE_VFP:
  4090. rc = dsi_display_dfps_calc_front_porch(
  4091. curr_refresh_rate,
  4092. timing->refresh_rate,
  4093. dsi_h_total_dce(timing),
  4094. DSI_V_TOTAL(timing),
  4095. timing->v_front_porch,
  4096. &adj_mode->timing.v_front_porch);
  4097. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4098. curr_refresh_rate, timing->refresh_rate,
  4099. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4100. break;
  4101. case DSI_DFPS_IMMEDIATE_HFP:
  4102. rc = dsi_display_dfps_calc_front_porch(
  4103. curr_refresh_rate,
  4104. timing->refresh_rate,
  4105. DSI_V_TOTAL(timing),
  4106. dsi_h_total_dce(timing),
  4107. timing->h_front_porch,
  4108. &adj_mode->timing.h_front_porch);
  4109. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4110. curr_refresh_rate, timing->refresh_rate,
  4111. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4112. if (!rc)
  4113. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4114. break;
  4115. default:
  4116. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4117. rc = -ENOTSUPP;
  4118. }
  4119. return rc;
  4120. }
  4121. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4122. struct dsi_display_mode *adj_mode)
  4123. {
  4124. int rc = 0;
  4125. if (!display || !adj_mode) {
  4126. DSI_ERR("Invalid params\n");
  4127. return false;
  4128. }
  4129. /* Currently the only seamless transition is dynamic fps */
  4130. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4131. if (rc) {
  4132. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4133. } else {
  4134. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4135. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4136. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4137. }
  4138. return rc;
  4139. }
  4140. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4141. struct dsi_display_mode *to_mode)
  4142. {
  4143. u32 cur_fps, to_fps;
  4144. u32 cur_h_active, to_h_active;
  4145. u32 cur_v_active, to_v_active;
  4146. cur_fps = cur_mode->timing.refresh_rate;
  4147. to_fps = to_mode->timing.refresh_rate;
  4148. cur_h_active = cur_mode->timing.h_active;
  4149. cur_v_active = cur_mode->timing.v_active;
  4150. to_h_active = to_mode->timing.h_active;
  4151. to_v_active = to_mode->timing.v_active;
  4152. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4153. (cur_fps != to_fps)) {
  4154. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4155. DSI_DEBUG("DMS Modeset with FPS change\n");
  4156. } else {
  4157. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4158. }
  4159. }
  4160. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4161. struct dsi_display_mode *mode,
  4162. u32 flags)
  4163. {
  4164. int rc = 0, clk_rate = 0;
  4165. int i;
  4166. struct dsi_display_ctrl *ctrl;
  4167. struct dsi_display_ctrl *mctrl;
  4168. struct dsi_display_mode_priv_info *priv_info;
  4169. bool commit_phy_timing = false;
  4170. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4171. priv_info = mode->priv_info;
  4172. if (!priv_info) {
  4173. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4174. display->name);
  4175. return -EINVAL;
  4176. }
  4177. SDE_EVT32(mode->dsi_mode_flags, mode->panel_mode);
  4178. display->panel->panel_mode = mode->panel_mode;
  4179. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4180. mode,
  4181. &display->config);
  4182. if (rc) {
  4183. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4184. display->name, rc);
  4185. goto error;
  4186. }
  4187. memcpy(&display->config.lane_map, &display->lane_map,
  4188. sizeof(display->lane_map));
  4189. mctrl = &display->ctrl[display->clk_master_idx];
  4190. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4191. if (mode->dsi_mode_flags &
  4192. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4193. display_for_each_ctrl(i, display) {
  4194. ctrl = &display->ctrl[i];
  4195. if (!ctrl->ctrl || (ctrl != mctrl))
  4196. continue;
  4197. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4198. true);
  4199. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4200. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4201. (dyn_clk_caps->maintain_const_fps)) {
  4202. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4203. true);
  4204. }
  4205. }
  4206. rc = dsi_display_dfps_update(display, mode);
  4207. if (rc) {
  4208. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4209. display->name, rc);
  4210. goto error;
  4211. }
  4212. display_for_each_ctrl(i, display) {
  4213. ctrl = &display->ctrl[i];
  4214. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4215. &display->config, mode, mode->dsi_mode_flags,
  4216. display->dsi_clk_handle);
  4217. if (rc) {
  4218. DSI_ERR("failed to update ctrl config\n");
  4219. goto error;
  4220. }
  4221. }
  4222. if (priv_info->phy_timing_len) {
  4223. display_for_each_ctrl(i, display) {
  4224. ctrl = &display->ctrl[i];
  4225. rc = dsi_phy_set_timing_params(ctrl->phy,
  4226. priv_info->phy_timing_val,
  4227. priv_info->phy_timing_len,
  4228. commit_phy_timing);
  4229. if (rc)
  4230. DSI_ERR("Fail to add timing params\n");
  4231. }
  4232. }
  4233. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4234. return rc;
  4235. }
  4236. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4237. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4238. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4239. if (rc)
  4240. DSI_ERR("dynamic clk change failed %d\n", rc);
  4241. /*
  4242. * skip rest of the opearations since
  4243. * dsi_display_dynamic_clk_switch_vid() already takes
  4244. * care of them.
  4245. */
  4246. return rc;
  4247. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4248. clk_rate = mode->timing.clk_rate_hz;
  4249. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4250. clk_rate);
  4251. if (rc) {
  4252. DSI_ERR("Failed to configure dynamic clk\n");
  4253. return rc;
  4254. }
  4255. }
  4256. }
  4257. display_for_each_ctrl(i, display) {
  4258. ctrl = &display->ctrl[i];
  4259. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4260. mode, mode->dsi_mode_flags,
  4261. display->dsi_clk_handle);
  4262. if (rc) {
  4263. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4264. display->name, rc);
  4265. goto error;
  4266. }
  4267. }
  4268. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4269. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4270. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4271. u64 to_bitclk = mode->timing.clk_rate_hz;
  4272. commit_phy_timing = true;
  4273. /* No need to set clkrate pending flag if clocks are same */
  4274. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4275. atomic_set(&display->clkrate_change_pending, 1);
  4276. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4277. }
  4278. if (priv_info->phy_timing_len) {
  4279. display_for_each_ctrl(i, display) {
  4280. ctrl = &display->ctrl[i];
  4281. rc = dsi_phy_set_timing_params(ctrl->phy,
  4282. priv_info->phy_timing_val,
  4283. priv_info->phy_timing_len,
  4284. commit_phy_timing);
  4285. if (rc)
  4286. DSI_ERR("failed to add DSI PHY timing params\n");
  4287. }
  4288. }
  4289. error:
  4290. return rc;
  4291. }
  4292. /**
  4293. * _dsi_display_dev_init - initializes the display device
  4294. * Initialization will acquire references to the resources required for the
  4295. * display hardware to function.
  4296. * @display: Handle to the display
  4297. * Returns: Zero on success
  4298. */
  4299. static int _dsi_display_dev_init(struct dsi_display *display)
  4300. {
  4301. int rc = 0;
  4302. if (!display) {
  4303. DSI_ERR("invalid display\n");
  4304. return -EINVAL;
  4305. }
  4306. if (!display->panel_node && !display->fw)
  4307. return 0;
  4308. mutex_lock(&display->display_lock);
  4309. display->parser = dsi_parser_get(&display->pdev->dev);
  4310. if (display->fw && display->parser)
  4311. display->parser_node = dsi_parser_get_head_node(
  4312. display->parser, display->fw->data,
  4313. display->fw->size);
  4314. rc = dsi_display_parse_dt(display);
  4315. if (rc) {
  4316. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4317. goto error;
  4318. }
  4319. rc = dsi_display_res_init(display);
  4320. if (rc) {
  4321. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4322. display->name, rc);
  4323. goto error;
  4324. }
  4325. error:
  4326. mutex_unlock(&display->display_lock);
  4327. return rc;
  4328. }
  4329. /**
  4330. * _dsi_display_dev_deinit - deinitializes the display device
  4331. * All the resources acquired during device init will be released.
  4332. * @display: Handle to the display
  4333. * Returns: Zero on success
  4334. */
  4335. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4336. {
  4337. int rc = 0;
  4338. if (!display) {
  4339. DSI_ERR("invalid display\n");
  4340. return -EINVAL;
  4341. }
  4342. mutex_lock(&display->display_lock);
  4343. rc = dsi_display_res_deinit(display);
  4344. if (rc)
  4345. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4346. display->name, rc);
  4347. mutex_unlock(&display->display_lock);
  4348. return rc;
  4349. }
  4350. /**
  4351. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4352. * @dsi_display: Pointer to dsi display
  4353. * Returns: Zero on success
  4354. */
  4355. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4356. {
  4357. struct dsi_display *display = dsi_display;
  4358. int rc = 0;
  4359. /* Remove the panel vote that was added during dsi display probe */
  4360. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4361. if (rc)
  4362. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4363. display->panel->name, rc);
  4364. return rc;
  4365. }
  4366. /**
  4367. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4368. * @dsi_display: Pointer to dsi display
  4369. * Returns: Zero on success
  4370. */
  4371. int dsi_display_cont_splash_config(void *dsi_display)
  4372. {
  4373. struct dsi_display *display = dsi_display;
  4374. int rc = 0;
  4375. /* Vote for gdsc required to read register address space */
  4376. if (!display) {
  4377. DSI_ERR("invalid input display param\n");
  4378. return -EINVAL;
  4379. }
  4380. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4381. if (rc < 0) {
  4382. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4383. rc);
  4384. return rc;
  4385. }
  4386. mutex_lock(&display->display_lock);
  4387. display->is_cont_splash_enabled = true;
  4388. /* Update splash status for clock manager */
  4389. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4390. display->is_cont_splash_enabled);
  4391. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4392. /* Set up ctrl isr before enabling core clk */
  4393. dsi_display_ctrl_isr_configure(display, true);
  4394. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4395. * regulator are inplicit from pre clk on callback
  4396. */
  4397. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4398. DSI_ALL_CLKS, DSI_CLK_ON);
  4399. if (rc) {
  4400. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4401. display->name, rc);
  4402. goto clk_manager_update;
  4403. }
  4404. mutex_unlock(&display->display_lock);
  4405. /* Set the current brightness level */
  4406. dsi_panel_bl_handoff(display->panel);
  4407. return rc;
  4408. clk_manager_update:
  4409. dsi_display_ctrl_isr_configure(display, false);
  4410. /* Update splash status for clock manager */
  4411. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4412. false);
  4413. pm_runtime_put_sync(display->drm_dev->dev);
  4414. display->is_cont_splash_enabled = false;
  4415. mutex_unlock(&display->display_lock);
  4416. return rc;
  4417. }
  4418. /**
  4419. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4420. * @display: Pointer to dsi display
  4421. * Returns: Zero on success
  4422. */
  4423. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4424. {
  4425. int rc = 0;
  4426. if (!display->is_cont_splash_enabled)
  4427. return 0;
  4428. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4429. DSI_ALL_CLKS, DSI_CLK_OFF);
  4430. if (rc)
  4431. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4432. display->name, rc);
  4433. pm_runtime_put_sync(display->drm_dev->dev);
  4434. display->is_cont_splash_enabled = false;
  4435. /* Update splash status for clock manager */
  4436. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4437. display->is_cont_splash_enabled);
  4438. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4439. return rc;
  4440. }
  4441. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4442. {
  4443. int rc = 0;
  4444. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4445. if (!rc) {
  4446. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4447. display->cached_clk_rate);
  4448. atomic_set(&display->clkrate_change_pending, 0);
  4449. } else {
  4450. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4451. display->cached_clk_rate, rc);
  4452. }
  4453. return rc;
  4454. }
  4455. static int dsi_display_validate_split_link(struct dsi_display *display)
  4456. {
  4457. int i, rc = 0;
  4458. struct dsi_display_ctrl *ctrl;
  4459. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4460. if (!host->split_link.split_link_enabled)
  4461. return 0;
  4462. if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4463. DSI_ERR("[%s] split link is not supported in command mode\n",
  4464. display->name);
  4465. rc = -ENOTSUPP;
  4466. goto error;
  4467. }
  4468. display_for_each_ctrl(i, display) {
  4469. ctrl = &display->ctrl[i];
  4470. if (!ctrl->ctrl->split_link_supported) {
  4471. DSI_ERR("[%s] split link is not supported by hw\n",
  4472. display->name);
  4473. rc = -ENOTSUPP;
  4474. goto error;
  4475. }
  4476. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4477. }
  4478. DSI_DEBUG("Split link is enabled\n");
  4479. return 0;
  4480. error:
  4481. host->split_link.split_link_enabled = false;
  4482. return rc;
  4483. }
  4484. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4485. {
  4486. int rc = 0;
  4487. struct dsi_display *display;
  4488. if (!data)
  4489. return -EINVAL;
  4490. rc = dsi_ctrl_get_io_resources(io_res);
  4491. if (rc)
  4492. goto end;
  4493. rc = dsi_phy_get_io_resources(io_res);
  4494. if (rc)
  4495. goto end;
  4496. display = (struct dsi_display *)data;
  4497. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4498. end:
  4499. return rc;
  4500. }
  4501. static int dsi_display_pre_release(void *data)
  4502. {
  4503. if (!data)
  4504. return -EINVAL;
  4505. dsi_display_ctrl_irq_update((struct dsi_display *)data, false);
  4506. return 0;
  4507. }
  4508. static int dsi_display_pre_acquire(void *data)
  4509. {
  4510. if (!data)
  4511. return -EINVAL;
  4512. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4513. return 0;
  4514. }
  4515. /**
  4516. * dsi_display_bind - bind dsi device with controlling device
  4517. * @dev: Pointer to base of platform device
  4518. * @master: Pointer to container of drm device
  4519. * @data: Pointer to private data
  4520. * Returns: Zero on success
  4521. */
  4522. static int dsi_display_bind(struct device *dev,
  4523. struct device *master,
  4524. void *data)
  4525. {
  4526. struct dsi_display_ctrl *display_ctrl;
  4527. struct drm_device *drm;
  4528. struct dsi_display *display;
  4529. struct dsi_clk_info info;
  4530. struct clk_ctrl_cb clk_cb;
  4531. void *handle = NULL;
  4532. struct platform_device *pdev = to_platform_device(dev);
  4533. char *client1 = "dsi_clk_client";
  4534. char *client2 = "mdp_event_client";
  4535. struct msm_vm_ops vm_event_ops = {
  4536. .vm_get_io_resources = dsi_display_get_io_resources,
  4537. .vm_pre_hw_release = dsi_display_pre_release,
  4538. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4539. };
  4540. int i, rc = 0;
  4541. if (!dev || !pdev || !master) {
  4542. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4543. dev, pdev, master);
  4544. return -EINVAL;
  4545. }
  4546. drm = dev_get_drvdata(master);
  4547. display = platform_get_drvdata(pdev);
  4548. if (!drm || !display) {
  4549. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4550. drm, display);
  4551. return -EINVAL;
  4552. }
  4553. if (!display->panel_node && !display->fw)
  4554. return 0;
  4555. if (!display->fw)
  4556. display->name = display->panel_node->name;
  4557. /* defer bind if ext bridge driver is not loaded */
  4558. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4559. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4560. if (!of_drm_find_bridge(
  4561. display->ext_bridge[i].node_of)) {
  4562. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4563. display->ext_bridge[i].node_of->full_name);
  4564. return -EPROBE_DEFER;
  4565. }
  4566. }
  4567. }
  4568. mutex_lock(&display->display_lock);
  4569. rc = dsi_display_validate_split_link(display);
  4570. if (rc) {
  4571. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4572. display->name, rc);
  4573. goto error;
  4574. }
  4575. rc = dsi_display_debugfs_init(display);
  4576. if (rc) {
  4577. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4578. goto error;
  4579. }
  4580. atomic_set(&display->clkrate_change_pending, 0);
  4581. display->cached_clk_rate = 0;
  4582. memset(&info, 0x0, sizeof(info));
  4583. display_for_each_ctrl(i, display) {
  4584. display_ctrl = &display->ctrl[i];
  4585. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4586. if (rc) {
  4587. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4588. display->name, i, rc);
  4589. goto error_ctrl_deinit;
  4590. }
  4591. display_ctrl->ctrl->horiz_index = i;
  4592. rc = dsi_phy_drv_init(display_ctrl->phy);
  4593. if (rc) {
  4594. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4595. display->name, i, rc);
  4596. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4597. goto error_ctrl_deinit;
  4598. }
  4599. display_ctrl->ctrl->dma_cmd_workq = display->dma_cmd_workq;
  4600. memcpy(&info.c_clks[i],
  4601. (&display_ctrl->ctrl->clk_info.core_clks),
  4602. sizeof(struct dsi_core_clk_info));
  4603. memcpy(&info.l_hs_clks[i],
  4604. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4605. sizeof(struct dsi_link_hs_clk_info));
  4606. memcpy(&info.l_lp_clks[i],
  4607. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4608. sizeof(struct dsi_link_lp_clk_info));
  4609. info.c_clks[i].drm = drm;
  4610. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4611. }
  4612. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4613. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4614. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4615. info.post_clkon_cb = dsi_post_clkon_cb;
  4616. info.priv_data = display;
  4617. info.master_ndx = display->clk_master_idx;
  4618. info.dsi_ctrl_count = display->ctrl_count;
  4619. snprintf(info.name, MAX_STRING_LEN,
  4620. "DSI_MNGR-%s", display->name);
  4621. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4622. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4623. rc = PTR_ERR(display->clk_mngr);
  4624. display->clk_mngr = NULL;
  4625. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4626. goto error_ctrl_deinit;
  4627. }
  4628. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4629. if (IS_ERR_OR_NULL(handle)) {
  4630. rc = PTR_ERR(handle);
  4631. DSI_ERR("failed to register %s client, rc = %d\n",
  4632. client1, rc);
  4633. goto error_clk_deinit;
  4634. } else {
  4635. display->dsi_clk_handle = handle;
  4636. }
  4637. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4638. if (IS_ERR_OR_NULL(handle)) {
  4639. rc = PTR_ERR(handle);
  4640. DSI_ERR("failed to register %s client, rc = %d\n",
  4641. client2, rc);
  4642. goto error_clk_client_deinit;
  4643. } else {
  4644. display->mdp_clk_handle = handle;
  4645. }
  4646. clk_cb.priv = display;
  4647. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4648. display_for_each_ctrl(i, display) {
  4649. display_ctrl = &display->ctrl[i];
  4650. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4651. if (rc) {
  4652. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4653. display->name, i, rc);
  4654. goto error_ctrl_deinit;
  4655. }
  4656. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4657. if (rc) {
  4658. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4659. display->name, i, rc);
  4660. goto error_ctrl_deinit;
  4661. }
  4662. }
  4663. dsi_display_update_byte_intf_div(display);
  4664. rc = dsi_display_mipi_host_init(display);
  4665. if (rc) {
  4666. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4667. display->name, rc);
  4668. goto error_ctrl_deinit;
  4669. }
  4670. rc = dsi_panel_drv_init(display->panel, &display->host);
  4671. if (rc) {
  4672. if (rc != -EPROBE_DEFER)
  4673. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4674. display->name, rc);
  4675. goto error_host_deinit;
  4676. }
  4677. DSI_INFO("Successfully bind display panel '%s'\n", display->name);
  4678. display->drm_dev = drm;
  4679. display_for_each_ctrl(i, display) {
  4680. display_ctrl = &display->ctrl[i];
  4681. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4682. continue;
  4683. display_ctrl->ctrl->drm_dev = drm;
  4684. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4685. &display_ctrl->ctrl->clk_freq);
  4686. if (rc) {
  4687. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4688. display->name, rc);
  4689. goto error;
  4690. }
  4691. }
  4692. /* register te irq handler */
  4693. dsi_display_register_te_irq(display);
  4694. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4695. goto error;
  4696. error_host_deinit:
  4697. (void)dsi_display_mipi_host_deinit(display);
  4698. error_clk_client_deinit:
  4699. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4700. error_clk_deinit:
  4701. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4702. error_ctrl_deinit:
  4703. for (i = i - 1; i >= 0; i--) {
  4704. display_ctrl = &display->ctrl[i];
  4705. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4706. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4707. }
  4708. (void)dsi_display_debugfs_deinit(display);
  4709. error:
  4710. mutex_unlock(&display->display_lock);
  4711. return rc;
  4712. }
  4713. /**
  4714. * dsi_display_unbind - unbind dsi from controlling device
  4715. * @dev: Pointer to base of platform device
  4716. * @master: Pointer to container of drm device
  4717. * @data: Pointer to private data
  4718. */
  4719. static void dsi_display_unbind(struct device *dev,
  4720. struct device *master, void *data)
  4721. {
  4722. struct dsi_display_ctrl *display_ctrl;
  4723. struct dsi_display *display;
  4724. struct platform_device *pdev = to_platform_device(dev);
  4725. int i, rc = 0;
  4726. if (!dev || !pdev || !master) {
  4727. DSI_ERR("invalid param(s)\n");
  4728. return;
  4729. }
  4730. display = platform_get_drvdata(pdev);
  4731. if (!display || !display->panel_node) {
  4732. DSI_ERR("invalid display\n");
  4733. return;
  4734. }
  4735. mutex_lock(&display->display_lock);
  4736. rc = dsi_display_mipi_host_deinit(display);
  4737. if (rc)
  4738. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4739. display->name,
  4740. rc);
  4741. display_for_each_ctrl(i, display) {
  4742. display_ctrl = &display->ctrl[i];
  4743. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4744. if (rc)
  4745. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4746. display->name, i, rc);
  4747. display->ctrl->ctrl->dma_cmd_workq = NULL;
  4748. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4749. if (rc)
  4750. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4751. display->name, i, rc);
  4752. }
  4753. atomic_set(&display->clkrate_change_pending, 0);
  4754. (void)dsi_display_debugfs_deinit(display);
  4755. mutex_unlock(&display->display_lock);
  4756. }
  4757. static const struct component_ops dsi_display_comp_ops = {
  4758. .bind = dsi_display_bind,
  4759. .unbind = dsi_display_unbind,
  4760. };
  4761. static struct platform_driver dsi_display_driver = {
  4762. .probe = dsi_display_dev_probe,
  4763. .remove = dsi_display_dev_remove,
  4764. .driver = {
  4765. .name = "msm-dsi-display",
  4766. .of_match_table = dsi_display_dt_match,
  4767. .suppress_bind_attrs = true,
  4768. },
  4769. };
  4770. static int dsi_display_init(struct dsi_display *display)
  4771. {
  4772. int rc = 0;
  4773. struct platform_device *pdev = display->pdev;
  4774. mutex_init(&display->display_lock);
  4775. rc = _dsi_display_dev_init(display);
  4776. if (rc) {
  4777. DSI_ERR("device init failed, rc=%d\n", rc);
  4778. goto end;
  4779. }
  4780. /*
  4781. * Vote on panel regulator is added to make sure panel regulators
  4782. * are ON for cont-splash enabled usecase.
  4783. * This panel regulator vote will be removed only in:
  4784. * 1) device suspend when cont-splash is enabled.
  4785. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4786. * For GKI, adding this vote will make sure that sync_state
  4787. * kernel driver doesn't disable the panel regulators after
  4788. * dsi probe is complete.
  4789. */
  4790. if (display->panel) {
  4791. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4792. true);
  4793. if (rc) {
  4794. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4795. display->panel->name, rc);
  4796. return rc;
  4797. }
  4798. }
  4799. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4800. if (rc)
  4801. DSI_ERR("component add failed, rc=%d\n", rc);
  4802. DSI_DEBUG("component add success: %s\n", display->name);
  4803. end:
  4804. return rc;
  4805. }
  4806. static void dsi_display_firmware_display(const struct firmware *fw,
  4807. void *context)
  4808. {
  4809. struct dsi_display *display = context;
  4810. if (fw) {
  4811. DSI_INFO("reading data from firmware, size=%zd\n",
  4812. fw->size);
  4813. display->fw = fw;
  4814. if (!strcmp(display->display_type, "primary"))
  4815. display->name = "dsi_firmware_display";
  4816. else if (!strcmp(display->display_type, "secondary"))
  4817. display->name = "dsi_firmware_display_secondary";
  4818. } else {
  4819. DSI_INFO("no firmware available, fallback to device node\n");
  4820. }
  4821. if (dsi_display_init(display))
  4822. return;
  4823. DSI_DEBUG("success\n");
  4824. }
  4825. int dsi_display_dev_probe(struct platform_device *pdev)
  4826. {
  4827. struct dsi_display *display = NULL;
  4828. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4829. int rc = 0, index = DSI_PRIMARY;
  4830. bool firm_req = false;
  4831. struct dsi_display_boot_param *boot_disp;
  4832. if (!pdev || !pdev->dev.of_node) {
  4833. DSI_ERR("pdev not found\n");
  4834. rc = -ENODEV;
  4835. goto end;
  4836. }
  4837. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4838. if (!display) {
  4839. rc = -ENOMEM;
  4840. goto end;
  4841. }
  4842. display->dma_cmd_workq = create_singlethread_workqueue(
  4843. "dsi_dma_cmd_workq");
  4844. if (!display->dma_cmd_workq) {
  4845. DSI_ERR("failed to create work queue\n");
  4846. rc = -EINVAL;
  4847. goto end;
  4848. }
  4849. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4850. if (!mdp_node) {
  4851. DSI_ERR("mdp_node not found\n");
  4852. rc = -ENODEV;
  4853. goto end;
  4854. }
  4855. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4856. "qcom,sde-trusted-vm-env");
  4857. if (display->trusted_vm_env)
  4858. DSI_INFO("Display enabled with trusted vm path\n");
  4859. /* initialize panel id to UINT64_MAX */
  4860. display->panel_id = ~0x0;
  4861. display->display_type = of_get_property(pdev->dev.of_node,
  4862. "label", NULL);
  4863. if (!display->display_type)
  4864. display->display_type = "primary";
  4865. if (!strcmp(display->display_type, "secondary"))
  4866. index = DSI_SECONDARY;
  4867. boot_disp = &boot_displays[index];
  4868. node = pdev->dev.of_node;
  4869. if (boot_disp->boot_disp_en) {
  4870. /* The panel name should be same as UEFI name index */
  4871. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4872. if (!panel_node)
  4873. DSI_WARN("panel_node %s not found\n", boot_disp->name);
  4874. } else {
  4875. panel_node = of_parse_phandle(node,
  4876. "qcom,dsi-default-panel", 0);
  4877. if (!panel_node)
  4878. DSI_WARN("default panel not found\n");
  4879. }
  4880. boot_disp->node = pdev->dev.of_node;
  4881. boot_disp->disp = display;
  4882. display->panel_node = panel_node;
  4883. display->pdev = pdev;
  4884. display->boot_disp = boot_disp;
  4885. dsi_display_parse_cmdline_topology(display, index);
  4886. platform_set_drvdata(pdev, display);
  4887. /* initialize display in firmware callback */
  4888. if (!boot_disp->boot_disp_en &&
  4889. IS_ENABLED(CONFIG_DSI_PARSER) &&
  4890. !display->trusted_vm_env) {
  4891. if (!strcmp(display->display_type, "primary"))
  4892. firm_req = !request_firmware_nowait(
  4893. THIS_MODULE, 1, "dsi_prop",
  4894. &pdev->dev, GFP_KERNEL, display,
  4895. dsi_display_firmware_display);
  4896. else if (!strcmp(display->display_type, "secondary"))
  4897. firm_req = !request_firmware_nowait(
  4898. THIS_MODULE, 1, "dsi_prop_sec",
  4899. &pdev->dev, GFP_KERNEL, display,
  4900. dsi_display_firmware_display);
  4901. }
  4902. if (!firm_req) {
  4903. rc = dsi_display_init(display);
  4904. if (rc)
  4905. goto end;
  4906. }
  4907. return 0;
  4908. end:
  4909. if (display)
  4910. devm_kfree(&pdev->dev, display);
  4911. return rc;
  4912. }
  4913. int dsi_display_dev_remove(struct platform_device *pdev)
  4914. {
  4915. int rc = 0, i = 0;
  4916. struct dsi_display *display;
  4917. struct dsi_display_ctrl *ctrl;
  4918. if (!pdev) {
  4919. DSI_ERR("Invalid device\n");
  4920. return -EINVAL;
  4921. }
  4922. display = platform_get_drvdata(pdev);
  4923. /* decrement ref count */
  4924. of_node_put(display->panel_node);
  4925. if (display->dma_cmd_workq) {
  4926. flush_workqueue(display->dma_cmd_workq);
  4927. destroy_workqueue(display->dma_cmd_workq);
  4928. display->dma_cmd_workq = NULL;
  4929. display_for_each_ctrl(i, display) {
  4930. ctrl = &display->ctrl[i];
  4931. if (!ctrl->ctrl)
  4932. continue;
  4933. ctrl->ctrl->dma_cmd_workq = NULL;
  4934. }
  4935. }
  4936. (void)_dsi_display_dev_deinit(display);
  4937. platform_set_drvdata(pdev, NULL);
  4938. devm_kfree(&pdev->dev, display);
  4939. return rc;
  4940. }
  4941. int dsi_display_get_num_of_displays(void)
  4942. {
  4943. int i, count = 0;
  4944. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  4945. struct dsi_display *display = boot_displays[i].disp;
  4946. if ((display && display->panel_node) ||
  4947. (display && display->fw))
  4948. count++;
  4949. }
  4950. return count;
  4951. }
  4952. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  4953. {
  4954. int index = 0, count = 0;
  4955. if (!display_array || !max_display_count) {
  4956. DSI_ERR("invalid params\n");
  4957. return 0;
  4958. }
  4959. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  4960. struct dsi_display *display = boot_displays[index].disp;
  4961. if ((display && display->panel_node) ||
  4962. (display && display->fw))
  4963. display_array[count++] = display;
  4964. }
  4965. return count;
  4966. }
  4967. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  4968. {
  4969. if (!display)
  4970. return;
  4971. mutex_lock(&display->display_lock);
  4972. display->is_active = is_active;
  4973. mutex_unlock(&display->display_lock);
  4974. }
  4975. int dsi_display_drm_bridge_init(struct dsi_display *display,
  4976. struct drm_encoder *enc)
  4977. {
  4978. int rc = 0;
  4979. struct dsi_bridge *bridge;
  4980. struct msm_drm_private *priv = NULL;
  4981. if (!display || !display->drm_dev || !enc) {
  4982. DSI_ERR("invalid param(s)\n");
  4983. return -EINVAL;
  4984. }
  4985. mutex_lock(&display->display_lock);
  4986. priv = display->drm_dev->dev_private;
  4987. if (!priv) {
  4988. DSI_ERR("Private data is not present\n");
  4989. rc = -EINVAL;
  4990. goto error;
  4991. }
  4992. if (display->bridge) {
  4993. DSI_ERR("display is already initialize\n");
  4994. goto error;
  4995. }
  4996. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  4997. if (IS_ERR_OR_NULL(bridge)) {
  4998. rc = PTR_ERR(bridge);
  4999. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  5000. goto error;
  5001. }
  5002. display->bridge = bridge;
  5003. priv->bridges[priv->num_bridges++] = &bridge->base;
  5004. error:
  5005. mutex_unlock(&display->display_lock);
  5006. return rc;
  5007. }
  5008. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5009. {
  5010. int rc = 0;
  5011. if (!display) {
  5012. DSI_ERR("Invalid params\n");
  5013. return -EINVAL;
  5014. }
  5015. mutex_lock(&display->display_lock);
  5016. dsi_drm_bridge_cleanup(display->bridge);
  5017. display->bridge = NULL;
  5018. mutex_unlock(&display->display_lock);
  5019. return rc;
  5020. }
  5021. /* Hook functions to call external connector, pointer validation is
  5022. * done in dsi_display_drm_ext_bridge_init.
  5023. */
  5024. static enum drm_connector_status dsi_display_drm_ext_detect(
  5025. struct drm_connector *connector,
  5026. bool force,
  5027. void *disp)
  5028. {
  5029. struct dsi_display *display = disp;
  5030. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5031. }
  5032. static int dsi_display_drm_ext_get_modes(
  5033. struct drm_connector *connector, void *disp,
  5034. const struct msm_resource_caps_info *avail_res)
  5035. {
  5036. struct dsi_display *display = disp;
  5037. struct drm_display_mode *pmode, *pt;
  5038. int count;
  5039. /* if there are modes defined in panel, ignore external modes */
  5040. if (display->panel->num_timing_nodes)
  5041. return dsi_connector_get_modes(connector, disp, avail_res);
  5042. count = display->ext_conn->helper_private->get_modes(
  5043. display->ext_conn);
  5044. list_for_each_entry_safe(pmode, pt,
  5045. &display->ext_conn->probed_modes, head) {
  5046. list_move_tail(&pmode->head, &connector->probed_modes);
  5047. }
  5048. connector->display_info = display->ext_conn->display_info;
  5049. return count;
  5050. }
  5051. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5052. struct drm_connector *connector,
  5053. struct drm_display_mode *mode,
  5054. void *disp, const struct msm_resource_caps_info *avail_res)
  5055. {
  5056. struct dsi_display *display = disp;
  5057. enum drm_mode_status status;
  5058. /* always do internal mode_valid check */
  5059. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5060. if (status != MODE_OK)
  5061. return status;
  5062. return display->ext_conn->helper_private->mode_valid(
  5063. display->ext_conn, mode);
  5064. }
  5065. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5066. void *disp,
  5067. struct drm_atomic_state *state)
  5068. {
  5069. struct dsi_display *display = disp;
  5070. struct drm_connector_state *c_state;
  5071. c_state = drm_atomic_get_new_connector_state(state, connector);
  5072. return display->ext_conn->helper_private->atomic_check(
  5073. display->ext_conn, state);
  5074. }
  5075. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5076. struct msm_display_info *info, void *disp)
  5077. {
  5078. struct dsi_display *display;
  5079. int i;
  5080. if (!info || !disp) {
  5081. DSI_ERR("invalid params\n");
  5082. return -EINVAL;
  5083. }
  5084. display = disp;
  5085. if (!display->panel) {
  5086. DSI_ERR("invalid display panel\n");
  5087. return -EINVAL;
  5088. }
  5089. mutex_lock(&display->display_lock);
  5090. memset(info, 0, sizeof(struct msm_display_info));
  5091. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5092. info->num_of_h_tiles = display->ctrl_count;
  5093. for (i = 0; i < info->num_of_h_tiles; i++)
  5094. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5095. info->is_connected = connector->status != connector_status_disconnected;
  5096. if (!strcmp(display->display_type, "primary"))
  5097. info->display_type = SDE_CONNECTOR_PRIMARY;
  5098. else if (!strcmp(display->display_type, "secondary"))
  5099. info->display_type = SDE_CONNECTOR_SECONDARY;
  5100. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5101. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5102. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5103. mutex_unlock(&display->display_lock);
  5104. return 0;
  5105. }
  5106. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5107. const struct drm_display_mode *drm_mode,
  5108. struct msm_mode_info *mode_info,
  5109. void *display, const struct msm_resource_caps_info *avail_res)
  5110. {
  5111. struct msm_display_topology *topology;
  5112. if (!drm_mode || !mode_info ||
  5113. !avail_res || !avail_res->max_mixer_width)
  5114. return -EINVAL;
  5115. memset(mode_info, 0, sizeof(*mode_info));
  5116. mode_info->frame_rate = drm_mode->vrefresh;
  5117. mode_info->vtotal = drm_mode->vtotal;
  5118. topology = &mode_info->topology;
  5119. topology->num_lm = (avail_res->max_mixer_width
  5120. <= drm_mode->hdisplay) ? 2 : 1;
  5121. topology->num_enc = 0;
  5122. topology->num_intf = topology->num_lm;
  5123. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5124. return 0;
  5125. }
  5126. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5127. struct drm_bridge *bridge)
  5128. {
  5129. struct msm_drm_private *priv;
  5130. struct sde_kms *sde_kms;
  5131. struct drm_connector *conn;
  5132. struct drm_connector_list_iter conn_iter;
  5133. struct sde_connector *sde_conn;
  5134. struct dsi_display *display;
  5135. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5136. int i;
  5137. if (!bridge || !bridge->encoder) {
  5138. SDE_ERROR("invalid argument\n");
  5139. return NULL;
  5140. }
  5141. priv = bridge->dev->dev_private;
  5142. sde_kms = to_sde_kms(priv->kms);
  5143. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5144. drm_for_each_connector_iter(conn, &conn_iter) {
  5145. sde_conn = to_sde_connector(conn);
  5146. if (sde_conn->encoder == bridge->encoder) {
  5147. display = sde_conn->display;
  5148. display_for_each_ctrl(i, display) {
  5149. if (display->ext_bridge[i].bridge == bridge) {
  5150. dsi_bridge = &display->ext_bridge[i];
  5151. break;
  5152. }
  5153. }
  5154. }
  5155. }
  5156. drm_connector_list_iter_end(&conn_iter);
  5157. return dsi_bridge;
  5158. }
  5159. static void dsi_display_drm_ext_adjust_timing(
  5160. const struct dsi_display *display,
  5161. struct drm_display_mode *mode)
  5162. {
  5163. mode->hdisplay /= display->ctrl_count;
  5164. mode->hsync_start /= display->ctrl_count;
  5165. mode->hsync_end /= display->ctrl_count;
  5166. mode->htotal /= display->ctrl_count;
  5167. mode->hskew /= display->ctrl_count;
  5168. mode->clock /= display->ctrl_count;
  5169. }
  5170. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5171. struct drm_bridge *bridge,
  5172. const struct drm_display_mode *mode)
  5173. {
  5174. struct dsi_display_ext_bridge *ext_bridge;
  5175. struct drm_display_mode tmp;
  5176. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5177. if (!ext_bridge)
  5178. return MODE_ERROR;
  5179. tmp = *mode;
  5180. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5181. return ext_bridge->orig_funcs->mode_valid(bridge, &tmp);
  5182. }
  5183. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5184. struct drm_bridge *bridge,
  5185. const struct drm_display_mode *mode,
  5186. struct drm_display_mode *adjusted_mode)
  5187. {
  5188. struct dsi_display_ext_bridge *ext_bridge;
  5189. struct drm_display_mode tmp;
  5190. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5191. if (!ext_bridge)
  5192. return false;
  5193. tmp = *mode;
  5194. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5195. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5196. }
  5197. static void dsi_display_drm_ext_bridge_mode_set(
  5198. struct drm_bridge *bridge,
  5199. const struct drm_display_mode *mode,
  5200. const struct drm_display_mode *adjusted_mode)
  5201. {
  5202. struct dsi_display_ext_bridge *ext_bridge;
  5203. struct drm_display_mode tmp;
  5204. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5205. if (!ext_bridge)
  5206. return;
  5207. tmp = *mode;
  5208. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5209. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5210. }
  5211. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5212. struct mipi_dsi_device *dsi)
  5213. {
  5214. struct dsi_display *display = to_dsi_display(host);
  5215. struct dsi_panel *panel;
  5216. if (!host || !dsi || !display->panel) {
  5217. DSI_ERR("Invalid param\n");
  5218. return -EINVAL;
  5219. }
  5220. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5221. dsi->name, dsi->channel, dsi->lanes,
  5222. dsi->format, dsi->mode_flags);
  5223. panel = display->panel;
  5224. panel->host_config.data_lanes = 0;
  5225. if (dsi->lanes > 0)
  5226. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5227. if (dsi->lanes > 1)
  5228. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5229. if (dsi->lanes > 2)
  5230. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5231. if (dsi->lanes > 3)
  5232. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5233. switch (dsi->format) {
  5234. case MIPI_DSI_FMT_RGB888:
  5235. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5236. break;
  5237. case MIPI_DSI_FMT_RGB666:
  5238. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5239. break;
  5240. case MIPI_DSI_FMT_RGB666_PACKED:
  5241. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5242. break;
  5243. case MIPI_DSI_FMT_RGB565:
  5244. default:
  5245. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5246. break;
  5247. }
  5248. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5249. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5250. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5251. panel->video_config.traffic_mode =
  5252. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5253. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5254. panel->video_config.traffic_mode =
  5255. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5256. else
  5257. panel->video_config.traffic_mode =
  5258. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5259. panel->video_config.hsa_lp11_en =
  5260. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5261. panel->video_config.hbp_lp11_en =
  5262. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5263. panel->video_config.hfp_lp11_en =
  5264. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5265. panel->video_config.pulse_mode_hsa_he =
  5266. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5267. panel->video_config.bllp_lp11_en =
  5268. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BLLP;
  5269. panel->video_config.eof_bllp_lp11_en =
  5270. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_EOF_BLLP;
  5271. } else {
  5272. panel->panel_mode = DSI_OP_CMD_MODE;
  5273. DSI_ERR("command mode not supported by ext bridge\n");
  5274. return -ENOTSUPP;
  5275. }
  5276. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5277. return 0;
  5278. }
  5279. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5280. .attach = dsi_host_ext_attach,
  5281. .detach = dsi_host_detach,
  5282. .transfer = dsi_host_transfer,
  5283. };
  5284. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5285. {
  5286. if (!display || !display->panel) {
  5287. pr_err("invalid param(s)\n");
  5288. return NULL;
  5289. }
  5290. return &display->panel->drm_panel;
  5291. }
  5292. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5293. struct drm_encoder *encoder, struct drm_connector *connector)
  5294. {
  5295. struct drm_device *drm;
  5296. struct drm_bridge *bridge;
  5297. struct drm_bridge *ext_bridge;
  5298. struct drm_connector *ext_conn;
  5299. struct sde_connector *sde_conn;
  5300. struct drm_bridge *prev_bridge;
  5301. int rc = 0, i;
  5302. if (!display || !encoder || !connector)
  5303. return -EINVAL;
  5304. drm = encoder->dev;
  5305. bridge = encoder->bridge;
  5306. sde_conn = to_sde_connector(connector);
  5307. prev_bridge = bridge;
  5308. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5309. return 0;
  5310. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5311. struct dsi_display_ext_bridge *ext_bridge_info =
  5312. &display->ext_bridge[i];
  5313. /* return if ext bridge is already initialized */
  5314. if (ext_bridge_info->bridge)
  5315. return 0;
  5316. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5317. if (IS_ERR_OR_NULL(ext_bridge)) {
  5318. rc = PTR_ERR(ext_bridge);
  5319. DSI_ERR("failed to find ext bridge\n");
  5320. goto error;
  5321. }
  5322. /* override functions for mode adjustment */
  5323. if (display->ext_bridge_cnt > 1) {
  5324. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5325. if (ext_bridge->funcs->mode_fixup)
  5326. ext_bridge_info->bridge_funcs.mode_fixup =
  5327. dsi_display_drm_ext_bridge_mode_fixup;
  5328. if (ext_bridge->funcs->mode_valid)
  5329. ext_bridge_info->bridge_funcs.mode_valid =
  5330. dsi_display_drm_ext_bridge_mode_valid;
  5331. if (ext_bridge->funcs->mode_set)
  5332. ext_bridge_info->bridge_funcs.mode_set =
  5333. dsi_display_drm_ext_bridge_mode_set;
  5334. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5335. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5336. }
  5337. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge);
  5338. if (rc) {
  5339. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5340. display->name, rc);
  5341. goto error;
  5342. }
  5343. ext_bridge_info->display = display;
  5344. ext_bridge_info->bridge = ext_bridge;
  5345. prev_bridge = ext_bridge;
  5346. /* ext bridge will init its own connector during attach,
  5347. * we need to extract it out of the connector list
  5348. */
  5349. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5350. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5351. struct drm_connector, head);
  5352. if (ext_conn && ext_conn != connector &&
  5353. ext_conn->encoder_ids[0] == bridge->encoder->base.id) {
  5354. list_del_init(&ext_conn->head);
  5355. display->ext_conn = ext_conn;
  5356. }
  5357. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5358. /* if there is no valid external connector created, or in split
  5359. * mode, default setting is used from panel defined in DT file.
  5360. */
  5361. if (!display->ext_conn ||
  5362. !display->ext_conn->funcs ||
  5363. !display->ext_conn->helper_private ||
  5364. display->ext_bridge_cnt > 1) {
  5365. display->ext_conn = NULL;
  5366. continue;
  5367. }
  5368. /* otherwise, hook up the functions to use external connector */
  5369. if (display->ext_conn->funcs->detect)
  5370. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5371. if (display->ext_conn->helper_private->get_modes)
  5372. sde_conn->ops.get_modes =
  5373. dsi_display_drm_ext_get_modes;
  5374. if (display->ext_conn->helper_private->mode_valid)
  5375. sde_conn->ops.mode_valid =
  5376. dsi_display_drm_ext_mode_valid;
  5377. if (display->ext_conn->helper_private->atomic_check)
  5378. sde_conn->ops.atomic_check =
  5379. dsi_display_drm_ext_atomic_check;
  5380. sde_conn->ops.get_info =
  5381. dsi_display_ext_get_info;
  5382. sde_conn->ops.get_mode_info =
  5383. dsi_display_ext_get_mode_info;
  5384. /* add support to attach/detach */
  5385. display->host.ops = &dsi_host_ext_ops;
  5386. }
  5387. return 0;
  5388. error:
  5389. return rc;
  5390. }
  5391. int dsi_display_get_info(struct drm_connector *connector,
  5392. struct msm_display_info *info, void *disp)
  5393. {
  5394. struct dsi_display *display;
  5395. struct dsi_panel_phy_props phy_props;
  5396. struct dsi_host_common_cfg *host;
  5397. int i, rc;
  5398. if (!info || !disp) {
  5399. DSI_ERR("invalid params\n");
  5400. return -EINVAL;
  5401. }
  5402. display = disp;
  5403. if (!display->panel) {
  5404. DSI_ERR("invalid display panel\n");
  5405. return -EINVAL;
  5406. }
  5407. mutex_lock(&display->display_lock);
  5408. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5409. if (rc) {
  5410. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5411. display->name, rc);
  5412. goto error;
  5413. }
  5414. memset(info, 0, sizeof(struct msm_display_info));
  5415. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5416. info->num_of_h_tiles = display->ctrl_count;
  5417. for (i = 0; i < info->num_of_h_tiles; i++)
  5418. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5419. info->is_connected = display->is_active;
  5420. if (!strcmp(display->display_type, "primary"))
  5421. info->display_type = SDE_CONNECTOR_PRIMARY;
  5422. else if (!strcmp(display->display_type, "secondary"))
  5423. info->display_type = SDE_CONNECTOR_SECONDARY;
  5424. info->width_mm = phy_props.panel_width_mm;
  5425. info->height_mm = phy_props.panel_height_mm;
  5426. info->max_width = 1920;
  5427. info->max_height = 1080;
  5428. info->qsync_min_fps =
  5429. display->panel->qsync_min_fps;
  5430. info->poms_align_vsync = display->panel->poms_align_vsync;
  5431. switch (display->panel->panel_mode) {
  5432. case DSI_OP_VIDEO_MODE:
  5433. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5434. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5435. if (display->panel->panel_mode_switch_enabled)
  5436. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5437. break;
  5438. case DSI_OP_CMD_MODE:
  5439. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5440. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5441. if (display->panel->panel_mode_switch_enabled)
  5442. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5443. info->is_te_using_watchdog_timer =
  5444. display->panel->te_using_watchdog_timer |
  5445. display->sw_te_using_wd;
  5446. break;
  5447. default:
  5448. DSI_ERR("unknwown dsi panel mode %d\n",
  5449. display->panel->panel_mode);
  5450. break;
  5451. }
  5452. if (display->panel->esd_config.esd_enabled &&
  5453. !display->sw_te_using_wd)
  5454. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5455. info->te_source = display->te_source;
  5456. host = &display->panel->host_config;
  5457. if (host->split_link.split_link_enabled)
  5458. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5459. info->dsc_count = display->panel->dsc_count;
  5460. info->lm_count = display->panel->lm_count;
  5461. error:
  5462. mutex_unlock(&display->display_lock);
  5463. return rc;
  5464. }
  5465. int dsi_display_get_mode_count(struct dsi_display *display,
  5466. u32 *count)
  5467. {
  5468. if (!display || !display->panel) {
  5469. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5470. display ? display->panel != NULL : 0);
  5471. return -EINVAL;
  5472. }
  5473. mutex_lock(&display->display_lock);
  5474. *count = display->panel->num_display_modes;
  5475. mutex_unlock(&display->display_lock);
  5476. return 0;
  5477. }
  5478. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5479. struct dsi_display_mode *dsi_mode,
  5480. int lanes, int bpp)
  5481. {
  5482. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5483. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5484. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5485. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5486. /* Constant FPS is not supported on command mode */
  5487. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  5488. return;
  5489. if (!dyn_clk_caps->maintain_const_fps)
  5490. return;
  5491. /*
  5492. * When there is a dynamic clock switch, there is small change
  5493. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5494. * is adjusted. It has been assumed that the refined porch values
  5495. * are supported by the panel. This logic can be enhanced further
  5496. * in future by taking min/max porches supported by the panel.
  5497. */
  5498. switch (dyn_clk_caps->type) {
  5499. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5500. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5501. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5502. do_div(old_htotal, display->ctrl_count);
  5503. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5504. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5505. if (dsi_display_is_type_cphy(display)) {
  5506. new_htotal = new_htotal * bits_per_symbol;
  5507. div = div * num_of_symbols;
  5508. }
  5509. do_div(new_htotal, div);
  5510. if (old_htotal > new_htotal)
  5511. dsi_mode->timing.h_front_porch -=
  5512. ((old_htotal - new_htotal) * display->ctrl_count);
  5513. else
  5514. dsi_mode->timing.h_front_porch +=
  5515. ((new_htotal - old_htotal) * display->ctrl_count);
  5516. break;
  5517. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5518. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5519. do_div(htotal, display->ctrl_count);
  5520. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5521. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5522. if (dsi_display_is_type_cphy(display)) {
  5523. new_vtotal = new_vtotal * bits_per_symbol;
  5524. div = div * num_of_symbols;
  5525. }
  5526. do_div(new_vtotal, div);
  5527. dsi_mode->timing.v_front_porch = new_vtotal -
  5528. dsi_mode->timing.v_back_porch -
  5529. dsi_mode->timing.v_sync_width -
  5530. dsi_mode->timing.v_active;
  5531. break;
  5532. default:
  5533. break;
  5534. }
  5535. }
  5536. static void _dsi_display_populate_bit_clks(struct dsi_display *display,
  5537. int start, int end, u32 *mode_idx)
  5538. {
  5539. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5540. struct dsi_display_mode *src, *dst;
  5541. struct dsi_host_common_cfg *cfg;
  5542. struct dsi_display_mode_priv_info *priv_info;
  5543. int i, j, total_modes, bpp, lanes = 0;
  5544. size_t size = 0;
  5545. if (!display || !mode_idx)
  5546. return;
  5547. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5548. if (!dyn_clk_caps->dyn_clk_support)
  5549. return;
  5550. cfg = &(display->panel->host_config);
  5551. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5552. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5553. lanes++;
  5554. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5555. lanes++;
  5556. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5557. lanes++;
  5558. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5559. lanes++;
  5560. total_modes = display->panel->num_display_modes;
  5561. for (i = start; i < end; i++) {
  5562. src = &display->modes[i];
  5563. if (!src)
  5564. return;
  5565. /*
  5566. * TODO: currently setting the first bit rate in
  5567. * the list as preferred rate. But ideally should
  5568. * be based on user or device tree preferrence.
  5569. */
  5570. src->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[0];
  5571. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5572. src->pixel_clk_khz =
  5573. div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5574. src->pixel_clk_khz /= 1000;
  5575. src->pixel_clk_khz *= display->ctrl_count;
  5576. }
  5577. for (i = 1; i < dyn_clk_caps->bit_clk_list_len; i++) {
  5578. if (*mode_idx >= total_modes)
  5579. return;
  5580. for (j = start; j < end; j++) {
  5581. src = &display->modes[j];
  5582. dst = &display->modes[*mode_idx];
  5583. if (!src || !dst) {
  5584. DSI_ERR("invalid mode index\n");
  5585. return;
  5586. }
  5587. memcpy(dst, src, sizeof(struct dsi_display_mode));
  5588. size = sizeof(struct dsi_display_mode_priv_info);
  5589. priv_info = kzalloc(size, GFP_KERNEL);
  5590. dst->priv_info = priv_info;
  5591. if (dst->priv_info)
  5592. memcpy(dst->priv_info, src->priv_info, size);
  5593. dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i];
  5594. dsi_display_adjust_mode_timing(display, dst, lanes,
  5595. bpp);
  5596. dst->pixel_clk_khz =
  5597. div_u64(dst->timing.clk_rate_hz * lanes, bpp);
  5598. dst->pixel_clk_khz /= 1000;
  5599. dst->pixel_clk_khz *= display->ctrl_count;
  5600. (*mode_idx)++;
  5601. }
  5602. }
  5603. }
  5604. void dsi_display_put_mode(struct dsi_display *display,
  5605. struct dsi_display_mode *mode)
  5606. {
  5607. dsi_panel_put_mode(mode);
  5608. }
  5609. int dsi_display_get_modes(struct dsi_display *display,
  5610. struct dsi_display_mode **out_modes)
  5611. {
  5612. struct dsi_dfps_capabilities dfps_caps;
  5613. struct dsi_display_ctrl *ctrl;
  5614. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5615. bool is_split_link, is_cmd_mode;
  5616. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5617. u32 sublinks_count, mode_idx, array_idx = 0;
  5618. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5619. int i, start, end, rc = -EINVAL;
  5620. if (!display || !out_modes) {
  5621. DSI_ERR("Invalid params\n");
  5622. return -EINVAL;
  5623. }
  5624. *out_modes = NULL;
  5625. ctrl = &display->ctrl[0];
  5626. mutex_lock(&display->display_lock);
  5627. if (display->modes)
  5628. goto exit;
  5629. display_mode_count = display->panel->num_display_modes;
  5630. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5631. GFP_KERNEL);
  5632. if (!display->modes) {
  5633. rc = -ENOMEM;
  5634. goto error;
  5635. }
  5636. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5637. if (rc) {
  5638. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5639. display->name);
  5640. goto error;
  5641. }
  5642. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5643. timing_mode_count = display->panel->num_timing_nodes;
  5644. /* Validate command line timing */
  5645. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5646. (display->cmdline_timing >= timing_mode_count))
  5647. display->cmdline_timing = NO_OVERRIDE;
  5648. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5649. struct dsi_display_mode display_mode;
  5650. int topology_override = NO_OVERRIDE;
  5651. bool is_preferred = false;
  5652. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5653. if (display->cmdline_timing == mode_idx) {
  5654. topology_override = display->cmdline_topology;
  5655. is_preferred = true;
  5656. }
  5657. memset(&display_mode, 0, sizeof(display_mode));
  5658. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5659. &display_mode,
  5660. topology_override);
  5661. if (rc) {
  5662. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5663. display->name, mode_idx);
  5664. goto error;
  5665. }
  5666. is_cmd_mode = (display_mode.panel_mode == DSI_OP_CMD_MODE);
  5667. /* Setup widebus support */
  5668. display_mode.priv_info->widebus_support =
  5669. ctrl->ctrl->hw.widebus_support;
  5670. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5671. is_cmd_mode) ? 1 : dfps_caps.dfps_list_len);
  5672. /* Calculate dsi frame transfer time */
  5673. if (is_cmd_mode) {
  5674. dsi_panel_calc_dsi_transfer_time(
  5675. &display->panel->host_config,
  5676. &display_mode, frame_threshold_us);
  5677. display_mode.priv_info->dsi_transfer_time_us =
  5678. display_mode.timing.dsi_transfer_time_us;
  5679. display_mode.priv_info->min_dsi_clk_hz =
  5680. display_mode.timing.min_dsi_clk_hz;
  5681. display_mode.priv_info->mdp_transfer_time_us =
  5682. display_mode.timing.mdp_transfer_time_us;
  5683. }
  5684. is_split_link = host->split_link.split_link_enabled;
  5685. sublinks_count = host->split_link.num_sublinks;
  5686. if (is_split_link && sublinks_count > 1) {
  5687. display_mode.timing.h_active *= sublinks_count;
  5688. display_mode.timing.h_front_porch *= sublinks_count;
  5689. display_mode.timing.h_sync_width *= sublinks_count;
  5690. display_mode.timing.h_back_porch *= sublinks_count;
  5691. display_mode.timing.h_skew *= sublinks_count;
  5692. display_mode.pixel_clk_khz *= sublinks_count;
  5693. } else {
  5694. display_mode.timing.h_active *= display->ctrl_count;
  5695. display_mode.timing.h_front_porch *=
  5696. display->ctrl_count;
  5697. display_mode.timing.h_sync_width *=
  5698. display->ctrl_count;
  5699. display_mode.timing.h_back_porch *=
  5700. display->ctrl_count;
  5701. display_mode.timing.h_skew *= display->ctrl_count;
  5702. display_mode.pixel_clk_khz *= display->ctrl_count;
  5703. }
  5704. start = array_idx;
  5705. for (i = 0; i < num_dfps_rates; i++) {
  5706. struct dsi_display_mode *sub_mode =
  5707. &display->modes[array_idx];
  5708. u32 curr_refresh_rate;
  5709. if (!sub_mode) {
  5710. DSI_ERR("invalid mode data\n");
  5711. rc = -EFAULT;
  5712. goto error;
  5713. }
  5714. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5715. array_idx++;
  5716. if (!dfps_caps.dfps_support || is_cmd_mode)
  5717. continue;
  5718. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5719. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5720. dsi_display_get_dfps_timing(display, sub_mode,
  5721. curr_refresh_rate);
  5722. }
  5723. end = array_idx;
  5724. /*
  5725. * if POMS is enabled and boot up mode is video mode,
  5726. * skip bit clk rates update for command mode,
  5727. * else if dynamic clk switch is supported then update all
  5728. * the bit clk rates.
  5729. */
  5730. if (is_cmd_mode &&
  5731. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  5732. continue;
  5733. _dsi_display_populate_bit_clks(display, start, end, &array_idx);
  5734. if (is_preferred) {
  5735. /* Set first timing sub mode as preferred mode */
  5736. display->modes[start].is_preferred = true;
  5737. }
  5738. }
  5739. exit:
  5740. *out_modes = display->modes;
  5741. rc = 0;
  5742. error:
  5743. if (rc)
  5744. kfree(display->modes);
  5745. mutex_unlock(&display->display_lock);
  5746. return rc;
  5747. }
  5748. int dsi_display_get_panel_vfp(void *dsi_display,
  5749. int h_active, int v_active)
  5750. {
  5751. int i, rc = 0;
  5752. u32 count, refresh_rate = 0;
  5753. struct dsi_dfps_capabilities dfps_caps;
  5754. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5755. struct dsi_host_common_cfg *host;
  5756. if (!display || !display->panel)
  5757. return -EINVAL;
  5758. mutex_lock(&display->display_lock);
  5759. count = display->panel->num_display_modes;
  5760. if (display->panel->cur_mode)
  5761. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5762. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5763. if (dfps_caps.dfps_support)
  5764. refresh_rate = dfps_caps.max_refresh_rate;
  5765. if (!refresh_rate) {
  5766. mutex_unlock(&display->display_lock);
  5767. DSI_ERR("Null Refresh Rate\n");
  5768. return -EINVAL;
  5769. }
  5770. host = &display->panel->host_config;
  5771. if (host->split_link.split_link_enabled)
  5772. h_active *= host->split_link.num_sublinks;
  5773. else
  5774. h_active *= display->ctrl_count;
  5775. for (i = 0; i < count; i++) {
  5776. struct dsi_display_mode *m = &display->modes[i];
  5777. if (m && v_active == m->timing.v_active &&
  5778. h_active == m->timing.h_active &&
  5779. refresh_rate == m->timing.refresh_rate) {
  5780. rc = m->timing.v_front_porch;
  5781. break;
  5782. }
  5783. }
  5784. mutex_unlock(&display->display_lock);
  5785. return rc;
  5786. }
  5787. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5788. {
  5789. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5790. u32 count, i;
  5791. int rc = 0;
  5792. *num_lm = 0;
  5793. mutex_lock(&display->display_lock);
  5794. count = display->panel->num_display_modes;
  5795. mutex_unlock(&display->display_lock);
  5796. if (!display->modes) {
  5797. struct dsi_display_mode *m;
  5798. rc = dsi_display_get_modes(display, &m);
  5799. if (rc)
  5800. return rc;
  5801. }
  5802. mutex_lock(&display->display_lock);
  5803. for (i = 0; i < count; i++) {
  5804. struct dsi_display_mode *m = &display->modes[i];
  5805. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5806. }
  5807. mutex_unlock(&display->display_lock);
  5808. return rc;
  5809. }
  5810. int dsi_display_find_mode(struct dsi_display *display,
  5811. const struct dsi_display_mode *cmp,
  5812. struct dsi_display_mode **out_mode)
  5813. {
  5814. u32 count, i;
  5815. int rc;
  5816. if (!display || !out_mode)
  5817. return -EINVAL;
  5818. *out_mode = NULL;
  5819. mutex_lock(&display->display_lock);
  5820. count = display->panel->num_display_modes;
  5821. mutex_unlock(&display->display_lock);
  5822. if (!display->modes) {
  5823. struct dsi_display_mode *m;
  5824. rc = dsi_display_get_modes(display, &m);
  5825. if (rc)
  5826. return rc;
  5827. }
  5828. mutex_lock(&display->display_lock);
  5829. for (i = 0; i < count; i++) {
  5830. struct dsi_display_mode *m = &display->modes[i];
  5831. if (cmp->timing.v_active == m->timing.v_active &&
  5832. cmp->timing.h_active == m->timing.h_active &&
  5833. cmp->timing.refresh_rate == m->timing.refresh_rate &&
  5834. cmp->panel_mode == m->panel_mode &&
  5835. cmp->pixel_clk_khz == m->pixel_clk_khz) {
  5836. *out_mode = m;
  5837. rc = 0;
  5838. break;
  5839. }
  5840. }
  5841. mutex_unlock(&display->display_lock);
  5842. if (!*out_mode) {
  5843. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  5844. display->name, cmp->timing.v_active,
  5845. cmp->timing.h_active, cmp->timing.refresh_rate,
  5846. cmp->pixel_clk_khz);
  5847. rc = -ENOENT;
  5848. }
  5849. return rc;
  5850. }
  5851. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  5852. struct dsi_display_mode *adj)
  5853. {
  5854. /*
  5855. * If there is a change in the hfp or vfp of the current and adjoining
  5856. * mode,then either it is a dfps mode switch or dynamic clk change with
  5857. * constant fps.
  5858. */
  5859. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  5860. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  5861. return true;
  5862. else
  5863. return false;
  5864. }
  5865. /**
  5866. * dsi_display_validate_mode_change() - Validate mode change case.
  5867. * @display: DSI display handle.
  5868. * @cur_mode: Current mode.
  5869. * @adj_mode: Mode to be set.
  5870. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  5871. * is change in hfp or vfp but vactive and hactive are same.
  5872. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  5873. * is change in clk but vactive and hactive are same.
  5874. * Return: error code.
  5875. */
  5876. int dsi_display_validate_mode_change(struct dsi_display *display,
  5877. struct dsi_display_mode *cur_mode,
  5878. struct dsi_display_mode *adj_mode)
  5879. {
  5880. int rc = 0;
  5881. struct dsi_dfps_capabilities dfps_caps;
  5882. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5883. if (!display || !adj_mode) {
  5884. DSI_ERR("Invalid params\n");
  5885. return -EINVAL;
  5886. }
  5887. if (!display->panel || !display->panel->cur_mode) {
  5888. DSI_DEBUG("Current panel mode not set\n");
  5889. return rc;
  5890. }
  5891. mutex_lock(&display->display_lock);
  5892. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5893. if ((cur_mode->timing.v_active == adj_mode->timing.v_active) &&
  5894. (cur_mode->timing.h_active == adj_mode->timing.h_active) &&
  5895. (cur_mode->panel_mode == adj_mode->panel_mode)) {
  5896. /* dfps and dynamic clock with const fps use case */
  5897. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  5898. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5899. if (dfps_caps.dfps_support ||
  5900. dyn_clk_caps->maintain_const_fps) {
  5901. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  5902. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  5903. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1,
  5904. cur_mode->timing.refresh_rate,
  5905. adj_mode->timing.refresh_rate,
  5906. cur_mode->timing.h_front_porch,
  5907. adj_mode->timing.h_front_porch,
  5908. cur_mode->timing.v_front_porch,
  5909. adj_mode->timing.v_front_porch);
  5910. }
  5911. }
  5912. /* dynamic clk change use case */
  5913. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  5914. if (dyn_clk_caps->dyn_clk_support) {
  5915. DSI_DEBUG("dynamic clk change detected\n");
  5916. if ((adj_mode->dsi_mode_flags &
  5917. DSI_MODE_FLAG_VRR) &&
  5918. (!dyn_clk_caps->maintain_const_fps)) {
  5919. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  5920. rc = -ENOTSUPP;
  5921. goto error;
  5922. }
  5923. adj_mode->dsi_mode_flags |=
  5924. DSI_MODE_FLAG_DYN_CLK;
  5925. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2,
  5926. cur_mode->pixel_clk_khz,
  5927. adj_mode->pixel_clk_khz);
  5928. }
  5929. }
  5930. }
  5931. error:
  5932. mutex_unlock(&display->display_lock);
  5933. return rc;
  5934. }
  5935. int dsi_display_validate_mode(struct dsi_display *display,
  5936. struct dsi_display_mode *mode,
  5937. u32 flags)
  5938. {
  5939. int rc = 0;
  5940. int i;
  5941. struct dsi_display_ctrl *ctrl;
  5942. struct dsi_display_mode adj_mode;
  5943. if (!display || !mode) {
  5944. DSI_ERR("Invalid params\n");
  5945. return -EINVAL;
  5946. }
  5947. mutex_lock(&display->display_lock);
  5948. adj_mode = *mode;
  5949. adjust_timing_by_ctrl_count(display, &adj_mode);
  5950. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  5951. if (rc) {
  5952. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  5953. display->name, rc);
  5954. goto error;
  5955. }
  5956. display_for_each_ctrl(i, display) {
  5957. ctrl = &display->ctrl[i];
  5958. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  5959. if (rc) {
  5960. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  5961. display->name, rc);
  5962. goto error;
  5963. }
  5964. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  5965. if (rc) {
  5966. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  5967. display->name, rc);
  5968. goto error;
  5969. }
  5970. }
  5971. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  5972. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  5973. rc = dsi_display_validate_mode_seamless(display, mode);
  5974. if (rc) {
  5975. DSI_ERR("[%s] seamless not possible rc=%d\n",
  5976. display->name, rc);
  5977. goto error;
  5978. }
  5979. }
  5980. error:
  5981. mutex_unlock(&display->display_lock);
  5982. return rc;
  5983. }
  5984. int dsi_display_set_mode(struct dsi_display *display,
  5985. struct dsi_display_mode *mode,
  5986. u32 flags)
  5987. {
  5988. int rc = 0;
  5989. struct dsi_display_mode adj_mode;
  5990. struct dsi_mode_info timing;
  5991. if (!display || !mode || !display->panel) {
  5992. DSI_ERR("Invalid params\n");
  5993. return -EINVAL;
  5994. }
  5995. mutex_lock(&display->display_lock);
  5996. adj_mode = *mode;
  5997. timing = adj_mode.timing;
  5998. adjust_timing_by_ctrl_count(display, &adj_mode);
  5999. if (!display->panel->cur_mode) {
  6000. display->panel->cur_mode =
  6001. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6002. if (!display->panel->cur_mode) {
  6003. rc = -ENOMEM;
  6004. goto error;
  6005. }
  6006. }
  6007. /*For dynamic DSI setting, use specified clock rate */
  6008. if (display->cached_clk_rate > 0)
  6009. adj_mode.priv_info->clk_rate_hz = display->cached_clk_rate;
  6010. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6011. if (rc) {
  6012. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6013. goto error;
  6014. }
  6015. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6016. if (rc) {
  6017. DSI_ERR("[%s] failed to set mode\n", display->name);
  6018. goto error;
  6019. }
  6020. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d\n",
  6021. adj_mode.priv_info->mdp_transfer_time_us,
  6022. timing.h_active, timing.v_active, timing.refresh_rate);
  6023. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6024. timing.h_active, timing.v_active, timing.refresh_rate);
  6025. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6026. error:
  6027. mutex_unlock(&display->display_lock);
  6028. return rc;
  6029. }
  6030. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  6031. {
  6032. int rc = 0;
  6033. int i;
  6034. struct dsi_display_ctrl *ctrl;
  6035. if (!display) {
  6036. DSI_ERR("Invalid params\n");
  6037. return -EINVAL;
  6038. }
  6039. display_for_each_ctrl(i, display) {
  6040. ctrl = &display->ctrl[i];
  6041. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  6042. if (rc) {
  6043. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  6044. display->name, i);
  6045. goto error;
  6046. }
  6047. }
  6048. display->is_tpg_enabled = enable;
  6049. error:
  6050. return rc;
  6051. }
  6052. static int dsi_display_pre_switch(struct dsi_display *display)
  6053. {
  6054. int rc = 0;
  6055. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6056. DSI_CORE_CLK, DSI_CLK_ON);
  6057. if (rc) {
  6058. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6059. display->name, rc);
  6060. goto error;
  6061. }
  6062. rc = dsi_display_ctrl_update(display);
  6063. if (rc) {
  6064. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6065. display->name, rc);
  6066. goto error_ctrl_clk_off;
  6067. }
  6068. if (!display->trusted_vm_env) {
  6069. rc = dsi_display_set_clk_src(display);
  6070. if (rc) {
  6071. DSI_ERR(
  6072. "[%s] failed to set DSI link clock source, rc=%d\n",
  6073. display->name, rc);
  6074. goto error_ctrl_deinit;
  6075. }
  6076. }
  6077. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6078. DSI_LINK_CLK, DSI_CLK_ON);
  6079. if (rc) {
  6080. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6081. display->name, rc);
  6082. goto error_ctrl_deinit;
  6083. }
  6084. goto error;
  6085. error_ctrl_deinit:
  6086. (void)dsi_display_ctrl_deinit(display);
  6087. error_ctrl_clk_off:
  6088. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6089. DSI_CORE_CLK, DSI_CLK_OFF);
  6090. error:
  6091. return rc;
  6092. }
  6093. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6094. {
  6095. int i;
  6096. struct dsi_display_ctrl *ctrl;
  6097. display_for_each_ctrl(i, display) {
  6098. ctrl = &display->ctrl[i];
  6099. if (!ctrl->ctrl)
  6100. continue;
  6101. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6102. return false;
  6103. }
  6104. return true;
  6105. }
  6106. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6107. {
  6108. struct dsi_display *display = NULL;
  6109. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6110. if (!display || !display->panel ||
  6111. atomic_read(&display->panel->esd_recovery_pending)) {
  6112. DSI_DEBUG("Invalid recovery use case\n");
  6113. return;
  6114. }
  6115. mutex_lock(&display->display_lock);
  6116. if (!_dsi_display_validate_host_state(display)) {
  6117. mutex_unlock(&display->display_lock);
  6118. return;
  6119. }
  6120. DSI_INFO("handle DSI FIFO underflow error\n");
  6121. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6122. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6123. DSI_ALL_CLKS, DSI_CLK_ON);
  6124. dsi_display_soft_reset(display);
  6125. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6126. DSI_ALL_CLKS, DSI_CLK_OFF);
  6127. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6128. mutex_unlock(&display->display_lock);
  6129. }
  6130. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6131. {
  6132. struct dsi_display *display = NULL;
  6133. struct dsi_display_ctrl *ctrl;
  6134. int i, rc;
  6135. int mask = BIT(20); /* clock lane */
  6136. int (*cb_func)(void *event_usr_ptr,
  6137. uint32_t event_idx, uint32_t instance_idx,
  6138. uint32_t data0, uint32_t data1,
  6139. uint32_t data2, uint32_t data3);
  6140. void *data;
  6141. u32 version = 0;
  6142. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6143. if (!display || !display->panel ||
  6144. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6145. atomic_read(&display->panel->esd_recovery_pending)) {
  6146. DSI_DEBUG("Invalid recovery use case\n");
  6147. return;
  6148. }
  6149. mutex_lock(&display->display_lock);
  6150. if (!_dsi_display_validate_host_state(display)) {
  6151. mutex_unlock(&display->display_lock);
  6152. return;
  6153. }
  6154. DSI_INFO("handle DSI FIFO overflow error\n");
  6155. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6156. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6157. DSI_ALL_CLKS, DSI_CLK_ON);
  6158. /*
  6159. * below recovery sequence is not applicable to
  6160. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6161. */
  6162. ctrl = &display->ctrl[display->clk_master_idx];
  6163. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6164. if (!version || (version < 0x20020001))
  6165. goto end;
  6166. /* reset ctrl and lanes */
  6167. display_for_each_ctrl(i, display) {
  6168. ctrl = &display->ctrl[i];
  6169. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6170. rc = dsi_phy_lane_reset(ctrl->phy);
  6171. }
  6172. /* wait for display line count to be in active area */
  6173. ctrl = &display->ctrl[display->clk_master_idx];
  6174. if (ctrl->ctrl->recovery_cb.event_cb) {
  6175. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6176. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6177. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6178. display->clk_master_idx, 0, 0, 0, 0);
  6179. if (rc < 0) {
  6180. DSI_DEBUG("sde callback failed\n");
  6181. goto end;
  6182. }
  6183. }
  6184. /* Enable Video mode for DSI controller */
  6185. display_for_each_ctrl(i, display) {
  6186. ctrl = &display->ctrl[i];
  6187. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6188. }
  6189. /*
  6190. * Add sufficient delay to make sure
  6191. * pixel transmission has started
  6192. */
  6193. udelay(200);
  6194. end:
  6195. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6196. DSI_ALL_CLKS, DSI_CLK_OFF);
  6197. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6198. mutex_unlock(&display->display_lock);
  6199. }
  6200. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6201. {
  6202. struct dsi_display *display = NULL;
  6203. struct dsi_display_ctrl *ctrl;
  6204. int i, rc;
  6205. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6206. int (*cb_func)(void *event_usr_ptr,
  6207. uint32_t event_idx, uint32_t instance_idx,
  6208. uint32_t data0, uint32_t data1,
  6209. uint32_t data2, uint32_t data3);
  6210. void *data;
  6211. u32 version = 0;
  6212. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6213. if (!display || !display->panel ||
  6214. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6215. atomic_read(&display->panel->esd_recovery_pending)) {
  6216. DSI_DEBUG("Invalid recovery use case\n");
  6217. return;
  6218. }
  6219. mutex_lock(&display->display_lock);
  6220. if (!_dsi_display_validate_host_state(display)) {
  6221. mutex_unlock(&display->display_lock);
  6222. return;
  6223. }
  6224. DSI_INFO("handle DSI LP RX Timeout error\n");
  6225. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6226. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6227. DSI_ALL_CLKS, DSI_CLK_ON);
  6228. /*
  6229. * below recovery sequence is not applicable to
  6230. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6231. */
  6232. ctrl = &display->ctrl[display->clk_master_idx];
  6233. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6234. if (!version || (version < 0x20020001))
  6235. goto end;
  6236. /* reset ctrl and lanes */
  6237. display_for_each_ctrl(i, display) {
  6238. ctrl = &display->ctrl[i];
  6239. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6240. rc = dsi_phy_lane_reset(ctrl->phy);
  6241. }
  6242. ctrl = &display->ctrl[display->clk_master_idx];
  6243. if (ctrl->ctrl->recovery_cb.event_cb) {
  6244. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6245. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6246. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6247. display->clk_master_idx, 0, 0, 0, 0);
  6248. if (rc < 0) {
  6249. DSI_DEBUG("Target is in suspend/shutdown\n");
  6250. goto end;
  6251. }
  6252. }
  6253. /* Enable Video mode for DSI controller */
  6254. display_for_each_ctrl(i, display) {
  6255. ctrl = &display->ctrl[i];
  6256. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6257. }
  6258. /*
  6259. * Add sufficient delay to make sure
  6260. * pixel transmission as started
  6261. */
  6262. udelay(200);
  6263. end:
  6264. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6265. DSI_ALL_CLKS, DSI_CLK_OFF);
  6266. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6267. mutex_unlock(&display->display_lock);
  6268. }
  6269. static int dsi_display_cb_error_handler(void *data,
  6270. uint32_t event_idx, uint32_t instance_idx,
  6271. uint32_t data0, uint32_t data1,
  6272. uint32_t data2, uint32_t data3)
  6273. {
  6274. struct dsi_display *display = data;
  6275. if (!display || !(display->err_workq))
  6276. return -EINVAL;
  6277. switch (event_idx) {
  6278. case DSI_FIFO_UNDERFLOW:
  6279. queue_work(display->err_workq, &display->fifo_underflow_work);
  6280. break;
  6281. case DSI_FIFO_OVERFLOW:
  6282. queue_work(display->err_workq, &display->fifo_overflow_work);
  6283. break;
  6284. case DSI_LP_Rx_TIMEOUT:
  6285. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6286. break;
  6287. default:
  6288. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6289. break;
  6290. }
  6291. return 0;
  6292. }
  6293. static void dsi_display_register_error_handler(struct dsi_display *display)
  6294. {
  6295. int i = 0;
  6296. struct dsi_display_ctrl *ctrl;
  6297. struct dsi_event_cb_info event_info;
  6298. if (!display)
  6299. return;
  6300. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6301. if (!display->err_workq) {
  6302. DSI_ERR("failed to create dsi workq!\n");
  6303. return;
  6304. }
  6305. INIT_WORK(&display->fifo_underflow_work,
  6306. dsi_display_handle_fifo_underflow);
  6307. INIT_WORK(&display->fifo_overflow_work,
  6308. dsi_display_handle_fifo_overflow);
  6309. INIT_WORK(&display->lp_rx_timeout_work,
  6310. dsi_display_handle_lp_rx_timeout);
  6311. memset(&event_info, 0, sizeof(event_info));
  6312. event_info.event_cb = dsi_display_cb_error_handler;
  6313. event_info.event_usr_ptr = display;
  6314. display_for_each_ctrl(i, display) {
  6315. ctrl = &display->ctrl[i];
  6316. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6317. }
  6318. }
  6319. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6320. {
  6321. int i = 0;
  6322. struct dsi_display_ctrl *ctrl;
  6323. if (!display)
  6324. return;
  6325. display_for_each_ctrl(i, display) {
  6326. ctrl = &display->ctrl[i];
  6327. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6328. 0, sizeof(struct dsi_event_cb_info));
  6329. }
  6330. if (display->err_workq) {
  6331. destroy_workqueue(display->err_workq);
  6332. display->err_workq = NULL;
  6333. }
  6334. }
  6335. int dsi_display_prepare(struct dsi_display *display)
  6336. {
  6337. int rc = 0;
  6338. struct dsi_display_mode *mode;
  6339. if (!display) {
  6340. DSI_ERR("Invalid params\n");
  6341. return -EINVAL;
  6342. }
  6343. if (!display->panel->cur_mode) {
  6344. DSI_ERR("no valid mode set for the display\n");
  6345. return -EINVAL;
  6346. }
  6347. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6348. mutex_lock(&display->display_lock);
  6349. mode = display->panel->cur_mode;
  6350. dsi_display_set_ctrl_esd_check_flag(display, false);
  6351. /* Set up ctrl isr before enabling core clk */
  6352. if (!display->trusted_vm_env)
  6353. dsi_display_ctrl_isr_configure(display, true);
  6354. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6355. if (display->is_cont_splash_enabled &&
  6356. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6357. DSI_ERR("DMS not supported on first frame\n");
  6358. rc = -EINVAL;
  6359. goto error;
  6360. }
  6361. if (!is_skip_op_required(display)) {
  6362. /* update dsi ctrl for new mode */
  6363. rc = dsi_display_pre_switch(display);
  6364. if (rc)
  6365. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6366. display->name, rc);
  6367. goto error;
  6368. }
  6369. }
  6370. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) &&
  6371. (!is_skip_op_required(display))) {
  6372. /*
  6373. * For continuous splash/trusted vm, we skip panel
  6374. * pre prepare since the regulator vote is already
  6375. * taken care in splash resource init
  6376. */
  6377. rc = dsi_panel_pre_prepare(display->panel);
  6378. if (rc) {
  6379. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6380. display->name, rc);
  6381. goto error;
  6382. }
  6383. }
  6384. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6385. DSI_CORE_CLK, DSI_CLK_ON);
  6386. if (rc) {
  6387. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6388. display->name, rc);
  6389. goto error_panel_post_unprep;
  6390. }
  6391. /*
  6392. * If ULPS during suspend feature is enabled, then DSI PHY was
  6393. * left on during suspend. In this case, we do not need to reset/init
  6394. * PHY. This would have already been done when the CORE clocks are
  6395. * turned on. However, if cont splash is disabled, the first time DSI
  6396. * is powered on, phy init needs to be done unconditionally.
  6397. */
  6398. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6399. rc = dsi_display_phy_sw_reset(display);
  6400. if (rc) {
  6401. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6402. display->name, rc);
  6403. goto error_ctrl_clk_off;
  6404. }
  6405. rc = dsi_display_phy_enable(display);
  6406. if (rc) {
  6407. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6408. display->name, rc);
  6409. goto error_ctrl_clk_off;
  6410. }
  6411. }
  6412. if (!display->trusted_vm_env) {
  6413. rc = dsi_display_set_clk_src(display);
  6414. if (rc) {
  6415. DSI_ERR(
  6416. "[%s] failed to set DSI link clock source, rc=%d\n",
  6417. display->name, rc);
  6418. goto error_phy_disable;
  6419. }
  6420. }
  6421. rc = dsi_display_ctrl_init(display);
  6422. if (rc) {
  6423. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6424. display->name, rc);
  6425. goto error_phy_disable;
  6426. }
  6427. /* Set up DSI ERROR event callback */
  6428. dsi_display_register_error_handler(display);
  6429. rc = dsi_display_ctrl_host_enable(display);
  6430. if (rc) {
  6431. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6432. display->name, rc);
  6433. goto error_ctrl_deinit;
  6434. }
  6435. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6436. DSI_LINK_CLK, DSI_CLK_ON);
  6437. if (rc) {
  6438. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6439. display->name, rc);
  6440. goto error_host_engine_off;
  6441. }
  6442. if (!is_skip_op_required(display)) {
  6443. /*
  6444. * For continuous splash/trusted vm, skip panel prepare and
  6445. * ctl reset since the pnael and ctrl is already in active
  6446. * state and panel on commands are not needed
  6447. */
  6448. rc = dsi_display_soft_reset(display);
  6449. if (rc) {
  6450. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6451. display->name, rc);
  6452. goto error_ctrl_link_off;
  6453. }
  6454. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)) {
  6455. rc = dsi_panel_prepare(display->panel);
  6456. if (rc) {
  6457. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6458. display->name, rc);
  6459. goto error_ctrl_link_off;
  6460. }
  6461. }
  6462. }
  6463. goto error;
  6464. error_ctrl_link_off:
  6465. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6466. DSI_LINK_CLK, DSI_CLK_OFF);
  6467. error_host_engine_off:
  6468. (void)dsi_display_ctrl_host_disable(display);
  6469. error_ctrl_deinit:
  6470. (void)dsi_display_ctrl_deinit(display);
  6471. error_phy_disable:
  6472. (void)dsi_display_phy_disable(display);
  6473. error_ctrl_clk_off:
  6474. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6475. DSI_CORE_CLK, DSI_CLK_OFF);
  6476. error_panel_post_unprep:
  6477. (void)dsi_panel_post_unprepare(display->panel);
  6478. error:
  6479. mutex_unlock(&display->display_lock);
  6480. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6481. return rc;
  6482. }
  6483. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6484. const struct dsi_display_ctrl *ctrl,
  6485. const struct msm_roi_list *req_rois,
  6486. struct dsi_rect *out_roi)
  6487. {
  6488. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6489. struct dsi_display_mode *cur_mode;
  6490. struct msm_roi_caps *roi_caps;
  6491. struct dsi_rect req_roi = { 0 };
  6492. int rc = 0;
  6493. cur_mode = display->panel->cur_mode;
  6494. if (!cur_mode)
  6495. return 0;
  6496. roi_caps = &cur_mode->priv_info->roi_caps;
  6497. if (req_rois->num_rects > roi_caps->num_roi) {
  6498. DSI_ERR("request for %d rois greater than max %d\n",
  6499. req_rois->num_rects,
  6500. roi_caps->num_roi);
  6501. rc = -EINVAL;
  6502. goto exit;
  6503. }
  6504. /**
  6505. * if no rois, user wants to reset back to full resolution
  6506. * note: h_active is already divided by ctrl_count
  6507. */
  6508. if (!req_rois->num_rects) {
  6509. *out_roi = *bounds;
  6510. goto exit;
  6511. }
  6512. /* intersect with the bounds */
  6513. req_roi.x = req_rois->roi[0].x1;
  6514. req_roi.y = req_rois->roi[0].y1;
  6515. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6516. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6517. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6518. exit:
  6519. /* adjust the ctrl origin to be top left within the ctrl */
  6520. out_roi->x = out_roi->x - bounds->x;
  6521. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6522. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6523. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6524. bounds->x, bounds->y, bounds->w, bounds->h,
  6525. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6526. return rc;
  6527. }
  6528. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6529. {
  6530. int i;
  6531. int rc = 0;
  6532. if (!display->panel->qsync_min_fps) {
  6533. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6534. return 0;
  6535. }
  6536. mutex_lock(&display->display_lock);
  6537. display_for_each_ctrl(i, display) {
  6538. if (enable) {
  6539. /* send the commands to enable qsync */
  6540. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6541. if (rc) {
  6542. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6543. goto exit;
  6544. }
  6545. } else {
  6546. /* send the commands to enable qsync */
  6547. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6548. if (rc) {
  6549. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6550. goto exit;
  6551. }
  6552. }
  6553. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6554. }
  6555. exit:
  6556. SDE_EVT32(enable, display->panel->qsync_min_fps, rc);
  6557. mutex_unlock(&display->display_lock);
  6558. return rc;
  6559. }
  6560. static int dsi_display_set_roi(struct dsi_display *display,
  6561. struct msm_roi_list *rois)
  6562. {
  6563. struct dsi_display_mode *cur_mode;
  6564. struct msm_roi_caps *roi_caps;
  6565. int rc = 0;
  6566. int i;
  6567. if (!display || !rois || !display->panel)
  6568. return -EINVAL;
  6569. cur_mode = display->panel->cur_mode;
  6570. if (!cur_mode)
  6571. return 0;
  6572. roi_caps = &cur_mode->priv_info->roi_caps;
  6573. if (!roi_caps->enabled)
  6574. return 0;
  6575. display_for_each_ctrl(i, display) {
  6576. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6577. struct dsi_rect ctrl_roi;
  6578. bool changed = false;
  6579. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6580. if (rc) {
  6581. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6582. return rc;
  6583. }
  6584. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6585. if (rc) {
  6586. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6587. return rc;
  6588. }
  6589. if (!changed)
  6590. continue;
  6591. /* send the new roi to the panel via dcs commands */
  6592. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6593. if (rc) {
  6594. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6595. return rc;
  6596. }
  6597. /* re-program the ctrl with the timing based on the new roi */
  6598. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6599. if (rc) {
  6600. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6601. return rc;
  6602. }
  6603. }
  6604. return rc;
  6605. }
  6606. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6607. struct dsi_display *display,
  6608. struct msm_display_kickoff_params *params)
  6609. {
  6610. int rc = 0, ret = 0;
  6611. int i;
  6612. /* check and setup MISR */
  6613. if (display->misr_enable)
  6614. _dsi_display_setup_misr(display);
  6615. /* dynamic DSI clock setting */
  6616. if (atomic_read(&display->clkrate_change_pending)) {
  6617. mutex_lock(&display->display_lock);
  6618. /*
  6619. * acquire panel_lock to make sure no commands are in progress
  6620. */
  6621. dsi_panel_acquire_panel_lock(display->panel);
  6622. /*
  6623. * Wait for DSI command engine not to be busy sending data
  6624. * from display engine.
  6625. * If waiting fails, return "rc" instead of below "ret" so as
  6626. * not to impact DRM commit. The clock updating would be
  6627. * deferred to the next DRM commit.
  6628. */
  6629. display_for_each_ctrl(i, display) {
  6630. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6631. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6632. if (ret)
  6633. goto wait_failure;
  6634. }
  6635. /*
  6636. * Don't check the return value so as not to impact DRM commit
  6637. * when error occurs.
  6638. */
  6639. (void)dsi_display_force_update_dsi_clk(display);
  6640. wait_failure:
  6641. /* release panel_lock */
  6642. dsi_panel_release_panel_lock(display->panel);
  6643. mutex_unlock(&display->display_lock);
  6644. }
  6645. if (!ret)
  6646. rc = dsi_display_set_roi(display, params->rois);
  6647. return rc;
  6648. }
  6649. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6650. {
  6651. int rc = 0;
  6652. if (!display || !display->panel) {
  6653. DSI_ERR("Invalid params\n");
  6654. return -EINVAL;
  6655. }
  6656. if (!display->panel->cur_mode) {
  6657. DSI_ERR("no valid mode set for the display\n");
  6658. return -EINVAL;
  6659. }
  6660. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6661. rc = dsi_display_vid_engine_enable(display);
  6662. if (rc) {
  6663. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6664. display->name, rc);
  6665. goto error_out;
  6666. }
  6667. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6668. rc = dsi_display_cmd_engine_enable(display);
  6669. if (rc) {
  6670. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6671. display->name, rc);
  6672. goto error_out;
  6673. }
  6674. } else {
  6675. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6676. rc = -EINVAL;
  6677. }
  6678. error_out:
  6679. return rc;
  6680. }
  6681. int dsi_display_pre_commit(void *display,
  6682. struct msm_display_conn_params *params)
  6683. {
  6684. bool enable = false;
  6685. int rc = 0;
  6686. if (!display || !params) {
  6687. pr_err("Invalid params\n");
  6688. return -EINVAL;
  6689. }
  6690. if (params->qsync_update) {
  6691. enable = (params->qsync_mode > 0) ? true : false;
  6692. rc = dsi_display_qsync(display, enable);
  6693. if (rc)
  6694. pr_err("%s failed to send qsync commands\n",
  6695. __func__);
  6696. SDE_EVT32(params->qsync_mode, rc);
  6697. }
  6698. return rc;
  6699. }
  6700. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6701. {
  6702. if (display->panel_id != ~0x0 &&
  6703. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6704. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6705. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6706. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6707. 0, ((display->panel_id & 0xffffffff00000000) >> 31),
  6708. (display->panel_id & 0xffffffff), 0, 0);
  6709. }
  6710. }
  6711. int dsi_display_enable(struct dsi_display *display)
  6712. {
  6713. int rc = 0;
  6714. struct dsi_display_mode *mode;
  6715. if (!display || !display->panel) {
  6716. DSI_ERR("Invalid params\n");
  6717. return -EINVAL;
  6718. }
  6719. if (!display->panel->cur_mode) {
  6720. DSI_ERR("no valid mode set for the display\n");
  6721. return -EINVAL;
  6722. }
  6723. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6724. /*
  6725. * Engine states and panel states are populated during splash
  6726. * resource/trusted vm and hence we return early
  6727. */
  6728. if (is_skip_op_required(display)) {
  6729. dsi_display_config_ctrl_for_cont_splash(display);
  6730. rc = dsi_display_splash_res_cleanup(display);
  6731. if (rc) {
  6732. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6733. rc);
  6734. return -EINVAL;
  6735. }
  6736. display->panel->panel_initialized = true;
  6737. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6738. dsi_display_panel_id_notification(display);
  6739. return 0;
  6740. }
  6741. mutex_lock(&display->display_lock);
  6742. mode = display->panel->cur_mode;
  6743. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6744. rc = dsi_panel_post_switch(display->panel);
  6745. if (rc) {
  6746. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6747. display->name, rc);
  6748. goto error;
  6749. }
  6750. } else if (!(display->panel->cur_mode->dsi_mode_flags &
  6751. DSI_MODE_FLAG_POMS)){
  6752. rc = dsi_panel_enable(display->panel);
  6753. if (rc) {
  6754. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6755. display->name, rc);
  6756. goto error;
  6757. }
  6758. }
  6759. dsi_display_panel_id_notification(display);
  6760. /* Block sending pps command if modeset is due to fps difference */
  6761. if ((mode->priv_info->dsc_enabled ||
  6762. mode->priv_info->vdc_enabled) &&
  6763. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6764. rc = dsi_panel_update_pps(display->panel);
  6765. if (rc) {
  6766. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6767. display->name, rc);
  6768. goto error;
  6769. }
  6770. }
  6771. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6772. rc = dsi_panel_switch(display->panel);
  6773. if (rc)
  6774. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6775. display->name, rc);
  6776. goto error;
  6777. }
  6778. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6779. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6780. rc = dsi_display_vid_engine_enable(display);
  6781. if (rc) {
  6782. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6783. display->name, rc);
  6784. goto error_disable_panel;
  6785. }
  6786. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6787. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6788. rc = dsi_display_cmd_engine_enable(display);
  6789. if (rc) {
  6790. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6791. display->name, rc);
  6792. goto error_disable_panel;
  6793. }
  6794. } else {
  6795. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6796. rc = -EINVAL;
  6797. goto error_disable_panel;
  6798. }
  6799. goto error;
  6800. error_disable_panel:
  6801. (void)dsi_panel_disable(display->panel);
  6802. error:
  6803. mutex_unlock(&display->display_lock);
  6804. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6805. return rc;
  6806. }
  6807. int dsi_display_post_enable(struct dsi_display *display)
  6808. {
  6809. int rc = 0;
  6810. if (!display) {
  6811. DSI_ERR("Invalid params\n");
  6812. return -EINVAL;
  6813. }
  6814. mutex_lock(&display->display_lock);
  6815. if (display->panel->cur_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS) {
  6816. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6817. dsi_panel_mode_switch_to_cmd(display->panel);
  6818. if (display->config.panel_mode == DSI_OP_VIDEO_MODE)
  6819. dsi_panel_mode_switch_to_vid(display->panel);
  6820. } else {
  6821. rc = dsi_panel_post_enable(display->panel);
  6822. if (rc)
  6823. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6824. display->name, rc);
  6825. }
  6826. /* remove the clk vote for CMD mode panels */
  6827. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6828. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6829. DSI_ALL_CLKS, DSI_CLK_OFF);
  6830. mutex_unlock(&display->display_lock);
  6831. return rc;
  6832. }
  6833. int dsi_display_pre_disable(struct dsi_display *display)
  6834. {
  6835. int rc = 0;
  6836. if (!display) {
  6837. DSI_ERR("Invalid params\n");
  6838. return -EINVAL;
  6839. }
  6840. mutex_lock(&display->display_lock);
  6841. /* enable the clk vote for CMD mode panels */
  6842. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6843. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6844. DSI_ALL_CLKS, DSI_CLK_ON);
  6845. if (display->poms_pending) {
  6846. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6847. dsi_panel_pre_mode_switch_to_video(display->panel);
  6848. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6849. /*
  6850. * Add unbalanced vote for clock & cmd engine to enable
  6851. * async trigger of pre video to cmd mode switch.
  6852. */
  6853. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6854. DSI_ALL_CLKS, DSI_CLK_ON);
  6855. if (rc) {
  6856. DSI_ERR("[%s]failed to enable all clocks,rc=%d",
  6857. display->name, rc);
  6858. goto exit;
  6859. }
  6860. rc = dsi_display_cmd_engine_enable(display);
  6861. if (rc) {
  6862. DSI_ERR("[%s]failed to enable cmd engine,rc=%d",
  6863. display->name, rc);
  6864. goto error_disable_clks;
  6865. }
  6866. dsi_panel_pre_mode_switch_to_cmd(display->panel);
  6867. }
  6868. } else {
  6869. rc = dsi_panel_pre_disable(display->panel);
  6870. if (rc)
  6871. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  6872. display->name, rc);
  6873. }
  6874. goto exit;
  6875. error_disable_clks:
  6876. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6877. DSI_ALL_CLKS, DSI_CLK_OFF);
  6878. if (rc)
  6879. DSI_ERR("[%s] failed to disable all DSI clocks, rc=%d\n",
  6880. display->name, rc);
  6881. exit:
  6882. mutex_unlock(&display->display_lock);
  6883. return rc;
  6884. }
  6885. static void dsi_display_handle_poms_te(struct work_struct *work)
  6886. {
  6887. struct dsi_display *display = NULL;
  6888. struct delayed_work *dw = to_delayed_work(work);
  6889. struct mipi_dsi_device *dsi = NULL;
  6890. struct dsi_panel *panel = NULL;
  6891. int rc = 0;
  6892. display = container_of(dw, struct dsi_display, poms_te_work);
  6893. if (!display || !display->panel) {
  6894. DSI_ERR("Invalid params\n");
  6895. return;
  6896. }
  6897. panel = display->panel;
  6898. mutex_lock(&panel->panel_lock);
  6899. if (!dsi_panel_initialized(panel)) {
  6900. rc = -EINVAL;
  6901. goto error;
  6902. }
  6903. dsi = &panel->mipi_device;
  6904. rc = mipi_dsi_dcs_set_tear_off(dsi);
  6905. error:
  6906. mutex_unlock(&panel->panel_lock);
  6907. if (rc < 0)
  6908. DSI_ERR("failed to set tear off\n");
  6909. }
  6910. int dsi_display_disable(struct dsi_display *display)
  6911. {
  6912. int rc = 0;
  6913. if (!display) {
  6914. DSI_ERR("Invalid params\n");
  6915. return -EINVAL;
  6916. }
  6917. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6918. mutex_lock(&display->display_lock);
  6919. /* cancel delayed work */
  6920. if (display->poms_pending &&
  6921. display->panel->poms_align_vsync)
  6922. cancel_delayed_work_sync(&display->poms_te_work);
  6923. rc = dsi_display_wake_up(display);
  6924. if (rc)
  6925. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  6926. display->name, rc);
  6927. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6928. rc = dsi_display_vid_engine_disable(display);
  6929. if (rc)
  6930. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  6931. display->name, rc);
  6932. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6933. /**
  6934. * On POMS request , disable panel TE through
  6935. * delayed work queue.
  6936. */
  6937. if (display->poms_pending &&
  6938. display->panel->poms_align_vsync) {
  6939. INIT_DELAYED_WORK(&display->poms_te_work,
  6940. dsi_display_handle_poms_te);
  6941. queue_delayed_work(system_wq,
  6942. &display->poms_te_work,
  6943. msecs_to_jiffies(100));
  6944. }
  6945. rc = dsi_display_cmd_engine_disable(display);
  6946. if (rc)
  6947. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  6948. display->name, rc);
  6949. } else {
  6950. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6951. rc = -EINVAL;
  6952. }
  6953. if (!display->poms_pending && !is_skip_op_required(display)) {
  6954. rc = dsi_panel_disable(display->panel);
  6955. if (rc)
  6956. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  6957. display->name, rc);
  6958. }
  6959. if (is_skip_op_required(display)) {
  6960. /* applicable only for trusted vm */
  6961. display->panel->panel_initialized = false;
  6962. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  6963. }
  6964. mutex_unlock(&display->display_lock);
  6965. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6966. return rc;
  6967. }
  6968. int dsi_display_update_pps(char *pps_cmd, void *disp)
  6969. {
  6970. struct dsi_display *display;
  6971. if (pps_cmd == NULL || disp == NULL) {
  6972. DSI_ERR("Invalid parameter\n");
  6973. return -EINVAL;
  6974. }
  6975. display = disp;
  6976. mutex_lock(&display->display_lock);
  6977. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  6978. mutex_unlock(&display->display_lock);
  6979. return 0;
  6980. }
  6981. int dsi_display_dump_clks_state(struct dsi_display *display)
  6982. {
  6983. int rc = 0;
  6984. if (!display) {
  6985. DSI_ERR("invalid display argument\n");
  6986. return -EINVAL;
  6987. }
  6988. if (!display->clk_mngr) {
  6989. DSI_ERR("invalid clk manager\n");
  6990. return -EINVAL;
  6991. }
  6992. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  6993. DSI_ERR("invalid clk handles\n");
  6994. return -EINVAL;
  6995. }
  6996. mutex_lock(&display->display_lock);
  6997. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  6998. if (rc) {
  6999. DSI_ERR("failed to dump dsi clock state\n");
  7000. goto end;
  7001. }
  7002. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7003. if (rc) {
  7004. DSI_ERR("failed to dump mdp clock state\n");
  7005. goto end;
  7006. }
  7007. end:
  7008. mutex_unlock(&display->display_lock);
  7009. return rc;
  7010. }
  7011. int dsi_display_unprepare(struct dsi_display *display)
  7012. {
  7013. int rc = 0, i;
  7014. struct dsi_display_ctrl *ctrl;
  7015. if (!display) {
  7016. DSI_ERR("Invalid params\n");
  7017. return -EINVAL;
  7018. }
  7019. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7020. mutex_lock(&display->display_lock);
  7021. rc = dsi_display_wake_up(display);
  7022. if (rc)
  7023. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7024. display->name, rc);
  7025. if (!display->poms_pending && !is_skip_op_required(display)) {
  7026. rc = dsi_panel_unprepare(display->panel);
  7027. if (rc)
  7028. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7029. display->name, rc);
  7030. }
  7031. /* Remove additional vote added for pre_mode_switch_to_cmd */
  7032. if (display->poms_pending &&
  7033. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7034. display_for_each_ctrl(i, display) {
  7035. ctrl = &display->ctrl[i];
  7036. if (!ctrl->ctrl || !ctrl->ctrl->dma_wait_queued)
  7037. continue;
  7038. flush_workqueue(display->dma_cmd_workq);
  7039. cancel_work_sync(&ctrl->ctrl->dma_cmd_wait);
  7040. ctrl->ctrl->dma_wait_queued = false;
  7041. }
  7042. dsi_display_cmd_engine_disable(display);
  7043. dsi_display_clk_ctrl(display->dsi_clk_handle,
  7044. DSI_ALL_CLKS, DSI_CLK_OFF);
  7045. }
  7046. rc = dsi_display_ctrl_host_disable(display);
  7047. if (rc)
  7048. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7049. display->name, rc);
  7050. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7051. DSI_LINK_CLK, DSI_CLK_OFF);
  7052. if (rc)
  7053. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7054. display->name, rc);
  7055. rc = dsi_display_ctrl_deinit(display);
  7056. if (rc)
  7057. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7058. display->name, rc);
  7059. if (!display->panel->ulps_suspend_enabled) {
  7060. rc = dsi_display_phy_disable(display);
  7061. if (rc)
  7062. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7063. display->name, rc);
  7064. }
  7065. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7066. DSI_CORE_CLK, DSI_CLK_OFF);
  7067. if (rc)
  7068. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7069. display->name, rc);
  7070. /* destrory dsi isr set up */
  7071. dsi_display_ctrl_isr_configure(display, false);
  7072. if (!display->poms_pending && !is_skip_op_required(display)) {
  7073. rc = dsi_panel_post_unprepare(display->panel);
  7074. if (rc)
  7075. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7076. display->name, rc);
  7077. }
  7078. mutex_unlock(&display->display_lock);
  7079. /* Free up DSI ERROR event callback */
  7080. dsi_display_unregister_error_handler(display);
  7081. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7082. return rc;
  7083. }
  7084. void __init dsi_display_register(void)
  7085. {
  7086. dsi_phy_drv_register();
  7087. dsi_ctrl_drv_register();
  7088. dsi_display_parse_boot_display_selection();
  7089. platform_driver_register(&dsi_display_driver);
  7090. }
  7091. void __exit dsi_display_unregister(void)
  7092. {
  7093. platform_driver_unregister(&dsi_display_driver);
  7094. dsi_ctrl_drv_unregister();
  7095. dsi_phy_drv_unregister();
  7096. }
  7097. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7098. 0600);
  7099. MODULE_PARM_DESC(dsi_display0,
  7100. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7101. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7102. 0600);
  7103. MODULE_PARM_DESC(dsi_display1,
  7104. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");