dp_tx.c 113 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "enet.h"
  33. #define DP_TX_QUEUE_MASK 0x3
  34. /* TODO Add support in TSO */
  35. #define DP_DESC_NUM_FRAG(x) 0
  36. /* disable TQM_BYPASS */
  37. #define TQM_BYPASS_WAR 0
  38. /* invalid peer id for reinject*/
  39. #define DP_INVALID_PEER 0XFFFE
  40. /*mapping between hal encrypt type and cdp_sec_type*/
  41. #define MAX_CDP_SEC_TYPE 12
  42. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  43. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  44. HAL_TX_ENCRYPT_TYPE_WEP_128,
  45. HAL_TX_ENCRYPT_TYPE_WEP_104,
  46. HAL_TX_ENCRYPT_TYPE_WEP_40,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  48. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  49. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  50. HAL_TX_ENCRYPT_TYPE_WAPI,
  51. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  53. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  54. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  55. /**
  56. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  57. * @vdev: DP Virtual device handle
  58. * @nbuf: Buffer pointer
  59. * @queue: queue ids container for nbuf
  60. *
  61. * TX packet queue has 2 instances, software descriptors id and dma ring id
  62. * Based on tx feature and hardware configuration queue id combination could be
  63. * different.
  64. * For example -
  65. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  66. * With no XPS,lock based resource protection, Descriptor pool ids are different
  67. * for each vdev, dma ring id will be same as single pdev id
  68. *
  69. * Return: None
  70. */
  71. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  72. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  73. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  74. {
  75. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  76. queue->desc_pool_id = queue_offset;
  77. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  79. "%s, pool_id:%d ring_id: %d",
  80. __func__, queue->desc_pool_id, queue->ring_id);
  81. return;
  82. }
  83. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  84. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  85. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  86. {
  87. /* get flow id */
  88. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  89. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  91. "%s, pool_id:%d ring_id: %d",
  92. __func__, queue->desc_pool_id, queue->ring_id);
  93. return;
  94. }
  95. #endif
  96. #if defined(FEATURE_TSO)
  97. /**
  98. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  99. *
  100. * @soc - core txrx main context
  101. * @seg_desc - tso segment descriptor
  102. * @num_seg_desc - tso number segment descriptor
  103. */
  104. static void dp_tx_tso_unmap_segment(
  105. struct dp_soc *soc,
  106. struct qdf_tso_seg_elem_t *seg_desc,
  107. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  108. {
  109. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  110. if (qdf_unlikely(!seg_desc)) {
  111. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  112. __func__, __LINE__);
  113. qdf_assert(0);
  114. } else if (qdf_unlikely(!num_seg_desc)) {
  115. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  116. __func__, __LINE__);
  117. qdf_assert(0);
  118. } else {
  119. bool is_last_seg;
  120. /* no tso segment left to do dma unmap */
  121. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  122. return;
  123. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  124. true : false;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. seg_desc, is_last_seg);
  127. num_seg_desc->num_seg.tso_cmn_num_seg--;
  128. }
  129. }
  130. /**
  131. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  132. * back to the freelist
  133. *
  134. * @soc - soc device handle
  135. * @tx_desc - Tx software descriptor
  136. */
  137. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  138. struct dp_tx_desc_s *tx_desc)
  139. {
  140. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  141. if (qdf_unlikely(!tx_desc->tso_desc)) {
  142. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  143. "%s %d TSO desc is NULL!",
  144. __func__, __LINE__);
  145. qdf_assert(0);
  146. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  147. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  148. "%s %d TSO num desc is NULL!",
  149. __func__, __LINE__);
  150. qdf_assert(0);
  151. } else {
  152. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  153. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  154. /* Add the tso num segment into the free list */
  155. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  156. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  157. tx_desc->tso_num_desc);
  158. tx_desc->tso_num_desc = NULL;
  159. }
  160. /* Add the tso segment into the free list*/
  161. dp_tx_tso_desc_free(soc,
  162. tx_desc->pool_id, tx_desc->tso_desc);
  163. tx_desc->tso_desc = NULL;
  164. }
  165. }
  166. #else
  167. static void dp_tx_tso_unmap_segment(
  168. struct dp_soc *soc,
  169. struct qdf_tso_seg_elem_t *seg_desc,
  170. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  171. {
  172. }
  173. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  174. struct dp_tx_desc_s *tx_desc)
  175. {
  176. }
  177. #endif
  178. /**
  179. * dp_tx_desc_release() - Release Tx Descriptor
  180. * @tx_desc : Tx Descriptor
  181. * @desc_pool_id: Descriptor Pool ID
  182. *
  183. * Deallocate all resources attached to Tx descriptor and free the Tx
  184. * descriptor.
  185. *
  186. * Return:
  187. */
  188. void
  189. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  190. {
  191. struct dp_pdev *pdev = tx_desc->pdev;
  192. struct dp_soc *soc;
  193. uint8_t comp_status = 0;
  194. qdf_assert(pdev);
  195. soc = pdev->soc;
  196. if (tx_desc->frm_type == dp_tx_frm_tso)
  197. dp_tx_tso_desc_release(soc, tx_desc);
  198. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  199. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  201. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  202. qdf_atomic_dec(&pdev->num_tx_outstanding);
  203. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  204. qdf_atomic_dec(&pdev->num_tx_exception);
  205. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  206. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  207. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  208. soc->hal_soc);
  209. else
  210. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  212. "Tx Completion Release desc %d status %d outstanding %d",
  213. tx_desc->id, comp_status,
  214. qdf_atomic_read(&pdev->num_tx_outstanding));
  215. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  216. return;
  217. }
  218. /**
  219. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  220. * @vdev: DP vdev Handle
  221. * @nbuf: skb
  222. *
  223. * Prepares and fills HTT metadata in the frame pre-header for special frames
  224. * that should be transmitted using varying transmit parameters.
  225. * There are 2 VDEV modes that currently needs this special metadata -
  226. * 1) Mesh Mode
  227. * 2) DSRC Mode
  228. *
  229. * Return: HTT metadata size
  230. *
  231. */
  232. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  233. uint32_t *meta_data)
  234. {
  235. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  236. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  237. uint8_t htt_desc_size;
  238. /* Size rounded of multiple of 8 bytes */
  239. uint8_t htt_desc_size_aligned;
  240. uint8_t *hdr = NULL;
  241. /*
  242. * Metadata - HTT MSDU Extension header
  243. */
  244. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  245. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  246. if (vdev->mesh_vdev) {
  247. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  248. htt_desc_size_aligned)) {
  249. DP_STATS_INC(vdev,
  250. tx_i.dropped.headroom_insufficient, 1);
  251. return 0;
  252. }
  253. /* Fill and add HTT metaheader */
  254. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  255. if (!hdr) {
  256. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  257. "Error in filling HTT metadata");
  258. return 0;
  259. }
  260. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  261. } else if (vdev->opmode == wlan_op_mode_ocb) {
  262. /* Todo - Add support for DSRC */
  263. }
  264. return htt_desc_size_aligned;
  265. }
  266. /**
  267. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  268. * @tso_seg: TSO segment to process
  269. * @ext_desc: Pointer to MSDU extension descriptor
  270. *
  271. * Return: void
  272. */
  273. #if defined(FEATURE_TSO)
  274. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  275. void *ext_desc)
  276. {
  277. uint8_t num_frag;
  278. uint32_t tso_flags;
  279. /*
  280. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  281. * tcp_flag_mask
  282. *
  283. * Checksum enable flags are set in TCL descriptor and not in Extension
  284. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  285. */
  286. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  287. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  288. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  289. tso_seg->tso_flags.ip_len);
  290. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  291. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  292. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  293. uint32_t lo = 0;
  294. uint32_t hi = 0;
  295. qdf_dmaaddr_to_32s(
  296. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  297. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  298. tso_seg->tso_frags[num_frag].length);
  299. }
  300. return;
  301. }
  302. #else
  303. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  304. void *ext_desc)
  305. {
  306. return;
  307. }
  308. #endif
  309. #if defined(FEATURE_TSO)
  310. /**
  311. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  312. * allocated and free them
  313. *
  314. * @soc: soc handle
  315. * @free_seg: list of tso segments
  316. * @msdu_info: msdu descriptor
  317. *
  318. * Return - void
  319. */
  320. static void dp_tx_free_tso_seg_list(
  321. struct dp_soc *soc,
  322. struct qdf_tso_seg_elem_t *free_seg,
  323. struct dp_tx_msdu_info_s *msdu_info)
  324. {
  325. struct qdf_tso_seg_elem_t *next_seg;
  326. while (free_seg) {
  327. next_seg = free_seg->next;
  328. dp_tx_tso_desc_free(soc,
  329. msdu_info->tx_queue.desc_pool_id,
  330. free_seg);
  331. free_seg = next_seg;
  332. }
  333. }
  334. /**
  335. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  336. * allocated and free them
  337. *
  338. * @soc: soc handle
  339. * @free_num_seg: list of tso number segments
  340. * @msdu_info: msdu descriptor
  341. * Return - void
  342. */
  343. static void dp_tx_free_tso_num_seg_list(
  344. struct dp_soc *soc,
  345. struct qdf_tso_num_seg_elem_t *free_num_seg,
  346. struct dp_tx_msdu_info_s *msdu_info)
  347. {
  348. struct qdf_tso_num_seg_elem_t *next_num_seg;
  349. while (free_num_seg) {
  350. next_num_seg = free_num_seg->next;
  351. dp_tso_num_seg_free(soc,
  352. msdu_info->tx_queue.desc_pool_id,
  353. free_num_seg);
  354. free_num_seg = next_num_seg;
  355. }
  356. }
  357. /**
  358. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  359. * do dma unmap for each segment
  360. *
  361. * @soc: soc handle
  362. * @free_seg: list of tso segments
  363. * @num_seg_desc: tso number segment descriptor
  364. *
  365. * Return - void
  366. */
  367. static void dp_tx_unmap_tso_seg_list(
  368. struct dp_soc *soc,
  369. struct qdf_tso_seg_elem_t *free_seg,
  370. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  371. {
  372. struct qdf_tso_seg_elem_t *next_seg;
  373. if (qdf_unlikely(!num_seg_desc)) {
  374. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  375. return;
  376. }
  377. while (free_seg) {
  378. next_seg = free_seg->next;
  379. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  380. free_seg = next_seg;
  381. }
  382. }
  383. /**
  384. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  385. * free the tso segments descriptor and
  386. * tso num segments descriptor
  387. *
  388. * @soc: soc handle
  389. * @msdu_info: msdu descriptor
  390. * @tso_seg_unmap: flag to show if dma unmap is necessary
  391. *
  392. * Return - void
  393. */
  394. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  395. struct dp_tx_msdu_info_s *msdu_info,
  396. bool tso_seg_unmap)
  397. {
  398. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  399. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  400. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  401. tso_info->tso_num_seg_list;
  402. /* do dma unmap for each segment */
  403. if (tso_seg_unmap)
  404. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  405. /* free all tso number segment descriptor though looks only have 1 */
  406. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  407. /* free all tso segment descriptor */
  408. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  409. }
  410. /**
  411. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  412. * @vdev: virtual device handle
  413. * @msdu: network buffer
  414. * @msdu_info: meta data associated with the msdu
  415. *
  416. * Return: QDF_STATUS_SUCCESS success
  417. */
  418. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  419. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  420. {
  421. struct qdf_tso_seg_elem_t *tso_seg;
  422. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  423. struct dp_soc *soc = vdev->pdev->soc;
  424. struct qdf_tso_info_t *tso_info;
  425. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  426. tso_info = &msdu_info->u.tso_info;
  427. tso_info->curr_seg = NULL;
  428. tso_info->tso_seg_list = NULL;
  429. tso_info->num_segs = num_seg;
  430. msdu_info->frm_type = dp_tx_frm_tso;
  431. tso_info->tso_num_seg_list = NULL;
  432. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  433. while (num_seg) {
  434. tso_seg = dp_tx_tso_desc_alloc(
  435. soc, msdu_info->tx_queue.desc_pool_id);
  436. if (tso_seg) {
  437. tso_seg->next = tso_info->tso_seg_list;
  438. tso_info->tso_seg_list = tso_seg;
  439. num_seg--;
  440. } else {
  441. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  442. __func__);
  443. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  444. return QDF_STATUS_E_NOMEM;
  445. }
  446. }
  447. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  448. tso_num_seg = dp_tso_num_seg_alloc(soc,
  449. msdu_info->tx_queue.desc_pool_id);
  450. if (tso_num_seg) {
  451. tso_num_seg->next = tso_info->tso_num_seg_list;
  452. tso_info->tso_num_seg_list = tso_num_seg;
  453. } else {
  454. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  455. __func__);
  456. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  457. return QDF_STATUS_E_NOMEM;
  458. }
  459. msdu_info->num_seg =
  460. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  461. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  462. msdu_info->num_seg);
  463. if (!(msdu_info->num_seg)) {
  464. /*
  465. * Free allocated TSO seg desc and number seg desc,
  466. * do unmap for segments if dma map has done.
  467. */
  468. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  469. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  470. return QDF_STATUS_E_INVAL;
  471. }
  472. tso_info->curr_seg = tso_info->tso_seg_list;
  473. return QDF_STATUS_SUCCESS;
  474. }
  475. #else
  476. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  477. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  478. {
  479. return QDF_STATUS_E_NOMEM;
  480. }
  481. #endif
  482. /**
  483. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  484. * @vdev: DP Vdev handle
  485. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  486. * @desc_pool_id: Descriptor Pool ID
  487. *
  488. * Return:
  489. */
  490. static
  491. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  492. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  493. {
  494. uint8_t i;
  495. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  496. struct dp_tx_seg_info_s *seg_info;
  497. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  498. struct dp_soc *soc = vdev->pdev->soc;
  499. /* Allocate an extension descriptor */
  500. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  501. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  502. if (!msdu_ext_desc) {
  503. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  504. return NULL;
  505. }
  506. if (msdu_info->exception_fw &&
  507. qdf_unlikely(vdev->mesh_vdev)) {
  508. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  509. &msdu_info->meta_data[0],
  510. sizeof(struct htt_tx_msdu_desc_ext2_t));
  511. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  512. }
  513. switch (msdu_info->frm_type) {
  514. case dp_tx_frm_sg:
  515. case dp_tx_frm_me:
  516. case dp_tx_frm_raw:
  517. seg_info = msdu_info->u.sg_info.curr_seg;
  518. /* Update the buffer pointers in MSDU Extension Descriptor */
  519. for (i = 0; i < seg_info->frag_cnt; i++) {
  520. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  521. seg_info->frags[i].paddr_lo,
  522. seg_info->frags[i].paddr_hi,
  523. seg_info->frags[i].len);
  524. }
  525. break;
  526. case dp_tx_frm_tso:
  527. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  528. &cached_ext_desc[0]);
  529. break;
  530. default:
  531. break;
  532. }
  533. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  534. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  535. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  536. msdu_ext_desc->vaddr);
  537. return msdu_ext_desc;
  538. }
  539. /**
  540. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  541. *
  542. * @skb: skb to be traced
  543. * @msdu_id: msdu_id of the packet
  544. * @vdev_id: vdev_id of the packet
  545. *
  546. * Return: None
  547. */
  548. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  549. uint8_t vdev_id)
  550. {
  551. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  552. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  553. DPTRACE(qdf_dp_trace_ptr(skb,
  554. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  555. QDF_TRACE_DEFAULT_PDEV_ID,
  556. qdf_nbuf_data_addr(skb),
  557. sizeof(qdf_nbuf_data(skb)),
  558. msdu_id, vdev_id));
  559. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  560. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  561. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  562. msdu_id, QDF_TX));
  563. }
  564. #ifdef QCA_512M_CONFIG
  565. /**
  566. * dp_tx_pdev_pflow_control - Check if allocated tx descriptors reached max
  567. * tx descriptor configured value
  568. * @vdev: DP vdev handle
  569. *
  570. * Return: true if allocated tx descriptors reached max configured value, else
  571. * false.
  572. */
  573. static inline bool
  574. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  575. {
  576. struct dp_pdev *pdev = vdev->pdev;
  577. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  578. pdev->num_tx_allowed) {
  579. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  580. "%s: queued packets are more than max tx, drop the frame",
  581. __func__);
  582. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  583. return true;
  584. }
  585. return false;
  586. }
  587. #else
  588. static inline bool
  589. dp_tx_pdev_pflow_control(struct dp_vdev *vdev)
  590. {
  591. return false;
  592. }
  593. #endif
  594. /**
  595. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  596. * @vdev: DP vdev handle
  597. * @nbuf: skb
  598. * @desc_pool_id: Descriptor pool ID
  599. * @meta_data: Metadata to the fw
  600. * @tx_exc_metadata: Handle that holds exception path metadata
  601. * Allocate and prepare Tx descriptor with msdu information.
  602. *
  603. * Return: Pointer to Tx Descriptor on success,
  604. * NULL on failure
  605. */
  606. static
  607. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  608. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  609. struct dp_tx_msdu_info_s *msdu_info,
  610. struct cdp_tx_exception_metadata *tx_exc_metadata)
  611. {
  612. uint8_t align_pad;
  613. uint8_t is_exception = 0;
  614. uint8_t htt_hdr_size;
  615. qdf_ether_header_t *eh;
  616. struct dp_tx_desc_s *tx_desc;
  617. struct dp_pdev *pdev = vdev->pdev;
  618. struct dp_soc *soc = pdev->soc;
  619. if (dp_tx_pdev_pflow_control(vdev))
  620. return NULL;
  621. /* Allocate software Tx descriptor */
  622. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  623. if (qdf_unlikely(!tx_desc)) {
  624. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  625. return NULL;
  626. }
  627. /* Flow control/Congestion Control counters */
  628. qdf_atomic_inc(&pdev->num_tx_outstanding);
  629. /* Initialize the SW tx descriptor */
  630. tx_desc->nbuf = nbuf;
  631. tx_desc->frm_type = dp_tx_frm_std;
  632. tx_desc->tx_encap_type = (tx_exc_metadata ?
  633. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  634. tx_desc->vdev = vdev;
  635. tx_desc->pdev = pdev;
  636. tx_desc->msdu_ext_desc = NULL;
  637. tx_desc->pkt_offset = 0;
  638. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  639. /*
  640. * For special modes (vdev_type == ocb or mesh), data frames should be
  641. * transmitted using varying transmit parameters (tx spec) which include
  642. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  643. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  644. * These frames are sent as exception packets to firmware.
  645. *
  646. * HW requirement is that metadata should always point to a
  647. * 8-byte aligned address. So we add alignment pad to start of buffer.
  648. * HTT Metadata should be ensured to be multiple of 8-bytes,
  649. * to get 8-byte aligned start address along with align_pad added
  650. *
  651. * |-----------------------------|
  652. * | |
  653. * |-----------------------------| <-----Buffer Pointer Address given
  654. * | | ^ in HW descriptor (aligned)
  655. * | HTT Metadata | |
  656. * | | |
  657. * | | | Packet Offset given in descriptor
  658. * | | |
  659. * |-----------------------------| |
  660. * | Alignment Pad | v
  661. * |-----------------------------| <----- Actual buffer start address
  662. * | SKB Data | (Unaligned)
  663. * | |
  664. * | |
  665. * | |
  666. * | |
  667. * | |
  668. * |-----------------------------|
  669. */
  670. if (qdf_unlikely((msdu_info->exception_fw)) ||
  671. (vdev->opmode == wlan_op_mode_ocb)) {
  672. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  673. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  674. DP_STATS_INC(vdev,
  675. tx_i.dropped.headroom_insufficient, 1);
  676. goto failure;
  677. }
  678. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  680. "qdf_nbuf_push_head failed");
  681. goto failure;
  682. }
  683. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  684. msdu_info->meta_data);
  685. if (htt_hdr_size == 0)
  686. goto failure;
  687. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  688. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  689. is_exception = 1;
  690. }
  691. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  692. qdf_nbuf_map(soc->osdev, nbuf,
  693. QDF_DMA_TO_DEVICE))) {
  694. /* Handle failure */
  695. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  696. "qdf_nbuf_map failed");
  697. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  698. goto failure;
  699. }
  700. if (qdf_unlikely(vdev->nawds_enabled)) {
  701. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  702. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  703. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  704. is_exception = 1;
  705. }
  706. }
  707. #if !TQM_BYPASS_WAR
  708. if (is_exception || tx_exc_metadata)
  709. #endif
  710. {
  711. /* Temporary WAR due to TQM VP issues */
  712. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  713. qdf_atomic_inc(&pdev->num_tx_exception);
  714. }
  715. return tx_desc;
  716. failure:
  717. dp_tx_desc_release(tx_desc, desc_pool_id);
  718. return NULL;
  719. }
  720. /**
  721. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  722. * @vdev: DP vdev handle
  723. * @nbuf: skb
  724. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  725. * @desc_pool_id : Descriptor Pool ID
  726. *
  727. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  728. * information. For frames wth fragments, allocate and prepare
  729. * an MSDU extension descriptor
  730. *
  731. * Return: Pointer to Tx Descriptor on success,
  732. * NULL on failure
  733. */
  734. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  735. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  736. uint8_t desc_pool_id)
  737. {
  738. struct dp_tx_desc_s *tx_desc;
  739. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  740. struct dp_pdev *pdev = vdev->pdev;
  741. struct dp_soc *soc = pdev->soc;
  742. if (dp_tx_pdev_pflow_control(vdev))
  743. return NULL;
  744. /* Allocate software Tx descriptor */
  745. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  746. if (!tx_desc) {
  747. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  748. return NULL;
  749. }
  750. /* Flow control/Congestion Control counters */
  751. qdf_atomic_inc(&pdev->num_tx_outstanding);
  752. /* Initialize the SW tx descriptor */
  753. tx_desc->nbuf = nbuf;
  754. tx_desc->frm_type = msdu_info->frm_type;
  755. tx_desc->tx_encap_type = vdev->tx_encap_type;
  756. tx_desc->vdev = vdev;
  757. tx_desc->pdev = pdev;
  758. tx_desc->pkt_offset = 0;
  759. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  760. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  761. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  762. /* Handle scattered frames - TSO/SG/ME */
  763. /* Allocate and prepare an extension descriptor for scattered frames */
  764. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  765. if (!msdu_ext_desc) {
  766. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  767. "%s Tx Extension Descriptor Alloc Fail",
  768. __func__);
  769. goto failure;
  770. }
  771. #if TQM_BYPASS_WAR
  772. /* Temporary WAR due to TQM VP issues */
  773. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  774. qdf_atomic_inc(&pdev->num_tx_exception);
  775. #endif
  776. if (qdf_unlikely(msdu_info->exception_fw))
  777. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  778. tx_desc->msdu_ext_desc = msdu_ext_desc;
  779. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  780. return tx_desc;
  781. failure:
  782. dp_tx_desc_release(tx_desc, desc_pool_id);
  783. return NULL;
  784. }
  785. /**
  786. * dp_tx_prepare_raw() - Prepare RAW packet TX
  787. * @vdev: DP vdev handle
  788. * @nbuf: buffer pointer
  789. * @seg_info: Pointer to Segment info Descriptor to be prepared
  790. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  791. * descriptor
  792. *
  793. * Return:
  794. */
  795. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  796. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  797. {
  798. qdf_nbuf_t curr_nbuf = NULL;
  799. uint16_t total_len = 0;
  800. qdf_dma_addr_t paddr;
  801. int32_t i;
  802. int32_t mapped_buf_num = 0;
  803. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  804. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  805. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  806. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  807. if (vdev->raw_mode_war &&
  808. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS))
  809. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  810. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  811. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  812. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  813. QDF_DMA_TO_DEVICE)) {
  814. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  815. "%s dma map error ", __func__);
  816. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  817. mapped_buf_num = i;
  818. goto error;
  819. }
  820. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  821. seg_info->frags[i].paddr_lo = paddr;
  822. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  823. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  824. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  825. total_len += qdf_nbuf_len(curr_nbuf);
  826. }
  827. seg_info->frag_cnt = i;
  828. seg_info->total_len = total_len;
  829. seg_info->next = NULL;
  830. sg_info->curr_seg = seg_info;
  831. msdu_info->frm_type = dp_tx_frm_raw;
  832. msdu_info->num_seg = 1;
  833. return nbuf;
  834. error:
  835. i = 0;
  836. while (nbuf) {
  837. curr_nbuf = nbuf;
  838. if (i < mapped_buf_num) {
  839. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  840. i++;
  841. }
  842. nbuf = qdf_nbuf_next(nbuf);
  843. qdf_nbuf_free(curr_nbuf);
  844. }
  845. return NULL;
  846. }
  847. /**
  848. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  849. * @soc: DP Soc Handle
  850. * @vdev: DP vdev handle
  851. * @tx_desc: Tx Descriptor Handle
  852. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  853. * @fw_metadata: Metadata to send to Target Firmware along with frame
  854. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  855. * @tx_exc_metadata: Handle that holds exception path meta data
  856. *
  857. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  858. * from software Tx descriptor
  859. *
  860. * Return:
  861. */
  862. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  863. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  864. uint16_t fw_metadata, uint8_t ring_id,
  865. struct cdp_tx_exception_metadata
  866. *tx_exc_metadata)
  867. {
  868. uint8_t type;
  869. uint16_t length;
  870. void *hal_tx_desc, *hal_tx_desc_cached;
  871. qdf_dma_addr_t dma_addr;
  872. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  873. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  874. tx_exc_metadata->sec_type : vdev->sec_type);
  875. /* Return Buffer Manager ID */
  876. uint8_t bm_id = ring_id;
  877. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  878. hal_tx_desc_cached = (void *) cached_desc;
  879. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  880. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  881. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  882. type = HAL_TX_BUF_TYPE_EXT_DESC;
  883. dma_addr = tx_desc->msdu_ext_desc->paddr;
  884. } else {
  885. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  886. type = HAL_TX_BUF_TYPE_BUFFER;
  887. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  888. }
  889. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  890. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  891. dma_addr, bm_id, tx_desc->id,
  892. type, soc->hal_soc);
  893. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  894. return QDF_STATUS_E_RESOURCES;
  895. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  896. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  897. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  898. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  899. vdev->pdev->lmac_id);
  900. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  901. vdev->search_type);
  902. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  903. vdev->bss_ast_hash);
  904. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  905. vdev->dscp_tid_map_id);
  906. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  907. sec_type_map[sec_type]);
  908. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  909. length, type, (uint64_t)dma_addr,
  910. tx_desc->pkt_offset, tx_desc->id);
  911. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  912. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  913. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  914. vdev->hal_desc_addr_search_flags);
  915. /* verify checksum offload configuration*/
  916. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  917. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  918. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  919. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  920. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  921. }
  922. if (tid != HTT_TX_EXT_TID_INVALID)
  923. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  924. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  925. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  926. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  927. /* Sync cached descriptor with HW */
  928. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  929. if (!hal_tx_desc) {
  930. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  931. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  932. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  933. return QDF_STATUS_E_RESOURCES;
  934. }
  935. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  936. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  937. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  938. return QDF_STATUS_SUCCESS;
  939. }
  940. /**
  941. * dp_cce_classify() - Classify the frame based on CCE rules
  942. * @vdev: DP vdev handle
  943. * @nbuf: skb
  944. *
  945. * Classify frames based on CCE rules
  946. * Return: bool( true if classified,
  947. * else false)
  948. */
  949. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  950. {
  951. qdf_ether_header_t *eh = NULL;
  952. uint16_t ether_type;
  953. qdf_llc_t *llcHdr;
  954. qdf_nbuf_t nbuf_clone = NULL;
  955. qdf_dot3_qosframe_t *qos_wh = NULL;
  956. /* for mesh packets don't do any classification */
  957. if (qdf_unlikely(vdev->mesh_vdev))
  958. return false;
  959. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  960. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  961. ether_type = eh->ether_type;
  962. llcHdr = (qdf_llc_t *)(nbuf->data +
  963. sizeof(qdf_ether_header_t));
  964. } else {
  965. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  966. /* For encrypted packets don't do any classification */
  967. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  968. return false;
  969. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  970. if (qdf_unlikely(
  971. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  972. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  973. ether_type = *(uint16_t *)(nbuf->data
  974. + QDF_IEEE80211_4ADDR_HDR_LEN
  975. + sizeof(qdf_llc_t)
  976. - sizeof(ether_type));
  977. llcHdr = (qdf_llc_t *)(nbuf->data +
  978. QDF_IEEE80211_4ADDR_HDR_LEN);
  979. } else {
  980. ether_type = *(uint16_t *)(nbuf->data
  981. + QDF_IEEE80211_3ADDR_HDR_LEN
  982. + sizeof(qdf_llc_t)
  983. - sizeof(ether_type));
  984. llcHdr = (qdf_llc_t *)(nbuf->data +
  985. QDF_IEEE80211_3ADDR_HDR_LEN);
  986. }
  987. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  988. && (ether_type ==
  989. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  990. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  991. return true;
  992. }
  993. }
  994. return false;
  995. }
  996. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  997. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  998. sizeof(*llcHdr));
  999. nbuf_clone = qdf_nbuf_clone(nbuf);
  1000. if (qdf_unlikely(nbuf_clone)) {
  1001. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1002. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1003. qdf_nbuf_pull_head(nbuf_clone,
  1004. sizeof(qdf_net_vlanhdr_t));
  1005. }
  1006. }
  1007. } else {
  1008. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1009. nbuf_clone = qdf_nbuf_clone(nbuf);
  1010. if (qdf_unlikely(nbuf_clone)) {
  1011. qdf_nbuf_pull_head(nbuf_clone,
  1012. sizeof(qdf_net_vlanhdr_t));
  1013. }
  1014. }
  1015. }
  1016. if (qdf_unlikely(nbuf_clone))
  1017. nbuf = nbuf_clone;
  1018. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1019. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1020. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1021. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1022. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1023. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1024. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1025. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1026. if (qdf_unlikely(nbuf_clone))
  1027. qdf_nbuf_free(nbuf_clone);
  1028. return true;
  1029. }
  1030. if (qdf_unlikely(nbuf_clone))
  1031. qdf_nbuf_free(nbuf_clone);
  1032. return false;
  1033. }
  1034. /**
  1035. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1036. * @vdev: DP vdev handle
  1037. * @nbuf: skb
  1038. *
  1039. * Extract the DSCP or PCP information from frame and map into TID value.
  1040. *
  1041. * Return: void
  1042. */
  1043. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1044. struct dp_tx_msdu_info_s *msdu_info)
  1045. {
  1046. uint8_t tos = 0, dscp_tid_override = 0;
  1047. uint8_t *hdr_ptr, *L3datap;
  1048. uint8_t is_mcast = 0;
  1049. qdf_ether_header_t *eh = NULL;
  1050. qdf_ethervlan_header_t *evh = NULL;
  1051. uint16_t ether_type;
  1052. qdf_llc_t *llcHdr;
  1053. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1054. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1055. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1056. eh = (qdf_ether_header_t *)nbuf->data;
  1057. hdr_ptr = eh->ether_dhost;
  1058. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1059. } else {
  1060. qdf_dot3_qosframe_t *qos_wh =
  1061. (qdf_dot3_qosframe_t *) nbuf->data;
  1062. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1063. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1064. return;
  1065. }
  1066. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1067. ether_type = eh->ether_type;
  1068. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1069. /*
  1070. * Check if packet is dot3 or eth2 type.
  1071. */
  1072. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1073. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1074. sizeof(*llcHdr));
  1075. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1076. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1077. sizeof(*llcHdr);
  1078. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1079. + sizeof(*llcHdr) +
  1080. sizeof(qdf_net_vlanhdr_t));
  1081. } else {
  1082. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1083. sizeof(*llcHdr);
  1084. }
  1085. } else {
  1086. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1087. evh = (qdf_ethervlan_header_t *) eh;
  1088. ether_type = evh->ether_type;
  1089. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1090. }
  1091. }
  1092. /*
  1093. * Find priority from IP TOS DSCP field
  1094. */
  1095. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1096. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1097. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1098. /* Only for unicast frames */
  1099. if (!is_mcast) {
  1100. /* send it on VO queue */
  1101. msdu_info->tid = DP_VO_TID;
  1102. }
  1103. } else {
  1104. /*
  1105. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1106. * from TOS byte.
  1107. */
  1108. tos = ip->ip_tos;
  1109. dscp_tid_override = 1;
  1110. }
  1111. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1112. /* TODO
  1113. * use flowlabel
  1114. *igmpmld cases to be handled in phase 2
  1115. */
  1116. unsigned long ver_pri_flowlabel;
  1117. unsigned long pri;
  1118. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1119. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1120. DP_IPV6_PRIORITY_SHIFT;
  1121. tos = pri;
  1122. dscp_tid_override = 1;
  1123. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1124. msdu_info->tid = DP_VO_TID;
  1125. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1126. /* Only for unicast frames */
  1127. if (!is_mcast) {
  1128. /* send ucast arp on VO queue */
  1129. msdu_info->tid = DP_VO_TID;
  1130. }
  1131. }
  1132. /*
  1133. * Assign all MCAST packets to BE
  1134. */
  1135. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1136. if (is_mcast) {
  1137. tos = 0;
  1138. dscp_tid_override = 1;
  1139. }
  1140. }
  1141. if (dscp_tid_override == 1) {
  1142. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1143. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1144. }
  1145. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1146. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1147. return;
  1148. }
  1149. /**
  1150. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1151. * @vdev: DP vdev handle
  1152. * @nbuf: skb
  1153. *
  1154. * Software based TID classification is required when more than 2 DSCP-TID
  1155. * mapping tables are needed.
  1156. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1157. *
  1158. * Return: void
  1159. */
  1160. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1161. struct dp_tx_msdu_info_s *msdu_info)
  1162. {
  1163. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1164. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1165. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1166. return;
  1167. /* for mesh packets don't do any classification */
  1168. if (qdf_unlikely(vdev->mesh_vdev))
  1169. return;
  1170. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1171. }
  1172. #ifdef FEATURE_WLAN_TDLS
  1173. /**
  1174. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1175. * @tx_desc: TX descriptor
  1176. *
  1177. * Return: None
  1178. */
  1179. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1180. {
  1181. if (tx_desc->vdev) {
  1182. if (tx_desc->vdev->is_tdls_frame) {
  1183. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1184. tx_desc->vdev->is_tdls_frame = false;
  1185. }
  1186. }
  1187. }
  1188. /**
  1189. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1190. * @tx_desc: TX descriptor
  1191. * @vdev: datapath vdev handle
  1192. *
  1193. * Return: None
  1194. */
  1195. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1196. struct dp_vdev *vdev)
  1197. {
  1198. struct hal_tx_completion_status ts = {0};
  1199. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1200. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1201. if (vdev->tx_non_std_data_callback.func) {
  1202. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1203. vdev->tx_non_std_data_callback.func(
  1204. vdev->tx_non_std_data_callback.ctxt,
  1205. nbuf, ts.status);
  1206. return;
  1207. }
  1208. }
  1209. #else
  1210. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1211. {
  1212. }
  1213. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1214. struct dp_vdev *vdev)
  1215. {
  1216. }
  1217. #endif
  1218. /**
  1219. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1220. * @vdev: DP vdev handle
  1221. * @nbuf: skb
  1222. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1223. * @meta_data: Metadata to the fw
  1224. * @tx_q: Tx queue to be used for this Tx frame
  1225. * @peer_id: peer_id of the peer in case of NAWDS frames
  1226. * @tx_exc_metadata: Handle that holds exception path metadata
  1227. *
  1228. * Return: NULL on success,
  1229. * nbuf when it fails to send
  1230. */
  1231. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1232. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1233. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1234. {
  1235. struct dp_pdev *pdev = vdev->pdev;
  1236. struct dp_soc *soc = pdev->soc;
  1237. struct dp_tx_desc_s *tx_desc;
  1238. QDF_STATUS status;
  1239. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1240. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1241. uint16_t htt_tcl_metadata = 0;
  1242. uint8_t tid = msdu_info->tid;
  1243. struct cdp_tid_tx_stats *tid_stats = NULL;
  1244. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1245. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1246. msdu_info, tx_exc_metadata);
  1247. if (!tx_desc) {
  1248. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1249. vdev, tx_q->desc_pool_id);
  1250. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1251. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1252. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1253. return nbuf;
  1254. }
  1255. if (qdf_unlikely(soc->cce_disable)) {
  1256. if (dp_cce_classify(vdev, nbuf) == true) {
  1257. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1258. tid = DP_VO_TID;
  1259. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1260. }
  1261. }
  1262. dp_tx_update_tdls_flags(tx_desc);
  1263. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1264. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1265. "%s %d : HAL RING Access Failed -- %pK",
  1266. __func__, __LINE__, hal_srng);
  1267. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1268. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1269. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1270. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1271. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1272. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1273. goto fail_return;
  1274. }
  1275. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1276. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1277. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1278. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1279. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1280. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1281. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1282. peer_id);
  1283. } else
  1284. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1285. if (msdu_info->exception_fw) {
  1286. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1287. }
  1288. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1289. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1290. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1291. if (status != QDF_STATUS_SUCCESS) {
  1292. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1293. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1294. __func__, tx_desc, tx_q->ring_id);
  1295. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1296. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1297. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1298. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1299. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1300. goto fail_return;
  1301. }
  1302. nbuf = NULL;
  1303. fail_return:
  1304. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1305. hal_srng_access_end(soc->hal_soc, hal_srng);
  1306. hif_pm_runtime_put(soc->hif_handle);
  1307. } else {
  1308. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1309. }
  1310. return nbuf;
  1311. }
  1312. /**
  1313. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1314. * @vdev: DP vdev handle
  1315. * @nbuf: skb
  1316. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1317. *
  1318. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1319. *
  1320. * Return: NULL on success,
  1321. * nbuf when it fails to send
  1322. */
  1323. #if QDF_LOCK_STATS
  1324. static noinline
  1325. #else
  1326. static
  1327. #endif
  1328. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1329. struct dp_tx_msdu_info_s *msdu_info)
  1330. {
  1331. uint8_t i;
  1332. struct dp_pdev *pdev = vdev->pdev;
  1333. struct dp_soc *soc = pdev->soc;
  1334. struct dp_tx_desc_s *tx_desc;
  1335. bool is_cce_classified = false;
  1336. QDF_STATUS status;
  1337. uint16_t htt_tcl_metadata = 0;
  1338. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1339. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1340. struct cdp_tid_tx_stats *tid_stats = NULL;
  1341. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1342. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1343. "%s %d : HAL RING Access Failed -- %pK",
  1344. __func__, __LINE__, hal_srng);
  1345. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1346. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[msdu_info->tid];
  1347. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1348. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1349. return nbuf;
  1350. }
  1351. if (qdf_unlikely(soc->cce_disable)) {
  1352. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1353. if (is_cce_classified) {
  1354. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1355. msdu_info->tid = DP_VO_TID;
  1356. }
  1357. }
  1358. if (msdu_info->frm_type == dp_tx_frm_me)
  1359. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1360. i = 0;
  1361. /* Print statement to track i and num_seg */
  1362. /*
  1363. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1364. * descriptors using information in msdu_info
  1365. */
  1366. while (i < msdu_info->num_seg) {
  1367. /*
  1368. * Setup Tx descriptor for an MSDU, and MSDU extension
  1369. * descriptor
  1370. */
  1371. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1372. tx_q->desc_pool_id);
  1373. if (!tx_desc) {
  1374. if (msdu_info->frm_type == dp_tx_frm_me) {
  1375. dp_tx_me_free_buf(pdev,
  1376. (void *)(msdu_info->u.sg_info
  1377. .curr_seg->frags[0].vaddr));
  1378. }
  1379. goto done;
  1380. }
  1381. if (msdu_info->frm_type == dp_tx_frm_me) {
  1382. tx_desc->me_buffer =
  1383. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1384. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1385. }
  1386. if (is_cce_classified)
  1387. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1388. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1389. if (msdu_info->exception_fw) {
  1390. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1391. }
  1392. /*
  1393. * Enqueue the Tx MSDU descriptor to HW for transmit
  1394. */
  1395. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1396. htt_tcl_metadata, tx_q->ring_id, NULL);
  1397. if (status != QDF_STATUS_SUCCESS) {
  1398. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1399. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1400. __func__, tx_desc, tx_q->ring_id);
  1401. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1402. tid_stats = &pdev->stats.tid_stats.
  1403. tid_tx_stats[msdu_info->tid];
  1404. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1405. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1406. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1407. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1408. goto done;
  1409. }
  1410. /*
  1411. * TODO
  1412. * if tso_info structure can be modified to have curr_seg
  1413. * as first element, following 2 blocks of code (for TSO and SG)
  1414. * can be combined into 1
  1415. */
  1416. /*
  1417. * For frames with multiple segments (TSO, ME), jump to next
  1418. * segment.
  1419. */
  1420. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1421. if (msdu_info->u.tso_info.curr_seg->next) {
  1422. msdu_info->u.tso_info.curr_seg =
  1423. msdu_info->u.tso_info.curr_seg->next;
  1424. /*
  1425. * If this is a jumbo nbuf, then increment the number of
  1426. * nbuf users for each additional segment of the msdu.
  1427. * This will ensure that the skb is freed only after
  1428. * receiving tx completion for all segments of an nbuf
  1429. */
  1430. qdf_nbuf_inc_users(nbuf);
  1431. /* Check with MCL if this is needed */
  1432. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1433. }
  1434. }
  1435. /*
  1436. * For Multicast-Unicast converted packets,
  1437. * each converted frame (for a client) is represented as
  1438. * 1 segment
  1439. */
  1440. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1441. (msdu_info->frm_type == dp_tx_frm_me)) {
  1442. if (msdu_info->u.sg_info.curr_seg->next) {
  1443. msdu_info->u.sg_info.curr_seg =
  1444. msdu_info->u.sg_info.curr_seg->next;
  1445. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1446. }
  1447. }
  1448. i++;
  1449. }
  1450. nbuf = NULL;
  1451. done:
  1452. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1453. hal_srng_access_end(soc->hal_soc, hal_srng);
  1454. hif_pm_runtime_put(soc->hif_handle);
  1455. } else {
  1456. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1457. }
  1458. return nbuf;
  1459. }
  1460. /**
  1461. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1462. * for SG frames
  1463. * @vdev: DP vdev handle
  1464. * @nbuf: skb
  1465. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1466. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1467. *
  1468. * Return: NULL on success,
  1469. * nbuf when it fails to send
  1470. */
  1471. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1472. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1473. {
  1474. uint32_t cur_frag, nr_frags;
  1475. qdf_dma_addr_t paddr;
  1476. struct dp_tx_sg_info_s *sg_info;
  1477. sg_info = &msdu_info->u.sg_info;
  1478. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1479. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1480. QDF_DMA_TO_DEVICE)) {
  1481. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1482. "dma map error");
  1483. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1484. qdf_nbuf_free(nbuf);
  1485. return NULL;
  1486. }
  1487. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1488. seg_info->frags[0].paddr_lo = paddr;
  1489. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1490. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1491. seg_info->frags[0].vaddr = (void *) nbuf;
  1492. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1493. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1494. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1495. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1496. "frag dma map error");
  1497. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1498. qdf_nbuf_free(nbuf);
  1499. return NULL;
  1500. }
  1501. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1502. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1503. seg_info->frags[cur_frag + 1].paddr_hi =
  1504. ((uint64_t) paddr) >> 32;
  1505. seg_info->frags[cur_frag + 1].len =
  1506. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1507. }
  1508. seg_info->frag_cnt = (cur_frag + 1);
  1509. seg_info->total_len = qdf_nbuf_len(nbuf);
  1510. seg_info->next = NULL;
  1511. sg_info->curr_seg = seg_info;
  1512. msdu_info->frm_type = dp_tx_frm_sg;
  1513. msdu_info->num_seg = 1;
  1514. return nbuf;
  1515. }
  1516. #ifdef MESH_MODE_SUPPORT
  1517. /**
  1518. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1519. and prepare msdu_info for mesh frames.
  1520. * @vdev: DP vdev handle
  1521. * @nbuf: skb
  1522. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1523. *
  1524. * Return: NULL on failure,
  1525. * nbuf when extracted successfully
  1526. */
  1527. static
  1528. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1529. struct dp_tx_msdu_info_s *msdu_info)
  1530. {
  1531. struct meta_hdr_s *mhdr;
  1532. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1533. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1534. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1535. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1536. msdu_info->exception_fw = 0;
  1537. goto remove_meta_hdr;
  1538. }
  1539. msdu_info->exception_fw = 1;
  1540. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1541. meta_data->host_tx_desc_pool = 1;
  1542. meta_data->update_peer_cache = 1;
  1543. meta_data->learning_frame = 1;
  1544. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1545. meta_data->power = mhdr->power;
  1546. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1547. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1548. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1549. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1550. meta_data->dyn_bw = 1;
  1551. meta_data->valid_pwr = 1;
  1552. meta_data->valid_mcs_mask = 1;
  1553. meta_data->valid_nss_mask = 1;
  1554. meta_data->valid_preamble_type = 1;
  1555. meta_data->valid_retries = 1;
  1556. meta_data->valid_bw_info = 1;
  1557. }
  1558. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1559. meta_data->encrypt_type = 0;
  1560. meta_data->valid_encrypt_type = 1;
  1561. meta_data->learning_frame = 0;
  1562. }
  1563. meta_data->valid_key_flags = 1;
  1564. meta_data->key_flags = (mhdr->keyix & 0x3);
  1565. remove_meta_hdr:
  1566. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1567. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1568. "qdf_nbuf_pull_head failed");
  1569. qdf_nbuf_free(nbuf);
  1570. return NULL;
  1571. }
  1572. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1573. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1574. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1575. " tid %d to_fw %d",
  1576. __func__, msdu_info->meta_data[0],
  1577. msdu_info->meta_data[1],
  1578. msdu_info->meta_data[2],
  1579. msdu_info->meta_data[3],
  1580. msdu_info->meta_data[4],
  1581. msdu_info->meta_data[5],
  1582. msdu_info->tid, msdu_info->exception_fw);
  1583. return nbuf;
  1584. }
  1585. #else
  1586. static
  1587. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1588. struct dp_tx_msdu_info_s *msdu_info)
  1589. {
  1590. return nbuf;
  1591. }
  1592. #endif
  1593. #ifdef DP_FEATURE_NAWDS_TX
  1594. /**
  1595. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1596. * @vdev: dp_vdev handle
  1597. * @nbuf: skb
  1598. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1599. * @tx_q: Tx queue to be used for this Tx frame
  1600. * @meta_data: Meta date for mesh
  1601. * @peer_id: peer_id of the peer in case of NAWDS frames
  1602. *
  1603. * return: NULL on success nbuf on failure
  1604. */
  1605. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1606. struct dp_tx_msdu_info_s *msdu_info)
  1607. {
  1608. struct dp_peer *peer = NULL;
  1609. struct dp_soc *soc = vdev->pdev->soc;
  1610. struct dp_ast_entry *ast_entry = NULL;
  1611. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1612. uint16_t peer_id = HTT_INVALID_PEER;
  1613. struct dp_peer *sa_peer = NULL;
  1614. qdf_nbuf_t nbuf_copy;
  1615. qdf_spin_lock_bh(&(soc->ast_lock));
  1616. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1617. (soc,
  1618. (uint8_t *)(eh->ether_shost),
  1619. vdev->pdev->pdev_id);
  1620. if (ast_entry)
  1621. sa_peer = ast_entry->peer;
  1622. qdf_spin_unlock_bh(&(soc->ast_lock));
  1623. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1624. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1625. (peer->nawds_enabled)) {
  1626. if (sa_peer == peer) {
  1627. QDF_TRACE(QDF_MODULE_ID_DP,
  1628. QDF_TRACE_LEVEL_DEBUG,
  1629. " %s: broadcast multicast packet",
  1630. __func__);
  1631. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1632. continue;
  1633. }
  1634. nbuf_copy = qdf_nbuf_copy(nbuf);
  1635. if (!nbuf_copy) {
  1636. QDF_TRACE(QDF_MODULE_ID_DP,
  1637. QDF_TRACE_LEVEL_ERROR,
  1638. "nbuf copy failed");
  1639. }
  1640. peer_id = peer->peer_ids[0];
  1641. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1642. msdu_info, peer_id, NULL);
  1643. if (nbuf_copy) {
  1644. qdf_nbuf_free(nbuf_copy);
  1645. continue;
  1646. }
  1647. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1648. 1, qdf_nbuf_len(nbuf));
  1649. }
  1650. }
  1651. if (peer_id == HTT_INVALID_PEER)
  1652. return nbuf;
  1653. return NULL;
  1654. }
  1655. #endif
  1656. /**
  1657. * dp_check_exc_metadata() - Checks if parameters are valid
  1658. * @tx_exc - holds all exception path parameters
  1659. *
  1660. * Returns true when all the parameters are valid else false
  1661. *
  1662. */
  1663. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1664. {
  1665. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1666. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1667. tx_exc->sec_type > cdp_num_sec_types) {
  1668. return false;
  1669. }
  1670. return true;
  1671. }
  1672. /**
  1673. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1674. * @vap_dev: DP vdev handle
  1675. * @nbuf: skb
  1676. * @tx_exc_metadata: Handle that holds exception path meta data
  1677. *
  1678. * Entry point for Core Tx layer (DP_TX) invoked from
  1679. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1680. *
  1681. * Return: NULL on success,
  1682. * nbuf when it fails to send
  1683. */
  1684. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1685. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1686. {
  1687. qdf_ether_header_t *eh = NULL;
  1688. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1689. struct dp_tx_msdu_info_s msdu_info;
  1690. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1691. msdu_info.tid = tx_exc_metadata->tid;
  1692. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1693. dp_verbose_debug("skb %pM", nbuf->data);
  1694. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1695. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1696. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1697. "Invalid parameters in exception path");
  1698. goto fail;
  1699. }
  1700. /* Basic sanity checks for unsupported packets */
  1701. /* MESH mode */
  1702. if (qdf_unlikely(vdev->mesh_vdev)) {
  1703. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1704. "Mesh mode is not supported in exception path");
  1705. goto fail;
  1706. }
  1707. /* TSO or SG */
  1708. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1709. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1710. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1711. "TSO and SG are not supported in exception path");
  1712. goto fail;
  1713. }
  1714. /* RAW */
  1715. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1716. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1717. "Raw frame is not supported in exception path");
  1718. goto fail;
  1719. }
  1720. /* Mcast enhancement*/
  1721. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1722. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1723. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1724. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1725. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1726. }
  1727. }
  1728. /*
  1729. * Get HW Queue to use for this frame.
  1730. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1731. * dedicated for data and 1 for command.
  1732. * "queue_id" maps to one hardware ring.
  1733. * With each ring, we also associate a unique Tx descriptor pool
  1734. * to minimize lock contention for these resources.
  1735. */
  1736. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1737. /* Single linear frame */
  1738. /*
  1739. * If nbuf is a simple linear frame, use send_single function to
  1740. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1741. * SRNG. There is no need to setup a MSDU extension descriptor.
  1742. */
  1743. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1744. tx_exc_metadata->peer_id, tx_exc_metadata);
  1745. return nbuf;
  1746. fail:
  1747. dp_verbose_debug("pkt send failed");
  1748. return nbuf;
  1749. }
  1750. /**
  1751. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1752. * @vap_dev: DP vdev handle
  1753. * @nbuf: skb
  1754. *
  1755. * Entry point for Core Tx layer (DP_TX) invoked from
  1756. * hard_start_xmit in OSIF/HDD
  1757. *
  1758. * Return: NULL on success,
  1759. * nbuf when it fails to send
  1760. */
  1761. #ifdef MESH_MODE_SUPPORT
  1762. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1763. {
  1764. struct meta_hdr_s *mhdr;
  1765. qdf_nbuf_t nbuf_mesh = NULL;
  1766. qdf_nbuf_t nbuf_clone = NULL;
  1767. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1768. uint8_t no_enc_frame = 0;
  1769. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1770. if (!nbuf_mesh) {
  1771. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1772. "qdf_nbuf_unshare failed");
  1773. return nbuf;
  1774. }
  1775. nbuf = nbuf_mesh;
  1776. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1777. if ((vdev->sec_type != cdp_sec_type_none) &&
  1778. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1779. no_enc_frame = 1;
  1780. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1781. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1782. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1783. !no_enc_frame) {
  1784. nbuf_clone = qdf_nbuf_clone(nbuf);
  1785. if (!nbuf_clone) {
  1786. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1787. "qdf_nbuf_clone failed");
  1788. return nbuf;
  1789. }
  1790. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1791. }
  1792. if (nbuf_clone) {
  1793. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1794. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1795. } else {
  1796. qdf_nbuf_free(nbuf_clone);
  1797. }
  1798. }
  1799. if (no_enc_frame)
  1800. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1801. else
  1802. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1803. nbuf = dp_tx_send(vap_dev, nbuf);
  1804. if ((!nbuf) && no_enc_frame) {
  1805. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1806. }
  1807. return nbuf;
  1808. }
  1809. #else
  1810. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1811. {
  1812. return dp_tx_send(vap_dev, nbuf);
  1813. }
  1814. #endif
  1815. /**
  1816. * dp_tx_send() - Transmit a frame on a given VAP
  1817. * @vap_dev: DP vdev handle
  1818. * @nbuf: skb
  1819. *
  1820. * Entry point for Core Tx layer (DP_TX) invoked from
  1821. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1822. * cases
  1823. *
  1824. * Return: NULL on success,
  1825. * nbuf when it fails to send
  1826. */
  1827. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1828. {
  1829. qdf_ether_header_t *eh = NULL;
  1830. struct dp_tx_msdu_info_s msdu_info;
  1831. struct dp_tx_seg_info_s seg_info;
  1832. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1833. uint16_t peer_id = HTT_INVALID_PEER;
  1834. qdf_nbuf_t nbuf_mesh = NULL;
  1835. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1836. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1837. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1838. dp_verbose_debug("skb %pM", nbuf->data);
  1839. /*
  1840. * Set Default Host TID value to invalid TID
  1841. * (TID override disabled)
  1842. */
  1843. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1844. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1845. if (qdf_unlikely(vdev->mesh_vdev)) {
  1846. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1847. &msdu_info);
  1848. if (!nbuf_mesh) {
  1849. dp_verbose_debug("Extracting mesh metadata failed");
  1850. return nbuf;
  1851. }
  1852. nbuf = nbuf_mesh;
  1853. }
  1854. /*
  1855. * Get HW Queue to use for this frame.
  1856. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1857. * dedicated for data and 1 for command.
  1858. * "queue_id" maps to one hardware ring.
  1859. * With each ring, we also associate a unique Tx descriptor pool
  1860. * to minimize lock contention for these resources.
  1861. */
  1862. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1863. /*
  1864. * TCL H/W supports 2 DSCP-TID mapping tables.
  1865. * Table 1 - Default DSCP-TID mapping table
  1866. * Table 2 - 1 DSCP-TID override table
  1867. *
  1868. * If we need a different DSCP-TID mapping for this vap,
  1869. * call tid_classify to extract DSCP/ToS from frame and
  1870. * map to a TID and store in msdu_info. This is later used
  1871. * to fill in TCL Input descriptor (per-packet TID override).
  1872. */
  1873. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1874. /*
  1875. * Classify the frame and call corresponding
  1876. * "prepare" function which extracts the segment (TSO)
  1877. * and fragmentation information (for TSO , SG, ME, or Raw)
  1878. * into MSDU_INFO structure which is later used to fill
  1879. * SW and HW descriptors.
  1880. */
  1881. if (qdf_nbuf_is_tso(nbuf)) {
  1882. dp_verbose_debug("TSO frame %pK", vdev);
  1883. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1884. qdf_nbuf_len(nbuf));
  1885. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1886. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1887. qdf_nbuf_len(nbuf));
  1888. return nbuf;
  1889. }
  1890. goto send_multiple;
  1891. }
  1892. /* SG */
  1893. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1894. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1895. if (!nbuf)
  1896. return NULL;
  1897. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1898. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1899. qdf_nbuf_len(nbuf));
  1900. goto send_multiple;
  1901. }
  1902. #ifdef ATH_SUPPORT_IQUE
  1903. /* Mcast to Ucast Conversion*/
  1904. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1905. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1906. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1907. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1908. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1909. DP_STATS_INC_PKT(vdev,
  1910. tx_i.mcast_en.mcast_pkt, 1,
  1911. qdf_nbuf_len(nbuf));
  1912. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1913. QDF_STATUS_SUCCESS) {
  1914. return NULL;
  1915. }
  1916. }
  1917. }
  1918. #endif
  1919. /* RAW */
  1920. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1921. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1922. if (!nbuf)
  1923. return NULL;
  1924. dp_verbose_debug("Raw frame %pK", vdev);
  1925. goto send_multiple;
  1926. }
  1927. /* Single linear frame */
  1928. /*
  1929. * If nbuf is a simple linear frame, use send_single function to
  1930. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1931. * SRNG. There is no need to setup a MSDU extension descriptor.
  1932. */
  1933. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1934. return nbuf;
  1935. send_multiple:
  1936. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1937. return nbuf;
  1938. }
  1939. /**
  1940. * dp_tx_reinject_handler() - Tx Reinject Handler
  1941. * @tx_desc: software descriptor head pointer
  1942. * @status : Tx completion status from HTT descriptor
  1943. *
  1944. * This function reinjects frames back to Target.
  1945. * Todo - Host queue needs to be added
  1946. *
  1947. * Return: none
  1948. */
  1949. static
  1950. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1951. {
  1952. struct dp_vdev *vdev;
  1953. struct dp_peer *peer = NULL;
  1954. uint32_t peer_id = HTT_INVALID_PEER;
  1955. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1956. qdf_nbuf_t nbuf_copy = NULL;
  1957. struct dp_tx_msdu_info_s msdu_info;
  1958. struct dp_peer *sa_peer = NULL;
  1959. struct dp_ast_entry *ast_entry = NULL;
  1960. struct dp_soc *soc = NULL;
  1961. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1962. #ifdef WDS_VENDOR_EXTENSION
  1963. int is_mcast = 0, is_ucast = 0;
  1964. int num_peers_3addr = 0;
  1965. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  1966. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1967. #endif
  1968. vdev = tx_desc->vdev;
  1969. soc = vdev->pdev->soc;
  1970. qdf_assert(vdev);
  1971. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1972. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1973. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1974. "%s Tx reinject path", __func__);
  1975. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1976. qdf_nbuf_len(tx_desc->nbuf));
  1977. qdf_spin_lock_bh(&(soc->ast_lock));
  1978. ast_entry = dp_peer_ast_hash_find_by_pdevid
  1979. (soc,
  1980. (uint8_t *)(eh->ether_shost),
  1981. vdev->pdev->pdev_id);
  1982. if (ast_entry)
  1983. sa_peer = ast_entry->peer;
  1984. qdf_spin_unlock_bh(&(soc->ast_lock));
  1985. #ifdef WDS_VENDOR_EXTENSION
  1986. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1987. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1988. } else {
  1989. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1990. }
  1991. is_ucast = !is_mcast;
  1992. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1993. if (peer->bss_peer)
  1994. continue;
  1995. /* Detect wds peers that use 3-addr framing for mcast.
  1996. * if there are any, the bss_peer is used to send the
  1997. * the mcast frame using 3-addr format. all wds enabled
  1998. * peers that use 4-addr framing for mcast frames will
  1999. * be duplicated and sent as 4-addr frames below.
  2000. */
  2001. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2002. num_peers_3addr = 1;
  2003. break;
  2004. }
  2005. }
  2006. #endif
  2007. if (qdf_unlikely(vdev->mesh_vdev)) {
  2008. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2009. } else {
  2010. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2011. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2012. #ifdef WDS_VENDOR_EXTENSION
  2013. /*
  2014. * . if 3-addr STA, then send on BSS Peer
  2015. * . if Peer WDS enabled and accept 4-addr mcast,
  2016. * send mcast on that peer only
  2017. * . if Peer WDS enabled and accept 4-addr ucast,
  2018. * send ucast on that peer only
  2019. */
  2020. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2021. (peer->wds_enabled &&
  2022. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2023. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2024. #else
  2025. ((peer->bss_peer &&
  2026. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2027. peer->nawds_enabled)) {
  2028. #endif
  2029. peer_id = DP_INVALID_PEER;
  2030. if (peer->nawds_enabled) {
  2031. peer_id = peer->peer_ids[0];
  2032. if (sa_peer == peer) {
  2033. QDF_TRACE(
  2034. QDF_MODULE_ID_DP,
  2035. QDF_TRACE_LEVEL_DEBUG,
  2036. " %s: multicast packet",
  2037. __func__);
  2038. DP_STATS_INC(peer,
  2039. tx.nawds_mcast_drop, 1);
  2040. continue;
  2041. }
  2042. }
  2043. nbuf_copy = qdf_nbuf_copy(nbuf);
  2044. if (!nbuf_copy) {
  2045. QDF_TRACE(QDF_MODULE_ID_DP,
  2046. QDF_TRACE_LEVEL_DEBUG,
  2047. FL("nbuf copy failed"));
  2048. break;
  2049. }
  2050. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2051. nbuf_copy,
  2052. &msdu_info,
  2053. peer_id,
  2054. NULL);
  2055. if (nbuf_copy) {
  2056. QDF_TRACE(QDF_MODULE_ID_DP,
  2057. QDF_TRACE_LEVEL_DEBUG,
  2058. FL("pkt send failed"));
  2059. qdf_nbuf_free(nbuf_copy);
  2060. } else {
  2061. if (peer_id != DP_INVALID_PEER)
  2062. DP_STATS_INC_PKT(peer,
  2063. tx.nawds_mcast,
  2064. 1, qdf_nbuf_len(nbuf));
  2065. }
  2066. }
  2067. }
  2068. }
  2069. if (vdev->nawds_enabled) {
  2070. peer_id = DP_INVALID_PEER;
  2071. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2072. 1, qdf_nbuf_len(nbuf));
  2073. nbuf = dp_tx_send_msdu_single(vdev,
  2074. nbuf,
  2075. &msdu_info,
  2076. peer_id, NULL);
  2077. if (nbuf) {
  2078. QDF_TRACE(QDF_MODULE_ID_DP,
  2079. QDF_TRACE_LEVEL_DEBUG,
  2080. FL("pkt send failed"));
  2081. qdf_nbuf_free(nbuf);
  2082. }
  2083. } else
  2084. qdf_nbuf_free(nbuf);
  2085. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2086. }
  2087. /**
  2088. * dp_tx_inspect_handler() - Tx Inspect Handler
  2089. * @tx_desc: software descriptor head pointer
  2090. * @status : Tx completion status from HTT descriptor
  2091. *
  2092. * Handles Tx frames sent back to Host for inspection
  2093. * (ProxyARP)
  2094. *
  2095. * Return: none
  2096. */
  2097. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2098. {
  2099. struct dp_soc *soc;
  2100. struct dp_pdev *pdev = tx_desc->pdev;
  2101. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2102. "%s Tx inspect path",
  2103. __func__);
  2104. qdf_assert(pdev);
  2105. soc = pdev->soc;
  2106. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2107. qdf_nbuf_len(tx_desc->nbuf));
  2108. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2109. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2110. }
  2111. #ifdef FEATURE_PERPKT_INFO
  2112. /**
  2113. * dp_get_completion_indication_for_stack() - send completion to stack
  2114. * @soc : dp_soc handle
  2115. * @pdev: dp_pdev handle
  2116. * @peer: dp peer handle
  2117. * @ts: transmit completion status structure
  2118. * @netbuf: Buffer pointer for free
  2119. *
  2120. * This function is used for indication whether buffer needs to be
  2121. * sent to stack for freeing or not
  2122. */
  2123. QDF_STATUS
  2124. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2125. struct dp_pdev *pdev,
  2126. struct dp_peer *peer,
  2127. struct hal_tx_completion_status *ts,
  2128. qdf_nbuf_t netbuf,
  2129. uint64_t time_latency)
  2130. {
  2131. struct tx_capture_hdr *ppdu_hdr;
  2132. uint16_t peer_id = ts->peer_id;
  2133. uint32_t ppdu_id = ts->ppdu_id;
  2134. uint8_t first_msdu = ts->first_msdu;
  2135. uint8_t last_msdu = ts->last_msdu;
  2136. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2137. !pdev->latency_capture_enable))
  2138. return QDF_STATUS_E_NOSUPPORT;
  2139. if (!peer) {
  2140. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2141. FL("Peer Invalid"));
  2142. return QDF_STATUS_E_INVAL;
  2143. }
  2144. if (pdev->mcopy_mode) {
  2145. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2146. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2147. return QDF_STATUS_E_INVAL;
  2148. }
  2149. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2150. pdev->m_copy_id.tx_peer_id = peer_id;
  2151. }
  2152. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2153. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2154. FL("No headroom"));
  2155. return QDF_STATUS_E_NOMEM;
  2156. }
  2157. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2158. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2159. QDF_MAC_ADDR_SIZE);
  2160. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2161. QDF_MAC_ADDR_SIZE);
  2162. ppdu_hdr->ppdu_id = ppdu_id;
  2163. ppdu_hdr->peer_id = peer_id;
  2164. ppdu_hdr->first_msdu = first_msdu;
  2165. ppdu_hdr->last_msdu = last_msdu;
  2166. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2167. ppdu_hdr->tsf = ts->tsf;
  2168. ppdu_hdr->time_latency = time_latency;
  2169. }
  2170. return QDF_STATUS_SUCCESS;
  2171. }
  2172. /**
  2173. * dp_send_completion_to_stack() - send completion to stack
  2174. * @soc : dp_soc handle
  2175. * @pdev: dp_pdev handle
  2176. * @peer_id: peer_id of the peer for which completion came
  2177. * @ppdu_id: ppdu_id
  2178. * @netbuf: Buffer pointer for free
  2179. *
  2180. * This function is used to send completion to stack
  2181. * to free buffer
  2182. */
  2183. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2184. uint16_t peer_id, uint32_t ppdu_id,
  2185. qdf_nbuf_t netbuf)
  2186. {
  2187. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2188. netbuf, peer_id,
  2189. WDI_NO_VAL, pdev->pdev_id);
  2190. }
  2191. #else
  2192. static QDF_STATUS
  2193. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2194. struct dp_pdev *pdev,
  2195. struct dp_peer *peer,
  2196. struct hal_tx_completion_status *ts,
  2197. qdf_nbuf_t netbuf,
  2198. uint64_t time_latency)
  2199. {
  2200. return QDF_STATUS_E_NOSUPPORT;
  2201. }
  2202. static void
  2203. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2204. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2205. {
  2206. }
  2207. #endif
  2208. /**
  2209. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2210. * @soc: Soc handle
  2211. * @desc: software Tx descriptor to be processed
  2212. *
  2213. * Return: none
  2214. */
  2215. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2216. {
  2217. struct dp_vdev *vdev = desc->vdev;
  2218. qdf_nbuf_t nbuf = desc->nbuf;
  2219. /* nbuf already freed in vdev detach path */
  2220. if (!nbuf)
  2221. return;
  2222. /* If it is TDLS mgmt, don't unmap or free the frame */
  2223. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2224. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2225. /* 0 : MSDU buffer, 1 : MLE */
  2226. if (desc->msdu_ext_desc) {
  2227. /* TSO free */
  2228. if (hal_tx_ext_desc_get_tso_enable(
  2229. desc->msdu_ext_desc->vaddr)) {
  2230. /* unmap eash TSO seg before free the nbuf */
  2231. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2232. desc->tso_num_desc);
  2233. qdf_nbuf_free(nbuf);
  2234. return;
  2235. }
  2236. }
  2237. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2238. if (qdf_likely(!vdev->mesh_vdev))
  2239. qdf_nbuf_free(nbuf);
  2240. else {
  2241. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2242. qdf_nbuf_free(nbuf);
  2243. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2244. } else
  2245. vdev->osif_tx_free_ext((nbuf));
  2246. }
  2247. }
  2248. /**
  2249. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2250. * @vdev: pointer to dp dev handler
  2251. * @status : Tx completion status from HTT descriptor
  2252. *
  2253. * Handles MEC notify event sent from fw to Host
  2254. *
  2255. * Return: none
  2256. */
  2257. #ifdef FEATURE_WDS
  2258. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2259. {
  2260. struct dp_soc *soc;
  2261. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2262. struct dp_peer *peer;
  2263. uint8_t mac_addr[QDF_MAC_ADDR_SIZE], i;
  2264. if (!vdev->mec_enabled)
  2265. return;
  2266. /* MEC required only in STA mode */
  2267. if (vdev->opmode != wlan_op_mode_sta)
  2268. return;
  2269. soc = vdev->pdev->soc;
  2270. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2271. peer = TAILQ_FIRST(&vdev->peer_list);
  2272. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2273. if (!peer) {
  2274. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2275. FL("peer is NULL"));
  2276. return;
  2277. }
  2278. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2279. "%s Tx MEC Handler",
  2280. __func__);
  2281. for (i = 0; i < QDF_MAC_ADDR_SIZE; i++)
  2282. mac_addr[(QDF_MAC_ADDR_SIZE - 1) - i] =
  2283. status[(QDF_MAC_ADDR_SIZE - 2) + i];
  2284. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  2285. dp_peer_add_ast(soc,
  2286. peer,
  2287. mac_addr,
  2288. CDP_TXRX_AST_TYPE_MEC,
  2289. flags);
  2290. }
  2291. #endif
  2292. #ifdef MESH_MODE_SUPPORT
  2293. /**
  2294. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2295. * in mesh meta header
  2296. * @tx_desc: software descriptor head pointer
  2297. * @ts: pointer to tx completion stats
  2298. * Return: none
  2299. */
  2300. static
  2301. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2302. struct hal_tx_completion_status *ts)
  2303. {
  2304. struct meta_hdr_s *mhdr;
  2305. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2306. if (!tx_desc->msdu_ext_desc) {
  2307. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2308. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2309. "netbuf %pK offset %d",
  2310. netbuf, tx_desc->pkt_offset);
  2311. return;
  2312. }
  2313. }
  2314. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2315. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2316. "netbuf %pK offset %lu", netbuf,
  2317. sizeof(struct meta_hdr_s));
  2318. return;
  2319. }
  2320. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2321. mhdr->rssi = ts->ack_frame_rssi;
  2322. mhdr->channel = tx_desc->pdev->operating_channel;
  2323. }
  2324. #else
  2325. static
  2326. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2327. struct hal_tx_completion_status *ts)
  2328. {
  2329. }
  2330. #endif
  2331. /**
  2332. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2333. * to pass in correct fields
  2334. *
  2335. * @vdev: pdev handle
  2336. * @tx_desc: tx descriptor
  2337. * @tid: tid value
  2338. * Return: none
  2339. */
  2340. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2341. struct dp_tx_desc_s *tx_desc, uint8_t tid)
  2342. {
  2343. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2344. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2345. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2346. return;
  2347. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2348. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2349. timestamp_hw_enqueue = tx_desc->timestamp;
  2350. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2351. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2352. timestamp_hw_enqueue);
  2353. interframe_delay = (uint32_t)(timestamp_ingress -
  2354. vdev->prev_tx_enq_tstamp);
  2355. /*
  2356. * Delay in software enqueue
  2357. */
  2358. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2359. CDP_DELAY_STATS_SW_ENQ);
  2360. /*
  2361. * Delay between packet enqueued to HW and Tx completion
  2362. */
  2363. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2364. CDP_DELAY_STATS_FW_HW_TRANSMIT);
  2365. /*
  2366. * Update interframe delay stats calculated at hardstart receive point.
  2367. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2368. * interframe delay will not be calculate correctly for 1st frame.
  2369. * On the other side, this will help in avoiding extra per packet check
  2370. * of !vdev->prev_tx_enq_tstamp.
  2371. */
  2372. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2373. CDP_DELAY_STATS_TX_INTERFRAME);
  2374. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2375. }
  2376. /**
  2377. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2378. * @tx_desc: software descriptor head pointer
  2379. * @ts: Tx completion status
  2380. * @peer: peer handle
  2381. *
  2382. * Return: None
  2383. */
  2384. static inline void
  2385. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2386. struct hal_tx_completion_status *ts,
  2387. struct dp_peer *peer)
  2388. {
  2389. struct dp_pdev *pdev = peer->vdev->pdev;
  2390. struct dp_soc *soc = NULL;
  2391. uint8_t mcs, pkt_type;
  2392. uint8_t tid = ts->tid;
  2393. uint32_t length;
  2394. struct cdp_tid_tx_stats *tid_stats;
  2395. if (!pdev)
  2396. return;
  2397. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2398. tid = CDP_MAX_DATA_TIDS - 1;
  2399. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2400. soc = pdev->soc;
  2401. mcs = ts->mcs;
  2402. pkt_type = ts->pkt_type;
  2403. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2404. dp_err("Release source is not from TQM");
  2405. return;
  2406. }
  2407. length = qdf_nbuf_len(tx_desc->nbuf);
  2408. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2409. if (qdf_unlikely(pdev->delay_stats_flag))
  2410. dp_tx_compute_delay(peer->vdev, tx_desc, tid);
  2411. tid_stats->complete_cnt++;
  2412. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2413. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2414. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2415. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2416. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2417. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2418. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2419. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2420. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2421. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2422. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2423. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2424. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2425. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2426. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2427. tid_stats->comp_fail_cnt++;
  2428. return;
  2429. }
  2430. tid_stats->success_cnt++;
  2431. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2432. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2433. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2434. /*
  2435. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2436. * Return from here if HTT PPDU events are enabled.
  2437. */
  2438. if (!(soc->process_tx_status))
  2439. return;
  2440. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2441. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2442. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2443. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2444. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2445. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2446. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2447. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2448. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2449. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2450. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2451. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2452. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2453. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2454. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2455. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2456. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2457. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2458. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2459. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2460. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2461. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2462. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2463. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2464. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2465. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2466. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2467. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2468. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2469. &peer->stats, ts->peer_id,
  2470. UPDATE_PEER_STATS, pdev->pdev_id);
  2471. #endif
  2472. }
  2473. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2474. /**
  2475. * dp_tx_flow_pool_lock() - take flow pool lock
  2476. * @soc: core txrx main context
  2477. * @tx_desc: tx desc
  2478. *
  2479. * Return: None
  2480. */
  2481. static inline
  2482. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2483. struct dp_tx_desc_s *tx_desc)
  2484. {
  2485. struct dp_tx_desc_pool_s *pool;
  2486. uint8_t desc_pool_id;
  2487. desc_pool_id = tx_desc->pool_id;
  2488. pool = &soc->tx_desc[desc_pool_id];
  2489. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2490. }
  2491. /**
  2492. * dp_tx_flow_pool_unlock() - release flow pool lock
  2493. * @soc: core txrx main context
  2494. * @tx_desc: tx desc
  2495. *
  2496. * Return: None
  2497. */
  2498. static inline
  2499. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2500. struct dp_tx_desc_s *tx_desc)
  2501. {
  2502. struct dp_tx_desc_pool_s *pool;
  2503. uint8_t desc_pool_id;
  2504. desc_pool_id = tx_desc->pool_id;
  2505. pool = &soc->tx_desc[desc_pool_id];
  2506. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2507. }
  2508. #else
  2509. static inline
  2510. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2511. {
  2512. }
  2513. static inline
  2514. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2515. {
  2516. }
  2517. #endif
  2518. /**
  2519. * dp_tx_notify_completion() - Notify tx completion for this desc
  2520. * @soc: core txrx main context
  2521. * @tx_desc: tx desc
  2522. * @netbuf: buffer
  2523. *
  2524. * Return: none
  2525. */
  2526. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2527. struct dp_tx_desc_s *tx_desc,
  2528. qdf_nbuf_t netbuf)
  2529. {
  2530. void *osif_dev;
  2531. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2532. qdf_assert(tx_desc);
  2533. dp_tx_flow_pool_lock(soc, tx_desc);
  2534. if (!tx_desc->vdev ||
  2535. !tx_desc->vdev->osif_vdev) {
  2536. dp_tx_flow_pool_unlock(soc, tx_desc);
  2537. return;
  2538. }
  2539. osif_dev = tx_desc->vdev->osif_vdev;
  2540. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2541. dp_tx_flow_pool_unlock(soc, tx_desc);
  2542. if (tx_compl_cbk)
  2543. tx_compl_cbk(netbuf, osif_dev);
  2544. }
  2545. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2546. * @pdev: pdev handle
  2547. * @tid: tid value
  2548. * @txdesc_ts: timestamp from txdesc
  2549. * @ppdu_id: ppdu id
  2550. *
  2551. * Return: none
  2552. */
  2553. #ifdef FEATURE_PERPKT_INFO
  2554. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2555. struct dp_peer *peer,
  2556. uint8_t tid,
  2557. uint64_t txdesc_ts,
  2558. uint32_t ppdu_id)
  2559. {
  2560. uint64_t delta_ms;
  2561. struct cdp_tx_sojourn_stats *sojourn_stats;
  2562. uint8_t tidno;
  2563. if (pdev->enhanced_stats_en == 0)
  2564. return;
  2565. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2566. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2567. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2568. if (!pdev->sojourn_buf)
  2569. return;
  2570. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2571. qdf_nbuf_data(pdev->sojourn_buf);
  2572. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2573. sizeof(struct cdp_tx_sojourn_stats));
  2574. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2575. for (tidno = 0; tidno < CDP_DATA_TID_MAX; tidno++) {
  2576. pdev->sojourn_stats.sum_sojourn_msdu[tidno] = 0;
  2577. pdev->sojourn_stats.num_msdus[tidno] = 0;
  2578. }
  2579. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2580. pdev->sojourn_buf, HTT_INVALID_PEER,
  2581. WDI_NO_VAL, pdev->pdev_id);
  2582. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2583. }
  2584. if (tid == HTT_INVALID_TID)
  2585. return;
  2586. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2587. txdesc_ts;
  2588. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2589. delta_ms);
  2590. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2591. pdev->sojourn_stats.num_msdus[tid]++;
  2592. }
  2593. #else
  2594. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2595. uint8_t tid,
  2596. uint64_t txdesc_ts,
  2597. uint32_t ppdu_id)
  2598. {
  2599. }
  2600. #endif
  2601. /**
  2602. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2603. * @soc: DP Soc handle
  2604. * @tx_desc: software Tx descriptor
  2605. * @ts : Tx completion status from HAL/HTT descriptor
  2606. *
  2607. * Return: none
  2608. */
  2609. static inline void
  2610. dp_tx_comp_process_desc(struct dp_soc *soc,
  2611. struct dp_tx_desc_s *desc,
  2612. struct hal_tx_completion_status *ts,
  2613. struct dp_peer *peer)
  2614. {
  2615. uint64_t time_latency = 0;
  2616. /*
  2617. * m_copy/tx_capture modes are not supported for
  2618. * scatter gather packets
  2619. */
  2620. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2621. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2622. desc->timestamp);
  2623. }
  2624. if (!(desc->msdu_ext_desc) &&
  2625. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2626. peer, ts, desc->nbuf,
  2627. time_latency)
  2628. == QDF_STATUS_SUCCESS)) {
  2629. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2630. QDF_DMA_TO_DEVICE);
  2631. dp_send_completion_to_stack(soc, desc->pdev, ts->peer_id,
  2632. ts->ppdu_id, desc->nbuf);
  2633. } else {
  2634. dp_tx_comp_free_buf(soc, desc);
  2635. }
  2636. }
  2637. /**
  2638. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2639. * @tx_desc: software descriptor head pointer
  2640. * @ts: Tx completion status
  2641. * @peer: peer handle
  2642. *
  2643. * Return: none
  2644. */
  2645. static inline
  2646. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2647. struct hal_tx_completion_status *ts,
  2648. struct dp_peer *peer)
  2649. {
  2650. uint32_t length;
  2651. qdf_ether_header_t *eh;
  2652. struct dp_soc *soc = NULL;
  2653. struct dp_vdev *vdev = tx_desc->vdev;
  2654. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2655. if (!vdev || !nbuf) {
  2656. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2657. "invalid tx descriptor. vdev or nbuf NULL");
  2658. goto out;
  2659. }
  2660. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2661. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2662. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2663. QDF_TRACE_DEFAULT_PDEV_ID,
  2664. qdf_nbuf_data_addr(nbuf),
  2665. sizeof(qdf_nbuf_data(nbuf)),
  2666. tx_desc->id,
  2667. ts->status));
  2668. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2669. "-------------------- \n"
  2670. "Tx Completion Stats: \n"
  2671. "-------------------- \n"
  2672. "ack_frame_rssi = %d \n"
  2673. "first_msdu = %d \n"
  2674. "last_msdu = %d \n"
  2675. "msdu_part_of_amsdu = %d \n"
  2676. "rate_stats valid = %d \n"
  2677. "bw = %d \n"
  2678. "pkt_type = %d \n"
  2679. "stbc = %d \n"
  2680. "ldpc = %d \n"
  2681. "sgi = %d \n"
  2682. "mcs = %d \n"
  2683. "ofdma = %d \n"
  2684. "tones_in_ru = %d \n"
  2685. "tsf = %d \n"
  2686. "ppdu_id = %d \n"
  2687. "transmit_cnt = %d \n"
  2688. "tid = %d \n"
  2689. "peer_id = %d\n",
  2690. ts->ack_frame_rssi, ts->first_msdu,
  2691. ts->last_msdu, ts->msdu_part_of_amsdu,
  2692. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2693. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2694. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2695. ts->transmit_cnt, ts->tid, ts->peer_id);
  2696. soc = vdev->pdev->soc;
  2697. /* Update SoC level stats */
  2698. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2699. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2700. /* Update per-packet stats for mesh mode */
  2701. if (qdf_unlikely(vdev->mesh_vdev) &&
  2702. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2703. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2704. length = qdf_nbuf_len(nbuf);
  2705. /* Update peer level stats */
  2706. if (!peer) {
  2707. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2708. "peer is null or deletion in progress");
  2709. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2710. goto out;
  2711. }
  2712. if (qdf_likely(!peer->bss_peer)) {
  2713. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2714. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2715. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2716. } else {
  2717. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2718. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2719. if ((peer->vdev->tx_encap_type ==
  2720. htt_cmn_pkt_type_ethernet) &&
  2721. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2722. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2723. }
  2724. }
  2725. }
  2726. dp_tx_update_peer_stats(tx_desc, ts, peer);
  2727. #ifdef QCA_SUPPORT_RDK_STATS
  2728. if (soc->wlanstats_enabled)
  2729. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2730. tx_desc->timestamp,
  2731. ts->ppdu_id);
  2732. #endif
  2733. out:
  2734. return;
  2735. }
  2736. /**
  2737. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2738. * @soc: core txrx main context
  2739. * @comp_head: software descriptor head pointer
  2740. *
  2741. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2742. * and release the software descriptors after processing is complete
  2743. *
  2744. * Return: none
  2745. */
  2746. static void
  2747. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2748. struct dp_tx_desc_s *comp_head)
  2749. {
  2750. struct dp_tx_desc_s *desc;
  2751. struct dp_tx_desc_s *next;
  2752. struct hal_tx_completion_status ts = {0};
  2753. struct dp_peer *peer;
  2754. qdf_nbuf_t netbuf;
  2755. DP_HIST_INIT();
  2756. desc = comp_head;
  2757. while (desc) {
  2758. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2759. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2760. dp_tx_comp_process_tx_status(desc, &ts, peer);
  2761. netbuf = desc->nbuf;
  2762. /* check tx complete notification */
  2763. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2764. dp_tx_notify_completion(soc, desc, netbuf);
  2765. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2766. if (peer)
  2767. dp_peer_unref_del_find_by_id(peer);
  2768. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2769. next = desc->next;
  2770. dp_tx_desc_release(desc, desc->pool_id);
  2771. desc = next;
  2772. }
  2773. DP_TX_HIST_STATS_PER_PDEV();
  2774. }
  2775. /**
  2776. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2777. * @tx_desc: software descriptor head pointer
  2778. * @status : Tx completion status from HTT descriptor
  2779. *
  2780. * This function will process HTT Tx indication messages from Target
  2781. *
  2782. * Return: none
  2783. */
  2784. static
  2785. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2786. {
  2787. uint8_t tx_status;
  2788. struct dp_pdev *pdev;
  2789. struct dp_vdev *vdev;
  2790. struct dp_soc *soc;
  2791. struct hal_tx_completion_status ts = {0};
  2792. uint32_t *htt_desc = (uint32_t *)status;
  2793. struct dp_peer *peer;
  2794. struct cdp_tid_tx_stats *tid_stats = NULL;
  2795. qdf_assert(tx_desc->pdev);
  2796. pdev = tx_desc->pdev;
  2797. vdev = tx_desc->vdev;
  2798. soc = pdev->soc;
  2799. if (!vdev)
  2800. return;
  2801. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2802. switch (tx_status) {
  2803. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2804. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2805. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2806. {
  2807. uint8_t tid;
  2808. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2809. ts.peer_id =
  2810. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2811. htt_desc[2]);
  2812. ts.tid =
  2813. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2814. htt_desc[2]);
  2815. } else {
  2816. ts.peer_id = HTT_INVALID_PEER;
  2817. ts.tid = HTT_INVALID_TID;
  2818. }
  2819. ts.ppdu_id =
  2820. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2821. htt_desc[1]);
  2822. ts.ack_frame_rssi =
  2823. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2824. htt_desc[1]);
  2825. ts.first_msdu = 1;
  2826. ts.last_msdu = 1;
  2827. tid = ts.tid;
  2828. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2829. tid = CDP_MAX_DATA_TIDS - 1;
  2830. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[tid];
  2831. if (qdf_unlikely(pdev->delay_stats_flag))
  2832. dp_tx_compute_delay(vdev, tx_desc, tid);
  2833. tid_stats->complete_cnt++;
  2834. if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
  2835. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  2836. tid_stats->comp_fail_cnt++;
  2837. } else {
  2838. tid_stats->success_cnt++;
  2839. }
  2840. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2841. if (qdf_likely(peer))
  2842. dp_peer_unref_del_find_by_id(peer);
  2843. dp_tx_comp_process_tx_status(tx_desc, &ts, peer);
  2844. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2845. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2846. break;
  2847. }
  2848. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2849. {
  2850. dp_tx_reinject_handler(tx_desc, status);
  2851. break;
  2852. }
  2853. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2854. {
  2855. dp_tx_inspect_handler(tx_desc, status);
  2856. break;
  2857. }
  2858. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2859. {
  2860. dp_tx_mec_handler(vdev, status);
  2861. break;
  2862. }
  2863. default:
  2864. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2865. "%s Invalid HTT tx_status %d\n",
  2866. __func__, tx_status);
  2867. break;
  2868. }
  2869. }
  2870. /**
  2871. * dp_tx_comp_handler() - Tx completion handler
  2872. * @soc: core txrx main context
  2873. * @ring_id: completion ring id
  2874. * @quota: No. of packets/descriptors that can be serviced in one loop
  2875. *
  2876. * This function will collect hardware release ring element contents and
  2877. * handle descriptor contents. Based on contents, free packet or handle error
  2878. * conditions
  2879. *
  2880. * Return: none
  2881. */
  2882. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2883. {
  2884. void *tx_comp_hal_desc;
  2885. uint8_t buffer_src;
  2886. uint8_t pool_id;
  2887. uint32_t tx_desc_id;
  2888. struct dp_tx_desc_s *tx_desc = NULL;
  2889. struct dp_tx_desc_s *head_desc = NULL;
  2890. struct dp_tx_desc_s *tail_desc = NULL;
  2891. uint32_t num_processed;
  2892. uint32_t count;
  2893. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2894. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2895. "%s %d : HAL RING Access Failed -- %pK",
  2896. __func__, __LINE__, hal_srng);
  2897. return 0;
  2898. }
  2899. num_processed = 0;
  2900. count = 0;
  2901. /* Find head descriptor from completion ring */
  2902. while (qdf_likely(tx_comp_hal_desc =
  2903. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2904. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2905. /* If this buffer was not released by TQM or FW, then it is not
  2906. * Tx completion indication, assert */
  2907. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2908. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2909. QDF_TRACE(QDF_MODULE_ID_DP,
  2910. QDF_TRACE_LEVEL_FATAL,
  2911. "Tx comp release_src != TQM | FW");
  2912. qdf_assert_always(0);
  2913. }
  2914. /* Get descriptor id */
  2915. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2916. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2917. DP_TX_DESC_ID_POOL_OS;
  2918. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2919. continue;
  2920. /* Find Tx descriptor */
  2921. tx_desc = dp_tx_desc_find(soc, pool_id,
  2922. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2923. DP_TX_DESC_ID_PAGE_OS,
  2924. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2925. DP_TX_DESC_ID_OFFSET_OS);
  2926. /*
  2927. * If the descriptor is already freed in vdev_detach,
  2928. * continue to next descriptor
  2929. */
  2930. if (!tx_desc->vdev) {
  2931. QDF_TRACE(QDF_MODULE_ID_DP,
  2932. QDF_TRACE_LEVEL_INFO,
  2933. "Descriptor freed in vdev_detach %d",
  2934. tx_desc_id);
  2935. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2936. count++;
  2937. continue;
  2938. }
  2939. /*
  2940. * If the release source is FW, process the HTT status
  2941. */
  2942. if (qdf_unlikely(buffer_src ==
  2943. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2944. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2945. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2946. htt_tx_status);
  2947. dp_tx_process_htt_completion(tx_desc,
  2948. htt_tx_status);
  2949. } else {
  2950. /* Pool id is not matching. Error */
  2951. if (tx_desc->pool_id != pool_id) {
  2952. QDF_TRACE(QDF_MODULE_ID_DP,
  2953. QDF_TRACE_LEVEL_FATAL,
  2954. "Tx Comp pool id %d not matched %d",
  2955. pool_id, tx_desc->pool_id);
  2956. qdf_assert_always(0);
  2957. }
  2958. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2959. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2960. QDF_TRACE(QDF_MODULE_ID_DP,
  2961. QDF_TRACE_LEVEL_FATAL,
  2962. "Txdesc invalid, flgs = %x,id = %d",
  2963. tx_desc->flags, tx_desc_id);
  2964. qdf_assert_always(0);
  2965. }
  2966. /* First ring descriptor on the cycle */
  2967. if (!head_desc) {
  2968. head_desc = tx_desc;
  2969. tail_desc = tx_desc;
  2970. }
  2971. tail_desc->next = tx_desc;
  2972. tx_desc->next = NULL;
  2973. tail_desc = tx_desc;
  2974. /* Collect hw completion contents */
  2975. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2976. &tx_desc->comp, 1);
  2977. }
  2978. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2979. /*
  2980. * Processed packet count is more than given quota
  2981. * stop to processing
  2982. */
  2983. if ((num_processed >= quota))
  2984. break;
  2985. count++;
  2986. }
  2987. hal_srng_access_end(soc->hal_soc, hal_srng);
  2988. /* Process the reaped descriptors */
  2989. if (head_desc)
  2990. dp_tx_comp_process_desc_list(soc, head_desc);
  2991. return num_processed;
  2992. }
  2993. #ifdef FEATURE_WLAN_TDLS
  2994. /**
  2995. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2996. *
  2997. * @data_vdev - which vdev should transmit the tx data frames
  2998. * @tx_spec - what non-standard handling to apply to the tx data frames
  2999. * @msdu_list - NULL-terminated list of tx MSDUs
  3000. *
  3001. * Return: NULL on success,
  3002. * nbuf when it fails to send
  3003. */
  3004. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  3005. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3006. {
  3007. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3008. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3009. vdev->is_tdls_frame = true;
  3010. return dp_tx_send(vdev_handle, msdu_list);
  3011. }
  3012. #endif
  3013. /**
  3014. * dp_tx_vdev_attach() - attach vdev to dp tx
  3015. * @vdev: virtual device instance
  3016. *
  3017. * Return: QDF_STATUS_SUCCESS: success
  3018. * QDF_STATUS_E_RESOURCES: Error return
  3019. */
  3020. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3021. {
  3022. /*
  3023. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3024. */
  3025. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3026. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3027. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3028. vdev->vdev_id);
  3029. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3030. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3031. /*
  3032. * Set HTT Extension Valid bit to 0 by default
  3033. */
  3034. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3035. dp_tx_vdev_update_search_flags(vdev);
  3036. return QDF_STATUS_SUCCESS;
  3037. }
  3038. #ifdef FEATURE_WDS
  3039. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3040. {
  3041. struct dp_soc *soc = vdev->pdev->soc;
  3042. /*
  3043. * If AST index override support is available (HKv2 etc),
  3044. * DA search flag be enabled always
  3045. *
  3046. * If AST index override support is not available (HKv1),
  3047. * DA search flag should be used for all modes except QWRAP
  3048. */
  3049. if (soc->ast_override_support || !vdev->proxysta_vdev)
  3050. return true;
  3051. return false;
  3052. }
  3053. #else
  3054. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3055. {
  3056. return false;
  3057. }
  3058. #endif
  3059. /**
  3060. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3061. * @vdev: virtual device instance
  3062. *
  3063. * Return: void
  3064. *
  3065. */
  3066. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3067. {
  3068. struct dp_soc *soc = vdev->pdev->soc;
  3069. /*
  3070. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3071. * for TDLS link
  3072. *
  3073. * Enable AddrY (SA based search) only for non-WDS STA and
  3074. * ProxySTA VAP (in HKv1) modes.
  3075. *
  3076. * In all other VAP modes, only DA based search should be
  3077. * enabled
  3078. */
  3079. if (vdev->opmode == wlan_op_mode_sta &&
  3080. vdev->tdls_link_connected)
  3081. vdev->hal_desc_addr_search_flags =
  3082. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3083. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3084. !dp_tx_da_search_override(vdev))
  3085. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3086. else
  3087. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3088. /* Set search type only when peer map v2 messaging is enabled
  3089. * as we will have the search index (AST hash) only when v2 is
  3090. * enabled
  3091. */
  3092. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3093. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3094. else
  3095. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3096. }
  3097. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3098. /* dp_tx_desc_flush() - release resources associated
  3099. * to tx_desc
  3100. * @vdev: virtual device instance
  3101. *
  3102. * This function will free all outstanding Tx buffers,
  3103. * including ME buffer for which either free during
  3104. * completion didn't happened or completion is not
  3105. * received.
  3106. */
  3107. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  3108. {
  3109. uint8_t i;
  3110. uint32_t j;
  3111. uint32_t num_desc, page_id, offset;
  3112. uint16_t num_desc_per_page;
  3113. struct dp_soc *soc = vdev->pdev->soc;
  3114. struct dp_tx_desc_s *tx_desc = NULL;
  3115. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3116. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3117. tx_desc_pool = &soc->tx_desc[i];
  3118. if (!(tx_desc_pool->pool_size) ||
  3119. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3120. !(tx_desc_pool->desc_pages.cacheable_pages))
  3121. continue;
  3122. num_desc = tx_desc_pool->pool_size;
  3123. num_desc_per_page =
  3124. tx_desc_pool->desc_pages.num_element_per_page;
  3125. for (j = 0; j < num_desc; j++) {
  3126. page_id = j / num_desc_per_page;
  3127. offset = j % num_desc_per_page;
  3128. if (qdf_unlikely(!(tx_desc_pool->
  3129. desc_pages.cacheable_pages)))
  3130. break;
  3131. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3132. if (tx_desc && (tx_desc->vdev == vdev) &&
  3133. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3134. dp_tx_comp_free_buf(soc, tx_desc);
  3135. dp_tx_desc_release(tx_desc, i);
  3136. }
  3137. }
  3138. }
  3139. }
  3140. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3141. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  3142. {
  3143. uint8_t i, num_pool;
  3144. uint32_t j;
  3145. uint32_t num_desc, page_id, offset;
  3146. uint16_t num_desc_per_page;
  3147. struct dp_soc *soc = vdev->pdev->soc;
  3148. struct dp_tx_desc_s *tx_desc = NULL;
  3149. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3150. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3151. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3152. for (i = 0; i < num_pool; i++) {
  3153. tx_desc_pool = &soc->tx_desc[i];
  3154. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3155. continue;
  3156. num_desc_per_page =
  3157. tx_desc_pool->desc_pages.num_element_per_page;
  3158. for (j = 0; j < num_desc; j++) {
  3159. page_id = j / num_desc_per_page;
  3160. offset = j % num_desc_per_page;
  3161. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3162. if (tx_desc && (tx_desc->vdev == vdev) &&
  3163. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  3164. dp_tx_comp_free_buf(soc, tx_desc);
  3165. dp_tx_desc_release(tx_desc, i);
  3166. }
  3167. }
  3168. }
  3169. }
  3170. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3171. /**
  3172. * dp_tx_vdev_detach() - detach vdev from dp tx
  3173. * @vdev: virtual device instance
  3174. *
  3175. * Return: QDF_STATUS_SUCCESS: success
  3176. * QDF_STATUS_E_RESOURCES: Error return
  3177. */
  3178. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3179. {
  3180. dp_tx_desc_flush(vdev);
  3181. return QDF_STATUS_SUCCESS;
  3182. }
  3183. /**
  3184. * dp_tx_pdev_attach() - attach pdev to dp tx
  3185. * @pdev: physical device instance
  3186. *
  3187. * Return: QDF_STATUS_SUCCESS: success
  3188. * QDF_STATUS_E_RESOURCES: Error return
  3189. */
  3190. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3191. {
  3192. struct dp_soc *soc = pdev->soc;
  3193. /* Initialize Flow control counters */
  3194. qdf_atomic_init(&pdev->num_tx_exception);
  3195. qdf_atomic_init(&pdev->num_tx_outstanding);
  3196. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3197. /* Initialize descriptors in TCL Ring */
  3198. hal_tx_init_data_ring(soc->hal_soc,
  3199. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3200. }
  3201. return QDF_STATUS_SUCCESS;
  3202. }
  3203. /**
  3204. * dp_tx_pdev_detach() - detach pdev from dp tx
  3205. * @pdev: physical device instance
  3206. *
  3207. * Return: QDF_STATUS_SUCCESS: success
  3208. * QDF_STATUS_E_RESOURCES: Error return
  3209. */
  3210. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3211. {
  3212. dp_tx_me_exit(pdev);
  3213. return QDF_STATUS_SUCCESS;
  3214. }
  3215. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3216. /* Pools will be allocated dynamically */
  3217. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3218. int num_desc)
  3219. {
  3220. uint8_t i;
  3221. for (i = 0; i < num_pool; i++) {
  3222. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3223. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3224. }
  3225. return 0;
  3226. }
  3227. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3228. {
  3229. uint8_t i;
  3230. for (i = 0; i < num_pool; i++)
  3231. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3232. }
  3233. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3234. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3235. int num_desc)
  3236. {
  3237. uint8_t i;
  3238. /* Allocate software Tx descriptor pools */
  3239. for (i = 0; i < num_pool; i++) {
  3240. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3241. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3242. "%s Tx Desc Pool alloc %d failed %pK",
  3243. __func__, i, soc);
  3244. return ENOMEM;
  3245. }
  3246. }
  3247. return 0;
  3248. }
  3249. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3250. {
  3251. uint8_t i;
  3252. for (i = 0; i < num_pool; i++) {
  3253. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3254. if (dp_tx_desc_pool_free(soc, i)) {
  3255. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3256. "%s Tx Desc Pool Free failed", __func__);
  3257. }
  3258. }
  3259. }
  3260. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3261. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3262. /**
  3263. * dp_tso_attach_wifi3() - TSO attach handler
  3264. * @txrx_soc: Opaque Dp handle
  3265. *
  3266. * Reserve TSO descriptor buffers
  3267. *
  3268. * Return: QDF_STATUS_E_FAILURE on failure or
  3269. * QDF_STATUS_SUCCESS on success
  3270. */
  3271. static
  3272. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3273. {
  3274. return dp_tso_soc_attach(txrx_soc);
  3275. }
  3276. /**
  3277. * dp_tso_detach_wifi3() - TSO Detach handler
  3278. * @txrx_soc: Opaque Dp handle
  3279. *
  3280. * Deallocate TSO descriptor buffers
  3281. *
  3282. * Return: QDF_STATUS_E_FAILURE on failure or
  3283. * QDF_STATUS_SUCCESS on success
  3284. */
  3285. static
  3286. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3287. {
  3288. return dp_tso_soc_detach(txrx_soc);
  3289. }
  3290. #else
  3291. static
  3292. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3293. {
  3294. return QDF_STATUS_SUCCESS;
  3295. }
  3296. static
  3297. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3298. {
  3299. return QDF_STATUS_SUCCESS;
  3300. }
  3301. #endif
  3302. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3303. {
  3304. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3305. uint8_t i;
  3306. uint8_t num_pool;
  3307. uint32_t num_desc;
  3308. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3309. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3310. for (i = 0; i < num_pool; i++)
  3311. dp_tx_tso_desc_pool_free(soc, i);
  3312. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3313. __func__, num_pool, num_desc);
  3314. for (i = 0; i < num_pool; i++)
  3315. dp_tx_tso_num_seg_pool_free(soc, i);
  3316. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3317. __func__, num_pool, num_desc);
  3318. return QDF_STATUS_SUCCESS;
  3319. }
  3320. /**
  3321. * dp_tso_attach() - TSO attach handler
  3322. * @txrx_soc: Opaque Dp handle
  3323. *
  3324. * Reserve TSO descriptor buffers
  3325. *
  3326. * Return: QDF_STATUS_E_FAILURE on failure or
  3327. * QDF_STATUS_SUCCESS on success
  3328. */
  3329. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3330. {
  3331. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3332. uint8_t i;
  3333. uint8_t num_pool;
  3334. uint32_t num_desc;
  3335. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3336. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3337. for (i = 0; i < num_pool; i++) {
  3338. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3339. dp_err("TSO Desc Pool alloc %d failed %pK",
  3340. i, soc);
  3341. return QDF_STATUS_E_FAILURE;
  3342. }
  3343. }
  3344. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3345. __func__, num_pool, num_desc);
  3346. for (i = 0; i < num_pool; i++) {
  3347. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3348. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3349. i, soc);
  3350. return QDF_STATUS_E_FAILURE;
  3351. }
  3352. }
  3353. return QDF_STATUS_SUCCESS;
  3354. }
  3355. /**
  3356. * dp_tx_soc_detach() - detach soc from dp tx
  3357. * @soc: core txrx main context
  3358. *
  3359. * This function will detach dp tx into main device context
  3360. * will free dp tx resource and initialize resources
  3361. *
  3362. * Return: QDF_STATUS_SUCCESS: success
  3363. * QDF_STATUS_E_RESOURCES: Error return
  3364. */
  3365. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3366. {
  3367. uint8_t num_pool;
  3368. uint16_t num_desc;
  3369. uint16_t num_ext_desc;
  3370. uint8_t i;
  3371. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3372. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3373. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3374. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3375. dp_tx_flow_control_deinit(soc);
  3376. dp_tx_delete_static_pools(soc, num_pool);
  3377. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3378. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3379. __func__, num_pool, num_desc);
  3380. for (i = 0; i < num_pool; i++) {
  3381. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3382. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3383. "%s Tx Ext Desc Pool Free failed",
  3384. __func__);
  3385. return QDF_STATUS_E_RESOURCES;
  3386. }
  3387. }
  3388. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3389. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3390. __func__, num_pool, num_ext_desc);
  3391. status = dp_tso_detach_wifi3(soc);
  3392. if (status != QDF_STATUS_SUCCESS)
  3393. return status;
  3394. return QDF_STATUS_SUCCESS;
  3395. }
  3396. /**
  3397. * dp_tx_soc_attach() - attach soc to dp tx
  3398. * @soc: core txrx main context
  3399. *
  3400. * This function will attach dp tx into main device context
  3401. * will allocate dp tx resource and initialize resources
  3402. *
  3403. * Return: QDF_STATUS_SUCCESS: success
  3404. * QDF_STATUS_E_RESOURCES: Error return
  3405. */
  3406. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3407. {
  3408. uint8_t i;
  3409. uint8_t num_pool;
  3410. uint32_t num_desc;
  3411. uint32_t num_ext_desc;
  3412. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3413. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3414. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3415. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3416. if (num_pool > MAX_TXDESC_POOLS)
  3417. goto fail;
  3418. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3419. goto fail;
  3420. dp_tx_flow_control_init(soc);
  3421. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3422. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3423. __func__, num_pool, num_desc);
  3424. /* Allocate extension tx descriptor pools */
  3425. for (i = 0; i < num_pool; i++) {
  3426. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3427. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3428. "MSDU Ext Desc Pool alloc %d failed %pK",
  3429. i, soc);
  3430. goto fail;
  3431. }
  3432. }
  3433. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3434. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3435. __func__, num_pool, num_ext_desc);
  3436. status = dp_tso_attach_wifi3((void *)soc);
  3437. if (status != QDF_STATUS_SUCCESS)
  3438. goto fail;
  3439. /* Initialize descriptors in TCL Rings */
  3440. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3441. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3442. hal_tx_init_data_ring(soc->hal_soc,
  3443. soc->tcl_data_ring[i].hal_srng);
  3444. }
  3445. }
  3446. /*
  3447. * todo - Add a runtime config option to enable this.
  3448. */
  3449. /*
  3450. * Due to multiple issues on NPR EMU, enable it selectively
  3451. * only for NPR EMU, should be removed, once NPR platforms
  3452. * are stable.
  3453. */
  3454. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3455. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3456. "%s HAL Tx init Success", __func__);
  3457. return QDF_STATUS_SUCCESS;
  3458. fail:
  3459. /* Detach will take care of freeing only allocated resources */
  3460. dp_tx_soc_detach(soc);
  3461. return QDF_STATUS_E_RESOURCES;
  3462. }
  3463. /*
  3464. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3465. * pdev: pointer to DP PDEV structure
  3466. * seg_info_head: Pointer to the head of list
  3467. *
  3468. * return: void
  3469. */
  3470. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3471. struct dp_tx_seg_info_s *seg_info_head)
  3472. {
  3473. struct dp_tx_me_buf_t *mc_uc_buf;
  3474. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3475. qdf_nbuf_t nbuf = NULL;
  3476. uint64_t phy_addr;
  3477. while (seg_info_head) {
  3478. nbuf = seg_info_head->nbuf;
  3479. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3480. seg_info_head->frags[0].vaddr;
  3481. phy_addr = seg_info_head->frags[0].paddr_hi;
  3482. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3483. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3484. phy_addr,
  3485. QDF_DMA_TO_DEVICE , QDF_MAC_ADDR_SIZE);
  3486. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3487. qdf_nbuf_free(nbuf);
  3488. seg_info_new = seg_info_head;
  3489. seg_info_head = seg_info_head->next;
  3490. qdf_mem_free(seg_info_new);
  3491. }
  3492. }
  3493. /**
  3494. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3495. * @vdev: DP VDEV handle
  3496. * @nbuf: Multicast nbuf
  3497. * @newmac: Table of the clients to which packets have to be sent
  3498. * @new_mac_cnt: No of clients
  3499. *
  3500. * return: no of converted packets
  3501. */
  3502. uint16_t
  3503. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3504. uint8_t newmac[][QDF_MAC_ADDR_SIZE], uint8_t new_mac_cnt)
  3505. {
  3506. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3507. struct dp_pdev *pdev = vdev->pdev;
  3508. qdf_ether_header_t *eh;
  3509. uint8_t *data;
  3510. uint16_t len;
  3511. /* reference to frame dst addr */
  3512. uint8_t *dstmac;
  3513. /* copy of original frame src addr */
  3514. uint8_t srcmac[QDF_MAC_ADDR_SIZE];
  3515. /* local index into newmac */
  3516. uint8_t new_mac_idx = 0;
  3517. struct dp_tx_me_buf_t *mc_uc_buf;
  3518. qdf_nbuf_t nbuf_clone;
  3519. struct dp_tx_msdu_info_s msdu_info;
  3520. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3521. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3522. struct dp_tx_seg_info_s *seg_info_new;
  3523. qdf_dma_addr_t paddr_data;
  3524. qdf_dma_addr_t paddr_mcbuf = 0;
  3525. uint8_t empty_entry_mac[QDF_MAC_ADDR_SIZE] = {0};
  3526. QDF_STATUS status;
  3527. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3528. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3529. eh = (qdf_ether_header_t *)nbuf;
  3530. qdf_mem_copy(srcmac, eh->ether_shost, QDF_MAC_ADDR_SIZE);
  3531. len = qdf_nbuf_len(nbuf);
  3532. data = qdf_nbuf_data(nbuf);
  3533. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3534. QDF_DMA_TO_DEVICE);
  3535. if (status) {
  3536. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3537. "Mapping failure Error:%d", status);
  3538. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3539. qdf_nbuf_free(nbuf);
  3540. return 1;
  3541. }
  3542. paddr_data = qdf_nbuf_mapped_paddr_get(nbuf) + QDF_MAC_ADDR_SIZE;
  3543. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3544. dstmac = newmac[new_mac_idx];
  3545. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3546. "added mac addr (%pM)", dstmac);
  3547. /* Check for NULL Mac Address */
  3548. if (!qdf_mem_cmp(dstmac, empty_entry_mac, QDF_MAC_ADDR_SIZE))
  3549. continue;
  3550. /* frame to self mac. skip */
  3551. if (!qdf_mem_cmp(dstmac, srcmac, QDF_MAC_ADDR_SIZE))
  3552. continue;
  3553. /*
  3554. * TODO: optimize to avoid malloc in per-packet path
  3555. * For eg. seg_pool can be made part of vdev structure
  3556. */
  3557. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3558. if (!seg_info_new) {
  3559. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3560. "alloc failed");
  3561. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3562. goto fail_seg_alloc;
  3563. }
  3564. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3565. if (!mc_uc_buf)
  3566. goto fail_buf_alloc;
  3567. /*
  3568. * TODO: Check if we need to clone the nbuf
  3569. * Or can we just use the reference for all cases
  3570. */
  3571. if (new_mac_idx < (new_mac_cnt - 1)) {
  3572. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3573. if (!nbuf_clone) {
  3574. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3575. goto fail_clone;
  3576. }
  3577. } else {
  3578. /*
  3579. * Update the ref
  3580. * to account for frame sent without cloning
  3581. */
  3582. qdf_nbuf_ref(nbuf);
  3583. nbuf_clone = nbuf;
  3584. }
  3585. qdf_mem_copy(mc_uc_buf->data, dstmac, QDF_MAC_ADDR_SIZE);
  3586. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3587. QDF_DMA_TO_DEVICE, QDF_MAC_ADDR_SIZE,
  3588. &paddr_mcbuf);
  3589. if (status) {
  3590. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3591. "Mapping failure Error:%d", status);
  3592. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3593. goto fail_map;
  3594. }
  3595. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3596. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3597. seg_info_new->frags[0].paddr_hi =
  3598. (uint16_t)((uint64_t)paddr_mcbuf >> 32);
  3599. seg_info_new->frags[0].len = QDF_MAC_ADDR_SIZE;
  3600. /*preparing data fragment*/
  3601. seg_info_new->frags[1].vaddr =
  3602. qdf_nbuf_data(nbuf) + QDF_MAC_ADDR_SIZE;
  3603. seg_info_new->frags[1].paddr_lo = (uint32_t)paddr_data;
  3604. seg_info_new->frags[1].paddr_hi =
  3605. (uint16_t)(((uint64_t)paddr_data) >> 32);
  3606. seg_info_new->frags[1].len = len - QDF_MAC_ADDR_SIZE;
  3607. seg_info_new->nbuf = nbuf_clone;
  3608. seg_info_new->frag_cnt = 2;
  3609. seg_info_new->total_len = len;
  3610. seg_info_new->next = NULL;
  3611. if (!seg_info_head)
  3612. seg_info_head = seg_info_new;
  3613. else
  3614. seg_info_tail->next = seg_info_new;
  3615. seg_info_tail = seg_info_new;
  3616. }
  3617. if (!seg_info_head) {
  3618. goto free_return;
  3619. }
  3620. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3621. msdu_info.num_seg = new_mac_cnt;
  3622. msdu_info.frm_type = dp_tx_frm_me;
  3623. if (qdf_unlikely(vdev->mcast_enhancement_en > 0) &&
  3624. qdf_unlikely(pdev->hmmc_tid_override_en))
  3625. msdu_info.tid = pdev->hmmc_tid;
  3626. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3627. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3628. while (seg_info_head->next) {
  3629. seg_info_new = seg_info_head;
  3630. seg_info_head = seg_info_head->next;
  3631. qdf_mem_free(seg_info_new);
  3632. }
  3633. qdf_mem_free(seg_info_head);
  3634. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3635. qdf_nbuf_free(nbuf);
  3636. return new_mac_cnt;
  3637. fail_map:
  3638. qdf_nbuf_free(nbuf_clone);
  3639. fail_clone:
  3640. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3641. fail_buf_alloc:
  3642. qdf_mem_free(seg_info_new);
  3643. fail_seg_alloc:
  3644. dp_tx_me_mem_free(pdev, seg_info_head);
  3645. free_return:
  3646. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3647. qdf_nbuf_free(nbuf);
  3648. return 1;
  3649. }