msm_rng.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2011-2013, 2015, 2017-2021 The Linux Foundation. All rights
  4. * reserved.
  5. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/hw_random.h>
  13. #include <linux/clk.h>
  14. #include <linux/slab.h>
  15. #include <linux/io.h>
  16. #include <linux/err.h>
  17. #include <linux/types.h>
  18. #include <linux/of.h>
  19. #include <linux/qrng.h>
  20. #include <linux/fs.h>
  21. #include <linux/cdev.h>
  22. #include <linux/delay.h>
  23. #include <linux/crypto.h>
  24. #include <crypto/internal/rng.h>
  25. #include <linux/interconnect.h>
  26. #include <linux/sched/signal.h>
  27. #include <linux/version.h>
  28. #define DRIVER_NAME "msm_rng"
  29. /* Device specific register offsets */
  30. #define PRNG_DATA_OUT_OFFSET 0x0000
  31. #define PRNG_STATUS_OFFSET 0x0004
  32. #define PRNG_LFSR_CFG_OFFSET 0x0100
  33. #define PRNG_CONFIG_OFFSET 0x0104
  34. /* Device specific register masks and config values */
  35. #define PRNG_LFSR_CFG_MASK 0xFFFF0000
  36. #define PRNG_LFSR_CFG_CLOCKS 0x0000DDDD
  37. #define PRNG_CONFIG_MASK 0xFFFFFFFD
  38. #define PRNG_HW_ENABLE 0x00000002
  39. #define MAX_HW_FIFO_DEPTH 16 /* FIFO is 16 words deep */
  40. #define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4) /* FIFO is 32 bits wide */
  41. #define RETRY_MAX_CNT 5 /* max retry times to read register */
  42. #define RETRY_DELAY_INTERVAL 440 /* retry delay interval in us */
  43. struct msm_rng_device {
  44. struct platform_device *pdev;
  45. void __iomem *base;
  46. struct clk *prng_clk;
  47. struct mutex rng_lock;
  48. struct icc_path *icc_path;
  49. };
  50. static struct msm_rng_device msm_rng_device_info;
  51. static struct msm_rng_device *msm_rng_dev_cached;
  52. static struct mutex cached_rng_lock;
  53. static long msm_rng_ioctl(struct file *filp, unsigned int cmd,
  54. unsigned long arg)
  55. {
  56. long ret = 0;
  57. switch (cmd) {
  58. case QRNG_IOCTL_RESET_BUS_BANDWIDTH:
  59. pr_debug("calling msm_rng_bus_scale(LOW)\n");
  60. ret = icc_set_bw(msm_rng_device_info.icc_path, 0, 0);
  61. if (ret)
  62. pr_err("failed qrng_reset_bus_bw, ret = %ld\n", ret);
  63. break;
  64. default:
  65. pr_err("Unsupported IOCTL call\n");
  66. break;
  67. }
  68. return ret;
  69. }
  70. /*
  71. *
  72. * This function calls hardware random bit generator directory and retuns it
  73. * back to caller
  74. *
  75. */
  76. static int msm_rng_direct_read(struct msm_rng_device *msm_rng_dev,
  77. void *data, size_t max)
  78. {
  79. struct platform_device *pdev;
  80. void __iomem *base;
  81. size_t currsize = 0;
  82. u32 val = 0;
  83. u32 *retdata = data;
  84. int ret;
  85. int failed = 0;
  86. pdev = msm_rng_dev->pdev;
  87. base = msm_rng_dev->base;
  88. /* no room for word data */
  89. if (max < 4)
  90. return 0;
  91. mutex_lock(&msm_rng_dev->rng_lock);
  92. if (msm_rng_dev->icc_path) {
  93. ret = icc_set_bw(msm_rng_dev->icc_path, 0, 300000);
  94. if (ret) {
  95. pr_err("bus_scale_client_update_req failed\n");
  96. goto bus_err;
  97. }
  98. }
  99. /* enable PRNG clock */
  100. if (msm_rng_dev->prng_clk) {
  101. ret = clk_prepare_enable(msm_rng_dev->prng_clk);
  102. if (ret) {
  103. pr_err("failed to enable prng clock\n");
  104. goto err;
  105. }
  106. }
  107. /* read random data from h/w */
  108. do {
  109. /* check status bit if data is available */
  110. if (!(readl_relaxed(base + PRNG_STATUS_OFFSET)
  111. & 0x00000001)) {
  112. if (failed++ == RETRY_MAX_CNT) {
  113. if (currsize == 0)
  114. pr_err("Data not available\n");
  115. break;
  116. }
  117. udelay(RETRY_DELAY_INTERVAL);
  118. } else {
  119. /* read FIFO */
  120. val = readl_relaxed(base + PRNG_DATA_OUT_OFFSET);
  121. /* write data back to callers pointer */
  122. *(retdata++) = val;
  123. currsize += 4;
  124. /* make sure we stay on 32bit boundary */
  125. if ((max - currsize) < 4)
  126. break;
  127. }
  128. } while (currsize < max);
  129. /* vote to turn off clock */
  130. if (msm_rng_dev->prng_clk)
  131. clk_disable_unprepare(msm_rng_dev->prng_clk);
  132. err:
  133. if (msm_rng_dev->icc_path) {
  134. ret = icc_set_bw(msm_rng_dev->icc_path, 0, 0);
  135. if (ret)
  136. pr_err("bus_scale_client_update_req failed\n");
  137. }
  138. bus_err:
  139. mutex_unlock(&msm_rng_dev->rng_lock);
  140. val = 0L;
  141. return currsize;
  142. }
  143. static int msm_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
  144. {
  145. struct msm_rng_device *msm_rng_dev;
  146. int rv = 0;
  147. msm_rng_dev = (struct msm_rng_device *)rng->priv;
  148. rv = msm_rng_direct_read(msm_rng_dev, data, max);
  149. return rv;
  150. }
  151. static struct hwrng msm_rng = {
  152. .name = DRIVER_NAME,
  153. .read = msm_rng_read,
  154. .quality = 1024,
  155. };
  156. static int msm_rng_enable_hw(struct msm_rng_device *msm_rng_dev)
  157. {
  158. unsigned long val = 0;
  159. unsigned long reg_val = 0;
  160. int ret = 0;
  161. if (msm_rng_dev->icc_path) {
  162. ret = icc_set_bw(msm_rng_dev->icc_path, 0, 30000);
  163. if (ret)
  164. pr_err("bus_scale_client_update_req failed\n");
  165. }
  166. /* Enable the PRNG CLK */
  167. if (msm_rng_dev->prng_clk) {
  168. ret = clk_prepare_enable(msm_rng_dev->prng_clk);
  169. if (ret) {
  170. dev_err(&(msm_rng_dev->pdev)->dev,
  171. "failed to enable clock in probe\n");
  172. return -EPERM;
  173. }
  174. }
  175. /* Enable PRNG h/w only if it is NOT ON */
  176. val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) &
  177. PRNG_HW_ENABLE;
  178. /* PRNG H/W is not ON */
  179. if (val != PRNG_HW_ENABLE) {
  180. val = readl_relaxed(msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
  181. val &= PRNG_LFSR_CFG_MASK;
  182. val |= PRNG_LFSR_CFG_CLOCKS;
  183. writel_relaxed(val, msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
  184. /* The PRNG CONFIG register should be first written */
  185. mb();
  186. reg_val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET)
  187. & PRNG_CONFIG_MASK;
  188. reg_val |= PRNG_HW_ENABLE;
  189. writel_relaxed(reg_val, msm_rng_dev->base + PRNG_CONFIG_OFFSET);
  190. /* The PRNG clk should be disabled only after we enable the
  191. * PRNG h/w by writing to the PRNG CONFIG register.
  192. */
  193. mb();
  194. }
  195. if (msm_rng_dev->prng_clk)
  196. clk_disable_unprepare(msm_rng_dev->prng_clk);
  197. if (msm_rng_dev->icc_path) {
  198. ret = icc_set_bw(msm_rng_dev->icc_path, 0, 0);
  199. if (ret)
  200. pr_err("bus_scale_client_update_req failed\n");
  201. }
  202. return 0;
  203. }
  204. static const struct file_operations msm_rng_fops = {
  205. .unlocked_ioctl = msm_rng_ioctl,
  206. };
  207. static struct class *msm_rng_class;
  208. static struct cdev msm_rng_cdev;
  209. static int msm_rng_probe(struct platform_device *pdev)
  210. {
  211. struct resource *res;
  212. struct msm_rng_device *msm_rng_dev = NULL;
  213. void __iomem *base = NULL;
  214. bool configure_qrng = true;
  215. int error = 0;
  216. struct device *dev;
  217. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  218. if (res == NULL) {
  219. dev_err(&pdev->dev, "invalid address\n");
  220. error = -EFAULT;
  221. goto err_exit;
  222. }
  223. msm_rng_dev = kzalloc(sizeof(struct msm_rng_device), GFP_KERNEL);
  224. if (!msm_rng_dev) {
  225. error = -ENOMEM;
  226. goto err_exit;
  227. }
  228. base = ioremap(res->start, resource_size(res));
  229. if (!base) {
  230. dev_err(&pdev->dev, "ioremap failed\n");
  231. error = -ENOMEM;
  232. goto err_iomap;
  233. }
  234. msm_rng_dev->base = base;
  235. /* create a handle for clock control */
  236. if (pdev->dev.of_node) {
  237. if (of_property_read_bool(pdev->dev.of_node,
  238. "qcom,no-clock-support"))
  239. msm_rng_dev->prng_clk = NULL;
  240. else
  241. msm_rng_dev->prng_clk = clk_get(&pdev->dev,
  242. "km_clk_src");
  243. }
  244. if (IS_ERR(msm_rng_dev->prng_clk)) {
  245. dev_err(&pdev->dev, "failed to register clock source\n");
  246. error = -ENODEV;
  247. goto err_clk_get;
  248. }
  249. /* save away pdev and register driver data */
  250. msm_rng_dev->pdev = pdev;
  251. platform_set_drvdata(pdev, msm_rng_dev);
  252. if (pdev->dev.of_node) {
  253. msm_rng_dev->icc_path = of_icc_get(&pdev->dev, "data_path");
  254. msm_rng_device_info.icc_path = msm_rng_dev->icc_path;
  255. if (IS_ERR(msm_rng_dev->icc_path)) {
  256. error = PTR_ERR(msm_rng_dev->icc_path);
  257. dev_err(&pdev->dev, "get icc path err %d\n", error);
  258. goto err_icc_get;
  259. }
  260. }
  261. /* Enable rng h/w for the targets which can access the entire
  262. * address space of PRNG.
  263. */
  264. if ((pdev->dev.of_node) && (of_property_read_bool(pdev->dev.of_node,
  265. "qcom,no-qrng-config")))
  266. configure_qrng = false;
  267. if (configure_qrng) {
  268. error = msm_rng_enable_hw(msm_rng_dev);
  269. if (error)
  270. goto err_icc_get;
  271. }
  272. mutex_init(&msm_rng_dev->rng_lock);
  273. mutex_init(&cached_rng_lock);
  274. /* register with hwrng framework */
  275. msm_rng.priv = (unsigned long) msm_rng_dev;
  276. error = hwrng_register(&msm_rng);
  277. if (error) {
  278. dev_err(&pdev->dev, "failed to register hwrng\n");
  279. goto err_reg_hwrng;
  280. }
  281. error = register_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME, &msm_rng_fops);
  282. if (error) {
  283. dev_err(&pdev->dev, "failed to register chrdev\n");
  284. goto err_reg_chrdev;
  285. }
  286. #if (KERNEL_VERSION(6, 3, 0) <= LINUX_VERSION_CODE)
  287. msm_rng_class = class_create("msm-rng");
  288. #else
  289. msm_rng_class = class_create(THIS_MODULE, "msm-rng");
  290. #endif
  291. if (IS_ERR(msm_rng_class)) {
  292. pr_err("class_create failed\n");
  293. error = PTR_ERR(msm_rng_class);
  294. goto err_create_cls;
  295. }
  296. dev = device_create(msm_rng_class, NULL, MKDEV(QRNG_IOC_MAGIC, 0),
  297. NULL, "msm-rng");
  298. if (IS_ERR(dev)) {
  299. pr_err("Device create failed\n");
  300. error = PTR_ERR(dev);
  301. goto err_create_dev;
  302. }
  303. cdev_init(&msm_rng_cdev, &msm_rng_fops);
  304. msm_rng_dev_cached = msm_rng_dev;
  305. return error;
  306. err_create_dev:
  307. class_destroy(msm_rng_class);
  308. err_create_cls:
  309. unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME);
  310. err_reg_chrdev:
  311. hwrng_unregister(&msm_rng);
  312. err_reg_hwrng:
  313. if (msm_rng_dev->icc_path)
  314. icc_put(msm_rng_dev->icc_path);
  315. err_icc_get:
  316. if (msm_rng_dev->prng_clk)
  317. clk_put(msm_rng_dev->prng_clk);
  318. err_clk_get:
  319. iounmap(msm_rng_dev->base);
  320. err_iomap:
  321. kfree_sensitive(msm_rng_dev);
  322. err_exit:
  323. return error;
  324. }
  325. static int msm_rng_remove(struct platform_device *pdev)
  326. {
  327. struct msm_rng_device *msm_rng_dev = platform_get_drvdata(pdev);
  328. cdev_del(&msm_rng_cdev);
  329. device_destroy(msm_rng_class, MKDEV(QRNG_IOC_MAGIC, 0));
  330. class_destroy(msm_rng_class);
  331. unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME);
  332. hwrng_unregister(&msm_rng);
  333. if (msm_rng_dev->prng_clk)
  334. clk_put(msm_rng_dev->prng_clk);
  335. iounmap(msm_rng_dev->base);
  336. platform_set_drvdata(pdev, NULL);
  337. if (msm_rng_dev->icc_path)
  338. icc_put(msm_rng_dev->icc_path);
  339. kfree_sensitive(msm_rng_dev);
  340. msm_rng_dev_cached = NULL;
  341. return 0;
  342. }
  343. static int qrng_get_random(struct crypto_rng *tfm, const u8 *src,
  344. unsigned int slen, u8 *rdata,
  345. unsigned int dlen)
  346. {
  347. int sizeread = 0;
  348. int rv = -EFAULT;
  349. if (!msm_rng_dev_cached) {
  350. pr_err("%s: msm_rng_dev is not initialized\n", __func__);
  351. rv = -ENODEV;
  352. goto err_exit;
  353. }
  354. if (!rdata) {
  355. pr_err("%s: data buffer is null\n", __func__);
  356. rv = -EINVAL;
  357. goto err_exit;
  358. }
  359. if (signal_pending(current) ||
  360. mutex_lock_interruptible(&cached_rng_lock)) {
  361. pr_err("%s: mutex lock interrupted\n", __func__);
  362. rv = -ERESTARTSYS;
  363. goto err_exit;
  364. }
  365. sizeread = msm_rng_direct_read(msm_rng_dev_cached, rdata, dlen);
  366. if (sizeread == dlen)
  367. rv = 0;
  368. mutex_unlock(&cached_rng_lock);
  369. err_exit:
  370. return rv;
  371. }
  372. static int qrng_reset(struct crypto_rng *tfm, const u8 *seed, unsigned int slen)
  373. {
  374. return 0;
  375. }
  376. static struct rng_alg rng_algs[] = { {
  377. .generate = qrng_get_random,
  378. .seed = qrng_reset,
  379. .seedsize = 0,
  380. .base = {
  381. .cra_name = "qrng",
  382. .cra_driver_name = "fips_hw_qrng",
  383. .cra_priority = 300,
  384. .cra_ctxsize = 0,
  385. .cra_module = THIS_MODULE,
  386. }
  387. } };
  388. static const struct of_device_id qrng_match[] = {
  389. {.compatible = "qcom,msm-rng"},
  390. {},
  391. };
  392. static struct platform_driver rng_driver = {
  393. .probe = msm_rng_probe,
  394. .remove = msm_rng_remove,
  395. .driver = {
  396. .name = DRIVER_NAME,
  397. .of_match_table = qrng_match,
  398. },
  399. };
  400. static int __init msm_rng_init(void)
  401. {
  402. int ret;
  403. msm_rng_dev_cached = NULL;
  404. ret = platform_driver_register(&rng_driver);
  405. if (ret) {
  406. pr_err("%s: platform_driver_register error:%d\n",
  407. __func__, ret);
  408. goto err_exit;
  409. }
  410. ret = crypto_register_rngs(rng_algs, ARRAY_SIZE(rng_algs));
  411. if (ret) {
  412. pr_err("%s: crypto_register_algs error:%d\n",
  413. __func__, ret);
  414. goto err_exit;
  415. }
  416. err_exit:
  417. return ret;
  418. }
  419. module_init(msm_rng_init);
  420. static void __exit msm_rng_exit(void)
  421. {
  422. crypto_unregister_rngs(rng_algs, ARRAY_SIZE(rng_algs));
  423. platform_driver_unregister(&rng_driver);
  424. }
  425. module_exit(msm_rng_exit);
  426. MODULE_DESCRIPTION("QTI MSM Random Number Driver");
  427. MODULE_LICENSE("GPL v2");