qmi.c 109 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  28. /*
  29. * Download QDSS config file based on build type. Add build type string to
  30. * file name. Download "qdss_trace_config_debug_v<n>.cfg" for debug build
  31. * and "qdss_trace_config_perf_v<n>.cfg" for perf build.
  32. */
  33. #ifdef CONFIG_CNSS2_DEBUG
  34. #define QDSS_FILE_BUILD_STR "debug_"
  35. #else
  36. #define QDSS_FILE_BUILD_STR "perf_"
  37. #endif
  38. #define HW_V1_NUMBER "v1"
  39. #define HW_V2_NUMBER "v2"
  40. #define CE_MSI_NAME "CE"
  41. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  42. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  43. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  44. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  45. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  46. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  47. #define DMS_QMI_MAX_MSG_LEN SZ_256
  48. #define MAX_SHADOW_REG_RESERVED 2
  49. #define MAX_NUM_SHADOW_REG_V3 (QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 - \
  50. MAX_SHADOW_REG_RESERVED)
  51. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  52. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  53. // these error values are not defined in <linux/soc/qcom/qmi.h> and fw is sending as error response
  54. #define QMI_ERR_HARDWARE_RESTRICTED_V01 0x0053
  55. #define QMI_ERR_ENOMEM_V01 0x0002
  56. enum nm_modem_bit {
  57. SLEEP_CLOCK_SELECT_INTERNAL_BIT = BIT(1),
  58. HOST_CSTATE_BIT = BIT(2),
  59. };
  60. #ifdef CONFIG_CNSS2_DEBUG
  61. static bool ignore_qmi_failure;
  62. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  63. void cnss_ignore_qmi_failure(bool ignore)
  64. {
  65. ignore_qmi_failure = ignore;
  66. }
  67. #else
  68. #define CNSS_QMI_ASSERT() do { } while (0)
  69. void cnss_ignore_qmi_failure(bool ignore) { }
  70. #endif
  71. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  72. {
  73. switch (mode) {
  74. case CNSS_MISSION:
  75. return "MISSION";
  76. case CNSS_FTM:
  77. return "FTM";
  78. case CNSS_EPPING:
  79. return "EPPING";
  80. case CNSS_WALTEST:
  81. return "WALTEST";
  82. case CNSS_OFF:
  83. return "OFF";
  84. case CNSS_CCPM:
  85. return "CCPM";
  86. case CNSS_QVIT:
  87. return "QVIT";
  88. case CNSS_CALIBRATION:
  89. return "CALIBRATION";
  90. default:
  91. return "UNKNOWN";
  92. }
  93. }
  94. static int qmi_send_wait(struct qmi_handle *qmi, void *req, void *rsp,
  95. struct qmi_elem_info *req_ei,
  96. struct qmi_elem_info *rsp_ei,
  97. int req_id, size_t req_len,
  98. unsigned long timeout)
  99. {
  100. struct qmi_txn txn;
  101. int ret;
  102. char *err_msg;
  103. struct qmi_response_type_v01 *resp = rsp;
  104. ret = qmi_txn_init(qmi, &txn, rsp_ei, rsp);
  105. if (ret < 0) {
  106. err_msg = "Qmi fail: fail to init txn,";
  107. goto out;
  108. }
  109. ret = qmi_send_request(qmi, NULL, &txn, req_id,
  110. req_len, req_ei, req);
  111. if (ret < 0) {
  112. qmi_txn_cancel(&txn);
  113. err_msg = "Qmi fail: fail to send req,";
  114. goto out;
  115. }
  116. ret = qmi_txn_wait(&txn, timeout);
  117. if (ret < 0) {
  118. err_msg = "Qmi fail: wait timeout,";
  119. goto out;
  120. } else if (resp->result != QMI_RESULT_SUCCESS_V01) {
  121. err_msg = "Qmi fail: request rejected,";
  122. cnss_pr_err("Qmi fail: respons with error:%d\n",
  123. resp->error);
  124. ret = -resp->result;
  125. goto out;
  126. }
  127. cnss_pr_dbg("req %x success\n", req_id);
  128. return 0;
  129. out:
  130. cnss_pr_err("%s req %x, ret %d\n", err_msg, req_id, ret);
  131. return ret;
  132. }
  133. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  134. {
  135. struct wlfw_ind_register_req_msg_v01 *req;
  136. struct wlfw_ind_register_resp_msg_v01 *resp;
  137. struct qmi_txn txn;
  138. int ret = 0;
  139. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  140. plat_priv->driver_state);
  141. req = kzalloc(sizeof(*req), GFP_KERNEL);
  142. if (!req)
  143. return -ENOMEM;
  144. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  145. if (!resp) {
  146. kfree(req);
  147. return -ENOMEM;
  148. }
  149. req->client_id_valid = 1;
  150. req->client_id = WLFW_CLIENT_ID;
  151. req->request_mem_enable_valid = 1;
  152. req->request_mem_enable = 1;
  153. req->fw_mem_ready_enable_valid = 1;
  154. req->fw_mem_ready_enable = 1;
  155. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  156. req->fw_init_done_enable_valid = 1;
  157. req->fw_init_done_enable = 1;
  158. req->pin_connect_result_enable_valid = 1;
  159. req->pin_connect_result_enable = 1;
  160. req->cal_done_enable_valid = 1;
  161. req->cal_done_enable = 1;
  162. req->qdss_trace_req_mem_enable_valid = 1;
  163. req->qdss_trace_req_mem_enable = 1;
  164. req->qdss_trace_save_enable_valid = 1;
  165. req->qdss_trace_save_enable = 1;
  166. req->qdss_trace_free_enable_valid = 1;
  167. req->qdss_trace_free_enable = 1;
  168. req->respond_get_info_enable_valid = 1;
  169. req->respond_get_info_enable = 1;
  170. req->wfc_call_twt_config_enable_valid = 1;
  171. req->wfc_call_twt_config_enable = 1;
  172. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  173. wlfw_ind_register_resp_msg_v01_ei, resp);
  174. if (ret < 0) {
  175. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  176. ret);
  177. goto out;
  178. }
  179. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  180. QMI_WLFW_IND_REGISTER_REQ_V01,
  181. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  182. wlfw_ind_register_req_msg_v01_ei, req);
  183. if (ret < 0) {
  184. qmi_txn_cancel(&txn);
  185. cnss_pr_err("Failed to send indication register request, err: %d\n",
  186. ret);
  187. goto out;
  188. }
  189. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  190. if (ret < 0) {
  191. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  192. ret);
  193. goto out;
  194. }
  195. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  196. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  197. resp->resp.result, resp->resp.error);
  198. ret = -resp->resp.result;
  199. goto out;
  200. }
  201. if (resp->fw_status_valid) {
  202. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  203. ret = -EALREADY;
  204. goto qmi_registered;
  205. }
  206. }
  207. kfree(req);
  208. kfree(resp);
  209. return 0;
  210. out:
  211. CNSS_QMI_ASSERT();
  212. qmi_registered:
  213. kfree(req);
  214. kfree(resp);
  215. return ret;
  216. }
  217. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  218. struct wlfw_host_cap_req_msg_v01 *req)
  219. {
  220. if (plat_priv->device_id == KIWI_DEVICE_ID ||
  221. plat_priv->device_id == MANGO_DEVICE_ID ||
  222. plat_priv->device_id == PEACH_DEVICE_ID) {
  223. req->mlo_capable_valid = 1;
  224. req->mlo_capable = 1;
  225. req->mlo_chip_id_valid = 1;
  226. req->mlo_chip_id = 0;
  227. req->mlo_group_id_valid = 1;
  228. req->mlo_group_id = 0;
  229. req->max_mlo_peer_valid = 1;
  230. /* Max peer number generally won't change for the same device
  231. * but needs to be synced with host driver.
  232. */
  233. req->max_mlo_peer = 32;
  234. req->mlo_num_chips_valid = 1;
  235. req->mlo_num_chips = 1;
  236. req->mlo_chip_info_valid = 1;
  237. req->mlo_chip_info[0].chip_id = 0;
  238. req->mlo_chip_info[0].num_local_links = 2;
  239. req->mlo_chip_info[0].hw_link_id[0] = 0;
  240. req->mlo_chip_info[0].hw_link_id[1] = 1;
  241. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  242. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  243. }
  244. }
  245. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  246. {
  247. struct wlfw_host_cap_req_msg_v01 *req;
  248. struct wlfw_host_cap_resp_msg_v01 *resp;
  249. struct qmi_txn txn;
  250. int ret = 0;
  251. u64 iova_start = 0, iova_size = 0,
  252. iova_ipa_start = 0, iova_ipa_size = 0;
  253. u64 feature_list = 0;
  254. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  255. plat_priv->driver_state);
  256. req = kzalloc(sizeof(*req), GFP_KERNEL);
  257. if (!req)
  258. return -ENOMEM;
  259. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  260. if (!resp) {
  261. kfree(req);
  262. return -ENOMEM;
  263. }
  264. req->num_clients_valid = 1;
  265. req->num_clients = 1;
  266. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  267. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  268. if (req->wake_msi) {
  269. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  270. req->wake_msi_valid = 1;
  271. }
  272. req->bdf_support_valid = 1;
  273. req->bdf_support = 1;
  274. req->m3_support_valid = 1;
  275. req->m3_support = 1;
  276. req->m3_cache_support_valid = 1;
  277. req->m3_cache_support = 1;
  278. req->cal_done_valid = 1;
  279. req->cal_done = plat_priv->cal_done;
  280. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  281. if (plat_priv->sleep_clk) {
  282. req->nm_modem_valid = 1;
  283. /* Notify firmware about the sleep clock selection,
  284. * nm_modem_bit[1] is used for this purpose.
  285. */
  286. req->nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT;
  287. }
  288. if (plat_priv->supported_link_speed) {
  289. req->pcie_link_info_valid = 1;
  290. req->pcie_link_info.pci_link_speed =
  291. plat_priv->supported_link_speed;
  292. cnss_pr_dbg("Supported link speed in Host Cap %d\n",
  293. plat_priv->supported_link_speed);
  294. }
  295. if (cnss_bus_is_smmu_s1_enabled(plat_priv) &&
  296. !cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  297. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  298. &iova_ipa_size)) {
  299. req->ddr_range_valid = 1;
  300. req->ddr_range[0].start = iova_start;
  301. req->ddr_range[0].size = iova_size + iova_ipa_size;
  302. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  303. req->ddr_range[0].start, req->ddr_range[0].size);
  304. }
  305. req->host_build_type_valid = 1;
  306. req->host_build_type = cnss_get_host_build_type();
  307. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  308. ret = cnss_get_feature_list(plat_priv, &feature_list);
  309. if (!ret) {
  310. req->feature_list_valid = 1;
  311. req->feature_list = feature_list;
  312. cnss_pr_dbg("Sending feature list 0x%llx\n",
  313. req->feature_list);
  314. }
  315. if (cnss_get_platform_name(plat_priv, req->platform_name,
  316. QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01))
  317. req->platform_name_valid = 1;
  318. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  319. wlfw_host_cap_resp_msg_v01_ei, resp);
  320. if (ret < 0) {
  321. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  322. ret);
  323. goto out;
  324. }
  325. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  326. QMI_WLFW_HOST_CAP_REQ_V01,
  327. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  328. wlfw_host_cap_req_msg_v01_ei, req);
  329. if (ret < 0) {
  330. qmi_txn_cancel(&txn);
  331. cnss_pr_err("Failed to send host capability request, err: %d\n",
  332. ret);
  333. goto out;
  334. }
  335. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  336. if (ret < 0) {
  337. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  338. ret);
  339. goto out;
  340. }
  341. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  342. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  343. resp->resp.result, resp->resp.error);
  344. ret = -resp->resp.result;
  345. goto out;
  346. }
  347. kfree(req);
  348. kfree(resp);
  349. return 0;
  350. out:
  351. CNSS_QMI_ASSERT();
  352. kfree(req);
  353. kfree(resp);
  354. return ret;
  355. }
  356. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  357. {
  358. struct wlfw_respond_mem_req_msg_v01 *req;
  359. struct wlfw_respond_mem_resp_msg_v01 *resp;
  360. struct qmi_txn txn;
  361. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  362. int ret = 0, i;
  363. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  364. plat_priv->driver_state);
  365. req = kzalloc(sizeof(*req), GFP_KERNEL);
  366. if (!req)
  367. return -ENOMEM;
  368. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  369. if (!resp) {
  370. kfree(req);
  371. return -ENOMEM;
  372. }
  373. if (plat_priv->fw_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  374. cnss_pr_err("Invalid seg len %u\n", plat_priv->fw_mem_seg_len);
  375. ret = -EINVAL;
  376. goto out;
  377. }
  378. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  379. for (i = 0; i < req->mem_seg_len; i++) {
  380. if (!fw_mem[i].pa || !fw_mem[i].size) {
  381. if (fw_mem[i].type == 0) {
  382. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  383. i);
  384. ret = -EINVAL;
  385. goto out;
  386. }
  387. cnss_pr_err("Memory for FW is not available for type: %u\n",
  388. fw_mem[i].type);
  389. ret = -ENOMEM;
  390. goto out;
  391. }
  392. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  393. fw_mem[i].va, &fw_mem[i].pa,
  394. fw_mem[i].size, fw_mem[i].type);
  395. req->mem_seg[i].addr = fw_mem[i].pa;
  396. req->mem_seg[i].size = fw_mem[i].size;
  397. req->mem_seg[i].type = fw_mem[i].type;
  398. }
  399. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  400. wlfw_respond_mem_resp_msg_v01_ei, resp);
  401. if (ret < 0) {
  402. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  403. ret);
  404. goto out;
  405. }
  406. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  407. QMI_WLFW_RESPOND_MEM_REQ_V01,
  408. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  409. wlfw_respond_mem_req_msg_v01_ei, req);
  410. if (ret < 0) {
  411. qmi_txn_cancel(&txn);
  412. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  413. ret);
  414. goto out;
  415. }
  416. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  417. if (ret < 0) {
  418. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  419. ret);
  420. goto out;
  421. }
  422. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  423. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  424. resp->resp.result, resp->resp.error);
  425. ret = -resp->resp.result;
  426. goto out;
  427. }
  428. kfree(req);
  429. kfree(resp);
  430. return 0;
  431. out:
  432. CNSS_QMI_ASSERT();
  433. kfree(req);
  434. kfree(resp);
  435. return ret;
  436. }
  437. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  438. {
  439. struct wlfw_cap_req_msg_v01 *req;
  440. struct wlfw_cap_resp_msg_v01 *resp;
  441. struct qmi_txn txn;
  442. char *fw_build_timestamp;
  443. int ret = 0, i;
  444. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  445. plat_priv->driver_state);
  446. req = kzalloc(sizeof(*req), GFP_KERNEL);
  447. if (!req)
  448. return -ENOMEM;
  449. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  450. if (!resp) {
  451. kfree(req);
  452. return -ENOMEM;
  453. }
  454. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  455. wlfw_cap_resp_msg_v01_ei, resp);
  456. if (ret < 0) {
  457. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  458. ret);
  459. goto out;
  460. }
  461. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  462. QMI_WLFW_CAP_REQ_V01,
  463. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  464. wlfw_cap_req_msg_v01_ei, req);
  465. if (ret < 0) {
  466. qmi_txn_cancel(&txn);
  467. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  468. ret);
  469. goto out;
  470. }
  471. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  472. if (ret < 0) {
  473. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  474. ret);
  475. goto out;
  476. }
  477. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  478. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  479. resp->resp.result, resp->resp.error);
  480. ret = -resp->resp.result;
  481. goto out;
  482. }
  483. if (resp->chip_info_valid) {
  484. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  485. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  486. }
  487. if (resp->board_info_valid)
  488. plat_priv->board_info.board_id = resp->board_info.board_id;
  489. else
  490. plat_priv->board_info.board_id = 0xFF;
  491. if (resp->soc_info_valid)
  492. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  493. if (resp->fw_version_info_valid) {
  494. plat_priv->fw_version_info.fw_version =
  495. resp->fw_version_info.fw_version;
  496. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  497. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  498. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  499. resp->fw_version_info.fw_build_timestamp,
  500. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  501. }
  502. if (resp->fw_build_id_valid) {
  503. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  504. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  505. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  506. }
  507. /* FW will send aop retention volatage for qca6490 */
  508. if (resp->voltage_mv_valid) {
  509. plat_priv->cpr_info.voltage = resp->voltage_mv;
  510. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  511. plat_priv->cpr_info.voltage);
  512. cnss_update_cpr_info(plat_priv);
  513. }
  514. if (resp->time_freq_hz_valid) {
  515. plat_priv->device_freq_hz = resp->time_freq_hz;
  516. cnss_pr_dbg("Device frequency is %d HZ\n",
  517. plat_priv->device_freq_hz);
  518. }
  519. if (resp->otp_version_valid)
  520. plat_priv->otp_version = resp->otp_version;
  521. if (resp->dev_mem_info_valid) {
  522. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  523. plat_priv->dev_mem_info[i].start =
  524. resp->dev_mem_info[i].start;
  525. plat_priv->dev_mem_info[i].size =
  526. resp->dev_mem_info[i].size;
  527. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  528. i, plat_priv->dev_mem_info[i].start,
  529. plat_priv->dev_mem_info[i].size);
  530. }
  531. }
  532. if (resp->fw_caps_valid) {
  533. plat_priv->fw_pcie_gen_switch =
  534. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  535. plat_priv->fw_aux_uc_support =
  536. !!(resp->fw_caps & QMI_WLFW_AUX_UC_SUPPORT_V01);
  537. cnss_pr_dbg("FW aux uc support capability: %d\n",
  538. plat_priv->fw_aux_uc_support);
  539. plat_priv->fw_caps = resp->fw_caps;
  540. }
  541. if (resp->hang_data_length_valid &&
  542. resp->hang_data_length &&
  543. resp->hang_data_length <= WLFW_MAX_HANG_EVENT_DATA_SIZE)
  544. plat_priv->hang_event_data_len = resp->hang_data_length;
  545. else
  546. plat_priv->hang_event_data_len = 0;
  547. if (resp->hang_data_addr_offset_valid)
  548. plat_priv->hang_data_addr_offset = resp->hang_data_addr_offset;
  549. else
  550. plat_priv->hang_data_addr_offset = 0;
  551. if (resp->hwid_bitmap_valid)
  552. plat_priv->hwid_bitmap = resp->hwid_bitmap;
  553. if (resp->ol_cpr_cfg_valid)
  554. cnss_aop_ol_cpr_cfg_setup(plat_priv, &resp->ol_cpr_cfg);
  555. /* Disable WLAN PDC in AOP firmware for boards which support on chip PMIC
  556. * so AOP will ignore SW_CTRL changes and do not update regulator votes.
  557. **/
  558. for (i = 0; i < plat_priv->on_chip_pmic_devices_count; i++) {
  559. if (plat_priv->board_info.board_id ==
  560. plat_priv->on_chip_pmic_board_ids[i]) {
  561. cnss_pr_dbg("Disabling WLAN PDC for board_id: %02x\n",
  562. plat_priv->board_info.board_id);
  563. ret = cnss_aop_send_msg(plat_priv,
  564. "{class: wlan_pdc, ss: rf, res: pdc, enable: 0}");
  565. if (ret < 0)
  566. cnss_pr_dbg("Failed to Send AOP Msg");
  567. break;
  568. }
  569. }
  570. if (resp->serial_id_valid) {
  571. plat_priv->serial_id = resp->serial_id;
  572. cnss_pr_info("serial id 0x%x 0x%x\n",
  573. resp->serial_id.serial_id_msb,
  574. resp->serial_id.serial_id_lsb);
  575. }
  576. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  577. plat_priv->chip_info.chip_id,
  578. plat_priv->chip_info.chip_family,
  579. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  580. plat_priv->otp_version);
  581. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, hwid_bitmap:0x%x\n",
  582. plat_priv->fw_version_info.fw_version,
  583. plat_priv->fw_version_info.fw_build_timestamp,
  584. plat_priv->fw_build_id,
  585. plat_priv->hwid_bitmap);
  586. cnss_pr_dbg("Hang event params, Length: 0x%x, Offset Address: 0x%x\n",
  587. plat_priv->hang_event_data_len,
  588. plat_priv->hang_data_addr_offset);
  589. kfree(req);
  590. kfree(resp);
  591. return 0;
  592. out:
  593. CNSS_QMI_ASSERT();
  594. kfree(req);
  595. kfree(resp);
  596. return ret;
  597. }
  598. static char *cnss_bdf_type_to_str(enum cnss_bdf_type bdf_type)
  599. {
  600. switch (bdf_type) {
  601. case CNSS_BDF_BIN:
  602. case CNSS_BDF_ELF:
  603. return "BDF";
  604. case CNSS_BDF_REGDB:
  605. return "REGDB";
  606. case CNSS_BDF_HDS:
  607. return "HDS";
  608. default:
  609. return "UNKNOWN";
  610. }
  611. }
  612. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  613. u32 bdf_type, char *filename,
  614. u32 filename_len)
  615. {
  616. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  617. int ret = 0;
  618. switch (bdf_type) {
  619. case CNSS_BDF_ELF:
  620. /* Board ID will be equal or less than 0xFF in GF mask case */
  621. if (plat_priv->board_info.board_id == 0xFF) {
  622. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  623. snprintf(filename_tmp, filename_len,
  624. ELF_BDF_FILE_NAME_GF);
  625. else
  626. snprintf(filename_tmp, filename_len,
  627. ELF_BDF_FILE_NAME);
  628. } else if (plat_priv->board_info.board_id < 0xFF) {
  629. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  630. snprintf(filename_tmp, filename_len,
  631. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  632. plat_priv->board_info.board_id);
  633. else
  634. snprintf(filename_tmp, filename_len,
  635. ELF_BDF_FILE_NAME_PREFIX "%02x",
  636. plat_priv->board_info.board_id);
  637. } else {
  638. snprintf(filename_tmp, filename_len,
  639. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  640. plat_priv->board_info.board_id >> 8 & 0xFF,
  641. plat_priv->board_info.board_id & 0xFF);
  642. }
  643. break;
  644. case CNSS_BDF_BIN:
  645. if (plat_priv->board_info.board_id == 0xFF) {
  646. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  647. snprintf(filename_tmp, filename_len,
  648. BIN_BDF_FILE_NAME_GF);
  649. else
  650. snprintf(filename_tmp, filename_len,
  651. BIN_BDF_FILE_NAME);
  652. } else if (plat_priv->board_info.board_id < 0xFF) {
  653. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  654. snprintf(filename_tmp, filename_len,
  655. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  656. plat_priv->board_info.board_id);
  657. else
  658. snprintf(filename_tmp, filename_len,
  659. BIN_BDF_FILE_NAME_PREFIX "%02x",
  660. plat_priv->board_info.board_id);
  661. } else {
  662. snprintf(filename_tmp, filename_len,
  663. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  664. plat_priv->board_info.board_id >> 8 & 0xFF,
  665. plat_priv->board_info.board_id & 0xFF);
  666. }
  667. break;
  668. case CNSS_BDF_REGDB:
  669. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  670. break;
  671. case CNSS_BDF_HDS:
  672. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  673. break;
  674. default:
  675. cnss_pr_err("Invalid BDF type: %d\n",
  676. plat_priv->ctrl_params.bdf_type);
  677. ret = -EINVAL;
  678. break;
  679. }
  680. if (!ret)
  681. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  682. return ret;
  683. }
  684. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  685. u32 bdf_type)
  686. {
  687. struct wlfw_bdf_download_req_msg_v01 *req;
  688. struct wlfw_bdf_download_resp_msg_v01 *resp;
  689. struct qmi_txn txn;
  690. char filename[MAX_FIRMWARE_NAME_LEN];
  691. const struct firmware *fw_entry = NULL;
  692. const u8 *temp;
  693. unsigned int remaining;
  694. int ret = 0;
  695. cnss_pr_dbg("Sending QMI_WLFW_BDF_DOWNLOAD_REQ_V01 message for bdf_type: %d (%s), state: 0x%lx\n",
  696. bdf_type, cnss_bdf_type_to_str(bdf_type), plat_priv->driver_state);
  697. req = kzalloc(sizeof(*req), GFP_KERNEL);
  698. if (!req)
  699. return -ENOMEM;
  700. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  701. if (!resp) {
  702. kfree(req);
  703. return -ENOMEM;
  704. }
  705. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  706. filename, sizeof(filename));
  707. if (ret)
  708. goto err_req_fw;
  709. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n", filename);
  710. if (bdf_type == CNSS_BDF_REGDB)
  711. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  712. filename);
  713. else
  714. ret = firmware_request_nowarn(&fw_entry, filename,
  715. &plat_priv->plat_dev->dev);
  716. if (ret) {
  717. cnss_pr_err("Failed to load %s: %s, ret: %d\n",
  718. cnss_bdf_type_to_str(bdf_type), filename, ret);
  719. goto err_req_fw;
  720. }
  721. temp = fw_entry->data;
  722. remaining = fw_entry->size;
  723. cnss_pr_dbg("Downloading %s: %s, size: %u\n",
  724. cnss_bdf_type_to_str(bdf_type), filename, remaining);
  725. while (remaining) {
  726. req->valid = 1;
  727. req->file_id_valid = 1;
  728. req->file_id = plat_priv->board_info.board_id;
  729. req->total_size_valid = 1;
  730. req->total_size = remaining;
  731. req->seg_id_valid = 1;
  732. req->data_valid = 1;
  733. req->end_valid = 1;
  734. req->bdf_type_valid = 1;
  735. req->bdf_type = bdf_type;
  736. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  737. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  738. } else {
  739. req->data_len = remaining;
  740. req->end = 1;
  741. }
  742. memcpy(req->data, temp, req->data_len);
  743. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  744. wlfw_bdf_download_resp_msg_v01_ei, resp);
  745. if (ret < 0) {
  746. cnss_pr_err("Failed to initialize txn for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  747. cnss_bdf_type_to_str(bdf_type), ret);
  748. goto err_send;
  749. }
  750. ret = qmi_send_request
  751. (&plat_priv->qmi_wlfw, NULL, &txn,
  752. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  753. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  754. wlfw_bdf_download_req_msg_v01_ei, req);
  755. if (ret < 0) {
  756. qmi_txn_cancel(&txn);
  757. cnss_pr_err("Failed to send QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  758. cnss_bdf_type_to_str(bdf_type), ret);
  759. goto err_send;
  760. }
  761. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  762. if (ret < 0) {
  763. cnss_pr_err("Timeout while waiting for FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, err: %d\n",
  764. cnss_bdf_type_to_str(bdf_type), ret);
  765. goto err_send;
  766. }
  767. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  768. cnss_pr_err("FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s failed, result: %d, err: %d\n",
  769. cnss_bdf_type_to_str(bdf_type), resp->resp.result,
  770. resp->resp.error);
  771. ret = -resp->resp.result;
  772. goto err_send;
  773. }
  774. remaining -= req->data_len;
  775. temp += req->data_len;
  776. req->seg_id++;
  777. }
  778. release_firmware(fw_entry);
  779. if (resp->host_bdf_data_valid) {
  780. /* QCA6490 enable S3E regulator for IPA configuration only */
  781. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  782. cnss_enable_int_pow_amp_vreg(plat_priv);
  783. plat_priv->cbc_file_download =
  784. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  785. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  786. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  787. plat_priv->cbc_file_download);
  788. }
  789. kfree(req);
  790. kfree(resp);
  791. return 0;
  792. err_send:
  793. release_firmware(fw_entry);
  794. err_req_fw:
  795. if (!(bdf_type == CNSS_BDF_REGDB ||
  796. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  797. ret == -EAGAIN))
  798. CNSS_QMI_ASSERT();
  799. kfree(req);
  800. kfree(resp);
  801. return ret;
  802. }
  803. int cnss_wlfw_tme_patch_dnld_send_sync(struct cnss_plat_data *plat_priv,
  804. enum wlfw_tme_lite_file_type_v01 file)
  805. {
  806. struct wlfw_tme_lite_info_req_msg_v01 *req;
  807. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  808. struct qmi_txn txn;
  809. struct cnss_fw_mem *tme_lite_mem = &plat_priv->tme_lite_mem;
  810. int ret = 0;
  811. cnss_pr_dbg("Sending TME patch information message, state: 0x%lx\n",
  812. plat_priv->driver_state);
  813. if (plat_priv->device_id != PEACH_DEVICE_ID)
  814. return 0;
  815. req = kzalloc(sizeof(*req), GFP_KERNEL);
  816. if (!req)
  817. return -ENOMEM;
  818. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  819. if (!resp) {
  820. kfree(req);
  821. return -ENOMEM;
  822. }
  823. if (!tme_lite_mem->pa || !tme_lite_mem->size) {
  824. cnss_pr_err("Memory for TME patch is not available\n");
  825. ret = -ENOMEM;
  826. goto out;
  827. }
  828. cnss_pr_dbg("TME-L patch memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  829. tme_lite_mem->va, &tme_lite_mem->pa, tme_lite_mem->size);
  830. req->tme_file = file;
  831. req->addr = plat_priv->tme_lite_mem.pa;
  832. req->size = plat_priv->tme_lite_mem.size;
  833. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  834. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  835. if (ret < 0) {
  836. cnss_pr_err("Failed to initialize txn for TME patch information request, err: %d\n",
  837. ret);
  838. goto out;
  839. }
  840. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  841. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  842. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  843. wlfw_tme_lite_info_req_msg_v01_ei, req);
  844. if (ret < 0) {
  845. qmi_txn_cancel(&txn);
  846. cnss_pr_err("Failed to send TME patch information request, err: %d\n",
  847. ret);
  848. goto out;
  849. }
  850. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  851. if (ret < 0) {
  852. cnss_pr_err("Failed to wait for response of TME patch information request, err: %d\n",
  853. ret);
  854. goto out;
  855. }
  856. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  857. cnss_pr_err("TME patch information request failed, result: %d, err: %d\n",
  858. resp->resp.result, resp->resp.error);
  859. ret = -resp->resp.result;
  860. goto out;
  861. }
  862. kfree(req);
  863. kfree(resp);
  864. return 0;
  865. out:
  866. kfree(req);
  867. kfree(resp);
  868. return ret;
  869. }
  870. int cnss_wlfw_tme_opt_file_dnld_send_sync(struct cnss_plat_data *plat_priv,
  871. enum wlfw_tme_lite_file_type_v01 file)
  872. {
  873. struct wlfw_tme_lite_info_req_msg_v01 *req;
  874. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  875. struct qmi_txn txn;
  876. struct cnss_fw_mem *tme_opt_file_mem = NULL;
  877. char *file_name = NULL;
  878. int ret = 0;
  879. if (plat_priv->device_id != PEACH_DEVICE_ID)
  880. return 0;
  881. cnss_pr_dbg("Sending TME opt file information message, state: 0x%lx\n",
  882. plat_priv->driver_state);
  883. req = kzalloc(sizeof(*req), GFP_KERNEL);
  884. if (!req)
  885. return -ENOMEM;
  886. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  887. if (!resp) {
  888. kfree(req);
  889. return -ENOMEM;
  890. }
  891. if (file == WLFW_TME_LITE_OEM_FUSE_FILE_V01) {
  892. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[0];
  893. file_name = TME_OEM_FUSE_FILE_NAME;
  894. } else if (file == WLFW_TME_LITE_RPR_FILE_V01) {
  895. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[1];
  896. file_name = TME_RPR_FILE_NAME;
  897. } else if (file == WLFW_TME_LITE_DPR_FILE_V01) {
  898. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[2];
  899. file_name = TME_DPR_FILE_NAME;
  900. }
  901. if (!tme_opt_file_mem || !tme_opt_file_mem->pa ||
  902. !tme_opt_file_mem->size) {
  903. cnss_pr_err("Memory for TME opt file is not available\n");
  904. ret = -ENOMEM;
  905. goto out;
  906. }
  907. cnss_pr_dbg("TME opt file %s memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  908. file_name, tme_opt_file_mem->va, &tme_opt_file_mem->pa, tme_opt_file_mem->size);
  909. req->tme_file = file;
  910. req->addr = tme_opt_file_mem->pa;
  911. req->size = tme_opt_file_mem->size;
  912. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  913. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  914. if (ret < 0) {
  915. cnss_pr_err("Failed to initialize txn for TME opt file information request, err: %d\n",
  916. ret);
  917. goto out;
  918. }
  919. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  920. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  921. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  922. wlfw_tme_lite_info_req_msg_v01_ei, req);
  923. if (ret < 0) {
  924. qmi_txn_cancel(&txn);
  925. cnss_pr_err("Failed to send TME opt file information request, err: %d\n",
  926. ret);
  927. goto out;
  928. }
  929. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  930. if (ret < 0) {
  931. cnss_pr_err("Failed to wait for response of TME opt file information request, err: %d\n",
  932. ret);
  933. goto out;
  934. }
  935. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  936. ret = -resp->resp.result;
  937. if (resp->resp.error == QMI_ERR_HARDWARE_RESTRICTED_V01) {
  938. cnss_pr_err("TME Power On failed\n");
  939. goto out;
  940. } else if (resp->resp.error == QMI_ERR_ENOMEM_V01) {
  941. cnss_pr_err("malloc SRAM failed\n");
  942. goto out;
  943. }
  944. cnss_pr_err("TME opt file information request failed, result: %d, err: %d\n",
  945. resp->resp.result, resp->resp.error);
  946. goto out;
  947. }
  948. kfree(req);
  949. kfree(resp);
  950. return 0;
  951. out:
  952. CNSS_QMI_ASSERT();
  953. kfree(req);
  954. kfree(resp);
  955. return ret;
  956. }
  957. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  958. {
  959. struct wlfw_m3_info_req_msg_v01 *req;
  960. struct wlfw_m3_info_resp_msg_v01 *resp;
  961. struct qmi_txn txn;
  962. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  963. int ret = 0;
  964. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  965. plat_priv->driver_state);
  966. req = kzalloc(sizeof(*req), GFP_KERNEL);
  967. if (!req)
  968. return -ENOMEM;
  969. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  970. if (!resp) {
  971. kfree(req);
  972. return -ENOMEM;
  973. }
  974. if (!m3_mem->pa || !m3_mem->size) {
  975. cnss_pr_err("Memory for M3 is not available\n");
  976. ret = -ENOMEM;
  977. goto out;
  978. }
  979. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  980. m3_mem->va, &m3_mem->pa, m3_mem->size);
  981. req->addr = plat_priv->m3_mem.pa;
  982. req->size = plat_priv->m3_mem.size;
  983. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  984. wlfw_m3_info_resp_msg_v01_ei, resp);
  985. if (ret < 0) {
  986. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  987. ret);
  988. goto out;
  989. }
  990. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  991. QMI_WLFW_M3_INFO_REQ_V01,
  992. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  993. wlfw_m3_info_req_msg_v01_ei, req);
  994. if (ret < 0) {
  995. qmi_txn_cancel(&txn);
  996. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  997. ret);
  998. goto out;
  999. }
  1000. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1001. if (ret < 0) {
  1002. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  1003. ret);
  1004. goto out;
  1005. }
  1006. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1007. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  1008. resp->resp.result, resp->resp.error);
  1009. ret = -resp->resp.result;
  1010. goto out;
  1011. }
  1012. kfree(req);
  1013. kfree(resp);
  1014. return 0;
  1015. out:
  1016. CNSS_QMI_ASSERT();
  1017. kfree(req);
  1018. kfree(resp);
  1019. return ret;
  1020. }
  1021. int cnss_wlfw_aux_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1022. {
  1023. struct wlfw_aux_uc_info_req_msg_v01 *req;
  1024. struct wlfw_aux_uc_info_resp_msg_v01 *resp;
  1025. struct qmi_txn txn;
  1026. struct cnss_fw_mem *aux_mem = &plat_priv->aux_mem;
  1027. int ret = 0;
  1028. cnss_pr_dbg("Sending QMI_WLFW_AUX_UC_INFO_REQ_V01 message, state: 0x%lx\n",
  1029. plat_priv->driver_state);
  1030. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1031. if (!req)
  1032. return -ENOMEM;
  1033. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1034. if (!resp) {
  1035. kfree(req);
  1036. return -ENOMEM;
  1037. }
  1038. if (!aux_mem->pa || !aux_mem->size) {
  1039. cnss_pr_err("Memory for AUX is not available\n");
  1040. ret = -ENOMEM;
  1041. goto out;
  1042. }
  1043. cnss_pr_dbg("AUX memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  1044. aux_mem->va, &aux_mem->pa, aux_mem->size);
  1045. req->addr = plat_priv->aux_mem.pa;
  1046. req->size = plat_priv->aux_mem.size;
  1047. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1048. wlfw_aux_uc_info_resp_msg_v01_ei, resp);
  1049. if (ret < 0) {
  1050. cnss_pr_err("Failed to initialize txn for QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1051. ret);
  1052. goto out;
  1053. }
  1054. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1055. QMI_WLFW_AUX_UC_INFO_REQ_V01,
  1056. WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1057. wlfw_aux_uc_info_req_msg_v01_ei, req);
  1058. if (ret < 0) {
  1059. qmi_txn_cancel(&txn);
  1060. cnss_pr_err("Failed to send QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1061. ret);
  1062. goto out;
  1063. }
  1064. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1065. if (ret < 0) {
  1066. cnss_pr_err("Failed to wait for response of QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1067. ret);
  1068. goto out;
  1069. }
  1070. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1071. cnss_pr_err("QMI_WLFW_AUX_UC_INFO_REQ_V01 request failed, result: %d, err: %d\n",
  1072. resp->resp.result, resp->resp.error);
  1073. ret = -resp->resp.result;
  1074. goto out;
  1075. }
  1076. kfree(req);
  1077. kfree(resp);
  1078. return 0;
  1079. out:
  1080. CNSS_QMI_ASSERT();
  1081. kfree(req);
  1082. kfree(resp);
  1083. return ret;
  1084. }
  1085. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  1086. u8 *mac, u32 mac_len)
  1087. {
  1088. struct wlfw_mac_addr_req_msg_v01 req;
  1089. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  1090. struct qmi_txn txn;
  1091. int ret;
  1092. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  1093. return -EINVAL;
  1094. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1095. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  1096. if (ret < 0) {
  1097. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  1098. ret);
  1099. ret = -EIO;
  1100. goto out;
  1101. }
  1102. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  1103. mac, plat_priv->driver_state);
  1104. memcpy(req.mac_addr, mac, mac_len);
  1105. req.mac_addr_valid = 1;
  1106. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1107. QMI_WLFW_MAC_ADDR_REQ_V01,
  1108. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  1109. wlfw_mac_addr_req_msg_v01_ei, &req);
  1110. if (ret < 0) {
  1111. qmi_txn_cancel(&txn);
  1112. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  1113. ret = -EIO;
  1114. goto out;
  1115. }
  1116. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1117. if (ret < 0) {
  1118. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  1119. ret);
  1120. ret = -EIO;
  1121. goto out;
  1122. }
  1123. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1124. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  1125. resp.resp.result);
  1126. ret = -resp.resp.result;
  1127. }
  1128. out:
  1129. return ret;
  1130. }
  1131. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  1132. u32 total_size)
  1133. {
  1134. int ret = 0;
  1135. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  1136. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  1137. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  1138. unsigned int remaining;
  1139. struct qmi_txn txn;
  1140. cnss_pr_dbg("%s\n", __func__);
  1141. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1142. if (!req)
  1143. return -ENOMEM;
  1144. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1145. if (!resp) {
  1146. kfree(req);
  1147. return -ENOMEM;
  1148. }
  1149. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  1150. if (!p_qdss_trace_data) {
  1151. ret = ENOMEM;
  1152. goto end;
  1153. }
  1154. remaining = total_size;
  1155. p_qdss_trace_data_temp = p_qdss_trace_data;
  1156. while (remaining && resp->end == 0) {
  1157. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1158. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  1159. if (ret < 0) {
  1160. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  1161. ret);
  1162. goto fail;
  1163. }
  1164. ret = qmi_send_request
  1165. (&plat_priv->qmi_wlfw, NULL, &txn,
  1166. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  1167. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  1168. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  1169. if (ret < 0) {
  1170. qmi_txn_cancel(&txn);
  1171. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  1172. ret);
  1173. goto fail;
  1174. }
  1175. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1176. if (ret < 0) {
  1177. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  1178. ret);
  1179. goto fail;
  1180. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1181. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  1182. resp->resp.result, resp->resp.error);
  1183. ret = -resp->resp.result;
  1184. goto fail;
  1185. } else {
  1186. ret = 0;
  1187. }
  1188. cnss_pr_dbg("%s: response total size %d data len %d",
  1189. __func__, resp->total_size, resp->data_len);
  1190. if ((resp->total_size_valid == 1 &&
  1191. resp->total_size == total_size) &&
  1192. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  1193. (resp->data_valid == 1 &&
  1194. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01) &&
  1195. resp->data_len <= remaining) {
  1196. memcpy(p_qdss_trace_data_temp,
  1197. resp->data, resp->data_len);
  1198. } else {
  1199. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  1200. __func__,
  1201. total_size, req->seg_id,
  1202. resp->total_size_valid,
  1203. resp->total_size,
  1204. resp->seg_id_valid,
  1205. resp->seg_id,
  1206. resp->data_valid,
  1207. resp->data_len);
  1208. ret = -1;
  1209. goto fail;
  1210. }
  1211. remaining -= resp->data_len;
  1212. p_qdss_trace_data_temp += resp->data_len;
  1213. req->seg_id++;
  1214. }
  1215. if (remaining == 0 && (resp->end_valid && resp->end)) {
  1216. ret = cnss_genl_send_msg(p_qdss_trace_data,
  1217. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  1218. total_size);
  1219. if (ret < 0) {
  1220. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  1221. ret);
  1222. ret = -1;
  1223. goto fail;
  1224. }
  1225. } else {
  1226. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  1227. __func__,
  1228. remaining, resp->end_valid, resp->end);
  1229. ret = -1;
  1230. goto fail;
  1231. }
  1232. fail:
  1233. kfree(p_qdss_trace_data);
  1234. end:
  1235. kfree(req);
  1236. kfree(resp);
  1237. return ret;
  1238. }
  1239. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  1240. char *filename, u32 filename_len,
  1241. bool fallback_file)
  1242. {
  1243. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  1244. char *build_str = QDSS_FILE_BUILD_STR;
  1245. if (fallback_file)
  1246. build_str = "";
  1247. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  1248. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1249. "_%s%s.cfg", build_str, HW_V2_NUMBER);
  1250. else
  1251. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1252. "_%s%s.cfg", build_str, HW_V1_NUMBER);
  1253. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  1254. }
  1255. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1256. {
  1257. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  1258. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  1259. struct qmi_txn txn;
  1260. const struct firmware *fw_entry = NULL;
  1261. const u8 *temp;
  1262. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  1263. unsigned int remaining;
  1264. int ret = 0;
  1265. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  1266. plat_priv->driver_state);
  1267. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1268. if (!req)
  1269. return -ENOMEM;
  1270. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1271. if (!resp) {
  1272. kfree(req);
  1273. return -ENOMEM;
  1274. }
  1275. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1276. sizeof(qdss_cfg_filename), false);
  1277. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1278. qdss_cfg_filename);
  1279. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1280. qdss_cfg_filename);
  1281. if (ret) {
  1282. cnss_pr_dbg("Unable to load %s ret %d, try default file\n",
  1283. qdss_cfg_filename, ret);
  1284. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1285. sizeof(qdss_cfg_filename),
  1286. true);
  1287. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1288. qdss_cfg_filename);
  1289. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1290. qdss_cfg_filename);
  1291. if (ret) {
  1292. cnss_pr_err("Unable to load %s ret %d\n",
  1293. qdss_cfg_filename, ret);
  1294. goto err_req_fw;
  1295. }
  1296. }
  1297. temp = fw_entry->data;
  1298. remaining = fw_entry->size;
  1299. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  1300. qdss_cfg_filename, remaining);
  1301. while (remaining) {
  1302. req->total_size_valid = 1;
  1303. req->total_size = remaining;
  1304. req->seg_id_valid = 1;
  1305. req->data_valid = 1;
  1306. req->end_valid = 1;
  1307. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1308. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  1309. } else {
  1310. req->data_len = remaining;
  1311. req->end = 1;
  1312. }
  1313. memcpy(req->data, temp, req->data_len);
  1314. ret = qmi_txn_init
  1315. (&plat_priv->qmi_wlfw, &txn,
  1316. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  1317. resp);
  1318. if (ret < 0) {
  1319. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  1320. ret);
  1321. goto err_send;
  1322. }
  1323. ret = qmi_send_request
  1324. (&plat_priv->qmi_wlfw, NULL, &txn,
  1325. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  1326. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  1327. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  1328. if (ret < 0) {
  1329. qmi_txn_cancel(&txn);
  1330. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  1331. ret);
  1332. goto err_send;
  1333. }
  1334. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1335. if (ret < 0) {
  1336. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  1337. ret);
  1338. goto err_send;
  1339. }
  1340. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1341. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  1342. resp->resp.result, resp->resp.error);
  1343. ret = -resp->resp.result;
  1344. goto err_send;
  1345. }
  1346. remaining -= req->data_len;
  1347. temp += req->data_len;
  1348. req->seg_id++;
  1349. }
  1350. release_firmware(fw_entry);
  1351. kfree(req);
  1352. kfree(resp);
  1353. return 0;
  1354. err_send:
  1355. release_firmware(fw_entry);
  1356. err_req_fw:
  1357. kfree(req);
  1358. kfree(resp);
  1359. return ret;
  1360. }
  1361. static int wlfw_send_qdss_trace_mode_req
  1362. (struct cnss_plat_data *plat_priv,
  1363. enum wlfw_qdss_trace_mode_enum_v01 mode,
  1364. unsigned long long option)
  1365. {
  1366. int rc = 0;
  1367. int tmp = 0;
  1368. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  1369. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  1370. struct qmi_txn txn;
  1371. if (!plat_priv)
  1372. return -ENODEV;
  1373. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1374. if (!req)
  1375. return -ENOMEM;
  1376. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1377. if (!resp) {
  1378. kfree(req);
  1379. return -ENOMEM;
  1380. }
  1381. req->mode_valid = 1;
  1382. req->mode = mode;
  1383. req->option_valid = 1;
  1384. req->option = option;
  1385. tmp = plat_priv->hw_trc_override;
  1386. req->hw_trc_disable_override_valid = 1;
  1387. req->hw_trc_disable_override =
  1388. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1389. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1390. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1391. __func__, mode, option, req->hw_trc_disable_override);
  1392. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1393. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1394. if (rc < 0) {
  1395. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1396. rc);
  1397. goto out;
  1398. }
  1399. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1400. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1401. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1402. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1403. if (rc < 0) {
  1404. qmi_txn_cancel(&txn);
  1405. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1406. goto out;
  1407. }
  1408. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1409. if (rc < 0) {
  1410. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1411. rc);
  1412. goto out;
  1413. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1414. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1415. resp->resp.result, resp->resp.error);
  1416. rc = -resp->resp.result;
  1417. goto out;
  1418. }
  1419. kfree(resp);
  1420. kfree(req);
  1421. return rc;
  1422. out:
  1423. kfree(resp);
  1424. kfree(req);
  1425. CNSS_QMI_ASSERT();
  1426. return rc;
  1427. }
  1428. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1429. {
  1430. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1431. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1432. }
  1433. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1434. {
  1435. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1436. option);
  1437. }
  1438. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1439. enum cnss_driver_mode mode)
  1440. {
  1441. struct wlfw_wlan_mode_req_msg_v01 *req;
  1442. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1443. struct qmi_txn txn;
  1444. int ret = 0;
  1445. if (!plat_priv)
  1446. return -ENODEV;
  1447. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1448. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1449. if (mode == CNSS_OFF &&
  1450. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1451. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1452. return 0;
  1453. }
  1454. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1455. if (!req)
  1456. return -ENOMEM;
  1457. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1458. if (!resp) {
  1459. kfree(req);
  1460. return -ENOMEM;
  1461. }
  1462. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1463. req->hw_debug_valid = 1;
  1464. req->hw_debug = 0;
  1465. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1466. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1467. if (ret < 0) {
  1468. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1469. cnss_qmi_mode_to_str(mode), mode, ret);
  1470. goto out;
  1471. }
  1472. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1473. QMI_WLFW_WLAN_MODE_REQ_V01,
  1474. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1475. wlfw_wlan_mode_req_msg_v01_ei, req);
  1476. if (ret < 0) {
  1477. qmi_txn_cancel(&txn);
  1478. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1479. cnss_qmi_mode_to_str(mode), mode, ret);
  1480. goto out;
  1481. }
  1482. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1483. if (ret < 0) {
  1484. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1485. cnss_qmi_mode_to_str(mode), mode, ret);
  1486. goto out;
  1487. }
  1488. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1489. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1490. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1491. resp->resp.error);
  1492. ret = -resp->resp.result;
  1493. goto out;
  1494. }
  1495. kfree(req);
  1496. kfree(resp);
  1497. return 0;
  1498. out:
  1499. if (mode == CNSS_OFF) {
  1500. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1501. ret = 0;
  1502. } else {
  1503. CNSS_QMI_ASSERT();
  1504. }
  1505. kfree(req);
  1506. kfree(resp);
  1507. return ret;
  1508. }
  1509. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1510. struct cnss_wlan_enable_cfg *config,
  1511. const char *host_version)
  1512. {
  1513. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1514. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1515. struct qmi_txn txn;
  1516. u32 i, ce_id, num_vectors, user_base_data, base_vector;
  1517. int ret = 0;
  1518. if (!plat_priv)
  1519. return -ENODEV;
  1520. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1521. plat_priv->driver_state);
  1522. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1523. if (!req)
  1524. return -ENOMEM;
  1525. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1526. if (!resp) {
  1527. kfree(req);
  1528. return -ENOMEM;
  1529. }
  1530. req->host_version_valid = 1;
  1531. strlcpy(req->host_version, host_version,
  1532. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1533. req->tgt_cfg_valid = 1;
  1534. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1535. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1536. else
  1537. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1538. for (i = 0; i < req->tgt_cfg_len; i++) {
  1539. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1540. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1541. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1542. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1543. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1544. }
  1545. req->svc_cfg_valid = 1;
  1546. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1547. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1548. else
  1549. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1550. for (i = 0; i < req->svc_cfg_len; i++) {
  1551. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1552. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1553. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1554. }
  1555. if (plat_priv->device_id != KIWI_DEVICE_ID &&
  1556. plat_priv->device_id != MANGO_DEVICE_ID &&
  1557. plat_priv->device_id != PEACH_DEVICE_ID) {
  1558. if (plat_priv->device_id == QCN7605_DEVICE_ID &&
  1559. config->num_shadow_reg_cfg) {
  1560. req->shadow_reg_valid = 1;
  1561. if (config->num_shadow_reg_cfg >
  1562. QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
  1563. req->shadow_reg_len =
  1564. QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
  1565. else
  1566. req->shadow_reg_len =
  1567. config->num_shadow_reg_cfg;
  1568. memcpy(req->shadow_reg, config->shadow_reg_cfg,
  1569. sizeof(struct wlfw_shadow_reg_cfg_s_v01) *
  1570. req->shadow_reg_len);
  1571. } else {
  1572. req->shadow_reg_v2_valid = 1;
  1573. if (config->num_shadow_reg_v2_cfg >
  1574. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1575. req->shadow_reg_v2_len =
  1576. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1577. else
  1578. req->shadow_reg_v2_len =
  1579. config->num_shadow_reg_v2_cfg;
  1580. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1581. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) *
  1582. req->shadow_reg_v2_len);
  1583. }
  1584. } else {
  1585. req->shadow_reg_v3_valid = 1;
  1586. if (config->num_shadow_reg_v3_cfg >
  1587. MAX_NUM_SHADOW_REG_V3)
  1588. req->shadow_reg_v3_len = MAX_NUM_SHADOW_REG_V3;
  1589. else
  1590. req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
  1591. plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
  1592. cnss_pr_dbg("Shadow reg v3 len: %d\n",
  1593. plat_priv->num_shadow_regs_v3);
  1594. memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
  1595. sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) *
  1596. req->shadow_reg_v3_len);
  1597. }
  1598. if (config->rri_over_ddr_cfg_valid) {
  1599. req->rri_over_ddr_cfg_valid = 1;
  1600. req->rri_over_ddr_cfg.base_addr_low =
  1601. config->rri_over_ddr_cfg.base_addr_low;
  1602. req->rri_over_ddr_cfg.base_addr_high =
  1603. config->rri_over_ddr_cfg.base_addr_high;
  1604. }
  1605. if (config->send_msi_ce) {
  1606. ret = cnss_bus_get_msi_assignment(plat_priv,
  1607. CE_MSI_NAME,
  1608. &num_vectors,
  1609. &user_base_data,
  1610. &base_vector);
  1611. if (!ret) {
  1612. req->msi_cfg_valid = 1;
  1613. req->msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1614. for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
  1615. ce_id++) {
  1616. req->msi_cfg[ce_id].ce_id = ce_id;
  1617. req->msi_cfg[ce_id].msi_vector =
  1618. (ce_id % num_vectors) + base_vector;
  1619. }
  1620. }
  1621. }
  1622. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1623. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1624. if (ret < 0) {
  1625. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1626. ret);
  1627. goto out;
  1628. }
  1629. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1630. QMI_WLFW_WLAN_CFG_REQ_V01,
  1631. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1632. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1633. if (ret < 0) {
  1634. qmi_txn_cancel(&txn);
  1635. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1636. ret);
  1637. goto out;
  1638. }
  1639. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1640. if (ret < 0) {
  1641. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1642. ret);
  1643. goto out;
  1644. }
  1645. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1646. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1647. resp->resp.result, resp->resp.error);
  1648. ret = -resp->resp.result;
  1649. goto out;
  1650. }
  1651. kfree(req);
  1652. kfree(resp);
  1653. return 0;
  1654. out:
  1655. CNSS_QMI_ASSERT();
  1656. kfree(req);
  1657. kfree(resp);
  1658. return ret;
  1659. }
  1660. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1661. u32 offset, u32 mem_type,
  1662. u32 data_len, u8 *data)
  1663. {
  1664. struct wlfw_athdiag_read_req_msg_v01 *req;
  1665. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1666. struct qmi_txn txn;
  1667. int ret = 0;
  1668. if (!plat_priv)
  1669. return -ENODEV;
  1670. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1671. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1672. data, data_len);
  1673. return -EINVAL;
  1674. }
  1675. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1676. plat_priv->driver_state, offset, mem_type, data_len);
  1677. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1678. if (!req)
  1679. return -ENOMEM;
  1680. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1681. if (!resp) {
  1682. kfree(req);
  1683. return -ENOMEM;
  1684. }
  1685. req->offset = offset;
  1686. req->mem_type = mem_type;
  1687. req->data_len = data_len;
  1688. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1689. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1690. if (ret < 0) {
  1691. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1692. ret);
  1693. goto out;
  1694. }
  1695. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1696. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1697. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1698. wlfw_athdiag_read_req_msg_v01_ei, req);
  1699. if (ret < 0) {
  1700. qmi_txn_cancel(&txn);
  1701. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1702. ret);
  1703. goto out;
  1704. }
  1705. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1706. if (ret < 0) {
  1707. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1708. ret);
  1709. goto out;
  1710. }
  1711. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1712. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1713. resp->resp.result, resp->resp.error);
  1714. ret = -resp->resp.result;
  1715. goto out;
  1716. }
  1717. if (!resp->data_valid || resp->data_len != data_len) {
  1718. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1719. resp->data_valid, resp->data_len);
  1720. ret = -EINVAL;
  1721. goto out;
  1722. }
  1723. memcpy(data, resp->data, resp->data_len);
  1724. kfree(req);
  1725. kfree(resp);
  1726. return 0;
  1727. out:
  1728. kfree(req);
  1729. kfree(resp);
  1730. return ret;
  1731. }
  1732. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1733. u32 offset, u32 mem_type,
  1734. u32 data_len, u8 *data)
  1735. {
  1736. struct wlfw_athdiag_write_req_msg_v01 *req;
  1737. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1738. struct qmi_txn txn;
  1739. int ret = 0;
  1740. if (!plat_priv)
  1741. return -ENODEV;
  1742. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1743. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1744. data, data_len);
  1745. return -EINVAL;
  1746. }
  1747. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1748. plat_priv->driver_state, offset, mem_type, data_len, data);
  1749. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1750. if (!req)
  1751. return -ENOMEM;
  1752. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1753. if (!resp) {
  1754. kfree(req);
  1755. return -ENOMEM;
  1756. }
  1757. req->offset = offset;
  1758. req->mem_type = mem_type;
  1759. req->data_len = data_len;
  1760. memcpy(req->data, data, data_len);
  1761. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1762. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1763. if (ret < 0) {
  1764. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1765. ret);
  1766. goto out;
  1767. }
  1768. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1769. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1770. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1771. wlfw_athdiag_write_req_msg_v01_ei, req);
  1772. if (ret < 0) {
  1773. qmi_txn_cancel(&txn);
  1774. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1775. ret);
  1776. goto out;
  1777. }
  1778. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1779. if (ret < 0) {
  1780. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1781. ret);
  1782. goto out;
  1783. }
  1784. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1785. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1786. resp->resp.result, resp->resp.error);
  1787. ret = -resp->resp.result;
  1788. goto out;
  1789. }
  1790. kfree(req);
  1791. kfree(resp);
  1792. return 0;
  1793. out:
  1794. kfree(req);
  1795. kfree(resp);
  1796. return ret;
  1797. }
  1798. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1799. u8 fw_log_mode)
  1800. {
  1801. struct wlfw_ini_req_msg_v01 *req;
  1802. struct wlfw_ini_resp_msg_v01 *resp;
  1803. struct qmi_txn txn;
  1804. int ret = 0;
  1805. if (!plat_priv)
  1806. return -ENODEV;
  1807. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1808. plat_priv->driver_state, fw_log_mode);
  1809. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1810. if (!req)
  1811. return -ENOMEM;
  1812. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1813. if (!resp) {
  1814. kfree(req);
  1815. return -ENOMEM;
  1816. }
  1817. req->enablefwlog_valid = 1;
  1818. req->enablefwlog = fw_log_mode;
  1819. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1820. wlfw_ini_resp_msg_v01_ei, resp);
  1821. if (ret < 0) {
  1822. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1823. fw_log_mode, ret);
  1824. goto out;
  1825. }
  1826. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1827. QMI_WLFW_INI_REQ_V01,
  1828. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1829. wlfw_ini_req_msg_v01_ei, req);
  1830. if (ret < 0) {
  1831. qmi_txn_cancel(&txn);
  1832. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1833. fw_log_mode, ret);
  1834. goto out;
  1835. }
  1836. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1837. if (ret < 0) {
  1838. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1839. fw_log_mode, ret);
  1840. goto out;
  1841. }
  1842. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1843. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1844. fw_log_mode, resp->resp.result, resp->resp.error);
  1845. ret = -resp->resp.result;
  1846. goto out;
  1847. }
  1848. kfree(req);
  1849. kfree(resp);
  1850. return 0;
  1851. out:
  1852. kfree(req);
  1853. kfree(resp);
  1854. return ret;
  1855. }
  1856. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1857. {
  1858. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1859. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1860. struct qmi_txn txn;
  1861. int ret = 0;
  1862. if (!plat_priv)
  1863. return -ENODEV;
  1864. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1865. !plat_priv->fw_pcie_gen_switch) {
  1866. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1867. return 0;
  1868. }
  1869. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1870. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1871. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1872. plat_priv->pcie_gen_speed;
  1873. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1874. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1875. if (ret < 0) {
  1876. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1877. ret);
  1878. goto out;
  1879. }
  1880. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1881. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1882. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1883. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1884. if (ret < 0) {
  1885. qmi_txn_cancel(&txn);
  1886. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1887. goto out;
  1888. }
  1889. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1890. if (ret < 0) {
  1891. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1892. ret);
  1893. goto out;
  1894. }
  1895. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1896. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1897. plat_priv->pcie_gen_speed, resp.resp.result,
  1898. resp.resp.error);
  1899. ret = -resp.resp.result;
  1900. }
  1901. out:
  1902. /* Reset PCIE Gen speed after one time use */
  1903. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1904. return ret;
  1905. }
  1906. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1907. {
  1908. struct wlfw_antenna_switch_req_msg_v01 *req;
  1909. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1910. struct qmi_txn txn;
  1911. int ret = 0;
  1912. if (!plat_priv)
  1913. return -ENODEV;
  1914. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1915. plat_priv->driver_state);
  1916. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1917. if (!req)
  1918. return -ENOMEM;
  1919. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1920. if (!resp) {
  1921. kfree(req);
  1922. return -ENOMEM;
  1923. }
  1924. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1925. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1926. if (ret < 0) {
  1927. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1928. ret);
  1929. goto out;
  1930. }
  1931. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1932. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1933. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1934. wlfw_antenna_switch_req_msg_v01_ei, req);
  1935. if (ret < 0) {
  1936. qmi_txn_cancel(&txn);
  1937. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1938. ret);
  1939. goto out;
  1940. }
  1941. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1942. if (ret < 0) {
  1943. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1944. ret);
  1945. goto out;
  1946. }
  1947. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1948. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1949. resp->resp.result, resp->resp.error);
  1950. ret = -resp->resp.result;
  1951. goto out;
  1952. }
  1953. if (resp->antenna_valid)
  1954. plat_priv->antenna = resp->antenna;
  1955. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1956. resp->antenna_valid, resp->antenna);
  1957. kfree(req);
  1958. kfree(resp);
  1959. return 0;
  1960. out:
  1961. kfree(req);
  1962. kfree(resp);
  1963. return ret;
  1964. }
  1965. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1966. {
  1967. struct wlfw_antenna_grant_req_msg_v01 *req;
  1968. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1969. struct qmi_txn txn;
  1970. int ret = 0;
  1971. if (!plat_priv)
  1972. return -ENODEV;
  1973. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1974. plat_priv->driver_state, plat_priv->grant);
  1975. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1976. if (!req)
  1977. return -ENOMEM;
  1978. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1979. if (!resp) {
  1980. kfree(req);
  1981. return -ENOMEM;
  1982. }
  1983. req->grant_valid = 1;
  1984. req->grant = plat_priv->grant;
  1985. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1986. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1987. if (ret < 0) {
  1988. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  1989. ret);
  1990. goto out;
  1991. }
  1992. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1993. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  1994. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  1995. wlfw_antenna_grant_req_msg_v01_ei, req);
  1996. if (ret < 0) {
  1997. qmi_txn_cancel(&txn);
  1998. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  1999. ret);
  2000. goto out;
  2001. }
  2002. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2003. if (ret < 0) {
  2004. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  2005. ret);
  2006. goto out;
  2007. }
  2008. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2009. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  2010. resp->resp.result, resp->resp.error);
  2011. ret = -resp->resp.result;
  2012. goto out;
  2013. }
  2014. kfree(req);
  2015. kfree(resp);
  2016. return 0;
  2017. out:
  2018. kfree(req);
  2019. kfree(resp);
  2020. return ret;
  2021. }
  2022. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  2023. {
  2024. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  2025. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  2026. struct qmi_txn txn;
  2027. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  2028. int ret = 0;
  2029. int i;
  2030. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  2031. plat_priv->driver_state);
  2032. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2033. if (!req)
  2034. return -ENOMEM;
  2035. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2036. if (!resp) {
  2037. kfree(req);
  2038. return -ENOMEM;
  2039. }
  2040. if (plat_priv->qdss_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2041. cnss_pr_err("Invalid seg len %u\n", plat_priv->qdss_mem_seg_len);
  2042. ret = -EINVAL;
  2043. goto out;
  2044. }
  2045. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  2046. for (i = 0; i < req->mem_seg_len; i++) {
  2047. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  2048. qdss_mem[i].va, &qdss_mem[i].pa,
  2049. qdss_mem[i].size, qdss_mem[i].type);
  2050. req->mem_seg[i].addr = qdss_mem[i].pa;
  2051. req->mem_seg[i].size = qdss_mem[i].size;
  2052. req->mem_seg[i].type = qdss_mem[i].type;
  2053. }
  2054. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2055. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  2056. if (ret < 0) {
  2057. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  2058. ret);
  2059. goto out;
  2060. }
  2061. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2062. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  2063. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2064. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  2065. if (ret < 0) {
  2066. qmi_txn_cancel(&txn);
  2067. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  2068. ret);
  2069. goto out;
  2070. }
  2071. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2072. if (ret < 0) {
  2073. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  2074. ret);
  2075. goto out;
  2076. }
  2077. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2078. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  2079. resp->resp.result, resp->resp.error);
  2080. ret = -resp->resp.result;
  2081. goto out;
  2082. }
  2083. kfree(req);
  2084. kfree(resp);
  2085. return 0;
  2086. out:
  2087. kfree(req);
  2088. kfree(resp);
  2089. return ret;
  2090. }
  2091. int cnss_wlfw_send_host_wfc_call_status(struct cnss_plat_data *plat_priv,
  2092. struct cnss_wfc_cfg cfg)
  2093. {
  2094. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2095. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2096. struct qmi_txn txn;
  2097. int ret = 0;
  2098. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2099. cnss_pr_err("Drop host WFC indication as FW not initialized\n");
  2100. return -EINVAL;
  2101. }
  2102. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2103. if (!req)
  2104. return -ENOMEM;
  2105. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2106. if (!resp) {
  2107. kfree(req);
  2108. return -ENOMEM;
  2109. }
  2110. req->wfc_call_active_valid = 1;
  2111. req->wfc_call_active = cfg.mode;
  2112. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2113. plat_priv->driver_state);
  2114. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2115. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2116. if (ret < 0) {
  2117. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2118. ret);
  2119. goto out;
  2120. }
  2121. cnss_pr_dbg("Send WFC Mode: %d\n", cfg.mode);
  2122. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2123. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2124. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2125. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2126. if (ret < 0) {
  2127. qmi_txn_cancel(&txn);
  2128. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2129. ret);
  2130. goto out;
  2131. }
  2132. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2133. if (ret < 0) {
  2134. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2135. ret);
  2136. goto out;
  2137. }
  2138. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2139. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2140. resp->resp.result, resp->resp.error);
  2141. ret = -EINVAL;
  2142. goto out;
  2143. }
  2144. ret = 0;
  2145. out:
  2146. kfree(req);
  2147. kfree(resp);
  2148. return ret;
  2149. }
  2150. static int cnss_wlfw_wfc_call_status_send_sync
  2151. (struct cnss_plat_data *plat_priv,
  2152. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  2153. {
  2154. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2155. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2156. struct qmi_txn txn;
  2157. int ret = 0;
  2158. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2159. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  2160. return -EINVAL;
  2161. }
  2162. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2163. if (!req)
  2164. return -ENOMEM;
  2165. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2166. if (!resp) {
  2167. kfree(req);
  2168. return -ENOMEM;
  2169. }
  2170. /**
  2171. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  2172. * But in r2 update QMI structure is expanded and as an effect qmi
  2173. * decoded structures have padding. Thus we cannot use buffer design.
  2174. * For backward compatibility for r1 design copy only wfc_call_active
  2175. * value in hex buffer.
  2176. */
  2177. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  2178. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  2179. /* wfc_call_active is mandatory in IMS indication */
  2180. req->wfc_call_active_valid = 1;
  2181. req->wfc_call_active = ind_msg->wfc_call_active;
  2182. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  2183. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  2184. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  2185. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  2186. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  2187. req->twt_ims_start = ind_msg->twt_ims_start;
  2188. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  2189. req->twt_ims_int = ind_msg->twt_ims_int;
  2190. req->media_quality_valid = ind_msg->media_quality_valid;
  2191. req->media_quality =
  2192. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  2193. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2194. plat_priv->driver_state);
  2195. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2196. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2197. if (ret < 0) {
  2198. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2199. ret);
  2200. goto out;
  2201. }
  2202. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2203. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2204. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2205. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2206. if (ret < 0) {
  2207. qmi_txn_cancel(&txn);
  2208. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2209. ret);
  2210. goto out;
  2211. }
  2212. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2213. if (ret < 0) {
  2214. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2215. ret);
  2216. goto out;
  2217. }
  2218. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2219. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2220. resp->resp.result, resp->resp.error);
  2221. ret = -resp->resp.result;
  2222. goto out;
  2223. }
  2224. ret = 0;
  2225. out:
  2226. kfree(req);
  2227. kfree(resp);
  2228. return ret;
  2229. }
  2230. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  2231. {
  2232. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  2233. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  2234. struct qmi_txn txn;
  2235. int ret = 0;
  2236. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  2237. plat_priv->dynamic_feature,
  2238. plat_priv->driver_state);
  2239. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2240. if (!req)
  2241. return -ENOMEM;
  2242. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2243. if (!resp) {
  2244. kfree(req);
  2245. return -ENOMEM;
  2246. }
  2247. req->mask_valid = 1;
  2248. req->mask = plat_priv->dynamic_feature;
  2249. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2250. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  2251. if (ret < 0) {
  2252. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  2253. ret);
  2254. goto out;
  2255. }
  2256. ret = qmi_send_request
  2257. (&plat_priv->qmi_wlfw, NULL, &txn,
  2258. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  2259. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  2260. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  2261. if (ret < 0) {
  2262. qmi_txn_cancel(&txn);
  2263. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  2264. ret);
  2265. goto out;
  2266. }
  2267. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2268. if (ret < 0) {
  2269. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  2270. ret);
  2271. goto out;
  2272. }
  2273. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2274. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  2275. resp->resp.result, resp->resp.error);
  2276. ret = -resp->resp.result;
  2277. goto out;
  2278. }
  2279. out:
  2280. kfree(req);
  2281. kfree(resp);
  2282. return ret;
  2283. }
  2284. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  2285. void *cmd, int cmd_len)
  2286. {
  2287. struct wlfw_get_info_req_msg_v01 *req;
  2288. struct wlfw_get_info_resp_msg_v01 *resp;
  2289. struct qmi_txn txn;
  2290. int ret = 0;
  2291. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  2292. type, cmd_len, plat_priv->driver_state);
  2293. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  2294. return -EINVAL;
  2295. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2296. if (!req)
  2297. return -ENOMEM;
  2298. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2299. if (!resp) {
  2300. kfree(req);
  2301. return -ENOMEM;
  2302. }
  2303. req->type = type;
  2304. req->data_len = cmd_len;
  2305. memcpy(req->data, cmd, req->data_len);
  2306. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2307. wlfw_get_info_resp_msg_v01_ei, resp);
  2308. if (ret < 0) {
  2309. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  2310. ret);
  2311. goto out;
  2312. }
  2313. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2314. QMI_WLFW_GET_INFO_REQ_V01,
  2315. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2316. wlfw_get_info_req_msg_v01_ei, req);
  2317. if (ret < 0) {
  2318. qmi_txn_cancel(&txn);
  2319. cnss_pr_err("Failed to send get info request, err: %d\n",
  2320. ret);
  2321. goto out;
  2322. }
  2323. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2324. if (ret < 0) {
  2325. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  2326. ret);
  2327. goto out;
  2328. }
  2329. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2330. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  2331. resp->resp.result, resp->resp.error);
  2332. ret = -resp->resp.result;
  2333. goto out;
  2334. }
  2335. kfree(req);
  2336. kfree(resp);
  2337. return 0;
  2338. out:
  2339. kfree(req);
  2340. kfree(resp);
  2341. return ret;
  2342. }
  2343. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  2344. {
  2345. return QMI_WLFW_TIMEOUT_MS;
  2346. }
  2347. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2348. struct sockaddr_qrtr *sq,
  2349. struct qmi_txn *txn, const void *data)
  2350. {
  2351. struct cnss_plat_data *plat_priv =
  2352. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2353. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  2354. int i;
  2355. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  2356. if (!txn) {
  2357. cnss_pr_err("Spurious indication\n");
  2358. return;
  2359. }
  2360. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2361. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2362. return;
  2363. }
  2364. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  2365. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  2366. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  2367. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2368. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  2369. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  2370. if (!plat_priv->fw_mem[i].va &&
  2371. plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  2372. plat_priv->fw_mem[i].attrs |=
  2373. DMA_ATTR_FORCE_CONTIGUOUS;
  2374. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  2375. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  2376. }
  2377. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  2378. 0, NULL);
  2379. }
  2380. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2381. struct sockaddr_qrtr *sq,
  2382. struct qmi_txn *txn, const void *data)
  2383. {
  2384. struct cnss_plat_data *plat_priv =
  2385. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2386. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  2387. if (!txn) {
  2388. cnss_pr_err("Spurious indication\n");
  2389. return;
  2390. }
  2391. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  2392. 0, NULL);
  2393. }
  2394. /**
  2395. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  2396. *
  2397. * This event is not required for HST/ HSP as FW calibration done is
  2398. * provided in QMI_WLFW_CAL_DONE_IND_V01
  2399. */
  2400. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2401. struct sockaddr_qrtr *sq,
  2402. struct qmi_txn *txn, const void *data)
  2403. {
  2404. struct cnss_plat_data *plat_priv =
  2405. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2406. struct cnss_cal_info *cal_info;
  2407. if (!txn) {
  2408. cnss_pr_err("Spurious indication\n");
  2409. return;
  2410. }
  2411. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  2412. plat_priv->device_id == QCA6490_DEVICE_ID) {
  2413. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  2414. return;
  2415. }
  2416. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  2417. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2418. if (!cal_info)
  2419. return;
  2420. cal_info->cal_status = CNSS_CAL_DONE;
  2421. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2422. 0, cal_info);
  2423. }
  2424. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2425. struct sockaddr_qrtr *sq,
  2426. struct qmi_txn *txn, const void *data)
  2427. {
  2428. struct cnss_plat_data *plat_priv =
  2429. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2430. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  2431. if (!txn) {
  2432. cnss_pr_err("Spurious indication\n");
  2433. return;
  2434. }
  2435. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  2436. }
  2437. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  2438. struct sockaddr_qrtr *sq,
  2439. struct qmi_txn *txn, const void *data)
  2440. {
  2441. struct cnss_plat_data *plat_priv =
  2442. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2443. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  2444. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  2445. if (!txn) {
  2446. cnss_pr_err("Spurious indication\n");
  2447. return;
  2448. }
  2449. if (ind_msg->pwr_pin_result_valid)
  2450. plat_priv->pin_result.fw_pwr_pin_result =
  2451. ind_msg->pwr_pin_result;
  2452. if (ind_msg->phy_io_pin_result_valid)
  2453. plat_priv->pin_result.fw_phy_io_pin_result =
  2454. ind_msg->phy_io_pin_result;
  2455. if (ind_msg->rf_pin_result_valid)
  2456. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  2457. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  2458. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  2459. ind_msg->rf_pin_result);
  2460. }
  2461. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  2462. u32 cal_file_download_size)
  2463. {
  2464. struct wlfw_cal_report_req_msg_v01 req = {0};
  2465. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  2466. struct qmi_txn txn;
  2467. int ret = 0;
  2468. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  2469. cal_file_download_size, plat_priv->driver_state);
  2470. req.cal_file_download_size_valid = 1;
  2471. req.cal_file_download_size = cal_file_download_size;
  2472. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2473. wlfw_cal_report_resp_msg_v01_ei, &resp);
  2474. if (ret < 0) {
  2475. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  2476. ret);
  2477. goto out;
  2478. }
  2479. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2480. QMI_WLFW_CAL_REPORT_REQ_V01,
  2481. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  2482. wlfw_cal_report_req_msg_v01_ei, &req);
  2483. if (ret < 0) {
  2484. qmi_txn_cancel(&txn);
  2485. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  2486. ret);
  2487. goto out;
  2488. }
  2489. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2490. if (ret < 0) {
  2491. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  2492. ret);
  2493. goto out;
  2494. }
  2495. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2496. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  2497. resp.resp.result, resp.resp.error);
  2498. ret = -resp.resp.result;
  2499. goto out;
  2500. }
  2501. out:
  2502. return ret;
  2503. }
  2504. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2505. struct sockaddr_qrtr *sq,
  2506. struct qmi_txn *txn, const void *data)
  2507. {
  2508. struct cnss_plat_data *plat_priv =
  2509. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2510. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2511. struct cnss_cal_info *cal_info;
  2512. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2513. ind->cal_file_upload_size);
  2514. cnss_pr_info("Calibration took %d ms\n",
  2515. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2516. if (!txn) {
  2517. cnss_pr_err("Spurious indication\n");
  2518. return;
  2519. }
  2520. if (ind->cal_file_upload_size_valid)
  2521. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2522. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2523. if (!cal_info)
  2524. return;
  2525. cal_info->cal_status = CNSS_CAL_DONE;
  2526. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2527. 0, cal_info);
  2528. }
  2529. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2530. struct sockaddr_qrtr *sq,
  2531. struct qmi_txn *txn,
  2532. const void *data)
  2533. {
  2534. struct cnss_plat_data *plat_priv =
  2535. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2536. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2537. int i;
  2538. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2539. if (!txn) {
  2540. cnss_pr_err("Spurious indication\n");
  2541. return;
  2542. }
  2543. if (plat_priv->qdss_mem_seg_len) {
  2544. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2545. plat_priv->qdss_mem_seg_len);
  2546. return;
  2547. }
  2548. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2549. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2550. return;
  2551. }
  2552. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2553. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2554. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2555. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2556. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2557. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2558. }
  2559. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2560. 0, NULL);
  2561. }
  2562. /**
  2563. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2564. *
  2565. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2566. * fw memory segment for dumping to file system. Only one type of mem can be
  2567. * saved per indication and is provided in mem seg index 0.
  2568. *
  2569. * Return: None
  2570. */
  2571. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2572. struct sockaddr_qrtr *sq,
  2573. struct qmi_txn *txn,
  2574. const void *data)
  2575. {
  2576. struct cnss_plat_data *plat_priv =
  2577. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2578. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2579. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2580. int i = 0;
  2581. if (!txn || !data) {
  2582. cnss_pr_err("Spurious indication\n");
  2583. return;
  2584. }
  2585. cnss_pr_dbg_buf("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2586. ind_msg->source, ind_msg->mem_seg_valid,
  2587. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2588. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2589. if (!event_data)
  2590. return;
  2591. event_data->mem_type = ind_msg->mem_seg[0].type;
  2592. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2593. event_data->total_size = ind_msg->total_size;
  2594. if (ind_msg->mem_seg_valid) {
  2595. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2596. cnss_pr_err("Invalid seg len indication\n");
  2597. goto free_event_data;
  2598. }
  2599. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2600. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2601. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2602. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2603. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2604. goto free_event_data;
  2605. }
  2606. cnss_pr_dbg_buf("seg-%d: addr 0x%llx size 0x%x\n",
  2607. i, ind_msg->mem_seg[i].addr,
  2608. ind_msg->mem_seg[i].size);
  2609. }
  2610. }
  2611. if (ind_msg->file_name_valid)
  2612. strlcpy(event_data->file_name, ind_msg->file_name,
  2613. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2614. if (ind_msg->source == 1) {
  2615. if (!ind_msg->file_name_valid)
  2616. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2617. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2618. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2619. 0, event_data);
  2620. } else {
  2621. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2622. if (!ind_msg->file_name_valid)
  2623. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2624. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2625. } else {
  2626. if (!ind_msg->file_name_valid)
  2627. strlcpy(event_data->file_name, "fw_mem_dump",
  2628. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2629. }
  2630. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2631. 0, event_data);
  2632. }
  2633. return;
  2634. free_event_data:
  2635. kfree(event_data);
  2636. }
  2637. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2638. struct sockaddr_qrtr *sq,
  2639. struct qmi_txn *txn,
  2640. const void *data)
  2641. {
  2642. struct cnss_plat_data *plat_priv =
  2643. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2644. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2645. 0, NULL);
  2646. }
  2647. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2648. struct sockaddr_qrtr *sq,
  2649. struct qmi_txn *txn,
  2650. const void *data)
  2651. {
  2652. struct cnss_plat_data *plat_priv =
  2653. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2654. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2655. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2656. if (!txn) {
  2657. cnss_pr_err("Spurious indication\n");
  2658. return;
  2659. }
  2660. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2661. ind_msg->data_len, ind_msg->type,
  2662. ind_msg->is_last, ind_msg->seq_no);
  2663. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2664. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2665. (void *)ind_msg->data,
  2666. ind_msg->data_len);
  2667. }
  2668. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2669. (struct cnss_plat_data *plat_priv,
  2670. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2671. {
  2672. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2673. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2674. struct qmi_txn txn;
  2675. int ret = 0;
  2676. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2677. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2678. return -EINVAL;
  2679. }
  2680. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2681. if (!req)
  2682. return -ENOMEM;
  2683. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2684. if (!resp) {
  2685. kfree(req);
  2686. return -ENOMEM;
  2687. }
  2688. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2689. req->twt_sta_start = ind_msg->twt_sta_start;
  2690. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2691. req->twt_sta_int = ind_msg->twt_sta_int;
  2692. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2693. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2694. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2695. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2696. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2697. req->twt_sta_dl = req->twt_sta_dl;
  2698. req->twt_sta_config_changed_valid =
  2699. ind_msg->twt_sta_config_changed_valid;
  2700. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2701. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2702. plat_priv->driver_state);
  2703. ret =
  2704. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2705. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2706. resp);
  2707. if (ret < 0) {
  2708. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2709. ret);
  2710. goto out;
  2711. }
  2712. ret =
  2713. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2714. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2715. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2716. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2717. if (ret < 0) {
  2718. qmi_txn_cancel(&txn);
  2719. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2720. goto out;
  2721. }
  2722. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2723. if (ret < 0) {
  2724. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2725. goto out;
  2726. }
  2727. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2728. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2729. resp->resp.result, resp->resp.error);
  2730. ret = -resp->resp.result;
  2731. goto out;
  2732. }
  2733. ret = 0;
  2734. out:
  2735. kfree(req);
  2736. kfree(resp);
  2737. return ret;
  2738. }
  2739. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2740. void *data)
  2741. {
  2742. int ret;
  2743. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2744. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2745. kfree(data);
  2746. return ret;
  2747. }
  2748. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2749. struct sockaddr_qrtr *sq,
  2750. struct qmi_txn *txn,
  2751. const void *data)
  2752. {
  2753. struct cnss_plat_data *plat_priv =
  2754. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2755. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2756. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2757. if (!txn) {
  2758. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2759. return;
  2760. }
  2761. if (!ind_msg) {
  2762. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2763. return;
  2764. }
  2765. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2766. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2767. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2768. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2769. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2770. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2771. ind_msg->twt_sta_config_changed_valid,
  2772. ind_msg->twt_sta_config_changed);
  2773. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2774. if (!event_data)
  2775. return;
  2776. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2777. event_data);
  2778. }
  2779. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2780. {
  2781. .type = QMI_INDICATION,
  2782. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2783. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2784. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2785. .fn = cnss_wlfw_request_mem_ind_cb
  2786. },
  2787. {
  2788. .type = QMI_INDICATION,
  2789. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2790. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2791. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2792. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2793. },
  2794. {
  2795. .type = QMI_INDICATION,
  2796. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2797. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2798. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2799. .fn = cnss_wlfw_fw_ready_ind_cb
  2800. },
  2801. {
  2802. .type = QMI_INDICATION,
  2803. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2804. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2805. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2806. .fn = cnss_wlfw_fw_init_done_ind_cb
  2807. },
  2808. {
  2809. .type = QMI_INDICATION,
  2810. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2811. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2812. .decoded_size =
  2813. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2814. .fn = cnss_wlfw_pin_result_ind_cb
  2815. },
  2816. {
  2817. .type = QMI_INDICATION,
  2818. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2819. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2820. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2821. .fn = cnss_wlfw_cal_done_ind_cb
  2822. },
  2823. {
  2824. .type = QMI_INDICATION,
  2825. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2826. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2827. .decoded_size =
  2828. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2829. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2830. },
  2831. {
  2832. .type = QMI_INDICATION,
  2833. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2834. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2835. .decoded_size =
  2836. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2837. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2838. },
  2839. {
  2840. .type = QMI_INDICATION,
  2841. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2842. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2843. .decoded_size =
  2844. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2845. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2846. },
  2847. {
  2848. .type = QMI_INDICATION,
  2849. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2850. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2851. .decoded_size =
  2852. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2853. .fn = cnss_wlfw_respond_get_info_ind_cb
  2854. },
  2855. {
  2856. .type = QMI_INDICATION,
  2857. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2858. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2859. .decoded_size =
  2860. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2861. .fn = cnss_wlfw_process_twt_cfg_ind
  2862. },
  2863. {}
  2864. };
  2865. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2866. void *data)
  2867. {
  2868. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2869. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2870. struct sockaddr_qrtr sq = { 0 };
  2871. int ret = 0;
  2872. if (!event_data)
  2873. return -EINVAL;
  2874. sq.sq_family = AF_QIPCRTR;
  2875. sq.sq_node = event_data->node;
  2876. sq.sq_port = event_data->port;
  2877. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2878. sizeof(sq), 0);
  2879. if (ret < 0) {
  2880. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2881. goto out;
  2882. }
  2883. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2884. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2885. plat_priv->driver_state);
  2886. kfree(data);
  2887. return 0;
  2888. out:
  2889. CNSS_QMI_ASSERT();
  2890. kfree(data);
  2891. return ret;
  2892. }
  2893. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2894. {
  2895. int ret = 0;
  2896. if (!plat_priv)
  2897. return -ENODEV;
  2898. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2899. cnss_pr_err("Unexpected WLFW server arrive\n");
  2900. CNSS_ASSERT(0);
  2901. return -EINVAL;
  2902. }
  2903. cnss_ignore_qmi_failure(false);
  2904. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2905. if (ret < 0)
  2906. goto out;
  2907. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2908. if (ret < 0) {
  2909. if (ret == -EALREADY)
  2910. ret = 0;
  2911. goto out;
  2912. }
  2913. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2914. if (ret < 0)
  2915. goto out;
  2916. return 0;
  2917. out:
  2918. return ret;
  2919. }
  2920. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2921. {
  2922. int ret;
  2923. if (!plat_priv)
  2924. return -ENODEV;
  2925. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2926. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2927. plat_priv->driver_state);
  2928. cnss_qmi_deinit(plat_priv);
  2929. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2930. ret = cnss_qmi_init(plat_priv);
  2931. if (ret < 0) {
  2932. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2933. CNSS_ASSERT(0);
  2934. }
  2935. return 0;
  2936. }
  2937. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2938. struct qmi_service *service)
  2939. {
  2940. struct cnss_plat_data *plat_priv =
  2941. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2942. struct cnss_qmi_event_server_arrive_data *event_data;
  2943. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2944. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2945. plat_priv->driver_state);
  2946. return 0;
  2947. }
  2948. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2949. service->node, service->port);
  2950. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2951. if (!event_data)
  2952. return -ENOMEM;
  2953. event_data->node = service->node;
  2954. event_data->port = service->port;
  2955. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2956. 0, event_data);
  2957. return 0;
  2958. }
  2959. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2960. struct qmi_service *service)
  2961. {
  2962. struct cnss_plat_data *plat_priv =
  2963. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2964. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2965. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2966. plat_priv->driver_state);
  2967. return;
  2968. }
  2969. cnss_pr_dbg("WLFW server exiting\n");
  2970. if (plat_priv) {
  2971. cnss_ignore_qmi_failure(true);
  2972. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2973. }
  2974. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  2975. 0, NULL);
  2976. }
  2977. static struct qmi_ops qmi_wlfw_ops = {
  2978. .new_server = wlfw_new_server,
  2979. .del_server = wlfw_del_server,
  2980. };
  2981. static int cnss_qmi_add_lookup(struct cnss_plat_data *plat_priv)
  2982. {
  2983. unsigned int id = WLFW_SERVICE_INS_ID_V01;
  2984. /* In order to support dual wlan card attach case,
  2985. * need separate qmi service instance id for each dev
  2986. */
  2987. if (cnss_is_dual_wlan_enabled() && plat_priv->qrtr_node_id != 0 &&
  2988. plat_priv->wlfw_service_instance_id != 0)
  2989. id = plat_priv->wlfw_service_instance_id;
  2990. return qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  2991. WLFW_SERVICE_VERS_V01, id);
  2992. }
  2993. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  2994. {
  2995. int ret = 0;
  2996. cnss_get_qrtr_info(plat_priv);
  2997. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  2998. QMI_WLFW_MAX_RECV_BUF_SIZE,
  2999. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  3000. if (ret < 0) {
  3001. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  3002. ret);
  3003. goto out;
  3004. }
  3005. ret = cnss_qmi_add_lookup(plat_priv);
  3006. if (ret < 0)
  3007. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  3008. out:
  3009. return ret;
  3010. }
  3011. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  3012. {
  3013. qmi_handle_release(&plat_priv->qmi_wlfw);
  3014. }
  3015. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  3016. {
  3017. struct dms_get_mac_address_req_msg_v01 req;
  3018. struct dms_get_mac_address_resp_msg_v01 resp;
  3019. struct qmi_txn txn;
  3020. int ret = 0;
  3021. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  3022. cnss_pr_err("DMS QMI connection not established\n");
  3023. return -EINVAL;
  3024. }
  3025. cnss_pr_dbg("Requesting DMS MAC address");
  3026. memset(&resp, 0, sizeof(resp));
  3027. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  3028. dms_get_mac_address_resp_msg_v01_ei, &resp);
  3029. if (ret < 0) {
  3030. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  3031. ret);
  3032. goto out;
  3033. }
  3034. req.device = DMS_DEVICE_MAC_WLAN_V01;
  3035. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  3036. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  3037. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  3038. dms_get_mac_address_req_msg_v01_ei, &req);
  3039. if (ret < 0) {
  3040. qmi_txn_cancel(&txn);
  3041. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  3042. ret);
  3043. goto out;
  3044. }
  3045. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  3046. if (ret < 0) {
  3047. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  3048. ret);
  3049. goto out;
  3050. }
  3051. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  3052. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  3053. resp.resp.result, resp.resp.error);
  3054. ret = -resp.resp.result;
  3055. goto out;
  3056. }
  3057. if (!resp.mac_address_valid ||
  3058. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  3059. cnss_pr_err("Invalid MAC address received from DMS\n");
  3060. plat_priv->dms.mac_valid = false;
  3061. goto out;
  3062. }
  3063. plat_priv->dms.mac_valid = true;
  3064. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  3065. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  3066. out:
  3067. return ret;
  3068. }
  3069. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  3070. unsigned int node, unsigned int port)
  3071. {
  3072. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  3073. struct sockaddr_qrtr sq = {0};
  3074. int ret = 0;
  3075. sq.sq_family = AF_QIPCRTR;
  3076. sq.sq_node = node;
  3077. sq.sq_port = port;
  3078. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  3079. sizeof(sq), 0);
  3080. if (ret < 0) {
  3081. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  3082. node, port);
  3083. goto out;
  3084. }
  3085. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3086. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  3087. plat_priv->driver_state);
  3088. out:
  3089. return ret;
  3090. }
  3091. static int dms_new_server(struct qmi_handle *qmi_dms,
  3092. struct qmi_service *service)
  3093. {
  3094. struct cnss_plat_data *plat_priv =
  3095. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3096. if (!service)
  3097. return -EINVAL;
  3098. return cnss_dms_connect_to_server(plat_priv, service->node,
  3099. service->port);
  3100. }
  3101. static void cnss_dms_server_exit_work(struct work_struct *work)
  3102. {
  3103. int ret;
  3104. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3105. cnss_dms_deinit(plat_priv);
  3106. cnss_pr_info("QMI DMS Server Exit");
  3107. clear_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3108. ret = cnss_dms_init(plat_priv);
  3109. if (ret < 0)
  3110. cnss_pr_err("QMI DMS service registraton failed, ret\n", ret);
  3111. }
  3112. static DECLARE_WORK(cnss_dms_del_work, cnss_dms_server_exit_work);
  3113. static void dms_del_server(struct qmi_handle *qmi_dms,
  3114. struct qmi_service *service)
  3115. {
  3116. struct cnss_plat_data *plat_priv =
  3117. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3118. if (!plat_priv)
  3119. return;
  3120. if (test_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state)) {
  3121. cnss_pr_info("DMS server delete or cnss remove in progress, Ignore server delete: 0x%lx\n",
  3122. plat_priv->driver_state);
  3123. return;
  3124. }
  3125. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3126. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3127. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  3128. plat_priv->driver_state);
  3129. schedule_work(&cnss_dms_del_work);
  3130. }
  3131. void cnss_cancel_dms_work(void)
  3132. {
  3133. cancel_work_sync(&cnss_dms_del_work);
  3134. }
  3135. static struct qmi_ops qmi_dms_ops = {
  3136. .new_server = dms_new_server,
  3137. .del_server = dms_del_server,
  3138. };
  3139. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  3140. {
  3141. int ret = 0;
  3142. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  3143. &qmi_dms_ops, NULL);
  3144. if (ret < 0) {
  3145. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  3146. goto out;
  3147. }
  3148. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  3149. DMS_SERVICE_VERS_V01, 0);
  3150. if (ret < 0)
  3151. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  3152. out:
  3153. return ret;
  3154. }
  3155. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  3156. {
  3157. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3158. qmi_handle_release(&plat_priv->qmi_dms);
  3159. }
  3160. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  3161. {
  3162. int ret;
  3163. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  3164. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  3165. struct qmi_txn txn;
  3166. if (!plat_priv)
  3167. return -ENODEV;
  3168. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  3169. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3170. if (!req)
  3171. return -ENOMEM;
  3172. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3173. if (!resp) {
  3174. kfree(req);
  3175. return -ENOMEM;
  3176. }
  3177. req->antenna = plat_priv->antenna;
  3178. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3179. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  3180. if (ret < 0) {
  3181. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  3182. ret);
  3183. goto out;
  3184. }
  3185. ret = qmi_send_request
  3186. (&plat_priv->coex_qmi, NULL, &txn,
  3187. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  3188. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  3189. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  3190. if (ret < 0) {
  3191. qmi_txn_cancel(&txn);
  3192. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  3193. ret);
  3194. goto out;
  3195. }
  3196. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3197. if (ret < 0) {
  3198. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  3199. ret);
  3200. goto out;
  3201. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3202. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  3203. resp->resp.result, resp->resp.error);
  3204. ret = -resp->resp.result;
  3205. goto out;
  3206. }
  3207. if (resp->grant_valid)
  3208. plat_priv->grant = resp->grant;
  3209. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  3210. kfree(resp);
  3211. kfree(req);
  3212. return 0;
  3213. out:
  3214. kfree(resp);
  3215. kfree(req);
  3216. return ret;
  3217. }
  3218. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  3219. {
  3220. int ret;
  3221. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  3222. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  3223. struct qmi_txn txn;
  3224. if (!plat_priv)
  3225. return -ENODEV;
  3226. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  3227. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3228. if (!req)
  3229. return -ENOMEM;
  3230. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3231. if (!resp) {
  3232. kfree(req);
  3233. return -ENOMEM;
  3234. }
  3235. req->antenna = plat_priv->antenna;
  3236. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3237. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  3238. if (ret < 0) {
  3239. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  3240. ret);
  3241. goto out;
  3242. }
  3243. ret = qmi_send_request
  3244. (&plat_priv->coex_qmi, NULL, &txn,
  3245. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  3246. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  3247. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  3248. if (ret < 0) {
  3249. qmi_txn_cancel(&txn);
  3250. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  3251. ret);
  3252. goto out;
  3253. }
  3254. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3255. if (ret < 0) {
  3256. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  3257. ret);
  3258. goto out;
  3259. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3260. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  3261. resp->resp.result, resp->resp.error);
  3262. ret = -resp->resp.result;
  3263. goto out;
  3264. }
  3265. kfree(resp);
  3266. kfree(req);
  3267. return 0;
  3268. out:
  3269. kfree(resp);
  3270. kfree(req);
  3271. return ret;
  3272. }
  3273. int cnss_send_subsys_restart_level_msg(struct cnss_plat_data *plat_priv)
  3274. {
  3275. int ret;
  3276. struct wlfw_subsys_restart_level_req_msg_v01 req;
  3277. struct wlfw_subsys_restart_level_resp_msg_v01 resp;
  3278. u8 pcss_enabled;
  3279. if (!plat_priv)
  3280. return -ENODEV;
  3281. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3282. cnss_pr_dbg("Can't send pcss cmd before fw ready\n");
  3283. return 0;
  3284. }
  3285. pcss_enabled = plat_priv->recovery_pcss_enabled;
  3286. cnss_pr_dbg("Sending pcss recovery status: %d\n", pcss_enabled);
  3287. req.restart_level_type_valid = 1;
  3288. req.restart_level_type = pcss_enabled;
  3289. ret = qmi_send_wait(&plat_priv->qmi_wlfw, &req, &resp,
  3290. wlfw_subsys_restart_level_req_msg_v01_ei,
  3291. wlfw_subsys_restart_level_resp_msg_v01_ei,
  3292. QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01,
  3293. WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN,
  3294. QMI_WLFW_TIMEOUT_JF);
  3295. if (ret < 0)
  3296. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  3297. return ret;
  3298. }
  3299. static int coex_new_server(struct qmi_handle *qmi,
  3300. struct qmi_service *service)
  3301. {
  3302. struct cnss_plat_data *plat_priv =
  3303. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3304. struct sockaddr_qrtr sq = { 0 };
  3305. int ret = 0;
  3306. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  3307. service->node, service->port);
  3308. sq.sq_family = AF_QIPCRTR;
  3309. sq.sq_node = service->node;
  3310. sq.sq_port = service->port;
  3311. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3312. if (ret < 0) {
  3313. cnss_pr_err("Fail to connect to remote service port\n");
  3314. return ret;
  3315. }
  3316. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3317. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  3318. plat_priv->driver_state);
  3319. return 0;
  3320. }
  3321. static void coex_del_server(struct qmi_handle *qmi,
  3322. struct qmi_service *service)
  3323. {
  3324. struct cnss_plat_data *plat_priv =
  3325. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3326. cnss_pr_dbg("COEX server exit\n");
  3327. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3328. }
  3329. static struct qmi_ops coex_qmi_ops = {
  3330. .new_server = coex_new_server,
  3331. .del_server = coex_del_server,
  3332. };
  3333. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  3334. { int ret;
  3335. ret = qmi_handle_init(&plat_priv->coex_qmi,
  3336. COEX_SERVICE_MAX_MSG_LEN,
  3337. &coex_qmi_ops, NULL);
  3338. if (ret < 0)
  3339. return ret;
  3340. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  3341. COEX_SERVICE_VERS_V01, 0);
  3342. return ret;
  3343. }
  3344. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  3345. {
  3346. qmi_handle_release(&plat_priv->coex_qmi);
  3347. }
  3348. /* IMS Service */
  3349. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  3350. {
  3351. int ret;
  3352. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  3353. struct qmi_txn *txn;
  3354. if (!plat_priv)
  3355. return -ENODEV;
  3356. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  3357. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3358. if (!req)
  3359. return -ENOMEM;
  3360. req->wfc_call_status_valid = 1;
  3361. req->wfc_call_status = 1;
  3362. txn = &plat_priv->txn;
  3363. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  3364. if (ret < 0) {
  3365. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  3366. ret);
  3367. goto out;
  3368. }
  3369. ret = qmi_send_request
  3370. (&plat_priv->ims_qmi, NULL, txn,
  3371. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3372. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  3373. ims_private_service_subscribe_ind_req_msg_v01_ei, req);
  3374. if (ret < 0) {
  3375. qmi_txn_cancel(txn);
  3376. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  3377. ret);
  3378. goto out;
  3379. }
  3380. kfree(req);
  3381. return 0;
  3382. out:
  3383. kfree(req);
  3384. return ret;
  3385. }
  3386. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  3387. struct sockaddr_qrtr *sq,
  3388. struct qmi_txn *txn,
  3389. const void *data)
  3390. {
  3391. const
  3392. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  3393. data;
  3394. cnss_pr_dbg("Received IMS subscribe indication response\n");
  3395. if (!txn) {
  3396. cnss_pr_err("spurious response\n");
  3397. return;
  3398. }
  3399. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3400. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  3401. resp->resp.result, resp->resp.error);
  3402. txn->result = -resp->resp.result;
  3403. }
  3404. }
  3405. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  3406. void *data)
  3407. {
  3408. int ret;
  3409. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3410. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  3411. kfree(data);
  3412. return ret;
  3413. }
  3414. static void
  3415. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  3416. struct sockaddr_qrtr *sq,
  3417. struct qmi_txn *txn, const void *data)
  3418. {
  3419. struct cnss_plat_data *plat_priv =
  3420. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  3421. const
  3422. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3423. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  3424. if (!txn) {
  3425. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  3426. return;
  3427. }
  3428. if (!ind_msg) {
  3429. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  3430. return;
  3431. }
  3432. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  3433. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  3434. ind_msg->all_wfc_calls_held,
  3435. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  3436. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  3437. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  3438. ind_msg->media_quality_valid, ind_msg->media_quality);
  3439. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  3440. if (!event_data)
  3441. return;
  3442. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  3443. 0, event_data);
  3444. }
  3445. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  3446. {
  3447. .type = QMI_RESPONSE,
  3448. .msg_id =
  3449. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3450. .ei =
  3451. ims_private_service_subscribe_ind_rsp_msg_v01_ei,
  3452. .decoded_size = sizeof(struct
  3453. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  3454. .fn = ims_subscribe_for_indication_resp_cb
  3455. },
  3456. {
  3457. .type = QMI_INDICATION,
  3458. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  3459. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  3460. .decoded_size =
  3461. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  3462. .fn = cnss_ims_process_wfc_call_ind_cb
  3463. },
  3464. {}
  3465. };
  3466. static int ims_new_server(struct qmi_handle *qmi,
  3467. struct qmi_service *service)
  3468. {
  3469. struct cnss_plat_data *plat_priv =
  3470. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3471. struct sockaddr_qrtr sq = { 0 };
  3472. int ret = 0;
  3473. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  3474. service->node, service->port);
  3475. sq.sq_family = AF_QIPCRTR;
  3476. sq.sq_node = service->node;
  3477. sq.sq_port = service->port;
  3478. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3479. if (ret < 0) {
  3480. cnss_pr_err("Fail to connect to remote service port\n");
  3481. return ret;
  3482. }
  3483. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3484. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  3485. plat_priv->driver_state);
  3486. ret = ims_subscribe_for_indication_send_async(plat_priv);
  3487. return ret;
  3488. }
  3489. static void ims_del_server(struct qmi_handle *qmi,
  3490. struct qmi_service *service)
  3491. {
  3492. struct cnss_plat_data *plat_priv =
  3493. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3494. cnss_pr_dbg("IMS server exit\n");
  3495. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3496. }
  3497. static struct qmi_ops ims_qmi_ops = {
  3498. .new_server = ims_new_server,
  3499. .del_server = ims_del_server,
  3500. };
  3501. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  3502. { int ret;
  3503. ret = qmi_handle_init(&plat_priv->ims_qmi,
  3504. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  3505. &ims_qmi_ops, qmi_ims_msg_handlers);
  3506. if (ret < 0)
  3507. return ret;
  3508. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  3509. IMSPRIVATE_SERVICE_VERS_V01, 0);
  3510. return ret;
  3511. }
  3512. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  3513. {
  3514. qmi_handle_release(&plat_priv->ims_qmi);
  3515. }