debug.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <linux/err.h>
  5. #include <linux/seq_file.h>
  6. #include <linux/debugfs.h>
  7. #include "main.h"
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "pci.h"
  11. #define MMIO_REG_ACCESS_MEM_TYPE 0xFF
  12. #define MMIO_REG_RAW_ACCESS_MEM_TYPE 0xFE
  13. #define DEFAULT_KERNEL_LOG_LEVEL INFO_LOG
  14. #define DEFAULT_IPC_LOG_LEVEL DEBUG_LOG
  15. enum log_level cnss_kernel_log_level = DEFAULT_KERNEL_LOG_LEVEL;
  16. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  17. void *cnss_ipc_log_context;
  18. void *cnss_ipc_log_long_context;
  19. enum log_level cnss_ipc_log_level = DEFAULT_IPC_LOG_LEVEL;
  20. static int cnss_set_ipc_log_level(u32 val)
  21. {
  22. if (val < MAX_LOG) {
  23. cnss_ipc_log_level = val;
  24. return 0;
  25. }
  26. return -EINVAL;
  27. }
  28. static u32 cnss_get_ipc_log_level(void)
  29. {
  30. return cnss_ipc_log_level;
  31. }
  32. #else
  33. static int cnss_set_ipc_log_level(int val) { return -EINVAL; }
  34. static u32 cnss_get_ipc_log_level(void) { return MAX_LOG; }
  35. #endif
  36. static int cnss_pin_connect_show(struct seq_file *s, void *data)
  37. {
  38. struct cnss_plat_data *cnss_priv = s->private;
  39. seq_puts(s, "Pin connect results\n");
  40. seq_printf(s, "FW power pin result: %04x\n",
  41. cnss_priv->pin_result.fw_pwr_pin_result);
  42. seq_printf(s, "FW PHY IO pin result: %04x\n",
  43. cnss_priv->pin_result.fw_phy_io_pin_result);
  44. seq_printf(s, "FW RF pin result: %04x\n",
  45. cnss_priv->pin_result.fw_rf_pin_result);
  46. seq_printf(s, "Host pin result: %04x\n",
  47. cnss_priv->pin_result.host_pin_result);
  48. seq_puts(s, "\n");
  49. return 0;
  50. }
  51. static int cnss_pin_connect_open(struct inode *inode, struct file *file)
  52. {
  53. return single_open(file, cnss_pin_connect_show, inode->i_private);
  54. }
  55. static const struct file_operations cnss_pin_connect_fops = {
  56. .read = seq_read,
  57. .release = single_release,
  58. .open = cnss_pin_connect_open,
  59. .owner = THIS_MODULE,
  60. .llseek = seq_lseek,
  61. };
  62. static u64 cnss_get_serial_id(struct cnss_plat_data *plat_priv)
  63. {
  64. u32 msb = plat_priv->serial_id.serial_id_msb;
  65. u32 lsb = plat_priv->serial_id.serial_id_lsb;
  66. msb &= 0xFFFF;
  67. return (((u64)msb << 32) | lsb);
  68. }
  69. static int cnss_stats_show_state(struct seq_file *s,
  70. struct cnss_plat_data *plat_priv)
  71. {
  72. enum cnss_driver_state i;
  73. int skip = 0;
  74. unsigned long state;
  75. seq_printf(s, "\nSerial Number: 0x%lx", cnss_get_serial_id(plat_priv));
  76. seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state);
  77. for (i = 0, state = plat_priv->driver_state; state != 0;
  78. state >>= 1, i++) {
  79. if (!(state & 0x1))
  80. continue;
  81. if (skip++)
  82. seq_puts(s, " | ");
  83. switch (i) {
  84. case CNSS_QMI_WLFW_CONNECTED:
  85. seq_puts(s, "QMI_WLFW_CONNECTED");
  86. continue;
  87. case CNSS_FW_MEM_READY:
  88. seq_puts(s, "FW_MEM_READY");
  89. continue;
  90. case CNSS_FW_READY:
  91. seq_puts(s, "FW_READY");
  92. continue;
  93. case CNSS_IN_COLD_BOOT_CAL:
  94. seq_puts(s, "IN_COLD_BOOT_CAL");
  95. continue;
  96. case CNSS_DRIVER_LOADING:
  97. seq_puts(s, "DRIVER_LOADING");
  98. continue;
  99. case CNSS_DRIVER_UNLOADING:
  100. seq_puts(s, "DRIVER_UNLOADING");
  101. continue;
  102. case CNSS_DRIVER_IDLE_RESTART:
  103. seq_puts(s, "IDLE_RESTART");
  104. continue;
  105. case CNSS_DRIVER_IDLE_SHUTDOWN:
  106. seq_puts(s, "IDLE_SHUTDOWN");
  107. continue;
  108. case CNSS_DRIVER_PROBED:
  109. seq_puts(s, "DRIVER_PROBED");
  110. continue;
  111. case CNSS_DRIVER_RECOVERY:
  112. seq_puts(s, "DRIVER_RECOVERY");
  113. continue;
  114. case CNSS_FW_BOOT_RECOVERY:
  115. seq_puts(s, "FW_BOOT_RECOVERY");
  116. continue;
  117. case CNSS_DEV_ERR_NOTIFY:
  118. seq_puts(s, "DEV_ERR");
  119. continue;
  120. case CNSS_DRIVER_DEBUG:
  121. seq_puts(s, "DRIVER_DEBUG");
  122. continue;
  123. case CNSS_COEX_CONNECTED:
  124. seq_puts(s, "COEX_CONNECTED");
  125. continue;
  126. case CNSS_IMS_CONNECTED:
  127. seq_puts(s, "IMS_CONNECTED");
  128. continue;
  129. case CNSS_IN_SUSPEND_RESUME:
  130. seq_puts(s, "IN_SUSPEND_RESUME");
  131. continue;
  132. case CNSS_IN_REBOOT:
  133. seq_puts(s, "IN_REBOOT");
  134. continue;
  135. case CNSS_COLD_BOOT_CAL_DONE:
  136. seq_puts(s, "COLD_BOOT_CAL_DONE");
  137. continue;
  138. case CNSS_IN_PANIC:
  139. seq_puts(s, "IN_PANIC");
  140. continue;
  141. case CNSS_QMI_DEL_SERVER:
  142. seq_puts(s, "DEL_SERVER_IN_PROGRESS");
  143. continue;
  144. case CNSS_QMI_DMS_CONNECTED:
  145. seq_puts(s, "DMS_CONNECTED");
  146. continue;
  147. case CNSS_DMS_DEL_SERVER:
  148. seq_puts(s, "DMS_DEL_SERVER");
  149. continue;
  150. case CNSS_DAEMON_CONNECTED:
  151. seq_puts(s, "DAEMON_CONNECTED");
  152. continue;
  153. case CNSS_PCI_PROBE_DONE:
  154. seq_puts(s, "PCI PROBE DONE");
  155. continue;
  156. case CNSS_DRIVER_REGISTER:
  157. seq_puts(s, "DRIVER REGISTERED");
  158. continue;
  159. case CNSS_WLAN_HW_DISABLED:
  160. seq_puts(s, "WLAN HW DISABLED");
  161. continue;
  162. case CNSS_FS_READY:
  163. seq_puts(s, "FS READY");
  164. continue;
  165. case CNSS_DRIVER_REGISTERED:
  166. seq_puts(s, "DRIVER REGISTERED");
  167. continue;
  168. case CNSS_POWER_OFF:
  169. seq_puts(s, "POWER OFF");
  170. continue;
  171. }
  172. seq_printf(s, "UNKNOWN-%d", i);
  173. }
  174. seq_puts(s, ")\n");
  175. return 0;
  176. }
  177. static int cnss_stats_show_gpio_state(struct seq_file *s,
  178. struct cnss_plat_data *plat_priv)
  179. {
  180. seq_printf(s, "\nHost SOL: %d", cnss_get_host_sol_value(plat_priv));
  181. seq_printf(s, "\nDev SOL: %d", cnss_get_dev_sol_value(plat_priv));
  182. return 0;
  183. }
  184. static int cnss_stats_show(struct seq_file *s, void *data)
  185. {
  186. struct cnss_plat_data *plat_priv = s->private;
  187. cnss_stats_show_state(s, plat_priv);
  188. cnss_stats_show_gpio_state(s, plat_priv);
  189. return 0;
  190. }
  191. static int cnss_stats_open(struct inode *inode, struct file *file)
  192. {
  193. return single_open(file, cnss_stats_show, inode->i_private);
  194. }
  195. static const struct file_operations cnss_stats_fops = {
  196. .read = seq_read,
  197. .release = single_release,
  198. .open = cnss_stats_open,
  199. .owner = THIS_MODULE,
  200. .llseek = seq_lseek,
  201. };
  202. static ssize_t cnss_dev_boot_debug_write(struct file *fp,
  203. const char __user *user_buf,
  204. size_t count, loff_t *off)
  205. {
  206. struct cnss_plat_data *plat_priv =
  207. ((struct seq_file *)fp->private_data)->private;
  208. struct cnss_pci_data *pci_priv;
  209. char buf[64];
  210. char *cmd;
  211. unsigned int len = 0;
  212. char *sptr, *token;
  213. const char *delim = " ";
  214. int ret = 0;
  215. if (!plat_priv)
  216. return -ENODEV;
  217. len = min(count, sizeof(buf) - 1);
  218. if (copy_from_user(buf, user_buf, len))
  219. return -EFAULT;
  220. buf[len] = '\0';
  221. sptr = buf;
  222. token = strsep(&sptr, delim);
  223. if (!token)
  224. return -EINVAL;
  225. cmd = token;
  226. cnss_pr_dbg("Received dev_boot debug command: %s\n", cmd);
  227. if (sysfs_streq(cmd, "on")) {
  228. ret = cnss_power_on_device(plat_priv, false);
  229. } else if (sysfs_streq(cmd, "off")) {
  230. cnss_power_off_device(plat_priv);
  231. } else if (sysfs_streq(cmd, "enumerate")) {
  232. ret = cnss_pci_init(plat_priv);
  233. } else if (sysfs_streq(cmd, "powerup")) {
  234. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  235. ret = cnss_driver_event_post(plat_priv,
  236. CNSS_DRIVER_EVENT_POWER_UP,
  237. CNSS_EVENT_SYNC, NULL);
  238. } else if (sysfs_streq(cmd, "shutdown")) {
  239. ret = cnss_driver_event_post(plat_priv,
  240. CNSS_DRIVER_EVENT_POWER_DOWN,
  241. 0, NULL);
  242. clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  243. } else if (sysfs_streq(cmd, "assert_host_sol")) {
  244. pci_priv = plat_priv->bus_priv;
  245. cnss_auto_resume(&pci_priv->pci_dev->dev);
  246. ret = cnss_set_host_sol_value(plat_priv, 1);
  247. } else if (sysfs_streq(cmd, "deassert_host_sol")) {
  248. ret = cnss_set_host_sol_value(plat_priv, 0);
  249. } else if (sysfs_streq(cmd, "pdc_update")) {
  250. if (!sptr)
  251. return -EINVAL;
  252. ret = cnss_aop_send_msg(plat_priv, sptr);
  253. } else if (sysfs_streq(cmd, "dev_check")) {
  254. cnss_wlan_hw_disable_check(plat_priv);
  255. } else if (sysfs_streq(cmd, "dev_enable")) {
  256. cnss_wlan_hw_enable();
  257. } else {
  258. pci_priv = plat_priv->bus_priv;
  259. if (!pci_priv)
  260. return -ENODEV;
  261. if (sysfs_streq(cmd, "download")) {
  262. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  263. ret = cnss_pci_start_mhi(pci_priv);
  264. } else if (sysfs_streq(cmd, "linkup")) {
  265. ret = cnss_resume_pci_link(pci_priv);
  266. } else if (sysfs_streq(cmd, "linkdown")) {
  267. ret = cnss_suspend_pci_link(pci_priv);
  268. } else if (sysfs_streq(cmd, "assert")) {
  269. cnss_pr_info("FW Assert triggered for debug\n");
  270. ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev);
  271. } else if (sysfs_streq(cmd, "set_cbc_done")) {
  272. cnss_pr_dbg("Force set cold boot cal done status\n");
  273. set_bit(CNSS_COLD_BOOT_CAL_DONE,
  274. &plat_priv->driver_state);
  275. } else {
  276. cnss_pr_err("Device boot debugfs command is invalid\n");
  277. ret = -EINVAL;
  278. }
  279. }
  280. if (ret < 0)
  281. return ret;
  282. return count;
  283. }
  284. static int cnss_dev_boot_debug_show(struct seq_file *s, void *data)
  285. {
  286. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/dev_boot\n");
  287. seq_puts(s, "<action> can be one of below:\n");
  288. seq_puts(s, "on: turn on device power, assert WLAN_EN\n");
  289. seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n");
  290. seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n");
  291. seq_puts(s, "download: download FW and do QMI handshake with FW\n");
  292. seq_puts(s, "linkup: bring up PCIe link\n");
  293. seq_puts(s, "linkdown: bring down PCIe link\n");
  294. seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n");
  295. seq_puts(s, "shutdown: full power off sequence to shutdown device\n");
  296. seq_puts(s, "assert: trigger firmware assert\n");
  297. seq_puts(s, "set_cbc_done: Set cold boot calibration done status\n");
  298. seq_puts(s, "\npdc_update usage:");
  299. seq_puts(s, "1. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: <vreg>.<mode>, <seq>: <val>} > <debugfs_path>/cnss/dev_boot\n");
  300. seq_puts(s, "2. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: pdc, enable: <val>} > <debugfs_path>/cnss/dev_boot\n");
  301. seq_puts(s, "assert_host_sol: Assert host sol\n");
  302. seq_puts(s, "deassert_host_sol: Deassert host sol\n");
  303. seq_puts(s, "dev_check: Check whether HW is disabled or not\n");
  304. seq_puts(s, "dev_enable: Enable HW\n");
  305. return 0;
  306. }
  307. static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file)
  308. {
  309. return single_open(file, cnss_dev_boot_debug_show, inode->i_private);
  310. }
  311. static const struct file_operations cnss_dev_boot_debug_fops = {
  312. .read = seq_read,
  313. .write = cnss_dev_boot_debug_write,
  314. .release = single_release,
  315. .open = cnss_dev_boot_debug_open,
  316. .owner = THIS_MODULE,
  317. .llseek = seq_lseek,
  318. };
  319. static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
  320. {
  321. struct cnss_plat_data *plat_priv = s->private;
  322. mutex_lock(&plat_priv->dev_lock);
  323. if (!plat_priv->diag_reg_read_buf) {
  324. seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
  325. seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
  326. seq_puts(s, "Use mem_type = 0xfe for register read by raw IO access which skips sanity checks, data_len will be ignored\n");
  327. seq_puts(s, "Use other mem_type for register read by QMI\n");
  328. mutex_unlock(&plat_priv->dev_lock);
  329. return 0;
  330. }
  331. seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n",
  332. plat_priv->diag_reg_read_addr,
  333. plat_priv->diag_reg_read_mem_type,
  334. plat_priv->diag_reg_read_len);
  335. seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4,
  336. plat_priv->diag_reg_read_buf,
  337. plat_priv->diag_reg_read_len, false);
  338. plat_priv->diag_reg_read_len = 0;
  339. kfree(plat_priv->diag_reg_read_buf);
  340. plat_priv->diag_reg_read_buf = NULL;
  341. mutex_unlock(&plat_priv->dev_lock);
  342. return 0;
  343. }
  344. static ssize_t cnss_reg_read_debug_write(struct file *fp,
  345. const char __user *user_buf,
  346. size_t count, loff_t *off)
  347. {
  348. struct cnss_plat_data *plat_priv =
  349. ((struct seq_file *)fp->private_data)->private;
  350. char buf[64];
  351. char *sptr, *token;
  352. unsigned int len = 0;
  353. u32 reg_offset, mem_type;
  354. u32 data_len = 0, reg_val = 0;
  355. u8 *reg_buf = NULL;
  356. const char *delim = " ";
  357. int ret = 0;
  358. len = min(count, sizeof(buf) - 1);
  359. if (copy_from_user(buf, user_buf, len))
  360. return -EFAULT;
  361. buf[len] = '\0';
  362. sptr = buf;
  363. token = strsep(&sptr, delim);
  364. if (!token)
  365. return -EINVAL;
  366. if (!sptr)
  367. return -EINVAL;
  368. if (kstrtou32(token, 0, &mem_type))
  369. return -EINVAL;
  370. token = strsep(&sptr, delim);
  371. if (!token)
  372. return -EINVAL;
  373. if (!sptr)
  374. return -EINVAL;
  375. if (kstrtou32(token, 0, &reg_offset))
  376. return -EINVAL;
  377. token = strsep(&sptr, delim);
  378. if (!token)
  379. return -EINVAL;
  380. if (kstrtou32(token, 0, &data_len))
  381. return -EINVAL;
  382. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  383. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  384. ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val,
  385. mem_type ==
  386. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  387. if (ret)
  388. return ret;
  389. cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
  390. reg_offset);
  391. return count;
  392. }
  393. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  394. cnss_pr_err("Firmware is not ready yet\n");
  395. return -EINVAL;
  396. }
  397. mutex_lock(&plat_priv->dev_lock);
  398. kfree(plat_priv->diag_reg_read_buf);
  399. plat_priv->diag_reg_read_buf = NULL;
  400. reg_buf = kzalloc(data_len, GFP_KERNEL);
  401. if (!reg_buf) {
  402. mutex_unlock(&plat_priv->dev_lock);
  403. return -ENOMEM;
  404. }
  405. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset,
  406. mem_type, data_len,
  407. reg_buf);
  408. if (ret) {
  409. kfree(reg_buf);
  410. mutex_unlock(&plat_priv->dev_lock);
  411. return ret;
  412. }
  413. plat_priv->diag_reg_read_addr = reg_offset;
  414. plat_priv->diag_reg_read_mem_type = mem_type;
  415. plat_priv->diag_reg_read_len = data_len;
  416. plat_priv->diag_reg_read_buf = reg_buf;
  417. mutex_unlock(&plat_priv->dev_lock);
  418. return count;
  419. }
  420. static int cnss_reg_read_debug_open(struct inode *inode, struct file *file)
  421. {
  422. return single_open(file, cnss_reg_read_debug_show, inode->i_private);
  423. }
  424. static const struct file_operations cnss_reg_read_debug_fops = {
  425. .read = seq_read,
  426. .write = cnss_reg_read_debug_write,
  427. .open = cnss_reg_read_debug_open,
  428. .owner = THIS_MODULE,
  429. .llseek = seq_lseek,
  430. };
  431. static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
  432. {
  433. seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
  434. seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
  435. seq_puts(s, "Use mem_type = 0xfe for register write by raw IO access which skips sanity checks\n");
  436. seq_puts(s, "Use other mem_type for register write by QMI\n");
  437. return 0;
  438. }
  439. static ssize_t cnss_reg_write_debug_write(struct file *fp,
  440. const char __user *user_buf,
  441. size_t count, loff_t *off)
  442. {
  443. struct cnss_plat_data *plat_priv =
  444. ((struct seq_file *)fp->private_data)->private;
  445. char buf[64];
  446. char *sptr, *token;
  447. unsigned int len = 0;
  448. u32 reg_offset, mem_type, reg_val;
  449. const char *delim = " ";
  450. int ret = 0;
  451. len = min(count, sizeof(buf) - 1);
  452. if (copy_from_user(buf, user_buf, len))
  453. return -EFAULT;
  454. buf[len] = '\0';
  455. sptr = buf;
  456. token = strsep(&sptr, delim);
  457. if (!token)
  458. return -EINVAL;
  459. if (!sptr)
  460. return -EINVAL;
  461. if (kstrtou32(token, 0, &mem_type))
  462. return -EINVAL;
  463. token = strsep(&sptr, delim);
  464. if (!token)
  465. return -EINVAL;
  466. if (!sptr)
  467. return -EINVAL;
  468. if (kstrtou32(token, 0, &reg_offset))
  469. return -EINVAL;
  470. token = strsep(&sptr, delim);
  471. if (!token)
  472. return -EINVAL;
  473. if (kstrtou32(token, 0, &reg_val))
  474. return -EINVAL;
  475. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  476. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  477. ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val,
  478. mem_type ==
  479. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  480. if (ret)
  481. return ret;
  482. cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
  483. reg_offset);
  484. return count;
  485. }
  486. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  487. cnss_pr_err("Firmware is not ready yet\n");
  488. return -EINVAL;
  489. }
  490. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
  491. sizeof(u32),
  492. (u8 *)&reg_val);
  493. if (ret)
  494. return ret;
  495. return count;
  496. }
  497. static int cnss_reg_write_debug_open(struct inode *inode, struct file *file)
  498. {
  499. return single_open(file, cnss_reg_write_debug_show, inode->i_private);
  500. }
  501. static const struct file_operations cnss_reg_write_debug_fops = {
  502. .read = seq_read,
  503. .write = cnss_reg_write_debug_write,
  504. .open = cnss_reg_write_debug_open,
  505. .owner = THIS_MODULE,
  506. .llseek = seq_lseek,
  507. };
  508. static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
  509. const char __user *user_buf,
  510. size_t count, loff_t *off)
  511. {
  512. struct cnss_plat_data *plat_priv =
  513. ((struct seq_file *)fp->private_data)->private;
  514. struct cnss_pci_data *pci_priv;
  515. char buf[64];
  516. char *cmd;
  517. unsigned int len = 0;
  518. int ret = 0;
  519. if (!plat_priv)
  520. return -ENODEV;
  521. pci_priv = plat_priv->bus_priv;
  522. if (!pci_priv)
  523. return -ENODEV;
  524. len = min(count, sizeof(buf) - 1);
  525. if (copy_from_user(buf, user_buf, len))
  526. return -EFAULT;
  527. buf[len] = '\0';
  528. cmd = buf;
  529. cnss_pr_dbg("Received runtime_pm debug command: %s\n", cmd);
  530. if (sysfs_streq(cmd, "usage_count")) {
  531. cnss_pci_pm_runtime_show_usage_count(pci_priv);
  532. } else if (sysfs_streq(cmd, "request_resume")) {
  533. ret = cnss_pci_pm_request_resume(pci_priv);
  534. } else if (sysfs_streq(cmd, "resume")) {
  535. ret = cnss_pci_pm_runtime_resume(pci_priv);
  536. } else if (sysfs_streq(cmd, "get")) {
  537. ret = cnss_pci_pm_runtime_get(pci_priv, RTPM_ID_CNSS);
  538. } else if (sysfs_streq(cmd, "get_noresume")) {
  539. cnss_pci_pm_runtime_get_noresume(pci_priv, RTPM_ID_CNSS);
  540. } else if (sysfs_streq(cmd, "put_autosuspend")) {
  541. ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv,
  542. RTPM_ID_CNSS);
  543. } else if (sysfs_streq(cmd, "put_noidle")) {
  544. cnss_pci_pm_runtime_put_noidle(pci_priv, RTPM_ID_CNSS);
  545. } else if (sysfs_streq(cmd, "mark_last_busy")) {
  546. cnss_pci_pm_runtime_mark_last_busy(pci_priv);
  547. } else if (sysfs_streq(cmd, "resume_bus")) {
  548. cnss_pci_resume_bus(pci_priv);
  549. } else if (sysfs_streq(cmd, "suspend_bus")) {
  550. cnss_pci_suspend_bus(pci_priv);
  551. } else {
  552. cnss_pr_err("Runtime PM debugfs command is invalid\n");
  553. ret = -EINVAL;
  554. }
  555. if (ret < 0)
  556. return ret;
  557. return count;
  558. }
  559. static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
  560. {
  561. struct cnss_plat_data *plat_priv = s->private;
  562. struct cnss_pci_data *pci_priv;
  563. int i;
  564. if (!plat_priv)
  565. return -ENODEV;
  566. pci_priv = plat_priv->bus_priv;
  567. if (!pci_priv)
  568. return -ENODEV;
  569. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
  570. seq_puts(s, "<action> can be one of below:\n");
  571. seq_puts(s, "usage_count: get runtime PM usage count\n");
  572. seq_puts(s, "reques_resume: do async runtime PM resume\n");
  573. seq_puts(s, "resume: do sync runtime PM resume\n");
  574. seq_puts(s, "get: do runtime PM get\n");
  575. seq_puts(s, "get_noresume: do runtime PM get noresume\n");
  576. seq_puts(s, "put_noidle: do runtime PM put noidle\n");
  577. seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
  578. seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
  579. seq_puts(s, "resume_bus: do bus resume only\n");
  580. seq_puts(s, "suspend_bus: do bus suspend only\n");
  581. seq_puts(s, "\nStats:\n");
  582. seq_printf(s, "%s: %u\n", "get count",
  583. atomic_read(&pci_priv->pm_stats.runtime_get));
  584. seq_printf(s, "%s: %u\n", "put count",
  585. atomic_read(&pci_priv->pm_stats.runtime_put));
  586. seq_printf(s, "%-10s%-10s%-10s%-15s%-15s\n",
  587. "id:", "get", "put", "get time(us)", "put time(us)");
  588. for (i = 0; i < RTPM_ID_MAX; i++) {
  589. seq_printf(s, "%d%-9s", i, ":");
  590. seq_printf(s, "%-10d",
  591. atomic_read(&pci_priv->pm_stats.runtime_get_id[i]));
  592. seq_printf(s, "%-10d",
  593. atomic_read(&pci_priv->pm_stats.runtime_put_id[i]));
  594. seq_printf(s, "%-15llu",
  595. pci_priv->pm_stats.runtime_get_timestamp_id[i]);
  596. seq_printf(s, "%-15llu\n",
  597. pci_priv->pm_stats.runtime_put_timestamp_id[i]);
  598. }
  599. return 0;
  600. }
  601. static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file)
  602. {
  603. return single_open(file, cnss_runtime_pm_debug_show, inode->i_private);
  604. }
  605. static const struct file_operations cnss_runtime_pm_debug_fops = {
  606. .read = seq_read,
  607. .write = cnss_runtime_pm_debug_write,
  608. .open = cnss_runtime_pm_debug_open,
  609. .owner = THIS_MODULE,
  610. .llseek = seq_lseek,
  611. };
  612. static int process_drv(struct cnss_plat_data *plat_priv, bool enabled)
  613. {
  614. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  615. cnss_pr_err("DRV cmd must be used before QMI ready\n");
  616. return -EINVAL;
  617. }
  618. enabled ? cnss_set_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01) :
  619. cnss_clear_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01);
  620. cnss_pr_info("%s DRV suspend\n", enabled ? "enable" : "disable");
  621. return 0;
  622. }
  623. static int process_quirks(struct cnss_plat_data *plat_priv, u32 val)
  624. {
  625. enum cnss_debug_quirks i;
  626. int ret = 0;
  627. unsigned long state;
  628. unsigned long quirks = 0;
  629. for (i = 0, state = val; i < QUIRK_MAX_VALUE; state >>= 1, i++) {
  630. switch (i) {
  631. case DISABLE_DRV:
  632. ret = process_drv(plat_priv, !(state & 0x1));
  633. if (!ret)
  634. quirks |= (state & 0x1) << i;
  635. continue;
  636. default:
  637. quirks |= (state & 0x1) << i;
  638. continue;
  639. }
  640. }
  641. plat_priv->ctrl_params.quirks = quirks;
  642. return 0;
  643. }
  644. static ssize_t cnss_control_params_debug_write(struct file *fp,
  645. const char __user *user_buf,
  646. size_t count, loff_t *off)
  647. {
  648. struct cnss_plat_data *plat_priv =
  649. ((struct seq_file *)fp->private_data)->private;
  650. char buf[64];
  651. char *sptr, *token;
  652. char *cmd;
  653. u32 val;
  654. unsigned int len = 0;
  655. const char *delim = " ";
  656. if (!plat_priv)
  657. return -ENODEV;
  658. len = min(count, sizeof(buf) - 1);
  659. if (copy_from_user(buf, user_buf, len))
  660. return -EFAULT;
  661. buf[len] = '\0';
  662. sptr = buf;
  663. token = strsep(&sptr, delim);
  664. if (!token)
  665. return -EINVAL;
  666. if (!sptr)
  667. return -EINVAL;
  668. cmd = token;
  669. token = strsep(&sptr, delim);
  670. if (!token)
  671. return -EINVAL;
  672. if (kstrtou32(token, 0, &val))
  673. return -EINVAL;
  674. if (strcmp(cmd, "quirks") == 0)
  675. process_quirks(plat_priv, val);
  676. else if (strcmp(cmd, "mhi_timeout") == 0)
  677. plat_priv->ctrl_params.mhi_timeout = val;
  678. else if (strcmp(cmd, "mhi_m2_timeout") == 0)
  679. plat_priv->ctrl_params.mhi_m2_timeout = val;
  680. else if (strcmp(cmd, "qmi_timeout") == 0)
  681. plat_priv->ctrl_params.qmi_timeout = val;
  682. else if (strcmp(cmd, "bdf_type") == 0)
  683. plat_priv->ctrl_params.bdf_type = val;
  684. else if (strcmp(cmd, "time_sync_period") == 0)
  685. plat_priv->ctrl_params.time_sync_period = val;
  686. else if (strcmp(cmd, "kern_log_level") == 0) {
  687. if (val < MAX_LOG)
  688. cnss_kernel_log_level = val;
  689. } else if (strcmp(cmd, "ipc_log_level") == 0) {
  690. return cnss_set_ipc_log_level(val) ? -EINVAL : count;
  691. } else
  692. return -EINVAL;
  693. return count;
  694. }
  695. static int cnss_show_quirks_state(struct seq_file *s,
  696. struct cnss_plat_data *plat_priv)
  697. {
  698. enum cnss_debug_quirks i;
  699. int skip = 0;
  700. unsigned long state;
  701. seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks);
  702. for (i = 0, state = plat_priv->ctrl_params.quirks;
  703. state != 0; state >>= 1, i++) {
  704. if (!(state & 0x1))
  705. continue;
  706. if (skip++)
  707. seq_puts(s, " | ");
  708. switch (i) {
  709. case LINK_DOWN_SELF_RECOVERY:
  710. seq_puts(s, "LINK_DOWN_SELF_RECOVERY");
  711. continue;
  712. case SKIP_DEVICE_BOOT:
  713. seq_puts(s, "SKIP_DEVICE_BOOT");
  714. continue;
  715. case USE_CORE_ONLY_FW:
  716. seq_puts(s, "USE_CORE_ONLY_FW");
  717. continue;
  718. case SKIP_RECOVERY:
  719. seq_puts(s, "SKIP_RECOVERY");
  720. continue;
  721. case QMI_BYPASS:
  722. seq_puts(s, "QMI_BYPASS");
  723. continue;
  724. case ENABLE_WALTEST:
  725. seq_puts(s, "WALTEST");
  726. continue;
  727. case ENABLE_PCI_LINK_DOWN_PANIC:
  728. seq_puts(s, "PCI_LINK_DOWN_PANIC");
  729. continue;
  730. case FBC_BYPASS:
  731. seq_puts(s, "FBC_BYPASS");
  732. continue;
  733. case ENABLE_DAEMON_SUPPORT:
  734. seq_puts(s, "DAEMON_SUPPORT");
  735. continue;
  736. case DISABLE_DRV:
  737. seq_puts(s, "DISABLE_DRV");
  738. continue;
  739. case DISABLE_IO_COHERENCY:
  740. seq_puts(s, "DISABLE_IO_COHERENCY");
  741. continue;
  742. case IGNORE_PCI_LINK_FAILURE:
  743. seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
  744. continue;
  745. case DISABLE_TIME_SYNC:
  746. seq_puts(s, "DISABLE_TIME_SYNC");
  747. continue;
  748. case FORCE_ONE_MSI:
  749. seq_puts(s, "FORCE_ONE_MSI");
  750. continue;
  751. default:
  752. continue;
  753. }
  754. }
  755. seq_puts(s, ")\n");
  756. return 0;
  757. }
  758. static int cnss_control_params_debug_show(struct seq_file *s, void *data)
  759. {
  760. struct cnss_plat_data *cnss_priv = s->private;
  761. u32 ipc_log_level;
  762. seq_puts(s, "\nUsage: echo <params_name> <value> > <debugfs_path>/cnss/control_params\n");
  763. seq_puts(s, "<params_name> can be one of below:\n");
  764. seq_puts(s, "quirks: Debug quirks for driver\n");
  765. seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n");
  766. seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n");
  767. seq_puts(s, "bdf_type: Type of board data file to be downloaded\n");
  768. seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n");
  769. seq_puts(s, "\nCurrent value:\n");
  770. cnss_show_quirks_state(s, cnss_priv);
  771. seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
  772. seq_printf(s, "mhi_m2_timeout: %u\n",
  773. cnss_priv->ctrl_params.mhi_m2_timeout);
  774. seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
  775. seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
  776. seq_printf(s, "time_sync_period: %u\n",
  777. cnss_priv->ctrl_params.time_sync_period);
  778. seq_printf(s, "kern_log_level: %u\n", cnss_kernel_log_level);
  779. ipc_log_level = cnss_get_ipc_log_level();
  780. if (ipc_log_level != MAX_LOG)
  781. seq_printf(s, "ipc_log_level: %u\n", ipc_log_level);
  782. return 0;
  783. }
  784. static int cnss_control_params_debug_open(struct inode *inode,
  785. struct file *file)
  786. {
  787. return single_open(file, cnss_control_params_debug_show,
  788. inode->i_private);
  789. }
  790. static const struct file_operations cnss_control_params_debug_fops = {
  791. .read = seq_read,
  792. .write = cnss_control_params_debug_write,
  793. .open = cnss_control_params_debug_open,
  794. .owner = THIS_MODULE,
  795. .llseek = seq_lseek,
  796. };
  797. static ssize_t cnss_dynamic_feature_write(struct file *fp,
  798. const char __user *user_buf,
  799. size_t count, loff_t *off)
  800. {
  801. struct cnss_plat_data *plat_priv =
  802. ((struct seq_file *)fp->private_data)->private;
  803. int ret = 0;
  804. u64 val;
  805. ret = kstrtou64_from_user(user_buf, count, 0, &val);
  806. if (ret)
  807. return ret;
  808. plat_priv->dynamic_feature = val;
  809. ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv);
  810. if (ret < 0)
  811. return ret;
  812. return count;
  813. }
  814. static int cnss_dynamic_feature_show(struct seq_file *s, void *data)
  815. {
  816. struct cnss_plat_data *cnss_priv = s->private;
  817. seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature);
  818. return 0;
  819. }
  820. static int cnss_dynamic_feature_open(struct inode *inode,
  821. struct file *file)
  822. {
  823. return single_open(file, cnss_dynamic_feature_show,
  824. inode->i_private);
  825. }
  826. static const struct file_operations cnss_dynamic_feature_fops = {
  827. .read = seq_read,
  828. .write = cnss_dynamic_feature_write,
  829. .open = cnss_dynamic_feature_open,
  830. .owner = THIS_MODULE,
  831. .llseek = seq_lseek,
  832. };
  833. static int cnss_smmu_fault_timestamp_show(struct seq_file *s, void *data)
  834. {
  835. struct cnss_plat_data *plat_priv = s->private;
  836. struct cnss_pci_data *pci_priv = plat_priv->bus_priv;
  837. if (!pci_priv)
  838. return -ENODEV;
  839. seq_printf(s, "smmu irq cb entry timestamp : %llu ns\n",
  840. pci_priv->smmu_fault_timestamp[SMMU_CB_ENTRY]);
  841. seq_printf(s, "smmu irq cb before doorbell ring timestamp : %llu ns\n",
  842. pci_priv->smmu_fault_timestamp[SMMU_CB_DOORBELL_RING]);
  843. seq_printf(s, "smmu irq cb after doorbell ring timestamp : %llu ns\n",
  844. pci_priv->smmu_fault_timestamp[SMMU_CB_EXIT]);
  845. return 0;
  846. }
  847. static int cnss_smmu_fault_timestamp_open(struct inode *inode,
  848. struct file *file)
  849. {
  850. return single_open(file, cnss_smmu_fault_timestamp_show,
  851. inode->i_private);
  852. }
  853. static const struct file_operations cnss_smmu_fault_timestamp_fops = {
  854. .read = seq_read,
  855. .release = single_release,
  856. .open = cnss_smmu_fault_timestamp_open,
  857. .owner = THIS_MODULE,
  858. .llseek = seq_lseek,
  859. };
  860. #ifdef CONFIG_DEBUG_FS
  861. #ifdef CONFIG_CNSS2_DEBUG
  862. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  863. {
  864. struct dentry *root_dentry = plat_priv->root_dentry;
  865. debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv,
  866. &cnss_dev_boot_debug_fops);
  867. debugfs_create_file("reg_read", 0600, root_dentry, plat_priv,
  868. &cnss_reg_read_debug_fops);
  869. debugfs_create_file("reg_write", 0600, root_dentry, plat_priv,
  870. &cnss_reg_write_debug_fops);
  871. debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv,
  872. &cnss_runtime_pm_debug_fops);
  873. debugfs_create_file("control_params", 0600, root_dentry, plat_priv,
  874. &cnss_control_params_debug_fops);
  875. debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv,
  876. &cnss_dynamic_feature_fops);
  877. debugfs_create_file("cnss_smmu_fault_timestamp", 0600, root_dentry,
  878. plat_priv, &cnss_smmu_fault_timestamp_fops);
  879. return 0;
  880. }
  881. #else
  882. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  883. {
  884. return 0;
  885. }
  886. #endif
  887. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  888. {
  889. int ret = 0;
  890. struct dentry *root_dentry;
  891. char name[CNSS_FS_NAME_SIZE];
  892. if (cnss_is_dual_wlan_enabled())
  893. snprintf(name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME "_%d",
  894. plat_priv->plat_idx);
  895. else
  896. snprintf(name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  897. root_dentry = debugfs_create_dir(name, 0);
  898. if (IS_ERR(root_dentry)) {
  899. ret = PTR_ERR(root_dentry);
  900. cnss_pr_err("Unable to create debugfs %d\n", ret);
  901. goto out;
  902. }
  903. plat_priv->root_dentry = root_dentry;
  904. debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv,
  905. &cnss_pin_connect_fops);
  906. debugfs_create_file("stats", 0644, root_dentry, plat_priv,
  907. &cnss_stats_fops);
  908. cnss_create_debug_only_node(plat_priv);
  909. out:
  910. return ret;
  911. }
  912. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  913. {
  914. debugfs_remove_recursive(plat_priv->root_dentry);
  915. }
  916. #else
  917. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  918. {
  919. plat_priv->root_dentry = NULL;
  920. return 0;
  921. }
  922. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  923. {
  924. }
  925. #endif
  926. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  927. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  928. enum log_level kern_log_level,
  929. enum log_level ipc_log_level, char *fmt, ...)
  930. {
  931. struct va_format vaf;
  932. va_list va_args;
  933. va_start(va_args, fmt);
  934. vaf.fmt = fmt;
  935. vaf.va = &va_args;
  936. if (kern_log_level <= cnss_kernel_log_level) {
  937. switch (kern_log_level) {
  938. case EMERG_LOG:
  939. pr_emerg("cnss: %pV", &vaf);
  940. break;
  941. case ALERT_LOG:
  942. pr_alert("cnss: %pV", &vaf);
  943. break;
  944. case CRIT_LOG:
  945. pr_crit("cnss: %pV", &vaf);
  946. break;
  947. case ERR_LOG:
  948. pr_err("cnss: %pV", &vaf);
  949. break;
  950. case WARNING_LOG:
  951. pr_warn("cnss: %pV", &vaf);
  952. break;
  953. case NOTICE_LOG:
  954. pr_notice("cnss: %pV", &vaf);
  955. break;
  956. case INFO_LOG:
  957. pr_info("cnss: %pV", &vaf);
  958. break;
  959. case DEBUG_LOG:
  960. case DEBUG_HI_LOG:
  961. pr_debug("cnss: %pV", &vaf);
  962. break;
  963. default:
  964. break;
  965. }
  966. }
  967. if (ipc_log_level <= cnss_ipc_log_level)
  968. ipc_log_string(log_ctx, "[%s] %s: %pV", process, fn, &vaf);
  969. va_end(va_args);
  970. }
  971. static int cnss_ipc_logging_init(void)
  972. {
  973. cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  974. "cnss", 0);
  975. if (!cnss_ipc_log_context) {
  976. cnss_pr_err("Unable to create IPC log context\n");
  977. return -EINVAL;
  978. }
  979. cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  980. "cnss-long", 0);
  981. if (!cnss_ipc_log_long_context) {
  982. cnss_pr_err("Unable to create IPC long log context\n");
  983. ipc_log_context_destroy(cnss_ipc_log_context);
  984. return -EINVAL;
  985. }
  986. return 0;
  987. }
  988. static void cnss_ipc_logging_deinit(void)
  989. {
  990. if (cnss_ipc_log_long_context) {
  991. ipc_log_context_destroy(cnss_ipc_log_long_context);
  992. cnss_ipc_log_long_context = NULL;
  993. }
  994. if (cnss_ipc_log_context) {
  995. ipc_log_context_destroy(cnss_ipc_log_context);
  996. cnss_ipc_log_context = NULL;
  997. }
  998. }
  999. #else
  1000. static int cnss_ipc_logging_init(void) { return 0; }
  1001. static void cnss_ipc_logging_deinit(void) {}
  1002. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  1003. enum log_level kern_log_level,
  1004. enum log_level ipc_log_level, char *fmt, ...)
  1005. {
  1006. struct va_format vaf;
  1007. va_list va_args;
  1008. va_start(va_args, fmt);
  1009. vaf.fmt = fmt;
  1010. vaf.va = &va_args;
  1011. if (kern_log_level <= cnss_kernel_log_level) {
  1012. switch (kern_log_level) {
  1013. case EMERG_LOG:
  1014. pr_emerg("cnss: %pV", &vaf);
  1015. break;
  1016. case ALERT_LOG:
  1017. pr_alert("cnss: %pV", &vaf);
  1018. break;
  1019. case CRIT_LOG:
  1020. pr_crit("cnss: %pV", &vaf);
  1021. break;
  1022. case ERR_LOG:
  1023. pr_err("cnss: %pV", &vaf);
  1024. break;
  1025. case WARNING_LOG:
  1026. pr_warn("cnss: %pV", &vaf);
  1027. break;
  1028. case NOTICE_LOG:
  1029. pr_notice("cnss: %pV", &vaf);
  1030. break;
  1031. case INFO_LOG:
  1032. pr_info("cnss: %pV", &vaf);
  1033. break;
  1034. case DEBUG_LOG:
  1035. case DEBUG_HI_LOG:
  1036. pr_debug("cnss: %pV", &vaf);
  1037. break;
  1038. default:
  1039. break;
  1040. }
  1041. }
  1042. va_end(va_args);
  1043. }
  1044. #endif
  1045. int cnss_debug_init(void)
  1046. {
  1047. return cnss_ipc_logging_init();
  1048. }
  1049. void cnss_debug_deinit(void)
  1050. {
  1051. cnss_ipc_logging_deinit();
  1052. }