sde_kms.c 108 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <drm/drm_atomic_uapi.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include "msm_drv.h"
  28. #include "msm_mmu.h"
  29. #include "msm_gem.h"
  30. #include "dsi_display.h"
  31. #include "dsi_drm.h"
  32. #include "sde_wb.h"
  33. #include "dp_display.h"
  34. #include "dp_drm.h"
  35. #include "dp_mst_drm.h"
  36. #include "sde_kms.h"
  37. #include "sde_core_irq.h"
  38. #include "sde_formats.h"
  39. #include "sde_hw_vbif.h"
  40. #include "sde_vbif.h"
  41. #include "sde_encoder.h"
  42. #include "sde_plane.h"
  43. #include "sde_crtc.h"
  44. #include "sde_color_processing.h"
  45. #include "sde_reg_dma.h"
  46. #include "sde_connector.h"
  47. #include "sde_vm.h"
  48. #include <linux/qcom_scm.h>
  49. #include "soc/qcom/secure_buffer.h"
  50. #include <linux/qtee_shmbridge.h>
  51. #include <linux/haven/hh_irq_lend.h>
  52. #define CREATE_TRACE_POINTS
  53. #include "sde_trace.h"
  54. /* defines for secure channel call */
  55. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  56. #define MDP_DEVICE_ID 0x1A
  57. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  58. static const char * const iommu_ports[] = {
  59. "mdp_0",
  60. };
  61. /**
  62. * Controls size of event log buffer. Specified as a power of 2.
  63. */
  64. #define SDE_EVTLOG_SIZE 1024
  65. /*
  66. * To enable overall DRM driver logging
  67. * # echo 0x2 > /sys/module/drm/parameters/debug
  68. *
  69. * To enable DRM driver h/w logging
  70. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  71. *
  72. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  73. */
  74. #define SDE_DEBUGFS_DIR "msm_sde"
  75. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  76. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  77. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  78. /**
  79. * sdecustom - enable certain driver customizations for sde clients
  80. * Enabling this modifies the standard DRM behavior slightly and assumes
  81. * that the clients have specific knowledge about the modifications that
  82. * are involved, so don't enable this unless you know what you're doing.
  83. *
  84. * Parts of the driver that are affected by this setting may be located by
  85. * searching for invocations of the 'sde_is_custom_client()' function.
  86. *
  87. * This is disabled by default.
  88. */
  89. static bool sdecustom = true;
  90. module_param(sdecustom, bool, 0400);
  91. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  92. static int sde_kms_hw_init(struct msm_kms *kms);
  93. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  94. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  95. static int _sde_kms_register_events(struct msm_kms *kms,
  96. struct drm_mode_object *obj, u32 event, bool en);
  97. bool sde_is_custom_client(void)
  98. {
  99. return sdecustom;
  100. }
  101. #ifdef CONFIG_DEBUG_FS
  102. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  103. {
  104. struct msm_drm_private *priv;
  105. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  106. return NULL;
  107. priv = sde_kms->dev->dev_private;
  108. return priv->debug_root;
  109. }
  110. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  111. {
  112. void *p;
  113. int rc;
  114. void *debugfs_root;
  115. p = sde_hw_util_get_log_mask_ptr();
  116. if (!sde_kms || !p)
  117. return -EINVAL;
  118. debugfs_root = sde_debugfs_get_root(sde_kms);
  119. if (!debugfs_root)
  120. return -EINVAL;
  121. /* allow debugfs_root to be NULL */
  122. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  123. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  124. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  125. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  126. if (rc) {
  127. SDE_ERROR("failed to init perf %d\n", rc);
  128. return rc;
  129. }
  130. if (sde_kms->catalog->qdss_count)
  131. debugfs_create_u32("qdss", 0600, debugfs_root,
  132. (u32 *)&sde_kms->qdss_enabled);
  133. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  134. (u32 *)&sde_kms->pm_suspend_clk_dump);
  135. return 0;
  136. }
  137. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  138. {
  139. struct sde_kms *sde_kms = to_sde_kms(kms);
  140. /* don't need to NULL check debugfs_root */
  141. if (sde_kms) {
  142. sde_debugfs_vbif_destroy(sde_kms);
  143. sde_debugfs_core_irq_destroy(sde_kms);
  144. }
  145. }
  146. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  147. {
  148. int i;
  149. struct device *dev = sde_kms->dev->dev;
  150. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  151. for (i = 0; i < sde_kms->dsi_display_count; i++)
  152. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  153. return 0;
  154. }
  155. #else
  156. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  157. {
  158. return 0;
  159. }
  160. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  161. {
  162. }
  163. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  164. {
  165. return 0;
  166. }
  167. #endif
  168. static bool _sde_kms_skip_vblank_op(struct sde_kms *sde_kms)
  169. {
  170. struct sde_vm_ops *vm_ops = NULL;
  171. if (!sde_kms->vm)
  172. return false;
  173. vm_ops = &sde_kms->vm->vm_ops;
  174. if (!vm_ops->vm_owns_hw(sde_kms))
  175. return true;
  176. return false;
  177. }
  178. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  179. {
  180. int ret = 0;
  181. struct sde_kms *sde_kms;
  182. if (!kms)
  183. return -EINVAL;
  184. sde_kms = to_sde_kms(kms);
  185. if (sde_kms->vm)
  186. mutex_lock(&sde_kms->vm->vm_res_lock);
  187. if (_sde_kms_skip_vblank_op(sde_kms)) {
  188. SDE_DEBUG("skipping vblank enable due to HW unavailablity\n");
  189. mutex_unlock(&sde_kms->vm->vm_res_lock);
  190. return 0;
  191. }
  192. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  193. ret = sde_crtc_vblank(crtc, true);
  194. SDE_ATRACE_END("sde_kms_enable_vblank");
  195. if (sde_kms->vm)
  196. mutex_unlock(&sde_kms->vm->vm_res_lock);
  197. return ret;
  198. }
  199. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  200. {
  201. struct sde_kms *sde_kms;
  202. if (!kms)
  203. return;
  204. sde_kms = to_sde_kms(kms);
  205. if (sde_kms->vm)
  206. mutex_lock(&sde_kms->vm->vm_res_lock);
  207. if (_sde_kms_skip_vblank_op(sde_kms)) {
  208. SDE_DEBUG("skipping vblank disable due to HW unavailablity\n");
  209. mutex_unlock(&sde_kms->vm->vm_res_lock);
  210. return;
  211. }
  212. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  213. sde_crtc_vblank(crtc, false);
  214. SDE_ATRACE_END("sde_kms_disable_vblank");
  215. if (sde_kms->vm)
  216. mutex_unlock(&sde_kms->vm->vm_res_lock);
  217. }
  218. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  219. struct drm_crtc *crtc)
  220. {
  221. struct drm_encoder *encoder;
  222. struct drm_device *dev;
  223. int ret;
  224. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  225. SDE_ERROR("invalid params\n");
  226. return;
  227. }
  228. if (!crtc->state->enable) {
  229. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  230. return;
  231. }
  232. if (!crtc->state->active) {
  233. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  234. return;
  235. }
  236. dev = crtc->dev;
  237. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  238. if (encoder->crtc != crtc)
  239. continue;
  240. /*
  241. * Video Mode - Wait for VSYNC
  242. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  243. * complete
  244. */
  245. SDE_EVT32_VERBOSE(DRMID(crtc));
  246. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  247. if (ret && ret != -EWOULDBLOCK) {
  248. SDE_ERROR(
  249. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  250. crtc->base.id, encoder->base.id, ret);
  251. break;
  252. }
  253. }
  254. }
  255. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  256. struct drm_crtc *crtc, bool enable)
  257. {
  258. struct drm_device *dev;
  259. struct msm_drm_private *priv;
  260. struct sde_mdss_cfg *sde_cfg;
  261. struct drm_plane *plane;
  262. int i, ret;
  263. dev = sde_kms->dev;
  264. priv = dev->dev_private;
  265. sde_cfg = sde_kms->catalog;
  266. ret = sde_vbif_halt_xin_mask(sde_kms,
  267. sde_cfg->sui_block_xin_mask, enable);
  268. if (ret) {
  269. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  270. return ret;
  271. }
  272. if (enable) {
  273. for (i = 0; i < priv->num_planes; i++) {
  274. plane = priv->planes[i];
  275. sde_plane_secure_ctrl_xin_client(plane, crtc);
  276. }
  277. }
  278. return 0;
  279. }
  280. /**
  281. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  282. * @sde_kms: Pointer to sde_kms struct
  283. * @vimd: switch the stage 2 translation to this VMID
  284. */
  285. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  286. {
  287. struct device dummy = {};
  288. dma_addr_t dma_handle;
  289. uint32_t num_sids;
  290. uint32_t *sec_sid;
  291. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  292. int ret = 0, i;
  293. struct qtee_shm shm;
  294. bool qtee_en = qtee_shmbridge_is_enabled();
  295. phys_addr_t mem_addr;
  296. u64 mem_size;
  297. num_sids = sde_cfg->sec_sid_mask_count;
  298. if (!num_sids) {
  299. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  300. return -EINVAL;
  301. }
  302. if (qtee_en) {
  303. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  304. &shm);
  305. if (ret)
  306. return -ENOMEM;
  307. sec_sid = (uint32_t *) shm.vaddr;
  308. mem_addr = shm.paddr;
  309. /**
  310. * SMMUSecureModeSwitch requires the size to be number of SID's
  311. * but shm allocates size in pages. Modify the args as per
  312. * client requirement.
  313. */
  314. mem_size = sizeof(uint32_t) * num_sids;
  315. } else {
  316. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  317. if (!sec_sid)
  318. return -ENOMEM;
  319. mem_addr = virt_to_phys(sec_sid);
  320. mem_size = sizeof(uint32_t) * num_sids;
  321. }
  322. for (i = 0; i < num_sids; i++) {
  323. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  324. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  325. }
  326. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  327. if (ret) {
  328. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  329. goto map_error;
  330. }
  331. set_dma_ops(&dummy, NULL);
  332. dma_handle = dma_map_single(&dummy, sec_sid,
  333. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  334. if (dma_mapping_error(&dummy, dma_handle)) {
  335. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  336. vmid);
  337. goto map_error;
  338. }
  339. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  340. vmid, num_sids, qtee_en);
  341. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  342. mem_size, vmid);
  343. if (ret)
  344. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  345. vmid, ret);
  346. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  347. vmid, qtee_en, num_sids, ret);
  348. dma_unmap_single(&dummy, dma_handle,
  349. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  350. map_error:
  351. if (qtee_en)
  352. qtee_shmbridge_free_shm(&shm);
  353. else
  354. kfree(sec_sid);
  355. return ret;
  356. }
  357. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  358. {
  359. u32 ret;
  360. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  361. return 0;
  362. /* detach_all_contexts */
  363. ret = sde_kms_mmu_detach(sde_kms, false);
  364. if (ret) {
  365. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  366. goto mmu_error;
  367. }
  368. ret = _sde_kms_scm_call(sde_kms, vmid);
  369. if (ret) {
  370. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  371. goto scm_error;
  372. }
  373. return 0;
  374. scm_error:
  375. sde_kms_mmu_attach(sde_kms, false);
  376. mmu_error:
  377. atomic_dec(&sde_kms->detach_all_cb);
  378. return ret;
  379. }
  380. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  381. u32 old_vmid)
  382. {
  383. u32 ret;
  384. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  385. return 0;
  386. ret = _sde_kms_scm_call(sde_kms, vmid);
  387. if (ret) {
  388. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  389. goto scm_error;
  390. }
  391. /* attach_all_contexts */
  392. ret = sde_kms_mmu_attach(sde_kms, false);
  393. if (ret) {
  394. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  395. goto mmu_error;
  396. }
  397. return 0;
  398. mmu_error:
  399. _sde_kms_scm_call(sde_kms, old_vmid);
  400. scm_error:
  401. atomic_inc(&sde_kms->detach_all_cb);
  402. return ret;
  403. }
  404. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  405. {
  406. u32 ret;
  407. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  408. return 0;
  409. /* detach secure_context */
  410. ret = sde_kms_mmu_detach(sde_kms, true);
  411. if (ret) {
  412. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  413. goto mmu_error;
  414. }
  415. ret = _sde_kms_scm_call(sde_kms, vmid);
  416. if (ret) {
  417. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  418. goto scm_error;
  419. }
  420. return 0;
  421. scm_error:
  422. sde_kms_mmu_attach(sde_kms, true);
  423. mmu_error:
  424. atomic_dec(&sde_kms->detach_sec_cb);
  425. return ret;
  426. }
  427. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  428. u32 old_vmid)
  429. {
  430. u32 ret;
  431. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  432. return 0;
  433. ret = _sde_kms_scm_call(sde_kms, vmid);
  434. if (ret) {
  435. goto scm_error;
  436. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  437. }
  438. ret = sde_kms_mmu_attach(sde_kms, true);
  439. if (ret) {
  440. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  441. goto mmu_error;
  442. }
  443. return 0;
  444. mmu_error:
  445. _sde_kms_scm_call(sde_kms, old_vmid);
  446. scm_error:
  447. atomic_inc(&sde_kms->detach_sec_cb);
  448. return ret;
  449. }
  450. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  451. struct drm_crtc *crtc, bool enable)
  452. {
  453. int ret;
  454. if (enable) {
  455. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  456. if (ret < 0) {
  457. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  458. return ret;
  459. }
  460. sde_crtc_misr_setup(crtc, true, 1);
  461. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  462. if (ret) {
  463. sde_crtc_misr_setup(crtc, false, 0);
  464. pm_runtime_put_sync(sde_kms->dev->dev);
  465. return ret;
  466. }
  467. } else {
  468. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  469. sde_crtc_misr_setup(crtc, false, 0);
  470. pm_runtime_put_sync(sde_kms->dev->dev);
  471. }
  472. return 0;
  473. }
  474. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  475. bool post_commit)
  476. {
  477. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  478. int old_smmu_state = smmu_state->state;
  479. int ret = 0;
  480. u32 vmid;
  481. if (!sde_kms || !crtc) {
  482. SDE_ERROR("invalid argument(s)\n");
  483. return -EINVAL;
  484. }
  485. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  486. post_commit, smmu_state->sui_misr_state,
  487. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  488. if ((!smmu_state->transition_type) ||
  489. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  490. /* Bail out */
  491. return 0;
  492. /* enable sui misr if requested, before the transition */
  493. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  494. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  495. if (ret) {
  496. smmu_state->sui_misr_state = NONE;
  497. goto end;
  498. }
  499. }
  500. mutex_lock(&sde_kms->secure_transition_lock);
  501. switch (smmu_state->state) {
  502. case DETACH_ALL_REQ:
  503. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  504. if (!ret)
  505. smmu_state->state = DETACHED;
  506. break;
  507. case ATTACH_ALL_REQ:
  508. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  509. VMID_CP_SEC_DISPLAY);
  510. if (!ret) {
  511. smmu_state->state = ATTACHED;
  512. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  513. }
  514. break;
  515. case DETACH_SEC_REQ:
  516. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  517. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  518. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  519. if (!ret)
  520. smmu_state->state = DETACHED_SEC;
  521. break;
  522. case ATTACH_SEC_REQ:
  523. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  524. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  525. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  526. if (!ret) {
  527. smmu_state->state = ATTACHED;
  528. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  529. }
  530. break;
  531. default:
  532. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  533. DRMID(crtc), smmu_state->state,
  534. smmu_state->transition_type);
  535. ret = -EINVAL;
  536. break;
  537. }
  538. mutex_unlock(&sde_kms->secure_transition_lock);
  539. /* disable sui misr if requested, after the transition */
  540. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  541. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  542. if (ret)
  543. goto end;
  544. }
  545. end:
  546. smmu_state->transition_error = false;
  547. if (ret) {
  548. smmu_state->transition_error = true;
  549. SDE_ERROR(
  550. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  551. DRMID(crtc), old_smmu_state, smmu_state->state,
  552. smmu_state->secure_level, ret);
  553. smmu_state->state = smmu_state->prev_state;
  554. smmu_state->secure_level = smmu_state->prev_secure_level;
  555. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  556. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  557. }
  558. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  559. DRMID(crtc), old_smmu_state, smmu_state->state,
  560. smmu_state->secure_level, ret);
  561. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  562. smmu_state->transition_type,
  563. smmu_state->transition_error,
  564. smmu_state->secure_level, smmu_state->prev_secure_level,
  565. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  566. smmu_state->sui_misr_state = NONE;
  567. smmu_state->transition_type = NONE;
  568. return ret;
  569. }
  570. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  571. struct drm_atomic_state *state)
  572. {
  573. struct drm_crtc *crtc;
  574. struct drm_crtc_state *old_crtc_state;
  575. struct drm_plane_state *old_plane_state, *new_plane_state;
  576. struct drm_plane *plane;
  577. struct drm_plane_state *plane_state;
  578. struct sde_kms *sde_kms = to_sde_kms(kms);
  579. struct drm_device *dev = sde_kms->dev;
  580. int i, ops = 0, ret = 0;
  581. bool old_valid_fb = false;
  582. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  583. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  584. if (!crtc->state || !crtc->state->active)
  585. continue;
  586. /*
  587. * It is safe to assume only one active crtc,
  588. * and compatible translation modes on the
  589. * planes staged on this crtc.
  590. * otherwise validation would have failed.
  591. * For this CRTC,
  592. */
  593. /*
  594. * 1. Check if old state on the CRTC has planes
  595. * staged with valid fbs
  596. */
  597. for_each_old_plane_in_state(state, plane, plane_state, i) {
  598. if (!plane_state->crtc)
  599. continue;
  600. if (plane_state->fb) {
  601. old_valid_fb = true;
  602. break;
  603. }
  604. }
  605. /*
  606. * 2.Get the operations needed to be performed before
  607. * secure transition can be initiated.
  608. */
  609. ops = sde_crtc_get_secure_transition_ops(crtc,
  610. old_crtc_state, old_valid_fb);
  611. if (ops < 0) {
  612. SDE_ERROR("invalid secure operations %x\n", ops);
  613. return ops;
  614. }
  615. if (!ops) {
  616. smmu_state->transition_error = false;
  617. goto no_ops;
  618. }
  619. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  620. crtc->base.id, ops, crtc->state);
  621. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  622. /* 3. Perform operations needed for secure transition */
  623. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  624. SDE_DEBUG("wait_for_transfer_done\n");
  625. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  626. }
  627. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  628. SDE_DEBUG("cleanup planes\n");
  629. drm_atomic_helper_cleanup_planes(dev, state);
  630. for_each_oldnew_plane_in_state(state, plane,
  631. old_plane_state, new_plane_state, i)
  632. sde_plane_destroy_fb(old_plane_state);
  633. }
  634. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  635. SDE_DEBUG("secure ctrl\n");
  636. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  637. }
  638. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  639. SDE_DEBUG("prepare planes %d",
  640. crtc->state->plane_mask);
  641. drm_atomic_crtc_for_each_plane(plane,
  642. crtc) {
  643. const struct drm_plane_helper_funcs *funcs;
  644. plane_state = plane->state;
  645. funcs = plane->helper_private;
  646. SDE_DEBUG("psde:%d FB[%u]\n",
  647. plane->base.id,
  648. plane->fb->base.id);
  649. if (!funcs)
  650. continue;
  651. if (funcs->prepare_fb(plane, plane_state)) {
  652. ret = funcs->prepare_fb(plane,
  653. plane_state);
  654. if (ret)
  655. return ret;
  656. }
  657. }
  658. }
  659. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  660. SDE_DEBUG("secure operations completed\n");
  661. }
  662. no_ops:
  663. return 0;
  664. }
  665. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  666. unsigned int splash_buffer_size,
  667. unsigned int ramdump_base,
  668. unsigned int ramdump_buffer_size)
  669. {
  670. unsigned long pfn_start, pfn_end, pfn_idx;
  671. int ret = 0;
  672. if (!mem_addr || !splash_buffer_size) {
  673. SDE_ERROR("invalid params\n");
  674. return -EINVAL;
  675. }
  676. /* leave ramdump memory only if base address matches */
  677. if (ramdump_base == mem_addr &&
  678. ramdump_buffer_size <= splash_buffer_size) {
  679. mem_addr += ramdump_buffer_size;
  680. splash_buffer_size -= ramdump_buffer_size;
  681. }
  682. pfn_start = mem_addr >> PAGE_SHIFT;
  683. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  684. if (ret) {
  685. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  686. return ret;
  687. }
  688. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  689. free_reserved_page(pfn_to_page(pfn_idx));
  690. return ret;
  691. }
  692. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  693. struct sde_splash_mem *splash)
  694. {
  695. struct msm_mmu *mmu = NULL;
  696. int ret = 0;
  697. if (!sde_kms->aspace[0]) {
  698. SDE_ERROR("aspace not found for sde kms node\n");
  699. return -EINVAL;
  700. }
  701. mmu = sde_kms->aspace[0]->mmu;
  702. if (!mmu) {
  703. SDE_ERROR("mmu not found for aspace\n");
  704. return -EINVAL;
  705. }
  706. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  707. SDE_ERROR("invalid input params for map\n");
  708. return -EINVAL;
  709. }
  710. if (!splash->ref_cnt) {
  711. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  712. splash->splash_buf_base,
  713. splash->splash_buf_size,
  714. IOMMU_READ | IOMMU_NOEXEC);
  715. if (ret)
  716. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  717. }
  718. splash->ref_cnt++;
  719. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  720. splash->splash_buf_base,
  721. splash->splash_buf_size,
  722. splash->ref_cnt);
  723. return ret;
  724. }
  725. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  726. {
  727. int i = 0;
  728. int ret = 0;
  729. if (!sde_kms)
  730. return -EINVAL;
  731. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  732. ret = _sde_kms_splash_mem_get(sde_kms,
  733. sde_kms->splash_data.splash_display[i].splash);
  734. if (ret)
  735. return ret;
  736. }
  737. return ret;
  738. }
  739. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  740. struct sde_splash_mem *splash)
  741. {
  742. struct msm_mmu *mmu = NULL;
  743. int rc = 0;
  744. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  745. SDE_ERROR("invalid params\n");
  746. return -EINVAL;
  747. }
  748. mmu = sde_kms->aspace[0]->mmu;
  749. if (!splash || !splash->ref_cnt ||
  750. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  751. return -EINVAL;
  752. splash->ref_cnt--;
  753. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  754. splash->splash_buf_base, splash->ref_cnt);
  755. if (!splash->ref_cnt) {
  756. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  757. splash->splash_buf_size);
  758. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  759. splash->splash_buf_size, splash->ramdump_base,
  760. splash->ramdump_size);
  761. splash->splash_buf_base = 0;
  762. splash->splash_buf_size = 0;
  763. }
  764. return rc;
  765. }
  766. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  767. {
  768. int i = 0;
  769. int ret = 0;
  770. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  771. return -EINVAL;
  772. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  773. ret = _sde_kms_splash_mem_put(sde_kms,
  774. sde_kms->splash_data.splash_display[i].splash);
  775. if (ret)
  776. return ret;
  777. }
  778. return ret;
  779. }
  780. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  781. struct drm_atomic_state *state)
  782. {
  783. struct drm_device *ddev;
  784. struct drm_crtc *crtc;
  785. struct drm_encoder *encoder;
  786. struct drm_connector *connector;
  787. struct sde_vm_ops *vm_ops;
  788. struct sde_crtc_state *cstate;
  789. enum sde_crtc_vm_req vm_req;
  790. int rc = 0;
  791. ddev = sde_kms->dev;
  792. if (!sde_kms->vm)
  793. return -EINVAL;
  794. vm_ops = &sde_kms->vm->vm_ops;
  795. crtc = state->crtcs[0].ptr;
  796. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  797. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  798. if (vm_req != VM_REQ_ACQUIRE)
  799. return 0;
  800. /* enable MDSS irq line */
  801. sde_irq_update(&sde_kms->base, true);
  802. /* clear the stale IRQ status bits */
  803. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  804. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  805. /* enable the display path IRQ's */
  806. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  807. sde_encoder_irq_control(encoder, true);
  808. /* Schedule ESD work */
  809. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  810. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  811. sde_connector_schedule_status_work(connector, true);
  812. /* handle non-SDE pre_acquire */
  813. if (vm_ops->vm_client_post_acquire)
  814. rc = vm_ops->vm_client_post_acquire(sde_kms);
  815. return rc;
  816. }
  817. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  818. struct drm_atomic_state *state)
  819. {
  820. struct drm_device *ddev;
  821. struct drm_plane *plane;
  822. struct sde_crtc_state *cstate;
  823. enum sde_crtc_vm_req vm_req;
  824. ddev = sde_kms->dev;
  825. pm_runtime_get_sync(ddev->dev);
  826. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  827. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  828. if (vm_req != VM_REQ_ACQUIRE)
  829. return 0;
  830. /* Clear the stale IRQ status bits */
  831. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  832. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  833. /* Program the SID's for the trusted VM */
  834. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  835. sde_plane_set_sid(plane, 1);
  836. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  837. return 0;
  838. }
  839. static void sde_kms_prepare_commit(struct msm_kms *kms,
  840. struct drm_atomic_state *state)
  841. {
  842. struct sde_kms *sde_kms;
  843. struct msm_drm_private *priv;
  844. struct drm_device *dev;
  845. struct drm_encoder *encoder;
  846. struct drm_crtc *crtc;
  847. struct drm_crtc_state *crtc_state;
  848. struct sde_vm_ops *vm_ops;
  849. int i, rc;
  850. if (!kms)
  851. return;
  852. sde_kms = to_sde_kms(kms);
  853. dev = sde_kms->dev;
  854. if (!dev || !dev->dev_private)
  855. return;
  856. priv = dev->dev_private;
  857. SDE_ATRACE_BEGIN("prepare_commit");
  858. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  859. if (rc < 0) {
  860. SDE_ERROR("failed to enable power resources %d\n", rc);
  861. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  862. goto end;
  863. }
  864. if (sde_kms->first_kickoff) {
  865. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  866. sde_kms->first_kickoff = false;
  867. }
  868. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  869. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  870. head) {
  871. if (encoder->crtc != crtc)
  872. continue;
  873. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  874. SDE_ERROR("crtc:%d, initiating hw reset\n",
  875. DRMID(crtc));
  876. sde_encoder_needs_hw_reset(encoder);
  877. sde_crtc_set_needs_hw_reset(crtc);
  878. }
  879. }
  880. }
  881. /*
  882. * NOTE: for secure use cases we want to apply the new HW
  883. * configuration only after completing preparation for secure
  884. * transitions prepare below if any transtions is required.
  885. */
  886. sde_kms_prepare_secure_transition(kms, state);
  887. if (!sde_kms->vm)
  888. goto end;
  889. vm_ops = &sde_kms->vm->vm_ops;
  890. if (vm_ops->vm_prepare_commit)
  891. vm_ops->vm_prepare_commit(sde_kms, state);
  892. end:
  893. SDE_ATRACE_END("prepare_commit");
  894. }
  895. static void sde_kms_commit(struct msm_kms *kms,
  896. struct drm_atomic_state *old_state)
  897. {
  898. struct sde_kms *sde_kms;
  899. struct drm_crtc *crtc;
  900. struct drm_crtc_state *old_crtc_state;
  901. int i;
  902. if (!kms || !old_state)
  903. return;
  904. sde_kms = to_sde_kms(kms);
  905. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  906. SDE_ERROR("power resource is not enabled\n");
  907. return;
  908. }
  909. SDE_ATRACE_BEGIN("sde_kms_commit");
  910. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  911. if (crtc->state->active) {
  912. SDE_EVT32(DRMID(crtc));
  913. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  914. }
  915. }
  916. SDE_ATRACE_END("sde_kms_commit");
  917. }
  918. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  919. struct sde_splash_display *splash_display)
  920. {
  921. if (!sde_kms || !splash_display ||
  922. !sde_kms->splash_data.num_splash_displays)
  923. return;
  924. if (sde_kms->splash_data.num_splash_regions)
  925. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  926. sde_kms->splash_data.num_splash_displays--;
  927. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  928. sde_kms->splash_data.num_splash_displays);
  929. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  930. }
  931. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  932. struct drm_crtc *crtc)
  933. {
  934. struct msm_drm_private *priv;
  935. struct sde_splash_display *splash_display;
  936. int i;
  937. if (!sde_kms || !crtc)
  938. return;
  939. priv = sde_kms->dev->dev_private;
  940. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  941. return;
  942. SDE_EVT32(DRMID(crtc), crtc->state->active,
  943. sde_kms->splash_data.num_splash_displays);
  944. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  945. splash_display = &sde_kms->splash_data.splash_display[i];
  946. if (splash_display->encoder &&
  947. crtc == splash_display->encoder->crtc)
  948. break;
  949. }
  950. if (i >= MAX_DSI_DISPLAYS)
  951. return;
  952. if (splash_display->cont_splash_enabled) {
  953. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  954. splash_display, false);
  955. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  956. }
  957. /* remove the votes if all displays are done with splash */
  958. if (!sde_kms->splash_data.num_splash_displays) {
  959. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  960. sde_power_data_bus_set_quota(&priv->phandle, i,
  961. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  962. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  963. pm_runtime_put_sync(sde_kms->dev->dev);
  964. }
  965. }
  966. void _sde_kms_program_mode_info(struct sde_kms *sde_kms)
  967. {
  968. struct drm_encoder *encoder;
  969. struct drm_crtc *crtc;
  970. struct drm_connector *connector;
  971. struct drm_connector_list_iter conn_iter;
  972. struct dsi_display *dsi_display;
  973. struct drm_display_mode *drm_mode;
  974. int i;
  975. struct drm_device *dev;
  976. u32 mode_index = 0;
  977. if (!sde_kms->dev || !sde_kms->hw_mdp)
  978. return;
  979. dev = sde_kms->dev;
  980. sde_kms->hw_mdp->ops.clear_mode_index(sde_kms->hw_mdp);
  981. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  982. dsi_display = (struct dsi_display *)sde_kms->dsi_displays[i];
  983. if (dsi_display->bridge->base.encoder) {
  984. encoder = dsi_display->bridge->base.encoder;
  985. crtc = encoder->crtc;
  986. if (!crtc->state->active)
  987. continue;
  988. mutex_lock(&dev->mode_config.mutex);
  989. drm_connector_list_iter_begin(dev, &conn_iter);
  990. drm_for_each_connector_iter(connector, &conn_iter) {
  991. if (connector->encoder_ids[0]
  992. == encoder->base.id)
  993. break;
  994. }
  995. drm_connector_list_iter_end(&conn_iter);
  996. mutex_unlock(&dev->mode_config.mutex);
  997. list_for_each_entry(drm_mode, &connector->modes, head) {
  998. if (drm_mode_equal(
  999. &crtc->state->mode, drm_mode))
  1000. break;
  1001. mode_index++;
  1002. }
  1003. sde_kms->hw_mdp->ops.set_mode_index(
  1004. sde_kms->hw_mdp, i, mode_index);
  1005. SDE_DEBUG("crtc:%d, display_idx:%d, mode_index:%d\n",
  1006. DRMID(crtc), i, mode_index);
  1007. }
  1008. }
  1009. }
  1010. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1011. struct drm_atomic_state *state)
  1012. {
  1013. struct sde_vm_ops *vm_ops;
  1014. struct drm_device *ddev;
  1015. struct drm_crtc *crtc;
  1016. struct drm_plane *plane;
  1017. struct drm_encoder *encoder;
  1018. struct sde_crtc_state *cstate;
  1019. struct drm_crtc_state *new_cstate;
  1020. enum sde_crtc_vm_req vm_req;
  1021. int rc = 0;
  1022. if (!sde_kms || !sde_kms->vm)
  1023. return -EINVAL;
  1024. vm_ops = &sde_kms->vm->vm_ops;
  1025. ddev = sde_kms->dev;
  1026. crtc = state->crtcs[0].ptr;
  1027. new_cstate = state->crtcs[0].new_state;
  1028. cstate = to_sde_crtc_state(new_cstate);
  1029. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1030. if (vm_req != VM_REQ_RELEASE)
  1031. return rc;
  1032. if (!new_cstate->active && !new_cstate->active_changed)
  1033. return rc;
  1034. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1035. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1036. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1037. sde_encoder_irq_control(encoder, false);
  1038. sde_irq_update(&sde_kms->base, false);
  1039. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1040. sde_plane_set_sid(plane, 0);
  1041. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1042. sde_kms_vm_trusted_resource_deinit(sde_kms);
  1043. if (vm_ops->vm_release)
  1044. rc = vm_ops->vm_release(sde_kms);
  1045. pm_runtime_put_sync(ddev->dev);
  1046. return rc;
  1047. }
  1048. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1049. struct drm_atomic_state *state)
  1050. {
  1051. struct drm_device *ddev;
  1052. struct drm_crtc *crtc;
  1053. struct drm_encoder *encoder;
  1054. struct drm_connector *connector;
  1055. int rc = 0;
  1056. ddev = sde_kms->dev;
  1057. crtc = state->crtcs[0].ptr;
  1058. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1059. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1060. /* disable ESD work */
  1061. list_for_each_entry(connector,
  1062. &ddev->mode_config.connector_list, head) {
  1063. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1064. sde_connector_schedule_status_work(connector, false);
  1065. }
  1066. /* disable SDE irq's */
  1067. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1068. sde_encoder_irq_control(encoder, false);
  1069. /* disable IRQ line */
  1070. sde_irq_update(&sde_kms->base, false);
  1071. return rc;
  1072. }
  1073. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1074. struct drm_atomic_state *state)
  1075. {
  1076. struct sde_vm_ops *vm_ops;
  1077. struct sde_crtc_state *cstate;
  1078. struct drm_crtc *crtc;
  1079. enum sde_crtc_vm_req vm_req;
  1080. int rc = 0;
  1081. if (!sde_kms || !sde_kms->vm)
  1082. return -EINVAL;
  1083. vm_ops = &sde_kms->vm->vm_ops;
  1084. crtc = state->crtcs[0].ptr;
  1085. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  1086. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1087. if (vm_req != VM_REQ_RELEASE)
  1088. goto exit;
  1089. /* handle SDE pre-release */
  1090. sde_kms_vm_pre_release(sde_kms, state);
  1091. /* properly handoff color processing features */
  1092. sde_cp_crtc_vm_primary_handoff(crtc);
  1093. /* program the current drm mode info to scratch reg */
  1094. _sde_kms_program_mode_info(sde_kms);
  1095. /* handle non-SDE clients pre-release */
  1096. if (vm_ops->vm_client_pre_release) {
  1097. rc = vm_ops->vm_client_pre_release(sde_kms);
  1098. if (rc) {
  1099. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1100. goto exit;
  1101. }
  1102. }
  1103. /* release HW */
  1104. if (vm_ops->vm_release) {
  1105. rc = vm_ops->vm_release(sde_kms);
  1106. if (rc)
  1107. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1108. }
  1109. exit:
  1110. return rc;
  1111. }
  1112. static void sde_kms_complete_commit(struct msm_kms *kms,
  1113. struct drm_atomic_state *old_state)
  1114. {
  1115. struct sde_kms *sde_kms;
  1116. struct msm_drm_private *priv;
  1117. struct drm_crtc *crtc;
  1118. struct drm_crtc_state *old_crtc_state;
  1119. struct drm_connector *connector;
  1120. struct drm_connector_state *old_conn_state;
  1121. struct msm_display_conn_params params;
  1122. struct sde_vm_ops *vm_ops;
  1123. int i, rc = 0;
  1124. if (!kms || !old_state)
  1125. return;
  1126. sde_kms = to_sde_kms(kms);
  1127. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1128. return;
  1129. priv = sde_kms->dev->dev_private;
  1130. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1131. SDE_ERROR("power resource is not enabled\n");
  1132. return;
  1133. }
  1134. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1135. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1136. sde_crtc_complete_commit(crtc, old_crtc_state);
  1137. /* complete secure transitions if any */
  1138. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1139. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1140. }
  1141. for_each_old_connector_in_state(old_state, connector,
  1142. old_conn_state, i) {
  1143. struct sde_connector *c_conn;
  1144. c_conn = to_sde_connector(connector);
  1145. if (!c_conn->ops.post_kickoff)
  1146. continue;
  1147. memset(&params, 0, sizeof(params));
  1148. sde_connector_complete_qsync_commit(connector, &params);
  1149. rc = c_conn->ops.post_kickoff(connector, &params);
  1150. if (rc) {
  1151. pr_err("Connector Post kickoff failed rc=%d\n",
  1152. rc);
  1153. }
  1154. }
  1155. if (sde_kms->vm) {
  1156. vm_ops = &sde_kms->vm->vm_ops;
  1157. if (vm_ops->vm_post_commit) {
  1158. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1159. if (rc)
  1160. SDE_ERROR("vm post commit failed, rc = %d\n",
  1161. rc);
  1162. }
  1163. }
  1164. pm_runtime_put_sync(sde_kms->dev->dev);
  1165. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1166. _sde_kms_release_splash_resource(sde_kms, crtc);
  1167. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1168. SDE_ATRACE_END("sde_kms_complete_commit");
  1169. }
  1170. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1171. struct drm_crtc *crtc)
  1172. {
  1173. struct drm_encoder *encoder;
  1174. struct drm_device *dev;
  1175. int ret;
  1176. if (!kms || !crtc || !crtc->state) {
  1177. SDE_ERROR("invalid params\n");
  1178. return;
  1179. }
  1180. dev = crtc->dev;
  1181. if (!crtc->state->enable) {
  1182. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1183. return;
  1184. }
  1185. if (!crtc->state->active) {
  1186. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1187. return;
  1188. }
  1189. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1190. SDE_ERROR("power resource is not enabled\n");
  1191. return;
  1192. }
  1193. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1194. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1195. if (encoder->crtc != crtc)
  1196. continue;
  1197. /*
  1198. * Wait for post-flush if necessary to delay before
  1199. * plane_cleanup. For example, wait for vsync in case of video
  1200. * mode panels. This may be a no-op for command mode panels.
  1201. */
  1202. SDE_EVT32_VERBOSE(DRMID(crtc));
  1203. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1204. if (ret && ret != -EWOULDBLOCK) {
  1205. SDE_ERROR("wait for commit done returned %d\n", ret);
  1206. sde_crtc_request_frame_reset(crtc);
  1207. break;
  1208. }
  1209. sde_crtc_complete_flip(crtc, NULL);
  1210. }
  1211. sde_crtc_static_cache_read_kickoff(crtc);
  1212. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1213. }
  1214. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1215. struct drm_atomic_state *old_state)
  1216. {
  1217. struct drm_crtc *crtc;
  1218. struct drm_crtc_state *old_crtc_state;
  1219. int i, rc;
  1220. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1221. SDE_ERROR("invalid argument(s)\n");
  1222. return;
  1223. }
  1224. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1225. retry:
  1226. /* attempt to acquire ww mutex for connection */
  1227. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1228. old_state->acquire_ctx);
  1229. if (rc == -EDEADLK) {
  1230. drm_modeset_backoff(old_state->acquire_ctx);
  1231. goto retry;
  1232. }
  1233. /* old_state actually contains updated crtc pointers */
  1234. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1235. if (crtc->state->active || crtc->state->active_changed)
  1236. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1237. }
  1238. SDE_ATRACE_END("sde_kms_prepare_fence");
  1239. }
  1240. /**
  1241. * _sde_kms_get_displays - query for underlying display handles and cache them
  1242. * @sde_kms: Pointer to sde kms structure
  1243. * Returns: Zero on success
  1244. */
  1245. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1246. {
  1247. int rc = -ENOMEM;
  1248. if (!sde_kms) {
  1249. SDE_ERROR("invalid sde kms\n");
  1250. return -EINVAL;
  1251. }
  1252. /* dsi */
  1253. sde_kms->dsi_displays = NULL;
  1254. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1255. if (sde_kms->dsi_display_count) {
  1256. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1257. sizeof(void *),
  1258. GFP_KERNEL);
  1259. if (!sde_kms->dsi_displays) {
  1260. SDE_ERROR("failed to allocate dsi displays\n");
  1261. goto exit_deinit_dsi;
  1262. }
  1263. sde_kms->dsi_display_count =
  1264. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1265. sde_kms->dsi_display_count);
  1266. }
  1267. /* wb */
  1268. sde_kms->wb_displays = NULL;
  1269. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1270. if (sde_kms->wb_display_count) {
  1271. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1272. sizeof(void *),
  1273. GFP_KERNEL);
  1274. if (!sde_kms->wb_displays) {
  1275. SDE_ERROR("failed to allocate wb displays\n");
  1276. goto exit_deinit_wb;
  1277. }
  1278. sde_kms->wb_display_count =
  1279. wb_display_get_displays(sde_kms->wb_displays,
  1280. sde_kms->wb_display_count);
  1281. }
  1282. /* dp */
  1283. sde_kms->dp_displays = NULL;
  1284. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1285. if (sde_kms->dp_display_count) {
  1286. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1287. sizeof(void *), GFP_KERNEL);
  1288. if (!sde_kms->dp_displays) {
  1289. SDE_ERROR("failed to allocate dp displays\n");
  1290. goto exit_deinit_dp;
  1291. }
  1292. sde_kms->dp_display_count =
  1293. dp_display_get_displays(sde_kms->dp_displays,
  1294. sde_kms->dp_display_count);
  1295. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1296. }
  1297. return 0;
  1298. exit_deinit_dp:
  1299. kfree(sde_kms->dp_displays);
  1300. sde_kms->dp_stream_count = 0;
  1301. sde_kms->dp_display_count = 0;
  1302. sde_kms->dp_displays = NULL;
  1303. exit_deinit_wb:
  1304. kfree(sde_kms->wb_displays);
  1305. sde_kms->wb_display_count = 0;
  1306. sde_kms->wb_displays = NULL;
  1307. exit_deinit_dsi:
  1308. kfree(sde_kms->dsi_displays);
  1309. sde_kms->dsi_display_count = 0;
  1310. sde_kms->dsi_displays = NULL;
  1311. return rc;
  1312. }
  1313. /**
  1314. * _sde_kms_release_displays - release cache of underlying display handles
  1315. * @sde_kms: Pointer to sde kms structure
  1316. */
  1317. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1318. {
  1319. if (!sde_kms) {
  1320. SDE_ERROR("invalid sde kms\n");
  1321. return;
  1322. }
  1323. kfree(sde_kms->wb_displays);
  1324. sde_kms->wb_displays = NULL;
  1325. sde_kms->wb_display_count = 0;
  1326. kfree(sde_kms->dsi_displays);
  1327. sde_kms->dsi_displays = NULL;
  1328. sde_kms->dsi_display_count = 0;
  1329. }
  1330. /**
  1331. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1332. * for underlying displays
  1333. * @dev: Pointer to drm device structure
  1334. * @priv: Pointer to private drm device data
  1335. * @sde_kms: Pointer to sde kms structure
  1336. * Returns: Zero on success
  1337. */
  1338. static int _sde_kms_setup_displays(struct drm_device *dev,
  1339. struct msm_drm_private *priv,
  1340. struct sde_kms *sde_kms)
  1341. {
  1342. static const struct sde_connector_ops dsi_ops = {
  1343. .set_info_blob = dsi_conn_set_info_blob,
  1344. .detect = dsi_conn_detect,
  1345. .get_modes = dsi_connector_get_modes,
  1346. .pre_destroy = dsi_connector_put_modes,
  1347. .mode_valid = dsi_conn_mode_valid,
  1348. .get_info = dsi_display_get_info,
  1349. .set_backlight = dsi_display_set_backlight,
  1350. .soft_reset = dsi_display_soft_reset,
  1351. .pre_kickoff = dsi_conn_pre_kickoff,
  1352. .clk_ctrl = dsi_display_clk_ctrl,
  1353. .set_power = dsi_display_set_power,
  1354. .get_mode_info = dsi_conn_get_mode_info,
  1355. .get_dst_format = dsi_display_get_dst_format,
  1356. .post_kickoff = dsi_conn_post_kickoff,
  1357. .check_status = dsi_display_check_status,
  1358. .enable_event = dsi_conn_enable_event,
  1359. .cmd_transfer = dsi_display_cmd_transfer,
  1360. .cont_splash_config = dsi_display_cont_splash_config,
  1361. .get_panel_vfp = dsi_display_get_panel_vfp,
  1362. .get_default_lms = dsi_display_get_default_lms,
  1363. .cmd_receive = dsi_display_cmd_receive,
  1364. };
  1365. static const struct sde_connector_ops wb_ops = {
  1366. .post_init = sde_wb_connector_post_init,
  1367. .set_info_blob = sde_wb_connector_set_info_blob,
  1368. .detect = sde_wb_connector_detect,
  1369. .get_modes = sde_wb_connector_get_modes,
  1370. .set_property = sde_wb_connector_set_property,
  1371. .get_info = sde_wb_get_info,
  1372. .soft_reset = NULL,
  1373. .get_mode_info = sde_wb_get_mode_info,
  1374. .get_dst_format = NULL,
  1375. .check_status = NULL,
  1376. .cmd_transfer = NULL,
  1377. .cont_splash_config = NULL,
  1378. .get_panel_vfp = NULL,
  1379. .cmd_receive = NULL,
  1380. };
  1381. static const struct sde_connector_ops dp_ops = {
  1382. .post_init = dp_connector_post_init,
  1383. .detect = dp_connector_detect,
  1384. .get_modes = dp_connector_get_modes,
  1385. .atomic_check = dp_connector_atomic_check,
  1386. .mode_valid = dp_connector_mode_valid,
  1387. .get_info = dp_connector_get_info,
  1388. .get_mode_info = dp_connector_get_mode_info,
  1389. .post_open = dp_connector_post_open,
  1390. .check_status = NULL,
  1391. .set_colorspace = dp_connector_set_colorspace,
  1392. .config_hdr = dp_connector_config_hdr,
  1393. .cmd_transfer = NULL,
  1394. .cont_splash_config = NULL,
  1395. .get_panel_vfp = NULL,
  1396. .update_pps = dp_connector_update_pps,
  1397. .cmd_receive = NULL,
  1398. };
  1399. struct msm_display_info info;
  1400. struct drm_encoder *encoder;
  1401. void *display, *connector;
  1402. int i, max_encoders;
  1403. int rc = 0;
  1404. u32 dsc_count = 0, mixer_count = 0;
  1405. u32 max_dp_dsc_count, max_dp_mixer_count;
  1406. if (!dev || !priv || !sde_kms) {
  1407. SDE_ERROR("invalid argument(s)\n");
  1408. return -EINVAL;
  1409. }
  1410. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1411. sde_kms->dp_display_count +
  1412. sde_kms->dp_stream_count;
  1413. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1414. max_encoders = ARRAY_SIZE(priv->encoders);
  1415. SDE_ERROR("capping number of displays to %d", max_encoders);
  1416. }
  1417. /* wb */
  1418. for (i = 0; i < sde_kms->wb_display_count &&
  1419. priv->num_encoders < max_encoders; ++i) {
  1420. display = sde_kms->wb_displays[i];
  1421. encoder = NULL;
  1422. memset(&info, 0x0, sizeof(info));
  1423. rc = sde_wb_get_info(NULL, &info, display);
  1424. if (rc) {
  1425. SDE_ERROR("wb get_info %d failed\n", i);
  1426. continue;
  1427. }
  1428. encoder = sde_encoder_init(dev, &info);
  1429. if (IS_ERR_OR_NULL(encoder)) {
  1430. SDE_ERROR("encoder init failed for wb %d\n", i);
  1431. continue;
  1432. }
  1433. rc = sde_wb_drm_init(display, encoder);
  1434. if (rc) {
  1435. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1436. sde_encoder_destroy(encoder);
  1437. continue;
  1438. }
  1439. connector = sde_connector_init(dev,
  1440. encoder,
  1441. 0,
  1442. display,
  1443. &wb_ops,
  1444. DRM_CONNECTOR_POLL_HPD,
  1445. DRM_MODE_CONNECTOR_VIRTUAL);
  1446. if (connector) {
  1447. priv->encoders[priv->num_encoders++] = encoder;
  1448. priv->connectors[priv->num_connectors++] = connector;
  1449. } else {
  1450. SDE_ERROR("wb %d connector init failed\n", i);
  1451. sde_wb_drm_deinit(display);
  1452. sde_encoder_destroy(encoder);
  1453. }
  1454. }
  1455. /* dsi */
  1456. for (i = 0; i < sde_kms->dsi_display_count &&
  1457. priv->num_encoders < max_encoders; ++i) {
  1458. display = sde_kms->dsi_displays[i];
  1459. encoder = NULL;
  1460. memset(&info, 0x0, sizeof(info));
  1461. rc = dsi_display_get_info(NULL, &info, display);
  1462. if (rc) {
  1463. SDE_ERROR("dsi get_info %d failed\n", i);
  1464. continue;
  1465. }
  1466. encoder = sde_encoder_init(dev, &info);
  1467. if (IS_ERR_OR_NULL(encoder)) {
  1468. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1469. continue;
  1470. }
  1471. rc = dsi_display_drm_bridge_init(display, encoder);
  1472. if (rc) {
  1473. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1474. sde_encoder_destroy(encoder);
  1475. continue;
  1476. }
  1477. connector = sde_connector_init(dev,
  1478. encoder,
  1479. dsi_display_get_drm_panel(display),
  1480. display,
  1481. &dsi_ops,
  1482. DRM_CONNECTOR_POLL_HPD,
  1483. DRM_MODE_CONNECTOR_DSI);
  1484. if (connector) {
  1485. priv->encoders[priv->num_encoders++] = encoder;
  1486. priv->connectors[priv->num_connectors++] = connector;
  1487. } else {
  1488. SDE_ERROR("dsi %d connector init failed\n", i);
  1489. dsi_display_drm_bridge_deinit(display);
  1490. sde_encoder_destroy(encoder);
  1491. continue;
  1492. }
  1493. rc = dsi_display_drm_ext_bridge_init(display,
  1494. encoder, connector);
  1495. if (rc) {
  1496. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1497. dsi_display_drm_bridge_deinit(display);
  1498. sde_connector_destroy(connector);
  1499. sde_encoder_destroy(encoder);
  1500. }
  1501. dsc_count += info.dsc_count;
  1502. mixer_count += info.lm_count;
  1503. }
  1504. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1505. sde_kms->catalog->mixer_count - mixer_count : 0;
  1506. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1507. sde_kms->catalog->dsc_count - dsc_count : 0;
  1508. /* dp */
  1509. for (i = 0; i < sde_kms->dp_display_count &&
  1510. priv->num_encoders < max_encoders; ++i) {
  1511. int idx;
  1512. display = sde_kms->dp_displays[i];
  1513. encoder = NULL;
  1514. memset(&info, 0x0, sizeof(info));
  1515. rc = dp_connector_get_info(NULL, &info, display);
  1516. if (rc) {
  1517. SDE_ERROR("dp get_info %d failed\n", i);
  1518. continue;
  1519. }
  1520. encoder = sde_encoder_init(dev, &info);
  1521. if (IS_ERR_OR_NULL(encoder)) {
  1522. SDE_ERROR("dp encoder init failed %d\n", i);
  1523. continue;
  1524. }
  1525. rc = dp_drm_bridge_init(display, encoder,
  1526. max_dp_mixer_count, max_dp_dsc_count);
  1527. if (rc) {
  1528. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1529. sde_encoder_destroy(encoder);
  1530. continue;
  1531. }
  1532. connector = sde_connector_init(dev,
  1533. encoder,
  1534. NULL,
  1535. display,
  1536. &dp_ops,
  1537. DRM_CONNECTOR_POLL_HPD,
  1538. DRM_MODE_CONNECTOR_DisplayPort);
  1539. if (connector) {
  1540. priv->encoders[priv->num_encoders++] = encoder;
  1541. priv->connectors[priv->num_connectors++] = connector;
  1542. } else {
  1543. SDE_ERROR("dp %d connector init failed\n", i);
  1544. dp_drm_bridge_deinit(display);
  1545. sde_encoder_destroy(encoder);
  1546. }
  1547. /* update display cap to MST_MODE for DP MST encoders */
  1548. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1549. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1550. priv->num_encoders < max_encoders; idx++) {
  1551. info.h_tile_instance[0] = idx;
  1552. encoder = sde_encoder_init(dev, &info);
  1553. if (IS_ERR_OR_NULL(encoder)) {
  1554. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1555. continue;
  1556. }
  1557. rc = dp_mst_drm_bridge_init(display, encoder);
  1558. if (rc) {
  1559. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1560. i, rc);
  1561. sde_encoder_destroy(encoder);
  1562. continue;
  1563. }
  1564. priv->encoders[priv->num_encoders++] = encoder;
  1565. }
  1566. }
  1567. return 0;
  1568. }
  1569. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1570. {
  1571. struct msm_drm_private *priv;
  1572. int i;
  1573. if (!sde_kms) {
  1574. SDE_ERROR("invalid sde_kms\n");
  1575. return;
  1576. } else if (!sde_kms->dev) {
  1577. SDE_ERROR("invalid dev\n");
  1578. return;
  1579. } else if (!sde_kms->dev->dev_private) {
  1580. SDE_ERROR("invalid dev_private\n");
  1581. return;
  1582. }
  1583. priv = sde_kms->dev->dev_private;
  1584. for (i = 0; i < priv->num_crtcs; i++)
  1585. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1586. priv->num_crtcs = 0;
  1587. for (i = 0; i < priv->num_planes; i++)
  1588. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1589. priv->num_planes = 0;
  1590. for (i = 0; i < priv->num_connectors; i++)
  1591. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1592. priv->num_connectors = 0;
  1593. for (i = 0; i < priv->num_encoders; i++)
  1594. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1595. priv->num_encoders = 0;
  1596. _sde_kms_release_displays(sde_kms);
  1597. }
  1598. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1599. {
  1600. struct drm_device *dev;
  1601. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1602. struct drm_crtc *crtc;
  1603. struct msm_drm_private *priv;
  1604. struct sde_mdss_cfg *catalog;
  1605. int primary_planes_idx = 0, i, ret;
  1606. int max_crtc_count;
  1607. u32 sspp_id[MAX_PLANES];
  1608. u32 master_plane_id[MAX_PLANES];
  1609. u32 num_virt_planes = 0;
  1610. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1611. SDE_ERROR("invalid sde_kms\n");
  1612. return -EINVAL;
  1613. }
  1614. dev = sde_kms->dev;
  1615. priv = dev->dev_private;
  1616. catalog = sde_kms->catalog;
  1617. ret = sde_core_irq_domain_add(sde_kms);
  1618. if (ret)
  1619. goto fail_irq;
  1620. /*
  1621. * Query for underlying display drivers, and create connectors,
  1622. * bridges and encoders for them.
  1623. */
  1624. if (!_sde_kms_get_displays(sde_kms))
  1625. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1626. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1627. /* Create the planes */
  1628. for (i = 0; i < catalog->sspp_count; i++) {
  1629. bool primary = true;
  1630. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1631. || primary_planes_idx >= max_crtc_count)
  1632. primary = false;
  1633. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1634. (1UL << max_crtc_count) - 1, 0);
  1635. if (IS_ERR(plane)) {
  1636. SDE_ERROR("sde_plane_init failed\n");
  1637. ret = PTR_ERR(plane);
  1638. goto fail;
  1639. }
  1640. priv->planes[priv->num_planes++] = plane;
  1641. if (primary)
  1642. primary_planes[primary_planes_idx++] = plane;
  1643. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1644. sde_is_custom_client()) {
  1645. int priority =
  1646. catalog->sspp[i].sblk->smart_dma_priority;
  1647. sspp_id[priority - 1] = catalog->sspp[i].id;
  1648. master_plane_id[priority - 1] = plane->base.id;
  1649. num_virt_planes++;
  1650. }
  1651. }
  1652. /* Initialize smart DMA virtual planes */
  1653. for (i = 0; i < num_virt_planes; i++) {
  1654. plane = sde_plane_init(dev, sspp_id[i], false,
  1655. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1656. if (IS_ERR(plane)) {
  1657. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1658. ret = PTR_ERR(plane);
  1659. goto fail;
  1660. }
  1661. priv->planes[priv->num_planes++] = plane;
  1662. }
  1663. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1664. /* Create one CRTC per encoder */
  1665. for (i = 0; i < max_crtc_count; i++) {
  1666. crtc = sde_crtc_init(dev, primary_planes[i]);
  1667. if (IS_ERR(crtc)) {
  1668. ret = PTR_ERR(crtc);
  1669. goto fail;
  1670. }
  1671. priv->crtcs[priv->num_crtcs++] = crtc;
  1672. }
  1673. if (sde_is_custom_client()) {
  1674. /* All CRTCs are compatible with all planes */
  1675. for (i = 0; i < priv->num_planes; i++)
  1676. priv->planes[i]->possible_crtcs =
  1677. (1 << priv->num_crtcs) - 1;
  1678. }
  1679. /* All CRTCs are compatible with all encoders */
  1680. for (i = 0; i < priv->num_encoders; i++)
  1681. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1682. return 0;
  1683. fail:
  1684. _sde_kms_drm_obj_destroy(sde_kms);
  1685. fail_irq:
  1686. sde_core_irq_domain_fini(sde_kms);
  1687. return ret;
  1688. }
  1689. /**
  1690. * sde_kms_timeline_status - provides current timeline status
  1691. * This API should be called without mode config lock.
  1692. * @dev: Pointer to drm device
  1693. */
  1694. void sde_kms_timeline_status(struct drm_device *dev)
  1695. {
  1696. struct drm_crtc *crtc;
  1697. struct drm_connector *conn;
  1698. struct drm_connector_list_iter conn_iter;
  1699. if (!dev) {
  1700. SDE_ERROR("invalid drm device node\n");
  1701. return;
  1702. }
  1703. drm_for_each_crtc(crtc, dev)
  1704. sde_crtc_timeline_status(crtc);
  1705. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1706. /*
  1707. *Probably locked from last close dumping status anyway
  1708. */
  1709. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1710. drm_connector_list_iter_begin(dev, &conn_iter);
  1711. drm_for_each_connector_iter(conn, &conn_iter)
  1712. sde_conn_timeline_status(conn);
  1713. drm_connector_list_iter_end(&conn_iter);
  1714. return;
  1715. }
  1716. mutex_lock(&dev->mode_config.mutex);
  1717. drm_connector_list_iter_begin(dev, &conn_iter);
  1718. drm_for_each_connector_iter(conn, &conn_iter)
  1719. sde_conn_timeline_status(conn);
  1720. drm_connector_list_iter_end(&conn_iter);
  1721. mutex_unlock(&dev->mode_config.mutex);
  1722. }
  1723. static int sde_kms_postinit(struct msm_kms *kms)
  1724. {
  1725. struct sde_kms *sde_kms = to_sde_kms(kms);
  1726. struct drm_device *dev;
  1727. struct drm_crtc *crtc;
  1728. int rc;
  1729. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1730. SDE_ERROR("invalid sde_kms\n");
  1731. return -EINVAL;
  1732. }
  1733. dev = sde_kms->dev;
  1734. rc = _sde_debugfs_init(sde_kms);
  1735. if (rc)
  1736. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1737. drm_for_each_crtc(crtc, dev)
  1738. sde_crtc_post_init(dev, crtc);
  1739. return rc;
  1740. }
  1741. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1742. struct drm_encoder *encoder)
  1743. {
  1744. return rate;
  1745. }
  1746. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1747. struct platform_device *pdev)
  1748. {
  1749. struct drm_device *dev;
  1750. struct msm_drm_private *priv;
  1751. int i;
  1752. if (!sde_kms || !pdev)
  1753. return;
  1754. dev = sde_kms->dev;
  1755. if (!dev)
  1756. return;
  1757. priv = dev->dev_private;
  1758. if (!priv)
  1759. return;
  1760. if (sde_kms->genpd_init) {
  1761. sde_kms->genpd_init = false;
  1762. pm_genpd_remove(&sde_kms->genpd);
  1763. of_genpd_del_provider(pdev->dev.of_node);
  1764. }
  1765. if (sde_kms->vm && sde_kms->vm->vm_ops.vm_deinit)
  1766. sde_kms->vm->vm_ops.vm_deinit(sde_kms, &sde_kms->vm->vm_ops);
  1767. if (sde_kms->hw_intr)
  1768. sde_hw_intr_destroy(sde_kms->hw_intr);
  1769. sde_kms->hw_intr = NULL;
  1770. if (sde_kms->power_event)
  1771. sde_power_handle_unregister_event(
  1772. &priv->phandle, sde_kms->power_event);
  1773. _sde_kms_release_displays(sde_kms);
  1774. _sde_kms_unmap_all_splash_regions(sde_kms);
  1775. if (sde_kms->catalog) {
  1776. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1777. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1778. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1779. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1780. }
  1781. }
  1782. if (sde_kms->rm_init)
  1783. sde_rm_destroy(&sde_kms->rm);
  1784. sde_kms->rm_init = false;
  1785. if (sde_kms->catalog)
  1786. sde_hw_catalog_deinit(sde_kms->catalog);
  1787. sde_kms->catalog = NULL;
  1788. if (sde_kms->sid)
  1789. msm_iounmap(pdev, sde_kms->sid);
  1790. sde_kms->sid = NULL;
  1791. if (sde_kms->reg_dma)
  1792. msm_iounmap(pdev, sde_kms->reg_dma);
  1793. sde_kms->reg_dma = NULL;
  1794. if (sde_kms->vbif[VBIF_NRT])
  1795. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1796. sde_kms->vbif[VBIF_NRT] = NULL;
  1797. if (sde_kms->vbif[VBIF_RT])
  1798. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1799. sde_kms->vbif[VBIF_RT] = NULL;
  1800. if (sde_kms->mmio)
  1801. msm_iounmap(pdev, sde_kms->mmio);
  1802. sde_kms->mmio = NULL;
  1803. sde_reg_dma_deinit();
  1804. _sde_kms_mmu_destroy(sde_kms);
  1805. }
  1806. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1807. {
  1808. int i;
  1809. if (!sde_kms)
  1810. return -EINVAL;
  1811. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1812. struct msm_mmu *mmu;
  1813. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1814. if (!aspace)
  1815. continue;
  1816. mmu = sde_kms->aspace[i]->mmu;
  1817. if (secure_only &&
  1818. !aspace->mmu->funcs->is_domain_secure(mmu))
  1819. continue;
  1820. /* cleanup aspace before detaching */
  1821. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1822. SDE_DEBUG("Detaching domain:%d\n", i);
  1823. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1824. ARRAY_SIZE(iommu_ports));
  1825. aspace->domain_attached = false;
  1826. }
  1827. return 0;
  1828. }
  1829. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1830. {
  1831. int i;
  1832. if (!sde_kms)
  1833. return -EINVAL;
  1834. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1835. struct msm_mmu *mmu;
  1836. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1837. if (!aspace)
  1838. continue;
  1839. mmu = sde_kms->aspace[i]->mmu;
  1840. if (secure_only &&
  1841. !aspace->mmu->funcs->is_domain_secure(mmu))
  1842. continue;
  1843. SDE_DEBUG("Attaching domain:%d\n", i);
  1844. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1845. ARRAY_SIZE(iommu_ports));
  1846. aspace->domain_attached = true;
  1847. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1848. }
  1849. return 0;
  1850. }
  1851. static void sde_kms_destroy(struct msm_kms *kms)
  1852. {
  1853. struct sde_kms *sde_kms;
  1854. struct drm_device *dev;
  1855. if (!kms) {
  1856. SDE_ERROR("invalid kms\n");
  1857. return;
  1858. }
  1859. sde_kms = to_sde_kms(kms);
  1860. dev = sde_kms->dev;
  1861. if (!dev || !dev->dev) {
  1862. SDE_ERROR("invalid device\n");
  1863. return;
  1864. }
  1865. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1866. kfree(sde_kms);
  1867. }
  1868. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1869. struct drm_atomic_state *state)
  1870. {
  1871. struct drm_device *dev = sde_kms->dev;
  1872. struct drm_plane *plane;
  1873. struct drm_plane_state *plane_state;
  1874. struct drm_crtc *crtc;
  1875. struct drm_crtc_state *crtc_state;
  1876. struct drm_connector *conn;
  1877. struct drm_connector_state *conn_state;
  1878. struct drm_connector_list_iter conn_iter;
  1879. int ret = 0;
  1880. drm_for_each_plane(plane, dev) {
  1881. plane_state = drm_atomic_get_plane_state(state, plane);
  1882. if (IS_ERR(plane_state)) {
  1883. ret = PTR_ERR(plane_state);
  1884. SDE_ERROR("error %d getting plane %d state\n",
  1885. ret, DRMID(plane));
  1886. return ret;
  1887. }
  1888. ret = sde_plane_helper_reset_custom_properties(plane,
  1889. plane_state);
  1890. if (ret) {
  1891. SDE_ERROR("error %d resetting plane props %d\n",
  1892. ret, DRMID(plane));
  1893. return ret;
  1894. }
  1895. }
  1896. drm_for_each_crtc(crtc, dev) {
  1897. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1898. if (IS_ERR(crtc_state)) {
  1899. ret = PTR_ERR(crtc_state);
  1900. SDE_ERROR("error %d getting crtc %d state\n",
  1901. ret, DRMID(crtc));
  1902. return ret;
  1903. }
  1904. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1905. if (ret) {
  1906. SDE_ERROR("error %d resetting crtc props %d\n",
  1907. ret, DRMID(crtc));
  1908. return ret;
  1909. }
  1910. }
  1911. drm_connector_list_iter_begin(dev, &conn_iter);
  1912. drm_for_each_connector_iter(conn, &conn_iter) {
  1913. conn_state = drm_atomic_get_connector_state(state, conn);
  1914. if (IS_ERR(conn_state)) {
  1915. ret = PTR_ERR(conn_state);
  1916. SDE_ERROR("error %d getting connector %d state\n",
  1917. ret, DRMID(conn));
  1918. return ret;
  1919. }
  1920. ret = sde_connector_helper_reset_custom_properties(conn,
  1921. conn_state);
  1922. if (ret) {
  1923. SDE_ERROR("error %d resetting connector props %d\n",
  1924. ret, DRMID(conn));
  1925. return ret;
  1926. }
  1927. }
  1928. drm_connector_list_iter_end(&conn_iter);
  1929. return ret;
  1930. }
  1931. static void sde_kms_lastclose(struct msm_kms *kms)
  1932. {
  1933. struct sde_kms *sde_kms;
  1934. struct drm_device *dev;
  1935. struct drm_atomic_state *state;
  1936. struct drm_modeset_acquire_ctx ctx;
  1937. int ret;
  1938. if (!kms) {
  1939. SDE_ERROR("invalid argument\n");
  1940. return;
  1941. }
  1942. sde_kms = to_sde_kms(kms);
  1943. dev = sde_kms->dev;
  1944. drm_modeset_acquire_init(&ctx, 0);
  1945. state = drm_atomic_state_alloc(dev);
  1946. if (!state) {
  1947. ret = -ENOMEM;
  1948. goto out_ctx;
  1949. }
  1950. state->acquire_ctx = &ctx;
  1951. retry:
  1952. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1953. if (ret)
  1954. goto out_state;
  1955. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1956. if (ret)
  1957. goto out_state;
  1958. ret = drm_atomic_commit(state);
  1959. out_state:
  1960. if (ret == -EDEADLK)
  1961. goto backoff;
  1962. drm_atomic_state_put(state);
  1963. out_ctx:
  1964. drm_modeset_drop_locks(&ctx);
  1965. drm_modeset_acquire_fini(&ctx);
  1966. if (ret)
  1967. SDE_ERROR("kms lastclose failed: %d\n", ret);
  1968. return;
  1969. backoff:
  1970. drm_atomic_state_clear(state);
  1971. drm_modeset_backoff(&ctx);
  1972. goto retry;
  1973. }
  1974. static int sde_kms_check_vm_request(struct msm_kms *kms,
  1975. struct drm_atomic_state *state)
  1976. {
  1977. struct sde_kms *sde_kms;
  1978. struct drm_device *dev;
  1979. struct drm_crtc *crtc;
  1980. struct drm_crtc_state *new_cstate, *old_cstate;
  1981. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  1982. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  1983. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  1984. struct sde_vm_ops *vm_ops;
  1985. bool vm_req_active = false;
  1986. enum sde_crtc_idle_pc_state idle_pc_state;
  1987. int rc = 0;
  1988. if (!kms || !state)
  1989. return -EINVAL;
  1990. sde_kms = to_sde_kms(kms);
  1991. dev = sde_kms->dev;
  1992. if (!sde_kms->vm)
  1993. return 0;
  1994. vm_ops = &sde_kms->vm->vm_ops;
  1995. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  1996. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  1997. new_state = to_sde_crtc_state(new_cstate);
  1998. if (!new_cstate->active && !new_cstate->active_changed)
  1999. continue;
  2000. new_vm_req = sde_crtc_get_property(new_state,
  2001. CRTC_PROP_VM_REQ_STATE);
  2002. commit_crtc_cnt++;
  2003. if (old_cstate) {
  2004. old_state = to_sde_crtc_state(old_cstate);
  2005. old_vm_req = sde_crtc_get_property(old_state,
  2006. CRTC_PROP_VM_REQ_STATE);
  2007. }
  2008. /**
  2009. * No active request if the transition is from
  2010. * VM_REQ_NONE to VM_REQ_NONE
  2011. */
  2012. if (new_vm_req || (old_state && old_vm_req))
  2013. vm_req_active = true;
  2014. idle_pc_state = sde_crtc_get_property(new_state,
  2015. CRTC_PROP_IDLE_PC_STATE);
  2016. active_crtc = crtc;
  2017. }
  2018. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2019. if (!crtc->state->active)
  2020. continue;
  2021. global_crtc_cnt++;
  2022. global_active_crtc = crtc;
  2023. }
  2024. /* Check for single crtc commits only on valid VM requests */
  2025. if (vm_req_active && active_crtc && global_active_crtc &&
  2026. (commit_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2027. global_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2028. active_crtc != global_active_crtc)) {
  2029. SDE_ERROR(
  2030. "failed to switch VM due to CRTC concurrencies: MAX_CNT: %d active_cnt: %d global_cnt: %d active_crtc: %d global_crtc: %d\n",
  2031. sde_kms->catalog->max_trusted_vm_displays,
  2032. commit_crtc_cnt, global_crtc_cnt, active_crtc,
  2033. global_active_crtc);
  2034. return -E2BIG;
  2035. }
  2036. if (!vm_req_active)
  2037. return 0;
  2038. /* disable idle-pc before releasing the HW */
  2039. if ((new_vm_req == VM_REQ_RELEASE) &&
  2040. (idle_pc_state == IDLE_PC_ENABLE)) {
  2041. SDE_ERROR("failed to switch VM since idle-pc is enabled\n");
  2042. return -EINVAL;
  2043. }
  2044. mutex_lock(&sde_kms->vm->vm_res_lock);
  2045. if (vm_ops->vm_request_valid)
  2046. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2047. if (rc)
  2048. SDE_ERROR(
  2049. "failed to complete vm transition request. old_state = %d, new_state = %d, hw_ownership: %d\n",
  2050. old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2051. mutex_unlock(&sde_kms->vm->vm_res_lock);
  2052. return rc;
  2053. }
  2054. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2055. struct drm_atomic_state *state)
  2056. {
  2057. struct sde_kms *sde_kms;
  2058. struct drm_device *dev;
  2059. struct drm_crtc *crtc;
  2060. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2061. struct drm_crtc_state *crtc_state;
  2062. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2063. bool sec_session = false, global_sec_session = false;
  2064. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2065. int i;
  2066. if (!kms || !state) {
  2067. return -EINVAL;
  2068. SDE_ERROR("invalid arguments\n");
  2069. }
  2070. sde_kms = to_sde_kms(kms);
  2071. dev = sde_kms->dev;
  2072. /* iterate state object for active secure/non-secure crtc */
  2073. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2074. if (!crtc_state->active)
  2075. continue;
  2076. active_crtc_cnt++;
  2077. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2078. &fb_sec, &fb_sec_dir);
  2079. if (fb_sec_dir)
  2080. sec_session = true;
  2081. cur_crtc = crtc;
  2082. }
  2083. /* iterate global list for active and secure/non-secure crtc */
  2084. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2085. if (!crtc->state->active)
  2086. continue;
  2087. global_active_crtc_cnt++;
  2088. /* update only when crtc is not the same as current crtc */
  2089. if (crtc != cur_crtc) {
  2090. fb_ns = fb_sec = fb_sec_dir = 0;
  2091. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2092. &fb_sec, &fb_sec_dir);
  2093. if (fb_sec_dir)
  2094. global_sec_session = true;
  2095. global_crtc = crtc;
  2096. }
  2097. }
  2098. if (!global_sec_session && !sec_session)
  2099. return 0;
  2100. /*
  2101. * - fail crtc commit, if secure-camera/secure-ui session is
  2102. * in-progress in any other display
  2103. * - fail secure-camera/secure-ui crtc commit, if any other display
  2104. * session is in-progress
  2105. */
  2106. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2107. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2108. SDE_ERROR(
  2109. "crtc%d secure check failed global_active:%d active:%d\n",
  2110. cur_crtc ? cur_crtc->base.id : -1,
  2111. global_active_crtc_cnt, active_crtc_cnt);
  2112. return -EPERM;
  2113. /*
  2114. * As only one crtc is allowed during secure session, the crtc
  2115. * in this commit should match with the global crtc
  2116. */
  2117. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2118. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2119. cur_crtc->base.id, sec_session,
  2120. global_crtc->base.id, global_sec_session);
  2121. return -EPERM;
  2122. }
  2123. return 0;
  2124. }
  2125. static int sde_kms_atomic_check(struct msm_kms *kms,
  2126. struct drm_atomic_state *state)
  2127. {
  2128. struct sde_kms *sde_kms;
  2129. struct drm_device *dev;
  2130. int ret;
  2131. if (!kms || !state)
  2132. return -EINVAL;
  2133. sde_kms = to_sde_kms(kms);
  2134. dev = sde_kms->dev;
  2135. SDE_ATRACE_BEGIN("atomic_check");
  2136. if (sde_kms_is_suspend_blocked(dev)) {
  2137. SDE_DEBUG("suspended, skip atomic_check\n");
  2138. ret = -EBUSY;
  2139. goto end;
  2140. }
  2141. ret = drm_atomic_helper_check(dev, state);
  2142. if (ret)
  2143. goto end;
  2144. /*
  2145. * Check if any secure transition(moving CRTC between secure and
  2146. * non-secure state and vice-versa) is allowed or not. when moving
  2147. * to secure state, planes with fb_mode set to dir_translated only can
  2148. * be staged on the CRTC, and only one CRTC can be active during
  2149. * Secure state
  2150. */
  2151. ret = sde_kms_check_secure_transition(kms, state);
  2152. if (ret)
  2153. goto end;
  2154. ret = sde_kms_check_vm_request(kms, state);
  2155. if (ret)
  2156. SDE_ERROR("vm switch request checks failed\n");
  2157. end:
  2158. SDE_ATRACE_END("atomic_check");
  2159. return ret;
  2160. }
  2161. static struct msm_gem_address_space*
  2162. _sde_kms_get_address_space(struct msm_kms *kms,
  2163. unsigned int domain)
  2164. {
  2165. struct sde_kms *sde_kms;
  2166. if (!kms) {
  2167. SDE_ERROR("invalid kms\n");
  2168. return NULL;
  2169. }
  2170. sde_kms = to_sde_kms(kms);
  2171. if (!sde_kms) {
  2172. SDE_ERROR("invalid sde_kms\n");
  2173. return NULL;
  2174. }
  2175. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2176. return NULL;
  2177. return (sde_kms->aspace[domain] &&
  2178. sde_kms->aspace[domain]->domain_attached) ?
  2179. sde_kms->aspace[domain] : NULL;
  2180. }
  2181. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2182. unsigned int domain)
  2183. {
  2184. struct sde_kms *sde_kms;
  2185. struct msm_gem_address_space *aspace;
  2186. if (!kms) {
  2187. SDE_ERROR("invalid kms\n");
  2188. return NULL;
  2189. }
  2190. sde_kms = to_sde_kms(kms);
  2191. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2192. SDE_ERROR("invalid params\n");
  2193. return NULL;
  2194. }
  2195. aspace = _sde_kms_get_address_space(kms, domain);
  2196. return (aspace && aspace->domain_attached) ?
  2197. msm_gem_get_aspace_device(aspace) : NULL;
  2198. }
  2199. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2200. {
  2201. struct drm_device *dev = NULL;
  2202. struct sde_kms *sde_kms = NULL;
  2203. struct drm_connector *connector = NULL;
  2204. struct drm_connector_list_iter conn_iter;
  2205. struct sde_connector *sde_conn = NULL;
  2206. if (!kms) {
  2207. SDE_ERROR("invalid kms\n");
  2208. return;
  2209. }
  2210. sde_kms = to_sde_kms(kms);
  2211. dev = sde_kms->dev;
  2212. if (!dev) {
  2213. SDE_ERROR("invalid device\n");
  2214. return;
  2215. }
  2216. if (!dev->mode_config.poll_enabled)
  2217. return;
  2218. mutex_lock(&dev->mode_config.mutex);
  2219. drm_connector_list_iter_begin(dev, &conn_iter);
  2220. drm_for_each_connector_iter(connector, &conn_iter) {
  2221. /* Only handle HPD capable connectors. */
  2222. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2223. continue;
  2224. sde_conn = to_sde_connector(connector);
  2225. if (sde_conn->ops.post_open)
  2226. sde_conn->ops.post_open(&sde_conn->base,
  2227. sde_conn->display);
  2228. }
  2229. drm_connector_list_iter_end(&conn_iter);
  2230. mutex_unlock(&dev->mode_config.mutex);
  2231. }
  2232. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2233. struct sde_splash_display *splash_display,
  2234. struct drm_crtc *crtc)
  2235. {
  2236. struct msm_drm_private *priv;
  2237. struct drm_plane *plane;
  2238. struct sde_splash_mem *splash;
  2239. enum sde_sspp plane_id;
  2240. bool is_virtual;
  2241. int i, j;
  2242. if (!sde_kms || !splash_display || !crtc) {
  2243. SDE_ERROR("invalid input args\n");
  2244. return -EINVAL;
  2245. }
  2246. priv = sde_kms->dev->dev_private;
  2247. for (i = 0; i < priv->num_planes; i++) {
  2248. plane = priv->planes[i];
  2249. plane_id = sde_plane_pipe(plane);
  2250. is_virtual = is_sde_plane_virtual(plane);
  2251. splash = splash_display->splash;
  2252. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2253. if ((plane_id != splash_display->pipes[j].sspp) ||
  2254. (splash_display->pipes[j].is_virtual
  2255. != is_virtual))
  2256. continue;
  2257. if (splash && sde_plane_validate_src_addr(plane,
  2258. splash->splash_buf_base,
  2259. splash->splash_buf_size)) {
  2260. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2261. plane_id, crtc->base.id);
  2262. }
  2263. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2264. crtc->base.id, plane_id, is_virtual);
  2265. }
  2266. }
  2267. return 0;
  2268. }
  2269. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2270. struct sde_kms *sde_kms, struct drm_connector *connector,
  2271. u32 display_idx)
  2272. {
  2273. struct drm_display_mode *drm_mode = NULL, *curr_mode = NULL;
  2274. u32 i = 0, mode_index;
  2275. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2276. /* currently consider modes[0] as the preferred mode */
  2277. curr_mode = list_first_entry(&connector->modes,
  2278. struct drm_display_mode, head);
  2279. } else if (sde_kms->hw_mdp && sde_kms->hw_mdp->ops.get_mode_index) {
  2280. mode_index = sde_kms->hw_mdp->ops.get_mode_index(
  2281. sde_kms->hw_mdp, display_idx);
  2282. list_for_each_entry(drm_mode, &connector->modes, head) {
  2283. if (mode_index == i) {
  2284. curr_mode = drm_mode;
  2285. break;
  2286. }
  2287. i++;
  2288. }
  2289. }
  2290. return curr_mode;
  2291. }
  2292. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  2293. {
  2294. void *display;
  2295. struct dsi_display *dsi_display;
  2296. struct msm_display_info info;
  2297. struct drm_encoder *encoder = NULL;
  2298. struct drm_crtc *crtc = NULL;
  2299. int i, rc = 0;
  2300. struct drm_display_mode *drm_mode = NULL;
  2301. struct drm_device *dev;
  2302. struct msm_drm_private *priv;
  2303. struct sde_kms *sde_kms;
  2304. struct drm_connector_list_iter conn_iter;
  2305. struct drm_connector *connector = NULL;
  2306. struct sde_connector *sde_conn = NULL;
  2307. struct sde_splash_display *splash_display;
  2308. if (!kms) {
  2309. SDE_ERROR("invalid kms\n");
  2310. return -EINVAL;
  2311. }
  2312. sde_kms = to_sde_kms(kms);
  2313. dev = sde_kms->dev;
  2314. if (!dev) {
  2315. SDE_ERROR("invalid device\n");
  2316. return -EINVAL;
  2317. }
  2318. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2319. && (!sde_kms->splash_data.num_splash_regions)) ||
  2320. !sde_kms->splash_data.num_splash_displays) {
  2321. DRM_INFO("cont_splash feature not enabled\n");
  2322. return rc;
  2323. }
  2324. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2325. sde_kms->splash_data.num_splash_displays,
  2326. sde_kms->dsi_display_count);
  2327. /* dsi */
  2328. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2329. display = sde_kms->dsi_displays[i];
  2330. dsi_display = (struct dsi_display *)display;
  2331. splash_display = &sde_kms->splash_data.splash_display[i];
  2332. if (!splash_display->cont_splash_enabled) {
  2333. SDE_DEBUG("display->name = %s splash not enabled\n",
  2334. dsi_display->name);
  2335. continue;
  2336. }
  2337. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2338. if (dsi_display->bridge->base.encoder) {
  2339. encoder = dsi_display->bridge->base.encoder;
  2340. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2341. }
  2342. memset(&info, 0x0, sizeof(info));
  2343. rc = dsi_display_get_info(NULL, &info, display);
  2344. if (rc) {
  2345. SDE_ERROR("dsi get_info %d failed\n", i);
  2346. encoder = NULL;
  2347. continue;
  2348. }
  2349. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2350. ((info.is_connected) ? "true" : "false"),
  2351. info.display_type);
  2352. if (!encoder) {
  2353. SDE_ERROR("encoder not initialized\n");
  2354. return -EINVAL;
  2355. }
  2356. priv = sde_kms->dev->dev_private;
  2357. encoder->crtc = priv->crtcs[i];
  2358. crtc = encoder->crtc;
  2359. splash_display->encoder = encoder;
  2360. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2361. i, crtc->base.id, encoder->base.id);
  2362. mutex_lock(&dev->mode_config.mutex);
  2363. drm_connector_list_iter_begin(dev, &conn_iter);
  2364. drm_for_each_connector_iter(connector, &conn_iter) {
  2365. /**
  2366. * SDE_KMS doesn't attach more than one encoder to
  2367. * a DSI connector. So it is safe to check only with
  2368. * the first encoder entry. Revisit this logic if we
  2369. * ever have to support continuous splash for
  2370. * external displays in MST configuration.
  2371. */
  2372. if (connector->encoder_ids[0] == encoder->base.id)
  2373. break;
  2374. }
  2375. drm_connector_list_iter_end(&conn_iter);
  2376. if (!connector) {
  2377. SDE_ERROR("connector not initialized\n");
  2378. mutex_unlock(&dev->mode_config.mutex);
  2379. return -EINVAL;
  2380. }
  2381. if (connector->funcs->fill_modes) {
  2382. connector->funcs->fill_modes(connector,
  2383. dev->mode_config.max_width,
  2384. dev->mode_config.max_height);
  2385. } else {
  2386. SDE_ERROR("fill_modes api not defined\n");
  2387. mutex_unlock(&dev->mode_config.mutex);
  2388. return -EINVAL;
  2389. }
  2390. mutex_unlock(&dev->mode_config.mutex);
  2391. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2392. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, i);
  2393. if (!drm_mode) {
  2394. SDE_ERROR("invalid drm-mode type:%d, index:%d\n",
  2395. sde_kms->splash_data.type, i);
  2396. return -EINVAL;
  2397. }
  2398. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2399. drm_mode->name, drm_mode->type,
  2400. drm_mode->flags);
  2401. /* Update CRTC drm structure */
  2402. crtc->state->active = true;
  2403. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2404. if (rc) {
  2405. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2406. return rc;
  2407. }
  2408. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2409. drm_mode_copy(&crtc->mode, drm_mode);
  2410. /* Update encoder structure */
  2411. sde_encoder_update_caps_for_cont_splash(encoder,
  2412. splash_display, true);
  2413. sde_crtc_update_cont_splash_settings(crtc);
  2414. sde_conn = to_sde_connector(connector);
  2415. if (sde_conn && sde_conn->ops.cont_splash_config)
  2416. sde_conn->ops.cont_splash_config(sde_conn->display);
  2417. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2418. splash_display, crtc);
  2419. if (rc) {
  2420. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2421. return rc;
  2422. }
  2423. }
  2424. return rc;
  2425. }
  2426. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2427. {
  2428. struct sde_kms *sde_kms;
  2429. if (!kms) {
  2430. SDE_ERROR("invalid kms\n");
  2431. return false;
  2432. }
  2433. sde_kms = to_sde_kms(kms);
  2434. return sde_kms->splash_data.num_splash_displays;
  2435. }
  2436. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2437. const struct drm_display_mode *mode,
  2438. const struct msm_resource_caps_info *res, u32 *num_lm)
  2439. {
  2440. struct sde_kms *sde_kms;
  2441. s64 mode_clock_hz = 0;
  2442. s64 max_mdp_clock_hz = 0;
  2443. s64 max_lm_width = 0;
  2444. s64 hdisplay_fp = 0;
  2445. s64 htotal_fp = 0;
  2446. s64 vtotal_fp = 0;
  2447. s64 vrefresh_fp = 0;
  2448. s64 mdp_fudge_factor = 0;
  2449. s64 num_lm_fp = 0;
  2450. s64 lm_clk_fp = 0;
  2451. s64 lm_width_fp = 0;
  2452. int rc = 0;
  2453. if (!num_lm) {
  2454. SDE_ERROR("invalid num_lm pointer\n");
  2455. return -EINVAL;
  2456. }
  2457. /* default to 1 layer mixer */
  2458. *num_lm = 1;
  2459. if (!kms || !mode || !res) {
  2460. SDE_ERROR("invalid input args\n");
  2461. return -EINVAL;
  2462. }
  2463. sde_kms = to_sde_kms(kms);
  2464. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2465. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2466. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2467. htotal_fp = drm_int2fixp(mode->htotal);
  2468. vtotal_fp = drm_int2fixp(mode->vtotal);
  2469. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2470. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2471. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2472. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2473. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2474. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2475. if (mode_clock_hz > max_mdp_clock_hz ||
  2476. hdisplay_fp > max_lm_width) {
  2477. *num_lm = 0;
  2478. do {
  2479. *num_lm += 2;
  2480. num_lm_fp = drm_int2fixp(*num_lm);
  2481. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2482. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2483. if (*num_lm > 4) {
  2484. rc = -EINVAL;
  2485. goto error;
  2486. }
  2487. } while (lm_clk_fp > max_mdp_clock_hz ||
  2488. lm_width_fp > max_lm_width);
  2489. mode_clock_hz = lm_clk_fp;
  2490. }
  2491. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2492. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2493. *num_lm, drm_fixp2int(mode_clock_hz),
  2494. sde_kms->perf.max_core_clk_rate);
  2495. return 0;
  2496. error:
  2497. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2498. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2499. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2500. *num_lm, drm_fixp2int(mode_clock_hz),
  2501. sde_kms->perf.max_core_clk_rate);
  2502. return rc;
  2503. }
  2504. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2505. u32 hdisplay, u32 *num_dsc)
  2506. {
  2507. struct sde_kms *sde_kms;
  2508. uint32_t max_dsc_width;
  2509. if (!num_dsc) {
  2510. SDE_ERROR("invalid num_dsc pointer\n");
  2511. return -EINVAL;
  2512. }
  2513. *num_dsc = 0;
  2514. if (!kms || !hdisplay) {
  2515. SDE_ERROR("invalid input args\n");
  2516. return -EINVAL;
  2517. }
  2518. sde_kms = to_sde_kms(kms);
  2519. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2520. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2521. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2522. hdisplay, max_dsc_width,
  2523. *num_dsc);
  2524. return 0;
  2525. }
  2526. static void _sde_kms_null_commit(struct drm_device *dev,
  2527. struct drm_encoder *enc)
  2528. {
  2529. struct drm_modeset_acquire_ctx ctx;
  2530. struct drm_connector *conn = NULL;
  2531. struct drm_connector *tmp_conn = NULL;
  2532. struct drm_connector_list_iter conn_iter;
  2533. struct drm_atomic_state *state = NULL;
  2534. struct drm_crtc_state *crtc_state = NULL;
  2535. struct drm_connector_state *conn_state = NULL;
  2536. int retry_cnt = 0;
  2537. int ret = 0;
  2538. drm_modeset_acquire_init(&ctx, 0);
  2539. retry:
  2540. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2541. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2542. drm_modeset_backoff(&ctx);
  2543. retry_cnt++;
  2544. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2545. goto retry;
  2546. } else if (WARN_ON(ret)) {
  2547. goto end;
  2548. }
  2549. state = drm_atomic_state_alloc(dev);
  2550. if (!state) {
  2551. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2552. goto end;
  2553. }
  2554. state->acquire_ctx = &ctx;
  2555. drm_connector_list_iter_begin(dev, &conn_iter);
  2556. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2557. if (enc == tmp_conn->state->best_encoder) {
  2558. conn = tmp_conn;
  2559. break;
  2560. }
  2561. }
  2562. drm_connector_list_iter_end(&conn_iter);
  2563. if (!conn) {
  2564. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2565. goto end;
  2566. }
  2567. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2568. conn_state = drm_atomic_get_connector_state(state, conn);
  2569. if (IS_ERR(conn_state)) {
  2570. SDE_ERROR("error %d getting connector %d state\n",
  2571. ret, DRMID(conn));
  2572. goto end;
  2573. }
  2574. crtc_state->active = true;
  2575. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2576. if (ret)
  2577. SDE_ERROR("error %d setting the crtc\n", ret);
  2578. ret = drm_atomic_commit(state);
  2579. if (ret)
  2580. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2581. end:
  2582. if (state)
  2583. drm_atomic_state_put(state);
  2584. drm_modeset_drop_locks(&ctx);
  2585. drm_modeset_acquire_fini(&ctx);
  2586. }
  2587. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2588. const int32_t connector_id)
  2589. {
  2590. struct drm_connector_list_iter conn_iter;
  2591. struct drm_connector *conn;
  2592. struct drm_encoder *drm_enc;
  2593. drm_connector_list_iter_begin(dev, &conn_iter);
  2594. drm_for_each_connector_iter(conn, &conn_iter) {
  2595. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2596. connector_id != conn->base.id)
  2597. continue;
  2598. if (conn->state && conn->state->best_encoder)
  2599. drm_enc = conn->state->best_encoder;
  2600. else
  2601. drm_enc = conn->encoder;
  2602. sde_encoder_early_wakeup(drm_enc);
  2603. }
  2604. drm_connector_list_iter_end(&conn_iter);
  2605. }
  2606. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2607. struct device *dev)
  2608. {
  2609. int i, ret, crtc_id = 0;
  2610. struct drm_device *ddev = dev_get_drvdata(dev);
  2611. struct drm_connector *conn;
  2612. struct drm_connector_list_iter conn_iter;
  2613. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2614. drm_connector_list_iter_begin(ddev, &conn_iter);
  2615. drm_for_each_connector_iter(conn, &conn_iter) {
  2616. uint64_t lp;
  2617. lp = sde_connector_get_lp(conn);
  2618. if (lp != SDE_MODE_DPMS_LP2)
  2619. continue;
  2620. if (sde_encoder_in_clone_mode(conn->encoder))
  2621. continue;
  2622. ret = sde_encoder_wait_for_event(conn->encoder,
  2623. MSM_ENC_TX_COMPLETE);
  2624. if (ret && ret != -EWOULDBLOCK) {
  2625. SDE_ERROR(
  2626. "[conn: %d] wait for commit done returned %d\n",
  2627. conn->base.id, ret);
  2628. } else if (!ret) {
  2629. crtc_id = drm_crtc_index(conn->state->crtc);
  2630. if (priv->event_thread[crtc_id].thread)
  2631. kthread_flush_worker(
  2632. &priv->event_thread[crtc_id].worker);
  2633. sde_encoder_idle_request(conn->encoder);
  2634. }
  2635. }
  2636. drm_connector_list_iter_end(&conn_iter);
  2637. for (i = 0; i < priv->num_crtcs; i++) {
  2638. if (priv->disp_thread[i].thread)
  2639. kthread_flush_worker(
  2640. &priv->disp_thread[i].worker);
  2641. if (priv->event_thread[i].thread)
  2642. kthread_flush_worker(
  2643. &priv->event_thread[i].worker);
  2644. }
  2645. kthread_flush_worker(&priv->pp_event_worker);
  2646. }
  2647. static int sde_kms_pm_suspend(struct device *dev)
  2648. {
  2649. struct drm_device *ddev;
  2650. struct drm_modeset_acquire_ctx ctx;
  2651. struct drm_connector *conn;
  2652. struct drm_encoder *enc;
  2653. struct drm_connector_list_iter conn_iter;
  2654. struct drm_atomic_state *state = NULL;
  2655. struct sde_kms *sde_kms;
  2656. int ret = 0, num_crtcs = 0;
  2657. if (!dev)
  2658. return -EINVAL;
  2659. ddev = dev_get_drvdata(dev);
  2660. if (!ddev || !ddev_to_msm_kms(ddev))
  2661. return -EINVAL;
  2662. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2663. SDE_EVT32(0);
  2664. /* disable hot-plug polling */
  2665. drm_kms_helper_poll_disable(ddev);
  2666. /* if a display stuck in CS trigger a null commit to complete handoff */
  2667. drm_for_each_encoder(enc, ddev) {
  2668. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2669. _sde_kms_null_commit(ddev, enc);
  2670. }
  2671. /* acquire modeset lock(s) */
  2672. drm_modeset_acquire_init(&ctx, 0);
  2673. retry:
  2674. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2675. if (ret)
  2676. goto unlock;
  2677. /* save current state for resume */
  2678. if (sde_kms->suspend_state)
  2679. drm_atomic_state_put(sde_kms->suspend_state);
  2680. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2681. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2682. ret = PTR_ERR(sde_kms->suspend_state);
  2683. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2684. sde_kms->suspend_state = NULL;
  2685. goto unlock;
  2686. }
  2687. /* create atomic state to disable all CRTCs */
  2688. state = drm_atomic_state_alloc(ddev);
  2689. if (!state) {
  2690. ret = -ENOMEM;
  2691. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2692. goto unlock;
  2693. }
  2694. state->acquire_ctx = &ctx;
  2695. drm_connector_list_iter_begin(ddev, &conn_iter);
  2696. drm_for_each_connector_iter(conn, &conn_iter) {
  2697. struct drm_crtc_state *crtc_state;
  2698. uint64_t lp;
  2699. if (!conn->state || !conn->state->crtc ||
  2700. conn->dpms != DRM_MODE_DPMS_ON ||
  2701. sde_encoder_in_clone_mode(conn->encoder))
  2702. continue;
  2703. lp = sde_connector_get_lp(conn);
  2704. if (lp == SDE_MODE_DPMS_LP1) {
  2705. /* transition LP1->LP2 on pm suspend */
  2706. ret = sde_connector_set_property_for_commit(conn, state,
  2707. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2708. if (ret) {
  2709. DRM_ERROR("failed to set lp2 for conn %d\n",
  2710. conn->base.id);
  2711. drm_connector_list_iter_end(&conn_iter);
  2712. goto unlock;
  2713. }
  2714. }
  2715. if (lp != SDE_MODE_DPMS_LP2) {
  2716. /* force CRTC to be inactive */
  2717. crtc_state = drm_atomic_get_crtc_state(state,
  2718. conn->state->crtc);
  2719. if (IS_ERR_OR_NULL(crtc_state)) {
  2720. DRM_ERROR("failed to get crtc %d state\n",
  2721. conn->state->crtc->base.id);
  2722. drm_connector_list_iter_end(&conn_iter);
  2723. goto unlock;
  2724. }
  2725. if (lp != SDE_MODE_DPMS_LP1)
  2726. crtc_state->active = false;
  2727. ++num_crtcs;
  2728. }
  2729. }
  2730. drm_connector_list_iter_end(&conn_iter);
  2731. /* check for nothing to do */
  2732. if (num_crtcs == 0) {
  2733. DRM_DEBUG("all crtcs are already in the off state\n");
  2734. sde_kms->suspend_block = true;
  2735. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2736. goto unlock;
  2737. }
  2738. /* commit the "disable all" state */
  2739. ret = drm_atomic_commit(state);
  2740. if (ret < 0) {
  2741. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2742. goto unlock;
  2743. }
  2744. sde_kms->suspend_block = true;
  2745. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2746. unlock:
  2747. if (state) {
  2748. drm_atomic_state_put(state);
  2749. state = NULL;
  2750. }
  2751. if (ret == -EDEADLK) {
  2752. drm_modeset_backoff(&ctx);
  2753. goto retry;
  2754. }
  2755. drm_modeset_drop_locks(&ctx);
  2756. drm_modeset_acquire_fini(&ctx);
  2757. /*
  2758. * pm runtime driver avoids multiple runtime_suspend API call by
  2759. * checking runtime_status. However, this call helps when there is a
  2760. * race condition between pm_suspend call and doze_suspend/power_off
  2761. * commit. It removes the extra vote from suspend and adds it back
  2762. * later to allow power collapse during pm_suspend call
  2763. */
  2764. pm_runtime_put_sync(dev);
  2765. pm_runtime_get_noresume(dev);
  2766. /* dump clock state before entering suspend */
  2767. if (sde_kms->pm_suspend_clk_dump)
  2768. _sde_kms_dump_clks_state(sde_kms);
  2769. return ret;
  2770. }
  2771. static int sde_kms_pm_resume(struct device *dev)
  2772. {
  2773. struct drm_device *ddev;
  2774. struct sde_kms *sde_kms;
  2775. struct drm_modeset_acquire_ctx ctx;
  2776. int ret, i;
  2777. if (!dev)
  2778. return -EINVAL;
  2779. ddev = dev_get_drvdata(dev);
  2780. if (!ddev || !ddev_to_msm_kms(ddev))
  2781. return -EINVAL;
  2782. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2783. SDE_EVT32(sde_kms->suspend_state != NULL);
  2784. drm_mode_config_reset(ddev);
  2785. drm_modeset_acquire_init(&ctx, 0);
  2786. retry:
  2787. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2788. if (ret == -EDEADLK) {
  2789. drm_modeset_backoff(&ctx);
  2790. goto retry;
  2791. } else if (WARN_ON(ret)) {
  2792. goto end;
  2793. }
  2794. sde_kms->suspend_block = false;
  2795. if (sde_kms->suspend_state) {
  2796. sde_kms->suspend_state->acquire_ctx = &ctx;
  2797. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2798. ret = drm_atomic_helper_commit_duplicated_state(
  2799. sde_kms->suspend_state, &ctx);
  2800. if (ret != -EDEADLK)
  2801. break;
  2802. drm_modeset_backoff(&ctx);
  2803. }
  2804. if (ret < 0)
  2805. DRM_ERROR("failed to restore state, %d\n", ret);
  2806. drm_atomic_state_put(sde_kms->suspend_state);
  2807. sde_kms->suspend_state = NULL;
  2808. }
  2809. end:
  2810. drm_modeset_drop_locks(&ctx);
  2811. drm_modeset_acquire_fini(&ctx);
  2812. /* enable hot-plug polling */
  2813. drm_kms_helper_poll_enable(ddev);
  2814. return 0;
  2815. }
  2816. static const struct msm_kms_funcs kms_funcs = {
  2817. .hw_init = sde_kms_hw_init,
  2818. .postinit = sde_kms_postinit,
  2819. .irq_preinstall = sde_irq_preinstall,
  2820. .irq_postinstall = sde_irq_postinstall,
  2821. .irq_uninstall = sde_irq_uninstall,
  2822. .irq = sde_irq,
  2823. .lastclose = sde_kms_lastclose,
  2824. .prepare_fence = sde_kms_prepare_fence,
  2825. .prepare_commit = sde_kms_prepare_commit,
  2826. .commit = sde_kms_commit,
  2827. .complete_commit = sde_kms_complete_commit,
  2828. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2829. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2830. .enable_vblank = sde_kms_enable_vblank,
  2831. .disable_vblank = sde_kms_disable_vblank,
  2832. .check_modified_format = sde_format_check_modified_format,
  2833. .atomic_check = sde_kms_atomic_check,
  2834. .get_format = sde_get_msm_format,
  2835. .round_pixclk = sde_kms_round_pixclk,
  2836. .display_early_wakeup = sde_kms_display_early_wakeup,
  2837. .pm_suspend = sde_kms_pm_suspend,
  2838. .pm_resume = sde_kms_pm_resume,
  2839. .destroy = sde_kms_destroy,
  2840. .debugfs_destroy = sde_kms_debugfs_destroy,
  2841. .cont_splash_config = sde_kms_cont_splash_config,
  2842. .register_events = _sde_kms_register_events,
  2843. .get_address_space = _sde_kms_get_address_space,
  2844. .get_address_space_device = _sde_kms_get_address_space_device,
  2845. .postopen = _sde_kms_post_open,
  2846. .check_for_splash = sde_kms_check_for_splash,
  2847. .get_mixer_count = sde_kms_get_mixer_count,
  2848. .get_dsc_count = sde_kms_get_dsc_count,
  2849. };
  2850. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2851. {
  2852. int i;
  2853. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2854. if (!sde_kms->aspace[i])
  2855. continue;
  2856. msm_gem_address_space_put(sde_kms->aspace[i]);
  2857. sde_kms->aspace[i] = NULL;
  2858. }
  2859. return 0;
  2860. }
  2861. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2862. {
  2863. struct msm_mmu *mmu;
  2864. int i, ret;
  2865. int early_map = 0;
  2866. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2867. return -EINVAL;
  2868. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2869. struct msm_gem_address_space *aspace;
  2870. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2871. if (IS_ERR(mmu)) {
  2872. ret = PTR_ERR(mmu);
  2873. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2874. i, ret);
  2875. continue;
  2876. }
  2877. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2878. mmu, "sde");
  2879. if (IS_ERR(aspace)) {
  2880. ret = PTR_ERR(aspace);
  2881. goto fail;
  2882. }
  2883. sde_kms->aspace[i] = aspace;
  2884. aspace->domain_attached = true;
  2885. /* Mapping splash memory block */
  2886. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2887. sde_kms->splash_data.num_splash_regions) {
  2888. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2889. if (ret) {
  2890. SDE_ERROR("failed to map ret:%d\n", ret);
  2891. goto fail;
  2892. }
  2893. }
  2894. /*
  2895. * disable early-map which would have been enabled during
  2896. * bootup by smmu through the device-tree hint for cont-spash
  2897. */
  2898. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2899. &early_map);
  2900. if (ret) {
  2901. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2902. ret, early_map);
  2903. goto early_map_fail;
  2904. }
  2905. }
  2906. sde_kms->base.aspace = sde_kms->aspace[0];
  2907. return 0;
  2908. early_map_fail:
  2909. _sde_kms_unmap_all_splash_regions(sde_kms);
  2910. fail:
  2911. mmu->funcs->destroy(mmu);
  2912. _sde_kms_mmu_destroy(sde_kms);
  2913. return ret;
  2914. }
  2915. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2916. {
  2917. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2918. return;
  2919. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2920. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2921. sde_kms->catalog);
  2922. if (sde_kms->sid)
  2923. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  2924. }
  2925. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2926. {
  2927. struct sde_vbif_set_qos_params qos_params;
  2928. struct sde_mdss_cfg *catalog;
  2929. if (!sde_kms->catalog)
  2930. return;
  2931. catalog = sde_kms->catalog;
  2932. memset(&qos_params, 0, sizeof(qos_params));
  2933. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2934. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2935. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2936. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2937. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2938. }
  2939. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  2940. {
  2941. struct sde_hw_uidle *uidle;
  2942. if (!sde_kms) {
  2943. SDE_ERROR("invalid kms\n");
  2944. return -EINVAL;
  2945. }
  2946. uidle = sde_kms->hw_uidle;
  2947. if (uidle && uidle->ops.active_override_enable)
  2948. uidle->ops.active_override_enable(uidle, enable);
  2949. return 0;
  2950. }
  2951. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  2952. {
  2953. struct device *cpu_dev;
  2954. int cpu = 0;
  2955. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  2956. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2957. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2958. return;
  2959. }
  2960. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2961. cpu_dev = get_cpu_device(cpu);
  2962. if (!cpu_dev) {
  2963. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2964. cpu);
  2965. continue;
  2966. }
  2967. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2968. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  2969. cpu_irq_latency);
  2970. else
  2971. dev_pm_qos_add_request(cpu_dev,
  2972. &sde_kms->pm_qos_irq_req[cpu],
  2973. DEV_PM_QOS_RESUME_LATENCY,
  2974. cpu_irq_latency);
  2975. }
  2976. }
  2977. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  2978. {
  2979. struct device *cpu_dev;
  2980. int cpu = 0;
  2981. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2982. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2983. return;
  2984. }
  2985. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2986. cpu_dev = get_cpu_device(cpu);
  2987. if (!cpu_dev) {
  2988. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2989. cpu);
  2990. continue;
  2991. }
  2992. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2993. dev_pm_qos_remove_request(
  2994. &sde_kms->pm_qos_irq_req[cpu]);
  2995. }
  2996. }
  2997. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  2998. {
  2999. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3000. mutex_lock(&priv->phandle.phandle_lock);
  3001. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3002. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3003. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3004. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3005. mutex_unlock(&priv->phandle.phandle_lock);
  3006. }
  3007. static void sde_kms_irq_affinity_notify(
  3008. struct irq_affinity_notify *affinity_notify,
  3009. const cpumask_t *mask)
  3010. {
  3011. struct msm_drm_private *priv;
  3012. struct sde_kms *sde_kms = container_of(affinity_notify,
  3013. struct sde_kms, affinity_notify);
  3014. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3015. return;
  3016. priv = sde_kms->dev->dev_private;
  3017. mutex_lock(&priv->phandle.phandle_lock);
  3018. // save irq cpu mask
  3019. sde_kms->irq_cpu_mask = *mask;
  3020. // request vote with updated irq cpu mask
  3021. if (sde_kms->irq_enabled)
  3022. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3023. mutex_unlock(&priv->phandle.phandle_lock);
  3024. }
  3025. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3026. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3027. {
  3028. struct sde_kms *sde_kms = usr;
  3029. struct msm_kms *msm_kms;
  3030. msm_kms = &sde_kms->base;
  3031. if (!sde_kms)
  3032. return;
  3033. SDE_DEBUG("event_type:%d\n", event_type);
  3034. SDE_EVT32_VERBOSE(event_type);
  3035. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3036. sde_irq_update(msm_kms, true);
  3037. sde_kms->first_kickoff = true;
  3038. if (sde_kms->splash_data.num_splash_displays ||
  3039. sde_in_trusted_vm(sde_kms))
  3040. return;
  3041. sde_vbif_init_memtypes(sde_kms);
  3042. sde_kms_init_shared_hw(sde_kms);
  3043. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3044. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3045. sde_irq_update(msm_kms, false);
  3046. sde_kms->first_kickoff = false;
  3047. if (sde_in_trusted_vm(sde_kms))
  3048. return;
  3049. _sde_kms_active_override(sde_kms, true);
  3050. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3051. sde_vbif_axi_halt_request(sde_kms);
  3052. }
  3053. }
  3054. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3055. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3056. {
  3057. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3058. int rc = -EINVAL;
  3059. SDE_DEBUG("\n");
  3060. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3061. if (rc > 0)
  3062. rc = 0;
  3063. SDE_EVT32(rc, genpd->device_count);
  3064. return rc;
  3065. }
  3066. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3067. {
  3068. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3069. SDE_DEBUG("\n");
  3070. pm_runtime_put_sync(sde_kms->dev->dev);
  3071. SDE_EVT32(genpd->device_count);
  3072. return 0;
  3073. }
  3074. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3075. struct sde_splash_data *data)
  3076. {
  3077. int i = 0;
  3078. int ret = 0;
  3079. struct device_node *parent, *node, *node1;
  3080. struct resource r, r1;
  3081. const char *node_name = "splash_region";
  3082. struct sde_splash_mem *mem;
  3083. bool share_splash_mem = false;
  3084. int num_displays, num_regions;
  3085. struct sde_splash_display *splash_display;
  3086. if (!data)
  3087. return -EINVAL;
  3088. memset(data, 0, sizeof(*data));
  3089. parent = of_find_node_by_path("/reserved-memory");
  3090. if (!parent) {
  3091. SDE_ERROR("failed to find reserved-memory node\n");
  3092. return -EINVAL;
  3093. }
  3094. node = of_find_node_by_name(parent, node_name);
  3095. if (!node) {
  3096. SDE_DEBUG("failed to find node %s\n", node_name);
  3097. return -EINVAL;
  3098. }
  3099. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3100. if (!node1)
  3101. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3102. /**
  3103. * Support sharing a single splash memory for all the built in displays
  3104. * and also independent splash region per displays. Incase of
  3105. * independent splash region for each connected display, dtsi node of
  3106. * cont_splash_region should be collection of all memory regions
  3107. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3108. */
  3109. num_displays = dsi_display_get_num_of_displays();
  3110. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3111. data->num_splash_displays = num_displays;
  3112. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3113. if (num_displays > num_regions) {
  3114. share_splash_mem = true;
  3115. pr_info(":%d displays share same splash buf\n", num_displays);
  3116. }
  3117. for (i = 0; i < num_displays; i++) {
  3118. splash_display = &data->splash_display[i];
  3119. if (!i || !share_splash_mem) {
  3120. if (of_address_to_resource(node, i, &r)) {
  3121. SDE_ERROR("invalid data for:%s\n", node_name);
  3122. return -EINVAL;
  3123. }
  3124. mem = &data->splash_mem[i];
  3125. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3126. SDE_DEBUG("failed to find ramdump memory\n");
  3127. mem->ramdump_base = 0;
  3128. mem->ramdump_size = 0;
  3129. } else {
  3130. mem->ramdump_base = (unsigned long)r1.start;
  3131. mem->ramdump_size = (r1.end - r1.start) + 1;
  3132. }
  3133. mem->splash_buf_base = (unsigned long)r.start;
  3134. mem->splash_buf_size = (r.end - r.start) + 1;
  3135. mem->ref_cnt = 0;
  3136. splash_display->splash = mem;
  3137. data->num_splash_regions++;
  3138. } else {
  3139. data->splash_display[i].splash = &data->splash_mem[0];
  3140. }
  3141. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3142. splash_display->splash->splash_buf_base,
  3143. splash_display->splash->splash_buf_size);
  3144. }
  3145. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3146. return ret;
  3147. }
  3148. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3149. struct platform_device *platformdev)
  3150. {
  3151. int rc = -EINVAL;
  3152. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3153. if (IS_ERR(sde_kms->mmio)) {
  3154. rc = PTR_ERR(sde_kms->mmio);
  3155. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3156. sde_kms->mmio = NULL;
  3157. goto error;
  3158. }
  3159. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3160. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3161. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3162. sde_kms->mmio_len);
  3163. if (rc)
  3164. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3165. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3166. "vbif_phys");
  3167. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3168. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3169. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3170. sde_kms->vbif[VBIF_RT] = NULL;
  3171. goto error;
  3172. }
  3173. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3174. "vbif_phys");
  3175. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3176. sde_kms->vbif_len[VBIF_RT]);
  3177. if (rc)
  3178. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3179. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3180. "vbif_nrt_phys");
  3181. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3182. sde_kms->vbif[VBIF_NRT] = NULL;
  3183. SDE_DEBUG("VBIF NRT is not defined");
  3184. } else {
  3185. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3186. "vbif_nrt_phys");
  3187. rc = sde_dbg_reg_register_base("vbif_nrt",
  3188. sde_kms->vbif[VBIF_NRT],
  3189. sde_kms->vbif_len[VBIF_NRT]);
  3190. if (rc)
  3191. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3192. rc);
  3193. }
  3194. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3195. "regdma_phys");
  3196. if (IS_ERR(sde_kms->reg_dma)) {
  3197. sde_kms->reg_dma = NULL;
  3198. SDE_DEBUG("REG_DMA is not defined");
  3199. } else {
  3200. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3201. "regdma_phys");
  3202. rc = sde_dbg_reg_register_base("reg_dma",
  3203. sde_kms->reg_dma,
  3204. sde_kms->reg_dma_len);
  3205. if (rc)
  3206. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3207. rc);
  3208. }
  3209. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3210. "sid_phys");
  3211. if (IS_ERR(sde_kms->sid)) {
  3212. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3213. sde_kms->sid = NULL;
  3214. } else {
  3215. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3216. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3217. sde_kms->sid_len);
  3218. if (rc)
  3219. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3220. }
  3221. error:
  3222. return rc;
  3223. }
  3224. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3225. struct sde_kms *sde_kms)
  3226. {
  3227. int rc = 0;
  3228. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3229. sde_kms->genpd.name = dev->unique;
  3230. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3231. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3232. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3233. if (rc < 0) {
  3234. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3235. sde_kms->genpd.name, rc);
  3236. return rc;
  3237. }
  3238. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3239. &sde_kms->genpd);
  3240. if (rc < 0) {
  3241. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3242. sde_kms->genpd.name, rc);
  3243. pm_genpd_remove(&sde_kms->genpd);
  3244. return rc;
  3245. }
  3246. sde_kms->genpd_init = true;
  3247. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3248. }
  3249. return rc;
  3250. }
  3251. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3252. struct drm_device *dev,
  3253. struct msm_drm_private *priv)
  3254. {
  3255. struct sde_rm *rm = NULL;
  3256. int i, rc = -EINVAL;
  3257. sde_kms->catalog = sde_hw_catalog_init(dev);
  3258. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3259. rc = PTR_ERR(sde_kms->catalog);
  3260. if (!sde_kms->catalog)
  3261. rc = -EINVAL;
  3262. SDE_ERROR("catalog init failed: %d\n", rc);
  3263. sde_kms->catalog = NULL;
  3264. goto power_error;
  3265. }
  3266. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3267. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3268. /* initialize power domain if defined */
  3269. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3270. if (rc) {
  3271. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3272. goto genpd_err;
  3273. }
  3274. rc = _sde_kms_mmu_init(sde_kms);
  3275. if (rc) {
  3276. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3277. goto power_error;
  3278. }
  3279. /* Initialize reg dma block which is a singleton */
  3280. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3281. sde_kms->dev);
  3282. if (rc) {
  3283. SDE_ERROR("failed: reg dma init failed\n");
  3284. goto power_error;
  3285. }
  3286. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3287. rm = &sde_kms->rm;
  3288. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3289. sde_kms->dev);
  3290. if (rc) {
  3291. SDE_ERROR("rm init failed: %d\n", rc);
  3292. goto power_error;
  3293. }
  3294. sde_kms->rm_init = true;
  3295. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3296. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3297. rc = PTR_ERR(sde_kms->hw_intr);
  3298. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3299. sde_kms->hw_intr = NULL;
  3300. goto hw_intr_init_err;
  3301. }
  3302. /*
  3303. * Attempt continuous splash handoff only if reserved
  3304. * splash memory is found & release resources on any error
  3305. * in finding display hw config in splash
  3306. */
  3307. if (sde_kms->splash_data.num_splash_regions) {
  3308. struct sde_splash_display *display;
  3309. int ret, display_count =
  3310. sde_kms->splash_data.num_splash_displays;
  3311. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3312. &sde_kms->splash_data, sde_kms->catalog);
  3313. for (i = 0; i < display_count; i++) {
  3314. display = &sde_kms->splash_data.splash_display[i];
  3315. /*
  3316. * free splash region on resource init failure and
  3317. * cont-splash disabled case
  3318. */
  3319. if (!display->cont_splash_enabled || ret)
  3320. _sde_kms_free_splash_display_data(
  3321. sde_kms, display);
  3322. }
  3323. }
  3324. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3325. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3326. rc = PTR_ERR(sde_kms->hw_mdp);
  3327. if (!sde_kms->hw_mdp)
  3328. rc = -EINVAL;
  3329. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3330. sde_kms->hw_mdp = NULL;
  3331. goto power_error;
  3332. }
  3333. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3334. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3335. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3336. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3337. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3338. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3339. if (!sde_kms->hw_vbif[vbif_idx])
  3340. rc = -EINVAL;
  3341. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3342. sde_kms->hw_vbif[vbif_idx] = NULL;
  3343. goto power_error;
  3344. }
  3345. }
  3346. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3347. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3348. sde_kms->mmio_len, sde_kms->catalog);
  3349. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3350. rc = PTR_ERR(sde_kms->hw_uidle);
  3351. if (!sde_kms->hw_uidle)
  3352. rc = -EINVAL;
  3353. /* uidle is optional, so do not make it a fatal error */
  3354. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3355. sde_kms->hw_uidle = NULL;
  3356. rc = 0;
  3357. }
  3358. } else {
  3359. sde_kms->hw_uidle = NULL;
  3360. }
  3361. if (sde_kms->sid) {
  3362. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3363. sde_kms->sid_len, sde_kms->catalog);
  3364. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3365. rc = PTR_ERR(sde_kms->hw_sid);
  3366. SDE_ERROR("failed to init sid %ld\n", rc);
  3367. sde_kms->hw_sid = NULL;
  3368. goto power_error;
  3369. }
  3370. }
  3371. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3372. &priv->phandle, "core_clk");
  3373. if (rc) {
  3374. SDE_ERROR("failed to init perf %d\n", rc);
  3375. goto perf_err;
  3376. }
  3377. /*
  3378. * _sde_kms_drm_obj_init should create the DRM related objects
  3379. * i.e. CRTCs, planes, encoders, connectors and so forth
  3380. */
  3381. rc = _sde_kms_drm_obj_init(sde_kms);
  3382. if (rc) {
  3383. SDE_ERROR("modeset init failed: %d\n", rc);
  3384. goto drm_obj_init_err;
  3385. }
  3386. return 0;
  3387. genpd_err:
  3388. drm_obj_init_err:
  3389. sde_core_perf_destroy(&sde_kms->perf);
  3390. hw_intr_init_err:
  3391. perf_err:
  3392. power_error:
  3393. return rc;
  3394. }
  3395. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3396. {
  3397. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3398. int rc = 0;
  3399. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3400. if (rc) {
  3401. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3402. return rc;
  3403. }
  3404. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3405. if (rc) {
  3406. SDE_ERROR("failed to get io irq for KMS");
  3407. return rc;
  3408. }
  3409. return rc;
  3410. }
  3411. static int sde_kms_hw_init(struct msm_kms *kms)
  3412. {
  3413. struct sde_kms *sde_kms;
  3414. struct drm_device *dev;
  3415. struct msm_drm_private *priv;
  3416. struct platform_device *platformdev;
  3417. int i, irq_num, rc = -EINVAL;
  3418. if (!kms) {
  3419. SDE_ERROR("invalid kms\n");
  3420. goto end;
  3421. }
  3422. sde_kms = to_sde_kms(kms);
  3423. dev = sde_kms->dev;
  3424. if (!dev || !dev->dev) {
  3425. SDE_ERROR("invalid device\n");
  3426. goto end;
  3427. }
  3428. platformdev = to_platform_device(dev->dev);
  3429. priv = dev->dev_private;
  3430. if (!priv) {
  3431. SDE_ERROR("invalid private data\n");
  3432. goto end;
  3433. }
  3434. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3435. if (rc)
  3436. goto error;
  3437. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3438. if (rc)
  3439. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3440. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3441. if (rc)
  3442. goto error;
  3443. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3444. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3445. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3446. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3447. mutex_init(&sde_kms->secure_transition_lock);
  3448. atomic_set(&sde_kms->detach_sec_cb, 0);
  3449. atomic_set(&sde_kms->detach_all_cb, 0);
  3450. atomic_set(&sde_kms->irq_vote_count, 0);
  3451. /*
  3452. * Support format modifiers for compression etc.
  3453. */
  3454. dev->mode_config.allow_fb_modifiers = true;
  3455. /*
  3456. * Handle (re)initializations during power enable
  3457. */
  3458. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3459. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3460. SDE_POWER_EVENT_POST_ENABLE |
  3461. SDE_POWER_EVENT_PRE_DISABLE,
  3462. sde_kms_handle_power_event, sde_kms, "kms");
  3463. if (sde_kms->splash_data.num_splash_displays) {
  3464. SDE_DEBUG("Skipping MDP Resources disable\n");
  3465. } else {
  3466. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3467. sde_power_data_bus_set_quota(&priv->phandle, i,
  3468. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3469. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3470. pm_runtime_put_sync(sde_kms->dev->dev);
  3471. }
  3472. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3473. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3474. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3475. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3476. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3477. if (sde_in_trusted_vm(sde_kms))
  3478. rc = sde_vm_trusted_init(sde_kms);
  3479. else
  3480. rc = sde_vm_primary_init(sde_kms);
  3481. if (rc) {
  3482. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3483. goto error;
  3484. }
  3485. return 0;
  3486. error:
  3487. _sde_kms_hw_destroy(sde_kms, platformdev);
  3488. end:
  3489. return rc;
  3490. }
  3491. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3492. {
  3493. struct msm_drm_private *priv;
  3494. struct sde_kms *sde_kms;
  3495. if (!dev || !dev->dev_private) {
  3496. SDE_ERROR("drm device node invalid\n");
  3497. return ERR_PTR(-EINVAL);
  3498. }
  3499. priv = dev->dev_private;
  3500. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3501. if (!sde_kms) {
  3502. SDE_ERROR("failed to allocate sde kms\n");
  3503. return ERR_PTR(-ENOMEM);
  3504. }
  3505. msm_kms_init(&sde_kms->base, &kms_funcs);
  3506. sde_kms->dev = dev;
  3507. return &sde_kms->base;
  3508. }
  3509. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3510. {
  3511. struct dsi_display *display;
  3512. struct sde_splash_display *handoff_display;
  3513. int i;
  3514. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3515. handoff_display = &sde_kms->splash_data.splash_display[i];
  3516. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3517. if (handoff_display->cont_splash_enabled)
  3518. _sde_kms_free_splash_display_data(sde_kms,
  3519. handoff_display);
  3520. dsi_display_set_active_state(display, false);
  3521. }
  3522. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3523. }
  3524. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms)
  3525. {
  3526. struct drm_device *dev;
  3527. struct msm_drm_private *priv;
  3528. struct sde_splash_display *handoff_display;
  3529. struct dsi_display *display;
  3530. int ret, i;
  3531. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3532. SDE_ERROR("invalid params\n");
  3533. return -EINVAL;
  3534. }
  3535. if (!sde_kms->vm->vm_ops.vm_owns_hw(sde_kms)) {
  3536. SDE_DEBUG(
  3537. "skipping sde res init as device assign is not completed\n");
  3538. return 0;
  3539. }
  3540. if (sde_kms->dsi_display_count != 1) {
  3541. SDE_ERROR("no. of displays not supported:%d\n",
  3542. sde_kms->dsi_display_count);
  3543. return -EINVAL;
  3544. }
  3545. dev = sde_kms->dev;
  3546. priv = dev->dev_private;
  3547. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3548. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3549. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3550. &sde_kms->splash_data, sde_kms->catalog);
  3551. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3552. handoff_display = &sde_kms->splash_data.splash_display[i];
  3553. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3554. if (!handoff_display->cont_splash_enabled || ret)
  3555. _sde_kms_free_splash_display_data(sde_kms,
  3556. handoff_display);
  3557. else
  3558. dsi_display_set_active_state(display, true);
  3559. }
  3560. ret = sde_kms_cont_splash_config(&sde_kms->base);
  3561. if (ret) {
  3562. SDE_ERROR("error in setting handoff configs\n");
  3563. goto error;
  3564. }
  3565. return 0;
  3566. error:
  3567. sde_kms_vm_trusted_resource_deinit(sde_kms);
  3568. return ret;
  3569. }
  3570. static int _sde_kms_register_events(struct msm_kms *kms,
  3571. struct drm_mode_object *obj, u32 event, bool en)
  3572. {
  3573. int ret = 0;
  3574. struct drm_crtc *crtc = NULL;
  3575. struct drm_connector *conn = NULL;
  3576. struct sde_kms *sde_kms = NULL;
  3577. if (!kms || !obj) {
  3578. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3579. return -EINVAL;
  3580. }
  3581. sde_kms = to_sde_kms(kms);
  3582. switch (obj->type) {
  3583. case DRM_MODE_OBJECT_CRTC:
  3584. crtc = obj_to_crtc(obj);
  3585. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3586. break;
  3587. case DRM_MODE_OBJECT_CONNECTOR:
  3588. conn = obj_to_connector(obj);
  3589. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3590. en);
  3591. break;
  3592. }
  3593. return ret;
  3594. }
  3595. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3596. {
  3597. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3598. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3599. }