wcd934x-dsp-cntl.c 38 KB

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  1. /*
  2. * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/slab.h>
  14. #include <linux/delay.h>
  15. #include <linux/component.h>
  16. #include <linux/debugfs.h>
  17. #include <sound/soc.h>
  18. #include <sound/wcd-dsp-mgr.h>
  19. #include <asoc/wcd934x_registers.h>
  20. #include "wcd934x.h"
  21. #include "wcd934x-dsp-cntl.h"
  22. #include "../wcd9xxx-irq.h"
  23. #include "../core.h"
  24. #define WCD_CNTL_DIR_NAME_LEN_MAX 32
  25. #define WCD_CPE_FLL_MAX_RETRIES 5
  26. #define WCD_MEM_ENABLE_MAX_RETRIES 20
  27. #define WCD_DSP_BOOT_TIMEOUT_MS 3000
  28. #define WCD_SYSFS_ENTRY_MAX_LEN 8
  29. #define WCD_PROCFS_ENTRY_MAX_LEN 16
  30. #define WCD_934X_RAMDUMP_START_ADDR 0x20100000
  31. #define WCD_934X_RAMDUMP_SIZE ((1024 * 1024) - 128)
  32. #define WCD_MISCDEV_CMD_MAX_LEN 11
  33. #define WCD_CNTL_MUTEX_LOCK(codec, lock) \
  34. { \
  35. dev_dbg(codec->dev, "%s: mutex_lock(%s)\n", \
  36. __func__, __stringify_1(lock)); \
  37. mutex_lock(&lock); \
  38. }
  39. #define WCD_CNTL_MUTEX_UNLOCK(codec, lock) \
  40. { \
  41. dev_dbg(codec->dev, "%s: mutex_unlock(%s)\n", \
  42. __func__, __stringify_1(lock)); \
  43. mutex_unlock(&lock); \
  44. }
  45. enum wcd_mem_type {
  46. WCD_MEM_TYPE_ALWAYS_ON,
  47. WCD_MEM_TYPE_SWITCHABLE,
  48. };
  49. struct wcd_cntl_attribute {
  50. struct attribute attr;
  51. ssize_t (*show)(struct wcd_dsp_cntl *cntl, char *buf);
  52. ssize_t (*store)(struct wcd_dsp_cntl *cntl, const char *buf,
  53. ssize_t count);
  54. };
  55. #define WCD_CNTL_ATTR(_name, _mode, _show, _store) \
  56. static struct wcd_cntl_attribute cntl_attr_##_name = { \
  57. .attr = {.name = __stringify(_name), .mode = _mode}, \
  58. .show = _show, \
  59. .store = _store, \
  60. }
  61. #define to_wcd_cntl_attr(a) \
  62. container_of((a), struct wcd_cntl_attribute, attr)
  63. #define to_wcd_cntl(kobj) \
  64. container_of((kobj), struct wcd_dsp_cntl, wcd_kobj)
  65. static u8 mem_enable_values[] = {
  66. 0xFE, 0xFC, 0xF8, 0xF0,
  67. 0xE0, 0xC0, 0x80, 0x00,
  68. };
  69. #ifdef CONFIG_DEBUG_FS
  70. #define WCD_CNTL_SET_ERR_IRQ_FLAG(cntl)\
  71. atomic_cmpxchg(&cntl->err_irq_flag, 0, 1)
  72. #define WCD_CNTL_CLR_ERR_IRQ_FLAG(cntl)\
  73. atomic_set(&cntl->err_irq_flag, 0)
  74. static u16 wdsp_reg_for_debug_dump[] = {
  75. WCD934X_CPE_SS_CPE_CTL,
  76. WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_0,
  77. WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1,
  78. WCD934X_CPE_SS_PWR_CPEFLL_CTL,
  79. WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_0,
  80. WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_1,
  81. WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_OVERRIDE,
  82. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_0,
  83. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_1,
  84. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_2,
  85. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_3,
  86. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_4,
  87. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_5,
  88. WCD934X_CPE_SS_PWR_CPE_DRAM1_SHUTDOWN,
  89. WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL,
  90. WCD934X_CPE_SS_MAD_CTL,
  91. WCD934X_CPE_SS_CPAR_CTL,
  92. WCD934X_CPE_SS_WDOG_CFG,
  93. WCD934X_CPE_SS_STATUS,
  94. WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A,
  95. WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B,
  96. WCD934X_CPE_SS_SS_ERROR_INT_MASK_1A,
  97. WCD934X_CPE_SS_SS_ERROR_INT_MASK_1B,
  98. WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0A,
  99. WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0B,
  100. WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1A,
  101. WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1B,
  102. };
  103. static void wcd_cntl_collect_debug_dumps(struct wcd_dsp_cntl *cntl)
  104. {
  105. struct snd_soc_codec *codec = cntl->codec;
  106. struct wdsp_err_signal_arg arg;
  107. int i;
  108. u8 val;
  109. /* If WDSP SSR happens, skip collecting debug dumps */
  110. if (WCD_CNTL_SET_ERR_IRQ_FLAG(cntl) != 0)
  111. return;
  112. /* Mask all error interrupts */
  113. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A,
  114. 0xFF);
  115. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B,
  116. 0xFF);
  117. /* Collect important WDSP registers dump for debug use */
  118. pr_err("%s: Dump the WDSP registers for debug use\n", __func__);
  119. for (i = 0; i < sizeof(wdsp_reg_for_debug_dump)/sizeof(u16); i++) {
  120. val = snd_soc_read(codec, wdsp_reg_for_debug_dump[i]);
  121. pr_err("%s: reg = 0x%x, val = 0x%x\n", __func__,
  122. wdsp_reg_for_debug_dump[i], val);
  123. }
  124. /* Trigger NMI in WDSP to sync and update the memory */
  125. snd_soc_write(codec, WCD934X_CPE_SS_BACKUP_INT, 0x02);
  126. /* Collect WDSP ramdump for debug use */
  127. if (cntl->m_dev && cntl->m_ops && cntl->m_ops->signal_handler) {
  128. arg.mem_dumps_enabled = cntl->ramdump_enable;
  129. arg.remote_start_addr = WCD_934X_RAMDUMP_START_ADDR;
  130. arg.dump_size = WCD_934X_RAMDUMP_SIZE;
  131. cntl->m_ops->signal_handler(cntl->m_dev, WDSP_DEBUG_DUMP,
  132. &arg);
  133. }
  134. /* Unmask the fatal irqs */
  135. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A,
  136. ~(cntl->irqs.fatal_irqs & 0xFF));
  137. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B,
  138. ~((cntl->irqs.fatal_irqs >> 8) & 0xFF));
  139. WCD_CNTL_CLR_ERR_IRQ_FLAG(cntl);
  140. }
  141. #else
  142. #define WCD_CNTL_SET_ERR_IRQ_FLAG(cntl) 0
  143. #define WCD_CNTL_CLR_ERR_IRQ_FLAG(cntl) do {} while (0)
  144. static void wcd_cntl_collect_debug_dumps(struct wcd_dsp_cntl *cntl)
  145. {
  146. }
  147. #endif
  148. static ssize_t wdsp_boot_show(struct wcd_dsp_cntl *cntl, char *buf)
  149. {
  150. return snprintf(buf, WCD_SYSFS_ENTRY_MAX_LEN,
  151. "%u", cntl->boot_reqs);
  152. }
  153. static ssize_t wdsp_boot_store(struct wcd_dsp_cntl *cntl,
  154. const char *buf, ssize_t count)
  155. {
  156. u32 val;
  157. bool vote;
  158. int ret;
  159. ret = kstrtou32(buf, 10, &val);
  160. if (ret) {
  161. dev_err(cntl->codec->dev,
  162. "%s: Invalid entry, ret = %d\n", __func__, ret);
  163. return -EINVAL;
  164. }
  165. if (val > 0) {
  166. cntl->boot_reqs++;
  167. vote = true;
  168. } else {
  169. cntl->boot_reqs--;
  170. vote = false;
  171. }
  172. if (cntl->m_dev && cntl->m_ops &&
  173. cntl->m_ops->vote_for_dsp)
  174. ret = cntl->m_ops->vote_for_dsp(cntl->m_dev, vote);
  175. else
  176. ret = -EINVAL;
  177. if (ret < 0)
  178. dev_err(cntl->codec->dev,
  179. "%s: failed to %s dsp\n", __func__,
  180. vote ? "enable" : "disable");
  181. return count;
  182. }
  183. WCD_CNTL_ATTR(boot, 0660, wdsp_boot_show, wdsp_boot_store);
  184. static ssize_t wcd_cntl_sysfs_show(struct kobject *kobj,
  185. struct attribute *attr, char *buf)
  186. {
  187. struct wcd_cntl_attribute *wcd_attr = to_wcd_cntl_attr(attr);
  188. struct wcd_dsp_cntl *cntl = to_wcd_cntl(kobj);
  189. ssize_t ret = -EINVAL;
  190. if (cntl && wcd_attr->show)
  191. ret = wcd_attr->show(cntl, buf);
  192. return ret;
  193. }
  194. static ssize_t wcd_cntl_sysfs_store(struct kobject *kobj,
  195. struct attribute *attr, const char *buf,
  196. size_t count)
  197. {
  198. struct wcd_cntl_attribute *wcd_attr = to_wcd_cntl_attr(attr);
  199. struct wcd_dsp_cntl *cntl = to_wcd_cntl(kobj);
  200. ssize_t ret = -EINVAL;
  201. if (cntl && wcd_attr->store)
  202. ret = wcd_attr->store(cntl, buf, count);
  203. return ret;
  204. }
  205. static const struct sysfs_ops wcd_cntl_sysfs_ops = {
  206. .show = wcd_cntl_sysfs_show,
  207. .store = wcd_cntl_sysfs_store,
  208. };
  209. static struct kobj_type wcd_cntl_ktype = {
  210. .sysfs_ops = &wcd_cntl_sysfs_ops,
  211. };
  212. static void wcd_cntl_change_online_state(struct wcd_dsp_cntl *cntl,
  213. u8 online)
  214. {
  215. struct wdsp_ssr_entry *ssr_entry = &cntl->ssr_entry;
  216. unsigned long ret;
  217. WCD_CNTL_MUTEX_LOCK(cntl->codec, cntl->ssr_mutex);
  218. ssr_entry->offline = !online;
  219. /* Make sure the write is complete */
  220. wmb();
  221. ret = xchg(&ssr_entry->offline_change, 1);
  222. wake_up_interruptible(&ssr_entry->offline_poll_wait);
  223. dev_dbg(cntl->codec->dev,
  224. "%s: requested %u, offline %u offline_change %u, ret = %ldn",
  225. __func__, online, ssr_entry->offline,
  226. ssr_entry->offline_change, ret);
  227. WCD_CNTL_MUTEX_UNLOCK(cntl->codec, cntl->ssr_mutex);
  228. }
  229. static ssize_t wdsp_ssr_entry_read(struct snd_info_entry *entry,
  230. void *file_priv_data, struct file *file,
  231. char __user *buf, size_t count, loff_t pos)
  232. {
  233. int len = 0;
  234. char buffer[WCD_PROCFS_ENTRY_MAX_LEN];
  235. struct wcd_dsp_cntl *cntl;
  236. struct wdsp_ssr_entry *ssr_entry;
  237. ssize_t ret;
  238. u8 offline;
  239. cntl = (struct wcd_dsp_cntl *) entry->private_data;
  240. if (!cntl) {
  241. pr_err("%s: Invalid private data for SSR procfs entry\n",
  242. __func__);
  243. return -EINVAL;
  244. }
  245. ssr_entry = &cntl->ssr_entry;
  246. WCD_CNTL_MUTEX_LOCK(cntl->codec, cntl->ssr_mutex);
  247. offline = ssr_entry->offline;
  248. /* Make sure the read is complete */
  249. rmb();
  250. dev_dbg(cntl->codec->dev, "%s: offline = %s\n", __func__,
  251. offline ? "true" : "false");
  252. len = snprintf(buffer, sizeof(buffer), "%s\n",
  253. offline ? "OFFLINE" : "ONLINE");
  254. ret = simple_read_from_buffer(buf, count, &pos, buffer, len);
  255. WCD_CNTL_MUTEX_UNLOCK(cntl->codec, cntl->ssr_mutex);
  256. return ret;
  257. }
  258. static unsigned int wdsp_ssr_entry_poll(struct snd_info_entry *entry,
  259. void *private_data, struct file *file,
  260. poll_table *wait)
  261. {
  262. struct wcd_dsp_cntl *cntl;
  263. struct wdsp_ssr_entry *ssr_entry;
  264. unsigned int ret = 0;
  265. if (!entry || !entry->private_data) {
  266. pr_err("%s: %s is NULL\n", __func__,
  267. (!entry) ? "entry" : "private_data");
  268. return -EINVAL;
  269. }
  270. cntl = (struct wcd_dsp_cntl *) entry->private_data;
  271. ssr_entry = &cntl->ssr_entry;
  272. dev_dbg(cntl->codec->dev, "%s: Poll wait, offline = %u\n",
  273. __func__, ssr_entry->offline);
  274. poll_wait(file, &ssr_entry->offline_poll_wait, wait);
  275. dev_dbg(cntl->codec->dev, "%s: Woken up Poll wait, offline = %u\n",
  276. __func__, ssr_entry->offline);
  277. WCD_CNTL_MUTEX_LOCK(cntl->codec, cntl->ssr_mutex);
  278. if (xchg(&ssr_entry->offline_change, 0))
  279. ret = POLLIN | POLLPRI | POLLRDNORM;
  280. dev_dbg(cntl->codec->dev, "%s: ret (%d) from poll_wait\n",
  281. __func__, ret);
  282. WCD_CNTL_MUTEX_UNLOCK(cntl->codec, cntl->ssr_mutex);
  283. return ret;
  284. }
  285. static struct snd_info_entry_ops wdsp_ssr_entry_ops = {
  286. .read = wdsp_ssr_entry_read,
  287. .poll = wdsp_ssr_entry_poll,
  288. };
  289. static int wcd_cntl_cpe_fll_calibrate(struct wcd_dsp_cntl *cntl)
  290. {
  291. struct snd_soc_codec *codec = cntl->codec;
  292. int ret = 0, retry = 0;
  293. u8 cal_lsb, cal_msb;
  294. u8 lock_det;
  295. /* Make sure clocks are gated */
  296. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPE_CTL,
  297. 0x05, 0x00);
  298. /* Enable CPE FLL reference clock */
  299. snd_soc_update_bits(codec, WCD934X_CLK_SYS_MCLK2_PRG1,
  300. 0x80, 0x80);
  301. snd_soc_update_bits(codec, WCD934X_CPE_FLL_USER_CTL_5,
  302. 0xF3, 0x13);
  303. snd_soc_write(codec, WCD934X_CPE_FLL_L_VAL_CTL_0, 0x50);
  304. /* Disable CPAR reset and Enable CPAR clk */
  305. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL,
  306. 0x02, 0x02);
  307. /* Write calibration l-value based on cdc clk rate */
  308. if (cntl->clk_rate == 9600000) {
  309. cal_lsb = 0x6d;
  310. cal_msb = 0x00;
  311. } else {
  312. cal_lsb = 0x56;
  313. cal_msb = 0x00;
  314. }
  315. snd_soc_write(codec, WCD934X_CPE_FLL_USER_CTL_6, cal_lsb);
  316. snd_soc_write(codec, WCD934X_CPE_FLL_USER_CTL_7, cal_msb);
  317. /* FLL mode to follow power up sequence */
  318. snd_soc_update_bits(codec, WCD934X_CPE_FLL_FLL_MODE,
  319. 0x60, 0x00);
  320. /* HW controlled CPE FLL */
  321. snd_soc_update_bits(codec, WCD934X_CPE_FLL_FLL_MODE,
  322. 0x80, 0x80);
  323. /* Force on CPE FLL */
  324. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CFG,
  325. 0x04, 0x04);
  326. do {
  327. /* Time for FLL calibration to complete */
  328. usleep_range(1000, 1100);
  329. lock_det = snd_soc_read(codec, WCD934X_CPE_FLL_STATUS_3);
  330. retry++;
  331. } while (!(lock_det & 0x01) &&
  332. retry <= WCD_CPE_FLL_MAX_RETRIES);
  333. if (!(lock_det & 0x01)) {
  334. dev_err(codec->dev, "%s: lock detect not set, 0x%02x\n",
  335. __func__, lock_det);
  336. ret = -EIO;
  337. goto err_lock_det;
  338. }
  339. snd_soc_update_bits(codec, WCD934X_CPE_FLL_FLL_MODE,
  340. 0x60, 0x20);
  341. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CFG,
  342. 0x04, 0x00);
  343. return ret;
  344. err_lock_det:
  345. /* Undo the register settings */
  346. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CFG,
  347. 0x04, 0x00);
  348. snd_soc_update_bits(codec, WCD934X_CPE_FLL_FLL_MODE,
  349. 0x80, 0x00);
  350. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL,
  351. 0x02, 0x00);
  352. return ret;
  353. }
  354. static void wcd_cntl_config_cpar(struct wcd_dsp_cntl *cntl)
  355. {
  356. struct snd_soc_codec *codec = cntl->codec;
  357. u8 nom_lo, nom_hi, svs2_lo, svs2_hi;
  358. /* Configure CPAR */
  359. nom_hi = svs2_hi = 0;
  360. if (cntl->clk_rate == 9600000) {
  361. nom_lo = 0x90;
  362. svs2_lo = 0x50;
  363. } else {
  364. nom_lo = 0x70;
  365. svs2_lo = 0x3e;
  366. }
  367. snd_soc_write(codec, WCD934X_TEST_DEBUG_LVAL_NOM_LOW, nom_lo);
  368. snd_soc_write(codec, WCD934X_TEST_DEBUG_LVAL_NOM_HIGH, nom_hi);
  369. snd_soc_write(codec, WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_LOW, svs2_lo);
  370. snd_soc_write(codec, WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_HIGH, svs2_hi);
  371. snd_soc_update_bits(codec, WCD934X_CPE_SS_PWR_CPEFLL_CTL,
  372. 0x03, 0x03);
  373. }
  374. static int wcd_cntl_cpe_fll_ctrl(struct wcd_dsp_cntl *cntl,
  375. bool enable)
  376. {
  377. struct snd_soc_codec *codec = cntl->codec;
  378. int ret = 0;
  379. if (enable) {
  380. ret = wcd_cntl_cpe_fll_calibrate(cntl);
  381. if (ret < 0) {
  382. dev_err(codec->dev,
  383. "%s: cpe_fll_cal failed, err = %d\n",
  384. __func__, ret);
  385. goto done;
  386. }
  387. wcd_cntl_config_cpar(cntl);
  388. /* Enable AHB CLK and CPE CLK*/
  389. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPE_CTL,
  390. 0x05, 0x05);
  391. } else {
  392. /* Disable AHB CLK and CPE CLK */
  393. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPE_CTL,
  394. 0x05, 0x00);
  395. /* Reset the CPAR mode for CPE FLL */
  396. snd_soc_write(codec, WCD934X_CPE_FLL_FLL_MODE, 0x20);
  397. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CFG,
  398. 0x04, 0x00);
  399. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL,
  400. 0x02, 0x00);
  401. }
  402. done:
  403. return ret;
  404. }
  405. static int wcd_cntl_clocks_enable(struct wcd_dsp_cntl *cntl)
  406. {
  407. struct snd_soc_codec *codec = cntl->codec;
  408. int ret;
  409. WCD_CNTL_MUTEX_LOCK(codec, cntl->clk_mutex);
  410. /* Enable codec clock */
  411. if (cntl->cdc_cb && cntl->cdc_cb->cdc_clk_en)
  412. ret = cntl->cdc_cb->cdc_clk_en(codec, true);
  413. else
  414. ret = -EINVAL;
  415. if (ret < 0) {
  416. dev_err(codec->dev,
  417. "%s: Failed to enable cdc clk, err = %d\n",
  418. __func__, ret);
  419. goto done;
  420. }
  421. /* Pull CPAR out of reset */
  422. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x00);
  423. /* Configure and Enable CPE FLL clock */
  424. ret = wcd_cntl_cpe_fll_ctrl(cntl, true);
  425. if (ret < 0) {
  426. dev_err(codec->dev,
  427. "%s: Failed to enable cpe clk, err = %d\n",
  428. __func__, ret);
  429. goto err_cpe_clk;
  430. }
  431. cntl->is_clk_enabled = true;
  432. /* Ungate the CPR clock */
  433. snd_soc_update_bits(codec, WCD934X_CODEC_RPM_CLK_GATE, 0x10, 0x00);
  434. done:
  435. WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex);
  436. return ret;
  437. err_cpe_clk:
  438. if (cntl->cdc_cb && cntl->cdc_cb->cdc_clk_en)
  439. cntl->cdc_cb->cdc_clk_en(codec, false);
  440. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04);
  441. WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex);
  442. return ret;
  443. }
  444. static int wcd_cntl_clocks_disable(struct wcd_dsp_cntl *cntl)
  445. {
  446. struct snd_soc_codec *codec = cntl->codec;
  447. int ret = 0;
  448. WCD_CNTL_MUTEX_LOCK(codec, cntl->clk_mutex);
  449. if (!cntl->is_clk_enabled) {
  450. dev_info(codec->dev, "%s: clocks already disabled\n",
  451. __func__);
  452. goto done;
  453. }
  454. /* Gate the CPR clock */
  455. snd_soc_update_bits(codec, WCD934X_CODEC_RPM_CLK_GATE, 0x10, 0x10);
  456. /* Disable CPE FLL clock */
  457. ret = wcd_cntl_cpe_fll_ctrl(cntl, false);
  458. if (ret < 0)
  459. dev_err(codec->dev,
  460. "%s: Failed to disable cpe clk, err = %d\n",
  461. __func__, ret);
  462. /*
  463. * Even if CPE FLL disable failed, go ahead and disable
  464. * the codec clock
  465. */
  466. if (cntl->cdc_cb && cntl->cdc_cb->cdc_clk_en)
  467. ret = cntl->cdc_cb->cdc_clk_en(codec, false);
  468. else
  469. ret = -EINVAL;
  470. cntl->is_clk_enabled = false;
  471. /* Put CPAR in reset */
  472. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04);
  473. done:
  474. WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex);
  475. return ret;
  476. }
  477. static void wcd_cntl_cpar_ctrl(struct wcd_dsp_cntl *cntl,
  478. bool enable)
  479. {
  480. struct snd_soc_codec *codec = cntl->codec;
  481. if (enable)
  482. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x03);
  483. else
  484. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x00);
  485. }
  486. static int wcd_cntl_enable_memory(struct wcd_dsp_cntl *cntl,
  487. enum wcd_mem_type mem_type)
  488. {
  489. struct snd_soc_codec *codec = cntl->codec;
  490. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  491. int loop_cnt = 0;
  492. u8 status;
  493. int ret = 0;
  494. switch (mem_type) {
  495. case WCD_MEM_TYPE_ALWAYS_ON:
  496. /* 512KB of always on region */
  497. wcd9xxx_slim_write_repeat(wcd9xxx,
  498. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_0,
  499. ARRAY_SIZE(mem_enable_values),
  500. mem_enable_values);
  501. wcd9xxx_slim_write_repeat(wcd9xxx,
  502. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_1,
  503. ARRAY_SIZE(mem_enable_values),
  504. mem_enable_values);
  505. break;
  506. case WCD_MEM_TYPE_SWITCHABLE:
  507. snd_soc_update_bits(codec, WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL,
  508. 0x04, 0x00);
  509. snd_soc_update_bits(codec, WCD934X_TEST_DEBUG_MEM_CTRL,
  510. 0x80, 0x80);
  511. snd_soc_update_bits(codec, WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL,
  512. 0x01, 0x01);
  513. do {
  514. loop_cnt++;
  515. /* Time to enable the power domain for memory */
  516. usleep_range(100, 150);
  517. status = snd_soc_read(codec,
  518. WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL);
  519. } while ((status & 0x02) != 0x02 &&
  520. loop_cnt != WCD_MEM_ENABLE_MAX_RETRIES);
  521. if ((status & 0x02) != 0x02) {
  522. dev_err(cntl->codec->dev,
  523. "%s: power domain not enabled, status = 0x%02x\n",
  524. __func__, status);
  525. ret = -EIO;
  526. goto done;
  527. }
  528. /* Rest of the memory */
  529. wcd9xxx_slim_write_repeat(wcd9xxx,
  530. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_2,
  531. ARRAY_SIZE(mem_enable_values),
  532. mem_enable_values);
  533. wcd9xxx_slim_write_repeat(wcd9xxx,
  534. WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_3,
  535. ARRAY_SIZE(mem_enable_values),
  536. mem_enable_values);
  537. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_DRAM1_SHUTDOWN,
  538. 0x05);
  539. break;
  540. default:
  541. dev_err(cntl->codec->dev, "%s: Invalid mem_type %d\n",
  542. __func__, mem_type);
  543. ret = -EINVAL;
  544. break;
  545. }
  546. done:
  547. /* Make sure Deep sleep of memories is enabled for all banks */
  548. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_0, 0xFF);
  549. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_1, 0x0F);
  550. return ret;
  551. }
  552. static void wcd_cntl_disable_memory(struct wcd_dsp_cntl *cntl,
  553. enum wcd_mem_type mem_type)
  554. {
  555. struct snd_soc_codec *codec = cntl->codec;
  556. u8 val;
  557. switch (mem_type) {
  558. case WCD_MEM_TYPE_ALWAYS_ON:
  559. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_1,
  560. 0xFF);
  561. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_0,
  562. 0xFF);
  563. break;
  564. case WCD_MEM_TYPE_SWITCHABLE:
  565. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_3,
  566. 0xFF);
  567. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_2,
  568. 0xFF);
  569. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_DRAM1_SHUTDOWN,
  570. 0x07);
  571. snd_soc_update_bits(codec, WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL,
  572. 0x01, 0x00);
  573. val = snd_soc_read(codec, WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL);
  574. if (val & 0x02)
  575. dev_err(codec->dev,
  576. "%s: Disable switchable failed, val = 0x%02x",
  577. __func__, val);
  578. snd_soc_update_bits(codec, WCD934X_TEST_DEBUG_MEM_CTRL,
  579. 0x80, 0x00);
  580. break;
  581. default:
  582. dev_err(cntl->codec->dev, "%s: Invalid mem_type %d\n",
  583. __func__, mem_type);
  584. break;
  585. }
  586. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_0, 0xFF);
  587. snd_soc_write(codec, WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_1, 0x0F);
  588. }
  589. static void wcd_cntl_do_shutdown(struct wcd_dsp_cntl *cntl)
  590. {
  591. struct snd_soc_codec *codec = cntl->codec;
  592. /* Disable WDOG */
  593. snd_soc_update_bits(codec, WCD934X_CPE_SS_WDOG_CFG,
  594. 0x3F, 0x01);
  595. /* Put WDSP in reset state */
  596. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPE_CTL,
  597. 0x02, 0x00);
  598. /* If DSP transitions from boot to shutdown, then vote for SVS */
  599. if (cntl->is_wdsp_booted)
  600. cntl->cdc_cb->cdc_vote_svs(codec, true);
  601. cntl->is_wdsp_booted = false;
  602. }
  603. static int wcd_cntl_do_boot(struct wcd_dsp_cntl *cntl)
  604. {
  605. struct snd_soc_codec *codec = cntl->codec;
  606. int ret = 0;
  607. /*
  608. * Debug mode is set from debugfs file node. If debug_mode
  609. * is set, then do not configure the watchdog timer. This
  610. * will be required for debugging the DSP firmware.
  611. */
  612. if (cntl->debug_mode) {
  613. snd_soc_update_bits(codec, WCD934X_CPE_SS_WDOG_CFG,
  614. 0x3F, 0x01);
  615. } else {
  616. snd_soc_update_bits(codec, WCD934X_CPE_SS_WDOG_CFG,
  617. 0x3F, 0x21);
  618. }
  619. /* Make sure all the error interrupts are cleared */
  620. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0A, 0xFF);
  621. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0B, 0xFF);
  622. reinit_completion(&cntl->boot_complete);
  623. /* Remove WDSP out of reset */
  624. snd_soc_update_bits(codec, WCD934X_CPE_SS_CPE_CTL,
  625. 0x02, 0x02);
  626. /*
  627. * In debug mode, DSP may not boot up normally,
  628. * wait indefinitely for DSP to boot.
  629. */
  630. if (cntl->debug_mode) {
  631. wait_for_completion(&cntl->boot_complete);
  632. dev_dbg(codec->dev, "%s: WDSP booted in dbg mode\n", __func__);
  633. cntl->is_wdsp_booted = true;
  634. goto done;
  635. }
  636. /* Boot in normal mode */
  637. ret = wait_for_completion_timeout(&cntl->boot_complete,
  638. msecs_to_jiffies(WCD_DSP_BOOT_TIMEOUT_MS));
  639. if (!ret) {
  640. dev_err(codec->dev, "%s: WDSP boot timed out\n",
  641. __func__);
  642. wcd_cntl_collect_debug_dumps(cntl);
  643. ret = -ETIMEDOUT;
  644. goto err_boot;
  645. } else {
  646. /*
  647. * Re-initialize the return code to 0, as in success case,
  648. * it will hold the remaining time for completion timeout
  649. */
  650. ret = 0;
  651. }
  652. dev_dbg(codec->dev, "%s: WDSP booted in normal mode\n", __func__);
  653. cntl->is_wdsp_booted = true;
  654. /* Enable WDOG */
  655. snd_soc_update_bits(codec, WCD934X_CPE_SS_WDOG_CFG,
  656. 0x10, 0x10);
  657. done:
  658. /* If dsp booted up, then remove vote on SVS */
  659. if (cntl->is_wdsp_booted)
  660. cntl->cdc_cb->cdc_vote_svs(codec, false);
  661. return ret;
  662. err_boot:
  663. /* call shutdown to perform cleanup */
  664. wcd_cntl_do_shutdown(cntl);
  665. return ret;
  666. }
  667. static irqreturn_t wcd_cntl_ipc_irq(int irq, void *data)
  668. {
  669. struct wcd_dsp_cntl *cntl = data;
  670. int ret;
  671. complete(&cntl->boot_complete);
  672. if (cntl->m_dev && cntl->m_ops &&
  673. cntl->m_ops->signal_handler)
  674. ret = cntl->m_ops->signal_handler(cntl->m_dev, WDSP_IPC1_INTR,
  675. NULL);
  676. else
  677. ret = -EINVAL;
  678. if (ret < 0)
  679. dev_err(cntl->codec->dev,
  680. "%s: Failed to handle irq %d\n", __func__, irq);
  681. return IRQ_HANDLED;
  682. }
  683. static irqreturn_t wcd_cntl_err_irq(int irq, void *data)
  684. {
  685. struct wcd_dsp_cntl *cntl = data;
  686. struct snd_soc_codec *codec = cntl->codec;
  687. struct wdsp_err_signal_arg arg;
  688. u16 status = 0;
  689. u8 reg_val;
  690. int rc, ret = 0;
  691. reg_val = snd_soc_read(codec, WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0A);
  692. status = status | reg_val;
  693. reg_val = snd_soc_read(codec, WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0B);
  694. status = status | (reg_val << 8);
  695. dev_info(codec->dev, "%s: error interrupt status = 0x%x\n",
  696. __func__, status);
  697. if ((status & cntl->irqs.fatal_irqs) &&
  698. (cntl->m_dev && cntl->m_ops && cntl->m_ops->signal_handler)) {
  699. /*
  700. * If WDSP SSR happens, skip collecting debug dumps.
  701. * If debug dumps collecting happens first, WDSP_ERR_INTR
  702. * will be blocked in signal_handler and get processed later.
  703. */
  704. rc = WCD_CNTL_SET_ERR_IRQ_FLAG(cntl);
  705. arg.mem_dumps_enabled = cntl->ramdump_enable;
  706. arg.remote_start_addr = WCD_934X_RAMDUMP_START_ADDR;
  707. arg.dump_size = WCD_934X_RAMDUMP_SIZE;
  708. ret = cntl->m_ops->signal_handler(cntl->m_dev, WDSP_ERR_INTR,
  709. &arg);
  710. if (ret < 0)
  711. dev_err(cntl->codec->dev,
  712. "%s: Failed to handle fatal irq 0x%x\n",
  713. __func__, status & cntl->irqs.fatal_irqs);
  714. wcd_cntl_change_online_state(cntl, 0);
  715. if (rc == 0)
  716. WCD_CNTL_CLR_ERR_IRQ_FLAG(cntl);
  717. } else {
  718. dev_err(cntl->codec->dev, "%s: Invalid signal_handler\n",
  719. __func__);
  720. }
  721. return IRQ_HANDLED;
  722. }
  723. static int wcd_control_handler(struct device *dev, void *priv_data,
  724. enum wdsp_event_type event, void *data)
  725. {
  726. struct wcd_dsp_cntl *cntl = priv_data;
  727. struct snd_soc_codec *codec = cntl->codec;
  728. int ret = 0;
  729. switch (event) {
  730. case WDSP_EVENT_POST_INIT:
  731. case WDSP_EVENT_POST_DLOAD_CODE:
  732. case WDSP_EVENT_DLOAD_FAILED:
  733. case WDSP_EVENT_POST_SHUTDOWN:
  734. /* Disable CPAR */
  735. wcd_cntl_cpar_ctrl(cntl, false);
  736. /* Disable all the clocks */
  737. ret = wcd_cntl_clocks_disable(cntl);
  738. if (ret < 0)
  739. dev_err(codec->dev,
  740. "%s: Failed to disable clocks, err = %d\n",
  741. __func__, ret);
  742. if (event == WDSP_EVENT_POST_DLOAD_CODE)
  743. /* Mark DSP online since code download is complete */
  744. wcd_cntl_change_online_state(cntl, 1);
  745. break;
  746. case WDSP_EVENT_PRE_DLOAD_DATA:
  747. case WDSP_EVENT_PRE_DLOAD_CODE:
  748. /* Enable all the clocks */
  749. ret = wcd_cntl_clocks_enable(cntl);
  750. if (ret < 0) {
  751. dev_err(codec->dev,
  752. "%s: Failed to enable clocks, err = %d\n",
  753. __func__, ret);
  754. goto done;
  755. }
  756. /* Enable CPAR */
  757. wcd_cntl_cpar_ctrl(cntl, true);
  758. if (event == WDSP_EVENT_PRE_DLOAD_CODE)
  759. wcd_cntl_enable_memory(cntl, WCD_MEM_TYPE_ALWAYS_ON);
  760. else if (event == WDSP_EVENT_PRE_DLOAD_DATA)
  761. wcd_cntl_enable_memory(cntl, WCD_MEM_TYPE_SWITCHABLE);
  762. break;
  763. case WDSP_EVENT_DO_BOOT:
  764. ret = wcd_cntl_do_boot(cntl);
  765. if (ret < 0)
  766. dev_err(codec->dev,
  767. "%s: WDSP boot failed, err = %d\n",
  768. __func__, ret);
  769. break;
  770. case WDSP_EVENT_DO_SHUTDOWN:
  771. wcd_cntl_do_shutdown(cntl);
  772. wcd_cntl_disable_memory(cntl, WCD_MEM_TYPE_SWITCHABLE);
  773. break;
  774. default:
  775. dev_dbg(codec->dev, "%s: unhandled event %d\n",
  776. __func__, event);
  777. }
  778. done:
  779. return ret;
  780. }
  781. static int wcd_cntl_sysfs_init(char *dir, struct wcd_dsp_cntl *cntl)
  782. {
  783. struct snd_soc_codec *codec = cntl->codec;
  784. int ret = 0;
  785. ret = kobject_init_and_add(&cntl->wcd_kobj, &wcd_cntl_ktype,
  786. kernel_kobj, dir);
  787. if (ret < 0) {
  788. dev_err(codec->dev,
  789. "%s: Failed to add kobject %s, err = %d\n",
  790. __func__, dir, ret);
  791. goto done;
  792. }
  793. ret = sysfs_create_file(&cntl->wcd_kobj, &cntl_attr_boot.attr);
  794. if (ret < 0) {
  795. dev_err(codec->dev,
  796. "%s: Failed to add wdsp_boot sysfs entry to %s\n",
  797. __func__, dir);
  798. goto fail_create_file;
  799. }
  800. return ret;
  801. fail_create_file:
  802. kobject_put(&cntl->wcd_kobj);
  803. done:
  804. return ret;
  805. }
  806. static void wcd_cntl_sysfs_remove(struct wcd_dsp_cntl *cntl)
  807. {
  808. sysfs_remove_file(&cntl->wcd_kobj, &cntl_attr_boot.attr);
  809. kobject_put(&cntl->wcd_kobj);
  810. }
  811. static void wcd_cntl_debugfs_init(char *dir, struct wcd_dsp_cntl *cntl)
  812. {
  813. struct snd_soc_codec *codec = cntl->codec;
  814. cntl->entry = debugfs_create_dir(dir, NULL);
  815. if (IS_ERR_OR_NULL(dir)) {
  816. dev_err(codec->dev, "%s debugfs_create_dir failed for %s\n",
  817. __func__, dir);
  818. goto done;
  819. }
  820. debugfs_create_u32("debug_mode", 0644,
  821. cntl->entry, &cntl->debug_mode);
  822. debugfs_create_bool("ramdump_enable", 0644,
  823. cntl->entry, &cntl->ramdump_enable);
  824. done:
  825. return;
  826. }
  827. static void wcd_cntl_debugfs_remove(struct wcd_dsp_cntl *cntl)
  828. {
  829. if (cntl)
  830. debugfs_remove(cntl->entry);
  831. }
  832. static int wcd_miscdev_release(struct inode *inode, struct file *filep)
  833. {
  834. struct wcd_dsp_cntl *cntl = container_of(filep->private_data,
  835. struct wcd_dsp_cntl, miscdev);
  836. if (!cntl->m_dev || !cntl->m_ops ||
  837. !cntl->m_ops->vote_for_dsp) {
  838. dev_err(cntl->codec->dev,
  839. "%s: DSP not ready to boot\n", __func__);
  840. return -EINVAL;
  841. }
  842. /* Make sure the DSP users goes to zero upon closing dev node */
  843. while (cntl->boot_reqs > 0) {
  844. cntl->m_ops->vote_for_dsp(cntl->m_dev, false);
  845. cntl->boot_reqs--;
  846. }
  847. return 0;
  848. }
  849. static ssize_t wcd_miscdev_write(struct file *filep, const char __user *ubuf,
  850. size_t count, loff_t *pos)
  851. {
  852. struct wcd_dsp_cntl *cntl = container_of(filep->private_data,
  853. struct wcd_dsp_cntl, miscdev);
  854. char val[WCD_MISCDEV_CMD_MAX_LEN];
  855. bool vote;
  856. int ret = 0;
  857. if (count == 0 || count > WCD_MISCDEV_CMD_MAX_LEN) {
  858. pr_err("%s: Invalid count = %zd\n", __func__, count);
  859. ret = -EINVAL;
  860. goto done;
  861. }
  862. ret = copy_from_user(val, ubuf, count);
  863. if (ret < 0) {
  864. dev_err(cntl->codec->dev,
  865. "%s: copy_from_user failed, err = %d\n",
  866. __func__, ret);
  867. ret = -EFAULT;
  868. goto done;
  869. }
  870. if (val[0] == '1') {
  871. cntl->boot_reqs++;
  872. vote = true;
  873. } else if (val[0] == '0') {
  874. if (cntl->boot_reqs == 0) {
  875. dev_err(cntl->codec->dev,
  876. "%s: WDSP already disabled\n", __func__);
  877. ret = -EINVAL;
  878. goto done;
  879. }
  880. cntl->boot_reqs--;
  881. vote = false;
  882. } else if (!strcmp(val, "DEBUG_DUMP")) {
  883. dev_dbg(cntl->codec->dev,
  884. "%s: Collect dumps for debug use\n", __func__);
  885. wcd_cntl_collect_debug_dumps(cntl);
  886. goto done;
  887. } else {
  888. dev_err(cntl->codec->dev, "%s: Invalid value %s\n",
  889. __func__, val);
  890. ret = -EINVAL;
  891. goto done;
  892. }
  893. dev_dbg(cntl->codec->dev,
  894. "%s: booted = %s, ref_cnt = %d, vote = %s\n",
  895. __func__, cntl->is_wdsp_booted ? "true" : "false",
  896. cntl->boot_reqs, vote ? "true" : "false");
  897. if (cntl->m_dev && cntl->m_ops &&
  898. cntl->m_ops->vote_for_dsp)
  899. ret = cntl->m_ops->vote_for_dsp(cntl->m_dev, vote);
  900. else
  901. ret = -EINVAL;
  902. done:
  903. if (ret)
  904. return ret;
  905. else
  906. return count;
  907. }
  908. static const struct file_operations wcd_miscdev_fops = {
  909. .write = wcd_miscdev_write,
  910. .release = wcd_miscdev_release,
  911. };
  912. static int wcd_cntl_miscdev_create(struct wcd_dsp_cntl *cntl)
  913. {
  914. snprintf(cntl->miscdev_name, ARRAY_SIZE(cntl->miscdev_name),
  915. "wcd_dsp%u_control", cntl->dsp_instance);
  916. cntl->miscdev.minor = MISC_DYNAMIC_MINOR;
  917. cntl->miscdev.name = cntl->miscdev_name;
  918. cntl->miscdev.fops = &wcd_miscdev_fops;
  919. cntl->miscdev.parent = cntl->codec->dev;
  920. return misc_register(&cntl->miscdev);
  921. }
  922. static void wcd_cntl_miscdev_destroy(struct wcd_dsp_cntl *cntl)
  923. {
  924. misc_deregister(&cntl->miscdev);
  925. }
  926. static int wcd_control_init(struct device *dev, void *priv_data)
  927. {
  928. struct wcd_dsp_cntl *cntl = priv_data;
  929. struct snd_soc_codec *codec = cntl->codec;
  930. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  931. struct wcd9xxx_core_resource *core_res = &wcd9xxx->core_res;
  932. int ret;
  933. bool err_irq_requested = false;
  934. ret = wcd9xxx_request_irq(core_res,
  935. cntl->irqs.cpe_ipc1_irq,
  936. wcd_cntl_ipc_irq, "CPE IPC1",
  937. cntl);
  938. if (ret < 0) {
  939. dev_err(codec->dev,
  940. "%s: Failed to request cpe ipc irq, err = %d\n",
  941. __func__, ret);
  942. goto done;
  943. }
  944. /* Unmask the fatal irqs */
  945. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A,
  946. ~(cntl->irqs.fatal_irqs & 0xFF));
  947. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B,
  948. ~((cntl->irqs.fatal_irqs >> 8) & 0xFF));
  949. /*
  950. * CPE ERR irq is used only for error reporting from WCD DSP,
  951. * even if this request fails, DSP can be function normally.
  952. * Continuing with init even if the CPE ERR irq request fails.
  953. */
  954. if (wcd9xxx_request_irq(core_res, cntl->irqs.cpe_err_irq,
  955. wcd_cntl_err_irq, "CPE ERR", cntl))
  956. dev_info(codec->dev, "%s: Failed request_irq(cpe_err_irq)",
  957. __func__);
  958. else
  959. err_irq_requested = true;
  960. /* Enable all the clocks */
  961. ret = wcd_cntl_clocks_enable(cntl);
  962. if (ret < 0) {
  963. dev_err(codec->dev, "%s: Failed to enable clocks, err = %d\n",
  964. __func__, ret);
  965. goto err_clk_enable;
  966. }
  967. wcd_cntl_cpar_ctrl(cntl, true);
  968. return 0;
  969. err_clk_enable:
  970. /* Mask all error interrupts */
  971. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A, 0xFF);
  972. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B, 0xFF);
  973. /* Free the irq's requested */
  974. wcd9xxx_free_irq(core_res, cntl->irqs.cpe_ipc1_irq, cntl);
  975. if (err_irq_requested)
  976. wcd9xxx_free_irq(core_res, cntl->irqs.cpe_err_irq, cntl);
  977. done:
  978. return ret;
  979. }
  980. static int wcd_control_deinit(struct device *dev, void *priv_data)
  981. {
  982. struct wcd_dsp_cntl *cntl = priv_data;
  983. struct snd_soc_codec *codec = cntl->codec;
  984. struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent);
  985. struct wcd9xxx_core_resource *core_res = &wcd9xxx->core_res;
  986. wcd_cntl_clocks_disable(cntl);
  987. wcd_cntl_cpar_ctrl(cntl, false);
  988. /* Mask all error interrupts */
  989. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A, 0xFF);
  990. snd_soc_write(codec, WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B, 0xFF);
  991. /* Free the irq's requested */
  992. wcd9xxx_free_irq(core_res, cntl->irqs.cpe_err_irq, cntl);
  993. wcd9xxx_free_irq(core_res, cntl->irqs.cpe_ipc1_irq, cntl);
  994. return 0;
  995. }
  996. static struct wdsp_cmpnt_ops control_ops = {
  997. .init = wcd_control_init,
  998. .deinit = wcd_control_deinit,
  999. .event_handler = wcd_control_handler,
  1000. };
  1001. static int wcd_ctrl_component_bind(struct device *dev,
  1002. struct device *master,
  1003. void *data)
  1004. {
  1005. struct wcd_dsp_cntl *cntl;
  1006. struct snd_soc_codec *codec;
  1007. struct snd_card *card;
  1008. struct snd_info_entry *entry;
  1009. char proc_name[WCD_PROCFS_ENTRY_MAX_LEN];
  1010. char wcd_cntl_dir_name[WCD_CNTL_DIR_NAME_LEN_MAX];
  1011. int ret = 0;
  1012. if (!dev || !master || !data) {
  1013. pr_err("%s: Invalid parameters\n", __func__);
  1014. return -EINVAL;
  1015. }
  1016. cntl = tavil_get_wcd_dsp_cntl(dev);
  1017. if (!cntl) {
  1018. dev_err(dev, "%s: Failed to get cntl reference\n",
  1019. __func__);
  1020. return -EINVAL;
  1021. }
  1022. cntl->m_dev = master;
  1023. cntl->m_ops = data;
  1024. if (!cntl->m_ops->register_cmpnt_ops) {
  1025. dev_err(dev, "%s: invalid master callback register_cmpnt_ops\n",
  1026. __func__);
  1027. ret = -EINVAL;
  1028. goto done;
  1029. }
  1030. ret = cntl->m_ops->register_cmpnt_ops(master, dev, cntl, &control_ops);
  1031. if (ret) {
  1032. dev_err(dev, "%s: register_cmpnt_ops failed, err = %d\n",
  1033. __func__, ret);
  1034. goto done;
  1035. }
  1036. ret = wcd_cntl_miscdev_create(cntl);
  1037. if (ret < 0) {
  1038. dev_err(dev, "%s: misc dev register failed, err = %d\n",
  1039. __func__, ret);
  1040. goto done;
  1041. }
  1042. snprintf(wcd_cntl_dir_name, WCD_CNTL_DIR_NAME_LEN_MAX,
  1043. "%s%d", "wdsp", cntl->dsp_instance);
  1044. ret = wcd_cntl_sysfs_init(wcd_cntl_dir_name, cntl);
  1045. if (ret < 0) {
  1046. dev_err(dev, "%s: sysfs_init failed, err = %d\n",
  1047. __func__, ret);
  1048. goto err_sysfs_init;
  1049. }
  1050. wcd_cntl_debugfs_init(wcd_cntl_dir_name, cntl);
  1051. codec = cntl->codec;
  1052. card = codec->component.card->snd_card;
  1053. snprintf(proc_name, WCD_PROCFS_ENTRY_MAX_LEN, "%s%d%s", "cpe",
  1054. cntl->dsp_instance, "_state");
  1055. entry = snd_info_create_card_entry(card, proc_name, card->proc_root);
  1056. if (!entry) {
  1057. /* Do not treat this as Fatal error */
  1058. dev_err(dev, "%s: Failed to create procfs entry %s\n",
  1059. __func__, proc_name);
  1060. goto err_sysfs_init;
  1061. }
  1062. cntl->ssr_entry.entry = entry;
  1063. cntl->ssr_entry.offline = 1;
  1064. entry->size = WCD_PROCFS_ENTRY_MAX_LEN;
  1065. entry->content = SNDRV_INFO_CONTENT_DATA;
  1066. entry->c.ops = &wdsp_ssr_entry_ops;
  1067. entry->private_data = cntl;
  1068. ret = snd_info_register(entry);
  1069. if (ret < 0) {
  1070. dev_err(dev, "%s: Failed to register entry %s, err = %d\n",
  1071. __func__, proc_name, ret);
  1072. snd_info_free_entry(entry);
  1073. /* Let bind still happen even if creating the entry failed */
  1074. ret = 0;
  1075. }
  1076. done:
  1077. return ret;
  1078. err_sysfs_init:
  1079. wcd_cntl_miscdev_destroy(cntl);
  1080. return ret;
  1081. }
  1082. static void wcd_ctrl_component_unbind(struct device *dev,
  1083. struct device *master,
  1084. void *data)
  1085. {
  1086. struct wcd_dsp_cntl *cntl;
  1087. if (!dev) {
  1088. pr_err("%s: Invalid device\n", __func__);
  1089. return;
  1090. }
  1091. cntl = tavil_get_wcd_dsp_cntl(dev);
  1092. if (!cntl) {
  1093. dev_err(dev, "%s: Failed to get cntl reference\n",
  1094. __func__);
  1095. return;
  1096. }
  1097. cntl->m_dev = NULL;
  1098. cntl->m_ops = NULL;
  1099. /* Remove the sysfs entries */
  1100. wcd_cntl_sysfs_remove(cntl);
  1101. /* Remove the debugfs entries */
  1102. wcd_cntl_debugfs_remove(cntl);
  1103. /* Remove the misc device */
  1104. wcd_cntl_miscdev_destroy(cntl);
  1105. }
  1106. static const struct component_ops wcd_ctrl_component_ops = {
  1107. .bind = wcd_ctrl_component_bind,
  1108. .unbind = wcd_ctrl_component_unbind,
  1109. };
  1110. /*
  1111. * wcd_dsp_ssr_event: handle the SSR event raised by caller.
  1112. * @cntl: Handle to the wcd_dsp_cntl structure
  1113. * @event: The SSR event to be handled
  1114. *
  1115. * Notifies the manager driver about the SSR event.
  1116. * Returns 0 on success and negative error code on error.
  1117. */
  1118. int wcd_dsp_ssr_event(struct wcd_dsp_cntl *cntl, enum cdc_ssr_event event)
  1119. {
  1120. int ret = 0;
  1121. if (!cntl) {
  1122. pr_err("%s: Invalid handle to control\n", __func__);
  1123. return -EINVAL;
  1124. }
  1125. if (!cntl->m_dev || !cntl->m_ops || !cntl->m_ops->signal_handler) {
  1126. dev_err(cntl->codec->dev,
  1127. "%s: Invalid signal_handler callback\n", __func__);
  1128. return -EINVAL;
  1129. }
  1130. switch (event) {
  1131. case WCD_CDC_DOWN_EVENT:
  1132. ret = cntl->m_ops->signal_handler(cntl->m_dev,
  1133. WDSP_CDC_DOWN_SIGNAL,
  1134. NULL);
  1135. if (ret < 0)
  1136. dev_err(cntl->codec->dev,
  1137. "%s: WDSP_CDC_DOWN_SIGNAL failed, err = %d\n",
  1138. __func__, ret);
  1139. wcd_cntl_change_online_state(cntl, 0);
  1140. break;
  1141. case WCD_CDC_UP_EVENT:
  1142. ret = cntl->m_ops->signal_handler(cntl->m_dev,
  1143. WDSP_CDC_UP_SIGNAL,
  1144. NULL);
  1145. if (ret < 0)
  1146. dev_err(cntl->codec->dev,
  1147. "%s: WDSP_CDC_UP_SIGNAL failed, err = %d\n",
  1148. __func__, ret);
  1149. break;
  1150. default:
  1151. dev_err(cntl->codec->dev, "%s: Invalid event %d\n",
  1152. __func__, event);
  1153. ret = -EINVAL;
  1154. break;
  1155. }
  1156. return ret;
  1157. }
  1158. EXPORT_SYMBOL(wcd_dsp_ssr_event);
  1159. /*
  1160. * wcd_dsp_cntl_init: Initialize the wcd-dsp control
  1161. * @codec: pointer to the codec handle
  1162. * @params: Parameters required to initialize wcd-dsp control
  1163. *
  1164. * This API is expected to be invoked by the codec driver and
  1165. * provide information essential for the wcd dsp control to
  1166. * configure and initialize the dsp
  1167. */
  1168. void wcd_dsp_cntl_init(struct snd_soc_codec *codec,
  1169. struct wcd_dsp_params *params,
  1170. struct wcd_dsp_cntl **cntl)
  1171. {
  1172. struct wcd_dsp_cntl *control;
  1173. int ret;
  1174. if (!codec || !params) {
  1175. pr_err("%s: Invalid handle to %s\n", __func__,
  1176. (!codec) ? "codec" : "params");
  1177. *cntl = NULL;
  1178. return;
  1179. }
  1180. if (*cntl) {
  1181. pr_err("%s: cntl is non NULL, maybe already initialized ?\n",
  1182. __func__);
  1183. return;
  1184. }
  1185. if (!params->cb || !params->cb->cdc_clk_en ||
  1186. !params->cb->cdc_vote_svs) {
  1187. dev_err(codec->dev,
  1188. "%s: clk_en and vote_svs callbacks must be provided\n",
  1189. __func__);
  1190. return;
  1191. }
  1192. control = kzalloc(sizeof(*control), GFP_KERNEL);
  1193. if (!(control))
  1194. return;
  1195. control->codec = codec;
  1196. control->clk_rate = params->clk_rate;
  1197. control->cdc_cb = params->cb;
  1198. control->dsp_instance = params->dsp_instance;
  1199. memcpy(&control->irqs, &params->irqs, sizeof(control->irqs));
  1200. init_completion(&control->boot_complete);
  1201. mutex_init(&control->clk_mutex);
  1202. mutex_init(&control->ssr_mutex);
  1203. init_waitqueue_head(&control->ssr_entry.offline_poll_wait);
  1204. WCD_CNTL_CLR_ERR_IRQ_FLAG(control);
  1205. /*
  1206. * The default state of WDSP is in SVS mode.
  1207. * Vote for SVS now, the vote will be removed only
  1208. * after DSP is booted up.
  1209. */
  1210. control->cdc_cb->cdc_vote_svs(codec, true);
  1211. /*
  1212. * If this is the last component needed by master to be ready,
  1213. * then component_bind will be called within the component_add.
  1214. * Hence, the data pointer should be assigned before component_add,
  1215. * so that we can access it during this component's bind call.
  1216. */
  1217. *cntl = control;
  1218. ret = component_add(codec->dev, &wcd_ctrl_component_ops);
  1219. if (ret) {
  1220. dev_err(codec->dev, "%s: component_add failed, err = %d\n",
  1221. __func__, ret);
  1222. kfree(*cntl);
  1223. *cntl = NULL;
  1224. }
  1225. }
  1226. EXPORT_SYMBOL(wcd_dsp_cntl_init);
  1227. /*
  1228. * wcd_dsp_cntl_deinit: De-initialize the wcd-dsp control
  1229. * @cntl: The struct wcd_dsp_cntl to de-initialize
  1230. *
  1231. * This API is intended to be invoked by the codec driver
  1232. * to de-initialize the wcd dsp control
  1233. */
  1234. void wcd_dsp_cntl_deinit(struct wcd_dsp_cntl **cntl)
  1235. {
  1236. struct wcd_dsp_cntl *control = *cntl;
  1237. struct snd_soc_codec *codec;
  1238. /* If control is NULL, there is nothing to de-initialize */
  1239. if (!control)
  1240. return;
  1241. codec = control->codec;
  1242. /*
  1243. * Calling shutdown will cleanup all register states,
  1244. * irrespective of DSP was booted up or not.
  1245. */
  1246. wcd_cntl_do_shutdown(control);
  1247. wcd_cntl_disable_memory(control, WCD_MEM_TYPE_SWITCHABLE);
  1248. wcd_cntl_disable_memory(control, WCD_MEM_TYPE_ALWAYS_ON);
  1249. component_del(codec->dev, &wcd_ctrl_component_ops);
  1250. mutex_destroy(&control->clk_mutex);
  1251. mutex_destroy(&control->ssr_mutex);
  1252. kfree(*cntl);
  1253. *cntl = NULL;
  1254. }
  1255. EXPORT_SYMBOL(wcd_dsp_cntl_deinit);