dp_tx.c 178 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  987. static bool
  988. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  989. struct cdp_tx_exception_metadata *tx_exc_metadata)
  990. {
  991. if (soc->features.wds_ext_ast_override_enable &&
  992. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  993. return true;
  994. return false;
  995. }
  996. #else
  997. static bool
  998. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  999. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1000. {
  1001. return false;
  1002. }
  1003. #endif
  1004. /**
  1005. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  1006. * @vdev: DP vdev handle
  1007. * @nbuf: skb
  1008. * @desc_pool_id: Descriptor pool ID
  1009. * @meta_data: Metadata to the fw
  1010. * @tx_exc_metadata: Handle that holds exception path metadata
  1011. * Allocate and prepare Tx descriptor with msdu information.
  1012. *
  1013. * Return: Pointer to Tx Descriptor on success,
  1014. * NULL on failure
  1015. */
  1016. static
  1017. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1018. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1019. struct dp_tx_msdu_info_s *msdu_info,
  1020. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1021. {
  1022. uint8_t align_pad;
  1023. uint8_t is_exception = 0;
  1024. uint8_t htt_hdr_size;
  1025. struct dp_tx_desc_s *tx_desc;
  1026. struct dp_pdev *pdev = vdev->pdev;
  1027. struct dp_soc *soc = pdev->soc;
  1028. if (dp_tx_limit_check(vdev, nbuf))
  1029. return NULL;
  1030. /* Allocate software Tx descriptor */
  1031. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1032. if (qdf_unlikely(!tx_desc)) {
  1033. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1034. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1035. return NULL;
  1036. }
  1037. dp_tx_outstanding_inc(pdev);
  1038. /* Initialize the SW tx descriptor */
  1039. tx_desc->nbuf = nbuf;
  1040. tx_desc->frm_type = dp_tx_frm_std;
  1041. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1042. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1043. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1044. tx_desc->vdev_id = vdev->vdev_id;
  1045. tx_desc->pdev = pdev;
  1046. tx_desc->msdu_ext_desc = NULL;
  1047. tx_desc->pkt_offset = 0;
  1048. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1049. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1050. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1051. if (qdf_unlikely(vdev->multipass_en)) {
  1052. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1053. goto failure;
  1054. }
  1055. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1056. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1057. is_exception = 1;
  1058. /* for BE chipsets if wds extension was enbled will not mark FW
  1059. * in desc will mark ast index based search for ast index.
  1060. */
  1061. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1062. return tx_desc;
  1063. /*
  1064. * For special modes (vdev_type == ocb or mesh), data frames should be
  1065. * transmitted using varying transmit parameters (tx spec) which include
  1066. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1067. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1068. * These frames are sent as exception packets to firmware.
  1069. *
  1070. * HW requirement is that metadata should always point to a
  1071. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1072. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1073. * to get 8-byte aligned start address along with align_pad added
  1074. *
  1075. * |-----------------------------|
  1076. * | |
  1077. * |-----------------------------| <-----Buffer Pointer Address given
  1078. * | | ^ in HW descriptor (aligned)
  1079. * | HTT Metadata | |
  1080. * | | |
  1081. * | | | Packet Offset given in descriptor
  1082. * | | |
  1083. * |-----------------------------| |
  1084. * | Alignment Pad | v
  1085. * |-----------------------------| <----- Actual buffer start address
  1086. * | SKB Data | (Unaligned)
  1087. * | |
  1088. * | |
  1089. * | |
  1090. * | |
  1091. * | |
  1092. * |-----------------------------|
  1093. */
  1094. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1095. (vdev->opmode == wlan_op_mode_ocb) ||
  1096. (tx_exc_metadata &&
  1097. tx_exc_metadata->is_tx_sniffer)) {
  1098. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1099. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1100. DP_STATS_INC(vdev,
  1101. tx_i.dropped.headroom_insufficient, 1);
  1102. goto failure;
  1103. }
  1104. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1105. dp_tx_err("qdf_nbuf_push_head failed");
  1106. goto failure;
  1107. }
  1108. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1109. msdu_info);
  1110. if (htt_hdr_size == 0)
  1111. goto failure;
  1112. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1113. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1114. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1115. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1116. msdu_info);
  1117. is_exception = 1;
  1118. tx_desc->length -= tx_desc->pkt_offset;
  1119. }
  1120. #if !TQM_BYPASS_WAR
  1121. if (is_exception || tx_exc_metadata)
  1122. #endif
  1123. {
  1124. /* Temporary WAR due to TQM VP issues */
  1125. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1126. qdf_atomic_inc(&soc->num_tx_exception);
  1127. }
  1128. return tx_desc;
  1129. failure:
  1130. dp_tx_desc_release(tx_desc, desc_pool_id);
  1131. return NULL;
  1132. }
  1133. /**
  1134. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1135. * @vdev: DP vdev handle
  1136. * @nbuf: skb
  1137. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1138. * @desc_pool_id : Descriptor Pool ID
  1139. *
  1140. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1141. * information. For frames with fragments, allocate and prepare
  1142. * an MSDU extension descriptor
  1143. *
  1144. * Return: Pointer to Tx Descriptor on success,
  1145. * NULL on failure
  1146. */
  1147. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1148. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1149. uint8_t desc_pool_id)
  1150. {
  1151. struct dp_tx_desc_s *tx_desc;
  1152. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1153. struct dp_pdev *pdev = vdev->pdev;
  1154. struct dp_soc *soc = pdev->soc;
  1155. if (dp_tx_limit_check(vdev, nbuf))
  1156. return NULL;
  1157. /* Allocate software Tx descriptor */
  1158. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1159. if (!tx_desc) {
  1160. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1161. return NULL;
  1162. }
  1163. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1164. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1165. dp_tx_outstanding_inc(pdev);
  1166. /* Initialize the SW tx descriptor */
  1167. tx_desc->nbuf = nbuf;
  1168. tx_desc->frm_type = msdu_info->frm_type;
  1169. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1170. tx_desc->vdev_id = vdev->vdev_id;
  1171. tx_desc->pdev = pdev;
  1172. tx_desc->pkt_offset = 0;
  1173. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1174. /* Handle scattered frames - TSO/SG/ME */
  1175. /* Allocate and prepare an extension descriptor for scattered frames */
  1176. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1177. if (!msdu_ext_desc) {
  1178. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1179. goto failure;
  1180. }
  1181. #if TQM_BYPASS_WAR
  1182. /* Temporary WAR due to TQM VP issues */
  1183. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1184. qdf_atomic_inc(&soc->num_tx_exception);
  1185. #endif
  1186. if (qdf_unlikely(msdu_info->exception_fw))
  1187. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1188. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1189. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1190. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1191. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1192. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1193. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1194. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1195. else
  1196. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1197. return tx_desc;
  1198. failure:
  1199. dp_tx_desc_release(tx_desc, desc_pool_id);
  1200. return NULL;
  1201. }
  1202. /**
  1203. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1204. * @vdev: DP vdev handle
  1205. * @nbuf: buffer pointer
  1206. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1207. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1208. * descriptor
  1209. *
  1210. * Return:
  1211. */
  1212. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1213. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1214. {
  1215. qdf_nbuf_t curr_nbuf = NULL;
  1216. uint16_t total_len = 0;
  1217. qdf_dma_addr_t paddr;
  1218. int32_t i;
  1219. int32_t mapped_buf_num = 0;
  1220. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1221. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1222. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1223. /* Continue only if frames are of DATA type */
  1224. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1225. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1226. dp_tx_debug("Pkt. recd is of not data type");
  1227. goto error;
  1228. }
  1229. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1230. if (vdev->raw_mode_war &&
  1231. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1232. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1233. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1234. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1235. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1236. /*
  1237. * Number of nbuf's must not exceed the size of the frags
  1238. * array in seg_info.
  1239. */
  1240. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1241. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1242. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1243. goto error;
  1244. }
  1245. if (QDF_STATUS_SUCCESS !=
  1246. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1247. curr_nbuf,
  1248. QDF_DMA_TO_DEVICE,
  1249. curr_nbuf->len)) {
  1250. dp_tx_err("%s dma map error ", __func__);
  1251. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1252. goto error;
  1253. }
  1254. /* Update the count of mapped nbuf's */
  1255. mapped_buf_num++;
  1256. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1257. seg_info->frags[i].paddr_lo = paddr;
  1258. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1259. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1260. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1261. total_len += qdf_nbuf_len(curr_nbuf);
  1262. }
  1263. seg_info->frag_cnt = i;
  1264. seg_info->total_len = total_len;
  1265. seg_info->next = NULL;
  1266. sg_info->curr_seg = seg_info;
  1267. msdu_info->frm_type = dp_tx_frm_raw;
  1268. msdu_info->num_seg = 1;
  1269. return nbuf;
  1270. error:
  1271. i = 0;
  1272. while (nbuf) {
  1273. curr_nbuf = nbuf;
  1274. if (i < mapped_buf_num) {
  1275. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1276. QDF_DMA_TO_DEVICE,
  1277. curr_nbuf->len);
  1278. i++;
  1279. }
  1280. nbuf = qdf_nbuf_next(nbuf);
  1281. qdf_nbuf_free(curr_nbuf);
  1282. }
  1283. return NULL;
  1284. }
  1285. /**
  1286. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1287. * @soc: DP soc handle
  1288. * @nbuf: Buffer pointer
  1289. *
  1290. * unmap the chain of nbufs that belong to this RAW frame.
  1291. *
  1292. * Return: None
  1293. */
  1294. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1295. qdf_nbuf_t nbuf)
  1296. {
  1297. qdf_nbuf_t cur_nbuf = nbuf;
  1298. do {
  1299. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1300. QDF_DMA_TO_DEVICE,
  1301. cur_nbuf->len);
  1302. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1303. } while (cur_nbuf);
  1304. }
  1305. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1306. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1307. qdf_nbuf_t nbuf)
  1308. {
  1309. qdf_nbuf_t nbuf_local;
  1310. struct dp_vdev *vdev_local = vdev_hdl;
  1311. do {
  1312. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1313. break;
  1314. nbuf_local = nbuf;
  1315. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1316. htt_cmn_pkt_type_raw))
  1317. break;
  1318. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1319. break;
  1320. else if (qdf_nbuf_is_tso((nbuf_local)))
  1321. break;
  1322. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1323. (nbuf_local),
  1324. NULL, 1, 0);
  1325. } while (0);
  1326. }
  1327. #endif
  1328. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1329. /**
  1330. * dp_tx_update_stats() - Update soc level tx stats
  1331. * @soc: DP soc handle
  1332. * @tx_desc: TX descriptor reference
  1333. * @ring_id: TCL ring id
  1334. *
  1335. * Returns: none
  1336. */
  1337. void dp_tx_update_stats(struct dp_soc *soc,
  1338. struct dp_tx_desc_s *tx_desc,
  1339. uint8_t ring_id)
  1340. {
  1341. uint32_t stats_len = dp_tx_get_pkt_len(tx_desc);
  1342. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1343. }
  1344. int
  1345. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1346. struct dp_tx_desc_s *tx_desc,
  1347. uint8_t tid,
  1348. struct dp_tx_msdu_info_s *msdu_info,
  1349. uint8_t ring_id)
  1350. {
  1351. struct dp_swlm *swlm = &soc->swlm;
  1352. union swlm_data swlm_query_data;
  1353. struct dp_swlm_tcl_data tcl_data;
  1354. QDF_STATUS status;
  1355. int ret;
  1356. if (!swlm->is_enabled)
  1357. return msdu_info->skip_hp_update;
  1358. tcl_data.nbuf = tx_desc->nbuf;
  1359. tcl_data.tid = tid;
  1360. tcl_data.ring_id = ring_id;
  1361. tcl_data.pkt_len = dp_tx_get_pkt_len(tx_desc);
  1362. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1363. swlm_query_data.tcl_data = &tcl_data;
  1364. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1365. if (QDF_IS_STATUS_ERROR(status)) {
  1366. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1367. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1368. return 0;
  1369. }
  1370. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1371. if (ret) {
  1372. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1373. } else {
  1374. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1375. }
  1376. return ret;
  1377. }
  1378. void
  1379. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1380. int coalesce)
  1381. {
  1382. if (coalesce)
  1383. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1384. else
  1385. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1386. }
  1387. static inline void
  1388. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1389. {
  1390. if (((i + 1) < msdu_info->num_seg))
  1391. msdu_info->skip_hp_update = 1;
  1392. else
  1393. msdu_info->skip_hp_update = 0;
  1394. }
  1395. static inline void
  1396. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1397. {
  1398. hal_ring_handle_t hal_ring_hdl =
  1399. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1400. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1401. dp_err("Fillmore: SRNG access start failed");
  1402. return;
  1403. }
  1404. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1405. }
  1406. static inline void
  1407. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1408. QDF_STATUS status,
  1409. struct dp_tx_msdu_info_s *msdu_info)
  1410. {
  1411. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1412. dp_flush_tcp_hp(soc,
  1413. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1414. }
  1415. }
  1416. #else
  1417. static inline void
  1418. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1419. {
  1420. }
  1421. static inline void
  1422. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1423. QDF_STATUS status,
  1424. struct dp_tx_msdu_info_s *msdu_info)
  1425. {
  1426. }
  1427. #endif
  1428. #ifdef FEATURE_RUNTIME_PM
  1429. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1430. {
  1431. int ret;
  1432. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1433. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1434. return ret;
  1435. }
  1436. /**
  1437. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1438. * @soc: Datapath soc handle
  1439. * @hal_ring_hdl: HAL ring handle
  1440. * @coalesce: Coalesce the current write or not
  1441. *
  1442. * Wrapper for HAL ring access end for data transmission for
  1443. * FEATURE_RUNTIME_PM
  1444. *
  1445. * Returns: none
  1446. */
  1447. void
  1448. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1449. hal_ring_handle_t hal_ring_hdl,
  1450. int coalesce)
  1451. {
  1452. int ret;
  1453. /*
  1454. * Avoid runtime get and put APIs under high throughput scenarios.
  1455. */
  1456. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1457. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1458. return;
  1459. }
  1460. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1461. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1462. if (hif_system_pm_state_check(soc->hif_handle)) {
  1463. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1464. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1465. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1466. } else {
  1467. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1468. }
  1469. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1470. } else {
  1471. dp_runtime_get(soc);
  1472. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1473. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1474. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1475. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1476. dp_runtime_put(soc);
  1477. }
  1478. }
  1479. #else
  1480. #ifdef DP_POWER_SAVE
  1481. void
  1482. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1483. hal_ring_handle_t hal_ring_hdl,
  1484. int coalesce)
  1485. {
  1486. if (hif_system_pm_state_check(soc->hif_handle)) {
  1487. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1488. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1489. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1490. } else {
  1491. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1492. }
  1493. }
  1494. #endif
  1495. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1496. {
  1497. return 0;
  1498. }
  1499. #endif
  1500. /**
  1501. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1502. * @vdev: DP vdev handle
  1503. * @nbuf: skb
  1504. *
  1505. * Extract the DSCP or PCP information from frame and map into TID value.
  1506. *
  1507. * Return: void
  1508. */
  1509. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1510. struct dp_tx_msdu_info_s *msdu_info)
  1511. {
  1512. uint8_t tos = 0, dscp_tid_override = 0;
  1513. uint8_t *hdr_ptr, *L3datap;
  1514. uint8_t is_mcast = 0;
  1515. qdf_ether_header_t *eh = NULL;
  1516. qdf_ethervlan_header_t *evh = NULL;
  1517. uint16_t ether_type;
  1518. qdf_llc_t *llcHdr;
  1519. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1520. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1521. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1522. eh = (qdf_ether_header_t *)nbuf->data;
  1523. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1524. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1525. } else {
  1526. qdf_dot3_qosframe_t *qos_wh =
  1527. (qdf_dot3_qosframe_t *) nbuf->data;
  1528. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1529. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1530. return;
  1531. }
  1532. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1533. ether_type = eh->ether_type;
  1534. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1535. /*
  1536. * Check if packet is dot3 or eth2 type.
  1537. */
  1538. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1539. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1540. sizeof(*llcHdr));
  1541. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1542. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1543. sizeof(*llcHdr);
  1544. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1545. + sizeof(*llcHdr) +
  1546. sizeof(qdf_net_vlanhdr_t));
  1547. } else {
  1548. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1549. sizeof(*llcHdr);
  1550. }
  1551. } else {
  1552. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1553. evh = (qdf_ethervlan_header_t *) eh;
  1554. ether_type = evh->ether_type;
  1555. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1556. }
  1557. }
  1558. /*
  1559. * Find priority from IP TOS DSCP field
  1560. */
  1561. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1562. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1563. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1564. /* Only for unicast frames */
  1565. if (!is_mcast) {
  1566. /* send it on VO queue */
  1567. msdu_info->tid = DP_VO_TID;
  1568. }
  1569. } else {
  1570. /*
  1571. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1572. * from TOS byte.
  1573. */
  1574. tos = ip->ip_tos;
  1575. dscp_tid_override = 1;
  1576. }
  1577. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1578. /* TODO
  1579. * use flowlabel
  1580. *igmpmld cases to be handled in phase 2
  1581. */
  1582. unsigned long ver_pri_flowlabel;
  1583. unsigned long pri;
  1584. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1585. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1586. DP_IPV6_PRIORITY_SHIFT;
  1587. tos = pri;
  1588. dscp_tid_override = 1;
  1589. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1590. msdu_info->tid = DP_VO_TID;
  1591. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1592. /* Only for unicast frames */
  1593. if (!is_mcast) {
  1594. /* send ucast arp on VO queue */
  1595. msdu_info->tid = DP_VO_TID;
  1596. }
  1597. }
  1598. /*
  1599. * Assign all MCAST packets to BE
  1600. */
  1601. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1602. if (is_mcast) {
  1603. tos = 0;
  1604. dscp_tid_override = 1;
  1605. }
  1606. }
  1607. if (dscp_tid_override == 1) {
  1608. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1609. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1610. }
  1611. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1612. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1613. return;
  1614. }
  1615. /**
  1616. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1617. * @vdev: DP vdev handle
  1618. * @nbuf: skb
  1619. *
  1620. * Software based TID classification is required when more than 2 DSCP-TID
  1621. * mapping tables are needed.
  1622. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1623. *
  1624. * Return: void
  1625. */
  1626. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1627. struct dp_tx_msdu_info_s *msdu_info)
  1628. {
  1629. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1630. /*
  1631. * skip_sw_tid_classification flag will set in below cases-
  1632. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1633. * 2. hlos_tid_override enabled for vdev
  1634. * 3. mesh mode enabled for vdev
  1635. */
  1636. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1637. /* Update tid in msdu_info from skb priority */
  1638. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1639. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1640. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1641. if (tid == DP_TX_INVALID_QOS_TAG)
  1642. return;
  1643. msdu_info->tid = tid;
  1644. return;
  1645. }
  1646. return;
  1647. }
  1648. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1649. }
  1650. #ifdef FEATURE_WLAN_TDLS
  1651. /**
  1652. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1653. * @soc: datapath SOC
  1654. * @vdev: datapath vdev
  1655. * @tx_desc: TX descriptor
  1656. *
  1657. * Return: None
  1658. */
  1659. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1660. struct dp_vdev *vdev,
  1661. struct dp_tx_desc_s *tx_desc)
  1662. {
  1663. if (vdev) {
  1664. if (vdev->is_tdls_frame) {
  1665. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1666. vdev->is_tdls_frame = false;
  1667. }
  1668. }
  1669. }
  1670. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1671. {
  1672. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1673. switch (soc->arch_id) {
  1674. case CDP_ARCH_TYPE_LI:
  1675. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1676. break;
  1677. case CDP_ARCH_TYPE_BE:
  1678. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1679. break;
  1680. default:
  1681. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1682. QDF_BUG(0);
  1683. }
  1684. return tx_status;
  1685. }
  1686. /**
  1687. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1688. * @soc: dp_soc handle
  1689. * @tx_desc: TX descriptor
  1690. * @vdev: datapath vdev handle
  1691. *
  1692. * Return: None
  1693. */
  1694. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1695. struct dp_tx_desc_s *tx_desc)
  1696. {
  1697. uint8_t tx_status = 0;
  1698. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1699. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1700. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1701. DP_MOD_ID_TDLS);
  1702. if (qdf_unlikely(!vdev)) {
  1703. dp_err_rl("vdev is null!");
  1704. goto error;
  1705. }
  1706. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1707. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1708. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1709. if (vdev->tx_non_std_data_callback.func) {
  1710. qdf_nbuf_set_next(nbuf, NULL);
  1711. vdev->tx_non_std_data_callback.func(
  1712. vdev->tx_non_std_data_callback.ctxt,
  1713. nbuf, tx_status);
  1714. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1715. return;
  1716. } else {
  1717. dp_err_rl("callback func is null");
  1718. }
  1719. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1720. error:
  1721. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1722. qdf_nbuf_free(nbuf);
  1723. }
  1724. /**
  1725. * dp_tx_msdu_single_map() - do nbuf map
  1726. * @vdev: DP vdev handle
  1727. * @tx_desc: DP TX descriptor pointer
  1728. * @nbuf: skb pointer
  1729. *
  1730. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1731. * operation done in other component.
  1732. *
  1733. * Return: QDF_STATUS
  1734. */
  1735. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1736. struct dp_tx_desc_s *tx_desc,
  1737. qdf_nbuf_t nbuf)
  1738. {
  1739. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1740. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1741. nbuf,
  1742. QDF_DMA_TO_DEVICE,
  1743. nbuf->len);
  1744. else
  1745. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1746. QDF_DMA_TO_DEVICE);
  1747. }
  1748. #else
  1749. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1750. struct dp_vdev *vdev,
  1751. struct dp_tx_desc_s *tx_desc)
  1752. {
  1753. }
  1754. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1755. struct dp_tx_desc_s *tx_desc)
  1756. {
  1757. }
  1758. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1759. struct dp_tx_desc_s *tx_desc,
  1760. qdf_nbuf_t nbuf)
  1761. {
  1762. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1763. nbuf,
  1764. QDF_DMA_TO_DEVICE,
  1765. nbuf->len);
  1766. }
  1767. #endif
  1768. static inline
  1769. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1770. struct dp_tx_desc_s *tx_desc,
  1771. qdf_nbuf_t nbuf)
  1772. {
  1773. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1774. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1775. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1776. return 0;
  1777. return qdf_nbuf_mapped_paddr_get(nbuf);
  1778. }
  1779. static inline
  1780. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1781. {
  1782. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1783. desc->nbuf,
  1784. desc->dma_addr,
  1785. QDF_DMA_TO_DEVICE,
  1786. desc->length);
  1787. }
  1788. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1789. static inline bool
  1790. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1791. {
  1792. struct net_device *ingress_dev;
  1793. skb_frag_t *frag;
  1794. uint16_t buf_len = 0;
  1795. uint16_t linear_data_len = 0;
  1796. uint8_t *payload_addr = NULL;
  1797. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1798. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1799. dev_put(ingress_dev);
  1800. frag = &(skb_shinfo(nbuf)->frags[0]);
  1801. buf_len = skb_frag_size(frag);
  1802. payload_addr = (uint8_t *)skb_frag_address(frag);
  1803. linear_data_len = skb_headlen(nbuf);
  1804. buf_len += linear_data_len;
  1805. payload_addr = payload_addr - linear_data_len;
  1806. memcpy(payload_addr, nbuf->data, linear_data_len);
  1807. msdu_info->frm_type = dp_tx_frm_rmnet;
  1808. msdu_info->buf_len = buf_len;
  1809. msdu_info->payload_addr = payload_addr;
  1810. return true;
  1811. }
  1812. dev_put(ingress_dev);
  1813. return false;
  1814. }
  1815. static inline
  1816. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1817. struct dp_tx_desc_s *tx_desc)
  1818. {
  1819. qdf_dma_addr_t paddr;
  1820. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1821. tx_desc->length = msdu_info->buf_len;
  1822. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1823. (void *)(msdu_info->payload_addr +
  1824. msdu_info->buf_len));
  1825. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1826. return paddr;
  1827. }
  1828. #else
  1829. static inline bool
  1830. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1831. {
  1832. return false;
  1833. }
  1834. static inline
  1835. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1836. struct dp_tx_desc_s *tx_desc)
  1837. {
  1838. return 0;
  1839. }
  1840. #endif
  1841. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1842. static inline
  1843. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1844. struct dp_tx_desc_s *tx_desc,
  1845. qdf_nbuf_t nbuf)
  1846. {
  1847. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1848. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1849. (void *)(nbuf->data + nbuf->len));
  1850. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1851. } else {
  1852. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1853. }
  1854. }
  1855. static inline
  1856. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1857. struct dp_tx_desc_s *desc)
  1858. {
  1859. if (qdf_unlikely(!(desc->flags &
  1860. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1861. return dp_tx_nbuf_unmap_regular(soc, desc);
  1862. }
  1863. #else
  1864. static inline
  1865. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1866. struct dp_tx_desc_s *tx_desc,
  1867. qdf_nbuf_t nbuf)
  1868. {
  1869. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1870. }
  1871. static inline
  1872. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1873. struct dp_tx_desc_s *desc)
  1874. {
  1875. return dp_tx_nbuf_unmap_regular(soc, desc);
  1876. }
  1877. #endif
  1878. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1879. static inline
  1880. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1881. {
  1882. dp_tx_nbuf_unmap(soc, desc);
  1883. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1884. }
  1885. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1886. {
  1887. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1888. dp_tx_nbuf_unmap(soc, desc);
  1889. }
  1890. #else
  1891. static inline
  1892. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1893. {
  1894. }
  1895. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1896. {
  1897. dp_tx_nbuf_unmap(soc, desc);
  1898. }
  1899. #endif
  1900. #ifdef MESH_MODE_SUPPORT
  1901. /**
  1902. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1903. * @soc: datapath SOC
  1904. * @vdev: datapath vdev
  1905. * @tx_desc: TX descriptor
  1906. *
  1907. * Return: None
  1908. */
  1909. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1910. struct dp_vdev *vdev,
  1911. struct dp_tx_desc_s *tx_desc)
  1912. {
  1913. if (qdf_unlikely(vdev->mesh_vdev))
  1914. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1915. }
  1916. /**
  1917. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1918. * @soc: dp_soc handle
  1919. * @tx_desc: TX descriptor
  1920. * @delayed_free: delay the nbuf free
  1921. *
  1922. * Return: nbuf to be freed late
  1923. */
  1924. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1925. struct dp_tx_desc_s *tx_desc,
  1926. bool delayed_free)
  1927. {
  1928. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1929. struct dp_vdev *vdev = NULL;
  1930. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1931. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1932. if (vdev)
  1933. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1934. if (delayed_free)
  1935. return nbuf;
  1936. qdf_nbuf_free(nbuf);
  1937. } else {
  1938. if (vdev && vdev->osif_tx_free_ext) {
  1939. vdev->osif_tx_free_ext((nbuf));
  1940. } else {
  1941. if (delayed_free)
  1942. return nbuf;
  1943. qdf_nbuf_free(nbuf);
  1944. }
  1945. }
  1946. if (vdev)
  1947. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1948. return NULL;
  1949. }
  1950. #else
  1951. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1952. struct dp_vdev *vdev,
  1953. struct dp_tx_desc_s *tx_desc)
  1954. {
  1955. }
  1956. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1957. struct dp_tx_desc_s *tx_desc,
  1958. bool delayed_free)
  1959. {
  1960. return NULL;
  1961. }
  1962. #endif
  1963. /**
  1964. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1965. * @vdev: DP vdev handle
  1966. * @nbuf: skb
  1967. *
  1968. * Return: 1 if frame needs to be dropped else 0
  1969. */
  1970. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1971. {
  1972. struct dp_pdev *pdev = NULL;
  1973. struct dp_ast_entry *src_ast_entry = NULL;
  1974. struct dp_ast_entry *dst_ast_entry = NULL;
  1975. struct dp_soc *soc = NULL;
  1976. qdf_assert(vdev);
  1977. pdev = vdev->pdev;
  1978. qdf_assert(pdev);
  1979. soc = pdev->soc;
  1980. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1981. (soc, dstmac, vdev->pdev->pdev_id);
  1982. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1983. (soc, srcmac, vdev->pdev->pdev_id);
  1984. if (dst_ast_entry && src_ast_entry) {
  1985. if (dst_ast_entry->peer_id ==
  1986. src_ast_entry->peer_id)
  1987. return 1;
  1988. }
  1989. return 0;
  1990. }
  1991. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1992. defined(WLAN_MCAST_MLO)
  1993. /* MLO peer id for reinject*/
  1994. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1995. /* MLO vdev id inc offset */
  1996. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1997. static inline void
  1998. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1999. {
  2000. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  2001. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2002. qdf_atomic_inc(&soc->num_tx_exception);
  2003. }
  2004. }
  2005. static inline void
  2006. dp_tx_update_mcast_param(uint16_t peer_id,
  2007. uint16_t *htt_tcl_metadata,
  2008. struct dp_vdev *vdev,
  2009. struct dp_tx_msdu_info_s *msdu_info)
  2010. {
  2011. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  2012. *htt_tcl_metadata = 0;
  2013. DP_TX_TCL_METADATA_TYPE_SET(
  2014. *htt_tcl_metadata,
  2015. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2016. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2017. msdu_info->gsn);
  2018. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2019. if (qdf_unlikely(vdev->nawds_enabled ||
  2020. dp_vdev_is_wds_ext_enabled(vdev)))
  2021. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2022. *htt_tcl_metadata, 1);
  2023. } else {
  2024. msdu_info->vdev_id = vdev->vdev_id;
  2025. }
  2026. }
  2027. #else
  2028. static inline void
  2029. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2030. {
  2031. }
  2032. static inline void
  2033. dp_tx_update_mcast_param(uint16_t peer_id,
  2034. uint16_t *htt_tcl_metadata,
  2035. struct dp_vdev *vdev,
  2036. struct dp_tx_msdu_info_s *msdu_info)
  2037. {
  2038. }
  2039. #endif
  2040. #ifdef DP_TX_SW_DROP_STATS_INC
  2041. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2042. qdf_nbuf_t nbuf,
  2043. enum cdp_tx_sw_drop drop_code)
  2044. {
  2045. /* EAPOL Drop stats */
  2046. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2047. switch (drop_code) {
  2048. case TX_DESC_ERR:
  2049. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2050. break;
  2051. case TX_HAL_RING_ACCESS_ERR:
  2052. DP_STATS_INC(pdev,
  2053. eap_drop_stats.tx_hal_ring_access_err, 1);
  2054. break;
  2055. case TX_DMA_MAP_ERR:
  2056. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2057. break;
  2058. case TX_HW_ENQUEUE:
  2059. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2060. break;
  2061. case TX_SW_ENQUEUE:
  2062. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2063. break;
  2064. default:
  2065. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2066. break;
  2067. }
  2068. }
  2069. }
  2070. #else
  2071. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2072. qdf_nbuf_t nbuf,
  2073. enum cdp_tx_sw_drop drop_code)
  2074. {
  2075. }
  2076. #endif
  2077. /**
  2078. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2079. * @vdev: DP vdev handle
  2080. * @nbuf: skb
  2081. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2082. * @meta_data: Metadata to the fw
  2083. * @tx_q: Tx queue to be used for this Tx frame
  2084. * @peer_id: peer_id of the peer in case of NAWDS frames
  2085. * @tx_exc_metadata: Handle that holds exception path metadata
  2086. *
  2087. * Return: NULL on success,
  2088. * nbuf when it fails to send
  2089. */
  2090. qdf_nbuf_t
  2091. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2092. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2093. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2094. {
  2095. struct dp_pdev *pdev = vdev->pdev;
  2096. struct dp_soc *soc = pdev->soc;
  2097. struct dp_tx_desc_s *tx_desc;
  2098. QDF_STATUS status;
  2099. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2100. uint16_t htt_tcl_metadata = 0;
  2101. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2102. uint8_t tid = msdu_info->tid;
  2103. struct cdp_tid_tx_stats *tid_stats = NULL;
  2104. qdf_dma_addr_t paddr;
  2105. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2106. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2107. msdu_info, tx_exc_metadata);
  2108. if (!tx_desc) {
  2109. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2110. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2111. drop_code = TX_DESC_ERR;
  2112. goto fail_return;
  2113. }
  2114. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2115. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2116. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2117. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2118. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2119. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2120. DP_TCL_METADATA_TYPE_PEER_BASED);
  2121. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2122. peer_id);
  2123. dp_tx_bypass_reinjection(soc, tx_desc);
  2124. } else
  2125. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2126. if (msdu_info->exception_fw)
  2127. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2128. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2129. !pdev->enhanced_stats_en);
  2130. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2131. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2132. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2133. else
  2134. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2135. if (!paddr) {
  2136. /* Handle failure */
  2137. dp_err("qdf_nbuf_map failed");
  2138. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2139. drop_code = TX_DMA_MAP_ERR;
  2140. goto release_desc;
  2141. }
  2142. tx_desc->dma_addr = paddr;
  2143. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2144. tx_desc->id, DP_TX_DESC_MAP);
  2145. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2146. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2147. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2148. htt_tcl_metadata,
  2149. tx_exc_metadata, msdu_info);
  2150. if (status != QDF_STATUS_SUCCESS) {
  2151. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2152. tx_desc, tx_q->ring_id);
  2153. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2154. tx_desc->id, DP_TX_DESC_UNMAP);
  2155. dp_tx_nbuf_unmap(soc, tx_desc);
  2156. drop_code = TX_HW_ENQUEUE;
  2157. goto release_desc;
  2158. }
  2159. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2160. return NULL;
  2161. release_desc:
  2162. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2163. fail_return:
  2164. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2165. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2166. tid_stats = &pdev->stats.tid_stats.
  2167. tid_tx_stats[tx_q->ring_id][tid];
  2168. tid_stats->swdrop_cnt[drop_code]++;
  2169. return nbuf;
  2170. }
  2171. /**
  2172. * dp_tdls_tx_comp_free_buff() - Free non std buffer when TDLS flag is set
  2173. * @soc: Soc handle
  2174. * @desc: software Tx descriptor to be processed
  2175. *
  2176. * Return: 0 if Success
  2177. */
  2178. #ifdef FEATURE_WLAN_TDLS
  2179. static inline int
  2180. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2181. {
  2182. /* If it is TDLS mgmt, don't unmap or free the frame */
  2183. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2184. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2185. return 0;
  2186. }
  2187. return 1;
  2188. }
  2189. #else
  2190. static inline int
  2191. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2192. {
  2193. return 1;
  2194. }
  2195. #endif
  2196. /**
  2197. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2198. * @soc: Soc handle
  2199. * @desc: software Tx descriptor to be processed
  2200. * @delayed_free: defer freeing of nbuf
  2201. *
  2202. * Return: nbuf to be freed later
  2203. */
  2204. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2205. bool delayed_free)
  2206. {
  2207. qdf_nbuf_t nbuf = desc->nbuf;
  2208. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2209. /* nbuf already freed in vdev detach path */
  2210. if (!nbuf)
  2211. return NULL;
  2212. if (!dp_tdls_tx_comp_free_buff(soc, desc))
  2213. return NULL;
  2214. /* 0 : MSDU buffer, 1 : MLE */
  2215. if (desc->msdu_ext_desc) {
  2216. /* TSO free */
  2217. if (hal_tx_ext_desc_get_tso_enable(
  2218. desc->msdu_ext_desc->vaddr)) {
  2219. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2220. desc->id, DP_TX_COMP_MSDU_EXT);
  2221. dp_tx_tso_seg_history_add(soc,
  2222. desc->msdu_ext_desc->tso_desc,
  2223. desc->nbuf, desc->id, type);
  2224. /* unmap eash TSO seg before free the nbuf */
  2225. dp_tx_tso_unmap_segment(soc,
  2226. desc->msdu_ext_desc->tso_desc,
  2227. desc->msdu_ext_desc->
  2228. tso_num_desc);
  2229. goto nbuf_free;
  2230. }
  2231. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2232. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2233. qdf_dma_addr_t iova;
  2234. uint32_t frag_len;
  2235. uint32_t i;
  2236. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2237. QDF_DMA_TO_DEVICE,
  2238. qdf_nbuf_headlen(nbuf));
  2239. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2240. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2241. &iova,
  2242. &frag_len);
  2243. if (!iova || !frag_len)
  2244. break;
  2245. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2246. QDF_DMA_TO_DEVICE);
  2247. }
  2248. goto nbuf_free;
  2249. }
  2250. }
  2251. /* If it's ME frame, dont unmap the cloned nbuf's */
  2252. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2253. goto nbuf_free;
  2254. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2255. dp_tx_unmap(soc, desc);
  2256. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2257. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2258. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2259. return NULL;
  2260. nbuf_free:
  2261. if (delayed_free)
  2262. return nbuf;
  2263. qdf_nbuf_free(nbuf);
  2264. return NULL;
  2265. }
  2266. /**
  2267. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2268. * @soc: DP soc handle
  2269. * @nbuf: skb
  2270. * @msdu_info: MSDU info
  2271. *
  2272. * Return: None
  2273. */
  2274. static inline void
  2275. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2276. struct dp_tx_msdu_info_s *msdu_info)
  2277. {
  2278. uint32_t cur_idx;
  2279. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2280. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2281. qdf_nbuf_headlen(nbuf));
  2282. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2283. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2284. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2285. seg->frags[cur_idx].paddr_hi) << 32),
  2286. seg->frags[cur_idx].len,
  2287. QDF_DMA_TO_DEVICE);
  2288. }
  2289. /**
  2290. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2291. * @vdev: DP vdev handle
  2292. * @nbuf: skb
  2293. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2294. *
  2295. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2296. *
  2297. * Return: NULL on success,
  2298. * nbuf when it fails to send
  2299. */
  2300. #if QDF_LOCK_STATS
  2301. noinline
  2302. #else
  2303. #endif
  2304. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2305. struct dp_tx_msdu_info_s *msdu_info)
  2306. {
  2307. uint32_t i;
  2308. struct dp_pdev *pdev = vdev->pdev;
  2309. struct dp_soc *soc = pdev->soc;
  2310. struct dp_tx_desc_s *tx_desc;
  2311. bool is_cce_classified = false;
  2312. QDF_STATUS status;
  2313. uint16_t htt_tcl_metadata = 0;
  2314. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2315. struct cdp_tid_tx_stats *tid_stats = NULL;
  2316. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2317. if (msdu_info->frm_type == dp_tx_frm_me)
  2318. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2319. i = 0;
  2320. /* Print statement to track i and num_seg */
  2321. /*
  2322. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2323. * descriptors using information in msdu_info
  2324. */
  2325. while (i < msdu_info->num_seg) {
  2326. /*
  2327. * Setup Tx descriptor for an MSDU, and MSDU extension
  2328. * descriptor
  2329. */
  2330. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2331. tx_q->desc_pool_id);
  2332. if (!tx_desc) {
  2333. if (msdu_info->frm_type == dp_tx_frm_me) {
  2334. prep_desc_fail++;
  2335. dp_tx_me_free_buf(pdev,
  2336. (void *)(msdu_info->u.sg_info
  2337. .curr_seg->frags[0].vaddr));
  2338. if (prep_desc_fail == msdu_info->num_seg) {
  2339. /*
  2340. * Unmap is needed only if descriptor
  2341. * preparation failed for all segments.
  2342. */
  2343. qdf_nbuf_unmap(soc->osdev,
  2344. msdu_info->u.sg_info.
  2345. curr_seg->nbuf,
  2346. QDF_DMA_TO_DEVICE);
  2347. }
  2348. /*
  2349. * Free the nbuf for the current segment
  2350. * and make it point to the next in the list.
  2351. * For me, there are as many segments as there
  2352. * are no of clients.
  2353. */
  2354. qdf_nbuf_free(msdu_info->u.sg_info
  2355. .curr_seg->nbuf);
  2356. if (msdu_info->u.sg_info.curr_seg->next) {
  2357. msdu_info->u.sg_info.curr_seg =
  2358. msdu_info->u.sg_info
  2359. .curr_seg->next;
  2360. nbuf = msdu_info->u.sg_info
  2361. .curr_seg->nbuf;
  2362. }
  2363. i++;
  2364. continue;
  2365. }
  2366. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2367. dp_tx_tso_seg_history_add(
  2368. soc,
  2369. msdu_info->u.tso_info.curr_seg,
  2370. nbuf, 0, DP_TX_DESC_UNMAP);
  2371. dp_tx_tso_unmap_segment(soc,
  2372. msdu_info->u.tso_info.
  2373. curr_seg,
  2374. msdu_info->u.tso_info.
  2375. tso_num_seg_list);
  2376. if (msdu_info->u.tso_info.curr_seg->next) {
  2377. msdu_info->u.tso_info.curr_seg =
  2378. msdu_info->u.tso_info.curr_seg->next;
  2379. i++;
  2380. continue;
  2381. }
  2382. }
  2383. if (msdu_info->frm_type == dp_tx_frm_sg)
  2384. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2385. goto done;
  2386. }
  2387. if (msdu_info->frm_type == dp_tx_frm_me) {
  2388. tx_desc->msdu_ext_desc->me_buffer =
  2389. (struct dp_tx_me_buf_t *)msdu_info->
  2390. u.sg_info.curr_seg->frags[0].vaddr;
  2391. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2392. }
  2393. if (is_cce_classified)
  2394. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2395. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2396. if (msdu_info->exception_fw) {
  2397. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2398. }
  2399. dp_tx_is_hp_update_required(i, msdu_info);
  2400. /*
  2401. * For frames with multiple segments (TSO, ME), jump to next
  2402. * segment.
  2403. */
  2404. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2405. if (msdu_info->u.tso_info.curr_seg->next) {
  2406. msdu_info->u.tso_info.curr_seg =
  2407. msdu_info->u.tso_info.curr_seg->next;
  2408. /*
  2409. * If this is a jumbo nbuf, then increment the
  2410. * number of nbuf users for each additional
  2411. * segment of the msdu. This will ensure that
  2412. * the skb is freed only after receiving tx
  2413. * completion for all segments of an nbuf
  2414. */
  2415. qdf_nbuf_inc_users(nbuf);
  2416. /* Check with MCL if this is needed */
  2417. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2418. */
  2419. }
  2420. }
  2421. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2422. &htt_tcl_metadata,
  2423. vdev,
  2424. msdu_info);
  2425. /*
  2426. * Enqueue the Tx MSDU descriptor to HW for transmit
  2427. */
  2428. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2429. htt_tcl_metadata,
  2430. NULL, msdu_info);
  2431. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2432. if (status != QDF_STATUS_SUCCESS) {
  2433. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2434. tx_desc, tx_q->ring_id);
  2435. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2436. tid_stats = &pdev->stats.tid_stats.
  2437. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2438. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2439. if (msdu_info->frm_type == dp_tx_frm_me) {
  2440. hw_enq_fail++;
  2441. if (hw_enq_fail == msdu_info->num_seg) {
  2442. /*
  2443. * Unmap is needed only if enqueue
  2444. * failed for all segments.
  2445. */
  2446. qdf_nbuf_unmap(soc->osdev,
  2447. msdu_info->u.sg_info.
  2448. curr_seg->nbuf,
  2449. QDF_DMA_TO_DEVICE);
  2450. }
  2451. /*
  2452. * Free the nbuf for the current segment
  2453. * and make it point to the next in the list.
  2454. * For me, there are as many segments as there
  2455. * are no of clients.
  2456. */
  2457. qdf_nbuf_free(msdu_info->u.sg_info
  2458. .curr_seg->nbuf);
  2459. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2460. if (msdu_info->u.sg_info.curr_seg->next) {
  2461. msdu_info->u.sg_info.curr_seg =
  2462. msdu_info->u.sg_info
  2463. .curr_seg->next;
  2464. nbuf = msdu_info->u.sg_info
  2465. .curr_seg->nbuf;
  2466. } else
  2467. break;
  2468. i++;
  2469. continue;
  2470. }
  2471. /*
  2472. * For TSO frames, the nbuf users increment done for
  2473. * the current segment has to be reverted, since the
  2474. * hw enqueue for this segment failed
  2475. */
  2476. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2477. msdu_info->u.tso_info.curr_seg) {
  2478. /*
  2479. * unmap and free current,
  2480. * retransmit remaining segments
  2481. */
  2482. dp_tx_comp_free_buf(soc, tx_desc, false);
  2483. i++;
  2484. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2485. continue;
  2486. }
  2487. if (msdu_info->frm_type == dp_tx_frm_sg)
  2488. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2489. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2490. goto done;
  2491. }
  2492. /*
  2493. * TODO
  2494. * if tso_info structure can be modified to have curr_seg
  2495. * as first element, following 2 blocks of code (for TSO and SG)
  2496. * can be combined into 1
  2497. */
  2498. /*
  2499. * For Multicast-Unicast converted packets,
  2500. * each converted frame (for a client) is represented as
  2501. * 1 segment
  2502. */
  2503. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2504. (msdu_info->frm_type == dp_tx_frm_me)) {
  2505. if (msdu_info->u.sg_info.curr_seg->next) {
  2506. msdu_info->u.sg_info.curr_seg =
  2507. msdu_info->u.sg_info.curr_seg->next;
  2508. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2509. } else
  2510. break;
  2511. }
  2512. i++;
  2513. }
  2514. nbuf = NULL;
  2515. done:
  2516. return nbuf;
  2517. }
  2518. /**
  2519. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2520. * for SG frames
  2521. * @vdev: DP vdev handle
  2522. * @nbuf: skb
  2523. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2524. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2525. *
  2526. * Return: NULL on success,
  2527. * nbuf when it fails to send
  2528. */
  2529. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2530. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2531. {
  2532. uint32_t cur_frag, nr_frags, i;
  2533. qdf_dma_addr_t paddr;
  2534. struct dp_tx_sg_info_s *sg_info;
  2535. sg_info = &msdu_info->u.sg_info;
  2536. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2537. if (QDF_STATUS_SUCCESS !=
  2538. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2539. QDF_DMA_TO_DEVICE,
  2540. qdf_nbuf_headlen(nbuf))) {
  2541. dp_tx_err("dma map error");
  2542. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2543. qdf_nbuf_free(nbuf);
  2544. return NULL;
  2545. }
  2546. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2547. seg_info->frags[0].paddr_lo = paddr;
  2548. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2549. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2550. seg_info->frags[0].vaddr = (void *) nbuf;
  2551. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2552. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2553. nbuf, 0,
  2554. QDF_DMA_TO_DEVICE,
  2555. cur_frag)) {
  2556. dp_tx_err("frag dma map error");
  2557. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2558. goto map_err;
  2559. }
  2560. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2561. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2562. seg_info->frags[cur_frag + 1].paddr_hi =
  2563. ((uint64_t) paddr) >> 32;
  2564. seg_info->frags[cur_frag + 1].len =
  2565. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2566. }
  2567. seg_info->frag_cnt = (cur_frag + 1);
  2568. seg_info->total_len = qdf_nbuf_len(nbuf);
  2569. seg_info->next = NULL;
  2570. sg_info->curr_seg = seg_info;
  2571. msdu_info->frm_type = dp_tx_frm_sg;
  2572. msdu_info->num_seg = 1;
  2573. return nbuf;
  2574. map_err:
  2575. /* restore paddr into nbuf before calling unmap */
  2576. qdf_nbuf_mapped_paddr_set(nbuf,
  2577. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2578. ((uint64_t)
  2579. seg_info->frags[0].paddr_hi) << 32));
  2580. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2581. QDF_DMA_TO_DEVICE,
  2582. seg_info->frags[0].len);
  2583. for (i = 1; i <= cur_frag; i++) {
  2584. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2585. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2586. seg_info->frags[i].paddr_hi) << 32),
  2587. seg_info->frags[i].len,
  2588. QDF_DMA_TO_DEVICE);
  2589. }
  2590. qdf_nbuf_free(nbuf);
  2591. return NULL;
  2592. }
  2593. /**
  2594. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2595. * @vdev: DP vdev handle
  2596. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2597. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2598. *
  2599. * Return: NULL on failure,
  2600. * nbuf when extracted successfully
  2601. */
  2602. static
  2603. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2604. struct dp_tx_msdu_info_s *msdu_info,
  2605. uint16_t ppdu_cookie)
  2606. {
  2607. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2608. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2609. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2610. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2611. (msdu_info->meta_data[5], 1);
  2612. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2613. (msdu_info->meta_data[5], 1);
  2614. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2615. (msdu_info->meta_data[6], ppdu_cookie);
  2616. msdu_info->exception_fw = 1;
  2617. msdu_info->is_tx_sniffer = 1;
  2618. }
  2619. #ifdef MESH_MODE_SUPPORT
  2620. /**
  2621. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2622. and prepare msdu_info for mesh frames.
  2623. * @vdev: DP vdev handle
  2624. * @nbuf: skb
  2625. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2626. *
  2627. * Return: NULL on failure,
  2628. * nbuf when extracted successfully
  2629. */
  2630. static
  2631. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2632. struct dp_tx_msdu_info_s *msdu_info)
  2633. {
  2634. struct meta_hdr_s *mhdr;
  2635. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2636. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2637. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2638. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2639. msdu_info->exception_fw = 0;
  2640. goto remove_meta_hdr;
  2641. }
  2642. msdu_info->exception_fw = 1;
  2643. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2644. meta_data->host_tx_desc_pool = 1;
  2645. meta_data->update_peer_cache = 1;
  2646. meta_data->learning_frame = 1;
  2647. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2648. meta_data->power = mhdr->power;
  2649. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2650. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2651. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2652. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2653. meta_data->dyn_bw = 1;
  2654. meta_data->valid_pwr = 1;
  2655. meta_data->valid_mcs_mask = 1;
  2656. meta_data->valid_nss_mask = 1;
  2657. meta_data->valid_preamble_type = 1;
  2658. meta_data->valid_retries = 1;
  2659. meta_data->valid_bw_info = 1;
  2660. }
  2661. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2662. meta_data->encrypt_type = 0;
  2663. meta_data->valid_encrypt_type = 1;
  2664. meta_data->learning_frame = 0;
  2665. }
  2666. meta_data->valid_key_flags = 1;
  2667. meta_data->key_flags = (mhdr->keyix & 0x3);
  2668. remove_meta_hdr:
  2669. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2670. dp_tx_err("qdf_nbuf_pull_head failed");
  2671. qdf_nbuf_free(nbuf);
  2672. return NULL;
  2673. }
  2674. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2675. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2676. " tid %d to_fw %d",
  2677. msdu_info->meta_data[0],
  2678. msdu_info->meta_data[1],
  2679. msdu_info->meta_data[2],
  2680. msdu_info->meta_data[3],
  2681. msdu_info->meta_data[4],
  2682. msdu_info->meta_data[5],
  2683. msdu_info->tid, msdu_info->exception_fw);
  2684. return nbuf;
  2685. }
  2686. #else
  2687. static
  2688. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2689. struct dp_tx_msdu_info_s *msdu_info)
  2690. {
  2691. return nbuf;
  2692. }
  2693. #endif
  2694. /**
  2695. * dp_check_exc_metadata() - Checks if parameters are valid
  2696. * @tx_exc - holds all exception path parameters
  2697. *
  2698. * Returns true when all the parameters are valid else false
  2699. *
  2700. */
  2701. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2702. {
  2703. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2704. HTT_INVALID_TID);
  2705. bool invalid_encap_type =
  2706. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2707. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2708. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2709. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2710. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2711. tx_exc->ppdu_cookie == 0);
  2712. if (tx_exc->is_intrabss_fwd)
  2713. return true;
  2714. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2715. invalid_cookie) {
  2716. return false;
  2717. }
  2718. return true;
  2719. }
  2720. #ifdef ATH_SUPPORT_IQUE
  2721. /**
  2722. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2723. * @vdev: vdev handle
  2724. * @nbuf: skb
  2725. *
  2726. * Return: true on success,
  2727. * false on failure
  2728. */
  2729. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2730. {
  2731. qdf_ether_header_t *eh;
  2732. /* Mcast to Ucast Conversion*/
  2733. if (qdf_likely(!vdev->mcast_enhancement_en))
  2734. return true;
  2735. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2736. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2737. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2738. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2739. qdf_nbuf_set_next(nbuf, NULL);
  2740. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2741. qdf_nbuf_len(nbuf));
  2742. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2743. QDF_STATUS_SUCCESS) {
  2744. return false;
  2745. }
  2746. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2747. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2748. QDF_STATUS_SUCCESS) {
  2749. return false;
  2750. }
  2751. }
  2752. }
  2753. return true;
  2754. }
  2755. #else
  2756. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2757. {
  2758. return true;
  2759. }
  2760. #endif
  2761. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2762. /**
  2763. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2764. * @vdev: vdev handle
  2765. * @nbuf: skb
  2766. *
  2767. * Return: true if frame is dropped, false otherwise
  2768. */
  2769. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2770. {
  2771. /* Drop tx mcast and WDS Extended feature check */
  2772. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2773. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2774. qdf_nbuf_data(nbuf);
  2775. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2776. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2777. return true;
  2778. }
  2779. }
  2780. return false;
  2781. }
  2782. #else
  2783. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2784. {
  2785. return false;
  2786. }
  2787. #endif
  2788. /**
  2789. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2790. * @nbuf: qdf_nbuf_t
  2791. * @vdev: struct dp_vdev *
  2792. *
  2793. * Allow packet for processing only if it is for peer client which is
  2794. * connected with same vap. Drop packet if client is connected to
  2795. * different vap.
  2796. *
  2797. * Return: QDF_STATUS
  2798. */
  2799. static inline QDF_STATUS
  2800. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2801. {
  2802. struct dp_ast_entry *dst_ast_entry = NULL;
  2803. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2804. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2805. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2806. return QDF_STATUS_SUCCESS;
  2807. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2808. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2809. eh->ether_dhost,
  2810. vdev->vdev_id);
  2811. /* If there is no ast entry, return failure */
  2812. if (qdf_unlikely(!dst_ast_entry)) {
  2813. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2814. return QDF_STATUS_E_FAILURE;
  2815. }
  2816. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2817. return QDF_STATUS_SUCCESS;
  2818. }
  2819. /**
  2820. * dp_tx_nawds_handler() - NAWDS handler
  2821. *
  2822. * @soc: DP soc handle
  2823. * @vdev_id: id of DP vdev handle
  2824. * @msdu_info: msdu_info required to create HTT metadata
  2825. * @nbuf: skb
  2826. *
  2827. * This API transfers the multicast frames with the peer id
  2828. * on NAWDS enabled peer.
  2829. * Return: none
  2830. */
  2831. static inline
  2832. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2833. struct dp_tx_msdu_info_s *msdu_info,
  2834. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2835. {
  2836. struct dp_peer *peer = NULL;
  2837. qdf_nbuf_t nbuf_clone = NULL;
  2838. uint16_t peer_id = DP_INVALID_PEER;
  2839. struct dp_txrx_peer *txrx_peer;
  2840. /* This check avoids pkt forwarding which is entered
  2841. * in the ast table but still doesn't have valid peerid.
  2842. */
  2843. if (sa_peer_id == HTT_INVALID_PEER)
  2844. return;
  2845. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2846. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2847. txrx_peer = dp_get_txrx_peer(peer);
  2848. if (!txrx_peer)
  2849. continue;
  2850. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2851. peer_id = peer->peer_id;
  2852. if (!dp_peer_is_primary_link_peer(peer))
  2853. continue;
  2854. /* Multicast packets needs to be
  2855. * dropped in case of intra bss forwarding
  2856. */
  2857. if (sa_peer_id == txrx_peer->peer_id) {
  2858. dp_tx_debug("multicast packet");
  2859. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2860. tx.nawds_mcast_drop,
  2861. 1);
  2862. continue;
  2863. }
  2864. nbuf_clone = qdf_nbuf_clone(nbuf);
  2865. if (!nbuf_clone) {
  2866. QDF_TRACE(QDF_MODULE_ID_DP,
  2867. QDF_TRACE_LEVEL_ERROR,
  2868. FL("nbuf clone failed"));
  2869. break;
  2870. }
  2871. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2872. msdu_info, peer_id,
  2873. NULL);
  2874. if (nbuf_clone) {
  2875. dp_tx_debug("pkt send failed");
  2876. qdf_nbuf_free(nbuf_clone);
  2877. } else {
  2878. if (peer_id != DP_INVALID_PEER)
  2879. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2880. tx.nawds_mcast,
  2881. 1, qdf_nbuf_len(nbuf));
  2882. }
  2883. }
  2884. }
  2885. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2886. }
  2887. /**
  2888. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2889. * @soc: DP soc handle
  2890. * @vdev_id: id of DP vdev handle
  2891. * @nbuf: skb
  2892. * @tx_exc_metadata: Handle that holds exception path meta data
  2893. *
  2894. * Entry point for Core Tx layer (DP_TX) invoked from
  2895. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2896. *
  2897. * Return: NULL on success,
  2898. * nbuf when it fails to send
  2899. */
  2900. qdf_nbuf_t
  2901. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2902. qdf_nbuf_t nbuf,
  2903. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2904. {
  2905. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2906. struct dp_tx_msdu_info_s msdu_info;
  2907. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2908. DP_MOD_ID_TX_EXCEPTION);
  2909. if (qdf_unlikely(!vdev))
  2910. goto fail;
  2911. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2912. if (!tx_exc_metadata)
  2913. goto fail;
  2914. msdu_info.tid = tx_exc_metadata->tid;
  2915. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2916. QDF_MAC_ADDR_REF(nbuf->data));
  2917. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2918. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2919. dp_tx_err("Invalid parameters in exception path");
  2920. goto fail;
  2921. }
  2922. /* for peer based metadata check if peer is valid */
  2923. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2924. struct dp_peer *peer = NULL;
  2925. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2926. tx_exc_metadata->peer_id,
  2927. DP_MOD_ID_TX_EXCEPTION);
  2928. if (qdf_unlikely(!peer)) {
  2929. DP_STATS_INC(vdev,
  2930. tx_i.dropped.invalid_peer_id_in_exc_path,
  2931. 1);
  2932. goto fail;
  2933. }
  2934. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2935. }
  2936. /* Basic sanity checks for unsupported packets */
  2937. /* MESH mode */
  2938. if (qdf_unlikely(vdev->mesh_vdev)) {
  2939. dp_tx_err("Mesh mode is not supported in exception path");
  2940. goto fail;
  2941. }
  2942. /*
  2943. * Classify the frame and call corresponding
  2944. * "prepare" function which extracts the segment (TSO)
  2945. * and fragmentation information (for TSO , SG, ME, or Raw)
  2946. * into MSDU_INFO structure which is later used to fill
  2947. * SW and HW descriptors.
  2948. */
  2949. if (qdf_nbuf_is_tso(nbuf)) {
  2950. dp_verbose_debug("TSO frame %pK", vdev);
  2951. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2952. qdf_nbuf_len(nbuf));
  2953. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2954. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2955. qdf_nbuf_len(nbuf));
  2956. goto fail;
  2957. }
  2958. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  2959. goto send_multiple;
  2960. }
  2961. /* SG */
  2962. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2963. struct dp_tx_seg_info_s seg_info = {0};
  2964. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2965. if (!nbuf)
  2966. goto fail;
  2967. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2968. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2969. qdf_nbuf_len(nbuf));
  2970. goto send_multiple;
  2971. }
  2972. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2973. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2974. qdf_nbuf_len(nbuf));
  2975. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2976. tx_exc_metadata->ppdu_cookie);
  2977. }
  2978. /*
  2979. * Get HW Queue to use for this frame.
  2980. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2981. * dedicated for data and 1 for command.
  2982. * "queue_id" maps to one hardware ring.
  2983. * With each ring, we also associate a unique Tx descriptor pool
  2984. * to minimize lock contention for these resources.
  2985. */
  2986. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2987. /*
  2988. * if the packet is mcast packet send through mlo_macst handler
  2989. * for all prnt_vdevs
  2990. */
  2991. if (soc->arch_ops.dp_tx_mlo_mcast_send) {
  2992. nbuf = soc->arch_ops.dp_tx_mlo_mcast_send(soc, vdev,
  2993. nbuf,
  2994. tx_exc_metadata);
  2995. if (!nbuf)
  2996. goto fail;
  2997. }
  2998. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2999. if (qdf_unlikely(vdev->nawds_enabled)) {
  3000. /*
  3001. * This is a multicast packet
  3002. */
  3003. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3004. tx_exc_metadata->peer_id);
  3005. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3006. 1, qdf_nbuf_len(nbuf));
  3007. }
  3008. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  3009. DP_INVALID_PEER, NULL);
  3010. } else {
  3011. /*
  3012. * Check exception descriptors
  3013. */
  3014. if (dp_tx_exception_limit_check(vdev))
  3015. goto fail;
  3016. /* Single linear frame */
  3017. /*
  3018. * If nbuf is a simple linear frame, use send_single function to
  3019. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3020. * SRNG. There is no need to setup a MSDU extension descriptor.
  3021. */
  3022. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  3023. tx_exc_metadata->peer_id,
  3024. tx_exc_metadata);
  3025. }
  3026. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3027. return nbuf;
  3028. send_multiple:
  3029. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3030. fail:
  3031. if (vdev)
  3032. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3033. dp_verbose_debug("pkt send failed");
  3034. return nbuf;
  3035. }
  3036. /**
  3037. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  3038. * in exception path in special case to avoid regular exception path chk.
  3039. * @soc: DP soc handle
  3040. * @vdev_id: id of DP vdev handle
  3041. * @nbuf: skb
  3042. * @tx_exc_metadata: Handle that holds exception path meta data
  3043. *
  3044. * Entry point for Core Tx layer (DP_TX) invoked from
  3045. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  3046. *
  3047. * Return: NULL on success,
  3048. * nbuf when it fails to send
  3049. */
  3050. qdf_nbuf_t
  3051. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3052. uint8_t vdev_id, qdf_nbuf_t nbuf,
  3053. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3054. {
  3055. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3056. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3057. DP_MOD_ID_TX_EXCEPTION);
  3058. if (qdf_unlikely(!vdev))
  3059. goto fail;
  3060. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3061. == QDF_STATUS_E_FAILURE)) {
  3062. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3063. goto fail;
  3064. }
  3065. /* Unref count as it will again be taken inside dp_tx_exception */
  3066. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3067. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  3068. fail:
  3069. if (vdev)
  3070. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3071. dp_verbose_debug("pkt send failed");
  3072. return nbuf;
  3073. }
  3074. /**
  3075. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  3076. * @soc: DP soc handle
  3077. * @vdev_id: DP vdev handle
  3078. * @nbuf: skb
  3079. *
  3080. * Entry point for Core Tx layer (DP_TX) invoked from
  3081. * hard_start_xmit in OSIF/HDD
  3082. *
  3083. * Return: NULL on success,
  3084. * nbuf when it fails to send
  3085. */
  3086. #ifdef MESH_MODE_SUPPORT
  3087. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3088. qdf_nbuf_t nbuf)
  3089. {
  3090. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3091. struct meta_hdr_s *mhdr;
  3092. qdf_nbuf_t nbuf_mesh = NULL;
  3093. qdf_nbuf_t nbuf_clone = NULL;
  3094. struct dp_vdev *vdev;
  3095. uint8_t no_enc_frame = 0;
  3096. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3097. if (!nbuf_mesh) {
  3098. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3099. "qdf_nbuf_unshare failed");
  3100. return nbuf;
  3101. }
  3102. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3103. if (!vdev) {
  3104. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3105. "vdev is NULL for vdev_id %d", vdev_id);
  3106. return nbuf;
  3107. }
  3108. nbuf = nbuf_mesh;
  3109. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3110. if ((vdev->sec_type != cdp_sec_type_none) &&
  3111. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3112. no_enc_frame = 1;
  3113. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3114. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3115. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3116. !no_enc_frame) {
  3117. nbuf_clone = qdf_nbuf_clone(nbuf);
  3118. if (!nbuf_clone) {
  3119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3120. "qdf_nbuf_clone failed");
  3121. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3122. return nbuf;
  3123. }
  3124. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3125. }
  3126. if (nbuf_clone) {
  3127. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3128. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3129. } else {
  3130. qdf_nbuf_free(nbuf_clone);
  3131. }
  3132. }
  3133. if (no_enc_frame)
  3134. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3135. else
  3136. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3137. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3138. if ((!nbuf) && no_enc_frame) {
  3139. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3140. }
  3141. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3142. return nbuf;
  3143. }
  3144. #else
  3145. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3146. qdf_nbuf_t nbuf)
  3147. {
  3148. return dp_tx_send(soc, vdev_id, nbuf);
  3149. }
  3150. #endif
  3151. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3152. static inline
  3153. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3154. {
  3155. if (nbuf) {
  3156. qdf_prefetch(&nbuf->len);
  3157. qdf_prefetch(&nbuf->data);
  3158. }
  3159. }
  3160. #else
  3161. static inline
  3162. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3163. {
  3164. }
  3165. #endif
  3166. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3167. /*
  3168. * dp_tx_drop() - Drop the frame on a given VAP
  3169. * @soc: DP soc handle
  3170. * @vdev_id: id of DP vdev handle
  3171. * @nbuf: skb
  3172. *
  3173. * Drop all the incoming packets
  3174. *
  3175. * Return: nbuf
  3176. *
  3177. */
  3178. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3179. qdf_nbuf_t nbuf)
  3180. {
  3181. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3182. struct dp_vdev *vdev = NULL;
  3183. vdev = soc->vdev_id_map[vdev_id];
  3184. if (qdf_unlikely(!vdev))
  3185. return nbuf;
  3186. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3187. return nbuf;
  3188. }
  3189. /*
  3190. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3191. * @soc: DP soc handle
  3192. * @vdev_id: id of DP vdev handle
  3193. * @nbuf: skb
  3194. * @tx_exc_metadata: Handle that holds exception path meta data
  3195. *
  3196. * Drop all the incoming packets
  3197. *
  3198. * Return: nbuf
  3199. *
  3200. */
  3201. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3202. qdf_nbuf_t nbuf,
  3203. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3204. {
  3205. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3206. }
  3207. #endif
  3208. #ifdef FEATURE_DIRECT_LINK
  3209. /*
  3210. * dp_vdev_tx_mark_to_fw() - Mark to_fw bit for the tx packet
  3211. * @nbuf: skb
  3212. * @vdev: DP vdev handle
  3213. *
  3214. * Return: None
  3215. */
  3216. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3217. {
  3218. if (qdf_unlikely(vdev->to_fw))
  3219. QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf) = 1;
  3220. }
  3221. #else
  3222. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3223. {
  3224. }
  3225. #endif
  3226. /*
  3227. * dp_tx_send() - Transmit a frame on a given VAP
  3228. * @soc: DP soc handle
  3229. * @vdev_id: id of DP vdev handle
  3230. * @nbuf: skb
  3231. *
  3232. * Entry point for Core Tx layer (DP_TX) invoked from
  3233. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3234. * cases
  3235. *
  3236. * Return: NULL on success,
  3237. * nbuf when it fails to send
  3238. */
  3239. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3240. qdf_nbuf_t nbuf)
  3241. {
  3242. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3243. uint16_t peer_id = HTT_INVALID_PEER;
  3244. /*
  3245. * doing a memzero is causing additional function call overhead
  3246. * so doing static stack clearing
  3247. */
  3248. struct dp_tx_msdu_info_s msdu_info = {0};
  3249. struct dp_vdev *vdev = NULL;
  3250. qdf_nbuf_t end_nbuf = NULL;
  3251. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3252. return nbuf;
  3253. /*
  3254. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3255. * this in per packet path.
  3256. *
  3257. * As in this path vdev memory is already protected with netdev
  3258. * tx lock
  3259. */
  3260. vdev = soc->vdev_id_map[vdev_id];
  3261. if (qdf_unlikely(!vdev))
  3262. return nbuf;
  3263. dp_vdev_tx_mark_to_fw(nbuf, vdev);
  3264. /*
  3265. * Set Default Host TID value to invalid TID
  3266. * (TID override disabled)
  3267. */
  3268. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3269. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  3270. if (qdf_unlikely(vdev->mesh_vdev)) {
  3271. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3272. &msdu_info);
  3273. if (!nbuf_mesh) {
  3274. dp_verbose_debug("Extracting mesh metadata failed");
  3275. return nbuf;
  3276. }
  3277. nbuf = nbuf_mesh;
  3278. }
  3279. /*
  3280. * Get HW Queue to use for this frame.
  3281. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3282. * dedicated for data and 1 for command.
  3283. * "queue_id" maps to one hardware ring.
  3284. * With each ring, we also associate a unique Tx descriptor pool
  3285. * to minimize lock contention for these resources.
  3286. */
  3287. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3288. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3289. 1);
  3290. /*
  3291. * TCL H/W supports 2 DSCP-TID mapping tables.
  3292. * Table 1 - Default DSCP-TID mapping table
  3293. * Table 2 - 1 DSCP-TID override table
  3294. *
  3295. * If we need a different DSCP-TID mapping for this vap,
  3296. * call tid_classify to extract DSCP/ToS from frame and
  3297. * map to a TID and store in msdu_info. This is later used
  3298. * to fill in TCL Input descriptor (per-packet TID override).
  3299. */
  3300. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3301. /*
  3302. * Classify the frame and call corresponding
  3303. * "prepare" function which extracts the segment (TSO)
  3304. * and fragmentation information (for TSO , SG, ME, or Raw)
  3305. * into MSDU_INFO structure which is later used to fill
  3306. * SW and HW descriptors.
  3307. */
  3308. if (qdf_nbuf_is_tso(nbuf)) {
  3309. dp_verbose_debug("TSO frame %pK", vdev);
  3310. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3311. qdf_nbuf_len(nbuf));
  3312. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3313. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3314. qdf_nbuf_len(nbuf));
  3315. return nbuf;
  3316. }
  3317. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  3318. goto send_multiple;
  3319. }
  3320. /* SG */
  3321. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3322. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3323. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3324. return nbuf;
  3325. } else {
  3326. struct dp_tx_seg_info_s seg_info = {0};
  3327. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3328. goto send_single;
  3329. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3330. &msdu_info);
  3331. if (!nbuf)
  3332. return NULL;
  3333. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3334. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3335. qdf_nbuf_len(nbuf));
  3336. goto send_multiple;
  3337. }
  3338. }
  3339. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3340. return NULL;
  3341. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3342. return nbuf;
  3343. /* RAW */
  3344. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3345. struct dp_tx_seg_info_s seg_info = {0};
  3346. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3347. if (!nbuf)
  3348. return NULL;
  3349. dp_verbose_debug("Raw frame %pK", vdev);
  3350. goto send_multiple;
  3351. }
  3352. if (qdf_unlikely(vdev->nawds_enabled)) {
  3353. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3354. qdf_nbuf_data(nbuf);
  3355. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3356. uint16_t sa_peer_id = DP_INVALID_PEER;
  3357. if (!soc->ast_offload_support) {
  3358. struct dp_ast_entry *ast_entry = NULL;
  3359. qdf_spin_lock_bh(&soc->ast_lock);
  3360. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3361. (soc,
  3362. (uint8_t *)(eh->ether_shost),
  3363. vdev->pdev->pdev_id);
  3364. if (ast_entry)
  3365. sa_peer_id = ast_entry->peer_id;
  3366. qdf_spin_unlock_bh(&soc->ast_lock);
  3367. }
  3368. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3369. sa_peer_id);
  3370. }
  3371. peer_id = DP_INVALID_PEER;
  3372. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3373. 1, qdf_nbuf_len(nbuf));
  3374. }
  3375. send_single:
  3376. /* Single linear frame */
  3377. /*
  3378. * If nbuf is a simple linear frame, use send_single function to
  3379. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3380. * SRNG. There is no need to setup a MSDU extension descriptor.
  3381. */
  3382. dp_tx_prefetch_nbuf_data(nbuf);
  3383. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3384. peer_id, end_nbuf);
  3385. return nbuf;
  3386. send_multiple:
  3387. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3388. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3389. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3390. return nbuf;
  3391. }
  3392. /**
  3393. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3394. * case to vaoid check in perpkt path.
  3395. * @soc: DP soc handle
  3396. * @vdev_id: id of DP vdev handle
  3397. * @nbuf: skb
  3398. *
  3399. * Entry point for Core Tx layer (DP_TX) invoked from
  3400. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3401. * with special condition to avoid per pkt check in dp_tx_send
  3402. *
  3403. * Return: NULL on success,
  3404. * nbuf when it fails to send
  3405. */
  3406. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3407. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3408. {
  3409. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3410. struct dp_vdev *vdev = NULL;
  3411. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3412. return nbuf;
  3413. /*
  3414. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3415. * this in per packet path.
  3416. *
  3417. * As in this path vdev memory is already protected with netdev
  3418. * tx lock
  3419. */
  3420. vdev = soc->vdev_id_map[vdev_id];
  3421. if (qdf_unlikely(!vdev))
  3422. return nbuf;
  3423. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3424. == QDF_STATUS_E_FAILURE)) {
  3425. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3426. return nbuf;
  3427. }
  3428. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3429. }
  3430. #ifdef UMAC_SUPPORT_PROXY_ARP
  3431. /**
  3432. * dp_tx_proxy_arp() - Tx proxy arp handler
  3433. * @vdev: datapath vdev handle
  3434. * @buf: sk buffer
  3435. *
  3436. * Return: status
  3437. */
  3438. static inline
  3439. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3440. {
  3441. if (vdev->osif_proxy_arp)
  3442. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3443. /*
  3444. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3445. * osif_proxy_arp has a valid function pointer assigned
  3446. * to it
  3447. */
  3448. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3449. return QDF_STATUS_NOT_INITIALIZED;
  3450. }
  3451. #else
  3452. /**
  3453. * dp_tx_proxy_arp() - Tx proxy arp handler
  3454. * @vdev: datapath vdev handle
  3455. * @buf: sk buffer
  3456. *
  3457. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3458. * is not defined.
  3459. *
  3460. * Return: status
  3461. */
  3462. static inline
  3463. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3464. {
  3465. return QDF_STATUS_SUCCESS;
  3466. }
  3467. #endif
  3468. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3469. #ifdef WLAN_MCAST_MLO
  3470. static bool
  3471. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3472. struct dp_tx_desc_s *tx_desc,
  3473. qdf_nbuf_t nbuf,
  3474. uint8_t reinject_reason)
  3475. {
  3476. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3477. if (soc->arch_ops.dp_tx_mcast_handler)
  3478. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3479. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3480. return true;
  3481. }
  3482. return false;
  3483. }
  3484. #else /* WLAN_MCAST_MLO */
  3485. static inline bool
  3486. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3487. struct dp_tx_desc_s *tx_desc,
  3488. qdf_nbuf_t nbuf,
  3489. uint8_t reinject_reason)
  3490. {
  3491. return false;
  3492. }
  3493. #endif /* WLAN_MCAST_MLO */
  3494. #else
  3495. static inline bool
  3496. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3497. struct dp_tx_desc_s *tx_desc,
  3498. qdf_nbuf_t nbuf,
  3499. uint8_t reinject_reason)
  3500. {
  3501. return false;
  3502. }
  3503. #endif
  3504. /**
  3505. * dp_tx_reinject_handler() - Tx Reinject Handler
  3506. * @soc: datapath soc handle
  3507. * @vdev: datapath vdev handle
  3508. * @tx_desc: software descriptor head pointer
  3509. * @status : Tx completion status from HTT descriptor
  3510. * @reinject_reason : reinject reason from HTT descriptor
  3511. *
  3512. * This function reinjects frames back to Target.
  3513. * Todo - Host queue needs to be added
  3514. *
  3515. * Return: none
  3516. */
  3517. void dp_tx_reinject_handler(struct dp_soc *soc,
  3518. struct dp_vdev *vdev,
  3519. struct dp_tx_desc_s *tx_desc,
  3520. uint8_t *status,
  3521. uint8_t reinject_reason)
  3522. {
  3523. struct dp_peer *peer = NULL;
  3524. uint32_t peer_id = HTT_INVALID_PEER;
  3525. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3526. qdf_nbuf_t nbuf_copy = NULL;
  3527. struct dp_tx_msdu_info_s msdu_info;
  3528. #ifdef WDS_VENDOR_EXTENSION
  3529. int is_mcast = 0, is_ucast = 0;
  3530. int num_peers_3addr = 0;
  3531. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3532. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3533. #endif
  3534. struct dp_txrx_peer *txrx_peer;
  3535. qdf_assert(vdev);
  3536. dp_tx_debug("Tx reinject path");
  3537. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3538. qdf_nbuf_len(tx_desc->nbuf));
  3539. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3540. return;
  3541. #ifdef WDS_VENDOR_EXTENSION
  3542. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3543. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3544. } else {
  3545. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3546. }
  3547. is_ucast = !is_mcast;
  3548. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3549. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3550. txrx_peer = dp_get_txrx_peer(peer);
  3551. if (!txrx_peer || txrx_peer->bss_peer)
  3552. continue;
  3553. /* Detect wds peers that use 3-addr framing for mcast.
  3554. * if there are any, the bss_peer is used to send the
  3555. * the mcast frame using 3-addr format. all wds enabled
  3556. * peers that use 4-addr framing for mcast frames will
  3557. * be duplicated and sent as 4-addr frames below.
  3558. */
  3559. if (!txrx_peer->wds_enabled ||
  3560. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3561. num_peers_3addr = 1;
  3562. break;
  3563. }
  3564. }
  3565. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3566. #endif
  3567. if (qdf_unlikely(vdev->mesh_vdev)) {
  3568. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3569. } else {
  3570. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3571. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3572. txrx_peer = dp_get_txrx_peer(peer);
  3573. if (!txrx_peer)
  3574. continue;
  3575. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3576. #ifdef WDS_VENDOR_EXTENSION
  3577. /*
  3578. * . if 3-addr STA, then send on BSS Peer
  3579. * . if Peer WDS enabled and accept 4-addr mcast,
  3580. * send mcast on that peer only
  3581. * . if Peer WDS enabled and accept 4-addr ucast,
  3582. * send ucast on that peer only
  3583. */
  3584. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3585. (txrx_peer->wds_enabled &&
  3586. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3587. (is_ucast &&
  3588. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3589. #else
  3590. (txrx_peer->bss_peer &&
  3591. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3592. #endif
  3593. peer_id = DP_INVALID_PEER;
  3594. nbuf_copy = qdf_nbuf_copy(nbuf);
  3595. if (!nbuf_copy) {
  3596. dp_tx_debug("nbuf copy failed");
  3597. break;
  3598. }
  3599. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3600. dp_tx_get_queue(vdev, nbuf,
  3601. &msdu_info.tx_queue);
  3602. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3603. nbuf_copy,
  3604. &msdu_info,
  3605. peer_id,
  3606. NULL);
  3607. if (nbuf_copy) {
  3608. dp_tx_debug("pkt send failed");
  3609. qdf_nbuf_free(nbuf_copy);
  3610. }
  3611. }
  3612. }
  3613. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3614. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3615. QDF_DMA_TO_DEVICE, nbuf->len);
  3616. qdf_nbuf_free(nbuf);
  3617. }
  3618. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3619. }
  3620. /**
  3621. * dp_tx_inspect_handler() - Tx Inspect Handler
  3622. * @soc: datapath soc handle
  3623. * @vdev: datapath vdev handle
  3624. * @tx_desc: software descriptor head pointer
  3625. * @status : Tx completion status from HTT descriptor
  3626. *
  3627. * Handles Tx frames sent back to Host for inspection
  3628. * (ProxyARP)
  3629. *
  3630. * Return: none
  3631. */
  3632. void dp_tx_inspect_handler(struct dp_soc *soc,
  3633. struct dp_vdev *vdev,
  3634. struct dp_tx_desc_s *tx_desc,
  3635. uint8_t *status)
  3636. {
  3637. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3638. "%s Tx inspect path",
  3639. __func__);
  3640. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3641. qdf_nbuf_len(tx_desc->nbuf));
  3642. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3643. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3644. }
  3645. #ifdef MESH_MODE_SUPPORT
  3646. /**
  3647. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3648. * in mesh meta header
  3649. * @tx_desc: software descriptor head pointer
  3650. * @ts: pointer to tx completion stats
  3651. * Return: none
  3652. */
  3653. static
  3654. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3655. struct hal_tx_completion_status *ts)
  3656. {
  3657. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3658. if (!tx_desc->msdu_ext_desc) {
  3659. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3660. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3661. "netbuf %pK offset %d",
  3662. netbuf, tx_desc->pkt_offset);
  3663. return;
  3664. }
  3665. }
  3666. }
  3667. #else
  3668. static
  3669. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3670. struct hal_tx_completion_status *ts)
  3671. {
  3672. }
  3673. #endif
  3674. #ifdef CONFIG_SAWF
  3675. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3676. struct dp_vdev *vdev,
  3677. struct dp_txrx_peer *txrx_peer,
  3678. struct dp_tx_desc_s *tx_desc,
  3679. struct hal_tx_completion_status *ts,
  3680. uint8_t tid)
  3681. {
  3682. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3683. ts, tid);
  3684. }
  3685. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3686. uint32_t nw_delay,
  3687. uint32_t sw_delay,
  3688. uint32_t hw_delay)
  3689. {
  3690. dp_peer_tid_delay_avg(tx_delay,
  3691. nw_delay,
  3692. sw_delay,
  3693. hw_delay);
  3694. }
  3695. #else
  3696. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3697. struct dp_vdev *vdev,
  3698. struct dp_txrx_peer *txrx_peer,
  3699. struct dp_tx_desc_s *tx_desc,
  3700. struct hal_tx_completion_status *ts,
  3701. uint8_t tid)
  3702. {
  3703. }
  3704. static inline void
  3705. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3706. uint32_t nw_delay, uint32_t sw_delay,
  3707. uint32_t hw_delay)
  3708. {
  3709. }
  3710. #endif
  3711. #ifdef QCA_PEER_EXT_STATS
  3712. #ifdef WLAN_CONFIG_TX_DELAY
  3713. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3714. struct dp_tx_desc_s *tx_desc,
  3715. struct hal_tx_completion_status *ts,
  3716. struct dp_vdev *vdev)
  3717. {
  3718. struct dp_soc *soc = vdev->pdev->soc;
  3719. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3720. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3721. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3722. if (!ts->valid)
  3723. return;
  3724. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3725. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3726. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3727. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3728. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3729. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3730. &fwhw_transmit_delay))
  3731. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3732. fwhw_transmit_delay);
  3733. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3734. fwhw_transmit_delay);
  3735. }
  3736. #else
  3737. /*
  3738. * dp_tx_compute_tid_delay() - Compute per TID delay
  3739. * @stats: Per TID delay stats
  3740. * @tx_desc: Software Tx descriptor
  3741. * @ts: Tx completion status
  3742. * @vdev: vdev
  3743. *
  3744. * Compute the software enqueue and hw enqueue delays and
  3745. * update the respective histograms
  3746. *
  3747. * Return: void
  3748. */
  3749. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3750. struct dp_tx_desc_s *tx_desc,
  3751. struct hal_tx_completion_status *ts,
  3752. struct dp_vdev *vdev)
  3753. {
  3754. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3755. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3756. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3757. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3758. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3759. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3760. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3761. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3762. timestamp_hw_enqueue);
  3763. /*
  3764. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3765. */
  3766. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3767. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3768. }
  3769. #endif
  3770. /*
  3771. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3772. * @txrx_peer: DP peer context
  3773. * @tx_desc: Tx software descriptor
  3774. * @tid: Transmission ID
  3775. * @ring_id: Rx CPU context ID/CPU_ID
  3776. *
  3777. * Update the peer extended stats. These are enhanced other
  3778. * delay stats per msdu level.
  3779. *
  3780. * Return: void
  3781. */
  3782. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3783. struct dp_tx_desc_s *tx_desc,
  3784. struct hal_tx_completion_status *ts,
  3785. uint8_t ring_id)
  3786. {
  3787. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3788. struct dp_soc *soc = NULL;
  3789. struct dp_peer_delay_stats *delay_stats = NULL;
  3790. uint8_t tid;
  3791. soc = pdev->soc;
  3792. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3793. return;
  3794. if (!txrx_peer->delay_stats)
  3795. return;
  3796. tid = ts->tid;
  3797. delay_stats = txrx_peer->delay_stats;
  3798. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3799. /*
  3800. * For non-TID packets use the TID 9
  3801. */
  3802. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3803. tid = CDP_MAX_DATA_TIDS - 1;
  3804. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3805. tx_desc, ts, txrx_peer->vdev);
  3806. }
  3807. #else
  3808. static inline
  3809. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3810. struct dp_tx_desc_s *tx_desc,
  3811. struct hal_tx_completion_status *ts,
  3812. uint8_t ring_id)
  3813. {
  3814. }
  3815. #endif
  3816. #ifdef WLAN_PEER_JITTER
  3817. /*
  3818. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3819. * @curr_delay: Current delay
  3820. * @prev_Delay: Previous delay
  3821. * @avg_jitter: Average Jitter
  3822. * Return: Newly Computed Average Jitter
  3823. */
  3824. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3825. uint32_t prev_delay,
  3826. uint32_t avg_jitter)
  3827. {
  3828. uint32_t curr_jitter;
  3829. int32_t jitter_diff;
  3830. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3831. if (!avg_jitter)
  3832. return curr_jitter;
  3833. jitter_diff = curr_jitter - avg_jitter;
  3834. if (jitter_diff < 0)
  3835. avg_jitter = avg_jitter -
  3836. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3837. else
  3838. avg_jitter = avg_jitter +
  3839. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3840. return avg_jitter;
  3841. }
  3842. /*
  3843. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3844. * @curr_delay: Current delay
  3845. * @avg_Delay: Average delay
  3846. * Return: Newly Computed Average Delay
  3847. */
  3848. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3849. uint32_t avg_delay)
  3850. {
  3851. int32_t delay_diff;
  3852. if (!avg_delay)
  3853. return curr_delay;
  3854. delay_diff = curr_delay - avg_delay;
  3855. if (delay_diff < 0)
  3856. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3857. DP_AVG_DELAY_WEIGHT_DENOM);
  3858. else
  3859. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3860. DP_AVG_DELAY_WEIGHT_DENOM);
  3861. return avg_delay;
  3862. }
  3863. #ifdef WLAN_CONFIG_TX_DELAY
  3864. /*
  3865. * dp_tx_compute_cur_delay() - get the current delay
  3866. * @soc: soc handle
  3867. * @vdev: vdev structure for data path state
  3868. * @ts: Tx completion status
  3869. * @curr_delay: current delay
  3870. * @tx_desc: tx descriptor
  3871. * Return: void
  3872. */
  3873. static
  3874. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3875. struct dp_vdev *vdev,
  3876. struct hal_tx_completion_status *ts,
  3877. uint32_t *curr_delay,
  3878. struct dp_tx_desc_s *tx_desc)
  3879. {
  3880. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3881. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3882. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3883. curr_delay);
  3884. return status;
  3885. }
  3886. #else
  3887. static
  3888. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3889. struct dp_vdev *vdev,
  3890. struct hal_tx_completion_status *ts,
  3891. uint32_t *curr_delay,
  3892. struct dp_tx_desc_s *tx_desc)
  3893. {
  3894. int64_t current_timestamp, timestamp_hw_enqueue;
  3895. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3896. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3897. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3898. return QDF_STATUS_SUCCESS;
  3899. }
  3900. #endif
  3901. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3902. * @jiiter - per tid per ring jitter stats
  3903. * @ts: Tx completion status
  3904. * @vdev - vdev structure for data path state
  3905. * @tx_desc - tx descriptor
  3906. * Return: void
  3907. */
  3908. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3909. struct hal_tx_completion_status *ts,
  3910. struct dp_vdev *vdev,
  3911. struct dp_tx_desc_s *tx_desc)
  3912. {
  3913. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3914. struct dp_soc *soc = vdev->pdev->soc;
  3915. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3916. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3917. jitter->tx_drop += 1;
  3918. return;
  3919. }
  3920. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3921. tx_desc);
  3922. if (QDF_IS_STATUS_SUCCESS(status)) {
  3923. avg_delay = jitter->tx_avg_delay;
  3924. avg_jitter = jitter->tx_avg_jitter;
  3925. prev_delay = jitter->tx_prev_delay;
  3926. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3927. prev_delay,
  3928. avg_jitter);
  3929. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3930. jitter->tx_avg_delay = avg_delay;
  3931. jitter->tx_avg_jitter = avg_jitter;
  3932. jitter->tx_prev_delay = curr_delay;
  3933. jitter->tx_total_success += 1;
  3934. } else if (status == QDF_STATUS_E_FAILURE) {
  3935. jitter->tx_avg_err += 1;
  3936. }
  3937. }
  3938. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3939. * @txrx_peer: DP peer context
  3940. * @tx_desc: Tx software descriptor
  3941. * @ts: Tx completion status
  3942. * @ring_id: Rx CPU context ID/CPU_ID
  3943. * Return: void
  3944. */
  3945. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3946. struct dp_tx_desc_s *tx_desc,
  3947. struct hal_tx_completion_status *ts,
  3948. uint8_t ring_id)
  3949. {
  3950. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3951. struct dp_soc *soc = pdev->soc;
  3952. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3953. uint8_t tid;
  3954. struct cdp_peer_tid_stats *rx_tid = NULL;
  3955. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3956. return;
  3957. tid = ts->tid;
  3958. jitter_stats = txrx_peer->jitter_stats;
  3959. qdf_assert_always(jitter_stats);
  3960. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3961. /*
  3962. * For non-TID packets use the TID 9
  3963. */
  3964. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3965. tid = CDP_MAX_DATA_TIDS - 1;
  3966. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3967. dp_tx_compute_tid_jitter(rx_tid,
  3968. ts, txrx_peer->vdev, tx_desc);
  3969. }
  3970. #else
  3971. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3972. struct dp_tx_desc_s *tx_desc,
  3973. struct hal_tx_completion_status *ts,
  3974. uint8_t ring_id)
  3975. {
  3976. }
  3977. #endif
  3978. #ifdef HW_TX_DELAY_STATS_ENABLE
  3979. /**
  3980. * dp_update_tx_delay_stats() - update the delay stats
  3981. * @vdev: vdev handle
  3982. * @delay: delay in ms or us based on the flag delay_in_us
  3983. * @tid: tid value
  3984. * @mode: type of tx delay mode
  3985. * @ring id: ring number
  3986. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3987. *
  3988. * Return: none
  3989. */
  3990. static inline
  3991. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3992. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3993. {
  3994. struct cdp_tid_tx_stats *tstats =
  3995. &vdev->stats.tid_tx_stats[ring_id][tid];
  3996. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3997. delay_in_us);
  3998. }
  3999. #else
  4000. static inline
  4001. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  4002. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  4003. {
  4004. struct cdp_tid_tx_stats *tstats =
  4005. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4006. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  4007. delay_in_us);
  4008. }
  4009. #endif
  4010. /**
  4011. * dp_tx_compute_delay() - Compute and fill in all timestamps
  4012. * to pass in correct fields
  4013. *
  4014. * @vdev: pdev handle
  4015. * @tx_desc: tx descriptor
  4016. * @tid: tid value
  4017. * @ring_id: TCL or WBM ring number for transmit path
  4018. * Return: none
  4019. */
  4020. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  4021. uint8_t tid, uint8_t ring_id)
  4022. {
  4023. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  4024. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  4025. uint32_t fwhw_transmit_delay_us;
  4026. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  4027. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  4028. return;
  4029. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  4030. fwhw_transmit_delay_us =
  4031. qdf_ktime_to_us(qdf_ktime_real_get()) -
  4032. qdf_ktime_to_us(tx_desc->timestamp);
  4033. /*
  4034. * Delay between packet enqueued to HW and Tx completion in us
  4035. */
  4036. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  4037. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  4038. ring_id, true);
  4039. /*
  4040. * For MCL, only enqueue to completion delay is required
  4041. * so return if the vdev flag is enabled.
  4042. */
  4043. return;
  4044. }
  4045. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  4046. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  4047. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  4048. timestamp_hw_enqueue);
  4049. if (!timestamp_hw_enqueue)
  4050. return;
  4051. /*
  4052. * Delay between packet enqueued to HW and Tx completion in ms
  4053. */
  4054. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  4055. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  4056. false);
  4057. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  4058. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  4059. interframe_delay = (uint32_t)(timestamp_ingress -
  4060. vdev->prev_tx_enq_tstamp);
  4061. /*
  4062. * Delay in software enqueue
  4063. */
  4064. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  4065. CDP_DELAY_STATS_SW_ENQ, ring_id,
  4066. false);
  4067. /*
  4068. * Update interframe delay stats calculated at hardstart receive point.
  4069. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  4070. * interframe delay will not be calculate correctly for 1st frame.
  4071. * On the other side, this will help in avoiding extra per packet check
  4072. * of !vdev->prev_tx_enq_tstamp.
  4073. */
  4074. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  4075. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  4076. false);
  4077. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  4078. }
  4079. #ifdef DISABLE_DP_STATS
  4080. static
  4081. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  4082. struct dp_txrx_peer *txrx_peer)
  4083. {
  4084. }
  4085. #else
  4086. static inline void
  4087. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  4088. {
  4089. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  4090. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  4091. if (subtype != QDF_PROTO_INVALID)
  4092. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  4093. 1);
  4094. }
  4095. #endif
  4096. #ifndef QCA_ENHANCED_STATS_SUPPORT
  4097. #ifdef DP_PEER_EXTENDED_API
  4098. static inline uint8_t
  4099. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4100. {
  4101. return txrx_peer->mpdu_retry_threshold;
  4102. }
  4103. #else
  4104. static inline uint8_t
  4105. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4106. {
  4107. return 0;
  4108. }
  4109. #endif
  4110. /**
  4111. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  4112. *
  4113. * @ts: Tx compltion status
  4114. * @txrx_peer: datapath txrx_peer handle
  4115. *
  4116. * Return: void
  4117. */
  4118. static inline void
  4119. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4120. struct dp_txrx_peer *txrx_peer)
  4121. {
  4122. uint8_t mcs, pkt_type, dst_mcs_idx;
  4123. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  4124. mcs = ts->mcs;
  4125. pkt_type = ts->pkt_type;
  4126. /* do HW to SW pkt type conversion */
  4127. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  4128. hal_2_dp_pkt_type_map[pkt_type]);
  4129. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  4130. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  4131. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4132. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  4133. 1);
  4134. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  4135. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  4136. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  4137. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4138. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  4139. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  4140. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  4141. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  4142. if (ts->first_msdu) {
  4143. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  4144. ts->transmit_cnt > 1);
  4145. if (!retry_threshold)
  4146. return;
  4147. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  4148. qdf_do_div(ts->transmit_cnt,
  4149. retry_threshold),
  4150. ts->transmit_cnt > retry_threshold);
  4151. }
  4152. }
  4153. #else
  4154. static inline void
  4155. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4156. struct dp_txrx_peer *txrx_peer)
  4157. {
  4158. }
  4159. #endif
  4160. /**
  4161. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4162. * per wbm ring
  4163. *
  4164. * @tx_desc: software descriptor head pointer
  4165. * @ts: Tx completion status
  4166. * @peer: peer handle
  4167. * @ring_id: ring number
  4168. *
  4169. * Return: None
  4170. */
  4171. static inline void
  4172. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4173. struct hal_tx_completion_status *ts,
  4174. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  4175. {
  4176. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4177. uint8_t tid = ts->tid;
  4178. uint32_t length;
  4179. struct cdp_tid_tx_stats *tid_stats;
  4180. if (!pdev)
  4181. return;
  4182. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4183. tid = CDP_MAX_DATA_TIDS - 1;
  4184. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4185. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4186. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4187. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4188. return;
  4189. }
  4190. length = qdf_nbuf_len(tx_desc->nbuf);
  4191. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4192. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4193. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4194. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4195. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4196. tid_stats->tqm_status_cnt[ts->status]++;
  4197. }
  4198. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4199. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4200. ts->transmit_cnt > 1);
  4201. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4202. 1, ts->transmit_cnt > 2);
  4203. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4204. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4205. ts->msdu_part_of_amsdu);
  4206. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4207. !ts->msdu_part_of_amsdu);
  4208. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4209. qdf_system_ticks();
  4210. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4211. return;
  4212. }
  4213. /*
  4214. * tx_failed is ideally supposed to be updated from HTT ppdu
  4215. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4216. * hw limitation there are no completions for failed cases.
  4217. * Hence updating tx_failed from data path. Please note that
  4218. * if tx_failed is fixed to be from ppdu, then this has to be
  4219. * removed
  4220. */
  4221. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4222. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4223. ts->transmit_cnt > DP_RETRY_COUNT);
  4224. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4225. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4226. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4227. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4228. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4229. length);
  4230. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4231. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4232. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4233. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4234. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4235. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4236. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4237. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4238. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4239. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4240. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4241. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4242. tx.dropped.fw_rem_queue_disable, 1);
  4243. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4244. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4245. tx.dropped.fw_rem_no_match, 1);
  4246. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4247. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4248. tx.dropped.drop_threshold, 1);
  4249. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4250. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4251. tx.dropped.drop_link_desc_na, 1);
  4252. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4253. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4254. tx.dropped.invalid_drop, 1);
  4255. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4256. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4257. tx.dropped.mcast_vdev_drop, 1);
  4258. } else {
  4259. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4260. }
  4261. }
  4262. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4263. /**
  4264. * dp_tx_flow_pool_lock() - take flow pool lock
  4265. * @soc: core txrx main context
  4266. * @tx_desc: tx desc
  4267. *
  4268. * Return: None
  4269. */
  4270. static inline
  4271. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4272. struct dp_tx_desc_s *tx_desc)
  4273. {
  4274. struct dp_tx_desc_pool_s *pool;
  4275. uint8_t desc_pool_id;
  4276. desc_pool_id = tx_desc->pool_id;
  4277. pool = &soc->tx_desc[desc_pool_id];
  4278. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4279. }
  4280. /**
  4281. * dp_tx_flow_pool_unlock() - release flow pool lock
  4282. * @soc: core txrx main context
  4283. * @tx_desc: tx desc
  4284. *
  4285. * Return: None
  4286. */
  4287. static inline
  4288. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4289. struct dp_tx_desc_s *tx_desc)
  4290. {
  4291. struct dp_tx_desc_pool_s *pool;
  4292. uint8_t desc_pool_id;
  4293. desc_pool_id = tx_desc->pool_id;
  4294. pool = &soc->tx_desc[desc_pool_id];
  4295. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4296. }
  4297. #else
  4298. static inline
  4299. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4300. {
  4301. }
  4302. static inline
  4303. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4304. {
  4305. }
  4306. #endif
  4307. /**
  4308. * dp_tx_notify_completion() - Notify tx completion for this desc
  4309. * @soc: core txrx main context
  4310. * @vdev: datapath vdev handle
  4311. * @tx_desc: tx desc
  4312. * @netbuf: buffer
  4313. * @status: tx status
  4314. *
  4315. * Return: none
  4316. */
  4317. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4318. struct dp_vdev *vdev,
  4319. struct dp_tx_desc_s *tx_desc,
  4320. qdf_nbuf_t netbuf,
  4321. uint8_t status)
  4322. {
  4323. void *osif_dev;
  4324. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4325. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4326. qdf_assert(tx_desc);
  4327. if (!vdev ||
  4328. !vdev->osif_vdev) {
  4329. return;
  4330. }
  4331. osif_dev = vdev->osif_vdev;
  4332. tx_compl_cbk = vdev->tx_comp;
  4333. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4334. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4335. if (tx_compl_cbk)
  4336. tx_compl_cbk(netbuf, osif_dev, flag);
  4337. }
  4338. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4339. * @pdev: pdev handle
  4340. * @tid: tid value
  4341. * @txdesc_ts: timestamp from txdesc
  4342. * @ppdu_id: ppdu id
  4343. *
  4344. * Return: none
  4345. */
  4346. #ifdef FEATURE_PERPKT_INFO
  4347. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4348. struct dp_txrx_peer *txrx_peer,
  4349. uint8_t tid,
  4350. uint64_t txdesc_ts,
  4351. uint32_t ppdu_id)
  4352. {
  4353. uint64_t delta_ms;
  4354. struct cdp_tx_sojourn_stats *sojourn_stats;
  4355. struct dp_peer *primary_link_peer = NULL;
  4356. struct dp_soc *link_peer_soc = NULL;
  4357. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4358. return;
  4359. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4360. tid >= CDP_DATA_TID_MAX))
  4361. return;
  4362. if (qdf_unlikely(!pdev->sojourn_buf))
  4363. return;
  4364. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4365. txrx_peer->peer_id,
  4366. DP_MOD_ID_TX_COMP);
  4367. if (qdf_unlikely(!primary_link_peer))
  4368. return;
  4369. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4370. qdf_nbuf_data(pdev->sojourn_buf);
  4371. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4372. sojourn_stats->cookie = (void *)
  4373. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4374. primary_link_peer);
  4375. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4376. txdesc_ts;
  4377. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4378. delta_ms);
  4379. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4380. sojourn_stats->num_msdus[tid] = 1;
  4381. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4382. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4383. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4384. pdev->sojourn_buf, HTT_INVALID_PEER,
  4385. WDI_NO_VAL, pdev->pdev_id);
  4386. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4387. sojourn_stats->num_msdus[tid] = 0;
  4388. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4389. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4390. }
  4391. #else
  4392. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4393. struct dp_txrx_peer *txrx_peer,
  4394. uint8_t tid,
  4395. uint64_t txdesc_ts,
  4396. uint32_t ppdu_id)
  4397. {
  4398. }
  4399. #endif
  4400. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4401. /**
  4402. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4403. * @soc: dp_soc handle
  4404. * @desc: Tx Descriptor
  4405. * @ts: HAL Tx completion descriptor contents
  4406. *
  4407. * This function is used to send tx completion to packet capture
  4408. */
  4409. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4410. struct dp_tx_desc_s *desc,
  4411. struct hal_tx_completion_status *ts)
  4412. {
  4413. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4414. desc, ts->peer_id,
  4415. WDI_NO_VAL, desc->pdev->pdev_id);
  4416. }
  4417. #endif
  4418. /**
  4419. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4420. * @soc: DP Soc handle
  4421. * @tx_desc: software Tx descriptor
  4422. * @ts : Tx completion status from HAL/HTT descriptor
  4423. *
  4424. * Return: none
  4425. */
  4426. void
  4427. dp_tx_comp_process_desc(struct dp_soc *soc,
  4428. struct dp_tx_desc_s *desc,
  4429. struct hal_tx_completion_status *ts,
  4430. struct dp_txrx_peer *txrx_peer)
  4431. {
  4432. uint64_t time_latency = 0;
  4433. uint16_t peer_id = DP_INVALID_PEER_ID;
  4434. /*
  4435. * m_copy/tx_capture modes are not supported for
  4436. * scatter gather packets
  4437. */
  4438. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4439. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4440. qdf_ktime_to_ms(desc->timestamp));
  4441. }
  4442. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4443. if (dp_tx_pkt_tracepoints_enabled())
  4444. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4445. desc->msdu_ext_desc ?
  4446. desc->msdu_ext_desc->tso_desc : NULL,
  4447. qdf_ktime_to_ms(desc->timestamp));
  4448. if (!(desc->msdu_ext_desc)) {
  4449. dp_tx_enh_unmap(soc, desc);
  4450. if (txrx_peer)
  4451. peer_id = txrx_peer->peer_id;
  4452. if (QDF_STATUS_SUCCESS ==
  4453. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4454. return;
  4455. }
  4456. if (QDF_STATUS_SUCCESS ==
  4457. dp_get_completion_indication_for_stack(soc,
  4458. desc->pdev,
  4459. txrx_peer, ts,
  4460. desc->nbuf,
  4461. time_latency)) {
  4462. dp_send_completion_to_stack(soc,
  4463. desc->pdev,
  4464. ts->peer_id,
  4465. ts->ppdu_id,
  4466. desc->nbuf);
  4467. return;
  4468. }
  4469. }
  4470. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4471. dp_tx_comp_free_buf(soc, desc, false);
  4472. }
  4473. #ifdef DISABLE_DP_STATS
  4474. /**
  4475. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4476. * @soc: core txrx main context
  4477. * @tx_desc: tx desc
  4478. * @status: tx status
  4479. *
  4480. * Return: none
  4481. */
  4482. static inline
  4483. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4484. struct dp_vdev *vdev,
  4485. struct dp_tx_desc_s *tx_desc,
  4486. uint8_t status)
  4487. {
  4488. }
  4489. #else
  4490. static inline
  4491. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4492. struct dp_vdev *vdev,
  4493. struct dp_tx_desc_s *tx_desc,
  4494. uint8_t status)
  4495. {
  4496. void *osif_dev;
  4497. ol_txrx_stats_rx_fp stats_cbk;
  4498. uint8_t pkt_type;
  4499. qdf_assert(tx_desc);
  4500. if (!vdev ||
  4501. !vdev->osif_vdev ||
  4502. !vdev->stats_cb)
  4503. return;
  4504. osif_dev = vdev->osif_vdev;
  4505. stats_cbk = vdev->stats_cb;
  4506. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4507. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4508. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4509. &pkt_type);
  4510. }
  4511. #endif
  4512. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4513. /* Mask for bit29 ~ bit31 */
  4514. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4515. /* Timestamp value (unit us) if bit29 is set */
  4516. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4517. /**
  4518. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4519. * @ack_ts: OTA ack timestamp, unit us.
  4520. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4521. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4522. *
  4523. * this function will restore the bit29 ~ bit31 3 bits value for
  4524. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4525. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4526. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4527. *
  4528. * Return: the adjusted buffer_timestamp value
  4529. */
  4530. static inline
  4531. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4532. uint32_t enqueue_ts,
  4533. uint32_t base_delta_ts)
  4534. {
  4535. uint32_t ack_buffer_ts;
  4536. uint32_t ack_buffer_ts_bit29_31;
  4537. uint32_t adjusted_enqueue_ts;
  4538. /* corresponding buffer_timestamp value when receive OTA Ack */
  4539. ack_buffer_ts = ack_ts - base_delta_ts;
  4540. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4541. /* restore the bit29 ~ bit31 value */
  4542. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4543. /*
  4544. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4545. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4546. * should not be marked, otherwise extra 0x20000000 us is added to
  4547. * enqueue_ts.
  4548. */
  4549. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4550. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4551. return adjusted_enqueue_ts;
  4552. }
  4553. QDF_STATUS
  4554. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4555. uint32_t delta_tsf,
  4556. uint32_t *delay_us)
  4557. {
  4558. uint32_t buffer_ts;
  4559. uint32_t delay;
  4560. if (!delay_us)
  4561. return QDF_STATUS_E_INVAL;
  4562. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4563. if (!ts->valid)
  4564. return QDF_STATUS_E_INVAL;
  4565. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4566. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4567. * valid up to 29 bits.
  4568. */
  4569. buffer_ts = ts->buffer_timestamp << 10;
  4570. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4571. buffer_ts, delta_tsf);
  4572. delay = ts->tsf - buffer_ts - delta_tsf;
  4573. if (qdf_unlikely(delay & 0x80000000)) {
  4574. dp_err_rl("delay = 0x%x (-ve)\n"
  4575. "release_src = %d\n"
  4576. "ppdu_id = 0x%x\n"
  4577. "peer_id = 0x%x\n"
  4578. "tid = 0x%x\n"
  4579. "release_reason = %d\n"
  4580. "tsf = %u (0x%x)\n"
  4581. "buffer_timestamp = %u (0x%x)\n"
  4582. "delta_tsf = %u (0x%x)\n",
  4583. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4584. ts->tid, ts->status, ts->tsf, ts->tsf,
  4585. ts->buffer_timestamp, ts->buffer_timestamp,
  4586. delta_tsf, delta_tsf);
  4587. delay = 0;
  4588. goto end;
  4589. }
  4590. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4591. if (delay > 0x1000000) {
  4592. dp_info_rl("----------------------\n"
  4593. "Tx completion status:\n"
  4594. "----------------------\n"
  4595. "release_src = %d\n"
  4596. "ppdu_id = 0x%x\n"
  4597. "release_reason = %d\n"
  4598. "tsf = %u (0x%x)\n"
  4599. "buffer_timestamp = %u (0x%x)\n"
  4600. "delta_tsf = %u (0x%x)\n",
  4601. ts->release_src, ts->ppdu_id, ts->status,
  4602. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4603. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4604. return QDF_STATUS_E_FAILURE;
  4605. }
  4606. end:
  4607. *delay_us = delay;
  4608. return QDF_STATUS_SUCCESS;
  4609. }
  4610. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4611. uint32_t delta_tsf)
  4612. {
  4613. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4614. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4615. DP_MOD_ID_CDP);
  4616. if (!vdev) {
  4617. dp_err_rl("vdev %d does not exist", vdev_id);
  4618. return;
  4619. }
  4620. vdev->delta_tsf = delta_tsf;
  4621. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4622. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4623. }
  4624. #endif
  4625. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4626. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4627. uint8_t vdev_id, bool enable)
  4628. {
  4629. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4630. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4631. DP_MOD_ID_CDP);
  4632. if (!vdev) {
  4633. dp_err_rl("vdev %d does not exist", vdev_id);
  4634. return QDF_STATUS_E_FAILURE;
  4635. }
  4636. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4637. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4638. return QDF_STATUS_SUCCESS;
  4639. }
  4640. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4641. uint32_t *val)
  4642. {
  4643. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4644. struct dp_vdev *vdev;
  4645. uint32_t delay_accum;
  4646. uint32_t pkts_accum;
  4647. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4648. if (!vdev) {
  4649. dp_err_rl("vdev %d does not exist", vdev_id);
  4650. return QDF_STATUS_E_FAILURE;
  4651. }
  4652. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4653. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4654. return QDF_STATUS_E_FAILURE;
  4655. }
  4656. /* Average uplink delay based on current accumulated values */
  4657. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4658. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4659. *val = delay_accum / pkts_accum;
  4660. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4661. delay_accum, pkts_accum);
  4662. /* Reset accumulated values to 0 */
  4663. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4664. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4665. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4666. return QDF_STATUS_SUCCESS;
  4667. }
  4668. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4669. struct hal_tx_completion_status *ts)
  4670. {
  4671. uint32_t ul_delay;
  4672. if (qdf_unlikely(!vdev)) {
  4673. dp_info_rl("vdev is null or delete in progress");
  4674. return;
  4675. }
  4676. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4677. return;
  4678. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4679. vdev->delta_tsf,
  4680. &ul_delay)))
  4681. return;
  4682. ul_delay /= 1000; /* in unit of ms */
  4683. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4684. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4685. }
  4686. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4687. static inline
  4688. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4689. struct hal_tx_completion_status *ts)
  4690. {
  4691. }
  4692. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4693. /**
  4694. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4695. * @soc: DP soc handle
  4696. * @tx_desc: software descriptor head pointer
  4697. * @ts: Tx completion status
  4698. * @txrx_peer: txrx peer handle
  4699. * @ring_id: ring number
  4700. *
  4701. * Return: none
  4702. */
  4703. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4704. struct dp_tx_desc_s *tx_desc,
  4705. struct hal_tx_completion_status *ts,
  4706. struct dp_txrx_peer *txrx_peer,
  4707. uint8_t ring_id)
  4708. {
  4709. uint32_t length;
  4710. qdf_ether_header_t *eh;
  4711. struct dp_vdev *vdev = NULL;
  4712. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4713. enum qdf_dp_tx_rx_status dp_status;
  4714. if (!nbuf) {
  4715. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4716. goto out;
  4717. }
  4718. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4719. length = dp_tx_get_pkt_len(tx_desc);
  4720. dp_status = dp_tx_hw_to_qdf(ts->status);
  4721. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4722. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4723. QDF_TRACE_DEFAULT_PDEV_ID,
  4724. qdf_nbuf_data_addr(nbuf),
  4725. sizeof(qdf_nbuf_data(nbuf)),
  4726. tx_desc->id, ts->status, dp_status));
  4727. dp_tx_comp_debug("-------------------- \n"
  4728. "Tx Completion Stats: \n"
  4729. "-------------------- \n"
  4730. "ack_frame_rssi = %d \n"
  4731. "first_msdu = %d \n"
  4732. "last_msdu = %d \n"
  4733. "msdu_part_of_amsdu = %d \n"
  4734. "rate_stats valid = %d \n"
  4735. "bw = %d \n"
  4736. "pkt_type = %d \n"
  4737. "stbc = %d \n"
  4738. "ldpc = %d \n"
  4739. "sgi = %d \n"
  4740. "mcs = %d \n"
  4741. "ofdma = %d \n"
  4742. "tones_in_ru = %d \n"
  4743. "tsf = %d \n"
  4744. "ppdu_id = %d \n"
  4745. "transmit_cnt = %d \n"
  4746. "tid = %d \n"
  4747. "peer_id = %d\n"
  4748. "tx_status = %d\n",
  4749. ts->ack_frame_rssi, ts->first_msdu,
  4750. ts->last_msdu, ts->msdu_part_of_amsdu,
  4751. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4752. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4753. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4754. ts->transmit_cnt, ts->tid, ts->peer_id,
  4755. ts->status);
  4756. /* Update SoC level stats */
  4757. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4758. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4759. if (!txrx_peer) {
  4760. dp_info_rl("peer is null or deletion in progress");
  4761. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4762. goto out;
  4763. }
  4764. vdev = txrx_peer->vdev;
  4765. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4766. dp_tx_update_uplink_delay(soc, vdev, ts);
  4767. /* check tx complete notification */
  4768. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4769. dp_tx_notify_completion(soc, vdev, tx_desc,
  4770. nbuf, ts->status);
  4771. /* Update per-packet stats for mesh mode */
  4772. if (qdf_unlikely(vdev->mesh_vdev) &&
  4773. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4774. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4775. /* Update peer level stats */
  4776. if (qdf_unlikely(txrx_peer->bss_peer &&
  4777. vdev->opmode == wlan_op_mode_ap)) {
  4778. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4779. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4780. length);
  4781. if (txrx_peer->vdev->tx_encap_type ==
  4782. htt_cmn_pkt_type_ethernet &&
  4783. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4784. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4785. tx.bcast, 1,
  4786. length);
  4787. }
  4788. }
  4789. } else {
  4790. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4791. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4792. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4793. 1, length);
  4794. if (qdf_unlikely(txrx_peer->in_twt)) {
  4795. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4796. tx.tx_success_twt,
  4797. 1, length);
  4798. }
  4799. }
  4800. }
  4801. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4802. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4803. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4804. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4805. ts, ts->tid);
  4806. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4807. #ifdef QCA_SUPPORT_RDK_STATS
  4808. if (soc->peerstats_enabled)
  4809. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4810. qdf_ktime_to_ms(tx_desc->timestamp),
  4811. ts->ppdu_id);
  4812. #endif
  4813. out:
  4814. return;
  4815. }
  4816. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4817. defined(QCA_ENHANCED_STATS_SUPPORT)
  4818. /*
  4819. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4820. * @txrx_peer: Datapath txrx_peer handle
  4821. * @length: Length of the packet
  4822. * @tx_status: Tx status from TQM/FW
  4823. * @update: enhanced flag value present in dp_pdev
  4824. *
  4825. * Return: none
  4826. */
  4827. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4828. uint32_t length, uint8_t tx_status,
  4829. bool update)
  4830. {
  4831. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4832. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4833. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4834. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4835. }
  4836. }
  4837. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4838. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4839. uint32_t length, uint8_t tx_status,
  4840. bool update)
  4841. {
  4842. if (!txrx_peer->hw_txrx_stats_en) {
  4843. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4844. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4845. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4846. }
  4847. }
  4848. #else
  4849. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4850. uint32_t length, uint8_t tx_status,
  4851. bool update)
  4852. {
  4853. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4854. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4855. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4856. }
  4857. #endif
  4858. /*
  4859. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4860. * @nbuf: skb buffer
  4861. *
  4862. * Return: none
  4863. */
  4864. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4865. static inline
  4866. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4867. {
  4868. qdf_nbuf_t nbuf = NULL;
  4869. if (next)
  4870. nbuf = next->nbuf;
  4871. if (nbuf)
  4872. qdf_prefetch(nbuf);
  4873. }
  4874. #else
  4875. static inline
  4876. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4877. {
  4878. }
  4879. #endif
  4880. /**
  4881. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4882. * @soc: core txrx main context
  4883. * @desc: software descriptor
  4884. *
  4885. * Return: true when packet is reinjected
  4886. */
  4887. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4888. defined(WLAN_MCAST_MLO)
  4889. static inline bool
  4890. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4891. {
  4892. struct dp_vdev *vdev = NULL;
  4893. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4894. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4895. !soc->arch_ops.dp_tx_is_mcast_primary)
  4896. return false;
  4897. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4898. DP_MOD_ID_REINJECT);
  4899. if (qdf_unlikely(!vdev)) {
  4900. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4901. desc->id);
  4902. return false;
  4903. }
  4904. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4905. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4906. return false;
  4907. }
  4908. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4909. qdf_nbuf_len(desc->nbuf));
  4910. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4911. dp_tx_desc_release(desc, desc->pool_id);
  4912. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4913. return true;
  4914. }
  4915. return false;
  4916. }
  4917. #else
  4918. static inline bool
  4919. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4920. {
  4921. return false;
  4922. }
  4923. #endif
  4924. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4925. static inline void
  4926. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4927. {
  4928. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4929. }
  4930. static inline void
  4931. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4932. struct dp_tx_desc_s *desc)
  4933. {
  4934. qdf_nbuf_t nbuf = NULL;
  4935. nbuf = desc->nbuf;
  4936. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4937. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4938. else
  4939. qdf_nbuf_free(nbuf);
  4940. }
  4941. static inline void
  4942. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4943. {
  4944. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4945. }
  4946. #else
  4947. static inline void
  4948. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4949. {
  4950. }
  4951. static inline void
  4952. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4953. struct dp_tx_desc_s *desc)
  4954. {
  4955. qdf_nbuf_free(desc->nbuf);
  4956. }
  4957. static inline void
  4958. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4959. {
  4960. }
  4961. #endif
  4962. /**
  4963. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4964. * @soc: core txrx main context
  4965. * @comp_head: software descriptor head pointer
  4966. * @ring_id: ring number
  4967. *
  4968. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4969. * and release the software descriptors after processing is complete
  4970. *
  4971. * Return: none
  4972. */
  4973. void
  4974. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4975. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4976. {
  4977. struct dp_tx_desc_s *desc;
  4978. struct dp_tx_desc_s *next;
  4979. struct hal_tx_completion_status ts;
  4980. struct dp_txrx_peer *txrx_peer = NULL;
  4981. uint16_t peer_id = DP_INVALID_PEER;
  4982. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4983. qdf_nbuf_queue_head_t h;
  4984. desc = comp_head;
  4985. dp_tx_nbuf_queue_head_init(&h);
  4986. while (desc) {
  4987. next = desc->next;
  4988. dp_tx_prefetch_next_nbuf_data(next);
  4989. if (peer_id != desc->peer_id) {
  4990. if (txrx_peer)
  4991. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4992. DP_MOD_ID_TX_COMP);
  4993. peer_id = desc->peer_id;
  4994. txrx_peer =
  4995. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4996. &txrx_ref_handle,
  4997. DP_MOD_ID_TX_COMP);
  4998. }
  4999. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  5000. desc = next;
  5001. continue;
  5002. }
  5003. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  5004. if (qdf_likely(txrx_peer))
  5005. dp_tx_update_peer_basic_stats(txrx_peer,
  5006. desc->length,
  5007. desc->tx_status,
  5008. false);
  5009. dp_tx_nbuf_dev_queue_free(&h, desc);
  5010. dp_ppeds_tx_desc_free(soc, desc);
  5011. desc = next;
  5012. continue;
  5013. }
  5014. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  5015. struct dp_pdev *pdev = desc->pdev;
  5016. if (qdf_likely(txrx_peer))
  5017. dp_tx_update_peer_basic_stats(txrx_peer,
  5018. desc->length,
  5019. desc->tx_status,
  5020. false);
  5021. qdf_assert(pdev);
  5022. dp_tx_outstanding_dec(pdev);
  5023. /*
  5024. * Calling a QDF WRAPPER here is creating significant
  5025. * performance impact so avoided the wrapper call here
  5026. */
  5027. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  5028. desc->id, DP_TX_COMP_UNMAP);
  5029. dp_tx_nbuf_unmap(soc, desc);
  5030. dp_tx_nbuf_dev_queue_free(&h, desc);
  5031. dp_tx_desc_free(soc, desc, desc->pool_id);
  5032. desc = next;
  5033. continue;
  5034. }
  5035. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  5036. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  5037. ring_id);
  5038. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  5039. dp_tx_desc_release(desc, desc->pool_id);
  5040. desc = next;
  5041. }
  5042. dp_tx_nbuf_dev_kfree_list(&h);
  5043. if (txrx_peer)
  5044. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  5045. }
  5046. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  5047. static inline
  5048. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5049. int max_reap_limit)
  5050. {
  5051. bool limit_hit = false;
  5052. limit_hit =
  5053. (num_reaped >= max_reap_limit) ? true : false;
  5054. if (limit_hit)
  5055. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  5056. return limit_hit;
  5057. }
  5058. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5059. {
  5060. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  5061. }
  5062. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5063. {
  5064. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  5065. return cfg->tx_comp_loop_pkt_limit;
  5066. }
  5067. #else
  5068. static inline
  5069. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5070. int max_reap_limit)
  5071. {
  5072. return false;
  5073. }
  5074. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5075. {
  5076. return false;
  5077. }
  5078. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5079. {
  5080. return 0;
  5081. }
  5082. #endif
  5083. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  5084. static inline int
  5085. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5086. int *max_reap_limit)
  5087. {
  5088. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  5089. max_reap_limit);
  5090. }
  5091. #else
  5092. static inline int
  5093. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5094. int *max_reap_limit)
  5095. {
  5096. return 0;
  5097. }
  5098. #endif
  5099. #ifdef DP_TX_TRACKING
  5100. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  5101. {
  5102. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  5103. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  5104. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  5105. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  5106. }
  5107. }
  5108. #endif
  5109. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  5110. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  5111. uint32_t quota)
  5112. {
  5113. void *tx_comp_hal_desc;
  5114. void *last_prefetched_hw_desc = NULL;
  5115. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  5116. hal_soc_handle_t hal_soc;
  5117. uint8_t buffer_src;
  5118. struct dp_tx_desc_s *tx_desc = NULL;
  5119. struct dp_tx_desc_s *head_desc = NULL;
  5120. struct dp_tx_desc_s *tail_desc = NULL;
  5121. uint32_t num_processed = 0;
  5122. uint32_t count;
  5123. uint32_t num_avail_for_reap = 0;
  5124. bool force_break = false;
  5125. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  5126. int max_reap_limit, ring_near_full;
  5127. uint32_t num_entries;
  5128. DP_HIST_INIT();
  5129. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  5130. more_data:
  5131. hal_soc = soc->hal_soc;
  5132. /* Re-initialize local variables to be re-used */
  5133. head_desc = NULL;
  5134. tail_desc = NULL;
  5135. count = 0;
  5136. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  5137. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  5138. &max_reap_limit);
  5139. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  5140. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5141. return 0;
  5142. }
  5143. if (!num_avail_for_reap)
  5144. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5145. hal_ring_hdl, 0);
  5146. if (num_avail_for_reap >= quota)
  5147. num_avail_for_reap = quota;
  5148. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5149. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5150. hal_ring_hdl,
  5151. num_avail_for_reap);
  5152. /* Find head descriptor from completion ring */
  5153. while (qdf_likely(num_avail_for_reap--)) {
  5154. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5155. if (qdf_unlikely(!tx_comp_hal_desc))
  5156. break;
  5157. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5158. tx_comp_hal_desc);
  5159. /* If this buffer was not released by TQM or FW, then it is not
  5160. * Tx completion indication, assert */
  5161. if (qdf_unlikely(buffer_src !=
  5162. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5163. (qdf_unlikely(buffer_src !=
  5164. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5165. uint8_t wbm_internal_error;
  5166. dp_err_rl(
  5167. "Tx comp release_src != TQM | FW but from %d",
  5168. buffer_src);
  5169. hal_dump_comp_desc(tx_comp_hal_desc);
  5170. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5171. /* When WBM sees NULL buffer_addr_info in any of
  5172. * ingress rings it sends an error indication,
  5173. * with wbm_internal_error=1, to a specific ring.
  5174. * The WBM2SW ring used to indicate these errors is
  5175. * fixed in HW, and that ring is being used as Tx
  5176. * completion ring. These errors are not related to
  5177. * Tx completions, and should just be ignored
  5178. */
  5179. wbm_internal_error = hal_get_wbm_internal_error(
  5180. hal_soc,
  5181. tx_comp_hal_desc);
  5182. if (wbm_internal_error) {
  5183. dp_err_rl("Tx comp wbm_internal_error!!");
  5184. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5185. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5186. buffer_src)
  5187. dp_handle_wbm_internal_error(
  5188. soc,
  5189. tx_comp_hal_desc,
  5190. hal_tx_comp_get_buffer_type(
  5191. tx_comp_hal_desc));
  5192. } else {
  5193. dp_err_rl("Tx comp wbm_internal_error false");
  5194. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5195. }
  5196. continue;
  5197. }
  5198. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5199. tx_comp_hal_desc,
  5200. &tx_desc);
  5201. if (qdf_unlikely(!tx_desc)) {
  5202. dp_err("unable to retrieve tx_desc!");
  5203. hal_dump_comp_desc(tx_comp_hal_desc);
  5204. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5205. QDF_BUG(0);
  5206. continue;
  5207. }
  5208. tx_desc->buffer_src = buffer_src;
  5209. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5210. goto add_to_pool2;
  5211. /*
  5212. * If the release source is FW, process the HTT status
  5213. */
  5214. if (qdf_unlikely(buffer_src ==
  5215. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5216. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5217. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5218. htt_tx_status);
  5219. /* Collect hw completion contents */
  5220. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5221. &tx_desc->comp, 1);
  5222. soc->arch_ops.dp_tx_process_htt_completion(
  5223. soc,
  5224. tx_desc,
  5225. htt_tx_status,
  5226. ring_id);
  5227. } else {
  5228. tx_desc->tx_status =
  5229. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5230. tx_desc->buffer_src = buffer_src;
  5231. /*
  5232. * If the fast completion mode is enabled extended
  5233. * metadata from descriptor is not copied
  5234. */
  5235. if (qdf_likely(tx_desc->flags &
  5236. DP_TX_DESC_FLAG_SIMPLE))
  5237. goto add_to_pool;
  5238. /*
  5239. * If the descriptor is already freed in vdev_detach,
  5240. * continue to next descriptor
  5241. */
  5242. if (qdf_unlikely
  5243. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5244. !tx_desc->flags)) {
  5245. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5246. tx_desc->id);
  5247. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5248. dp_tx_desc_check_corruption(tx_desc);
  5249. continue;
  5250. }
  5251. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5252. dp_tx_comp_info_rl("pdev in down state %d",
  5253. tx_desc->id);
  5254. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5255. dp_tx_comp_free_buf(soc, tx_desc, false);
  5256. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5257. goto next_desc;
  5258. }
  5259. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5260. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5261. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5262. tx_desc->flags, tx_desc->id);
  5263. qdf_assert_always(0);
  5264. }
  5265. /* Collect hw completion contents */
  5266. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5267. &tx_desc->comp, 1);
  5268. add_to_pool:
  5269. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5270. add_to_pool2:
  5271. /* First ring descriptor on the cycle */
  5272. if (!head_desc) {
  5273. head_desc = tx_desc;
  5274. tail_desc = tx_desc;
  5275. }
  5276. tail_desc->next = tx_desc;
  5277. tx_desc->next = NULL;
  5278. tail_desc = tx_desc;
  5279. }
  5280. next_desc:
  5281. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5282. /*
  5283. * Processed packet count is more than given quota
  5284. * stop to processing
  5285. */
  5286. count++;
  5287. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5288. num_avail_for_reap,
  5289. hal_ring_hdl,
  5290. &last_prefetched_hw_desc,
  5291. &last_prefetched_sw_desc);
  5292. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5293. break;
  5294. }
  5295. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5296. /* Process the reaped descriptors */
  5297. if (head_desc)
  5298. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5299. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5300. /*
  5301. * If we are processing in near-full condition, there are 3 scenario
  5302. * 1) Ring entries has reached critical state
  5303. * 2) Ring entries are still near high threshold
  5304. * 3) Ring entries are below the safe level
  5305. *
  5306. * One more loop will move the state to normal processing and yield
  5307. */
  5308. if (ring_near_full)
  5309. goto more_data;
  5310. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5311. if (num_processed >= quota)
  5312. force_break = true;
  5313. if (!force_break &&
  5314. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5315. hal_ring_hdl)) {
  5316. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5317. if (!hif_exec_should_yield(soc->hif_handle,
  5318. int_ctx->dp_intr_id))
  5319. goto more_data;
  5320. num_avail_for_reap =
  5321. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5322. hal_ring_hdl,
  5323. true);
  5324. if (qdf_unlikely(num_entries &&
  5325. (num_avail_for_reap >=
  5326. num_entries >> 1))) {
  5327. DP_STATS_INC(soc, tx.near_full, 1);
  5328. goto more_data;
  5329. }
  5330. }
  5331. }
  5332. DP_TX_HIST_STATS_PER_PDEV();
  5333. return num_processed;
  5334. }
  5335. #ifdef FEATURE_WLAN_TDLS
  5336. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5337. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5338. {
  5339. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5340. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5341. DP_MOD_ID_TDLS);
  5342. if (!vdev) {
  5343. dp_err("vdev handle for id %d is NULL", vdev_id);
  5344. return NULL;
  5345. }
  5346. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5347. vdev->is_tdls_frame = true;
  5348. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5349. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5350. }
  5351. #endif
  5352. /**
  5353. * dp_tx_vdev_attach() - attach vdev to dp tx
  5354. * @vdev: virtual device instance
  5355. *
  5356. * Return: QDF_STATUS_SUCCESS: success
  5357. * QDF_STATUS_E_RESOURCES: Error return
  5358. */
  5359. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5360. {
  5361. int pdev_id;
  5362. /*
  5363. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5364. */
  5365. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5366. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5367. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5368. vdev->vdev_id);
  5369. pdev_id =
  5370. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5371. vdev->pdev->pdev_id);
  5372. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5373. /*
  5374. * Set HTT Extension Valid bit to 0 by default
  5375. */
  5376. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5377. dp_tx_vdev_update_search_flags(vdev);
  5378. return QDF_STATUS_SUCCESS;
  5379. }
  5380. #ifndef FEATURE_WDS
  5381. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5382. {
  5383. return false;
  5384. }
  5385. #endif
  5386. /**
  5387. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5388. * @vdev: virtual device instance
  5389. *
  5390. * Return: void
  5391. *
  5392. */
  5393. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5394. {
  5395. struct dp_soc *soc = vdev->pdev->soc;
  5396. /*
  5397. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5398. * for TDLS link
  5399. *
  5400. * Enable AddrY (SA based search) only for non-WDS STA and
  5401. * ProxySTA VAP (in HKv1) modes.
  5402. *
  5403. * In all other VAP modes, only DA based search should be
  5404. * enabled
  5405. */
  5406. if (vdev->opmode == wlan_op_mode_sta &&
  5407. vdev->tdls_link_connected)
  5408. vdev->hal_desc_addr_search_flags =
  5409. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5410. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5411. !dp_tx_da_search_override(vdev))
  5412. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5413. else
  5414. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5415. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5416. vdev->search_type = soc->sta_mode_search_policy;
  5417. else
  5418. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5419. }
  5420. static inline bool
  5421. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5422. struct dp_vdev *vdev,
  5423. struct dp_tx_desc_s *tx_desc)
  5424. {
  5425. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5426. return false;
  5427. /*
  5428. * if vdev is given, then only check whether desc
  5429. * vdev match. if vdev is NULL, then check whether
  5430. * desc pdev match.
  5431. */
  5432. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5433. (tx_desc->pdev == pdev);
  5434. }
  5435. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5436. /**
  5437. * dp_tx_desc_flush() - release resources associated
  5438. * to TX Desc
  5439. *
  5440. * @dp_pdev: Handle to DP pdev structure
  5441. * @vdev: virtual device instance
  5442. * NULL: no specific Vdev is required and check all allcated TX desc
  5443. * on this pdev.
  5444. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5445. *
  5446. * @force_free:
  5447. * true: flush the TX desc.
  5448. * false: only reset the Vdev in each allocated TX desc
  5449. * that associated to current Vdev.
  5450. *
  5451. * This function will go through the TX desc pool to flush
  5452. * the outstanding TX data or reset Vdev to NULL in associated TX
  5453. * Desc.
  5454. */
  5455. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5456. bool force_free)
  5457. {
  5458. uint8_t i;
  5459. uint32_t j;
  5460. uint32_t num_desc, page_id, offset;
  5461. uint16_t num_desc_per_page;
  5462. struct dp_soc *soc = pdev->soc;
  5463. struct dp_tx_desc_s *tx_desc = NULL;
  5464. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5465. if (!vdev && !force_free) {
  5466. dp_err("Reset TX desc vdev, Vdev param is required!");
  5467. return;
  5468. }
  5469. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5470. tx_desc_pool = &soc->tx_desc[i];
  5471. if (!(tx_desc_pool->pool_size) ||
  5472. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5473. !(tx_desc_pool->desc_pages.cacheable_pages))
  5474. continue;
  5475. /*
  5476. * Add flow pool lock protection in case pool is freed
  5477. * due to all tx_desc is recycled when handle TX completion.
  5478. * this is not necessary when do force flush as:
  5479. * a. double lock will happen if dp_tx_desc_release is
  5480. * also trying to acquire it.
  5481. * b. dp interrupt has been disabled before do force TX desc
  5482. * flush in dp_pdev_deinit().
  5483. */
  5484. if (!force_free)
  5485. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5486. num_desc = tx_desc_pool->pool_size;
  5487. num_desc_per_page =
  5488. tx_desc_pool->desc_pages.num_element_per_page;
  5489. for (j = 0; j < num_desc; j++) {
  5490. page_id = j / num_desc_per_page;
  5491. offset = j % num_desc_per_page;
  5492. if (qdf_unlikely(!(tx_desc_pool->
  5493. desc_pages.cacheable_pages)))
  5494. break;
  5495. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5496. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5497. /*
  5498. * Free TX desc if force free is
  5499. * required, otherwise only reset vdev
  5500. * in this TX desc.
  5501. */
  5502. if (force_free) {
  5503. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5504. dp_tx_comp_free_buf(soc, tx_desc,
  5505. false);
  5506. dp_tx_desc_release(tx_desc, i);
  5507. } else {
  5508. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5509. }
  5510. }
  5511. }
  5512. if (!force_free)
  5513. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5514. }
  5515. }
  5516. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5517. /**
  5518. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5519. *
  5520. * @soc: Handle to DP soc structure
  5521. * @tx_desc: pointer of one TX desc
  5522. * @desc_pool_id: TX Desc pool id
  5523. */
  5524. static inline void
  5525. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5526. uint8_t desc_pool_id)
  5527. {
  5528. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5529. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5530. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5531. }
  5532. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5533. bool force_free)
  5534. {
  5535. uint8_t i, num_pool;
  5536. uint32_t j;
  5537. uint32_t num_desc, page_id, offset;
  5538. uint16_t num_desc_per_page;
  5539. struct dp_soc *soc = pdev->soc;
  5540. struct dp_tx_desc_s *tx_desc = NULL;
  5541. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5542. if (!vdev && !force_free) {
  5543. dp_err("Reset TX desc vdev, Vdev param is required!");
  5544. return;
  5545. }
  5546. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5547. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5548. for (i = 0; i < num_pool; i++) {
  5549. tx_desc_pool = &soc->tx_desc[i];
  5550. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5551. continue;
  5552. num_desc_per_page =
  5553. tx_desc_pool->desc_pages.num_element_per_page;
  5554. for (j = 0; j < num_desc; j++) {
  5555. page_id = j / num_desc_per_page;
  5556. offset = j % num_desc_per_page;
  5557. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5558. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5559. if (force_free) {
  5560. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5561. dp_tx_comp_free_buf(soc, tx_desc,
  5562. false);
  5563. dp_tx_desc_release(tx_desc, i);
  5564. } else {
  5565. dp_tx_desc_reset_vdev(soc, tx_desc,
  5566. i);
  5567. }
  5568. }
  5569. }
  5570. }
  5571. }
  5572. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5573. /**
  5574. * dp_tx_vdev_detach() - detach vdev from dp tx
  5575. * @vdev: virtual device instance
  5576. *
  5577. * Return: QDF_STATUS_SUCCESS: success
  5578. * QDF_STATUS_E_RESOURCES: Error return
  5579. */
  5580. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5581. {
  5582. struct dp_pdev *pdev = vdev->pdev;
  5583. /* Reset TX desc associated to this Vdev as NULL */
  5584. dp_tx_desc_flush(pdev, vdev, false);
  5585. return QDF_STATUS_SUCCESS;
  5586. }
  5587. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5588. /* Pools will be allocated dynamically */
  5589. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5590. int num_desc)
  5591. {
  5592. uint8_t i;
  5593. for (i = 0; i < num_pool; i++) {
  5594. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5595. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5596. }
  5597. return QDF_STATUS_SUCCESS;
  5598. }
  5599. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5600. uint32_t num_desc)
  5601. {
  5602. return QDF_STATUS_SUCCESS;
  5603. }
  5604. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5605. {
  5606. }
  5607. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5608. {
  5609. uint8_t i;
  5610. for (i = 0; i < num_pool; i++)
  5611. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5612. }
  5613. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5614. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5615. uint32_t num_desc)
  5616. {
  5617. uint8_t i, count;
  5618. /* Allocate software Tx descriptor pools */
  5619. for (i = 0; i < num_pool; i++) {
  5620. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5622. FL("Tx Desc Pool alloc %d failed %pK"),
  5623. i, soc);
  5624. goto fail;
  5625. }
  5626. }
  5627. return QDF_STATUS_SUCCESS;
  5628. fail:
  5629. for (count = 0; count < i; count++)
  5630. dp_tx_desc_pool_free(soc, count);
  5631. return QDF_STATUS_E_NOMEM;
  5632. }
  5633. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5634. uint32_t num_desc)
  5635. {
  5636. uint8_t i;
  5637. for (i = 0; i < num_pool; i++) {
  5638. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5639. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5640. FL("Tx Desc Pool init %d failed %pK"),
  5641. i, soc);
  5642. return QDF_STATUS_E_NOMEM;
  5643. }
  5644. }
  5645. return QDF_STATUS_SUCCESS;
  5646. }
  5647. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5648. {
  5649. uint8_t i;
  5650. for (i = 0; i < num_pool; i++)
  5651. dp_tx_desc_pool_deinit(soc, i);
  5652. }
  5653. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5654. {
  5655. uint8_t i;
  5656. for (i = 0; i < num_pool; i++)
  5657. dp_tx_desc_pool_free(soc, i);
  5658. }
  5659. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5660. /**
  5661. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5662. * @soc: core txrx main context
  5663. * @num_pool: number of pools
  5664. *
  5665. */
  5666. static void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5667. {
  5668. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5669. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5670. }
  5671. /**
  5672. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5673. * @soc: core txrx main context
  5674. * @num_pool: number of pools
  5675. *
  5676. */
  5677. static void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5678. {
  5679. dp_tx_tso_desc_pool_free(soc, num_pool);
  5680. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5681. }
  5682. /**
  5683. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5684. * @soc: core txrx main context
  5685. *
  5686. * This function frees all tx related descriptors as below
  5687. * 1. Regular TX descriptors (static pools)
  5688. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5689. * 3. TSO descriptors
  5690. *
  5691. */
  5692. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5693. {
  5694. uint8_t num_pool;
  5695. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5696. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5697. dp_tx_ext_desc_pool_free(soc, num_pool);
  5698. dp_tx_delete_static_pools(soc, num_pool);
  5699. }
  5700. /**
  5701. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5702. * @soc: core txrx main context
  5703. *
  5704. * This function de-initializes all tx related descriptors as below
  5705. * 1. Regular TX descriptors (static pools)
  5706. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5707. * 3. TSO descriptors
  5708. *
  5709. */
  5710. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5711. {
  5712. uint8_t num_pool;
  5713. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5714. dp_tx_flow_control_deinit(soc);
  5715. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5716. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5717. dp_tx_deinit_static_pools(soc, num_pool);
  5718. }
  5719. /**
  5720. * dp_tx_tso_cmn_desc_pool_alloc() - TSO cmn desc pool allocator
  5721. * @soc: DP soc handle
  5722. * @num_pool: Number of pools
  5723. * @num_desc: Number of descriptors
  5724. *
  5725. * Reserve TSO descriptor buffers
  5726. *
  5727. * Return: QDF_STATUS_E_FAILURE on failure or
  5728. * QDF_STATUS_SUCCESS on success
  5729. */
  5730. static QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5731. uint8_t num_pool,
  5732. uint32_t num_desc)
  5733. {
  5734. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5735. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5736. return QDF_STATUS_E_FAILURE;
  5737. }
  5738. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5739. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5740. num_pool, soc);
  5741. return QDF_STATUS_E_FAILURE;
  5742. }
  5743. return QDF_STATUS_SUCCESS;
  5744. }
  5745. /**
  5746. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5747. * @soc: DP soc handle
  5748. * @num_pool: Number of pools
  5749. * @num_desc: Number of descriptors
  5750. *
  5751. * Initialize TSO descriptor pools
  5752. *
  5753. * Return: QDF_STATUS_E_FAILURE on failure or
  5754. * QDF_STATUS_SUCCESS on success
  5755. */
  5756. static QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5757. uint8_t num_pool,
  5758. uint32_t num_desc)
  5759. {
  5760. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5761. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5762. return QDF_STATUS_E_FAILURE;
  5763. }
  5764. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5765. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5766. num_pool, soc);
  5767. return QDF_STATUS_E_FAILURE;
  5768. }
  5769. return QDF_STATUS_SUCCESS;
  5770. }
  5771. /**
  5772. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5773. * @soc: core txrx main context
  5774. *
  5775. * This function allocates memory for following descriptor pools
  5776. * 1. regular sw tx descriptor pools (static pools)
  5777. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5778. * 3. TSO descriptor pools
  5779. *
  5780. * Return: QDF_STATUS_SUCCESS: success
  5781. * QDF_STATUS_E_RESOURCES: Error return
  5782. */
  5783. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5784. {
  5785. uint8_t num_pool;
  5786. uint32_t num_desc;
  5787. uint32_t num_ext_desc;
  5788. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5789. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5790. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5791. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5792. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5793. __func__, num_pool, num_desc);
  5794. if ((num_pool > MAX_TXDESC_POOLS) ||
  5795. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5796. goto fail1;
  5797. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5798. goto fail1;
  5799. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5800. goto fail2;
  5801. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5802. return QDF_STATUS_SUCCESS;
  5803. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5804. goto fail3;
  5805. return QDF_STATUS_SUCCESS;
  5806. fail3:
  5807. dp_tx_ext_desc_pool_free(soc, num_pool);
  5808. fail2:
  5809. dp_tx_delete_static_pools(soc, num_pool);
  5810. fail1:
  5811. return QDF_STATUS_E_RESOURCES;
  5812. }
  5813. /**
  5814. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5815. * @soc: core txrx main context
  5816. *
  5817. * This function initializes the following TX descriptor pools
  5818. * 1. regular sw tx descriptor pools (static pools)
  5819. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5820. * 3. TSO descriptor pools
  5821. *
  5822. * Return: QDF_STATUS_SUCCESS: success
  5823. * QDF_STATUS_E_RESOURCES: Error return
  5824. */
  5825. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5826. {
  5827. uint8_t num_pool;
  5828. uint32_t num_desc;
  5829. uint32_t num_ext_desc;
  5830. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5831. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5832. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5833. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5834. goto fail1;
  5835. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5836. goto fail2;
  5837. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5838. return QDF_STATUS_SUCCESS;
  5839. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5840. goto fail3;
  5841. dp_tx_flow_control_init(soc);
  5842. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5843. return QDF_STATUS_SUCCESS;
  5844. fail3:
  5845. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5846. fail2:
  5847. dp_tx_deinit_static_pools(soc, num_pool);
  5848. fail1:
  5849. return QDF_STATUS_E_RESOURCES;
  5850. }
  5851. /**
  5852. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5853. * @txrx_soc: dp soc handle
  5854. *
  5855. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5856. * QDF_STATUS_E_FAILURE
  5857. */
  5858. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5859. {
  5860. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5861. uint8_t num_pool;
  5862. uint32_t num_ext_desc;
  5863. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5864. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5865. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5866. return QDF_STATUS_E_FAILURE;
  5867. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5868. return QDF_STATUS_E_FAILURE;
  5869. return QDF_STATUS_SUCCESS;
  5870. }
  5871. /**
  5872. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5873. * @txrx_soc: dp soc handle
  5874. *
  5875. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5876. */
  5877. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5878. {
  5879. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5880. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5881. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5882. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5883. return QDF_STATUS_SUCCESS;
  5884. }
  5885. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5886. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5887. enum qdf_pkt_timestamp_index index, uint64_t time,
  5888. qdf_nbuf_t nbuf)
  5889. {
  5890. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5891. uint64_t tsf_time;
  5892. if (vdev->get_tsf_time) {
  5893. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5894. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5895. }
  5896. }
  5897. }
  5898. void dp_pkt_get_timestamp(uint64_t *time)
  5899. {
  5900. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5901. *time = qdf_get_log_timestamp();
  5902. }
  5903. #endif