qcs405.c 213 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #include "codecs/csra66x0/csra66x0.h"
  38. #include <dt-bindings/sound/audio-codec-port-types.h>
  39. #define DRV_NAME "qcs405-asoc-snd"
  40. #define __CHIPSET__ "QCS405 "
  41. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  42. #define DEV_NAME_STR_LEN 32
  43. #define SAMPLING_RATE_8KHZ 8000
  44. #define SAMPLING_RATE_11P025KHZ 11025
  45. #define SAMPLING_RATE_16KHZ 16000
  46. #define SAMPLING_RATE_22P05KHZ 22050
  47. #define SAMPLING_RATE_32KHZ 32000
  48. #define SAMPLING_RATE_44P1KHZ 44100
  49. #define SAMPLING_RATE_48KHZ 48000
  50. #define SAMPLING_RATE_88P2KHZ 88200
  51. #define SAMPLING_RATE_96KHZ 96000
  52. #define SAMPLING_RATE_176P4KHZ 176400
  53. #define SAMPLING_RATE_192KHZ 192000
  54. #define SAMPLING_RATE_352P8KHZ 352800
  55. #define SAMPLING_RATE_384KHZ 384000
  56. #define WSA8810_NAME_1 "wsa881x.20170211"
  57. #define WSA8810_NAME_2 "wsa881x.20170212"
  58. #define WCN_CDC_SLIM_RX_CH_MAX 2
  59. #define WCN_CDC_SLIM_TX_CH_MAX 3
  60. #define TDM_CHANNEL_MAX 8
  61. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. enum {
  64. SLIM_RX_0 = 0,
  65. SLIM_RX_1,
  66. SLIM_RX_2,
  67. SLIM_RX_3,
  68. SLIM_RX_4,
  69. SLIM_RX_5,
  70. SLIM_RX_6,
  71. SLIM_RX_7,
  72. SLIM_RX_MAX,
  73. };
  74. enum {
  75. SLIM_TX_0 = 0,
  76. SLIM_TX_1,
  77. SLIM_TX_2,
  78. SLIM_TX_3,
  79. SLIM_TX_4,
  80. SLIM_TX_5,
  81. SLIM_TX_6,
  82. SLIM_TX_7,
  83. SLIM_TX_8,
  84. SLIM_TX_MAX,
  85. };
  86. enum {
  87. PRIM_MI2S = 0,
  88. SEC_MI2S,
  89. TERT_MI2S,
  90. QUAT_MI2S,
  91. QUIN_MI2S,
  92. MI2S_MAX,
  93. };
  94. enum {
  95. PRIM_AUX_PCM = 0,
  96. SEC_AUX_PCM,
  97. TERT_AUX_PCM,
  98. QUAT_AUX_PCM,
  99. QUIN_AUX_PCM,
  100. AUX_PCM_MAX,
  101. };
  102. enum {
  103. WSA_CDC_DMA_RX_0 = 0,
  104. WSA_CDC_DMA_RX_1,
  105. CDC_DMA_RX_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_TX_0 = 0,
  109. WSA_CDC_DMA_TX_1,
  110. WSA_CDC_DMA_TX_2,
  111. VA_CDC_DMA_TX_0,
  112. VA_CDC_DMA_TX_1,
  113. CDC_DMA_TX_MAX,
  114. };
  115. struct mi2s_conf {
  116. struct mutex lock;
  117. u32 ref_cnt;
  118. u32 msm_is_mi2s_master;
  119. };
  120. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  121. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  122. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  123. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  124. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  125. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  126. };
  127. struct dev_config {
  128. u32 sample_rate;
  129. u32 bit_format;
  130. u32 channels;
  131. };
  132. struct msm_wsa881x_dev_info {
  133. struct device_node *of_node;
  134. u32 index;
  135. };
  136. struct msm_csra66x0_dev_info {
  137. struct device_node *of_node;
  138. u32 index;
  139. };
  140. enum pinctrl_pin_state {
  141. STATE_DISABLE = 0, /* All pins are in sleep state */
  142. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  143. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  144. };
  145. struct msm_pinctrl_info {
  146. struct pinctrl *pinctrl;
  147. struct pinctrl_state *mi2s_disable;
  148. struct pinctrl_state *tdm_disable;
  149. struct pinctrl_state *mi2s_active;
  150. struct pinctrl_state *tdm_active;
  151. enum pinctrl_pin_state curr_state;
  152. };
  153. struct msm_asoc_mach_data {
  154. struct snd_info_entry *codec_root;
  155. struct msm_pinctrl_info pinctrl_info;
  156. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  157. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  158. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  160. int dmic_01_gpio_cnt;
  161. int dmic_23_gpio_cnt;
  162. int dmic_45_gpio_cnt;
  163. int dmic_67_gpio_cnt;
  164. };
  165. struct msm_asoc_wcd93xx_codec {
  166. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  167. enum afe_config_type config_type);
  168. };
  169. static const char *const pin_states[] = {"sleep", "i2s-active",
  170. "tdm-active"};
  171. enum {
  172. TDM_0 = 0,
  173. TDM_1,
  174. TDM_2,
  175. TDM_3,
  176. TDM_4,
  177. TDM_5,
  178. TDM_6,
  179. TDM_7,
  180. TDM_PORT_MAX,
  181. };
  182. enum {
  183. TDM_PRI = 0,
  184. TDM_SEC,
  185. TDM_TERT,
  186. TDM_QUAT,
  187. TDM_QUIN,
  188. TDM_INTERFACE_MAX,
  189. };
  190. struct tdm_port {
  191. u32 mode;
  192. u32 channel;
  193. };
  194. /* TDM default config */
  195. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  196. { /* PRI TDM */
  197. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  198. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  199. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  200. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  201. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  205. },
  206. { /* SEC TDM */
  207. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  208. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  215. },
  216. { /* TERT TDM */
  217. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  218. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  225. },
  226. { /* QUAT TDM */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  235. },
  236. { /* QUIN TDM */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  245. }
  246. };
  247. /* TDM default config */
  248. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  249. { /* PRI TDM */
  250. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  258. },
  259. { /* SEC TDM */
  260. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  268. },
  269. { /* TERT TDM */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  278. },
  279. { /* QUAT TDM */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  288. },
  289. { /* QUIN TDM */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  298. }
  299. };
  300. /* Default configuration of slimbus channels */
  301. static struct dev_config slim_rx_cfg[] = {
  302. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  303. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  304. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  305. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  306. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  307. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. };
  311. static struct dev_config slim_tx_cfg[] = {
  312. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  313. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  314. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  321. };
  322. /* Default configuration of Codec DMA Interface Tx */
  323. static struct dev_config cdc_dma_rx_cfg[] = {
  324. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  325. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. };
  327. /* Default configuration of Codec DMA Interface Rx */
  328. static struct dev_config cdc_dma_tx_cfg[] = {
  329. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  330. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  331. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  333. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  334. };
  335. static struct dev_config usb_rx_cfg = {
  336. .sample_rate = SAMPLING_RATE_48KHZ,
  337. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  338. .channels = 2,
  339. };
  340. static struct dev_config usb_tx_cfg = {
  341. .sample_rate = SAMPLING_RATE_48KHZ,
  342. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  343. .channels = 1,
  344. };
  345. static struct dev_config proxy_rx_cfg = {
  346. .sample_rate = SAMPLING_RATE_48KHZ,
  347. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  348. .channels = 2,
  349. };
  350. /* Default configuration of MI2S channels */
  351. static struct dev_config mi2s_rx_cfg[] = {
  352. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  353. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  354. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  355. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  356. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  357. };
  358. static struct dev_config mi2s_tx_cfg[] = {
  359. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  360. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  361. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  362. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. };
  365. static struct dev_config aux_pcm_rx_cfg[] = {
  366. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  367. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  368. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  369. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. };
  372. static struct dev_config aux_pcm_tx_cfg[] = {
  373. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  374. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  375. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  376. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. };
  379. static int msm_vi_feed_tx_ch = 2;
  380. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  381. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  382. "Five", "Six", "Seven",
  383. "Eight"};
  384. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  385. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  386. "S32_LE"};
  387. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  388. "KHZ_32", "KHZ_44P1", "KHZ_48",
  389. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  390. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  391. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  392. "KHZ_44P1", "KHZ_48",
  393. "KHZ_88P2", "KHZ_96"};
  394. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  395. "Five", "Six", "Seven",
  396. "Eight"};
  397. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  398. "Six", "Seven", "Eight"};
  399. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  400. "KHZ_16", "KHZ_22P05",
  401. "KHZ_32", "KHZ_44P1", "KHZ_48",
  402. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  403. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  404. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  405. "Five", "Six", "Seven", "Eight"};
  406. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  407. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  408. "KHZ_48", "KHZ_176P4",
  409. "KHZ_352P8"};
  410. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  411. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  412. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  413. "KHZ_48", "KHZ_96", "KHZ_192"};
  414. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  415. "Five", "Six", "Seven",
  416. "Eight"};
  417. static const char *const qos_text[] = {"Disable", "Enable"};
  418. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  419. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  420. "Five", "Six", "Seven",
  421. "Eight"};
  422. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  423. "KHZ_16", "KHZ_22P05",
  424. "KHZ_32", "KHZ_44P1", "KHZ_48",
  425. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  426. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  427. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  428. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  429. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  505. cdc_dma_sample_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  507. cdc_dma_sample_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  509. cdc_dma_sample_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  511. cdc_dma_sample_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  513. cdc_dma_sample_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  515. cdc_dma_sample_rate_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  517. cdc_dma_sample_rate_text);
  518. static struct platform_device *spdev;
  519. static bool is_initial_boot;
  520. static bool codec_reg_done;
  521. static struct snd_soc_aux_dev *msm_aux_dev;
  522. static struct snd_soc_codec_conf *msm_codec_conf;
  523. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  524. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  525. int enable, bool dapm);
  526. static int msm_wsa881x_init(struct snd_soc_component *component);
  527. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  528. struct snd_ctl_elem_value *ucontrol);
  529. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  530. {"MIC BIAS1", NULL, "MCLK TX"},
  531. {"MIC BIAS2", NULL, "MCLK TX"},
  532. {"MIC BIAS3", NULL, "MCLK TX"},
  533. {"MIC BIAS4", NULL, "MCLK TX"},
  534. };
  535. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  536. {
  537. AFE_API_VERSION_I2S_CONFIG,
  538. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  539. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  540. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  541. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  542. 0,
  543. },
  544. {
  545. AFE_API_VERSION_I2S_CONFIG,
  546. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  547. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  548. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  549. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  550. 0,
  551. },
  552. {
  553. AFE_API_VERSION_I2S_CONFIG,
  554. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  555. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  556. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  557. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  558. 0,
  559. },
  560. {
  561. AFE_API_VERSION_I2S_CONFIG,
  562. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  563. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  564. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  565. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  566. 0,
  567. },
  568. {
  569. AFE_API_VERSION_I2S_CONFIG,
  570. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  571. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  572. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  573. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  574. 0,
  575. }
  576. };
  577. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  578. static int slim_get_sample_rate_val(int sample_rate)
  579. {
  580. int sample_rate_val = 0;
  581. switch (sample_rate) {
  582. case SAMPLING_RATE_8KHZ:
  583. sample_rate_val = 0;
  584. break;
  585. case SAMPLING_RATE_16KHZ:
  586. sample_rate_val = 1;
  587. break;
  588. case SAMPLING_RATE_32KHZ:
  589. sample_rate_val = 2;
  590. break;
  591. case SAMPLING_RATE_44P1KHZ:
  592. sample_rate_val = 3;
  593. break;
  594. case SAMPLING_RATE_48KHZ:
  595. sample_rate_val = 4;
  596. break;
  597. case SAMPLING_RATE_88P2KHZ:
  598. sample_rate_val = 5;
  599. break;
  600. case SAMPLING_RATE_96KHZ:
  601. sample_rate_val = 6;
  602. break;
  603. case SAMPLING_RATE_176P4KHZ:
  604. sample_rate_val = 7;
  605. break;
  606. case SAMPLING_RATE_192KHZ:
  607. sample_rate_val = 8;
  608. break;
  609. case SAMPLING_RATE_352P8KHZ:
  610. sample_rate_val = 9;
  611. break;
  612. case SAMPLING_RATE_384KHZ:
  613. sample_rate_val = 10;
  614. break;
  615. default:
  616. sample_rate_val = 4;
  617. break;
  618. }
  619. return sample_rate_val;
  620. }
  621. static int slim_get_sample_rate(int value)
  622. {
  623. int sample_rate = 0;
  624. switch (value) {
  625. case 0:
  626. sample_rate = SAMPLING_RATE_8KHZ;
  627. break;
  628. case 1:
  629. sample_rate = SAMPLING_RATE_16KHZ;
  630. break;
  631. case 2:
  632. sample_rate = SAMPLING_RATE_32KHZ;
  633. break;
  634. case 3:
  635. sample_rate = SAMPLING_RATE_44P1KHZ;
  636. break;
  637. case 4:
  638. sample_rate = SAMPLING_RATE_48KHZ;
  639. break;
  640. case 5:
  641. sample_rate = SAMPLING_RATE_88P2KHZ;
  642. break;
  643. case 6:
  644. sample_rate = SAMPLING_RATE_96KHZ;
  645. break;
  646. case 7:
  647. sample_rate = SAMPLING_RATE_176P4KHZ;
  648. break;
  649. case 8:
  650. sample_rate = SAMPLING_RATE_192KHZ;
  651. break;
  652. case 9:
  653. sample_rate = SAMPLING_RATE_352P8KHZ;
  654. break;
  655. case 10:
  656. sample_rate = SAMPLING_RATE_384KHZ;
  657. break;
  658. default:
  659. sample_rate = SAMPLING_RATE_48KHZ;
  660. break;
  661. }
  662. return sample_rate;
  663. }
  664. static int slim_get_bit_format_val(int bit_format)
  665. {
  666. int val = 0;
  667. switch (bit_format) {
  668. case SNDRV_PCM_FORMAT_S32_LE:
  669. val = 3;
  670. break;
  671. case SNDRV_PCM_FORMAT_S24_3LE:
  672. val = 2;
  673. break;
  674. case SNDRV_PCM_FORMAT_S24_LE:
  675. val = 1;
  676. break;
  677. case SNDRV_PCM_FORMAT_S16_LE:
  678. default:
  679. val = 0;
  680. break;
  681. }
  682. return val;
  683. }
  684. static int slim_get_bit_format(int val)
  685. {
  686. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  687. switch (val) {
  688. case 0:
  689. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  690. break;
  691. case 1:
  692. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  693. break;
  694. case 2:
  695. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  696. break;
  697. case 3:
  698. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  699. break;
  700. default:
  701. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  702. break;
  703. }
  704. return bit_fmt;
  705. }
  706. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  707. {
  708. int port_id = 0;
  709. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  710. port_id = SLIM_RX_0;
  711. } else if (strnstr(kcontrol->id.name,
  712. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  713. port_id = SLIM_RX_2;
  714. } else if (strnstr(kcontrol->id.name,
  715. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  716. port_id = SLIM_RX_5;
  717. } else if (strnstr(kcontrol->id.name,
  718. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  719. port_id = SLIM_RX_6;
  720. } else if (strnstr(kcontrol->id.name,
  721. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  722. port_id = SLIM_TX_0;
  723. } else if (strnstr(kcontrol->id.name,
  724. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  725. port_id = SLIM_TX_1;
  726. } else {
  727. pr_err("%s: unsupported channel: %s",
  728. __func__, kcontrol->id.name);
  729. return -EINVAL;
  730. }
  731. return port_id;
  732. }
  733. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  734. struct snd_ctl_elem_value *ucontrol)
  735. {
  736. int ch_num = slim_get_port_idx(kcontrol);
  737. if (ch_num < 0)
  738. return ch_num;
  739. ucontrol->value.enumerated.item[0] =
  740. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  741. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  742. ch_num, slim_rx_cfg[ch_num].sample_rate,
  743. ucontrol->value.enumerated.item[0]);
  744. return 0;
  745. }
  746. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  747. struct snd_ctl_elem_value *ucontrol)
  748. {
  749. int ch_num = slim_get_port_idx(kcontrol);
  750. if (ch_num < 0)
  751. return ch_num;
  752. slim_rx_cfg[ch_num].sample_rate =
  753. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  754. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  755. ch_num, slim_rx_cfg[ch_num].sample_rate,
  756. ucontrol->value.enumerated.item[0]);
  757. return 0;
  758. }
  759. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  760. struct snd_ctl_elem_value *ucontrol)
  761. {
  762. int ch_num = slim_get_port_idx(kcontrol);
  763. if (ch_num < 0)
  764. return ch_num;
  765. ucontrol->value.enumerated.item[0] =
  766. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  767. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  768. ch_num, slim_tx_cfg[ch_num].sample_rate,
  769. ucontrol->value.enumerated.item[0]);
  770. return 0;
  771. }
  772. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  773. struct snd_ctl_elem_value *ucontrol)
  774. {
  775. int sample_rate = 0;
  776. int ch_num = slim_get_port_idx(kcontrol);
  777. if (ch_num < 0)
  778. return ch_num;
  779. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  780. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  781. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  782. __func__, sample_rate);
  783. return -EINVAL;
  784. }
  785. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  786. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  787. ch_num, slim_tx_cfg[ch_num].sample_rate,
  788. ucontrol->value.enumerated.item[0]);
  789. return 0;
  790. }
  791. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  792. struct snd_ctl_elem_value *ucontrol)
  793. {
  794. int ch_num = slim_get_port_idx(kcontrol);
  795. if (ch_num < 0)
  796. return ch_num;
  797. ucontrol->value.enumerated.item[0] =
  798. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  799. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  800. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  801. ucontrol->value.enumerated.item[0]);
  802. return 0;
  803. }
  804. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  805. struct snd_ctl_elem_value *ucontrol)
  806. {
  807. int ch_num = slim_get_port_idx(kcontrol);
  808. if (ch_num < 0)
  809. return ch_num;
  810. slim_rx_cfg[ch_num].bit_format =
  811. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  812. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  813. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  814. ucontrol->value.enumerated.item[0]);
  815. return 0;
  816. }
  817. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  818. struct snd_ctl_elem_value *ucontrol)
  819. {
  820. int ch_num = slim_get_port_idx(kcontrol);
  821. if (ch_num < 0)
  822. return ch_num;
  823. ucontrol->value.enumerated.item[0] =
  824. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  825. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  826. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  827. ucontrol->value.enumerated.item[0]);
  828. return 0;
  829. }
  830. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  831. struct snd_ctl_elem_value *ucontrol)
  832. {
  833. int ch_num = slim_get_port_idx(kcontrol);
  834. if (ch_num < 0)
  835. return ch_num;
  836. slim_tx_cfg[ch_num].bit_format =
  837. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  838. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  839. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  840. ucontrol->value.enumerated.item[0]);
  841. return 0;
  842. }
  843. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  844. struct snd_ctl_elem_value *ucontrol)
  845. {
  846. int ch_num = slim_get_port_idx(kcontrol);
  847. if (ch_num < 0)
  848. return ch_num;
  849. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  850. ch_num, slim_rx_cfg[ch_num].channels);
  851. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  852. return 0;
  853. }
  854. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  855. struct snd_ctl_elem_value *ucontrol)
  856. {
  857. int ch_num = slim_get_port_idx(kcontrol);
  858. if (ch_num < 0)
  859. return ch_num;
  860. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  861. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  862. ch_num, slim_rx_cfg[ch_num].channels);
  863. return 1;
  864. }
  865. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  866. struct snd_ctl_elem_value *ucontrol)
  867. {
  868. int ch_num = slim_get_port_idx(kcontrol);
  869. if (ch_num < 0)
  870. return ch_num;
  871. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  872. ch_num, slim_tx_cfg[ch_num].channels);
  873. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  874. return 0;
  875. }
  876. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  877. struct snd_ctl_elem_value *ucontrol)
  878. {
  879. int ch_num = slim_get_port_idx(kcontrol);
  880. if (ch_num < 0)
  881. return ch_num;
  882. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  883. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  884. ch_num, slim_tx_cfg[ch_num].channels);
  885. return 1;
  886. }
  887. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  888. struct snd_ctl_elem_value *ucontrol)
  889. {
  890. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  891. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  892. ucontrol->value.integer.value[0]);
  893. return 0;
  894. }
  895. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  896. struct snd_ctl_elem_value *ucontrol)
  897. {
  898. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  899. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  900. return 1;
  901. }
  902. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  903. struct snd_ctl_elem_value *ucontrol)
  904. {
  905. /*
  906. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  907. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  908. * value.
  909. */
  910. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  911. case SAMPLING_RATE_96KHZ:
  912. ucontrol->value.integer.value[0] = 5;
  913. break;
  914. case SAMPLING_RATE_88P2KHZ:
  915. ucontrol->value.integer.value[0] = 4;
  916. break;
  917. case SAMPLING_RATE_48KHZ:
  918. ucontrol->value.integer.value[0] = 3;
  919. break;
  920. case SAMPLING_RATE_44P1KHZ:
  921. ucontrol->value.integer.value[0] = 2;
  922. break;
  923. case SAMPLING_RATE_16KHZ:
  924. ucontrol->value.integer.value[0] = 1;
  925. break;
  926. case SAMPLING_RATE_8KHZ:
  927. default:
  928. ucontrol->value.integer.value[0] = 0;
  929. break;
  930. }
  931. pr_debug("%s: sample rate = %d", __func__,
  932. slim_rx_cfg[SLIM_RX_7].sample_rate);
  933. return 0;
  934. }
  935. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  936. struct snd_ctl_elem_value *ucontrol)
  937. {
  938. switch (ucontrol->value.integer.value[0]) {
  939. case 1:
  940. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  941. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  942. break;
  943. case 2:
  944. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  945. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  946. break;
  947. case 3:
  948. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  949. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  950. break;
  951. case 4:
  952. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  953. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  954. break;
  955. case 5:
  956. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  957. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  958. break;
  959. case 0:
  960. default:
  961. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  962. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  963. break;
  964. }
  965. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  966. __func__,
  967. slim_rx_cfg[SLIM_RX_7].sample_rate,
  968. slim_tx_cfg[SLIM_TX_7].sample_rate,
  969. ucontrol->value.enumerated.item[0]);
  970. return 0;
  971. }
  972. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  973. {
  974. int idx = 0;
  975. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  976. sizeof("WSA_CDC_DMA_RX_0")))
  977. idx = WSA_CDC_DMA_RX_0;
  978. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  979. sizeof("WSA_CDC_DMA_RX_0")))
  980. idx = WSA_CDC_DMA_RX_1;
  981. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  982. sizeof("WSA_CDC_DMA_TX_0")))
  983. idx = WSA_CDC_DMA_TX_0;
  984. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  985. sizeof("WSA_CDC_DMA_TX_1")))
  986. idx = WSA_CDC_DMA_TX_1;
  987. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  988. sizeof("WSA_CDC_DMA_TX_2")))
  989. idx = WSA_CDC_DMA_TX_2;
  990. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  991. sizeof("VA_CDC_DMA_TX_0")))
  992. idx = VA_CDC_DMA_TX_0;
  993. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  994. sizeof("VA_CDC_DMA_TX_1")))
  995. idx = VA_CDC_DMA_TX_1;
  996. else {
  997. pr_err("%s: unsupported port: %s\n",
  998. __func__, kcontrol->id.name);
  999. return -EINVAL;
  1000. }
  1001. return idx;
  1002. }
  1003. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1004. struct snd_ctl_elem_value *ucontrol)
  1005. {
  1006. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1007. if (ch_num < 0)
  1008. return ch_num;
  1009. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1010. cdc_dma_rx_cfg[ch_num].channels - 1);
  1011. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1012. return 0;
  1013. }
  1014. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1015. struct snd_ctl_elem_value *ucontrol)
  1016. {
  1017. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1018. if (ch_num < 0)
  1019. return ch_num;
  1020. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1021. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1022. cdc_dma_rx_cfg[ch_num].channels);
  1023. return 1;
  1024. }
  1025. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1026. struct snd_ctl_elem_value *ucontrol)
  1027. {
  1028. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1029. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1030. case SNDRV_PCM_FORMAT_S32_LE:
  1031. ucontrol->value.integer.value[0] = 3;
  1032. break;
  1033. case SNDRV_PCM_FORMAT_S24_3LE:
  1034. ucontrol->value.integer.value[0] = 2;
  1035. break;
  1036. case SNDRV_PCM_FORMAT_S24_LE:
  1037. ucontrol->value.integer.value[0] = 1;
  1038. break;
  1039. case SNDRV_PCM_FORMAT_S16_LE:
  1040. default:
  1041. ucontrol->value.integer.value[0] = 0;
  1042. break;
  1043. }
  1044. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1045. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1046. ucontrol->value.integer.value[0]);
  1047. return 0;
  1048. }
  1049. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1050. struct snd_ctl_elem_value *ucontrol)
  1051. {
  1052. int rc = 0;
  1053. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1054. switch (ucontrol->value.integer.value[0]) {
  1055. case 3:
  1056. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1057. break;
  1058. case 2:
  1059. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1060. break;
  1061. case 1:
  1062. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1063. break;
  1064. case 0:
  1065. default:
  1066. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1067. break;
  1068. }
  1069. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1070. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1071. ucontrol->value.integer.value[0]);
  1072. return rc;
  1073. }
  1074. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1075. {
  1076. int sample_rate_val = 0;
  1077. switch (sample_rate) {
  1078. case SAMPLING_RATE_8KHZ:
  1079. sample_rate_val = 0;
  1080. break;
  1081. case SAMPLING_RATE_16KHZ:
  1082. sample_rate_val = 1;
  1083. break;
  1084. case SAMPLING_RATE_32KHZ:
  1085. sample_rate_val = 2;
  1086. break;
  1087. case SAMPLING_RATE_44P1KHZ:
  1088. sample_rate_val = 3;
  1089. break;
  1090. case SAMPLING_RATE_48KHZ:
  1091. sample_rate_val = 4;
  1092. break;
  1093. case SAMPLING_RATE_88P2KHZ:
  1094. sample_rate_val = 5;
  1095. break;
  1096. case SAMPLING_RATE_96KHZ:
  1097. sample_rate_val = 6;
  1098. break;
  1099. case SAMPLING_RATE_176P4KHZ:
  1100. sample_rate_val = 7;
  1101. break;
  1102. case SAMPLING_RATE_192KHZ:
  1103. sample_rate_val = 8;
  1104. break;
  1105. case SAMPLING_RATE_352P8KHZ:
  1106. sample_rate_val = 9;
  1107. break;
  1108. case SAMPLING_RATE_384KHZ:
  1109. sample_rate_val = 10;
  1110. break;
  1111. default:
  1112. sample_rate_val = 4;
  1113. break;
  1114. }
  1115. return sample_rate_val;
  1116. }
  1117. static int cdc_dma_get_sample_rate(int value)
  1118. {
  1119. int sample_rate = 0;
  1120. switch (value) {
  1121. case 0:
  1122. sample_rate = SAMPLING_RATE_8KHZ;
  1123. break;
  1124. case 1:
  1125. sample_rate = SAMPLING_RATE_16KHZ;
  1126. break;
  1127. case 2:
  1128. sample_rate = SAMPLING_RATE_32KHZ;
  1129. break;
  1130. case 3:
  1131. sample_rate = SAMPLING_RATE_44P1KHZ;
  1132. break;
  1133. case 4:
  1134. sample_rate = SAMPLING_RATE_48KHZ;
  1135. break;
  1136. case 5:
  1137. sample_rate = SAMPLING_RATE_88P2KHZ;
  1138. break;
  1139. case 6:
  1140. sample_rate = SAMPLING_RATE_96KHZ;
  1141. break;
  1142. case 7:
  1143. sample_rate = SAMPLING_RATE_176P4KHZ;
  1144. break;
  1145. case 8:
  1146. sample_rate = SAMPLING_RATE_192KHZ;
  1147. break;
  1148. case 9:
  1149. sample_rate = SAMPLING_RATE_352P8KHZ;
  1150. break;
  1151. case 10:
  1152. sample_rate = SAMPLING_RATE_384KHZ;
  1153. break;
  1154. default:
  1155. sample_rate = SAMPLING_RATE_48KHZ;
  1156. break;
  1157. }
  1158. return sample_rate;
  1159. }
  1160. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1161. struct snd_ctl_elem_value *ucontrol)
  1162. {
  1163. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1164. if (ch_num < 0)
  1165. return ch_num;
  1166. ucontrol->value.enumerated.item[0] =
  1167. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1168. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1169. cdc_dma_rx_cfg[ch_num].sample_rate);
  1170. return 0;
  1171. }
  1172. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1173. struct snd_ctl_elem_value *ucontrol)
  1174. {
  1175. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1176. if (ch_num < 0)
  1177. return ch_num;
  1178. cdc_dma_rx_cfg[ch_num].sample_rate =
  1179. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1180. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1181. __func__, ucontrol->value.enumerated.item[0],
  1182. cdc_dma_rx_cfg[ch_num].sample_rate);
  1183. return 0;
  1184. }
  1185. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1186. struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1189. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1190. cdc_dma_tx_cfg[ch_num].channels);
  1191. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1192. return 0;
  1193. }
  1194. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1198. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1199. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1200. cdc_dma_tx_cfg[ch_num].channels);
  1201. return 1;
  1202. }
  1203. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1204. struct snd_ctl_elem_value *ucontrol)
  1205. {
  1206. int sample_rate_val;
  1207. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1208. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1209. case SAMPLING_RATE_384KHZ:
  1210. sample_rate_val = 12;
  1211. break;
  1212. case SAMPLING_RATE_352P8KHZ:
  1213. sample_rate_val = 11;
  1214. break;
  1215. case SAMPLING_RATE_192KHZ:
  1216. sample_rate_val = 10;
  1217. break;
  1218. case SAMPLING_RATE_176P4KHZ:
  1219. sample_rate_val = 9;
  1220. break;
  1221. case SAMPLING_RATE_96KHZ:
  1222. sample_rate_val = 8;
  1223. break;
  1224. case SAMPLING_RATE_88P2KHZ:
  1225. sample_rate_val = 7;
  1226. break;
  1227. case SAMPLING_RATE_48KHZ:
  1228. sample_rate_val = 6;
  1229. break;
  1230. case SAMPLING_RATE_44P1KHZ:
  1231. sample_rate_val = 5;
  1232. break;
  1233. case SAMPLING_RATE_32KHZ:
  1234. sample_rate_val = 4;
  1235. break;
  1236. case SAMPLING_RATE_22P05KHZ:
  1237. sample_rate_val = 3;
  1238. break;
  1239. case SAMPLING_RATE_16KHZ:
  1240. sample_rate_val = 2;
  1241. break;
  1242. case SAMPLING_RATE_11P025KHZ:
  1243. sample_rate_val = 1;
  1244. break;
  1245. case SAMPLING_RATE_8KHZ:
  1246. sample_rate_val = 0;
  1247. break;
  1248. default:
  1249. sample_rate_val = 6;
  1250. break;
  1251. }
  1252. ucontrol->value.integer.value[0] = sample_rate_val;
  1253. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1254. cdc_dma_tx_cfg[ch_num].sample_rate);
  1255. return 0;
  1256. }
  1257. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1258. struct snd_ctl_elem_value *ucontrol)
  1259. {
  1260. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1261. switch (ucontrol->value.integer.value[0]) {
  1262. case 12:
  1263. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1264. break;
  1265. case 11:
  1266. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1267. break;
  1268. case 10:
  1269. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1270. break;
  1271. case 9:
  1272. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1273. break;
  1274. case 8:
  1275. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1276. break;
  1277. case 7:
  1278. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1279. break;
  1280. case 6:
  1281. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1282. break;
  1283. case 5:
  1284. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1285. break;
  1286. case 4:
  1287. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1288. break;
  1289. case 3:
  1290. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1291. break;
  1292. case 2:
  1293. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1294. break;
  1295. case 1:
  1296. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1297. break;
  1298. case 0:
  1299. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1300. break;
  1301. default:
  1302. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1303. break;
  1304. }
  1305. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1306. __func__, ucontrol->value.integer.value[0],
  1307. cdc_dma_tx_cfg[ch_num].sample_rate);
  1308. return 0;
  1309. }
  1310. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1311. struct snd_ctl_elem_value *ucontrol)
  1312. {
  1313. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1314. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1315. case SNDRV_PCM_FORMAT_S32_LE:
  1316. ucontrol->value.integer.value[0] = 3;
  1317. break;
  1318. case SNDRV_PCM_FORMAT_S24_3LE:
  1319. ucontrol->value.integer.value[0] = 2;
  1320. break;
  1321. case SNDRV_PCM_FORMAT_S24_LE:
  1322. ucontrol->value.integer.value[0] = 1;
  1323. break;
  1324. case SNDRV_PCM_FORMAT_S16_LE:
  1325. default:
  1326. ucontrol->value.integer.value[0] = 0;
  1327. break;
  1328. }
  1329. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1330. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1331. ucontrol->value.integer.value[0]);
  1332. return 0;
  1333. }
  1334. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1335. struct snd_ctl_elem_value *ucontrol)
  1336. {
  1337. int rc = 0;
  1338. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1339. switch (ucontrol->value.integer.value[0]) {
  1340. case 3:
  1341. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1342. break;
  1343. case 2:
  1344. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1345. break;
  1346. case 1:
  1347. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1348. break;
  1349. case 0:
  1350. default:
  1351. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1352. break;
  1353. }
  1354. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1355. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1356. ucontrol->value.integer.value[0]);
  1357. return rc;
  1358. }
  1359. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1360. struct snd_ctl_elem_value *ucontrol)
  1361. {
  1362. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1363. usb_rx_cfg.channels);
  1364. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1365. return 0;
  1366. }
  1367. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1368. struct snd_ctl_elem_value *ucontrol)
  1369. {
  1370. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1371. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1372. return 1;
  1373. }
  1374. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1375. struct snd_ctl_elem_value *ucontrol)
  1376. {
  1377. int sample_rate_val;
  1378. switch (usb_rx_cfg.sample_rate) {
  1379. case SAMPLING_RATE_384KHZ:
  1380. sample_rate_val = 12;
  1381. break;
  1382. case SAMPLING_RATE_352P8KHZ:
  1383. sample_rate_val = 11;
  1384. break;
  1385. case SAMPLING_RATE_192KHZ:
  1386. sample_rate_val = 10;
  1387. break;
  1388. case SAMPLING_RATE_176P4KHZ:
  1389. sample_rate_val = 9;
  1390. break;
  1391. case SAMPLING_RATE_96KHZ:
  1392. sample_rate_val = 8;
  1393. break;
  1394. case SAMPLING_RATE_88P2KHZ:
  1395. sample_rate_val = 7;
  1396. break;
  1397. case SAMPLING_RATE_48KHZ:
  1398. sample_rate_val = 6;
  1399. break;
  1400. case SAMPLING_RATE_44P1KHZ:
  1401. sample_rate_val = 5;
  1402. break;
  1403. case SAMPLING_RATE_32KHZ:
  1404. sample_rate_val = 4;
  1405. break;
  1406. case SAMPLING_RATE_22P05KHZ:
  1407. sample_rate_val = 3;
  1408. break;
  1409. case SAMPLING_RATE_16KHZ:
  1410. sample_rate_val = 2;
  1411. break;
  1412. case SAMPLING_RATE_11P025KHZ:
  1413. sample_rate_val = 1;
  1414. break;
  1415. case SAMPLING_RATE_8KHZ:
  1416. default:
  1417. sample_rate_val = 0;
  1418. break;
  1419. }
  1420. ucontrol->value.integer.value[0] = sample_rate_val;
  1421. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1422. usb_rx_cfg.sample_rate);
  1423. return 0;
  1424. }
  1425. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1426. struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. switch (ucontrol->value.integer.value[0]) {
  1429. case 12:
  1430. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1431. break;
  1432. case 11:
  1433. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1434. break;
  1435. case 10:
  1436. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1437. break;
  1438. case 9:
  1439. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1440. break;
  1441. case 8:
  1442. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1443. break;
  1444. case 7:
  1445. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1446. break;
  1447. case 6:
  1448. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1449. break;
  1450. case 5:
  1451. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1452. break;
  1453. case 4:
  1454. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1455. break;
  1456. case 3:
  1457. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1458. break;
  1459. case 2:
  1460. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1461. break;
  1462. case 1:
  1463. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1464. break;
  1465. case 0:
  1466. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1467. break;
  1468. default:
  1469. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1470. break;
  1471. }
  1472. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1473. __func__, ucontrol->value.integer.value[0],
  1474. usb_rx_cfg.sample_rate);
  1475. return 0;
  1476. }
  1477. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. switch (usb_rx_cfg.bit_format) {
  1481. case SNDRV_PCM_FORMAT_S32_LE:
  1482. ucontrol->value.integer.value[0] = 3;
  1483. break;
  1484. case SNDRV_PCM_FORMAT_S24_3LE:
  1485. ucontrol->value.integer.value[0] = 2;
  1486. break;
  1487. case SNDRV_PCM_FORMAT_S24_LE:
  1488. ucontrol->value.integer.value[0] = 1;
  1489. break;
  1490. case SNDRV_PCM_FORMAT_S16_LE:
  1491. default:
  1492. ucontrol->value.integer.value[0] = 0;
  1493. break;
  1494. }
  1495. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1496. __func__, usb_rx_cfg.bit_format,
  1497. ucontrol->value.integer.value[0]);
  1498. return 0;
  1499. }
  1500. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1501. struct snd_ctl_elem_value *ucontrol)
  1502. {
  1503. int rc = 0;
  1504. switch (ucontrol->value.integer.value[0]) {
  1505. case 3:
  1506. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1507. break;
  1508. case 2:
  1509. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1510. break;
  1511. case 1:
  1512. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1513. break;
  1514. case 0:
  1515. default:
  1516. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1517. break;
  1518. }
  1519. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1520. __func__, usb_rx_cfg.bit_format,
  1521. ucontrol->value.integer.value[0]);
  1522. return rc;
  1523. }
  1524. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1525. struct snd_ctl_elem_value *ucontrol)
  1526. {
  1527. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1528. usb_tx_cfg.channels);
  1529. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1530. return 0;
  1531. }
  1532. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1533. struct snd_ctl_elem_value *ucontrol)
  1534. {
  1535. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1536. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1537. return 1;
  1538. }
  1539. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1540. struct snd_ctl_elem_value *ucontrol)
  1541. {
  1542. int sample_rate_val;
  1543. switch (usb_tx_cfg.sample_rate) {
  1544. case SAMPLING_RATE_384KHZ:
  1545. sample_rate_val = 12;
  1546. break;
  1547. case SAMPLING_RATE_352P8KHZ:
  1548. sample_rate_val = 11;
  1549. break;
  1550. case SAMPLING_RATE_192KHZ:
  1551. sample_rate_val = 10;
  1552. break;
  1553. case SAMPLING_RATE_176P4KHZ:
  1554. sample_rate_val = 9;
  1555. break;
  1556. case SAMPLING_RATE_96KHZ:
  1557. sample_rate_val = 8;
  1558. break;
  1559. case SAMPLING_RATE_88P2KHZ:
  1560. sample_rate_val = 7;
  1561. break;
  1562. case SAMPLING_RATE_48KHZ:
  1563. sample_rate_val = 6;
  1564. break;
  1565. case SAMPLING_RATE_44P1KHZ:
  1566. sample_rate_val = 5;
  1567. break;
  1568. case SAMPLING_RATE_32KHZ:
  1569. sample_rate_val = 4;
  1570. break;
  1571. case SAMPLING_RATE_22P05KHZ:
  1572. sample_rate_val = 3;
  1573. break;
  1574. case SAMPLING_RATE_16KHZ:
  1575. sample_rate_val = 2;
  1576. break;
  1577. case SAMPLING_RATE_11P025KHZ:
  1578. sample_rate_val = 1;
  1579. break;
  1580. case SAMPLING_RATE_8KHZ:
  1581. sample_rate_val = 0;
  1582. break;
  1583. default:
  1584. sample_rate_val = 6;
  1585. break;
  1586. }
  1587. ucontrol->value.integer.value[0] = sample_rate_val;
  1588. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1589. usb_tx_cfg.sample_rate);
  1590. return 0;
  1591. }
  1592. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1593. struct snd_ctl_elem_value *ucontrol)
  1594. {
  1595. switch (ucontrol->value.integer.value[0]) {
  1596. case 12:
  1597. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1598. break;
  1599. case 11:
  1600. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1601. break;
  1602. case 10:
  1603. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1604. break;
  1605. case 9:
  1606. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1607. break;
  1608. case 8:
  1609. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1610. break;
  1611. case 7:
  1612. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1613. break;
  1614. case 6:
  1615. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1616. break;
  1617. case 5:
  1618. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1619. break;
  1620. case 4:
  1621. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1622. break;
  1623. case 3:
  1624. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1625. break;
  1626. case 2:
  1627. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1628. break;
  1629. case 1:
  1630. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1631. break;
  1632. case 0:
  1633. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1634. break;
  1635. default:
  1636. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1637. break;
  1638. }
  1639. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1640. __func__, ucontrol->value.integer.value[0],
  1641. usb_tx_cfg.sample_rate);
  1642. return 0;
  1643. }
  1644. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1645. struct snd_ctl_elem_value *ucontrol)
  1646. {
  1647. switch (usb_tx_cfg.bit_format) {
  1648. case SNDRV_PCM_FORMAT_S32_LE:
  1649. ucontrol->value.integer.value[0] = 3;
  1650. break;
  1651. case SNDRV_PCM_FORMAT_S24_3LE:
  1652. ucontrol->value.integer.value[0] = 2;
  1653. break;
  1654. case SNDRV_PCM_FORMAT_S24_LE:
  1655. ucontrol->value.integer.value[0] = 1;
  1656. break;
  1657. case SNDRV_PCM_FORMAT_S16_LE:
  1658. default:
  1659. ucontrol->value.integer.value[0] = 0;
  1660. break;
  1661. }
  1662. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1663. __func__, usb_tx_cfg.bit_format,
  1664. ucontrol->value.integer.value[0]);
  1665. return 0;
  1666. }
  1667. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1668. struct snd_ctl_elem_value *ucontrol)
  1669. {
  1670. int rc = 0;
  1671. switch (ucontrol->value.integer.value[0]) {
  1672. case 3:
  1673. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1674. break;
  1675. case 2:
  1676. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1677. break;
  1678. case 1:
  1679. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1680. break;
  1681. case 0:
  1682. default:
  1683. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1684. break;
  1685. }
  1686. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1687. __func__, usb_tx_cfg.bit_format,
  1688. ucontrol->value.integer.value[0]);
  1689. return rc;
  1690. }
  1691. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1692. struct snd_ctl_elem_value *ucontrol)
  1693. {
  1694. pr_debug("%s: proxy_rx channels = %d\n",
  1695. __func__, proxy_rx_cfg.channels);
  1696. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1697. return 0;
  1698. }
  1699. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1700. struct snd_ctl_elem_value *ucontrol)
  1701. {
  1702. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1703. pr_debug("%s: proxy_rx channels = %d\n",
  1704. __func__, proxy_rx_cfg.channels);
  1705. return 1;
  1706. }
  1707. static int tdm_get_sample_rate(int value)
  1708. {
  1709. int sample_rate = 0;
  1710. switch (value) {
  1711. case 0:
  1712. sample_rate = SAMPLING_RATE_8KHZ;
  1713. break;
  1714. case 1:
  1715. sample_rate = SAMPLING_RATE_16KHZ;
  1716. break;
  1717. case 2:
  1718. sample_rate = SAMPLING_RATE_32KHZ;
  1719. break;
  1720. case 3:
  1721. sample_rate = SAMPLING_RATE_48KHZ;
  1722. break;
  1723. case 4:
  1724. sample_rate = SAMPLING_RATE_176P4KHZ;
  1725. break;
  1726. case 5:
  1727. sample_rate = SAMPLING_RATE_352P8KHZ;
  1728. break;
  1729. default:
  1730. sample_rate = SAMPLING_RATE_48KHZ;
  1731. break;
  1732. }
  1733. return sample_rate;
  1734. }
  1735. static int aux_pcm_get_sample_rate(int value)
  1736. {
  1737. int sample_rate;
  1738. switch (value) {
  1739. case 1:
  1740. sample_rate = SAMPLING_RATE_16KHZ;
  1741. break;
  1742. case 0:
  1743. default:
  1744. sample_rate = SAMPLING_RATE_8KHZ;
  1745. break;
  1746. }
  1747. return sample_rate;
  1748. }
  1749. static int tdm_get_sample_rate_val(int sample_rate)
  1750. {
  1751. int sample_rate_val = 0;
  1752. switch (sample_rate) {
  1753. case SAMPLING_RATE_8KHZ:
  1754. sample_rate_val = 0;
  1755. break;
  1756. case SAMPLING_RATE_16KHZ:
  1757. sample_rate_val = 1;
  1758. break;
  1759. case SAMPLING_RATE_32KHZ:
  1760. sample_rate_val = 2;
  1761. break;
  1762. case SAMPLING_RATE_48KHZ:
  1763. sample_rate_val = 3;
  1764. break;
  1765. case SAMPLING_RATE_176P4KHZ:
  1766. sample_rate_val = 4;
  1767. break;
  1768. case SAMPLING_RATE_352P8KHZ:
  1769. sample_rate_val = 5;
  1770. break;
  1771. default:
  1772. sample_rate_val = 3;
  1773. break;
  1774. }
  1775. return sample_rate_val;
  1776. }
  1777. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1778. {
  1779. int sample_rate_val;
  1780. switch (sample_rate) {
  1781. case SAMPLING_RATE_16KHZ:
  1782. sample_rate_val = 1;
  1783. break;
  1784. case SAMPLING_RATE_8KHZ:
  1785. default:
  1786. sample_rate_val = 0;
  1787. break;
  1788. }
  1789. return sample_rate_val;
  1790. }
  1791. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1792. struct tdm_port *port)
  1793. {
  1794. if (port) {
  1795. if (strnstr(kcontrol->id.name, "PRI",
  1796. sizeof(kcontrol->id.name))) {
  1797. port->mode = TDM_PRI;
  1798. } else if (strnstr(kcontrol->id.name, "SEC",
  1799. sizeof(kcontrol->id.name))) {
  1800. port->mode = TDM_SEC;
  1801. } else if (strnstr(kcontrol->id.name, "TERT",
  1802. sizeof(kcontrol->id.name))) {
  1803. port->mode = TDM_TERT;
  1804. } else if (strnstr(kcontrol->id.name, "QUAT",
  1805. sizeof(kcontrol->id.name))) {
  1806. port->mode = TDM_QUAT;
  1807. } else if (strnstr(kcontrol->id.name, "QUIN",
  1808. sizeof(kcontrol->id.name))) {
  1809. port->mode = TDM_QUIN;
  1810. } else {
  1811. pr_err("%s: unsupported mode in: %s",
  1812. __func__, kcontrol->id.name);
  1813. return -EINVAL;
  1814. }
  1815. if (strnstr(kcontrol->id.name, "RX_0",
  1816. sizeof(kcontrol->id.name)) ||
  1817. strnstr(kcontrol->id.name, "TX_0",
  1818. sizeof(kcontrol->id.name))) {
  1819. port->channel = TDM_0;
  1820. } else if (strnstr(kcontrol->id.name, "RX_1",
  1821. sizeof(kcontrol->id.name)) ||
  1822. strnstr(kcontrol->id.name, "TX_1",
  1823. sizeof(kcontrol->id.name))) {
  1824. port->channel = TDM_1;
  1825. } else if (strnstr(kcontrol->id.name, "RX_2",
  1826. sizeof(kcontrol->id.name)) ||
  1827. strnstr(kcontrol->id.name, "TX_2",
  1828. sizeof(kcontrol->id.name))) {
  1829. port->channel = TDM_2;
  1830. } else if (strnstr(kcontrol->id.name, "RX_3",
  1831. sizeof(kcontrol->id.name)) ||
  1832. strnstr(kcontrol->id.name, "TX_3",
  1833. sizeof(kcontrol->id.name))) {
  1834. port->channel = TDM_3;
  1835. } else if (strnstr(kcontrol->id.name, "RX_4",
  1836. sizeof(kcontrol->id.name)) ||
  1837. strnstr(kcontrol->id.name, "TX_4",
  1838. sizeof(kcontrol->id.name))) {
  1839. port->channel = TDM_4;
  1840. } else if (strnstr(kcontrol->id.name, "RX_5",
  1841. sizeof(kcontrol->id.name)) ||
  1842. strnstr(kcontrol->id.name, "TX_5",
  1843. sizeof(kcontrol->id.name))) {
  1844. port->channel = TDM_5;
  1845. } else if (strnstr(kcontrol->id.name, "RX_6",
  1846. sizeof(kcontrol->id.name)) ||
  1847. strnstr(kcontrol->id.name, "TX_6",
  1848. sizeof(kcontrol->id.name))) {
  1849. port->channel = TDM_6;
  1850. } else if (strnstr(kcontrol->id.name, "RX_7",
  1851. sizeof(kcontrol->id.name)) ||
  1852. strnstr(kcontrol->id.name, "TX_7",
  1853. sizeof(kcontrol->id.name))) {
  1854. port->channel = TDM_7;
  1855. } else {
  1856. pr_err("%s: unsupported channel in: %s",
  1857. __func__, kcontrol->id.name);
  1858. return -EINVAL;
  1859. }
  1860. } else
  1861. return -EINVAL;
  1862. return 0;
  1863. }
  1864. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1865. struct snd_ctl_elem_value *ucontrol)
  1866. {
  1867. struct tdm_port port;
  1868. int ret = tdm_get_port_idx(kcontrol, &port);
  1869. if (ret) {
  1870. pr_err("%s: unsupported control: %s",
  1871. __func__, kcontrol->id.name);
  1872. } else {
  1873. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1874. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1875. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1876. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1877. ucontrol->value.enumerated.item[0]);
  1878. }
  1879. return ret;
  1880. }
  1881. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1882. struct snd_ctl_elem_value *ucontrol)
  1883. {
  1884. struct tdm_port port;
  1885. int ret = tdm_get_port_idx(kcontrol, &port);
  1886. if (ret) {
  1887. pr_err("%s: unsupported control: %s",
  1888. __func__, kcontrol->id.name);
  1889. } else {
  1890. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1891. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1892. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1893. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1894. ucontrol->value.enumerated.item[0]);
  1895. }
  1896. return ret;
  1897. }
  1898. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1899. struct snd_ctl_elem_value *ucontrol)
  1900. {
  1901. struct tdm_port port;
  1902. int ret = tdm_get_port_idx(kcontrol, &port);
  1903. if (ret) {
  1904. pr_err("%s: unsupported control: %s",
  1905. __func__, kcontrol->id.name);
  1906. } else {
  1907. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1908. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1909. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1910. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1911. ucontrol->value.enumerated.item[0]);
  1912. }
  1913. return ret;
  1914. }
  1915. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1916. struct snd_ctl_elem_value *ucontrol)
  1917. {
  1918. struct tdm_port port;
  1919. int ret = tdm_get_port_idx(kcontrol, &port);
  1920. if (ret) {
  1921. pr_err("%s: unsupported control: %s",
  1922. __func__, kcontrol->id.name);
  1923. } else {
  1924. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1925. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1926. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1927. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1928. ucontrol->value.enumerated.item[0]);
  1929. }
  1930. return ret;
  1931. }
  1932. static int tdm_get_format(int value)
  1933. {
  1934. int format = 0;
  1935. switch (value) {
  1936. case 0:
  1937. format = SNDRV_PCM_FORMAT_S16_LE;
  1938. break;
  1939. case 1:
  1940. format = SNDRV_PCM_FORMAT_S24_LE;
  1941. break;
  1942. case 2:
  1943. format = SNDRV_PCM_FORMAT_S32_LE;
  1944. break;
  1945. default:
  1946. format = SNDRV_PCM_FORMAT_S16_LE;
  1947. break;
  1948. }
  1949. return format;
  1950. }
  1951. static int tdm_get_format_val(int format)
  1952. {
  1953. int value = 0;
  1954. switch (format) {
  1955. case SNDRV_PCM_FORMAT_S16_LE:
  1956. value = 0;
  1957. break;
  1958. case SNDRV_PCM_FORMAT_S24_LE:
  1959. value = 1;
  1960. break;
  1961. case SNDRV_PCM_FORMAT_S32_LE:
  1962. value = 2;
  1963. break;
  1964. default:
  1965. value = 0;
  1966. break;
  1967. }
  1968. return value;
  1969. }
  1970. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1971. struct snd_ctl_elem_value *ucontrol)
  1972. {
  1973. struct tdm_port port;
  1974. int ret = tdm_get_port_idx(kcontrol, &port);
  1975. if (ret) {
  1976. pr_err("%s: unsupported control: %s",
  1977. __func__, kcontrol->id.name);
  1978. } else {
  1979. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1980. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1981. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1982. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1983. ucontrol->value.enumerated.item[0]);
  1984. }
  1985. return ret;
  1986. }
  1987. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1988. struct snd_ctl_elem_value *ucontrol)
  1989. {
  1990. struct tdm_port port;
  1991. int ret = tdm_get_port_idx(kcontrol, &port);
  1992. if (ret) {
  1993. pr_err("%s: unsupported control: %s",
  1994. __func__, kcontrol->id.name);
  1995. } else {
  1996. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1997. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1998. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1999. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2000. ucontrol->value.enumerated.item[0]);
  2001. }
  2002. return ret;
  2003. }
  2004. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2005. struct snd_ctl_elem_value *ucontrol)
  2006. {
  2007. struct tdm_port port;
  2008. int ret = tdm_get_port_idx(kcontrol, &port);
  2009. if (ret) {
  2010. pr_err("%s: unsupported control: %s",
  2011. __func__, kcontrol->id.name);
  2012. } else {
  2013. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2014. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2015. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2016. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2017. ucontrol->value.enumerated.item[0]);
  2018. }
  2019. return ret;
  2020. }
  2021. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2022. struct snd_ctl_elem_value *ucontrol)
  2023. {
  2024. struct tdm_port port;
  2025. int ret = tdm_get_port_idx(kcontrol, &port);
  2026. if (ret) {
  2027. pr_err("%s: unsupported control: %s",
  2028. __func__, kcontrol->id.name);
  2029. } else {
  2030. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2031. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2032. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2033. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2034. ucontrol->value.enumerated.item[0]);
  2035. }
  2036. return ret;
  2037. }
  2038. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2039. struct snd_ctl_elem_value *ucontrol)
  2040. {
  2041. struct tdm_port port;
  2042. int ret = tdm_get_port_idx(kcontrol, &port);
  2043. if (ret) {
  2044. pr_err("%s: unsupported control: %s",
  2045. __func__, kcontrol->id.name);
  2046. } else {
  2047. ucontrol->value.enumerated.item[0] =
  2048. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2049. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2050. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2051. ucontrol->value.enumerated.item[0]);
  2052. }
  2053. return ret;
  2054. }
  2055. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2056. struct snd_ctl_elem_value *ucontrol)
  2057. {
  2058. struct tdm_port port;
  2059. int ret = tdm_get_port_idx(kcontrol, &port);
  2060. if (ret) {
  2061. pr_err("%s: unsupported control: %s",
  2062. __func__, kcontrol->id.name);
  2063. } else {
  2064. tdm_rx_cfg[port.mode][port.channel].channels =
  2065. ucontrol->value.enumerated.item[0] + 1;
  2066. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2067. tdm_rx_cfg[port.mode][port.channel].channels,
  2068. ucontrol->value.enumerated.item[0] + 1);
  2069. }
  2070. return ret;
  2071. }
  2072. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2073. struct snd_ctl_elem_value *ucontrol)
  2074. {
  2075. struct tdm_port port;
  2076. int ret = tdm_get_port_idx(kcontrol, &port);
  2077. if (ret) {
  2078. pr_err("%s: unsupported control: %s",
  2079. __func__, kcontrol->id.name);
  2080. } else {
  2081. ucontrol->value.enumerated.item[0] =
  2082. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2083. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2084. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2085. ucontrol->value.enumerated.item[0]);
  2086. }
  2087. return ret;
  2088. }
  2089. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2090. struct snd_ctl_elem_value *ucontrol)
  2091. {
  2092. struct tdm_port port;
  2093. int ret = tdm_get_port_idx(kcontrol, &port);
  2094. if (ret) {
  2095. pr_err("%s: unsupported control: %s",
  2096. __func__, kcontrol->id.name);
  2097. } else {
  2098. tdm_tx_cfg[port.mode][port.channel].channels =
  2099. ucontrol->value.enumerated.item[0] + 1;
  2100. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2101. tdm_tx_cfg[port.mode][port.channel].channels,
  2102. ucontrol->value.enumerated.item[0] + 1);
  2103. }
  2104. return ret;
  2105. }
  2106. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2107. {
  2108. int idx;
  2109. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2110. sizeof("PRIM_AUX_PCM")))
  2111. idx = PRIM_AUX_PCM;
  2112. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2113. sizeof("SEC_AUX_PCM")))
  2114. idx = SEC_AUX_PCM;
  2115. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2116. sizeof("TERT_AUX_PCM")))
  2117. idx = TERT_AUX_PCM;
  2118. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2119. sizeof("QUAT_AUX_PCM")))
  2120. idx = QUAT_AUX_PCM;
  2121. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2122. sizeof("QUIN_AUX_PCM")))
  2123. idx = QUIN_AUX_PCM;
  2124. else {
  2125. pr_err("%s: unsupported port: %s",
  2126. __func__, kcontrol->id.name);
  2127. idx = -EINVAL;
  2128. }
  2129. return idx;
  2130. }
  2131. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2132. struct snd_ctl_elem_value *ucontrol)
  2133. {
  2134. int idx = aux_pcm_get_port_idx(kcontrol);
  2135. if (idx < 0)
  2136. return idx;
  2137. aux_pcm_rx_cfg[idx].sample_rate =
  2138. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2139. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2140. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2141. ucontrol->value.enumerated.item[0]);
  2142. return 0;
  2143. }
  2144. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2145. struct snd_ctl_elem_value *ucontrol)
  2146. {
  2147. int idx = aux_pcm_get_port_idx(kcontrol);
  2148. if (idx < 0)
  2149. return idx;
  2150. ucontrol->value.enumerated.item[0] =
  2151. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2152. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2153. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2154. ucontrol->value.enumerated.item[0]);
  2155. return 0;
  2156. }
  2157. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2158. struct snd_ctl_elem_value *ucontrol)
  2159. {
  2160. int idx = aux_pcm_get_port_idx(kcontrol);
  2161. if (idx < 0)
  2162. return idx;
  2163. aux_pcm_tx_cfg[idx].sample_rate =
  2164. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2165. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2166. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2167. ucontrol->value.enumerated.item[0]);
  2168. return 0;
  2169. }
  2170. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2171. struct snd_ctl_elem_value *ucontrol)
  2172. {
  2173. int idx = aux_pcm_get_port_idx(kcontrol);
  2174. if (idx < 0)
  2175. return idx;
  2176. ucontrol->value.enumerated.item[0] =
  2177. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2178. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2179. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2180. ucontrol->value.enumerated.item[0]);
  2181. return 0;
  2182. }
  2183. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2184. {
  2185. int idx;
  2186. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2187. sizeof("PRIM_MI2S_RX")))
  2188. idx = PRIM_MI2S;
  2189. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2190. sizeof("SEC_MI2S_RX")))
  2191. idx = SEC_MI2S;
  2192. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2193. sizeof("TERT_MI2S_RX")))
  2194. idx = TERT_MI2S;
  2195. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2196. sizeof("QUAT_MI2S_RX")))
  2197. idx = QUAT_MI2S;
  2198. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2199. sizeof("QUIN_MI2S_RX")))
  2200. idx = QUIN_MI2S;
  2201. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2202. sizeof("PRIM_MI2S_TX")))
  2203. idx = PRIM_MI2S;
  2204. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2205. sizeof("SEC_MI2S_TX")))
  2206. idx = SEC_MI2S;
  2207. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2208. sizeof("TERT_MI2S_TX")))
  2209. idx = TERT_MI2S;
  2210. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2211. sizeof("QUAT_MI2S_TX")))
  2212. idx = QUAT_MI2S;
  2213. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2214. sizeof("QUIN_MI2S_TX")))
  2215. idx = QUIN_MI2S;
  2216. else {
  2217. pr_err("%s: unsupported channel: %s",
  2218. __func__, kcontrol->id.name);
  2219. idx = -EINVAL;
  2220. }
  2221. return idx;
  2222. }
  2223. static int mi2s_get_sample_rate_val(int sample_rate)
  2224. {
  2225. int sample_rate_val;
  2226. switch (sample_rate) {
  2227. case SAMPLING_RATE_8KHZ:
  2228. sample_rate_val = 0;
  2229. break;
  2230. case SAMPLING_RATE_11P025KHZ:
  2231. sample_rate_val = 1;
  2232. break;
  2233. case SAMPLING_RATE_16KHZ:
  2234. sample_rate_val = 2;
  2235. break;
  2236. case SAMPLING_RATE_22P05KHZ:
  2237. sample_rate_val = 3;
  2238. break;
  2239. case SAMPLING_RATE_32KHZ:
  2240. sample_rate_val = 4;
  2241. break;
  2242. case SAMPLING_RATE_44P1KHZ:
  2243. sample_rate_val = 5;
  2244. break;
  2245. case SAMPLING_RATE_48KHZ:
  2246. sample_rate_val = 6;
  2247. break;
  2248. case SAMPLING_RATE_96KHZ:
  2249. sample_rate_val = 7;
  2250. break;
  2251. case SAMPLING_RATE_192KHZ:
  2252. sample_rate_val = 8;
  2253. break;
  2254. default:
  2255. sample_rate_val = 6;
  2256. break;
  2257. }
  2258. return sample_rate_val;
  2259. }
  2260. static int mi2s_get_sample_rate(int value)
  2261. {
  2262. int sample_rate;
  2263. switch (value) {
  2264. case 0:
  2265. sample_rate = SAMPLING_RATE_8KHZ;
  2266. break;
  2267. case 1:
  2268. sample_rate = SAMPLING_RATE_11P025KHZ;
  2269. break;
  2270. case 2:
  2271. sample_rate = SAMPLING_RATE_16KHZ;
  2272. break;
  2273. case 3:
  2274. sample_rate = SAMPLING_RATE_22P05KHZ;
  2275. break;
  2276. case 4:
  2277. sample_rate = SAMPLING_RATE_32KHZ;
  2278. break;
  2279. case 5:
  2280. sample_rate = SAMPLING_RATE_44P1KHZ;
  2281. break;
  2282. case 6:
  2283. sample_rate = SAMPLING_RATE_48KHZ;
  2284. break;
  2285. case 7:
  2286. sample_rate = SAMPLING_RATE_96KHZ;
  2287. break;
  2288. case 8:
  2289. sample_rate = SAMPLING_RATE_192KHZ;
  2290. break;
  2291. default:
  2292. sample_rate = SAMPLING_RATE_48KHZ;
  2293. break;
  2294. }
  2295. return sample_rate;
  2296. }
  2297. static int mi2s_auxpcm_get_format(int value)
  2298. {
  2299. int format;
  2300. switch (value) {
  2301. case 0:
  2302. format = SNDRV_PCM_FORMAT_S16_LE;
  2303. break;
  2304. case 1:
  2305. format = SNDRV_PCM_FORMAT_S24_LE;
  2306. break;
  2307. case 2:
  2308. format = SNDRV_PCM_FORMAT_S24_3LE;
  2309. break;
  2310. case 3:
  2311. format = SNDRV_PCM_FORMAT_S32_LE;
  2312. break;
  2313. default:
  2314. format = SNDRV_PCM_FORMAT_S16_LE;
  2315. break;
  2316. }
  2317. return format;
  2318. }
  2319. static int mi2s_auxpcm_get_format_value(int format)
  2320. {
  2321. int value;
  2322. switch (format) {
  2323. case SNDRV_PCM_FORMAT_S16_LE:
  2324. value = 0;
  2325. break;
  2326. case SNDRV_PCM_FORMAT_S24_LE:
  2327. value = 1;
  2328. break;
  2329. case SNDRV_PCM_FORMAT_S24_3LE:
  2330. value = 2;
  2331. break;
  2332. case SNDRV_PCM_FORMAT_S32_LE:
  2333. value = 3;
  2334. break;
  2335. default:
  2336. value = 0;
  2337. break;
  2338. }
  2339. return value;
  2340. }
  2341. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2342. struct snd_ctl_elem_value *ucontrol)
  2343. {
  2344. int idx = mi2s_get_port_idx(kcontrol);
  2345. if (idx < 0)
  2346. return idx;
  2347. mi2s_rx_cfg[idx].sample_rate =
  2348. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2349. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2350. idx, mi2s_rx_cfg[idx].sample_rate,
  2351. ucontrol->value.enumerated.item[0]);
  2352. return 0;
  2353. }
  2354. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2355. struct snd_ctl_elem_value *ucontrol)
  2356. {
  2357. int idx = mi2s_get_port_idx(kcontrol);
  2358. if (idx < 0)
  2359. return idx;
  2360. ucontrol->value.enumerated.item[0] =
  2361. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2362. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2363. idx, mi2s_rx_cfg[idx].sample_rate,
  2364. ucontrol->value.enumerated.item[0]);
  2365. return 0;
  2366. }
  2367. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2368. struct snd_ctl_elem_value *ucontrol)
  2369. {
  2370. int idx = mi2s_get_port_idx(kcontrol);
  2371. if (idx < 0)
  2372. return idx;
  2373. mi2s_tx_cfg[idx].sample_rate =
  2374. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2375. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2376. idx, mi2s_tx_cfg[idx].sample_rate,
  2377. ucontrol->value.enumerated.item[0]);
  2378. return 0;
  2379. }
  2380. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2381. struct snd_ctl_elem_value *ucontrol)
  2382. {
  2383. int idx = mi2s_get_port_idx(kcontrol);
  2384. if (idx < 0)
  2385. return idx;
  2386. ucontrol->value.enumerated.item[0] =
  2387. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2388. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2389. idx, mi2s_tx_cfg[idx].sample_rate,
  2390. ucontrol->value.enumerated.item[0]);
  2391. return 0;
  2392. }
  2393. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2394. struct snd_ctl_elem_value *ucontrol)
  2395. {
  2396. int idx = mi2s_get_port_idx(kcontrol);
  2397. if (idx < 0)
  2398. return idx;
  2399. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2400. idx, mi2s_rx_cfg[idx].channels);
  2401. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2402. return 0;
  2403. }
  2404. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2405. struct snd_ctl_elem_value *ucontrol)
  2406. {
  2407. int idx = mi2s_get_port_idx(kcontrol);
  2408. if (idx < 0)
  2409. return idx;
  2410. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2411. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2412. idx, mi2s_rx_cfg[idx].channels);
  2413. return 1;
  2414. }
  2415. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2416. struct snd_ctl_elem_value *ucontrol)
  2417. {
  2418. int idx = mi2s_get_port_idx(kcontrol);
  2419. if (idx < 0)
  2420. return idx;
  2421. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2422. idx, mi2s_tx_cfg[idx].channels);
  2423. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2424. return 0;
  2425. }
  2426. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2427. struct snd_ctl_elem_value *ucontrol)
  2428. {
  2429. int idx = mi2s_get_port_idx(kcontrol);
  2430. if (idx < 0)
  2431. return idx;
  2432. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2433. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2434. idx, mi2s_tx_cfg[idx].channels);
  2435. return 1;
  2436. }
  2437. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2438. struct snd_ctl_elem_value *ucontrol)
  2439. {
  2440. int idx = mi2s_get_port_idx(kcontrol);
  2441. if (idx < 0)
  2442. return idx;
  2443. ucontrol->value.enumerated.item[0] =
  2444. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2445. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2446. idx, mi2s_rx_cfg[idx].bit_format,
  2447. ucontrol->value.enumerated.item[0]);
  2448. return 0;
  2449. }
  2450. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2451. struct snd_ctl_elem_value *ucontrol)
  2452. {
  2453. int idx = mi2s_get_port_idx(kcontrol);
  2454. if (idx < 0)
  2455. return idx;
  2456. mi2s_rx_cfg[idx].bit_format =
  2457. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2458. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2459. idx, mi2s_rx_cfg[idx].bit_format,
  2460. ucontrol->value.enumerated.item[0]);
  2461. return 0;
  2462. }
  2463. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2464. struct snd_ctl_elem_value *ucontrol)
  2465. {
  2466. int idx = mi2s_get_port_idx(kcontrol);
  2467. if (idx < 0)
  2468. return idx;
  2469. ucontrol->value.enumerated.item[0] =
  2470. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2471. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2472. idx, mi2s_tx_cfg[idx].bit_format,
  2473. ucontrol->value.enumerated.item[0]);
  2474. return 0;
  2475. }
  2476. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2477. struct snd_ctl_elem_value *ucontrol)
  2478. {
  2479. int idx = mi2s_get_port_idx(kcontrol);
  2480. if (idx < 0)
  2481. return idx;
  2482. mi2s_tx_cfg[idx].bit_format =
  2483. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2484. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2485. idx, mi2s_tx_cfg[idx].bit_format,
  2486. ucontrol->value.enumerated.item[0]);
  2487. return 0;
  2488. }
  2489. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2490. struct snd_ctl_elem_value *ucontrol)
  2491. {
  2492. int idx = aux_pcm_get_port_idx(kcontrol);
  2493. if (idx < 0)
  2494. return idx;
  2495. ucontrol->value.enumerated.item[0] =
  2496. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2497. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2498. idx, aux_pcm_rx_cfg[idx].bit_format,
  2499. ucontrol->value.enumerated.item[0]);
  2500. return 0;
  2501. }
  2502. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2503. struct snd_ctl_elem_value *ucontrol)
  2504. {
  2505. int idx = aux_pcm_get_port_idx(kcontrol);
  2506. if (idx < 0)
  2507. return idx;
  2508. aux_pcm_rx_cfg[idx].bit_format =
  2509. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2510. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2511. idx, aux_pcm_rx_cfg[idx].bit_format,
  2512. ucontrol->value.enumerated.item[0]);
  2513. return 0;
  2514. }
  2515. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2516. struct snd_ctl_elem_value *ucontrol)
  2517. {
  2518. int idx = aux_pcm_get_port_idx(kcontrol);
  2519. if (idx < 0)
  2520. return idx;
  2521. ucontrol->value.enumerated.item[0] =
  2522. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2523. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2524. idx, aux_pcm_tx_cfg[idx].bit_format,
  2525. ucontrol->value.enumerated.item[0]);
  2526. return 0;
  2527. }
  2528. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2529. struct snd_ctl_elem_value *ucontrol)
  2530. {
  2531. int idx = aux_pcm_get_port_idx(kcontrol);
  2532. if (idx < 0)
  2533. return idx;
  2534. aux_pcm_tx_cfg[idx].bit_format =
  2535. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2536. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2537. idx, aux_pcm_tx_cfg[idx].bit_format,
  2538. ucontrol->value.enumerated.item[0]);
  2539. return 0;
  2540. }
  2541. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2542. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2543. slim_rx_ch_get, slim_rx_ch_put),
  2544. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2545. slim_rx_ch_get, slim_rx_ch_put),
  2546. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2547. slim_tx_ch_get, slim_tx_ch_put),
  2548. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2549. slim_tx_ch_get, slim_tx_ch_put),
  2550. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2551. slim_rx_ch_get, slim_rx_ch_put),
  2552. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2553. slim_rx_ch_get, slim_rx_ch_put),
  2554. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2555. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2556. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2557. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2558. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2559. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2560. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2561. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2562. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2563. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2564. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2565. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2566. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2567. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2568. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2569. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2570. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2571. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2572. };
  2573. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2574. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2575. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2576. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2577. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2578. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2579. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2580. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2581. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2582. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2583. va_cdc_dma_tx_0_sample_rate,
  2584. cdc_dma_tx_sample_rate_get,
  2585. cdc_dma_tx_sample_rate_put),
  2586. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2587. va_cdc_dma_tx_1_sample_rate,
  2588. cdc_dma_tx_sample_rate_get,
  2589. cdc_dma_tx_sample_rate_put),
  2590. };
  2591. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2592. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2593. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2594. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2595. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2596. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2597. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2598. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2599. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2600. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2601. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2602. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2603. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2604. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2605. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2606. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2607. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2608. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2609. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2610. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2611. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2612. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2613. wsa_cdc_dma_rx_0_sample_rate,
  2614. cdc_dma_rx_sample_rate_get,
  2615. cdc_dma_rx_sample_rate_put),
  2616. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2617. wsa_cdc_dma_rx_1_sample_rate,
  2618. cdc_dma_rx_sample_rate_get,
  2619. cdc_dma_rx_sample_rate_put),
  2620. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2621. wsa_cdc_dma_tx_0_sample_rate,
  2622. cdc_dma_tx_sample_rate_get,
  2623. cdc_dma_tx_sample_rate_put),
  2624. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2625. wsa_cdc_dma_tx_1_sample_rate,
  2626. cdc_dma_tx_sample_rate_get,
  2627. cdc_dma_tx_sample_rate_put),
  2628. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2629. wsa_cdc_dma_tx_2_sample_rate,
  2630. cdc_dma_tx_sample_rate_get,
  2631. cdc_dma_tx_sample_rate_put),
  2632. };
  2633. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2634. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2635. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2636. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2637. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2638. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2639. proxy_rx_ch_get, proxy_rx_ch_put),
  2640. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2641. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2642. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2643. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2644. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2645. msm_bt_sample_rate_get,
  2646. msm_bt_sample_rate_put),
  2647. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2648. usb_audio_rx_sample_rate_get,
  2649. usb_audio_rx_sample_rate_put),
  2650. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2651. usb_audio_tx_sample_rate_get,
  2652. usb_audio_tx_sample_rate_put),
  2653. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2654. tdm_rx_sample_rate_get,
  2655. tdm_rx_sample_rate_put),
  2656. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2657. tdm_tx_sample_rate_get,
  2658. tdm_tx_sample_rate_put),
  2659. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2660. tdm_rx_format_get,
  2661. tdm_rx_format_put),
  2662. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2663. tdm_tx_format_get,
  2664. tdm_tx_format_put),
  2665. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2666. tdm_rx_ch_get,
  2667. tdm_rx_ch_put),
  2668. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2669. tdm_tx_ch_get,
  2670. tdm_tx_ch_put),
  2671. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2672. tdm_rx_sample_rate_get,
  2673. tdm_rx_sample_rate_put),
  2674. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2675. tdm_tx_sample_rate_get,
  2676. tdm_tx_sample_rate_put),
  2677. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2678. tdm_rx_format_get,
  2679. tdm_rx_format_put),
  2680. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2681. tdm_tx_format_get,
  2682. tdm_tx_format_put),
  2683. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2684. tdm_rx_ch_get,
  2685. tdm_rx_ch_put),
  2686. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2687. tdm_tx_ch_get,
  2688. tdm_tx_ch_put),
  2689. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2690. tdm_rx_sample_rate_get,
  2691. tdm_rx_sample_rate_put),
  2692. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2693. tdm_tx_sample_rate_get,
  2694. tdm_tx_sample_rate_put),
  2695. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2696. tdm_rx_format_get,
  2697. tdm_rx_format_put),
  2698. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2699. tdm_tx_format_get,
  2700. tdm_tx_format_put),
  2701. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2702. tdm_rx_ch_get,
  2703. tdm_rx_ch_put),
  2704. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2705. tdm_tx_ch_get,
  2706. tdm_tx_ch_put),
  2707. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2708. tdm_rx_sample_rate_get,
  2709. tdm_rx_sample_rate_put),
  2710. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2711. tdm_tx_sample_rate_get,
  2712. tdm_tx_sample_rate_put),
  2713. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2714. tdm_rx_format_get,
  2715. tdm_rx_format_put),
  2716. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2717. tdm_tx_format_get,
  2718. tdm_tx_format_put),
  2719. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2720. tdm_rx_ch_get,
  2721. tdm_rx_ch_put),
  2722. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2723. tdm_tx_ch_get,
  2724. tdm_tx_ch_put),
  2725. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2726. tdm_rx_sample_rate_get,
  2727. tdm_rx_sample_rate_put),
  2728. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2729. tdm_tx_sample_rate_get,
  2730. tdm_tx_sample_rate_put),
  2731. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2732. tdm_rx_format_get,
  2733. tdm_rx_format_put),
  2734. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2735. tdm_tx_format_get,
  2736. tdm_tx_format_put),
  2737. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2738. tdm_rx_ch_get,
  2739. tdm_rx_ch_put),
  2740. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2741. tdm_tx_ch_get,
  2742. tdm_tx_ch_put),
  2743. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2744. aux_pcm_rx_sample_rate_get,
  2745. aux_pcm_rx_sample_rate_put),
  2746. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2747. aux_pcm_rx_sample_rate_get,
  2748. aux_pcm_rx_sample_rate_put),
  2749. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2750. aux_pcm_rx_sample_rate_get,
  2751. aux_pcm_rx_sample_rate_put),
  2752. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2753. aux_pcm_rx_sample_rate_get,
  2754. aux_pcm_rx_sample_rate_put),
  2755. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2756. aux_pcm_rx_sample_rate_get,
  2757. aux_pcm_rx_sample_rate_put),
  2758. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2759. aux_pcm_tx_sample_rate_get,
  2760. aux_pcm_tx_sample_rate_put),
  2761. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2762. aux_pcm_tx_sample_rate_get,
  2763. aux_pcm_tx_sample_rate_put),
  2764. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2765. aux_pcm_tx_sample_rate_get,
  2766. aux_pcm_tx_sample_rate_put),
  2767. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2768. aux_pcm_tx_sample_rate_get,
  2769. aux_pcm_tx_sample_rate_put),
  2770. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2771. aux_pcm_tx_sample_rate_get,
  2772. aux_pcm_tx_sample_rate_put),
  2773. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2774. mi2s_rx_sample_rate_get,
  2775. mi2s_rx_sample_rate_put),
  2776. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2777. mi2s_rx_sample_rate_get,
  2778. mi2s_rx_sample_rate_put),
  2779. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2780. mi2s_rx_sample_rate_get,
  2781. mi2s_rx_sample_rate_put),
  2782. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2783. mi2s_rx_sample_rate_get,
  2784. mi2s_rx_sample_rate_put),
  2785. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2786. mi2s_rx_sample_rate_get,
  2787. mi2s_rx_sample_rate_put),
  2788. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2789. mi2s_tx_sample_rate_get,
  2790. mi2s_tx_sample_rate_put),
  2791. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2792. mi2s_tx_sample_rate_get,
  2793. mi2s_tx_sample_rate_put),
  2794. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2795. mi2s_tx_sample_rate_get,
  2796. mi2s_tx_sample_rate_put),
  2797. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2798. mi2s_tx_sample_rate_get,
  2799. mi2s_tx_sample_rate_put),
  2800. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2801. mi2s_tx_sample_rate_get,
  2802. mi2s_tx_sample_rate_put),
  2803. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2804. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2805. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2806. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2807. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2808. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2809. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2810. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2811. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2812. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2813. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2814. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2815. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2816. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2817. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2818. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2819. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2820. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2821. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2822. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2823. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2824. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2825. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2826. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2827. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2828. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2829. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2830. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2831. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2832. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2833. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2834. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2835. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2836. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2837. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2838. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2839. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2840. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2841. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2842. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2843. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2844. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2845. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2846. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2847. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2848. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2849. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2850. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2851. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2852. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2853. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2854. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2855. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2856. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2857. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2858. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2859. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2860. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2861. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2862. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2863. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  2864. msm_snd_vad_cfg_put),
  2865. };
  2866. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2867. int enable, bool dapm)
  2868. {
  2869. int ret = 0;
  2870. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2871. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2872. } else {
  2873. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2874. __func__);
  2875. ret = -EINVAL;
  2876. }
  2877. return ret;
  2878. }
  2879. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2880. int enable, bool dapm)
  2881. {
  2882. int ret = 0;
  2883. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2884. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2885. } else {
  2886. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2887. __func__);
  2888. ret = -EINVAL;
  2889. }
  2890. return ret;
  2891. }
  2892. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2893. struct snd_kcontrol *kcontrol, int event)
  2894. {
  2895. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2896. pr_debug("%s: event = %d\n", __func__, event);
  2897. switch (event) {
  2898. case SND_SOC_DAPM_PRE_PMU:
  2899. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2900. case SND_SOC_DAPM_POST_PMD:
  2901. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2902. }
  2903. return 0;
  2904. }
  2905. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2906. struct snd_kcontrol *kcontrol, int event)
  2907. {
  2908. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2909. pr_debug("%s: event = %d\n", __func__, event);
  2910. switch (event) {
  2911. case SND_SOC_DAPM_PRE_PMU:
  2912. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2913. case SND_SOC_DAPM_POST_PMD:
  2914. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2915. }
  2916. return 0;
  2917. }
  2918. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2919. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2920. msm_mclk_event,
  2921. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2922. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2923. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2924. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2925. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2926. };
  2927. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2928. struct snd_kcontrol *kcontrol, int event)
  2929. {
  2930. struct msm_asoc_mach_data *pdata = NULL;
  2931. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2932. int ret = 0;
  2933. uint32_t dmic_idx;
  2934. int *dmic_gpio_cnt;
  2935. struct device_node *dmic_gpio;
  2936. char *wname;
  2937. wname = strpbrk(w->name, "01234567");
  2938. if (!wname) {
  2939. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2940. return -EINVAL;
  2941. }
  2942. ret = kstrtouint(wname, 10, &dmic_idx);
  2943. if (ret < 0) {
  2944. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2945. __func__);
  2946. return -EINVAL;
  2947. }
  2948. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2949. switch (dmic_idx) {
  2950. case 0:
  2951. case 1:
  2952. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2953. dmic_gpio = pdata->dmic_01_gpio_p;
  2954. break;
  2955. case 2:
  2956. case 3:
  2957. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2958. dmic_gpio = pdata->dmic_23_gpio_p;
  2959. break;
  2960. case 4:
  2961. case 5:
  2962. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2963. dmic_gpio = pdata->dmic_45_gpio_p;
  2964. break;
  2965. case 6:
  2966. case 7:
  2967. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2968. dmic_gpio = pdata->dmic_67_gpio_p;
  2969. break;
  2970. default:
  2971. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2972. __func__);
  2973. return -EINVAL;
  2974. }
  2975. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2976. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2977. switch (event) {
  2978. case SND_SOC_DAPM_PRE_PMU:
  2979. (*dmic_gpio_cnt)++;
  2980. if (*dmic_gpio_cnt == 1) {
  2981. ret = msm_cdc_pinctrl_select_active_state(
  2982. dmic_gpio);
  2983. if (ret < 0) {
  2984. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2985. __func__, "dmic_gpio");
  2986. return ret;
  2987. }
  2988. }
  2989. break;
  2990. case SND_SOC_DAPM_POST_PMD:
  2991. (*dmic_gpio_cnt)--;
  2992. if (*dmic_gpio_cnt == 0) {
  2993. ret = msm_cdc_pinctrl_select_sleep_state(
  2994. dmic_gpio);
  2995. if (ret < 0) {
  2996. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  2997. __func__, "dmic_gpio");
  2998. return ret;
  2999. }
  3000. }
  3001. break;
  3002. default:
  3003. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3004. __func__, event);
  3005. return -EINVAL;
  3006. }
  3007. return 0;
  3008. }
  3009. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3010. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3011. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3012. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3013. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3014. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3015. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3016. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3017. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3018. };
  3019. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3020. };
  3021. static inline int param_is_mask(int p)
  3022. {
  3023. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3024. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3025. }
  3026. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3027. int n)
  3028. {
  3029. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3030. }
  3031. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3032. unsigned int bit)
  3033. {
  3034. if (bit >= SNDRV_MASK_MAX)
  3035. return;
  3036. if (param_is_mask(n)) {
  3037. struct snd_mask *m = param_to_mask(p, n);
  3038. m->bits[0] = 0;
  3039. m->bits[1] = 0;
  3040. m->bits[bit >> 5] |= (1 << (bit & 31));
  3041. }
  3042. }
  3043. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3044. {
  3045. int ch_id = 0;
  3046. switch (be_id) {
  3047. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3048. ch_id = SLIM_RX_0;
  3049. break;
  3050. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3051. ch_id = SLIM_RX_1;
  3052. break;
  3053. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3054. ch_id = SLIM_RX_2;
  3055. break;
  3056. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3057. ch_id = SLIM_RX_3;
  3058. break;
  3059. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3060. ch_id = SLIM_RX_4;
  3061. break;
  3062. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3063. ch_id = SLIM_RX_6;
  3064. break;
  3065. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3066. ch_id = SLIM_TX_0;
  3067. break;
  3068. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3069. ch_id = SLIM_TX_3;
  3070. break;
  3071. default:
  3072. ch_id = SLIM_RX_0;
  3073. break;
  3074. }
  3075. return ch_id;
  3076. }
  3077. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3078. {
  3079. *port_id = 0xFFFF;
  3080. switch (be_id) {
  3081. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3082. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3083. break;
  3084. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3085. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3086. break;
  3087. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3088. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3089. break;
  3090. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3091. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3092. break;
  3093. default:
  3094. return -EINVAL;
  3095. }
  3096. return 0;
  3097. }
  3098. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3099. {
  3100. int idx = 0;
  3101. switch (be_id) {
  3102. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3103. idx = WSA_CDC_DMA_RX_0;
  3104. break;
  3105. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3106. idx = WSA_CDC_DMA_TX_0;
  3107. break;
  3108. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3109. idx = WSA_CDC_DMA_RX_1;
  3110. break;
  3111. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3112. idx = WSA_CDC_DMA_TX_1;
  3113. break;
  3114. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3115. idx = WSA_CDC_DMA_TX_2;
  3116. break;
  3117. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3118. idx = VA_CDC_DMA_TX_0;
  3119. break;
  3120. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3121. idx = VA_CDC_DMA_TX_1;
  3122. break;
  3123. default:
  3124. idx = VA_CDC_DMA_TX_0;
  3125. break;
  3126. }
  3127. return idx;
  3128. }
  3129. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3130. struct snd_pcm_hw_params *params)
  3131. {
  3132. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3133. struct snd_interval *rate = hw_param_interval(params,
  3134. SNDRV_PCM_HW_PARAM_RATE);
  3135. struct snd_interval *channels = hw_param_interval(params,
  3136. SNDRV_PCM_HW_PARAM_CHANNELS);
  3137. int rc = 0;
  3138. int idx;
  3139. void *config = NULL;
  3140. struct snd_soc_codec *codec = NULL;
  3141. pr_debug("%s: format = %d, rate = %d\n",
  3142. __func__, params_format(params), params_rate(params));
  3143. switch (dai_link->id) {
  3144. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3145. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3146. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3147. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3148. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3149. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3150. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3151. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3152. slim_rx_cfg[idx].bit_format);
  3153. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3154. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3155. break;
  3156. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3157. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3158. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3159. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3160. slim_tx_cfg[idx].bit_format);
  3161. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3162. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3163. break;
  3164. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3165. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3166. slim_tx_cfg[1].bit_format);
  3167. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3168. channels->min = channels->max = slim_tx_cfg[1].channels;
  3169. break;
  3170. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3171. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3172. SNDRV_PCM_FORMAT_S32_LE);
  3173. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3174. channels->min = channels->max = msm_vi_feed_tx_ch;
  3175. break;
  3176. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3177. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3178. slim_rx_cfg[5].bit_format);
  3179. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3180. channels->min = channels->max = slim_rx_cfg[5].channels;
  3181. break;
  3182. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3183. codec = rtd->codec;
  3184. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3185. channels->min = channels->max = 1;
  3186. config = msm_codec_fn.get_afe_config_fn(codec,
  3187. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3188. if (config) {
  3189. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3190. config, SLIMBUS_5_TX);
  3191. if (rc)
  3192. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3193. __func__, rc);
  3194. }
  3195. break;
  3196. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3197. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3198. slim_rx_cfg[SLIM_RX_7].bit_format);
  3199. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3200. channels->min = channels->max =
  3201. slim_rx_cfg[SLIM_RX_7].channels;
  3202. break;
  3203. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3204. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3205. channels->min = channels->max =
  3206. slim_tx_cfg[SLIM_TX_7].channels;
  3207. break;
  3208. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3209. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3210. channels->min = channels->max =
  3211. slim_tx_cfg[SLIM_TX_8].channels;
  3212. break;
  3213. case MSM_BACKEND_DAI_USB_RX:
  3214. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3215. usb_rx_cfg.bit_format);
  3216. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3217. channels->min = channels->max = usb_rx_cfg.channels;
  3218. break;
  3219. case MSM_BACKEND_DAI_USB_TX:
  3220. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3221. usb_tx_cfg.bit_format);
  3222. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3223. channels->min = channels->max = usb_tx_cfg.channels;
  3224. break;
  3225. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3226. channels->min = channels->max = proxy_rx_cfg.channels;
  3227. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3228. break;
  3229. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3230. channels->min = channels->max =
  3231. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3232. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3233. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3234. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3235. break;
  3236. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3237. channels->min = channels->max =
  3238. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3239. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3240. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3241. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3242. break;
  3243. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3244. channels->min = channels->max =
  3245. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3246. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3247. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3248. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3249. break;
  3250. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3251. channels->min = channels->max =
  3252. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3253. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3254. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3255. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3256. break;
  3257. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3258. channels->min = channels->max =
  3259. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3260. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3261. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3262. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3263. break;
  3264. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3265. channels->min = channels->max =
  3266. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3267. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3268. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3269. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3270. break;
  3271. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3272. channels->min = channels->max =
  3273. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3274. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3275. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3276. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3277. break;
  3278. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3279. channels->min = channels->max =
  3280. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3281. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3282. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3283. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3284. break;
  3285. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3286. channels->min = channels->max =
  3287. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3288. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3289. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3290. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3291. break;
  3292. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3293. channels->min = channels->max =
  3294. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3295. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3296. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3297. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3298. break;
  3299. case MSM_BACKEND_DAI_AUXPCM_RX:
  3300. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3301. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3302. rate->min = rate->max =
  3303. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3304. channels->min = channels->max =
  3305. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3306. break;
  3307. case MSM_BACKEND_DAI_AUXPCM_TX:
  3308. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3309. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3310. rate->min = rate->max =
  3311. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3312. channels->min = channels->max =
  3313. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3314. break;
  3315. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3316. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3317. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3318. rate->min = rate->max =
  3319. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3320. channels->min = channels->max =
  3321. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3322. break;
  3323. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3324. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3325. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3326. rate->min = rate->max =
  3327. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3328. channels->min = channels->max =
  3329. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3330. break;
  3331. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3332. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3333. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3334. rate->min = rate->max =
  3335. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3336. channels->min = channels->max =
  3337. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3338. break;
  3339. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3340. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3341. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3342. rate->min = rate->max =
  3343. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3344. channels->min = channels->max =
  3345. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3346. break;
  3347. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3348. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3349. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3350. rate->min = rate->max =
  3351. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3352. channels->min = channels->max =
  3353. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3354. break;
  3355. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3356. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3357. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3358. rate->min = rate->max =
  3359. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3360. channels->min = channels->max =
  3361. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3362. break;
  3363. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3364. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3365. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3366. rate->min = rate->max =
  3367. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3368. channels->min = channels->max =
  3369. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3370. break;
  3371. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3372. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3373. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3374. rate->min = rate->max =
  3375. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3376. channels->min = channels->max =
  3377. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3378. break;
  3379. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3380. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3381. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3382. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3383. channels->min = channels->max =
  3384. mi2s_rx_cfg[PRIM_MI2S].channels;
  3385. break;
  3386. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3387. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3388. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3389. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3390. channels->min = channels->max =
  3391. mi2s_tx_cfg[PRIM_MI2S].channels;
  3392. break;
  3393. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3394. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3395. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3396. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3397. channels->min = channels->max =
  3398. mi2s_rx_cfg[SEC_MI2S].channels;
  3399. break;
  3400. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3401. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3402. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3403. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3404. channels->min = channels->max =
  3405. mi2s_tx_cfg[SEC_MI2S].channels;
  3406. break;
  3407. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3408. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3409. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3410. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3411. channels->min = channels->max =
  3412. mi2s_rx_cfg[TERT_MI2S].channels;
  3413. break;
  3414. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3415. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3416. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3417. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3418. channels->min = channels->max =
  3419. mi2s_tx_cfg[TERT_MI2S].channels;
  3420. break;
  3421. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3422. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3423. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3424. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3425. channels->min = channels->max =
  3426. mi2s_rx_cfg[QUAT_MI2S].channels;
  3427. break;
  3428. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3429. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3430. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3431. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3432. channels->min = channels->max =
  3433. mi2s_tx_cfg[QUAT_MI2S].channels;
  3434. break;
  3435. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3436. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3437. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3438. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3439. channels->min = channels->max =
  3440. mi2s_rx_cfg[QUIN_MI2S].channels;
  3441. break;
  3442. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3443. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3444. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3445. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3446. channels->min = channels->max =
  3447. mi2s_tx_cfg[QUIN_MI2S].channels;
  3448. break;
  3449. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3450. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3451. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3452. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3453. cdc_dma_rx_cfg[idx].bit_format);
  3454. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3455. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3456. break;
  3457. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3458. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3459. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3460. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3461. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3462. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3463. cdc_dma_tx_cfg[idx].bit_format);
  3464. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3465. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3466. break;
  3467. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3468. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3469. SNDRV_PCM_FORMAT_S32_LE);
  3470. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3471. channels->min = channels->max = msm_vi_feed_tx_ch;
  3472. break;
  3473. default:
  3474. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3475. break;
  3476. }
  3477. return rc;
  3478. }
  3479. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3480. {
  3481. int ret = 0;
  3482. void *config_data = NULL;
  3483. if (!msm_codec_fn.get_afe_config_fn) {
  3484. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3485. __func__);
  3486. return -EINVAL;
  3487. }
  3488. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3489. AFE_CDC_REGISTERS_CONFIG);
  3490. if (config_data) {
  3491. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3492. if (ret) {
  3493. dev_err(codec->dev,
  3494. "%s: Failed to set codec registers config %d\n",
  3495. __func__, ret);
  3496. return ret;
  3497. }
  3498. }
  3499. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3500. AFE_CDC_REGISTER_PAGE_CONFIG);
  3501. if (config_data) {
  3502. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3503. 0);
  3504. if (ret)
  3505. dev_err(codec->dev,
  3506. "%s: Failed to set cdc register page config\n",
  3507. __func__);
  3508. }
  3509. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3510. AFE_SLIMBUS_SLAVE_CONFIG);
  3511. if (config_data) {
  3512. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3513. if (ret) {
  3514. dev_err(codec->dev,
  3515. "%s: Failed to set slimbus slave config %d\n",
  3516. __func__, ret);
  3517. return ret;
  3518. }
  3519. }
  3520. return 0;
  3521. }
  3522. static void msm_afe_clear_config(void)
  3523. {
  3524. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3525. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3526. }
  3527. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3528. struct snd_card *card)
  3529. {
  3530. int ret = 0;
  3531. unsigned long timeout;
  3532. int adsp_ready = 0;
  3533. bool snd_card_online = 0;
  3534. timeout = jiffies +
  3535. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3536. do {
  3537. if (!snd_card_online) {
  3538. snd_card_online = snd_card_is_online_state(card);
  3539. pr_debug("%s: Sound card is %s\n", __func__,
  3540. snd_card_online ? "Online" : "Offline");
  3541. }
  3542. if (!adsp_ready) {
  3543. adsp_ready = q6core_is_adsp_ready();
  3544. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3545. adsp_ready ? "ready" : "not ready");
  3546. }
  3547. if (snd_card_online && adsp_ready)
  3548. break;
  3549. /*
  3550. * Sound card/ADSP will be coming up after subsystem restart and
  3551. * it might not be fully up when the control reaches
  3552. * here. So, wait for 50msec before checking ADSP state
  3553. */
  3554. msleep(50);
  3555. } while (time_after(timeout, jiffies));
  3556. if (!snd_card_online || !adsp_ready) {
  3557. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3558. __func__,
  3559. snd_card_online ? "Online" : "Offline",
  3560. adsp_ready ? "ready" : "not ready");
  3561. ret = -ETIMEDOUT;
  3562. goto err;
  3563. }
  3564. ret = msm_afe_set_config(codec);
  3565. if (ret)
  3566. pr_err("%s: Failed to set AFE config. err %d\n",
  3567. __func__, ret);
  3568. return 0;
  3569. err:
  3570. return ret;
  3571. }
  3572. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3573. unsigned long opcode, void *ptr)
  3574. {
  3575. int ret;
  3576. struct snd_soc_card *card = NULL;
  3577. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3578. struct snd_soc_pcm_runtime *rtd;
  3579. struct snd_soc_codec *codec;
  3580. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3581. switch (opcode) {
  3582. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3583. /*
  3584. * Use flag to ignore initial boot notifications
  3585. * On initial boot msm_adsp_power_up_config is
  3586. * called on init. There is no need to clear
  3587. * and set the config again on initial boot.
  3588. */
  3589. if (is_initial_boot)
  3590. break;
  3591. msm_afe_clear_config();
  3592. break;
  3593. case AUDIO_NOTIFIER_SERVICE_UP:
  3594. if (is_initial_boot) {
  3595. is_initial_boot = false;
  3596. break;
  3597. }
  3598. if (!spdev)
  3599. return -EINVAL;
  3600. card = platform_get_drvdata(spdev);
  3601. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3602. if (!rtd) {
  3603. dev_err(card->dev,
  3604. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3605. __func__, be_dl_name);
  3606. ret = -EINVAL;
  3607. goto err;
  3608. }
  3609. codec = rtd->codec;
  3610. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3611. if (ret < 0) {
  3612. dev_err(card->dev,
  3613. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3614. __func__, ret);
  3615. goto err;
  3616. }
  3617. break;
  3618. default:
  3619. break;
  3620. }
  3621. err:
  3622. return NOTIFY_OK;
  3623. }
  3624. static struct notifier_block service_nb = {
  3625. .notifier_call = qcs405_notifier_service_cb,
  3626. .priority = -INT_MAX,
  3627. };
  3628. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3629. {
  3630. int ret = 0;
  3631. void *config_data;
  3632. struct snd_soc_codec *codec = rtd->codec;
  3633. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3634. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3635. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3636. struct snd_card *card;
  3637. struct snd_info_entry *entry;
  3638. struct msm_asoc_mach_data *pdata =
  3639. snd_soc_card_get_drvdata(rtd->card);
  3640. /*
  3641. * Codec SLIMBUS configuration
  3642. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3643. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3644. * TX14, TX15, TX16
  3645. */
  3646. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3647. 151, 152, 153, 154, 155, 156};
  3648. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3649. 134, 135, 136, 137, 138, 139,
  3650. 140, 141, 142, 143};
  3651. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3652. rtd->pmdown_time = 0;
  3653. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3654. ARRAY_SIZE(msm_snd_sb_controls));
  3655. if (ret < 0) {
  3656. pr_err("%s: add_codec_controls failed, err %d\n",
  3657. __func__, ret);
  3658. return ret;
  3659. }
  3660. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3661. ARRAY_SIZE(msm_dapm_widgets));
  3662. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3663. ARRAY_SIZE(wcd_audio_paths));
  3664. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3665. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3666. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3667. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3668. snd_soc_dapm_sync(dapm);
  3669. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3670. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3671. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3672. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3673. if (ret) {
  3674. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3675. __func__, ret);
  3676. goto err;
  3677. }
  3678. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3679. AFE_AANC_VERSION);
  3680. if (config_data) {
  3681. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3682. if (ret) {
  3683. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3684. __func__, ret);
  3685. goto err;
  3686. }
  3687. }
  3688. card = rtd->card->snd_card;
  3689. entry = snd_info_create_subdir(card->module, "codecs",
  3690. card->proc_root);
  3691. if (!entry) {
  3692. pr_debug("%s: Cannot create codecs module entry\n",
  3693. __func__);
  3694. ret = 0;
  3695. goto err;
  3696. }
  3697. pdata->codec_root = entry;
  3698. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3699. codec_reg_done = true;
  3700. return 0;
  3701. err:
  3702. return ret;
  3703. }
  3704. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3705. {
  3706. int ret = 0;
  3707. struct snd_soc_codec *codec = rtd->codec;
  3708. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3709. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3710. ARRAY_SIZE(msm_snd_va_controls));
  3711. if (ret < 0) {
  3712. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3713. __func__, ret);
  3714. return ret;
  3715. }
  3716. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3717. ARRAY_SIZE(msm_va_dapm_widgets));
  3718. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3719. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3720. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3721. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3722. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3723. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3724. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3725. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3726. snd_soc_dapm_sync(dapm);
  3727. return ret;
  3728. }
  3729. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3730. {
  3731. int ret = 0;
  3732. struct snd_soc_codec *codec = rtd->codec;
  3733. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3734. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3735. ARRAY_SIZE(msm_snd_wsa_controls));
  3736. if (ret < 0) {
  3737. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3738. __func__, ret);
  3739. return ret;
  3740. }
  3741. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3742. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3743. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3744. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3745. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3746. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3747. snd_soc_dapm_sync(dapm);
  3748. return ret;
  3749. }
  3750. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3751. {
  3752. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3753. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3754. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3755. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3756. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3757. }
  3758. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3759. struct snd_pcm_hw_params *params)
  3760. {
  3761. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3762. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3763. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3764. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3765. int ret = 0;
  3766. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3767. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3768. u32 user_set_tx_ch = 0;
  3769. u32 rx_ch_count;
  3770. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3771. ret = snd_soc_dai_get_channel_map(codec_dai,
  3772. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3773. if (ret < 0) {
  3774. pr_err("%s: failed to get codec chan map, err:%d\n",
  3775. __func__, ret);
  3776. goto err;
  3777. }
  3778. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3779. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3780. slim_rx_cfg[5].channels);
  3781. rx_ch_count = slim_rx_cfg[5].channels;
  3782. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3783. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3784. slim_rx_cfg[2].channels);
  3785. rx_ch_count = slim_rx_cfg[2].channels;
  3786. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3787. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3788. slim_rx_cfg[6].channels);
  3789. rx_ch_count = slim_rx_cfg[6].channels;
  3790. } else {
  3791. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3792. slim_rx_cfg[0].channels);
  3793. rx_ch_count = slim_rx_cfg[0].channels;
  3794. }
  3795. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3796. rx_ch_count, rx_ch);
  3797. if (ret < 0) {
  3798. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3799. __func__, ret);
  3800. goto err;
  3801. }
  3802. } else {
  3803. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3804. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3805. ret = snd_soc_dai_get_channel_map(codec_dai,
  3806. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3807. if (ret < 0) {
  3808. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3809. __func__, ret);
  3810. goto err;
  3811. }
  3812. /* For <codec>_tx1 case */
  3813. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3814. user_set_tx_ch = slim_tx_cfg[0].channels;
  3815. /* For <codec>_tx3 case */
  3816. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3817. user_set_tx_ch = slim_tx_cfg[1].channels;
  3818. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3819. user_set_tx_ch = msm_vi_feed_tx_ch;
  3820. else
  3821. user_set_tx_ch = tx_ch_cnt;
  3822. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3823. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3824. tx_ch_cnt, dai_link->id);
  3825. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3826. user_set_tx_ch, tx_ch, 0, 0);
  3827. if (ret < 0)
  3828. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3829. __func__, ret);
  3830. }
  3831. err:
  3832. return ret;
  3833. }
  3834. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3835. struct snd_pcm_hw_params *params)
  3836. {
  3837. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3838. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3839. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3840. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3841. int ret = 0;
  3842. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3843. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3844. u32 user_set_tx_ch = 0;
  3845. u32 user_set_rx_ch = 0;
  3846. u32 ch_id;
  3847. ret = snd_soc_dai_get_channel_map(codec_dai,
  3848. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3849. &rx_ch_cdc_dma);
  3850. if (ret < 0) {
  3851. pr_err("%s: failed to get codec chan map, err:%d\n",
  3852. __func__, ret);
  3853. goto err;
  3854. }
  3855. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3856. switch (dai_link->id) {
  3857. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3858. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3859. {
  3860. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3861. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3862. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3863. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3864. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3865. user_set_rx_ch, &rx_ch_cdc_dma);
  3866. if (ret < 0) {
  3867. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3868. __func__, ret);
  3869. goto err;
  3870. }
  3871. }
  3872. break;
  3873. }
  3874. } else {
  3875. switch (dai_link->id) {
  3876. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3877. {
  3878. user_set_tx_ch = msm_vi_feed_tx_ch;
  3879. }
  3880. break;
  3881. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3882. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3883. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3884. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3885. {
  3886. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3887. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3888. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3889. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3890. }
  3891. break;
  3892. }
  3893. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3894. &tx_ch_cdc_dma, 0, 0);
  3895. if (ret < 0) {
  3896. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3897. __func__, ret);
  3898. goto err;
  3899. }
  3900. }
  3901. err:
  3902. return ret;
  3903. }
  3904. static int msm_slimbus_2_hw_params(struct snd_pcm_substream *substream,
  3905. struct snd_pcm_hw_params *params)
  3906. {
  3907. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3908. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3909. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3910. unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3911. unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
  3912. unsigned int num_tx_ch = 0;
  3913. unsigned int num_rx_ch = 0;
  3914. int ret = 0;
  3915. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3916. num_rx_ch = params_channels(params);
  3917. pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__,
  3918. codec_dai->name, codec_dai->id, num_rx_ch);
  3919. ret = snd_soc_dai_get_channel_map(codec_dai,
  3920. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3921. if (ret < 0) {
  3922. pr_err("%s: failed to get codec chan map, err:%d\n",
  3923. __func__, ret);
  3924. goto err;
  3925. }
  3926. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3927. num_rx_ch, rx_ch);
  3928. if (ret < 0) {
  3929. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3930. __func__, ret);
  3931. goto err;
  3932. }
  3933. } else {
  3934. num_tx_ch = params_channels(params);
  3935. pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__,
  3936. codec_dai->name, codec_dai->id, num_tx_ch);
  3937. ret = snd_soc_dai_get_channel_map(codec_dai,
  3938. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3939. if (ret < 0) {
  3940. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3941. __func__, ret);
  3942. goto err;
  3943. }
  3944. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3945. num_tx_ch, tx_ch, 0, 0);
  3946. if (ret < 0) {
  3947. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3948. __func__, ret);
  3949. goto err;
  3950. }
  3951. }
  3952. err:
  3953. return ret;
  3954. }
  3955. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3956. struct snd_pcm_hw_params *params)
  3957. {
  3958. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3959. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3960. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3961. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3962. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3963. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3964. int ret;
  3965. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3966. codec_dai->name, codec_dai->id);
  3967. ret = snd_soc_dai_get_channel_map(codec_dai,
  3968. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3969. if (ret) {
  3970. dev_err(rtd->dev,
  3971. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3972. __func__, ret);
  3973. goto err;
  3974. }
  3975. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3976. __func__, tx_ch_cnt, dai_link->id);
  3977. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3978. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3979. if (ret)
  3980. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3981. __func__, ret);
  3982. err:
  3983. return ret;
  3984. }
  3985. static int msm_get_port_id(int be_id)
  3986. {
  3987. int afe_port_id;
  3988. switch (be_id) {
  3989. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3990. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3991. break;
  3992. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3993. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3994. break;
  3995. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3996. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3997. break;
  3998. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3999. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4000. break;
  4001. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4002. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4003. break;
  4004. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4005. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4006. break;
  4007. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4008. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4009. break;
  4010. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4011. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4012. break;
  4013. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4014. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4015. break;
  4016. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4017. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4018. break;
  4019. default:
  4020. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4021. afe_port_id = -EINVAL;
  4022. }
  4023. return afe_port_id;
  4024. }
  4025. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4026. {
  4027. u32 bit_per_sample;
  4028. switch (bit_format) {
  4029. case SNDRV_PCM_FORMAT_S32_LE:
  4030. case SNDRV_PCM_FORMAT_S24_3LE:
  4031. case SNDRV_PCM_FORMAT_S24_LE:
  4032. bit_per_sample = 32;
  4033. break;
  4034. case SNDRV_PCM_FORMAT_S16_LE:
  4035. default:
  4036. bit_per_sample = 16;
  4037. break;
  4038. }
  4039. return bit_per_sample;
  4040. }
  4041. static void update_mi2s_clk_val(int dai_id, int stream)
  4042. {
  4043. u32 bit_per_sample;
  4044. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4045. bit_per_sample =
  4046. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4047. mi2s_clk[dai_id].clk_freq_in_hz =
  4048. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4049. } else {
  4050. bit_per_sample =
  4051. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4052. mi2s_clk[dai_id].clk_freq_in_hz =
  4053. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4054. }
  4055. }
  4056. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4057. {
  4058. int ret = 0;
  4059. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4060. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4061. int port_id = 0;
  4062. int index = cpu_dai->id;
  4063. port_id = msm_get_port_id(rtd->dai_link->id);
  4064. if (port_id < 0) {
  4065. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4066. ret = port_id;
  4067. goto err;
  4068. }
  4069. if (enable) {
  4070. update_mi2s_clk_val(index, substream->stream);
  4071. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4072. mi2s_clk[index].clk_freq_in_hz);
  4073. }
  4074. mi2s_clk[index].enable = enable;
  4075. ret = afe_set_lpass_clock_v2(port_id,
  4076. &mi2s_clk[index]);
  4077. if (ret < 0) {
  4078. dev_err(rtd->card->dev,
  4079. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4080. __func__, port_id, ret);
  4081. goto err;
  4082. }
  4083. err:
  4084. return ret;
  4085. }
  4086. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4087. enum pinctrl_pin_state new_state)
  4088. {
  4089. int ret = 0;
  4090. int curr_state = 0;
  4091. if (pinctrl_info == NULL) {
  4092. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4093. ret = -EINVAL;
  4094. goto err;
  4095. }
  4096. if (pinctrl_info->pinctrl == NULL) {
  4097. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4098. ret = -EINVAL;
  4099. goto err;
  4100. }
  4101. curr_state = pinctrl_info->curr_state;
  4102. pinctrl_info->curr_state = new_state;
  4103. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4104. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4105. if (curr_state == pinctrl_info->curr_state) {
  4106. pr_debug("%s: Already in same state\n", __func__);
  4107. goto err;
  4108. }
  4109. if (curr_state != STATE_DISABLE &&
  4110. pinctrl_info->curr_state != STATE_DISABLE) {
  4111. pr_debug("%s: state already active cannot switch\n", __func__);
  4112. ret = -EIO;
  4113. goto err;
  4114. }
  4115. switch (pinctrl_info->curr_state) {
  4116. case STATE_MI2S_ACTIVE:
  4117. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4118. pinctrl_info->mi2s_active);
  4119. if (ret) {
  4120. pr_err("%s: MI2S state select failed with %d\n",
  4121. __func__, ret);
  4122. ret = -EIO;
  4123. goto err;
  4124. }
  4125. break;
  4126. case STATE_TDM_ACTIVE:
  4127. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4128. pinctrl_info->tdm_active);
  4129. if (ret) {
  4130. pr_err("%s: TDM state select failed with %d\n",
  4131. __func__, ret);
  4132. ret = -EIO;
  4133. goto err;
  4134. }
  4135. break;
  4136. case STATE_DISABLE:
  4137. if (curr_state == STATE_MI2S_ACTIVE) {
  4138. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4139. pinctrl_info->mi2s_disable);
  4140. } else {
  4141. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4142. pinctrl_info->tdm_disable);
  4143. }
  4144. if (ret) {
  4145. pr_err("%s: state disable failed with %d\n",
  4146. __func__, ret);
  4147. ret = -EIO;
  4148. goto err;
  4149. }
  4150. break;
  4151. default:
  4152. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4153. return -EINVAL;
  4154. }
  4155. err:
  4156. return ret;
  4157. }
  4158. static void msm_release_pinctrl(struct platform_device *pdev)
  4159. {
  4160. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4161. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4162. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4163. if (pinctrl_info->pinctrl) {
  4164. devm_pinctrl_put(pinctrl_info->pinctrl);
  4165. pinctrl_info->pinctrl = NULL;
  4166. }
  4167. }
  4168. static int msm_get_pinctrl(struct platform_device *pdev)
  4169. {
  4170. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4171. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4172. struct msm_pinctrl_info *pinctrl_info = NULL;
  4173. struct pinctrl *pinctrl;
  4174. int ret;
  4175. pinctrl_info = &pdata->pinctrl_info;
  4176. if (pinctrl_info == NULL) {
  4177. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4178. return -EINVAL;
  4179. }
  4180. pinctrl = devm_pinctrl_get(&pdev->dev);
  4181. if (IS_ERR_OR_NULL(pinctrl)) {
  4182. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4183. return -EINVAL;
  4184. }
  4185. pinctrl_info->pinctrl = pinctrl;
  4186. /* get all the states handles from Device Tree */
  4187. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4188. "quat-mi2s-sleep");
  4189. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4190. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4191. goto err;
  4192. }
  4193. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4194. "quat-mi2s-active");
  4195. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4196. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4197. goto err;
  4198. }
  4199. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4200. "quat-tdm-sleep");
  4201. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4202. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4203. goto err;
  4204. }
  4205. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4206. "quat-tdm-active");
  4207. if (IS_ERR(pinctrl_info->tdm_active)) {
  4208. pr_err("%s: could not get tdm_active pinstate\n",
  4209. __func__);
  4210. goto err;
  4211. }
  4212. /* Reset the TLMM pins to a default state */
  4213. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4214. pinctrl_info->mi2s_disable);
  4215. if (ret != 0) {
  4216. pr_err("%s: Disable TLMM pins failed with %d\n",
  4217. __func__, ret);
  4218. ret = -EIO;
  4219. goto err;
  4220. }
  4221. pinctrl_info->curr_state = STATE_DISABLE;
  4222. return 0;
  4223. err:
  4224. devm_pinctrl_put(pinctrl);
  4225. pinctrl_info->pinctrl = NULL;
  4226. return -EINVAL;
  4227. }
  4228. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4229. struct snd_pcm_hw_params *params)
  4230. {
  4231. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4232. struct snd_interval *rate = hw_param_interval(params,
  4233. SNDRV_PCM_HW_PARAM_RATE);
  4234. struct snd_interval *channels = hw_param_interval(params,
  4235. SNDRV_PCM_HW_PARAM_CHANNELS);
  4236. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4237. channels->min = channels->max =
  4238. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4239. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4240. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4241. rate->min = rate->max =
  4242. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4243. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4244. channels->min = channels->max =
  4245. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4246. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4247. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4248. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4249. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4250. channels->min = channels->max =
  4251. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4252. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4253. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4254. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4255. } else {
  4256. pr_err("%s: dai id 0x%x not supported\n",
  4257. __func__, cpu_dai->id);
  4258. return -EINVAL;
  4259. }
  4260. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4261. __func__, cpu_dai->id, channels->max, rate->max,
  4262. params_format(params));
  4263. return 0;
  4264. }
  4265. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4266. struct snd_pcm_hw_params *params)
  4267. {
  4268. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4269. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4270. int ret = 0;
  4271. int slot_width = 32;
  4272. int channels, slots;
  4273. unsigned int slot_mask, rate, clk_freq;
  4274. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4275. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4276. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4277. switch (cpu_dai->id) {
  4278. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4279. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4280. break;
  4281. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4282. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4283. break;
  4284. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4285. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4286. break;
  4287. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4288. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4289. break;
  4290. case AFE_PORT_ID_QUINARY_TDM_RX:
  4291. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4292. break;
  4293. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4294. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4295. break;
  4296. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4297. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4298. break;
  4299. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4300. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4301. break;
  4302. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4303. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4304. break;
  4305. case AFE_PORT_ID_QUINARY_TDM_TX:
  4306. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4307. break;
  4308. default:
  4309. pr_err("%s: dai id 0x%x not supported\n",
  4310. __func__, cpu_dai->id);
  4311. return -EINVAL;
  4312. }
  4313. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4314. /*2 slot config - bits 0 and 1 set for the first two slots */
  4315. slot_mask = 0x0000FFFF >> (16-slots);
  4316. channels = slots;
  4317. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4318. __func__, slot_width, slots);
  4319. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4320. slots, slot_width);
  4321. if (ret < 0) {
  4322. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4323. __func__, ret);
  4324. goto end;
  4325. }
  4326. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4327. 0, NULL, channels, slot_offset);
  4328. if (ret < 0) {
  4329. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4330. __func__, ret);
  4331. goto end;
  4332. }
  4333. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4334. /*2 slot config - bits 0 and 1 set for the first two slots */
  4335. slot_mask = 0x0000FFFF >> (16-slots);
  4336. channels = slots;
  4337. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4338. __func__, slot_width, slots);
  4339. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4340. slots, slot_width);
  4341. if (ret < 0) {
  4342. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4343. __func__, ret);
  4344. goto end;
  4345. }
  4346. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4347. channels, slot_offset, 0, NULL);
  4348. if (ret < 0) {
  4349. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4350. __func__, ret);
  4351. goto end;
  4352. }
  4353. } else {
  4354. ret = -EINVAL;
  4355. pr_err("%s: invalid use case, err:%d\n",
  4356. __func__, ret);
  4357. goto end;
  4358. }
  4359. rate = params_rate(params);
  4360. clk_freq = rate * slot_width * slots;
  4361. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4362. if (ret < 0)
  4363. pr_err("%s: failed to set tdm clk, err:%d\n",
  4364. __func__, ret);
  4365. end:
  4366. return ret;
  4367. }
  4368. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4369. {
  4370. int ret = 0;
  4371. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4372. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4373. struct snd_soc_card *card = rtd->card;
  4374. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4375. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4376. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4377. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4378. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4379. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4380. if (ret)
  4381. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4382. __func__, ret);
  4383. }
  4384. return ret;
  4385. }
  4386. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4387. {
  4388. int ret = 0;
  4389. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4390. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4391. struct snd_soc_card *card = rtd->card;
  4392. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4393. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4394. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4395. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4396. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4397. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4398. if (ret)
  4399. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4400. __func__, ret);
  4401. }
  4402. }
  4403. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4404. .hw_params = qcs405_tdm_snd_hw_params,
  4405. .startup = qcs405_tdm_snd_startup,
  4406. .shutdown = qcs405_tdm_snd_shutdown
  4407. };
  4408. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4409. {
  4410. cpumask_t mask;
  4411. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4412. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4413. cpumask_clear(&mask);
  4414. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4415. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4416. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4417. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4418. pm_qos_add_request(&substream->latency_pm_qos_req,
  4419. PM_QOS_CPU_DMA_LATENCY,
  4420. MSM_LL_QOS_VALUE);
  4421. return 0;
  4422. }
  4423. static struct snd_soc_ops msm_fe_qos_ops = {
  4424. .prepare = msm_fe_qos_prepare,
  4425. };
  4426. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4427. {
  4428. int ret = 0;
  4429. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4430. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4431. int index = cpu_dai->id;
  4432. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4433. struct snd_soc_card *card = rtd->card;
  4434. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4435. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4436. int ret_pinctrl = 0;
  4437. dev_dbg(rtd->card->dev,
  4438. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4439. __func__, substream->name, substream->stream,
  4440. cpu_dai->name, cpu_dai->id);
  4441. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4442. ret = -EINVAL;
  4443. dev_err(rtd->card->dev,
  4444. "%s: CPU DAI id (%d) out of range\n",
  4445. __func__, cpu_dai->id);
  4446. goto err;
  4447. }
  4448. /*
  4449. * Mutex protection in case the same MI2S
  4450. * interface using for both TX and RX so
  4451. * that the same clock won't be enable twice.
  4452. */
  4453. mutex_lock(&mi2s_intf_conf[index].lock);
  4454. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4455. /* Check if msm needs to provide the clock to the interface */
  4456. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4457. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4458. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4459. }
  4460. ret = msm_mi2s_set_sclk(substream, true);
  4461. if (ret < 0) {
  4462. dev_err(rtd->card->dev,
  4463. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4464. __func__, ret);
  4465. goto clean_up;
  4466. }
  4467. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4468. if (ret < 0) {
  4469. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4470. __func__, index, ret);
  4471. goto clk_off;
  4472. }
  4473. if (index == QUAT_MI2S) {
  4474. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4475. STATE_MI2S_ACTIVE);
  4476. if (ret_pinctrl)
  4477. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4478. __func__, ret_pinctrl);
  4479. }
  4480. }
  4481. clk_off:
  4482. if (ret < 0)
  4483. msm_mi2s_set_sclk(substream, false);
  4484. clean_up:
  4485. if (ret < 0)
  4486. mi2s_intf_conf[index].ref_cnt--;
  4487. mutex_unlock(&mi2s_intf_conf[index].lock);
  4488. err:
  4489. return ret;
  4490. }
  4491. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4492. {
  4493. int ret;
  4494. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4495. int index = rtd->cpu_dai->id;
  4496. struct snd_soc_card *card = rtd->card;
  4497. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4498. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4499. int ret_pinctrl = 0;
  4500. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4501. substream->name, substream->stream);
  4502. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4503. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4504. return;
  4505. }
  4506. mutex_lock(&mi2s_intf_conf[index].lock);
  4507. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4508. ret = msm_mi2s_set_sclk(substream, false);
  4509. if (ret < 0)
  4510. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4511. __func__, index, ret);
  4512. if (index == QUAT_MI2S) {
  4513. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4514. STATE_DISABLE);
  4515. if (ret_pinctrl)
  4516. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4517. __func__, ret_pinctrl);
  4518. }
  4519. }
  4520. mutex_unlock(&mi2s_intf_conf[index].lock);
  4521. }
  4522. static struct snd_soc_ops msm_mi2s_be_ops = {
  4523. .startup = msm_mi2s_snd_startup,
  4524. .shutdown = msm_mi2s_snd_shutdown,
  4525. };
  4526. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4527. .hw_params = msm_snd_cdc_dma_hw_params,
  4528. };
  4529. static struct snd_soc_ops msm_be_ops = {
  4530. .hw_params = msm_snd_hw_params,
  4531. };
  4532. static struct snd_soc_ops msm_slimbus_2_be_ops = {
  4533. .hw_params = msm_slimbus_2_hw_params,
  4534. };
  4535. static struct snd_soc_ops msm_wcn_ops = {
  4536. .hw_params = msm_wcn_hw_params,
  4537. };
  4538. /* Digital audio interface glue - connects codec <---> CPU */
  4539. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4540. /* FrontEnd DAI Links */
  4541. {
  4542. .name = MSM_DAILINK_NAME(Media1),
  4543. .stream_name = "MultiMedia1",
  4544. .cpu_dai_name = "MultiMedia1",
  4545. .platform_name = "msm-pcm-dsp.0",
  4546. .dynamic = 1,
  4547. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4548. .dpcm_playback = 1,
  4549. .dpcm_capture = 1,
  4550. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4551. SND_SOC_DPCM_TRIGGER_POST},
  4552. .codec_dai_name = "snd-soc-dummy-dai",
  4553. .codec_name = "snd-soc-dummy",
  4554. .ignore_suspend = 1,
  4555. /* this dainlink has playback support */
  4556. .ignore_pmdown_time = 1,
  4557. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4558. },
  4559. {
  4560. .name = MSM_DAILINK_NAME(Media2),
  4561. .stream_name = "MultiMedia2",
  4562. .cpu_dai_name = "MultiMedia2",
  4563. .platform_name = "msm-pcm-dsp.0",
  4564. .dynamic = 1,
  4565. .dpcm_playback = 1,
  4566. .dpcm_capture = 1,
  4567. .codec_dai_name = "snd-soc-dummy-dai",
  4568. .codec_name = "snd-soc-dummy",
  4569. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4570. SND_SOC_DPCM_TRIGGER_POST},
  4571. .ignore_suspend = 1,
  4572. /* this dainlink has playback support */
  4573. .ignore_pmdown_time = 1,
  4574. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4575. },
  4576. {
  4577. .name = "VoiceMMode1",
  4578. .stream_name = "VoiceMMode1",
  4579. .cpu_dai_name = "VoiceMMode1",
  4580. .platform_name = "msm-pcm-voice",
  4581. .dynamic = 1,
  4582. .dpcm_playback = 1,
  4583. .dpcm_capture = 1,
  4584. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4585. SND_SOC_DPCM_TRIGGER_POST},
  4586. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4587. .ignore_suspend = 1,
  4588. .ignore_pmdown_time = 1,
  4589. .codec_dai_name = "snd-soc-dummy-dai",
  4590. .codec_name = "snd-soc-dummy",
  4591. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4592. },
  4593. {
  4594. .name = "MSM VoIP",
  4595. .stream_name = "VoIP",
  4596. .cpu_dai_name = "VoIP",
  4597. .platform_name = "msm-voip-dsp",
  4598. .dynamic = 1,
  4599. .dpcm_playback = 1,
  4600. .dpcm_capture = 1,
  4601. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4602. SND_SOC_DPCM_TRIGGER_POST},
  4603. .codec_dai_name = "snd-soc-dummy-dai",
  4604. .codec_name = "snd-soc-dummy",
  4605. .ignore_suspend = 1,
  4606. /* this dainlink has playback support */
  4607. .ignore_pmdown_time = 1,
  4608. .id = MSM_FRONTEND_DAI_VOIP,
  4609. },
  4610. {
  4611. .name = MSM_DAILINK_NAME(ULL),
  4612. .stream_name = "MultiMedia3",
  4613. .cpu_dai_name = "MultiMedia3",
  4614. .platform_name = "msm-pcm-dsp.2",
  4615. .dynamic = 1,
  4616. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4617. .dpcm_playback = 1,
  4618. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4619. SND_SOC_DPCM_TRIGGER_POST},
  4620. .codec_dai_name = "snd-soc-dummy-dai",
  4621. .codec_name = "snd-soc-dummy",
  4622. .ignore_suspend = 1,
  4623. /* this dainlink has playback support */
  4624. .ignore_pmdown_time = 1,
  4625. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4626. },
  4627. /* Hostless PCM purpose */
  4628. {
  4629. .name = "SLIMBUS_0 Hostless",
  4630. .stream_name = "SLIMBUS_0 Hostless",
  4631. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4632. .platform_name = "msm-pcm-hostless",
  4633. .dynamic = 1,
  4634. .dpcm_playback = 1,
  4635. .dpcm_capture = 1,
  4636. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4637. SND_SOC_DPCM_TRIGGER_POST},
  4638. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4639. .ignore_suspend = 1,
  4640. /* this dailink has playback support */
  4641. .ignore_pmdown_time = 1,
  4642. .codec_dai_name = "snd-soc-dummy-dai",
  4643. .codec_name = "snd-soc-dummy",
  4644. },
  4645. /* Hostless PCM purpose */
  4646. {
  4647. .name = "CDC_DMA Hostless",
  4648. .stream_name = "CDC_DMA Hostless",
  4649. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  4650. .platform_name = "msm-pcm-hostless",
  4651. .dynamic = 1,
  4652. .dpcm_playback = 1,
  4653. .dpcm_capture = 1,
  4654. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4655. SND_SOC_DPCM_TRIGGER_POST},
  4656. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4657. .ignore_suspend = 1,
  4658. /* this dailink has playback support */
  4659. .ignore_pmdown_time = 1,
  4660. .codec_dai_name = "snd-soc-dummy-dai",
  4661. .codec_name = "snd-soc-dummy",
  4662. },
  4663. {
  4664. .name = "MSM AFE-PCM RX",
  4665. .stream_name = "AFE-PROXY RX",
  4666. .cpu_dai_name = "msm-dai-q6-dev.241",
  4667. .codec_name = "msm-stub-codec.1",
  4668. .codec_dai_name = "msm-stub-rx",
  4669. .platform_name = "msm-pcm-afe",
  4670. .dpcm_playback = 1,
  4671. .ignore_suspend = 1,
  4672. /* this dainlink has playback support */
  4673. .ignore_pmdown_time = 1,
  4674. },
  4675. {
  4676. .name = "MSM AFE-PCM TX",
  4677. .stream_name = "AFE-PROXY TX",
  4678. .cpu_dai_name = "msm-dai-q6-dev.240",
  4679. .codec_name = "msm-stub-codec.1",
  4680. .codec_dai_name = "msm-stub-tx",
  4681. .platform_name = "msm-pcm-afe",
  4682. .dpcm_capture = 1,
  4683. .ignore_suspend = 1,
  4684. },
  4685. {
  4686. .name = MSM_DAILINK_NAME(Compress1),
  4687. .stream_name = "Compress1",
  4688. .cpu_dai_name = "MultiMedia4",
  4689. .platform_name = "msm-compress-dsp",
  4690. .dynamic = 1,
  4691. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4692. .dpcm_playback = 1,
  4693. .dpcm_capture = 1,
  4694. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4695. SND_SOC_DPCM_TRIGGER_POST},
  4696. .codec_dai_name = "snd-soc-dummy-dai",
  4697. .codec_name = "snd-soc-dummy",
  4698. .ignore_suspend = 1,
  4699. .ignore_pmdown_time = 1,
  4700. /* this dainlink has playback support */
  4701. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4702. },
  4703. {
  4704. .name = "AUXPCM Hostless",
  4705. .stream_name = "AUXPCM Hostless",
  4706. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4707. .platform_name = "msm-pcm-hostless",
  4708. .dynamic = 1,
  4709. .dpcm_playback = 1,
  4710. .dpcm_capture = 1,
  4711. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4712. SND_SOC_DPCM_TRIGGER_POST},
  4713. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4714. .ignore_suspend = 1,
  4715. /* this dainlink has playback support */
  4716. .ignore_pmdown_time = 1,
  4717. .codec_dai_name = "snd-soc-dummy-dai",
  4718. .codec_name = "snd-soc-dummy",
  4719. },
  4720. {
  4721. .name = "SLIMBUS_1 Hostless",
  4722. .stream_name = "SLIMBUS_1 Hostless",
  4723. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4724. .platform_name = "msm-pcm-hostless",
  4725. .dynamic = 1,
  4726. .dpcm_playback = 1,
  4727. .dpcm_capture = 1,
  4728. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4729. SND_SOC_DPCM_TRIGGER_POST},
  4730. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4731. .ignore_suspend = 1,
  4732. /* this dailink has playback support */
  4733. .ignore_pmdown_time = 1,
  4734. .codec_dai_name = "snd-soc-dummy-dai",
  4735. .codec_name = "snd-soc-dummy",
  4736. },
  4737. {
  4738. .name = "SLIMBUS_3 Hostless",
  4739. .stream_name = "SLIMBUS_3 Hostless",
  4740. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4741. .platform_name = "msm-pcm-hostless",
  4742. .dynamic = 1,
  4743. .dpcm_playback = 1,
  4744. .dpcm_capture = 1,
  4745. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4746. SND_SOC_DPCM_TRIGGER_POST},
  4747. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4748. .ignore_suspend = 1,
  4749. /* this dailink has playback support */
  4750. .ignore_pmdown_time = 1,
  4751. .codec_dai_name = "snd-soc-dummy-dai",
  4752. .codec_name = "snd-soc-dummy",
  4753. },
  4754. {
  4755. .name = "SLIMBUS_4 Hostless",
  4756. .stream_name = "SLIMBUS_4 Hostless",
  4757. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4758. .platform_name = "msm-pcm-hostless",
  4759. .dynamic = 1,
  4760. .dpcm_playback = 1,
  4761. .dpcm_capture = 1,
  4762. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4763. SND_SOC_DPCM_TRIGGER_POST},
  4764. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4765. .ignore_suspend = 1,
  4766. /* this dailink has playback support */
  4767. .ignore_pmdown_time = 1,
  4768. .codec_dai_name = "snd-soc-dummy-dai",
  4769. .codec_name = "snd-soc-dummy",
  4770. },
  4771. {
  4772. .name = MSM_DAILINK_NAME(LowLatency),
  4773. .stream_name = "MultiMedia5",
  4774. .cpu_dai_name = "MultiMedia5",
  4775. .platform_name = "msm-pcm-dsp.1",
  4776. .dynamic = 1,
  4777. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4778. .dpcm_playback = 1,
  4779. .dpcm_capture = 1,
  4780. .codec_dai_name = "snd-soc-dummy-dai",
  4781. .codec_name = "snd-soc-dummy",
  4782. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4783. SND_SOC_DPCM_TRIGGER_POST},
  4784. .ignore_suspend = 1,
  4785. /* this dainlink has playback support */
  4786. .ignore_pmdown_time = 1,
  4787. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4788. .ops = &msm_fe_qos_ops,
  4789. },
  4790. {
  4791. .name = "Listen 1 Audio Service",
  4792. .stream_name = "Listen 1 Audio Service",
  4793. .cpu_dai_name = "LSM1",
  4794. .platform_name = "msm-lsm-client",
  4795. .dynamic = 1,
  4796. .dpcm_capture = 1,
  4797. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4798. SND_SOC_DPCM_TRIGGER_POST },
  4799. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4800. .ignore_suspend = 1,
  4801. .codec_dai_name = "snd-soc-dummy-dai",
  4802. .codec_name = "snd-soc-dummy",
  4803. .id = MSM_FRONTEND_DAI_LSM1,
  4804. },
  4805. /* Multiple Tunnel instances */
  4806. {
  4807. .name = MSM_DAILINK_NAME(Compress2),
  4808. .stream_name = "Compress2",
  4809. .cpu_dai_name = "MultiMedia7",
  4810. .platform_name = "msm-compress-dsp",
  4811. .dynamic = 1,
  4812. .dpcm_playback = 1,
  4813. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4814. SND_SOC_DPCM_TRIGGER_POST},
  4815. .codec_dai_name = "snd-soc-dummy-dai",
  4816. .codec_name = "snd-soc-dummy",
  4817. .ignore_suspend = 1,
  4818. .ignore_pmdown_time = 1,
  4819. /* this dainlink has playback support */
  4820. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4821. },
  4822. {
  4823. .name = MSM_DAILINK_NAME(MultiMedia10),
  4824. .stream_name = "MultiMedia10",
  4825. .cpu_dai_name = "MultiMedia10",
  4826. .platform_name = "msm-pcm-dsp.1",
  4827. .dynamic = 1,
  4828. .dpcm_playback = 1,
  4829. .dpcm_capture = 1,
  4830. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4831. SND_SOC_DPCM_TRIGGER_POST},
  4832. .codec_dai_name = "snd-soc-dummy-dai",
  4833. .codec_name = "snd-soc-dummy",
  4834. .ignore_suspend = 1,
  4835. .ignore_pmdown_time = 1,
  4836. /* this dainlink has playback support */
  4837. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4838. },
  4839. {
  4840. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4841. .stream_name = "MM_NOIRQ",
  4842. .cpu_dai_name = "MultiMedia8",
  4843. .platform_name = "msm-pcm-dsp-noirq",
  4844. .dynamic = 1,
  4845. .dpcm_playback = 1,
  4846. .dpcm_capture = 1,
  4847. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4848. SND_SOC_DPCM_TRIGGER_POST},
  4849. .codec_dai_name = "snd-soc-dummy-dai",
  4850. .codec_name = "snd-soc-dummy",
  4851. .ignore_suspend = 1,
  4852. .ignore_pmdown_time = 1,
  4853. /* this dainlink has playback support */
  4854. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4855. .ops = &msm_fe_qos_ops,
  4856. },
  4857. /* HDMI Hostless */
  4858. {
  4859. .name = "HDMI_RX_HOSTLESS",
  4860. .stream_name = "HDMI_RX_HOSTLESS",
  4861. .cpu_dai_name = "HDMI_HOSTLESS",
  4862. .platform_name = "msm-pcm-hostless",
  4863. .dynamic = 1,
  4864. .dpcm_playback = 1,
  4865. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4866. SND_SOC_DPCM_TRIGGER_POST},
  4867. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4868. .ignore_suspend = 1,
  4869. .ignore_pmdown_time = 1,
  4870. .codec_dai_name = "snd-soc-dummy-dai",
  4871. .codec_name = "snd-soc-dummy",
  4872. },
  4873. {
  4874. .name = "VoiceMMode2",
  4875. .stream_name = "VoiceMMode2",
  4876. .cpu_dai_name = "VoiceMMode2",
  4877. .platform_name = "msm-pcm-voice",
  4878. .dynamic = 1,
  4879. .dpcm_playback = 1,
  4880. .dpcm_capture = 1,
  4881. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4882. SND_SOC_DPCM_TRIGGER_POST},
  4883. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4884. .ignore_suspend = 1,
  4885. .ignore_pmdown_time = 1,
  4886. .codec_dai_name = "snd-soc-dummy-dai",
  4887. .codec_name = "snd-soc-dummy",
  4888. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4889. },
  4890. /* LSM FE */
  4891. {
  4892. .name = "Listen 2 Audio Service",
  4893. .stream_name = "Listen 2 Audio Service",
  4894. .cpu_dai_name = "LSM2",
  4895. .platform_name = "msm-lsm-client",
  4896. .dynamic = 1,
  4897. .dpcm_capture = 1,
  4898. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4899. SND_SOC_DPCM_TRIGGER_POST },
  4900. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4901. .ignore_suspend = 1,
  4902. .codec_dai_name = "snd-soc-dummy-dai",
  4903. .codec_name = "snd-soc-dummy",
  4904. .id = MSM_FRONTEND_DAI_LSM2,
  4905. },
  4906. {
  4907. .name = "Listen 3 Audio Service",
  4908. .stream_name = "Listen 3 Audio Service",
  4909. .cpu_dai_name = "LSM3",
  4910. .platform_name = "msm-lsm-client",
  4911. .dynamic = 1,
  4912. .dpcm_capture = 1,
  4913. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4914. SND_SOC_DPCM_TRIGGER_POST },
  4915. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4916. .ignore_suspend = 1,
  4917. .codec_dai_name = "snd-soc-dummy-dai",
  4918. .codec_name = "snd-soc-dummy",
  4919. .id = MSM_FRONTEND_DAI_LSM3,
  4920. },
  4921. {
  4922. .name = "Listen 4 Audio Service",
  4923. .stream_name = "Listen 4 Audio Service",
  4924. .cpu_dai_name = "LSM4",
  4925. .platform_name = "msm-lsm-client",
  4926. .dynamic = 1,
  4927. .dpcm_capture = 1,
  4928. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4929. SND_SOC_DPCM_TRIGGER_POST },
  4930. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4931. .ignore_suspend = 1,
  4932. .codec_dai_name = "snd-soc-dummy-dai",
  4933. .codec_name = "snd-soc-dummy",
  4934. .id = MSM_FRONTEND_DAI_LSM4,
  4935. },
  4936. {
  4937. .name = "Listen 5 Audio Service",
  4938. .stream_name = "Listen 5 Audio Service",
  4939. .cpu_dai_name = "LSM5",
  4940. .platform_name = "msm-lsm-client",
  4941. .dynamic = 1,
  4942. .dpcm_capture = 1,
  4943. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4944. SND_SOC_DPCM_TRIGGER_POST },
  4945. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4946. .ignore_suspend = 1,
  4947. .codec_dai_name = "snd-soc-dummy-dai",
  4948. .codec_name = "snd-soc-dummy",
  4949. .id = MSM_FRONTEND_DAI_LSM5,
  4950. },
  4951. {
  4952. .name = "Listen 6 Audio Service",
  4953. .stream_name = "Listen 6 Audio Service",
  4954. .cpu_dai_name = "LSM6",
  4955. .platform_name = "msm-lsm-client",
  4956. .dynamic = 1,
  4957. .dpcm_capture = 1,
  4958. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4959. SND_SOC_DPCM_TRIGGER_POST },
  4960. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4961. .ignore_suspend = 1,
  4962. .codec_dai_name = "snd-soc-dummy-dai",
  4963. .codec_name = "snd-soc-dummy",
  4964. .id = MSM_FRONTEND_DAI_LSM6,
  4965. },
  4966. {
  4967. .name = "Listen 7 Audio Service",
  4968. .stream_name = "Listen 7 Audio Service",
  4969. .cpu_dai_name = "LSM7",
  4970. .platform_name = "msm-lsm-client",
  4971. .dynamic = 1,
  4972. .dpcm_capture = 1,
  4973. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4974. SND_SOC_DPCM_TRIGGER_POST },
  4975. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4976. .ignore_suspend = 1,
  4977. .codec_dai_name = "snd-soc-dummy-dai",
  4978. .codec_name = "snd-soc-dummy",
  4979. .id = MSM_FRONTEND_DAI_LSM7,
  4980. },
  4981. {
  4982. .name = "Listen 8 Audio Service",
  4983. .stream_name = "Listen 8 Audio Service",
  4984. .cpu_dai_name = "LSM8",
  4985. .platform_name = "msm-lsm-client",
  4986. .dynamic = 1,
  4987. .dpcm_capture = 1,
  4988. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4989. SND_SOC_DPCM_TRIGGER_POST },
  4990. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4991. .ignore_suspend = 1,
  4992. .codec_dai_name = "snd-soc-dummy-dai",
  4993. .codec_name = "snd-soc-dummy",
  4994. .id = MSM_FRONTEND_DAI_LSM8,
  4995. },
  4996. {
  4997. .name = MSM_DAILINK_NAME(Media9),
  4998. .stream_name = "MultiMedia9",
  4999. .cpu_dai_name = "MultiMedia9",
  5000. .platform_name = "msm-pcm-dsp.0",
  5001. .dynamic = 1,
  5002. .dpcm_playback = 1,
  5003. .dpcm_capture = 1,
  5004. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5005. SND_SOC_DPCM_TRIGGER_POST},
  5006. .codec_dai_name = "snd-soc-dummy-dai",
  5007. .codec_name = "snd-soc-dummy",
  5008. .ignore_suspend = 1,
  5009. /* this dainlink has playback support */
  5010. .ignore_pmdown_time = 1,
  5011. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  5012. },
  5013. {
  5014. .name = MSM_DAILINK_NAME(Compress4),
  5015. .stream_name = "Compress4",
  5016. .cpu_dai_name = "MultiMedia11",
  5017. .platform_name = "msm-compress-dsp",
  5018. .dynamic = 1,
  5019. .dpcm_playback = 1,
  5020. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5021. SND_SOC_DPCM_TRIGGER_POST},
  5022. .codec_dai_name = "snd-soc-dummy-dai",
  5023. .codec_name = "snd-soc-dummy",
  5024. .ignore_suspend = 1,
  5025. .ignore_pmdown_time = 1,
  5026. /* this dainlink has playback support */
  5027. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5028. },
  5029. {
  5030. .name = MSM_DAILINK_NAME(Compress5),
  5031. .stream_name = "Compress5",
  5032. .cpu_dai_name = "MultiMedia12",
  5033. .platform_name = "msm-compress-dsp",
  5034. .dynamic = 1,
  5035. .dpcm_playback = 1,
  5036. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5037. SND_SOC_DPCM_TRIGGER_POST},
  5038. .codec_dai_name = "snd-soc-dummy-dai",
  5039. .codec_name = "snd-soc-dummy",
  5040. .ignore_suspend = 1,
  5041. .ignore_pmdown_time = 1,
  5042. /* this dainlink has playback support */
  5043. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5044. },
  5045. {
  5046. .name = MSM_DAILINK_NAME(Compress6),
  5047. .stream_name = "Compress6",
  5048. .cpu_dai_name = "MultiMedia13",
  5049. .platform_name = "msm-compress-dsp",
  5050. .dynamic = 1,
  5051. .dpcm_playback = 1,
  5052. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5053. SND_SOC_DPCM_TRIGGER_POST},
  5054. .codec_dai_name = "snd-soc-dummy-dai",
  5055. .codec_name = "snd-soc-dummy",
  5056. .ignore_suspend = 1,
  5057. .ignore_pmdown_time = 1,
  5058. /* this dainlink has playback support */
  5059. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5060. },
  5061. {
  5062. .name = MSM_DAILINK_NAME(Compress7),
  5063. .stream_name = "Compress7",
  5064. .cpu_dai_name = "MultiMedia14",
  5065. .platform_name = "msm-compress-dsp",
  5066. .dynamic = 1,
  5067. .dpcm_playback = 1,
  5068. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5069. SND_SOC_DPCM_TRIGGER_POST},
  5070. .codec_dai_name = "snd-soc-dummy-dai",
  5071. .codec_name = "snd-soc-dummy",
  5072. .ignore_suspend = 1,
  5073. .ignore_pmdown_time = 1,
  5074. /* this dainlink has playback support */
  5075. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5076. },
  5077. {
  5078. .name = MSM_DAILINK_NAME(Compress8),
  5079. .stream_name = "Compress8",
  5080. .cpu_dai_name = "MultiMedia15",
  5081. .platform_name = "msm-compress-dsp",
  5082. .dynamic = 1,
  5083. .dpcm_playback = 1,
  5084. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5085. SND_SOC_DPCM_TRIGGER_POST},
  5086. .codec_dai_name = "snd-soc-dummy-dai",
  5087. .codec_name = "snd-soc-dummy",
  5088. .ignore_suspend = 1,
  5089. .ignore_pmdown_time = 1,
  5090. /* this dainlink has playback support */
  5091. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5092. },
  5093. {
  5094. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5095. .stream_name = "MM_NOIRQ_2",
  5096. .cpu_dai_name = "MultiMedia16",
  5097. .platform_name = "msm-pcm-dsp-noirq",
  5098. .dynamic = 1,
  5099. .dpcm_playback = 1,
  5100. .dpcm_capture = 1,
  5101. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5102. SND_SOC_DPCM_TRIGGER_POST},
  5103. .codec_dai_name = "snd-soc-dummy-dai",
  5104. .codec_name = "snd-soc-dummy",
  5105. .ignore_suspend = 1,
  5106. .ignore_pmdown_time = 1,
  5107. /* this dainlink has playback support */
  5108. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5109. },
  5110. {
  5111. .name = "SLIMBUS_8 Hostless",
  5112. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5113. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5114. .platform_name = "msm-pcm-hostless",
  5115. .dynamic = 1,
  5116. .dpcm_capture = 1,
  5117. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5118. SND_SOC_DPCM_TRIGGER_POST},
  5119. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5120. .ignore_suspend = 1,
  5121. .codec_dai_name = "snd-soc-dummy-dai",
  5122. .codec_name = "snd-soc-dummy",
  5123. },
  5124. };
  5125. static struct snd_soc_dai_link msm_tasha_fe_dai_links[] = {
  5126. /* Ultrasound RX DAI Link */
  5127. {
  5128. .name = "SLIMBUS_2 Hostless Playback",
  5129. .stream_name = "SLIMBUS_2 Hostless Playback",
  5130. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5131. .platform_name = "msm-pcm-hostless",
  5132. .codec_name = "tasha_codec",
  5133. .codec_dai_name = "tasha_rx2",
  5134. .ignore_suspend = 1,
  5135. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5136. .ops = &msm_slimbus_2_be_ops,
  5137. },
  5138. /* Ultrasound TX DAI Link */
  5139. {
  5140. .name = "SLIMBUS_2 Hostless Capture",
  5141. .stream_name = "SLIMBUS_2 Hostless Capture",
  5142. .cpu_dai_name = "msm-dai-q6-dev.16389",
  5143. .platform_name = "msm-pcm-hostless",
  5144. .codec_name = "tasha_codec",
  5145. .codec_dai_name = "tasha_tx2",
  5146. .ignore_suspend = 1,
  5147. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5148. .ops = &msm_slimbus_2_be_ops,
  5149. },
  5150. {
  5151. .name = "SLIMBUS_6 Hostless Playback",
  5152. .stream_name = "SLIMBUS_6 Hostless",
  5153. .cpu_dai_name = "SLIMBUS6_HOSTLESS",
  5154. .platform_name = "msm-pcm-hostless",
  5155. .dynamic = 1,
  5156. .dpcm_playback = 1,
  5157. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5158. SND_SOC_DPCM_TRIGGER_POST},
  5159. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5160. .ignore_suspend = 1,
  5161. /* this dailink has playback support */
  5162. .ignore_pmdown_time = 1,
  5163. .codec_dai_name = "snd-soc-dummy-dai",
  5164. .codec_name = "snd-soc-dummy",
  5165. },
  5166. };
  5167. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5168. {
  5169. .name = MSM_DAILINK_NAME(ASM Loopback),
  5170. .stream_name = "MultiMedia6",
  5171. .cpu_dai_name = "MultiMedia6",
  5172. .platform_name = "msm-pcm-loopback",
  5173. .dynamic = 1,
  5174. .dpcm_playback = 1,
  5175. .dpcm_capture = 1,
  5176. .codec_dai_name = "snd-soc-dummy-dai",
  5177. .codec_name = "snd-soc-dummy",
  5178. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5179. SND_SOC_DPCM_TRIGGER_POST},
  5180. .ignore_suspend = 1,
  5181. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5182. .ignore_pmdown_time = 1,
  5183. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5184. },
  5185. {
  5186. .name = "USB Audio Hostless",
  5187. .stream_name = "USB Audio Hostless",
  5188. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5189. .platform_name = "msm-pcm-hostless",
  5190. .dynamic = 1,
  5191. .dpcm_playback = 1,
  5192. .dpcm_capture = 1,
  5193. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5194. SND_SOC_DPCM_TRIGGER_POST},
  5195. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5196. .ignore_suspend = 1,
  5197. .ignore_pmdown_time = 1,
  5198. .codec_dai_name = "snd-soc-dummy-dai",
  5199. .codec_name = "snd-soc-dummy",
  5200. },
  5201. {
  5202. .name = "SLIMBUS_7 Hostless",
  5203. .stream_name = "SLIMBUS_7 Hostless",
  5204. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5205. .platform_name = "msm-pcm-hostless",
  5206. .dynamic = 1,
  5207. .dpcm_capture = 1,
  5208. .dpcm_playback = 1,
  5209. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5210. SND_SOC_DPCM_TRIGGER_POST},
  5211. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5212. .ignore_suspend = 1,
  5213. .ignore_pmdown_time = 1,
  5214. .codec_dai_name = "snd-soc-dummy-dai",
  5215. .codec_name = "snd-soc-dummy",
  5216. },
  5217. };
  5218. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5219. /* Backend AFE DAI Links */
  5220. {
  5221. .name = LPASS_BE_AFE_PCM_RX,
  5222. .stream_name = "AFE Playback",
  5223. .cpu_dai_name = "msm-dai-q6-dev.224",
  5224. .platform_name = "msm-pcm-routing",
  5225. .codec_name = "msm-stub-codec.1",
  5226. .codec_dai_name = "msm-stub-rx",
  5227. .no_pcm = 1,
  5228. .dpcm_playback = 1,
  5229. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5230. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5231. /* this dainlink has playback support */
  5232. .ignore_pmdown_time = 1,
  5233. .ignore_suspend = 1,
  5234. },
  5235. {
  5236. .name = LPASS_BE_AFE_PCM_TX,
  5237. .stream_name = "AFE Capture",
  5238. .cpu_dai_name = "msm-dai-q6-dev.225",
  5239. .platform_name = "msm-pcm-routing",
  5240. .codec_name = "msm-stub-codec.1",
  5241. .codec_dai_name = "msm-stub-tx",
  5242. .no_pcm = 1,
  5243. .dpcm_capture = 1,
  5244. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5245. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5246. .ignore_suspend = 1,
  5247. },
  5248. /* Incall Record Uplink BACK END DAI Link */
  5249. {
  5250. .name = LPASS_BE_INCALL_RECORD_TX,
  5251. .stream_name = "Voice Uplink Capture",
  5252. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5253. .platform_name = "msm-pcm-routing",
  5254. .codec_name = "msm-stub-codec.1",
  5255. .codec_dai_name = "msm-stub-tx",
  5256. .no_pcm = 1,
  5257. .dpcm_capture = 1,
  5258. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5259. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5260. .ignore_suspend = 1,
  5261. },
  5262. /* Incall Record Downlink BACK END DAI Link */
  5263. {
  5264. .name = LPASS_BE_INCALL_RECORD_RX,
  5265. .stream_name = "Voice Downlink Capture",
  5266. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5267. .platform_name = "msm-pcm-routing",
  5268. .codec_name = "msm-stub-codec.1",
  5269. .codec_dai_name = "msm-stub-tx",
  5270. .no_pcm = 1,
  5271. .dpcm_capture = 1,
  5272. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5273. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5274. .ignore_suspend = 1,
  5275. },
  5276. /* Incall Music BACK END DAI Link */
  5277. {
  5278. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5279. .stream_name = "Voice Farend Playback",
  5280. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5281. .platform_name = "msm-pcm-routing",
  5282. .codec_name = "msm-stub-codec.1",
  5283. .codec_dai_name = "msm-stub-rx",
  5284. .no_pcm = 1,
  5285. .dpcm_playback = 1,
  5286. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5287. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5288. .ignore_suspend = 1,
  5289. .ignore_pmdown_time = 1,
  5290. },
  5291. /* Incall Music 2 BACK END DAI Link */
  5292. {
  5293. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5294. .stream_name = "Voice2 Farend Playback",
  5295. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5296. .platform_name = "msm-pcm-routing",
  5297. .codec_name = "msm-stub-codec.1",
  5298. .codec_dai_name = "msm-stub-rx",
  5299. .no_pcm = 1,
  5300. .dpcm_playback = 1,
  5301. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5302. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5303. .ignore_suspend = 1,
  5304. .ignore_pmdown_time = 1,
  5305. },
  5306. {
  5307. .name = LPASS_BE_USB_AUDIO_RX,
  5308. .stream_name = "USB Audio Playback",
  5309. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5310. .platform_name = "msm-pcm-routing",
  5311. .codec_name = "msm-stub-codec.1",
  5312. .codec_dai_name = "msm-stub-rx",
  5313. .no_pcm = 1,
  5314. .dpcm_playback = 1,
  5315. .id = MSM_BACKEND_DAI_USB_RX,
  5316. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5317. .ignore_pmdown_time = 1,
  5318. .ignore_suspend = 1,
  5319. },
  5320. {
  5321. .name = LPASS_BE_USB_AUDIO_TX,
  5322. .stream_name = "USB Audio Capture",
  5323. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5324. .platform_name = "msm-pcm-routing",
  5325. .codec_name = "msm-stub-codec.1",
  5326. .codec_dai_name = "msm-stub-tx",
  5327. .no_pcm = 1,
  5328. .dpcm_capture = 1,
  5329. .id = MSM_BACKEND_DAI_USB_TX,
  5330. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5331. .ignore_suspend = 1,
  5332. },
  5333. {
  5334. .name = LPASS_BE_PRI_TDM_RX_0,
  5335. .stream_name = "Primary TDM0 Playback",
  5336. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5337. .platform_name = "msm-pcm-routing",
  5338. .codec_name = "msm-stub-codec.1",
  5339. .codec_dai_name = "msm-stub-rx",
  5340. .no_pcm = 1,
  5341. .dpcm_playback = 1,
  5342. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5343. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5344. .ops = &qcs405_tdm_be_ops,
  5345. .ignore_suspend = 1,
  5346. .ignore_pmdown_time = 1,
  5347. },
  5348. {
  5349. .name = LPASS_BE_PRI_TDM_TX_0,
  5350. .stream_name = "Primary TDM0 Capture",
  5351. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5352. .platform_name = "msm-pcm-routing",
  5353. .codec_name = "msm-stub-codec.1",
  5354. .codec_dai_name = "msm-stub-tx",
  5355. .no_pcm = 1,
  5356. .dpcm_capture = 1,
  5357. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5358. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5359. .ops = &qcs405_tdm_be_ops,
  5360. .ignore_suspend = 1,
  5361. },
  5362. {
  5363. .name = LPASS_BE_SEC_TDM_RX_0,
  5364. .stream_name = "Secondary TDM0 Playback",
  5365. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5366. .platform_name = "msm-pcm-routing",
  5367. .codec_name = "msm-stub-codec.1",
  5368. .codec_dai_name = "msm-stub-rx",
  5369. .no_pcm = 1,
  5370. .dpcm_playback = 1,
  5371. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5372. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5373. .ops = &qcs405_tdm_be_ops,
  5374. .ignore_suspend = 1,
  5375. .ignore_pmdown_time = 1,
  5376. },
  5377. {
  5378. .name = LPASS_BE_SEC_TDM_TX_0,
  5379. .stream_name = "Secondary TDM0 Capture",
  5380. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5381. .platform_name = "msm-pcm-routing",
  5382. .codec_name = "msm-stub-codec.1",
  5383. .codec_dai_name = "msm-stub-tx",
  5384. .no_pcm = 1,
  5385. .dpcm_capture = 1,
  5386. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5387. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5388. .ops = &qcs405_tdm_be_ops,
  5389. .ignore_suspend = 1,
  5390. },
  5391. {
  5392. .name = LPASS_BE_TERT_TDM_RX_0,
  5393. .stream_name = "Tertiary TDM0 Playback",
  5394. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5395. .platform_name = "msm-pcm-routing",
  5396. .codec_name = "msm-stub-codec.1",
  5397. .codec_dai_name = "msm-stub-rx",
  5398. .no_pcm = 1,
  5399. .dpcm_playback = 1,
  5400. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5401. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5402. .ops = &qcs405_tdm_be_ops,
  5403. .ignore_suspend = 1,
  5404. .ignore_pmdown_time = 1,
  5405. },
  5406. {
  5407. .name = LPASS_BE_TERT_TDM_TX_0,
  5408. .stream_name = "Tertiary TDM0 Capture",
  5409. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5410. .platform_name = "msm-pcm-routing",
  5411. .codec_name = "msm-stub-codec.1",
  5412. .codec_dai_name = "msm-stub-tx",
  5413. .no_pcm = 1,
  5414. .dpcm_capture = 1,
  5415. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5416. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5417. .ops = &qcs405_tdm_be_ops,
  5418. .ignore_suspend = 1,
  5419. },
  5420. {
  5421. .name = LPASS_BE_QUAT_TDM_RX_0,
  5422. .stream_name = "Quaternary TDM0 Playback",
  5423. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5424. .platform_name = "msm-pcm-routing",
  5425. .codec_name = "msm-stub-codec.1",
  5426. .codec_dai_name = "msm-stub-rx",
  5427. .no_pcm = 1,
  5428. .dpcm_playback = 1,
  5429. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5430. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5431. .ops = &qcs405_tdm_be_ops,
  5432. .ignore_suspend = 1,
  5433. .ignore_pmdown_time = 1,
  5434. },
  5435. {
  5436. .name = LPASS_BE_QUAT_TDM_TX_0,
  5437. .stream_name = "Quaternary TDM0 Capture",
  5438. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5439. .platform_name = "msm-pcm-routing",
  5440. .codec_name = "msm-stub-codec.1",
  5441. .codec_dai_name = "msm-stub-tx",
  5442. .no_pcm = 1,
  5443. .dpcm_capture = 1,
  5444. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5445. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5446. .ops = &qcs405_tdm_be_ops,
  5447. .ignore_suspend = 1,
  5448. },
  5449. {
  5450. .name = LPASS_BE_QUIN_TDM_RX_0,
  5451. .stream_name = "Quinary TDM0 Playback",
  5452. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5453. .platform_name = "msm-pcm-routing",
  5454. .codec_name = "msm-stub-codec.1",
  5455. .codec_dai_name = "msm-stub-rx",
  5456. .no_pcm = 1,
  5457. .dpcm_playback = 1,
  5458. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5459. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5460. .ops = &qcs405_tdm_be_ops,
  5461. .ignore_suspend = 1,
  5462. .ignore_pmdown_time = 1,
  5463. },
  5464. {
  5465. .name = LPASS_BE_QUIN_TDM_TX_0,
  5466. .stream_name = "Quinary TDM0 Capture",
  5467. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5468. .platform_name = "msm-pcm-routing",
  5469. .codec_name = "msm-stub-codec.1",
  5470. .codec_dai_name = "msm-stub-tx",
  5471. .no_pcm = 1,
  5472. .dpcm_capture = 1,
  5473. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5474. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5475. .ops = &qcs405_tdm_be_ops,
  5476. .ignore_suspend = 1,
  5477. },
  5478. };
  5479. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5480. {
  5481. .name = LPASS_BE_SLIMBUS_0_RX,
  5482. .stream_name = "Slimbus Playback",
  5483. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5484. .platform_name = "msm-pcm-routing",
  5485. .codec_name = "tasha_codec",
  5486. .codec_dai_name = "tasha_mix_rx1",
  5487. .no_pcm = 1,
  5488. .dpcm_playback = 1,
  5489. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5490. .init = &msm_audrx_init,
  5491. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5492. /* this dainlink has playback support */
  5493. .ignore_pmdown_time = 1,
  5494. .ignore_suspend = 1,
  5495. .ops = &msm_be_ops,
  5496. },
  5497. {
  5498. .name = LPASS_BE_SLIMBUS_0_TX,
  5499. .stream_name = "Slimbus Capture",
  5500. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5501. .platform_name = "msm-pcm-routing",
  5502. .codec_name = "tasha_codec",
  5503. .codec_dai_name = "tasha_tx1",
  5504. .no_pcm = 1,
  5505. .dpcm_capture = 1,
  5506. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5507. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5508. .ignore_suspend = 1,
  5509. .ops = &msm_be_ops,
  5510. },
  5511. {
  5512. .name = LPASS_BE_SLIMBUS_1_RX,
  5513. .stream_name = "Slimbus1 Playback",
  5514. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5515. .platform_name = "msm-pcm-routing",
  5516. .codec_name = "tasha_codec",
  5517. .codec_dai_name = "tasha_mix_rx1",
  5518. .no_pcm = 1,
  5519. .dpcm_playback = 1,
  5520. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5521. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5522. .ops = &msm_be_ops,
  5523. /* dai link has playback support */
  5524. .ignore_pmdown_time = 1,
  5525. .ignore_suspend = 1,
  5526. },
  5527. {
  5528. .name = LPASS_BE_SLIMBUS_1_TX,
  5529. .stream_name = "Slimbus1 Capture",
  5530. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5531. .platform_name = "msm-pcm-routing",
  5532. .codec_name = "tasha_codec",
  5533. .codec_dai_name = "tasha_tx3",
  5534. .no_pcm = 1,
  5535. .dpcm_capture = 1,
  5536. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5537. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5538. .ops = &msm_be_ops,
  5539. .ignore_suspend = 1,
  5540. },
  5541. {
  5542. .name = LPASS_BE_SLIMBUS_2_RX,
  5543. .stream_name = "Slimbus2 Playback",
  5544. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5545. .platform_name = "msm-pcm-routing",
  5546. .codec_name = "tasha_codec",
  5547. .codec_dai_name = "tasha_rx2",
  5548. .no_pcm = 1,
  5549. .dpcm_playback = 1,
  5550. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5551. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5552. .ops = &msm_be_ops,
  5553. .ignore_pmdown_time = 1,
  5554. .ignore_suspend = 1,
  5555. },
  5556. {
  5557. .name = LPASS_BE_SLIMBUS_3_RX,
  5558. .stream_name = "Slimbus3 Playback",
  5559. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5560. .platform_name = "msm-pcm-routing",
  5561. .codec_name = "tasha_codec",
  5562. .codec_dai_name = "tasha_mix_rx1",
  5563. .no_pcm = 1,
  5564. .dpcm_playback = 1,
  5565. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5566. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5567. .ops = &msm_be_ops,
  5568. /* dai link has playback support */
  5569. .ignore_pmdown_time = 1,
  5570. .ignore_suspend = 1,
  5571. },
  5572. {
  5573. .name = LPASS_BE_SLIMBUS_3_TX,
  5574. .stream_name = "Slimbus3 Capture",
  5575. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5576. .platform_name = "msm-pcm-routing",
  5577. .codec_name = "tasha_codec",
  5578. .codec_dai_name = "tasha_tx1",
  5579. .no_pcm = 1,
  5580. .dpcm_capture = 1,
  5581. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5582. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5583. .ops = &msm_be_ops,
  5584. .ignore_suspend = 1,
  5585. },
  5586. {
  5587. .name = LPASS_BE_SLIMBUS_4_RX,
  5588. .stream_name = "Slimbus4 Playback",
  5589. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5590. .platform_name = "msm-pcm-routing",
  5591. .codec_name = "tasha_codec",
  5592. .codec_dai_name = "tasha_mix_rx1",
  5593. .no_pcm = 1,
  5594. .dpcm_playback = 1,
  5595. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5596. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5597. .ops = &msm_be_ops,
  5598. /* dai link has playback support */
  5599. .ignore_pmdown_time = 1,
  5600. .ignore_suspend = 1,
  5601. },
  5602. {
  5603. .name = LPASS_BE_SLIMBUS_5_RX,
  5604. .stream_name = "Slimbus5 Playback",
  5605. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5606. .platform_name = "msm-pcm-routing",
  5607. .codec_name = "tasha_codec",
  5608. .codec_dai_name = "tasha_rx3",
  5609. .no_pcm = 1,
  5610. .dpcm_playback = 1,
  5611. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5612. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5613. .ops = &msm_be_ops,
  5614. /* dai link has playback support */
  5615. .ignore_pmdown_time = 1,
  5616. .ignore_suspend = 1,
  5617. },
  5618. {
  5619. .name = LPASS_BE_SLIMBUS_6_RX,
  5620. .stream_name = "Slimbus6 Playback",
  5621. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5622. .platform_name = "msm-pcm-routing",
  5623. .codec_name = "tasha_codec",
  5624. .codec_dai_name = "tasha_rx4",
  5625. .no_pcm = 1,
  5626. .dpcm_playback = 1,
  5627. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5628. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5629. .ops = &msm_be_ops,
  5630. /* dai link has playback support */
  5631. .ignore_pmdown_time = 1,
  5632. .ignore_suspend = 1,
  5633. },
  5634. /* Slimbus VI Recording */
  5635. {
  5636. .name = LPASS_BE_SLIMBUS_TX_VI,
  5637. .stream_name = "Slimbus4 Capture",
  5638. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5639. .platform_name = "msm-pcm-routing",
  5640. .codec_name = "tasha_codec",
  5641. .codec_dai_name = "tasha_vifeedback",
  5642. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5643. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5644. .ops = &msm_be_ops,
  5645. .ignore_suspend = 1,
  5646. .no_pcm = 1,
  5647. .dpcm_capture = 1,
  5648. .ignore_pmdown_time = 1,
  5649. },
  5650. };
  5651. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5652. {
  5653. .name = LPASS_BE_SLIMBUS_7_RX,
  5654. .stream_name = "Slimbus7 Playback",
  5655. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5656. .platform_name = "msm-pcm-routing",
  5657. .codec_name = "btfmslim_slave",
  5658. /* BT codec driver determines capabilities based on
  5659. * dai name, bt codecdai name should always contains
  5660. * supported usecase information
  5661. */
  5662. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5663. .no_pcm = 1,
  5664. .dpcm_playback = 1,
  5665. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5666. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5667. .ops = &msm_wcn_ops,
  5668. /* dai link has playback support */
  5669. .ignore_pmdown_time = 1,
  5670. .ignore_suspend = 1,
  5671. },
  5672. {
  5673. .name = LPASS_BE_SLIMBUS_7_TX,
  5674. .stream_name = "Slimbus7 Capture",
  5675. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5676. .platform_name = "msm-pcm-routing",
  5677. .codec_name = "btfmslim_slave",
  5678. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5679. .no_pcm = 1,
  5680. .dpcm_capture = 1,
  5681. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5682. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5683. .ops = &msm_wcn_ops,
  5684. .ignore_suspend = 1,
  5685. },
  5686. {
  5687. .name = LPASS_BE_SLIMBUS_8_TX,
  5688. .stream_name = "Slimbus8 Capture",
  5689. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5690. .platform_name = "msm-pcm-routing",
  5691. .codec_name = "btfmslim_slave",
  5692. .codec_dai_name = "btfm_fm_slim_tx",
  5693. .no_pcm = 1,
  5694. .dpcm_capture = 1,
  5695. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5696. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5697. .init = &msm_wcn_init,
  5698. .ops = &msm_wcn_ops,
  5699. .ignore_suspend = 1,
  5700. },
  5701. };
  5702. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5703. {
  5704. .name = LPASS_BE_PRI_MI2S_RX,
  5705. .stream_name = "Primary MI2S Playback",
  5706. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5707. .platform_name = "msm-pcm-routing",
  5708. .codec_name = "msm-stub-codec.1",
  5709. .codec_dai_name = "msm-stub-rx",
  5710. .no_pcm = 1,
  5711. .dpcm_playback = 1,
  5712. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5713. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5714. .ops = &msm_mi2s_be_ops,
  5715. .ignore_suspend = 1,
  5716. .ignore_pmdown_time = 1,
  5717. },
  5718. {
  5719. .name = LPASS_BE_PRI_MI2S_TX,
  5720. .stream_name = "Primary MI2S Capture",
  5721. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5722. .platform_name = "msm-pcm-routing",
  5723. .codec_name = "msm-stub-codec.1",
  5724. .codec_dai_name = "msm-stub-tx",
  5725. .no_pcm = 1,
  5726. .dpcm_capture = 1,
  5727. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5728. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5729. .ops = &msm_mi2s_be_ops,
  5730. .ignore_suspend = 1,
  5731. },
  5732. {
  5733. .name = LPASS_BE_SEC_MI2S_RX,
  5734. .stream_name = "Secondary MI2S Playback",
  5735. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5736. .platform_name = "msm-pcm-routing",
  5737. .codec_name = "msm-stub-codec.1",
  5738. .codec_dai_name = "msm-stub-rx",
  5739. .no_pcm = 1,
  5740. .dpcm_playback = 1,
  5741. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5742. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5743. .ops = &msm_mi2s_be_ops,
  5744. .ignore_suspend = 1,
  5745. .ignore_pmdown_time = 1,
  5746. },
  5747. {
  5748. .name = LPASS_BE_SEC_MI2S_TX,
  5749. .stream_name = "Secondary MI2S Capture",
  5750. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5751. .platform_name = "msm-pcm-routing",
  5752. .codec_name = "msm-stub-codec.1",
  5753. .codec_dai_name = "msm-stub-tx",
  5754. .no_pcm = 1,
  5755. .dpcm_capture = 1,
  5756. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5757. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5758. .ops = &msm_mi2s_be_ops,
  5759. .ignore_suspend = 1,
  5760. },
  5761. {
  5762. .name = LPASS_BE_TERT_MI2S_RX,
  5763. .stream_name = "Tertiary MI2S Playback",
  5764. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5765. .platform_name = "msm-pcm-routing",
  5766. .codec_name = "msm-stub-codec.1",
  5767. .codec_dai_name = "msm-stub-rx",
  5768. .no_pcm = 1,
  5769. .dpcm_playback = 1,
  5770. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5771. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5772. .ops = &msm_mi2s_be_ops,
  5773. .ignore_suspend = 1,
  5774. .ignore_pmdown_time = 1,
  5775. },
  5776. {
  5777. .name = LPASS_BE_TERT_MI2S_TX,
  5778. .stream_name = "Tertiary MI2S Capture",
  5779. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5780. .platform_name = "msm-pcm-routing",
  5781. .codec_name = "msm-stub-codec.1",
  5782. .codec_dai_name = "msm-stub-tx",
  5783. .no_pcm = 1,
  5784. .dpcm_capture = 1,
  5785. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5786. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5787. .ops = &msm_mi2s_be_ops,
  5788. .ignore_suspend = 1,
  5789. },
  5790. {
  5791. .name = LPASS_BE_QUAT_MI2S_RX,
  5792. .stream_name = "Quaternary MI2S Playback",
  5793. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5794. .platform_name = "msm-pcm-routing",
  5795. .codec_name = "msm-stub-codec.1",
  5796. .codec_dai_name = "msm-stub-rx",
  5797. .no_pcm = 1,
  5798. .dpcm_playback = 1,
  5799. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5800. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5801. .ops = &msm_mi2s_be_ops,
  5802. .ignore_suspend = 1,
  5803. .ignore_pmdown_time = 1,
  5804. },
  5805. {
  5806. .name = LPASS_BE_QUAT_MI2S_TX,
  5807. .stream_name = "Quaternary MI2S Capture",
  5808. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5809. .platform_name = "msm-pcm-routing",
  5810. .codec_name = "msm-stub-codec.1",
  5811. .codec_dai_name = "msm-stub-tx",
  5812. .no_pcm = 1,
  5813. .dpcm_capture = 1,
  5814. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5815. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5816. .ops = &msm_mi2s_be_ops,
  5817. .ignore_suspend = 1,
  5818. },
  5819. {
  5820. .name = LPASS_BE_QUIN_MI2S_RX,
  5821. .stream_name = "Quinary MI2S Playback",
  5822. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5823. .platform_name = "msm-pcm-routing",
  5824. .codec_name = "msm-stub-codec.1",
  5825. .codec_dai_name = "msm-stub-rx",
  5826. .no_pcm = 1,
  5827. .dpcm_playback = 1,
  5828. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5829. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5830. .ops = &msm_mi2s_be_ops,
  5831. .ignore_suspend = 1,
  5832. .ignore_pmdown_time = 1,
  5833. },
  5834. {
  5835. .name = LPASS_BE_QUIN_MI2S_TX,
  5836. .stream_name = "Quinary MI2S Capture",
  5837. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5838. .platform_name = "msm-pcm-routing",
  5839. .codec_name = "msm-stub-codec.1",
  5840. .codec_dai_name = "msm-stub-tx",
  5841. .no_pcm = 1,
  5842. .dpcm_capture = 1,
  5843. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5844. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5845. .ops = &msm_mi2s_be_ops,
  5846. .ignore_suspend = 1,
  5847. },
  5848. };
  5849. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5850. /* Primary AUX PCM Backend DAI Links */
  5851. {
  5852. .name = LPASS_BE_AUXPCM_RX,
  5853. .stream_name = "AUX PCM Playback",
  5854. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5855. .platform_name = "msm-pcm-routing",
  5856. .codec_name = "msm-stub-codec.1",
  5857. .codec_dai_name = "msm-stub-rx",
  5858. .no_pcm = 1,
  5859. .dpcm_playback = 1,
  5860. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5861. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5862. .ignore_pmdown_time = 1,
  5863. .ignore_suspend = 1,
  5864. },
  5865. {
  5866. .name = LPASS_BE_AUXPCM_TX,
  5867. .stream_name = "AUX PCM Capture",
  5868. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5869. .platform_name = "msm-pcm-routing",
  5870. .codec_name = "msm-stub-codec.1",
  5871. .codec_dai_name = "msm-stub-tx",
  5872. .no_pcm = 1,
  5873. .dpcm_capture = 1,
  5874. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5875. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5876. .ignore_suspend = 1,
  5877. },
  5878. /* Secondary AUX PCM Backend DAI Links */
  5879. {
  5880. .name = LPASS_BE_SEC_AUXPCM_RX,
  5881. .stream_name = "Sec AUX PCM Playback",
  5882. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5883. .platform_name = "msm-pcm-routing",
  5884. .codec_name = "msm-stub-codec.1",
  5885. .codec_dai_name = "msm-stub-rx",
  5886. .no_pcm = 1,
  5887. .dpcm_playback = 1,
  5888. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5889. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5890. .ignore_pmdown_time = 1,
  5891. .ignore_suspend = 1,
  5892. },
  5893. {
  5894. .name = LPASS_BE_SEC_AUXPCM_TX,
  5895. .stream_name = "Sec AUX PCM Capture",
  5896. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5897. .platform_name = "msm-pcm-routing",
  5898. .codec_name = "msm-stub-codec.1",
  5899. .codec_dai_name = "msm-stub-tx",
  5900. .no_pcm = 1,
  5901. .dpcm_capture = 1,
  5902. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5903. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5904. .ignore_suspend = 1,
  5905. },
  5906. /* Tertiary AUX PCM Backend DAI Links */
  5907. {
  5908. .name = LPASS_BE_TERT_AUXPCM_RX,
  5909. .stream_name = "Tert AUX PCM Playback",
  5910. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5911. .platform_name = "msm-pcm-routing",
  5912. .codec_name = "msm-stub-codec.1",
  5913. .codec_dai_name = "msm-stub-rx",
  5914. .no_pcm = 1,
  5915. .dpcm_playback = 1,
  5916. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5917. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5918. .ignore_suspend = 1,
  5919. },
  5920. {
  5921. .name = LPASS_BE_TERT_AUXPCM_TX,
  5922. .stream_name = "Tert AUX PCM Capture",
  5923. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5924. .platform_name = "msm-pcm-routing",
  5925. .codec_name = "msm-stub-codec.1",
  5926. .codec_dai_name = "msm-stub-tx",
  5927. .no_pcm = 1,
  5928. .dpcm_capture = 1,
  5929. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5930. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5931. .ignore_suspend = 1,
  5932. },
  5933. /* Quaternary AUX PCM Backend DAI Links */
  5934. {
  5935. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5936. .stream_name = "Quat AUX PCM Playback",
  5937. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5938. .platform_name = "msm-pcm-routing",
  5939. .codec_name = "msm-stub-codec.1",
  5940. .codec_dai_name = "msm-stub-rx",
  5941. .no_pcm = 1,
  5942. .dpcm_playback = 1,
  5943. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5944. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5945. .ignore_pmdown_time = 1,
  5946. .ignore_suspend = 1,
  5947. },
  5948. {
  5949. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5950. .stream_name = "Quat AUX PCM Capture",
  5951. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5952. .platform_name = "msm-pcm-routing",
  5953. .codec_name = "msm-stub-codec.1",
  5954. .codec_dai_name = "msm-stub-tx",
  5955. .no_pcm = 1,
  5956. .dpcm_capture = 1,
  5957. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5958. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5959. .ignore_suspend = 1,
  5960. },
  5961. /* Quinary AUX PCM Backend DAI Links */
  5962. {
  5963. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5964. .stream_name = "Quin AUX PCM Playback",
  5965. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5966. .platform_name = "msm-pcm-routing",
  5967. .codec_name = "msm-stub-codec.1",
  5968. .codec_dai_name = "msm-stub-rx",
  5969. .no_pcm = 1,
  5970. .dpcm_playback = 1,
  5971. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5972. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5973. .ignore_pmdown_time = 1,
  5974. .ignore_suspend = 1,
  5975. },
  5976. {
  5977. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5978. .stream_name = "Quin AUX PCM Capture",
  5979. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5980. .platform_name = "msm-pcm-routing",
  5981. .codec_name = "msm-stub-codec.1",
  5982. .codec_dai_name = "msm-stub-tx",
  5983. .no_pcm = 1,
  5984. .dpcm_capture = 1,
  5985. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5986. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5987. .ignore_suspend = 1,
  5988. },
  5989. };
  5990. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5991. /* WSA CDC DMA Backend DAI Links */
  5992. {
  5993. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5994. .stream_name = "WSA CDC DMA0 Playback",
  5995. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  5996. .platform_name = "msm-pcm-routing",
  5997. .codec_name = "bolero_codec",
  5998. .codec_dai_name = "wsa_macro_rx1",
  5999. .no_pcm = 1,
  6000. .dpcm_playback = 1,
  6001. .init = &msm_wsa_cdc_dma_init,
  6002. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  6003. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6004. .ignore_pmdown_time = 1,
  6005. .ignore_suspend = 1,
  6006. .ops = &msm_cdc_dma_be_ops,
  6007. },
  6008. {
  6009. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  6010. .stream_name = "WSA CDC DMA0 Capture",
  6011. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  6012. .platform_name = "msm-pcm-hostless",
  6013. .codec_name = "bolero_codec",
  6014. .codec_dai_name = "wsa_macro_vifeedback",
  6015. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  6016. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6017. .ignore_suspend = 1,
  6018. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6019. .ops = &msm_cdc_dma_be_ops,
  6020. },
  6021. {
  6022. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  6023. .stream_name = "WSA CDC DMA1 Playback",
  6024. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  6025. .platform_name = "msm-pcm-routing",
  6026. .codec_name = "bolero_codec",
  6027. .codec_dai_name = "wsa_macro_rx_mix",
  6028. .no_pcm = 1,
  6029. .dpcm_playback = 1,
  6030. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  6031. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6032. .ignore_pmdown_time = 1,
  6033. .ignore_suspend = 1,
  6034. .ops = &msm_cdc_dma_be_ops,
  6035. },
  6036. {
  6037. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6038. .stream_name = "WSA CDC DMA1 Capture",
  6039. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6040. .platform_name = "msm-pcm-routing",
  6041. .codec_name = "bolero_codec",
  6042. .codec_dai_name = "wsa_macro_echo",
  6043. .no_pcm = 1,
  6044. .dpcm_capture = 1,
  6045. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6046. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6047. .ignore_suspend = 1,
  6048. .ops = &msm_cdc_dma_be_ops,
  6049. },
  6050. };
  6051. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6052. {
  6053. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6054. .stream_name = "VA CDC DMA0 Capture",
  6055. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6056. .platform_name = "msm-pcm-routing",
  6057. .codec_name = "bolero_codec",
  6058. .codec_dai_name = "va_macro_tx1",
  6059. .no_pcm = 1,
  6060. .dpcm_capture = 1,
  6061. .init = &msm_va_cdc_dma_init,
  6062. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6063. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6064. .ignore_suspend = 1,
  6065. .ops = &msm_cdc_dma_be_ops,
  6066. },
  6067. {
  6068. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6069. .stream_name = "VA CDC DMA1 Capture",
  6070. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6071. .platform_name = "msm-pcm-routing",
  6072. .codec_name = "bolero_codec",
  6073. .codec_dai_name = "va_macro_tx2",
  6074. .no_pcm = 1,
  6075. .dpcm_capture = 1,
  6076. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6077. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6078. .ignore_suspend = 1,
  6079. .ops = &msm_cdc_dma_be_ops,
  6080. },
  6081. };
  6082. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6083. ARRAY_SIZE(msm_common_dai_links) +
  6084. ARRAY_SIZE(msm_tasha_fe_dai_links) +
  6085. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6086. ARRAY_SIZE(msm_common_be_dai_links) +
  6087. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6088. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6089. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6090. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6091. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6092. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links)];
  6093. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6094. {
  6095. int ret = 0;
  6096. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6097. &service_nb);
  6098. if (ret < 0)
  6099. pr_err("%s: Audio notifier register failed ret = %d\n",
  6100. __func__, ret);
  6101. return ret;
  6102. }
  6103. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6104. struct snd_ctl_elem_value *ucontrol)
  6105. {
  6106. int ret = 0;
  6107. int port_id;
  6108. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6109. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6110. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6111. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6112. (vad_enable < 0) || (vad_enable > 1) ||
  6113. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6114. pr_err("%s: Invalid arguments\n", __func__);
  6115. ret = -EINVAL;
  6116. goto done;
  6117. }
  6118. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6119. vad_enable, preroll_config, vad_intf);
  6120. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6121. if (ret) {
  6122. pr_err("%s: Invalid vad interface\n", __func__);
  6123. goto done;
  6124. }
  6125. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6126. done:
  6127. return ret;
  6128. }
  6129. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6130. {
  6131. int ret = 0;
  6132. uint32_t tasha_codec = 0;
  6133. ret = afe_cal_init_hwdep(card);
  6134. if (ret) {
  6135. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6136. ret = 0;
  6137. }
  6138. /* tasha late probe when it is present */
  6139. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6140. &tasha_codec);
  6141. if (ret) {
  6142. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6143. ret = 0;
  6144. } else {
  6145. if (tasha_codec) {
  6146. ret = msm_snd_card_tasha_late_probe(card);
  6147. if (ret)
  6148. dev_err(card->dev, "%s: tasha late probe err\n",
  6149. __func__);
  6150. }
  6151. }
  6152. return ret;
  6153. }
  6154. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6155. .name = "qcs405-snd-card",
  6156. .controls = msm_snd_controls,
  6157. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6158. .late_probe = msm_snd_card_codec_late_probe,
  6159. };
  6160. static int msm_populate_dai_link_component_of_node(
  6161. struct snd_soc_card *card)
  6162. {
  6163. int i, index, ret = 0;
  6164. struct device *cdev = card->dev;
  6165. struct snd_soc_dai_link *dai_link = card->dai_link;
  6166. struct device_node *np;
  6167. if (!cdev) {
  6168. pr_err("%s: Sound card device memory NULL\n", __func__);
  6169. return -ENODEV;
  6170. }
  6171. for (i = 0; i < card->num_links; i++) {
  6172. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6173. continue;
  6174. /* populate platform_of_node for snd card dai links */
  6175. if (dai_link[i].platform_name &&
  6176. !dai_link[i].platform_of_node) {
  6177. index = of_property_match_string(cdev->of_node,
  6178. "asoc-platform-names",
  6179. dai_link[i].platform_name);
  6180. if (index < 0) {
  6181. pr_err("%s: No match found for platform name: %s\n",
  6182. __func__, dai_link[i].platform_name);
  6183. ret = index;
  6184. goto err;
  6185. }
  6186. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6187. index);
  6188. if (!np) {
  6189. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6190. __func__, dai_link[i].platform_name,
  6191. index);
  6192. ret = -ENODEV;
  6193. goto err;
  6194. }
  6195. dai_link[i].platform_of_node = np;
  6196. dai_link[i].platform_name = NULL;
  6197. }
  6198. /* populate cpu_of_node for snd card dai links */
  6199. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6200. index = of_property_match_string(cdev->of_node,
  6201. "asoc-cpu-names",
  6202. dai_link[i].cpu_dai_name);
  6203. if (index >= 0) {
  6204. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6205. index);
  6206. if (!np) {
  6207. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6208. __func__,
  6209. dai_link[i].cpu_dai_name);
  6210. ret = -ENODEV;
  6211. goto err;
  6212. }
  6213. dai_link[i].cpu_of_node = np;
  6214. dai_link[i].cpu_dai_name = NULL;
  6215. }
  6216. }
  6217. /* populate codec_of_node for snd card dai links */
  6218. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6219. index = of_property_match_string(cdev->of_node,
  6220. "asoc-codec-names",
  6221. dai_link[i].codec_name);
  6222. if (index < 0)
  6223. continue;
  6224. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6225. index);
  6226. if (!np) {
  6227. pr_err("%s: retrieving phandle for codec %s failed\n",
  6228. __func__, dai_link[i].codec_name);
  6229. ret = -ENODEV;
  6230. goto err;
  6231. }
  6232. dai_link[i].codec_of_node = np;
  6233. dai_link[i].codec_name = NULL;
  6234. }
  6235. }
  6236. err:
  6237. return ret;
  6238. }
  6239. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6240. /* FrontEnd DAI Links */
  6241. {
  6242. .name = "MSMSTUB Media1",
  6243. .stream_name = "MultiMedia1",
  6244. .cpu_dai_name = "MultiMedia1",
  6245. .platform_name = "msm-pcm-dsp.0",
  6246. .dynamic = 1,
  6247. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6248. .dpcm_playback = 1,
  6249. .dpcm_capture = 1,
  6250. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6251. SND_SOC_DPCM_TRIGGER_POST},
  6252. .codec_dai_name = "snd-soc-dummy-dai",
  6253. .codec_name = "snd-soc-dummy",
  6254. .ignore_suspend = 1,
  6255. /* this dainlink has playback support */
  6256. .ignore_pmdown_time = 1,
  6257. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6258. },
  6259. };
  6260. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6261. /* Backend DAI Links */
  6262. {
  6263. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6264. .stream_name = "VA CDC DMA0 Capture",
  6265. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6266. .platform_name = "msm-pcm-routing",
  6267. .codec_name = "bolero_codec",
  6268. .codec_dai_name = "va_macro_tx1",
  6269. .no_pcm = 1,
  6270. .dpcm_capture = 1,
  6271. .init = &msm_va_cdc_dma_init,
  6272. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6273. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6274. .ignore_suspend = 1,
  6275. .ops = &msm_cdc_dma_be_ops,
  6276. },
  6277. {
  6278. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6279. .stream_name = "VA CDC DMA1 Capture",
  6280. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6281. .platform_name = "msm-pcm-routing",
  6282. .codec_name = "bolero_codec",
  6283. .codec_dai_name = "va_macro_tx2",
  6284. .no_pcm = 1,
  6285. .dpcm_capture = 1,
  6286. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6287. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6288. .ignore_suspend = 1,
  6289. .ops = &msm_cdc_dma_be_ops,
  6290. },
  6291. };
  6292. static struct snd_soc_dai_link msm_stub_dai_links[
  6293. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6294. ARRAY_SIZE(msm_stub_be_dai_links)];
  6295. struct snd_soc_card snd_soc_card_stub_msm = {
  6296. .name = "qcs405-stub-snd-card",
  6297. };
  6298. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6299. { .compatible = "qcom,qcs405-asoc-snd",
  6300. .data = "codec"},
  6301. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6302. .data = "stub_codec"},
  6303. {},
  6304. };
  6305. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6306. {
  6307. struct snd_soc_card *card = NULL;
  6308. struct snd_soc_dai_link *dailink;
  6309. int total_links = 0;
  6310. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6311. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6312. const struct of_device_id *match;
  6313. int rc = 0;
  6314. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6315. if (!match) {
  6316. dev_err(dev, "%s: No DT match found for sound card\n",
  6317. __func__);
  6318. return NULL;
  6319. }
  6320. if (!strcmp(match->data, "codec")) {
  6321. card = &snd_soc_card_qcs405_msm;
  6322. memcpy(msm_qcs405_dai_links + total_links,
  6323. msm_common_dai_links,
  6324. sizeof(msm_common_dai_links));
  6325. total_links += ARRAY_SIZE(msm_common_dai_links);
  6326. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6327. &tasha_codec);
  6328. if (rc) {
  6329. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6330. __func__);
  6331. } else {
  6332. if (tasha_codec) {
  6333. dev_dbg(dev, "%s(): Tasha codec is present\n",
  6334. __func__);
  6335. memcpy(msm_qcs405_dai_links + total_links,
  6336. msm_tasha_fe_dai_links,
  6337. sizeof(msm_tasha_fe_dai_links));
  6338. total_links +=
  6339. ARRAY_SIZE(msm_tasha_fe_dai_links);
  6340. }
  6341. }
  6342. memcpy(msm_qcs405_dai_links + total_links,
  6343. msm_common_misc_fe_dai_links,
  6344. sizeof(msm_common_misc_fe_dai_links));
  6345. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6346. memcpy(msm_qcs405_dai_links + total_links,
  6347. msm_common_be_dai_links,
  6348. sizeof(msm_common_be_dai_links));
  6349. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6350. if (tasha_codec) {
  6351. memcpy(msm_qcs405_dai_links + total_links,
  6352. msm_tasha_be_dai_links,
  6353. sizeof(msm_tasha_be_dai_links));
  6354. total_links += ARRAY_SIZE(msm_tasha_be_dai_links);
  6355. }
  6356. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6357. &va_bolero_codec);
  6358. if (rc) {
  6359. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6360. __func__);
  6361. } else {
  6362. if (va_bolero_codec) {
  6363. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6364. __func__);
  6365. memcpy(msm_qcs405_dai_links + total_links,
  6366. msm_va_cdc_dma_be_dai_links,
  6367. sizeof(msm_va_cdc_dma_be_dai_links));
  6368. total_links +=
  6369. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6370. }
  6371. }
  6372. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6373. &wsa_bolero_codec);
  6374. if (rc) {
  6375. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6376. __func__);
  6377. } else {
  6378. if (wsa_bolero_codec) {
  6379. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6380. __func__);
  6381. memcpy(msm_qcs405_dai_links + total_links,
  6382. msm_wsa_cdc_dma_be_dai_links,
  6383. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6384. total_links +=
  6385. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6386. }
  6387. }
  6388. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6389. &mi2s_audio_intf);
  6390. if (rc) {
  6391. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6392. __func__);
  6393. } else {
  6394. if (mi2s_audio_intf) {
  6395. memcpy(msm_qcs405_dai_links + total_links,
  6396. msm_mi2s_be_dai_links,
  6397. sizeof(msm_mi2s_be_dai_links));
  6398. total_links +=
  6399. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6400. }
  6401. }
  6402. rc = of_property_read_u32(dev->of_node,
  6403. "qcom,auxpcm-audio-intf",
  6404. &auxpcm_audio_intf);
  6405. if (rc) {
  6406. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6407. __func__);
  6408. } else {
  6409. if (auxpcm_audio_intf) {
  6410. memcpy(msm_qcs405_dai_links + total_links,
  6411. msm_auxpcm_be_dai_links,
  6412. sizeof(msm_auxpcm_be_dai_links));
  6413. total_links +=
  6414. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6415. }
  6416. }
  6417. dailink = msm_qcs405_dai_links;
  6418. } else if (!strcmp(match->data, "stub_codec")) {
  6419. card = &snd_soc_card_stub_msm;
  6420. memcpy(msm_stub_dai_links + total_links,
  6421. msm_stub_fe_dai_links,
  6422. sizeof(msm_stub_fe_dai_links));
  6423. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6424. memcpy(msm_stub_dai_links + total_links,
  6425. msm_stub_be_dai_links,
  6426. sizeof(msm_stub_be_dai_links));
  6427. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6428. dailink = msm_stub_dai_links;
  6429. }
  6430. if (card) {
  6431. card->dai_link = dailink;
  6432. card->num_links = total_links;
  6433. }
  6434. return card;
  6435. }
  6436. static int msm_wsa881x_init(struct snd_soc_component *component)
  6437. {
  6438. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6439. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6440. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6441. SPKR_L_BOOST, SPKR_L_VI};
  6442. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6443. SPKR_R_BOOST, SPKR_R_VI};
  6444. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6445. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6446. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6447. struct msm_asoc_mach_data *pdata;
  6448. struct snd_soc_dapm_context *dapm;
  6449. int ret = 0;
  6450. if (!codec) {
  6451. pr_err("%s codec is NULL\n", __func__);
  6452. return -EINVAL;
  6453. }
  6454. dapm = snd_soc_codec_get_dapm(codec);
  6455. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6456. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6457. __func__, codec->component.name);
  6458. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6459. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6460. &ch_rate[0], &spkleft_port_types[0]);
  6461. if (dapm->component) {
  6462. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6463. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6464. }
  6465. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6466. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6467. __func__, codec->component.name);
  6468. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6469. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6470. &ch_rate[0], &spkright_port_types[0]);
  6471. if (dapm->component) {
  6472. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6473. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6474. }
  6475. } else {
  6476. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6477. codec->component.name);
  6478. ret = -EINVAL;
  6479. goto err;
  6480. }
  6481. pdata = snd_soc_card_get_drvdata(component->card);
  6482. if (pdata && pdata->codec_root)
  6483. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6484. codec);
  6485. err:
  6486. return ret;
  6487. }
  6488. static int msm_init_wsa_dev(struct platform_device *pdev,
  6489. struct snd_soc_card *card)
  6490. {
  6491. struct device_node *wsa_of_node;
  6492. u32 wsa_max_devs;
  6493. u32 wsa_dev_cnt;
  6494. int i;
  6495. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6496. const char *wsa_auxdev_name_prefix[1];
  6497. char *dev_name_str = NULL;
  6498. int found = 0;
  6499. int ret = 0;
  6500. /* Get maximum WSA device count for this platform */
  6501. ret = of_property_read_u32(pdev->dev.of_node,
  6502. "qcom,wsa-max-devs", &wsa_max_devs);
  6503. if (ret) {
  6504. dev_info(&pdev->dev,
  6505. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6506. __func__, pdev->dev.of_node->full_name, ret);
  6507. card->num_aux_devs = 0;
  6508. return 0;
  6509. }
  6510. if (wsa_max_devs == 0) {
  6511. dev_warn(&pdev->dev,
  6512. "%s: Max WSA devices is 0 for this target?\n",
  6513. __func__);
  6514. card->num_aux_devs = 0;
  6515. return 0;
  6516. }
  6517. /* Get count of WSA device phandles for this platform */
  6518. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6519. "qcom,wsa-devs", NULL);
  6520. if (wsa_dev_cnt == -ENOENT) {
  6521. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6522. __func__);
  6523. goto err;
  6524. } else if (wsa_dev_cnt <= 0) {
  6525. dev_err(&pdev->dev,
  6526. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6527. __func__, wsa_dev_cnt);
  6528. ret = -EINVAL;
  6529. goto err;
  6530. }
  6531. /*
  6532. * Expect total phandles count to be NOT less than maximum possible
  6533. * WSA count. However, if it is less, then assign same value to
  6534. * max count as well.
  6535. */
  6536. if (wsa_dev_cnt < wsa_max_devs) {
  6537. dev_dbg(&pdev->dev,
  6538. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6539. __func__, wsa_max_devs, wsa_dev_cnt);
  6540. wsa_max_devs = wsa_dev_cnt;
  6541. }
  6542. /* Make sure prefix string passed for each WSA device */
  6543. ret = of_property_count_strings(pdev->dev.of_node,
  6544. "qcom,wsa-aux-dev-prefix");
  6545. if (ret != wsa_dev_cnt) {
  6546. dev_err(&pdev->dev,
  6547. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6548. __func__, wsa_dev_cnt, ret);
  6549. ret = -EINVAL;
  6550. goto err;
  6551. }
  6552. /*
  6553. * Alloc mem to store phandle and index info of WSA device, if already
  6554. * registered with ALSA core
  6555. */
  6556. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6557. sizeof(struct msm_wsa881x_dev_info),
  6558. GFP_KERNEL);
  6559. if (!wsa881x_dev_info) {
  6560. ret = -ENOMEM;
  6561. goto err;
  6562. }
  6563. /*
  6564. * search and check whether all WSA devices are already
  6565. * registered with ALSA core or not. If found a node, store
  6566. * the node and the index in a local array of struct for later
  6567. * use.
  6568. */
  6569. for (i = 0; i < wsa_dev_cnt; i++) {
  6570. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6571. "qcom,wsa-devs", i);
  6572. if (unlikely(!wsa_of_node)) {
  6573. /* we should not be here */
  6574. dev_err(&pdev->dev,
  6575. "%s: wsa dev node is not present\n",
  6576. __func__);
  6577. ret = -EINVAL;
  6578. goto err_free_dev_info;
  6579. }
  6580. if (soc_find_component(wsa_of_node, NULL)) {
  6581. /* WSA device registered with ALSA core */
  6582. wsa881x_dev_info[found].of_node = wsa_of_node;
  6583. wsa881x_dev_info[found].index = i;
  6584. found++;
  6585. if (found == wsa_max_devs)
  6586. break;
  6587. }
  6588. }
  6589. if (found < wsa_max_devs) {
  6590. dev_err(&pdev->dev,
  6591. "%s: failed to find %d components. Found only %d\n",
  6592. __func__, wsa_max_devs, found);
  6593. return -EPROBE_DEFER;
  6594. }
  6595. dev_info(&pdev->dev,
  6596. "%s: found %d wsa881x devices registered with ALSA core\n",
  6597. __func__, found);
  6598. card->num_aux_devs = wsa_max_devs;
  6599. card->num_configs = wsa_max_devs;
  6600. /* Alloc array of AUX devs struct */
  6601. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6602. sizeof(struct snd_soc_aux_dev),
  6603. GFP_KERNEL);
  6604. if (!msm_aux_dev) {
  6605. ret = -ENOMEM;
  6606. goto err_free_dev_info;
  6607. }
  6608. /* Alloc array of codec conf struct */
  6609. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6610. sizeof(struct snd_soc_codec_conf),
  6611. GFP_KERNEL);
  6612. if (!msm_codec_conf) {
  6613. ret = -ENOMEM;
  6614. goto err_free_aux_dev;
  6615. }
  6616. for (i = 0; i < card->num_aux_devs; i++) {
  6617. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6618. GFP_KERNEL);
  6619. if (!dev_name_str) {
  6620. ret = -ENOMEM;
  6621. goto err_free_cdc_conf;
  6622. }
  6623. ret = of_property_read_string_index(pdev->dev.of_node,
  6624. "qcom,wsa-aux-dev-prefix",
  6625. wsa881x_dev_info[i].index,
  6626. wsa_auxdev_name_prefix);
  6627. if (ret) {
  6628. dev_err(&pdev->dev,
  6629. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6630. __func__, ret);
  6631. ret = -EINVAL;
  6632. goto err_free_dev_name_str;
  6633. }
  6634. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6635. msm_aux_dev[i].name = dev_name_str;
  6636. msm_aux_dev[i].codec_name = NULL;
  6637. msm_aux_dev[i].codec_of_node =
  6638. wsa881x_dev_info[i].of_node;
  6639. msm_aux_dev[i].init = msm_wsa881x_init;
  6640. msm_codec_conf[i].dev_name = NULL;
  6641. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6642. msm_codec_conf[i].of_node =
  6643. wsa881x_dev_info[i].of_node;
  6644. }
  6645. card->codec_conf = msm_codec_conf;
  6646. card->aux_dev = msm_aux_dev;
  6647. return 0;
  6648. err_free_dev_name_str:
  6649. devm_kfree(&pdev->dev, dev_name_str);
  6650. err_free_cdc_conf:
  6651. devm_kfree(&pdev->dev, msm_codec_conf);
  6652. err_free_aux_dev:
  6653. devm_kfree(&pdev->dev, msm_aux_dev);
  6654. err_free_dev_info:
  6655. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6656. err:
  6657. return ret;
  6658. }
  6659. static int msm_csra66x0_init(struct snd_soc_component *component)
  6660. {
  6661. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6662. if (!codec) {
  6663. pr_err("%s codec is NULL\n", __func__);
  6664. return -EINVAL;
  6665. }
  6666. return 0;
  6667. }
  6668. static int msm_init_csra_dev(struct platform_device *pdev,
  6669. struct snd_soc_card *card)
  6670. {
  6671. struct device_node *csra_of_node;
  6672. u32 csra_max_devs;
  6673. u32 csra_dev_cnt;
  6674. char *dev_name_str = NULL;
  6675. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  6676. const char *csra_auxdev_name_prefix[1];
  6677. int i;
  6678. int found = 0;
  6679. int ret = 0;
  6680. /* Get maximum CSRA device count for this platform */
  6681. ret = of_property_read_u32(pdev->dev.of_node,
  6682. "qcom,csra-max-devs", &csra_max_devs);
  6683. if (ret) {
  6684. dev_info(&pdev->dev,
  6685. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  6686. __func__, pdev->dev.of_node->full_name, ret);
  6687. card->num_aux_devs = 0;
  6688. return 0;
  6689. }
  6690. if (csra_max_devs == 0) {
  6691. dev_warn(&pdev->dev,
  6692. "%s: Max CSRA devices is 0 for this target?\n",
  6693. __func__);
  6694. return 0;
  6695. }
  6696. /* Get count of CSRA device phandles for this platform */
  6697. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6698. "qcom,csra-devs", NULL);
  6699. if (csra_dev_cnt == -ENOENT) {
  6700. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  6701. __func__);
  6702. goto err;
  6703. } else if (csra_dev_cnt <= 0) {
  6704. dev_err(&pdev->dev,
  6705. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  6706. __func__, csra_dev_cnt);
  6707. ret = -EINVAL;
  6708. goto err;
  6709. }
  6710. /*
  6711. * Expect total phandles count to be NOT less than maximum possible
  6712. * CSRA count. However, if it is less, then assign same value to
  6713. * max count as well.
  6714. */
  6715. if (csra_dev_cnt < csra_max_devs) {
  6716. dev_dbg(&pdev->dev,
  6717. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  6718. __func__, csra_max_devs, csra_dev_cnt);
  6719. csra_max_devs = csra_dev_cnt;
  6720. }
  6721. /* Make sure prefix string passed for each CSRA device */
  6722. ret = of_property_count_strings(pdev->dev.of_node,
  6723. "qcom,csra-aux-dev-prefix");
  6724. if (ret != csra_dev_cnt) {
  6725. dev_err(&pdev->dev,
  6726. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  6727. __func__, csra_dev_cnt, ret);
  6728. ret = -EINVAL;
  6729. goto err;
  6730. }
  6731. /*
  6732. * Alloc mem to store phandle and index info of CSRA device, if already
  6733. * registered with ALSA core
  6734. */
  6735. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  6736. sizeof(struct msm_csra66x0_dev_info),
  6737. GFP_KERNEL);
  6738. if (!csra66x0_dev_info) {
  6739. ret = -ENOMEM;
  6740. goto err;
  6741. }
  6742. /*
  6743. * search and check whether all CSRA devices are already
  6744. * registered with ALSA core or not. If found a node, store
  6745. * the node and the index in a local array of struct for later
  6746. * use.
  6747. */
  6748. for (i = 0; i < csra_dev_cnt; i++) {
  6749. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  6750. "qcom,csra-devs", i);
  6751. if (unlikely(!csra_of_node)) {
  6752. /* we should not be here */
  6753. dev_err(&pdev->dev,
  6754. "%s: csra dev node is not present\n",
  6755. __func__);
  6756. ret = -EINVAL;
  6757. goto err_free_dev_info;
  6758. }
  6759. if (soc_find_component(csra_of_node, NULL)) {
  6760. /* CSRA device registered with ALSA core */
  6761. csra66x0_dev_info[found].of_node = csra_of_node;
  6762. csra66x0_dev_info[found].index = i;
  6763. found++;
  6764. if (found == csra_max_devs)
  6765. break;
  6766. }
  6767. }
  6768. if (found < csra_max_devs) {
  6769. dev_dbg(&pdev->dev,
  6770. "%s: failed to find %d components. Found only %d\n",
  6771. __func__, csra_max_devs, found);
  6772. return -EPROBE_DEFER;
  6773. }
  6774. dev_info(&pdev->dev,
  6775. "%s: found %d csra66x0 devices registered with ALSA core\n",
  6776. __func__, found);
  6777. card->num_aux_devs = csra_max_devs;
  6778. card->num_configs = csra_max_devs;
  6779. /* Alloc array of AUX devs struct */
  6780. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6781. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  6782. if (!msm_aux_dev) {
  6783. ret = -ENOMEM;
  6784. goto err_free_dev_info;
  6785. }
  6786. /* Alloc array of codec conf struct */
  6787. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6788. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  6789. if (!msm_codec_conf) {
  6790. ret = -ENOMEM;
  6791. goto err_free_aux_dev;
  6792. }
  6793. for (i = 0; i < card->num_aux_devs; i++) {
  6794. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6795. GFP_KERNEL);
  6796. if (!dev_name_str) {
  6797. ret = -ENOMEM;
  6798. goto err_free_cdc_conf;
  6799. }
  6800. ret = of_property_read_string_index(pdev->dev.of_node,
  6801. "qcom,csra-aux-dev-prefix",
  6802. csra66x0_dev_info[i].index,
  6803. csra_auxdev_name_prefix);
  6804. if (ret) {
  6805. dev_err(&pdev->dev,
  6806. "%s: failed to read csra aux dev prefix, ret = %d\n",
  6807. __func__, ret);
  6808. ret = -EINVAL;
  6809. goto err_free_dev_name_str;
  6810. }
  6811. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  6812. msm_aux_dev[i].name = dev_name_str;
  6813. msm_aux_dev[i].codec_name = NULL;
  6814. msm_aux_dev[i].codec_of_node =
  6815. csra66x0_dev_info[i].of_node;
  6816. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  6817. msm_codec_conf[i].dev_name = NULL;
  6818. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  6819. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  6820. }
  6821. card->codec_conf = msm_codec_conf;
  6822. card->aux_dev = msm_aux_dev;
  6823. return 0;
  6824. err_free_dev_name_str:
  6825. devm_kfree(&pdev->dev, dev_name_str);
  6826. err_free_cdc_conf:
  6827. devm_kfree(&pdev->dev, msm_codec_conf);
  6828. err_free_aux_dev:
  6829. devm_kfree(&pdev->dev, msm_aux_dev);
  6830. err_free_dev_info:
  6831. devm_kfree(&pdev->dev, csra66x0_dev_info);
  6832. err:
  6833. return ret;
  6834. }
  6835. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6836. {
  6837. int count;
  6838. u32 mi2s_master_slave[MI2S_MAX];
  6839. int ret;
  6840. for (count = 0; count < MI2S_MAX; count++) {
  6841. mutex_init(&mi2s_intf_conf[count].lock);
  6842. mi2s_intf_conf[count].ref_cnt = 0;
  6843. }
  6844. ret = of_property_read_u32_array(pdev->dev.of_node,
  6845. "qcom,msm-mi2s-master",
  6846. mi2s_master_slave, MI2S_MAX);
  6847. if (ret) {
  6848. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6849. __func__);
  6850. } else {
  6851. for (count = 0; count < MI2S_MAX; count++) {
  6852. mi2s_intf_conf[count].msm_is_mi2s_master =
  6853. mi2s_master_slave[count];
  6854. }
  6855. }
  6856. }
  6857. static void msm_i2s_auxpcm_deinit(void)
  6858. {
  6859. int count;
  6860. for (count = 0; count < MI2S_MAX; count++) {
  6861. mutex_destroy(&mi2s_intf_conf[count].lock);
  6862. mi2s_intf_conf[count].ref_cnt = 0;
  6863. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6864. }
  6865. }
  6866. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6867. {
  6868. struct snd_soc_card *card;
  6869. struct msm_asoc_mach_data *pdata;
  6870. int ret;
  6871. u32 val;
  6872. if (!pdev->dev.of_node) {
  6873. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6874. return -EINVAL;
  6875. }
  6876. pdata = devm_kzalloc(&pdev->dev,
  6877. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6878. if (!pdata)
  6879. return -ENOMEM;
  6880. card = populate_snd_card_dailinks(&pdev->dev);
  6881. if (!card) {
  6882. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6883. ret = -EINVAL;
  6884. goto err;
  6885. }
  6886. card->dev = &pdev->dev;
  6887. platform_set_drvdata(pdev, card);
  6888. snd_soc_card_set_drvdata(card, pdata);
  6889. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6890. if (ret) {
  6891. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6892. ret);
  6893. goto err;
  6894. }
  6895. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6896. if (ret) {
  6897. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6898. ret);
  6899. goto err;
  6900. }
  6901. ret = msm_populate_dai_link_component_of_node(card);
  6902. if (ret) {
  6903. ret = -EPROBE_DEFER;
  6904. goto err;
  6905. }
  6906. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  6907. if (ret) {
  6908. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  6909. val = 0;
  6910. }
  6911. if (val) {
  6912. ret = msm_init_csra_dev(pdev, card);
  6913. if (ret)
  6914. goto err;
  6915. } else {
  6916. ret = msm_init_wsa_dev(pdev, card);
  6917. if (ret)
  6918. goto err;
  6919. }
  6920. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6921. "qcom,cdc-dmic01-gpios",
  6922. 0);
  6923. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6924. "qcom,cdc-dmic23-gpios",
  6925. 0);
  6926. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6927. "qcom,cdc-dmic45-gpios",
  6928. 0);
  6929. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6930. "qcom,cdc-dmic67-gpios",
  6931. 0);
  6932. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6933. if (ret == -EPROBE_DEFER) {
  6934. if (codec_reg_done)
  6935. ret = -EINVAL;
  6936. goto err;
  6937. } else if (ret) {
  6938. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6939. ret);
  6940. goto err;
  6941. }
  6942. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  6943. spdev = pdev;
  6944. /* Parse pinctrl info from devicetree */
  6945. ret = msm_get_pinctrl(pdev);
  6946. if (!ret) {
  6947. pr_debug("%s: pinctrl parsing successful\n", __func__);
  6948. } else {
  6949. dev_dbg(&pdev->dev,
  6950. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  6951. __func__, ret);
  6952. ret = 0;
  6953. }
  6954. msm_i2s_auxpcm_init(pdev);
  6955. is_initial_boot = true;
  6956. return 0;
  6957. err:
  6958. msm_release_pinctrl(pdev);
  6959. return ret;
  6960. }
  6961. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6962. {
  6963. audio_notifier_deregister("qcs405");
  6964. msm_i2s_auxpcm_deinit();
  6965. msm_release_pinctrl(pdev);
  6966. return 0;
  6967. }
  6968. static struct platform_driver qcs405_asoc_machine_driver = {
  6969. .driver = {
  6970. .name = DRV_NAME,
  6971. .owner = THIS_MODULE,
  6972. .pm = &snd_soc_pm_ops,
  6973. .of_match_table = qcs405_asoc_machine_of_match,
  6974. },
  6975. .probe = msm_asoc_machine_probe,
  6976. .remove = msm_asoc_machine_remove,
  6977. };
  6978. module_platform_driver(qcs405_asoc_machine_driver);
  6979. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  6980. MODULE_LICENSE("GPL v2");
  6981. MODULE_ALIAS("platform:" DRV_NAME);
  6982. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);