dp_tx.c 171 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. /**
  987. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  988. * @vdev: DP vdev handle
  989. * @nbuf: skb
  990. * @desc_pool_id: Descriptor pool ID
  991. * @meta_data: Metadata to the fw
  992. * @tx_exc_metadata: Handle that holds exception path metadata
  993. * Allocate and prepare Tx descriptor with msdu information.
  994. *
  995. * Return: Pointer to Tx Descriptor on success,
  996. * NULL on failure
  997. */
  998. static
  999. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1000. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1001. struct dp_tx_msdu_info_s *msdu_info,
  1002. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1003. {
  1004. uint8_t align_pad;
  1005. uint8_t is_exception = 0;
  1006. uint8_t htt_hdr_size;
  1007. struct dp_tx_desc_s *tx_desc;
  1008. struct dp_pdev *pdev = vdev->pdev;
  1009. struct dp_soc *soc = pdev->soc;
  1010. if (dp_tx_limit_check(vdev))
  1011. return NULL;
  1012. /* Allocate software Tx descriptor */
  1013. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1014. if (qdf_unlikely(!tx_desc)) {
  1015. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1016. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1017. return NULL;
  1018. }
  1019. dp_tx_outstanding_inc(pdev);
  1020. /* Initialize the SW tx descriptor */
  1021. tx_desc->nbuf = nbuf;
  1022. tx_desc->frm_type = dp_tx_frm_std;
  1023. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1024. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1025. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1026. tx_desc->vdev_id = vdev->vdev_id;
  1027. tx_desc->pdev = pdev;
  1028. tx_desc->msdu_ext_desc = NULL;
  1029. tx_desc->pkt_offset = 0;
  1030. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1031. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1032. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1033. if (qdf_unlikely(vdev->multipass_en)) {
  1034. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1035. goto failure;
  1036. }
  1037. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1038. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1039. is_exception = 1;
  1040. /*
  1041. * For special modes (vdev_type == ocb or mesh), data frames should be
  1042. * transmitted using varying transmit parameters (tx spec) which include
  1043. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1044. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1045. * These frames are sent as exception packets to firmware.
  1046. *
  1047. * HW requirement is that metadata should always point to a
  1048. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1049. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1050. * to get 8-byte aligned start address along with align_pad added
  1051. *
  1052. * |-----------------------------|
  1053. * | |
  1054. * |-----------------------------| <-----Buffer Pointer Address given
  1055. * | | ^ in HW descriptor (aligned)
  1056. * | HTT Metadata | |
  1057. * | | |
  1058. * | | | Packet Offset given in descriptor
  1059. * | | |
  1060. * |-----------------------------| |
  1061. * | Alignment Pad | v
  1062. * |-----------------------------| <----- Actual buffer start address
  1063. * | SKB Data | (Unaligned)
  1064. * | |
  1065. * | |
  1066. * | |
  1067. * | |
  1068. * | |
  1069. * |-----------------------------|
  1070. */
  1071. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1072. (vdev->opmode == wlan_op_mode_ocb) ||
  1073. (tx_exc_metadata &&
  1074. tx_exc_metadata->is_tx_sniffer)) {
  1075. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1076. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1077. DP_STATS_INC(vdev,
  1078. tx_i.dropped.headroom_insufficient, 1);
  1079. goto failure;
  1080. }
  1081. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1082. dp_tx_err("qdf_nbuf_push_head failed");
  1083. goto failure;
  1084. }
  1085. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1086. msdu_info);
  1087. if (htt_hdr_size == 0)
  1088. goto failure;
  1089. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1090. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1091. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1092. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1093. msdu_info);
  1094. is_exception = 1;
  1095. tx_desc->length -= tx_desc->pkt_offset;
  1096. }
  1097. #if !TQM_BYPASS_WAR
  1098. if (is_exception || tx_exc_metadata)
  1099. #endif
  1100. {
  1101. /* Temporary WAR due to TQM VP issues */
  1102. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1103. qdf_atomic_inc(&soc->num_tx_exception);
  1104. }
  1105. return tx_desc;
  1106. failure:
  1107. dp_tx_desc_release(tx_desc, desc_pool_id);
  1108. return NULL;
  1109. }
  1110. /**
  1111. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1112. * @vdev: DP vdev handle
  1113. * @nbuf: skb
  1114. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1115. * @desc_pool_id : Descriptor Pool ID
  1116. *
  1117. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1118. * information. For frames with fragments, allocate and prepare
  1119. * an MSDU extension descriptor
  1120. *
  1121. * Return: Pointer to Tx Descriptor on success,
  1122. * NULL on failure
  1123. */
  1124. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1125. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1126. uint8_t desc_pool_id)
  1127. {
  1128. struct dp_tx_desc_s *tx_desc;
  1129. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1130. struct dp_pdev *pdev = vdev->pdev;
  1131. struct dp_soc *soc = pdev->soc;
  1132. if (dp_tx_limit_check(vdev))
  1133. return NULL;
  1134. /* Allocate software Tx descriptor */
  1135. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1136. if (!tx_desc) {
  1137. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1138. return NULL;
  1139. }
  1140. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1141. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1142. dp_tx_outstanding_inc(pdev);
  1143. /* Initialize the SW tx descriptor */
  1144. tx_desc->nbuf = nbuf;
  1145. tx_desc->frm_type = msdu_info->frm_type;
  1146. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1147. tx_desc->vdev_id = vdev->vdev_id;
  1148. tx_desc->pdev = pdev;
  1149. tx_desc->pkt_offset = 0;
  1150. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1151. /* Handle scattered frames - TSO/SG/ME */
  1152. /* Allocate and prepare an extension descriptor for scattered frames */
  1153. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1154. if (!msdu_ext_desc) {
  1155. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1156. goto failure;
  1157. }
  1158. #if TQM_BYPASS_WAR
  1159. /* Temporary WAR due to TQM VP issues */
  1160. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1161. qdf_atomic_inc(&soc->num_tx_exception);
  1162. #endif
  1163. if (qdf_unlikely(msdu_info->exception_fw))
  1164. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1165. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1166. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1167. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1168. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1169. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1170. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1171. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1172. else
  1173. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1174. return tx_desc;
  1175. failure:
  1176. dp_tx_desc_release(tx_desc, desc_pool_id);
  1177. return NULL;
  1178. }
  1179. /**
  1180. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1181. * @vdev: DP vdev handle
  1182. * @nbuf: buffer pointer
  1183. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1184. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1185. * descriptor
  1186. *
  1187. * Return:
  1188. */
  1189. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1190. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1191. {
  1192. qdf_nbuf_t curr_nbuf = NULL;
  1193. uint16_t total_len = 0;
  1194. qdf_dma_addr_t paddr;
  1195. int32_t i;
  1196. int32_t mapped_buf_num = 0;
  1197. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1198. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1199. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1200. /* Continue only if frames are of DATA type */
  1201. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1202. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1203. dp_tx_debug("Pkt. recd is of not data type");
  1204. goto error;
  1205. }
  1206. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1207. if (vdev->raw_mode_war &&
  1208. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1209. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1210. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1211. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1212. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1213. /*
  1214. * Number of nbuf's must not exceed the size of the frags
  1215. * array in seg_info.
  1216. */
  1217. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1218. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1219. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1220. goto error;
  1221. }
  1222. if (QDF_STATUS_SUCCESS !=
  1223. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1224. curr_nbuf,
  1225. QDF_DMA_TO_DEVICE,
  1226. curr_nbuf->len)) {
  1227. dp_tx_err("%s dma map error ", __func__);
  1228. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1229. goto error;
  1230. }
  1231. /* Update the count of mapped nbuf's */
  1232. mapped_buf_num++;
  1233. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1234. seg_info->frags[i].paddr_lo = paddr;
  1235. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1236. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1237. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1238. total_len += qdf_nbuf_len(curr_nbuf);
  1239. }
  1240. seg_info->frag_cnt = i;
  1241. seg_info->total_len = total_len;
  1242. seg_info->next = NULL;
  1243. sg_info->curr_seg = seg_info;
  1244. msdu_info->frm_type = dp_tx_frm_raw;
  1245. msdu_info->num_seg = 1;
  1246. return nbuf;
  1247. error:
  1248. i = 0;
  1249. while (nbuf) {
  1250. curr_nbuf = nbuf;
  1251. if (i < mapped_buf_num) {
  1252. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1253. QDF_DMA_TO_DEVICE,
  1254. curr_nbuf->len);
  1255. i++;
  1256. }
  1257. nbuf = qdf_nbuf_next(nbuf);
  1258. qdf_nbuf_free(curr_nbuf);
  1259. }
  1260. return NULL;
  1261. }
  1262. /**
  1263. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1264. * @soc: DP soc handle
  1265. * @nbuf: Buffer pointer
  1266. *
  1267. * unmap the chain of nbufs that belong to this RAW frame.
  1268. *
  1269. * Return: None
  1270. */
  1271. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1272. qdf_nbuf_t nbuf)
  1273. {
  1274. qdf_nbuf_t cur_nbuf = nbuf;
  1275. do {
  1276. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1277. QDF_DMA_TO_DEVICE,
  1278. cur_nbuf->len);
  1279. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1280. } while (cur_nbuf);
  1281. }
  1282. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1283. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1284. qdf_nbuf_t nbuf)
  1285. {
  1286. qdf_nbuf_t nbuf_local;
  1287. struct dp_vdev *vdev_local = vdev_hdl;
  1288. do {
  1289. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1290. break;
  1291. nbuf_local = nbuf;
  1292. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1293. htt_cmn_pkt_type_raw))
  1294. break;
  1295. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1296. break;
  1297. else if (qdf_nbuf_is_tso((nbuf_local)))
  1298. break;
  1299. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1300. (nbuf_local),
  1301. NULL, 1, 0);
  1302. } while (0);
  1303. }
  1304. #endif
  1305. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1306. /**
  1307. * dp_tx_update_stats() - Update soc level tx stats
  1308. * @soc: DP soc handle
  1309. * @tx_desc: TX descriptor reference
  1310. * @ring_id: TCL ring id
  1311. *
  1312. * Returns: none
  1313. */
  1314. void dp_tx_update_stats(struct dp_soc *soc,
  1315. struct dp_tx_desc_s *tx_desc,
  1316. uint8_t ring_id)
  1317. {
  1318. uint32_t stats_len = 0;
  1319. if (tx_desc->frm_type == dp_tx_frm_tso)
  1320. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1321. else
  1322. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1323. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1324. }
  1325. int
  1326. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1327. struct dp_tx_desc_s *tx_desc,
  1328. uint8_t tid,
  1329. struct dp_tx_msdu_info_s *msdu_info,
  1330. uint8_t ring_id)
  1331. {
  1332. struct dp_swlm *swlm = &soc->swlm;
  1333. union swlm_data swlm_query_data;
  1334. struct dp_swlm_tcl_data tcl_data;
  1335. QDF_STATUS status;
  1336. int ret;
  1337. if (!swlm->is_enabled)
  1338. return msdu_info->skip_hp_update;
  1339. tcl_data.nbuf = tx_desc->nbuf;
  1340. tcl_data.tid = tid;
  1341. tcl_data.ring_id = ring_id;
  1342. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1343. tcl_data.pkt_len =
  1344. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1345. } else {
  1346. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1347. }
  1348. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1349. swlm_query_data.tcl_data = &tcl_data;
  1350. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1351. if (QDF_IS_STATUS_ERROR(status)) {
  1352. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1353. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1354. return 0;
  1355. }
  1356. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1357. if (ret) {
  1358. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1359. } else {
  1360. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1361. }
  1362. return ret;
  1363. }
  1364. void
  1365. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1366. int coalesce)
  1367. {
  1368. if (coalesce)
  1369. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1370. else
  1371. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1372. }
  1373. static inline void
  1374. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1375. {
  1376. if (((i + 1) < msdu_info->num_seg))
  1377. msdu_info->skip_hp_update = 1;
  1378. else
  1379. msdu_info->skip_hp_update = 0;
  1380. }
  1381. static inline void
  1382. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1383. {
  1384. hal_ring_handle_t hal_ring_hdl =
  1385. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1386. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1387. dp_err("Fillmore: SRNG access start failed");
  1388. return;
  1389. }
  1390. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1391. }
  1392. static inline void
  1393. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1394. QDF_STATUS status,
  1395. struct dp_tx_msdu_info_s *msdu_info)
  1396. {
  1397. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1398. dp_flush_tcp_hp(soc,
  1399. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1400. }
  1401. }
  1402. #else
  1403. static inline void
  1404. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1405. {
  1406. }
  1407. static inline void
  1408. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1409. QDF_STATUS status,
  1410. struct dp_tx_msdu_info_s *msdu_info)
  1411. {
  1412. }
  1413. #endif
  1414. #ifdef FEATURE_RUNTIME_PM
  1415. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1416. {
  1417. int ret;
  1418. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1419. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1420. return ret;
  1421. }
  1422. /**
  1423. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1424. * @soc: Datapath soc handle
  1425. * @hal_ring_hdl: HAL ring handle
  1426. * @coalesce: Coalesce the current write or not
  1427. *
  1428. * Wrapper for HAL ring access end for data transmission for
  1429. * FEATURE_RUNTIME_PM
  1430. *
  1431. * Returns: none
  1432. */
  1433. void
  1434. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1435. hal_ring_handle_t hal_ring_hdl,
  1436. int coalesce)
  1437. {
  1438. int ret;
  1439. /*
  1440. * Avoid runtime get and put APIs under high throughput scenarios.
  1441. */
  1442. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1443. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1444. return;
  1445. }
  1446. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1447. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1448. if (hif_system_pm_state_check(soc->hif_handle) ||
  1449. qdf_unlikely(soc->is_tx_pause)) {
  1450. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1451. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1452. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1453. } else {
  1454. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1455. }
  1456. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1457. } else {
  1458. dp_runtime_get(soc);
  1459. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1460. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1461. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1462. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1463. dp_runtime_put(soc);
  1464. }
  1465. }
  1466. #else
  1467. #ifdef DP_POWER_SAVE
  1468. void
  1469. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1470. hal_ring_handle_t hal_ring_hdl,
  1471. int coalesce)
  1472. {
  1473. if (hif_system_pm_state_check(soc->hif_handle) ||
  1474. qdf_unlikely(soc->is_tx_pause)) {
  1475. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1476. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1477. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1478. } else {
  1479. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1480. }
  1481. }
  1482. #endif
  1483. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1484. {
  1485. return 0;
  1486. }
  1487. #endif
  1488. /**
  1489. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1490. * @vdev: DP vdev handle
  1491. * @nbuf: skb
  1492. *
  1493. * Extract the DSCP or PCP information from frame and map into TID value.
  1494. *
  1495. * Return: void
  1496. */
  1497. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1498. struct dp_tx_msdu_info_s *msdu_info)
  1499. {
  1500. uint8_t tos = 0, dscp_tid_override = 0;
  1501. uint8_t *hdr_ptr, *L3datap;
  1502. uint8_t is_mcast = 0;
  1503. qdf_ether_header_t *eh = NULL;
  1504. qdf_ethervlan_header_t *evh = NULL;
  1505. uint16_t ether_type;
  1506. qdf_llc_t *llcHdr;
  1507. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1508. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1509. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1510. eh = (qdf_ether_header_t *)nbuf->data;
  1511. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1512. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1513. } else {
  1514. qdf_dot3_qosframe_t *qos_wh =
  1515. (qdf_dot3_qosframe_t *) nbuf->data;
  1516. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1517. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1518. return;
  1519. }
  1520. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1521. ether_type = eh->ether_type;
  1522. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1523. /*
  1524. * Check if packet is dot3 or eth2 type.
  1525. */
  1526. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1527. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1528. sizeof(*llcHdr));
  1529. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1530. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1531. sizeof(*llcHdr);
  1532. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1533. + sizeof(*llcHdr) +
  1534. sizeof(qdf_net_vlanhdr_t));
  1535. } else {
  1536. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1537. sizeof(*llcHdr);
  1538. }
  1539. } else {
  1540. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1541. evh = (qdf_ethervlan_header_t *) eh;
  1542. ether_type = evh->ether_type;
  1543. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1544. }
  1545. }
  1546. /*
  1547. * Find priority from IP TOS DSCP field
  1548. */
  1549. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1550. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1551. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1552. /* Only for unicast frames */
  1553. if (!is_mcast) {
  1554. /* send it on VO queue */
  1555. msdu_info->tid = DP_VO_TID;
  1556. }
  1557. } else {
  1558. /*
  1559. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1560. * from TOS byte.
  1561. */
  1562. tos = ip->ip_tos;
  1563. dscp_tid_override = 1;
  1564. }
  1565. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1566. /* TODO
  1567. * use flowlabel
  1568. *igmpmld cases to be handled in phase 2
  1569. */
  1570. unsigned long ver_pri_flowlabel;
  1571. unsigned long pri;
  1572. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1573. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1574. DP_IPV6_PRIORITY_SHIFT;
  1575. tos = pri;
  1576. dscp_tid_override = 1;
  1577. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1578. msdu_info->tid = DP_VO_TID;
  1579. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1580. /* Only for unicast frames */
  1581. if (!is_mcast) {
  1582. /* send ucast arp on VO queue */
  1583. msdu_info->tid = DP_VO_TID;
  1584. }
  1585. }
  1586. /*
  1587. * Assign all MCAST packets to BE
  1588. */
  1589. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1590. if (is_mcast) {
  1591. tos = 0;
  1592. dscp_tid_override = 1;
  1593. }
  1594. }
  1595. if (dscp_tid_override == 1) {
  1596. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1597. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1598. }
  1599. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1600. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1601. return;
  1602. }
  1603. /**
  1604. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1605. * @vdev: DP vdev handle
  1606. * @nbuf: skb
  1607. *
  1608. * Software based TID classification is required when more than 2 DSCP-TID
  1609. * mapping tables are needed.
  1610. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1611. *
  1612. * Return: void
  1613. */
  1614. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1615. struct dp_tx_msdu_info_s *msdu_info)
  1616. {
  1617. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1618. /*
  1619. * skip_sw_tid_classification flag will set in below cases-
  1620. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1621. * 2. hlos_tid_override enabled for vdev
  1622. * 3. mesh mode enabled for vdev
  1623. */
  1624. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1625. /* Update tid in msdu_info from skb priority */
  1626. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1627. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1628. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1629. if (tid == DP_TX_INVALID_QOS_TAG)
  1630. return;
  1631. msdu_info->tid = tid;
  1632. return;
  1633. }
  1634. return;
  1635. }
  1636. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1637. }
  1638. #ifdef FEATURE_WLAN_TDLS
  1639. /**
  1640. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1641. * @soc: datapath SOC
  1642. * @vdev: datapath vdev
  1643. * @tx_desc: TX descriptor
  1644. *
  1645. * Return: None
  1646. */
  1647. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1648. struct dp_vdev *vdev,
  1649. struct dp_tx_desc_s *tx_desc)
  1650. {
  1651. if (vdev) {
  1652. if (vdev->is_tdls_frame) {
  1653. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1654. vdev->is_tdls_frame = false;
  1655. }
  1656. }
  1657. }
  1658. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1659. {
  1660. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1661. switch (soc->arch_id) {
  1662. case CDP_ARCH_TYPE_LI:
  1663. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1664. break;
  1665. case CDP_ARCH_TYPE_BE:
  1666. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1667. break;
  1668. default:
  1669. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1670. QDF_BUG(0);
  1671. }
  1672. return tx_status;
  1673. }
  1674. /**
  1675. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1676. * @soc: dp_soc handle
  1677. * @tx_desc: TX descriptor
  1678. * @vdev: datapath vdev handle
  1679. *
  1680. * Return: None
  1681. */
  1682. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1683. struct dp_tx_desc_s *tx_desc)
  1684. {
  1685. uint8_t tx_status = 0;
  1686. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1687. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1688. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1689. DP_MOD_ID_TDLS);
  1690. if (qdf_unlikely(!vdev)) {
  1691. dp_err_rl("vdev is null!");
  1692. goto error;
  1693. }
  1694. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1695. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1696. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1697. if (vdev->tx_non_std_data_callback.func) {
  1698. qdf_nbuf_set_next(nbuf, NULL);
  1699. vdev->tx_non_std_data_callback.func(
  1700. vdev->tx_non_std_data_callback.ctxt,
  1701. nbuf, tx_status);
  1702. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1703. return;
  1704. } else {
  1705. dp_err_rl("callback func is null");
  1706. }
  1707. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1708. error:
  1709. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1710. qdf_nbuf_free(nbuf);
  1711. }
  1712. /**
  1713. * dp_tx_msdu_single_map() - do nbuf map
  1714. * @vdev: DP vdev handle
  1715. * @tx_desc: DP TX descriptor pointer
  1716. * @nbuf: skb pointer
  1717. *
  1718. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1719. * operation done in other component.
  1720. *
  1721. * Return: QDF_STATUS
  1722. */
  1723. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1724. struct dp_tx_desc_s *tx_desc,
  1725. qdf_nbuf_t nbuf)
  1726. {
  1727. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1728. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1729. nbuf,
  1730. QDF_DMA_TO_DEVICE,
  1731. nbuf->len);
  1732. else
  1733. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1734. QDF_DMA_TO_DEVICE);
  1735. }
  1736. #else
  1737. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1738. struct dp_vdev *vdev,
  1739. struct dp_tx_desc_s *tx_desc)
  1740. {
  1741. }
  1742. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1743. struct dp_tx_desc_s *tx_desc)
  1744. {
  1745. }
  1746. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1747. struct dp_tx_desc_s *tx_desc,
  1748. qdf_nbuf_t nbuf)
  1749. {
  1750. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1751. nbuf,
  1752. QDF_DMA_TO_DEVICE,
  1753. nbuf->len);
  1754. }
  1755. #endif
  1756. static inline
  1757. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1758. struct dp_tx_desc_s *tx_desc,
  1759. qdf_nbuf_t nbuf)
  1760. {
  1761. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1762. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1763. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1764. return 0;
  1765. return qdf_nbuf_mapped_paddr_get(nbuf);
  1766. }
  1767. static inline
  1768. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1769. {
  1770. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1771. desc->nbuf,
  1772. desc->dma_addr,
  1773. QDF_DMA_TO_DEVICE,
  1774. desc->length);
  1775. }
  1776. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1777. static inline
  1778. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1779. struct dp_tx_desc_s *tx_desc,
  1780. qdf_nbuf_t nbuf)
  1781. {
  1782. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1783. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1784. (void *)(nbuf->data + nbuf->len));
  1785. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1786. } else {
  1787. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1788. }
  1789. }
  1790. static inline
  1791. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1792. struct dp_tx_desc_s *desc)
  1793. {
  1794. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1795. return dp_tx_nbuf_unmap_regular(soc, desc);
  1796. }
  1797. #else
  1798. static inline
  1799. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1800. struct dp_tx_desc_s *tx_desc,
  1801. qdf_nbuf_t nbuf)
  1802. {
  1803. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1804. }
  1805. static inline
  1806. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1807. struct dp_tx_desc_s *desc)
  1808. {
  1809. return dp_tx_nbuf_unmap_regular(soc, desc);
  1810. }
  1811. #endif
  1812. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1813. static inline
  1814. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1815. {
  1816. dp_tx_nbuf_unmap(soc, desc);
  1817. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1818. }
  1819. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1820. {
  1821. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1822. dp_tx_nbuf_unmap(soc, desc);
  1823. }
  1824. #else
  1825. static inline
  1826. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1827. {
  1828. }
  1829. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1830. {
  1831. dp_tx_nbuf_unmap(soc, desc);
  1832. }
  1833. #endif
  1834. #ifdef MESH_MODE_SUPPORT
  1835. /**
  1836. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1837. * @soc: datapath SOC
  1838. * @vdev: datapath vdev
  1839. * @tx_desc: TX descriptor
  1840. *
  1841. * Return: None
  1842. */
  1843. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1844. struct dp_vdev *vdev,
  1845. struct dp_tx_desc_s *tx_desc)
  1846. {
  1847. if (qdf_unlikely(vdev->mesh_vdev))
  1848. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1849. }
  1850. /**
  1851. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1852. * @soc: dp_soc handle
  1853. * @tx_desc: TX descriptor
  1854. * @delayed_free: delay the nbuf free
  1855. *
  1856. * Return: nbuf to be freed late
  1857. */
  1858. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1859. struct dp_tx_desc_s *tx_desc,
  1860. bool delayed_free)
  1861. {
  1862. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1863. struct dp_vdev *vdev = NULL;
  1864. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1865. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1866. if (vdev)
  1867. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1868. if (delayed_free)
  1869. return nbuf;
  1870. qdf_nbuf_free(nbuf);
  1871. } else {
  1872. if (vdev && vdev->osif_tx_free_ext) {
  1873. vdev->osif_tx_free_ext((nbuf));
  1874. } else {
  1875. if (delayed_free)
  1876. return nbuf;
  1877. qdf_nbuf_free(nbuf);
  1878. }
  1879. }
  1880. if (vdev)
  1881. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1882. return NULL;
  1883. }
  1884. #else
  1885. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1886. struct dp_vdev *vdev,
  1887. struct dp_tx_desc_s *tx_desc)
  1888. {
  1889. }
  1890. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1891. struct dp_tx_desc_s *tx_desc,
  1892. bool delayed_free)
  1893. {
  1894. return NULL;
  1895. }
  1896. #endif
  1897. /**
  1898. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1899. * @vdev: DP vdev handle
  1900. * @nbuf: skb
  1901. *
  1902. * Return: 1 if frame needs to be dropped else 0
  1903. */
  1904. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1905. {
  1906. struct dp_pdev *pdev = NULL;
  1907. struct dp_ast_entry *src_ast_entry = NULL;
  1908. struct dp_ast_entry *dst_ast_entry = NULL;
  1909. struct dp_soc *soc = NULL;
  1910. qdf_assert(vdev);
  1911. pdev = vdev->pdev;
  1912. qdf_assert(pdev);
  1913. soc = pdev->soc;
  1914. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1915. (soc, dstmac, vdev->pdev->pdev_id);
  1916. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1917. (soc, srcmac, vdev->pdev->pdev_id);
  1918. if (dst_ast_entry && src_ast_entry) {
  1919. if (dst_ast_entry->peer_id ==
  1920. src_ast_entry->peer_id)
  1921. return 1;
  1922. }
  1923. return 0;
  1924. }
  1925. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1926. defined(WLAN_MCAST_MLO)
  1927. /* MLO peer id for reinject*/
  1928. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1929. /* MLO vdev id inc offset */
  1930. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1931. static inline void
  1932. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1933. {
  1934. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1935. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1936. qdf_atomic_inc(&soc->num_tx_exception);
  1937. }
  1938. }
  1939. static inline void
  1940. dp_tx_update_mcast_param(uint16_t peer_id,
  1941. uint16_t *htt_tcl_metadata,
  1942. struct dp_vdev *vdev,
  1943. struct dp_tx_msdu_info_s *msdu_info)
  1944. {
  1945. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1946. *htt_tcl_metadata = 0;
  1947. DP_TX_TCL_METADATA_TYPE_SET(
  1948. *htt_tcl_metadata,
  1949. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1950. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1951. msdu_info->gsn);
  1952. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1953. if (qdf_unlikely(vdev->nawds_enabled))
  1954. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  1955. *htt_tcl_metadata, 1);
  1956. } else {
  1957. msdu_info->vdev_id = vdev->vdev_id;
  1958. }
  1959. }
  1960. #else
  1961. static inline void
  1962. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1963. {
  1964. }
  1965. static inline void
  1966. dp_tx_update_mcast_param(uint16_t peer_id,
  1967. uint16_t *htt_tcl_metadata,
  1968. struct dp_vdev *vdev,
  1969. struct dp_tx_msdu_info_s *msdu_info)
  1970. {
  1971. }
  1972. #endif
  1973. #ifdef DP_TX_SW_DROP_STATS_INC
  1974. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  1975. qdf_nbuf_t nbuf,
  1976. enum cdp_tx_sw_drop drop_code)
  1977. {
  1978. /* EAPOL Drop stats */
  1979. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  1980. switch (drop_code) {
  1981. case TX_DESC_ERR:
  1982. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  1983. break;
  1984. case TX_HAL_RING_ACCESS_ERR:
  1985. DP_STATS_INC(pdev,
  1986. eap_drop_stats.tx_hal_ring_access_err, 1);
  1987. break;
  1988. case TX_DMA_MAP_ERR:
  1989. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  1990. break;
  1991. case TX_HW_ENQUEUE:
  1992. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  1993. break;
  1994. case TX_SW_ENQUEUE:
  1995. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  1996. break;
  1997. default:
  1998. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  1999. break;
  2000. }
  2001. }
  2002. }
  2003. #else
  2004. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2005. qdf_nbuf_t nbuf,
  2006. enum cdp_tx_sw_drop drop_code)
  2007. {
  2008. }
  2009. #endif
  2010. /**
  2011. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2012. * @vdev: DP vdev handle
  2013. * @nbuf: skb
  2014. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2015. * @meta_data: Metadata to the fw
  2016. * @tx_q: Tx queue to be used for this Tx frame
  2017. * @peer_id: peer_id of the peer in case of NAWDS frames
  2018. * @tx_exc_metadata: Handle that holds exception path metadata
  2019. *
  2020. * Return: NULL on success,
  2021. * nbuf when it fails to send
  2022. */
  2023. qdf_nbuf_t
  2024. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2025. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2026. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2027. {
  2028. struct dp_pdev *pdev = vdev->pdev;
  2029. struct dp_soc *soc = pdev->soc;
  2030. struct dp_tx_desc_s *tx_desc;
  2031. QDF_STATUS status;
  2032. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2033. uint16_t htt_tcl_metadata = 0;
  2034. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2035. uint8_t tid = msdu_info->tid;
  2036. struct cdp_tid_tx_stats *tid_stats = NULL;
  2037. qdf_dma_addr_t paddr;
  2038. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2039. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2040. msdu_info, tx_exc_metadata);
  2041. if (!tx_desc) {
  2042. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2043. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2044. drop_code = TX_DESC_ERR;
  2045. goto fail_return;
  2046. }
  2047. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2048. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2049. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2050. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2051. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2052. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2053. DP_TCL_METADATA_TYPE_PEER_BASED);
  2054. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2055. peer_id);
  2056. dp_tx_bypass_reinjection(soc, tx_desc);
  2057. } else
  2058. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2059. if (msdu_info->exception_fw)
  2060. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2061. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2062. !pdev->enhanced_stats_en);
  2063. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2064. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2065. if (!paddr) {
  2066. /* Handle failure */
  2067. dp_err("qdf_nbuf_map failed");
  2068. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2069. drop_code = TX_DMA_MAP_ERR;
  2070. goto release_desc;
  2071. }
  2072. tx_desc->dma_addr = paddr;
  2073. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2074. tx_desc->id, DP_TX_DESC_MAP);
  2075. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2076. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2077. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2078. htt_tcl_metadata,
  2079. tx_exc_metadata, msdu_info);
  2080. if (status != QDF_STATUS_SUCCESS) {
  2081. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2082. tx_desc, tx_q->ring_id);
  2083. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2084. tx_desc->id, DP_TX_DESC_UNMAP);
  2085. dp_tx_nbuf_unmap(soc, tx_desc);
  2086. drop_code = TX_HW_ENQUEUE;
  2087. goto release_desc;
  2088. }
  2089. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2090. return NULL;
  2091. release_desc:
  2092. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2093. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2094. fail_return:
  2095. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2096. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2097. tid_stats = &pdev->stats.tid_stats.
  2098. tid_tx_stats[tx_q->ring_id][tid];
  2099. tid_stats->swdrop_cnt[drop_code]++;
  2100. return nbuf;
  2101. }
  2102. /**
  2103. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2104. * @soc: Soc handle
  2105. * @desc: software Tx descriptor to be processed
  2106. * @delayed_free: defer freeing of nbuf
  2107. *
  2108. * Return: nbuf to be freed later
  2109. */
  2110. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2111. bool delayed_free)
  2112. {
  2113. qdf_nbuf_t nbuf = desc->nbuf;
  2114. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2115. /* nbuf already freed in vdev detach path */
  2116. if (!nbuf)
  2117. return NULL;
  2118. /* If it is TDLS mgmt, don't unmap or free the frame */
  2119. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2120. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2121. return NULL;
  2122. }
  2123. /* 0 : MSDU buffer, 1 : MLE */
  2124. if (desc->msdu_ext_desc) {
  2125. /* TSO free */
  2126. if (hal_tx_ext_desc_get_tso_enable(
  2127. desc->msdu_ext_desc->vaddr)) {
  2128. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2129. desc->id, DP_TX_COMP_MSDU_EXT);
  2130. dp_tx_tso_seg_history_add(soc,
  2131. desc->msdu_ext_desc->tso_desc,
  2132. desc->nbuf, desc->id, type);
  2133. /* unmap eash TSO seg before free the nbuf */
  2134. dp_tx_tso_unmap_segment(soc,
  2135. desc->msdu_ext_desc->tso_desc,
  2136. desc->msdu_ext_desc->
  2137. tso_num_desc);
  2138. goto nbuf_free;
  2139. }
  2140. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2141. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2142. qdf_dma_addr_t iova;
  2143. uint32_t frag_len;
  2144. uint32_t i;
  2145. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2146. QDF_DMA_TO_DEVICE,
  2147. qdf_nbuf_headlen(nbuf));
  2148. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2149. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2150. &iova,
  2151. &frag_len);
  2152. if (!iova || !frag_len)
  2153. break;
  2154. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2155. QDF_DMA_TO_DEVICE);
  2156. }
  2157. goto nbuf_free;
  2158. }
  2159. }
  2160. /* If it's ME frame, dont unmap the cloned nbuf's */
  2161. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2162. goto nbuf_free;
  2163. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2164. dp_tx_unmap(soc, desc);
  2165. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2166. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2167. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2168. return NULL;
  2169. nbuf_free:
  2170. if (delayed_free)
  2171. return nbuf;
  2172. qdf_nbuf_free(nbuf);
  2173. return NULL;
  2174. }
  2175. /**
  2176. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2177. * @soc: DP soc handle
  2178. * @nbuf: skb
  2179. * @msdu_info: MSDU info
  2180. *
  2181. * Return: None
  2182. */
  2183. static inline void
  2184. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2185. struct dp_tx_msdu_info_s *msdu_info)
  2186. {
  2187. uint32_t cur_idx;
  2188. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2189. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2190. qdf_nbuf_headlen(nbuf));
  2191. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2192. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2193. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2194. seg->frags[cur_idx].paddr_hi) << 32),
  2195. seg->frags[cur_idx].len,
  2196. QDF_DMA_TO_DEVICE);
  2197. }
  2198. /**
  2199. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2200. * @vdev: DP vdev handle
  2201. * @nbuf: skb
  2202. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2203. *
  2204. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2205. *
  2206. * Return: NULL on success,
  2207. * nbuf when it fails to send
  2208. */
  2209. #if QDF_LOCK_STATS
  2210. noinline
  2211. #else
  2212. #endif
  2213. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2214. struct dp_tx_msdu_info_s *msdu_info)
  2215. {
  2216. uint32_t i;
  2217. struct dp_pdev *pdev = vdev->pdev;
  2218. struct dp_soc *soc = pdev->soc;
  2219. struct dp_tx_desc_s *tx_desc;
  2220. bool is_cce_classified = false;
  2221. QDF_STATUS status;
  2222. uint16_t htt_tcl_metadata = 0;
  2223. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2224. struct cdp_tid_tx_stats *tid_stats = NULL;
  2225. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2226. if (msdu_info->frm_type == dp_tx_frm_me)
  2227. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2228. i = 0;
  2229. /* Print statement to track i and num_seg */
  2230. /*
  2231. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2232. * descriptors using information in msdu_info
  2233. */
  2234. while (i < msdu_info->num_seg) {
  2235. /*
  2236. * Setup Tx descriptor for an MSDU, and MSDU extension
  2237. * descriptor
  2238. */
  2239. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2240. tx_q->desc_pool_id);
  2241. if (!tx_desc) {
  2242. if (msdu_info->frm_type == dp_tx_frm_me) {
  2243. prep_desc_fail++;
  2244. dp_tx_me_free_buf(pdev,
  2245. (void *)(msdu_info->u.sg_info
  2246. .curr_seg->frags[0].vaddr));
  2247. if (prep_desc_fail == msdu_info->num_seg) {
  2248. /*
  2249. * Unmap is needed only if descriptor
  2250. * preparation failed for all segments.
  2251. */
  2252. qdf_nbuf_unmap(soc->osdev,
  2253. msdu_info->u.sg_info.
  2254. curr_seg->nbuf,
  2255. QDF_DMA_TO_DEVICE);
  2256. }
  2257. /*
  2258. * Free the nbuf for the current segment
  2259. * and make it point to the next in the list.
  2260. * For me, there are as many segments as there
  2261. * are no of clients.
  2262. */
  2263. qdf_nbuf_free(msdu_info->u.sg_info
  2264. .curr_seg->nbuf);
  2265. if (msdu_info->u.sg_info.curr_seg->next) {
  2266. msdu_info->u.sg_info.curr_seg =
  2267. msdu_info->u.sg_info
  2268. .curr_seg->next;
  2269. nbuf = msdu_info->u.sg_info
  2270. .curr_seg->nbuf;
  2271. }
  2272. i++;
  2273. continue;
  2274. }
  2275. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2276. dp_tx_tso_seg_history_add(
  2277. soc,
  2278. msdu_info->u.tso_info.curr_seg,
  2279. nbuf, 0, DP_TX_DESC_UNMAP);
  2280. dp_tx_tso_unmap_segment(soc,
  2281. msdu_info->u.tso_info.
  2282. curr_seg,
  2283. msdu_info->u.tso_info.
  2284. tso_num_seg_list);
  2285. if (msdu_info->u.tso_info.curr_seg->next) {
  2286. msdu_info->u.tso_info.curr_seg =
  2287. msdu_info->u.tso_info.curr_seg->next;
  2288. i++;
  2289. continue;
  2290. }
  2291. }
  2292. if (msdu_info->frm_type == dp_tx_frm_sg)
  2293. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2294. goto done;
  2295. }
  2296. if (msdu_info->frm_type == dp_tx_frm_me) {
  2297. tx_desc->msdu_ext_desc->me_buffer =
  2298. (struct dp_tx_me_buf_t *)msdu_info->
  2299. u.sg_info.curr_seg->frags[0].vaddr;
  2300. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2301. }
  2302. if (is_cce_classified)
  2303. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2304. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2305. if (msdu_info->exception_fw) {
  2306. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2307. }
  2308. dp_tx_is_hp_update_required(i, msdu_info);
  2309. /*
  2310. * For frames with multiple segments (TSO, ME), jump to next
  2311. * segment.
  2312. */
  2313. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2314. if (msdu_info->u.tso_info.curr_seg->next) {
  2315. msdu_info->u.tso_info.curr_seg =
  2316. msdu_info->u.tso_info.curr_seg->next;
  2317. /*
  2318. * If this is a jumbo nbuf, then increment the
  2319. * number of nbuf users for each additional
  2320. * segment of the msdu. This will ensure that
  2321. * the skb is freed only after receiving tx
  2322. * completion for all segments of an nbuf
  2323. */
  2324. qdf_nbuf_inc_users(nbuf);
  2325. /* Check with MCL if this is needed */
  2326. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2327. */
  2328. }
  2329. }
  2330. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2331. &htt_tcl_metadata,
  2332. vdev,
  2333. msdu_info);
  2334. /*
  2335. * Enqueue the Tx MSDU descriptor to HW for transmit
  2336. */
  2337. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2338. htt_tcl_metadata,
  2339. NULL, msdu_info);
  2340. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2341. if (status != QDF_STATUS_SUCCESS) {
  2342. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2343. tx_desc, tx_q->ring_id);
  2344. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2345. tid_stats = &pdev->stats.tid_stats.
  2346. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2347. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2348. if (msdu_info->frm_type == dp_tx_frm_me) {
  2349. hw_enq_fail++;
  2350. if (hw_enq_fail == msdu_info->num_seg) {
  2351. /*
  2352. * Unmap is needed only if enqueue
  2353. * failed for all segments.
  2354. */
  2355. qdf_nbuf_unmap(soc->osdev,
  2356. msdu_info->u.sg_info.
  2357. curr_seg->nbuf,
  2358. QDF_DMA_TO_DEVICE);
  2359. }
  2360. /*
  2361. * Free the nbuf for the current segment
  2362. * and make it point to the next in the list.
  2363. * For me, there are as many segments as there
  2364. * are no of clients.
  2365. */
  2366. qdf_nbuf_free(msdu_info->u.sg_info
  2367. .curr_seg->nbuf);
  2368. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2369. if (msdu_info->u.sg_info.curr_seg->next) {
  2370. msdu_info->u.sg_info.curr_seg =
  2371. msdu_info->u.sg_info
  2372. .curr_seg->next;
  2373. nbuf = msdu_info->u.sg_info
  2374. .curr_seg->nbuf;
  2375. } else
  2376. break;
  2377. i++;
  2378. continue;
  2379. }
  2380. /*
  2381. * For TSO frames, the nbuf users increment done for
  2382. * the current segment has to be reverted, since the
  2383. * hw enqueue for this segment failed
  2384. */
  2385. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2386. msdu_info->u.tso_info.curr_seg) {
  2387. /*
  2388. * unmap and free current,
  2389. * retransmit remaining segments
  2390. */
  2391. dp_tx_comp_free_buf(soc, tx_desc, false);
  2392. i++;
  2393. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2394. continue;
  2395. }
  2396. if (msdu_info->frm_type == dp_tx_frm_sg)
  2397. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2398. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2399. goto done;
  2400. }
  2401. /*
  2402. * TODO
  2403. * if tso_info structure can be modified to have curr_seg
  2404. * as first element, following 2 blocks of code (for TSO and SG)
  2405. * can be combined into 1
  2406. */
  2407. /*
  2408. * For Multicast-Unicast converted packets,
  2409. * each converted frame (for a client) is represented as
  2410. * 1 segment
  2411. */
  2412. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2413. (msdu_info->frm_type == dp_tx_frm_me)) {
  2414. if (msdu_info->u.sg_info.curr_seg->next) {
  2415. msdu_info->u.sg_info.curr_seg =
  2416. msdu_info->u.sg_info.curr_seg->next;
  2417. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2418. } else
  2419. break;
  2420. }
  2421. i++;
  2422. }
  2423. nbuf = NULL;
  2424. done:
  2425. return nbuf;
  2426. }
  2427. /**
  2428. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2429. * for SG frames
  2430. * @vdev: DP vdev handle
  2431. * @nbuf: skb
  2432. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2433. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2434. *
  2435. * Return: NULL on success,
  2436. * nbuf when it fails to send
  2437. */
  2438. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2439. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2440. {
  2441. uint32_t cur_frag, nr_frags, i;
  2442. qdf_dma_addr_t paddr;
  2443. struct dp_tx_sg_info_s *sg_info;
  2444. sg_info = &msdu_info->u.sg_info;
  2445. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2446. if (QDF_STATUS_SUCCESS !=
  2447. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2448. QDF_DMA_TO_DEVICE,
  2449. qdf_nbuf_headlen(nbuf))) {
  2450. dp_tx_err("dma map error");
  2451. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2452. qdf_nbuf_free(nbuf);
  2453. return NULL;
  2454. }
  2455. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2456. seg_info->frags[0].paddr_lo = paddr;
  2457. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2458. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2459. seg_info->frags[0].vaddr = (void *) nbuf;
  2460. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2461. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2462. nbuf, 0,
  2463. QDF_DMA_TO_DEVICE,
  2464. cur_frag)) {
  2465. dp_tx_err("frag dma map error");
  2466. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2467. goto map_err;
  2468. }
  2469. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2470. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2471. seg_info->frags[cur_frag + 1].paddr_hi =
  2472. ((uint64_t) paddr) >> 32;
  2473. seg_info->frags[cur_frag + 1].len =
  2474. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2475. }
  2476. seg_info->frag_cnt = (cur_frag + 1);
  2477. seg_info->total_len = qdf_nbuf_len(nbuf);
  2478. seg_info->next = NULL;
  2479. sg_info->curr_seg = seg_info;
  2480. msdu_info->frm_type = dp_tx_frm_sg;
  2481. msdu_info->num_seg = 1;
  2482. return nbuf;
  2483. map_err:
  2484. /* restore paddr into nbuf before calling unmap */
  2485. qdf_nbuf_mapped_paddr_set(nbuf,
  2486. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2487. ((uint64_t)
  2488. seg_info->frags[0].paddr_hi) << 32));
  2489. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2490. QDF_DMA_TO_DEVICE,
  2491. seg_info->frags[0].len);
  2492. for (i = 1; i <= cur_frag; i++) {
  2493. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2494. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2495. seg_info->frags[i].paddr_hi) << 32),
  2496. seg_info->frags[i].len,
  2497. QDF_DMA_TO_DEVICE);
  2498. }
  2499. qdf_nbuf_free(nbuf);
  2500. return NULL;
  2501. }
  2502. /**
  2503. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2504. * @vdev: DP vdev handle
  2505. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2506. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2507. *
  2508. * Return: NULL on failure,
  2509. * nbuf when extracted successfully
  2510. */
  2511. static
  2512. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2513. struct dp_tx_msdu_info_s *msdu_info,
  2514. uint16_t ppdu_cookie)
  2515. {
  2516. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2517. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2518. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2519. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2520. (msdu_info->meta_data[5], 1);
  2521. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2522. (msdu_info->meta_data[5], 1);
  2523. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2524. (msdu_info->meta_data[6], ppdu_cookie);
  2525. msdu_info->exception_fw = 1;
  2526. msdu_info->is_tx_sniffer = 1;
  2527. }
  2528. #ifdef MESH_MODE_SUPPORT
  2529. /**
  2530. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2531. and prepare msdu_info for mesh frames.
  2532. * @vdev: DP vdev handle
  2533. * @nbuf: skb
  2534. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2535. *
  2536. * Return: NULL on failure,
  2537. * nbuf when extracted successfully
  2538. */
  2539. static
  2540. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2541. struct dp_tx_msdu_info_s *msdu_info)
  2542. {
  2543. struct meta_hdr_s *mhdr;
  2544. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2545. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2546. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2547. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2548. msdu_info->exception_fw = 0;
  2549. goto remove_meta_hdr;
  2550. }
  2551. msdu_info->exception_fw = 1;
  2552. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2553. meta_data->host_tx_desc_pool = 1;
  2554. meta_data->update_peer_cache = 1;
  2555. meta_data->learning_frame = 1;
  2556. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2557. meta_data->power = mhdr->power;
  2558. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2559. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2560. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2561. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2562. meta_data->dyn_bw = 1;
  2563. meta_data->valid_pwr = 1;
  2564. meta_data->valid_mcs_mask = 1;
  2565. meta_data->valid_nss_mask = 1;
  2566. meta_data->valid_preamble_type = 1;
  2567. meta_data->valid_retries = 1;
  2568. meta_data->valid_bw_info = 1;
  2569. }
  2570. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2571. meta_data->encrypt_type = 0;
  2572. meta_data->valid_encrypt_type = 1;
  2573. meta_data->learning_frame = 0;
  2574. }
  2575. meta_data->valid_key_flags = 1;
  2576. meta_data->key_flags = (mhdr->keyix & 0x3);
  2577. remove_meta_hdr:
  2578. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2579. dp_tx_err("qdf_nbuf_pull_head failed");
  2580. qdf_nbuf_free(nbuf);
  2581. return NULL;
  2582. }
  2583. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2584. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2585. " tid %d to_fw %d",
  2586. msdu_info->meta_data[0],
  2587. msdu_info->meta_data[1],
  2588. msdu_info->meta_data[2],
  2589. msdu_info->meta_data[3],
  2590. msdu_info->meta_data[4],
  2591. msdu_info->meta_data[5],
  2592. msdu_info->tid, msdu_info->exception_fw);
  2593. return nbuf;
  2594. }
  2595. #else
  2596. static
  2597. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2598. struct dp_tx_msdu_info_s *msdu_info)
  2599. {
  2600. return nbuf;
  2601. }
  2602. #endif
  2603. /**
  2604. * dp_check_exc_metadata() - Checks if parameters are valid
  2605. * @tx_exc - holds all exception path parameters
  2606. *
  2607. * Returns true when all the parameters are valid else false
  2608. *
  2609. */
  2610. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2611. {
  2612. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2613. HTT_INVALID_TID);
  2614. bool invalid_encap_type =
  2615. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2616. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2617. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2618. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2619. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2620. tx_exc->ppdu_cookie == 0);
  2621. if (tx_exc->is_intrabss_fwd)
  2622. return true;
  2623. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2624. invalid_cookie) {
  2625. return false;
  2626. }
  2627. return true;
  2628. }
  2629. #ifdef ATH_SUPPORT_IQUE
  2630. /**
  2631. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2632. * @vdev: vdev handle
  2633. * @nbuf: skb
  2634. *
  2635. * Return: true on success,
  2636. * false on failure
  2637. */
  2638. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2639. {
  2640. qdf_ether_header_t *eh;
  2641. /* Mcast to Ucast Conversion*/
  2642. if (qdf_likely(!vdev->mcast_enhancement_en))
  2643. return true;
  2644. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2645. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2646. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2647. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2648. qdf_nbuf_set_next(nbuf, NULL);
  2649. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2650. qdf_nbuf_len(nbuf));
  2651. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2652. QDF_STATUS_SUCCESS) {
  2653. return false;
  2654. }
  2655. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2656. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2657. QDF_STATUS_SUCCESS) {
  2658. return false;
  2659. }
  2660. }
  2661. }
  2662. return true;
  2663. }
  2664. #else
  2665. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2666. {
  2667. return true;
  2668. }
  2669. #endif
  2670. /**
  2671. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2672. * @nbuf: qdf_nbuf_t
  2673. * @vdev: struct dp_vdev *
  2674. *
  2675. * Allow packet for processing only if it is for peer client which is
  2676. * connected with same vap. Drop packet if client is connected to
  2677. * different vap.
  2678. *
  2679. * Return: QDF_STATUS
  2680. */
  2681. static inline QDF_STATUS
  2682. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2683. {
  2684. struct dp_ast_entry *dst_ast_entry = NULL;
  2685. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2686. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2687. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2688. return QDF_STATUS_SUCCESS;
  2689. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2690. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2691. eh->ether_dhost,
  2692. vdev->vdev_id);
  2693. /* If there is no ast entry, return failure */
  2694. if (qdf_unlikely(!dst_ast_entry)) {
  2695. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2696. return QDF_STATUS_E_FAILURE;
  2697. }
  2698. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2699. return QDF_STATUS_SUCCESS;
  2700. }
  2701. /**
  2702. * dp_tx_nawds_handler() - NAWDS handler
  2703. *
  2704. * @soc: DP soc handle
  2705. * @vdev_id: id of DP vdev handle
  2706. * @msdu_info: msdu_info required to create HTT metadata
  2707. * @nbuf: skb
  2708. *
  2709. * This API transfers the multicast frames with the peer id
  2710. * on NAWDS enabled peer.
  2711. * Return: none
  2712. */
  2713. static inline
  2714. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2715. struct dp_tx_msdu_info_s *msdu_info,
  2716. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2717. {
  2718. struct dp_peer *peer = NULL;
  2719. qdf_nbuf_t nbuf_clone = NULL;
  2720. uint16_t peer_id = DP_INVALID_PEER;
  2721. struct dp_txrx_peer *txrx_peer;
  2722. /* This check avoids pkt forwarding which is entered
  2723. * in the ast table but still doesn't have valid peerid.
  2724. */
  2725. if (sa_peer_id == HTT_INVALID_PEER)
  2726. return;
  2727. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2728. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2729. txrx_peer = dp_get_txrx_peer(peer);
  2730. if (!txrx_peer)
  2731. continue;
  2732. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2733. peer_id = peer->peer_id;
  2734. if (!dp_peer_is_primary_link_peer(peer))
  2735. continue;
  2736. /* Multicast packets needs to be
  2737. * dropped in case of intra bss forwarding
  2738. */
  2739. if (sa_peer_id == txrx_peer->peer_id) {
  2740. dp_tx_debug("multicast packet");
  2741. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2742. tx.nawds_mcast_drop,
  2743. 1);
  2744. continue;
  2745. }
  2746. nbuf_clone = qdf_nbuf_clone(nbuf);
  2747. if (!nbuf_clone) {
  2748. QDF_TRACE(QDF_MODULE_ID_DP,
  2749. QDF_TRACE_LEVEL_ERROR,
  2750. FL("nbuf clone failed"));
  2751. break;
  2752. }
  2753. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2754. msdu_info, peer_id,
  2755. NULL);
  2756. if (nbuf_clone) {
  2757. dp_tx_debug("pkt send failed");
  2758. qdf_nbuf_free(nbuf_clone);
  2759. } else {
  2760. if (peer_id != DP_INVALID_PEER)
  2761. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2762. tx.nawds_mcast,
  2763. 1, qdf_nbuf_len(nbuf));
  2764. }
  2765. }
  2766. }
  2767. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2768. }
  2769. /**
  2770. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2771. * @soc: DP soc handle
  2772. * @vdev_id: id of DP vdev handle
  2773. * @nbuf: skb
  2774. * @tx_exc_metadata: Handle that holds exception path meta data
  2775. *
  2776. * Entry point for Core Tx layer (DP_TX) invoked from
  2777. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2778. *
  2779. * Return: NULL on success,
  2780. * nbuf when it fails to send
  2781. */
  2782. qdf_nbuf_t
  2783. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2784. qdf_nbuf_t nbuf,
  2785. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2786. {
  2787. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2788. qdf_ether_header_t *eh = NULL;
  2789. struct dp_tx_msdu_info_s msdu_info;
  2790. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2791. DP_MOD_ID_TX_EXCEPTION);
  2792. if (qdf_unlikely(!vdev))
  2793. goto fail;
  2794. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2795. if (!tx_exc_metadata)
  2796. goto fail;
  2797. msdu_info.tid = tx_exc_metadata->tid;
  2798. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2799. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2800. QDF_MAC_ADDR_REF(nbuf->data));
  2801. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2802. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2803. dp_tx_err("Invalid parameters in exception path");
  2804. goto fail;
  2805. }
  2806. /* for peer based metadata check if peer is valid */
  2807. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2808. struct dp_peer *peer = NULL;
  2809. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2810. tx_exc_metadata->peer_id,
  2811. DP_MOD_ID_TX_EXCEPTION);
  2812. if (qdf_unlikely(!peer)) {
  2813. DP_STATS_INC(vdev,
  2814. tx_i.dropped.invalid_peer_id_in_exc_path,
  2815. 1);
  2816. goto fail;
  2817. }
  2818. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2819. }
  2820. /* Basic sanity checks for unsupported packets */
  2821. /* MESH mode */
  2822. if (qdf_unlikely(vdev->mesh_vdev)) {
  2823. dp_tx_err("Mesh mode is not supported in exception path");
  2824. goto fail;
  2825. }
  2826. /*
  2827. * Classify the frame and call corresponding
  2828. * "prepare" function which extracts the segment (TSO)
  2829. * and fragmentation information (for TSO , SG, ME, or Raw)
  2830. * into MSDU_INFO structure which is later used to fill
  2831. * SW and HW descriptors.
  2832. */
  2833. if (qdf_nbuf_is_tso(nbuf)) {
  2834. dp_verbose_debug("TSO frame %pK", vdev);
  2835. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2836. qdf_nbuf_len(nbuf));
  2837. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2838. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2839. qdf_nbuf_len(nbuf));
  2840. goto fail;
  2841. }
  2842. goto send_multiple;
  2843. }
  2844. /* SG */
  2845. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2846. struct dp_tx_seg_info_s seg_info = {0};
  2847. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2848. if (!nbuf)
  2849. goto fail;
  2850. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2851. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2852. qdf_nbuf_len(nbuf));
  2853. goto send_multiple;
  2854. }
  2855. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2856. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2857. qdf_nbuf_len(nbuf));
  2858. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2859. tx_exc_metadata->ppdu_cookie);
  2860. }
  2861. /*
  2862. * Get HW Queue to use for this frame.
  2863. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2864. * dedicated for data and 1 for command.
  2865. * "queue_id" maps to one hardware ring.
  2866. * With each ring, we also associate a unique Tx descriptor pool
  2867. * to minimize lock contention for these resources.
  2868. */
  2869. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2870. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2871. if (qdf_unlikely(vdev->nawds_enabled)) {
  2872. /*
  2873. * This is a multicast packet
  2874. */
  2875. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2876. tx_exc_metadata->peer_id);
  2877. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2878. 1, qdf_nbuf_len(nbuf));
  2879. }
  2880. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2881. DP_INVALID_PEER, NULL);
  2882. } else {
  2883. /*
  2884. * Check exception descriptors
  2885. */
  2886. if (dp_tx_exception_limit_check(vdev))
  2887. goto fail;
  2888. /* Single linear frame */
  2889. /*
  2890. * If nbuf is a simple linear frame, use send_single function to
  2891. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2892. * SRNG. There is no need to setup a MSDU extension descriptor.
  2893. */
  2894. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2895. tx_exc_metadata->peer_id,
  2896. tx_exc_metadata);
  2897. }
  2898. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2899. return nbuf;
  2900. send_multiple:
  2901. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2902. fail:
  2903. if (vdev)
  2904. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2905. dp_verbose_debug("pkt send failed");
  2906. return nbuf;
  2907. }
  2908. /**
  2909. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2910. * in exception path in special case to avoid regular exception path chk.
  2911. * @soc: DP soc handle
  2912. * @vdev_id: id of DP vdev handle
  2913. * @nbuf: skb
  2914. * @tx_exc_metadata: Handle that holds exception path meta data
  2915. *
  2916. * Entry point for Core Tx layer (DP_TX) invoked from
  2917. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2918. *
  2919. * Return: NULL on success,
  2920. * nbuf when it fails to send
  2921. */
  2922. qdf_nbuf_t
  2923. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2924. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2925. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2926. {
  2927. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2928. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2929. DP_MOD_ID_TX_EXCEPTION);
  2930. if (qdf_unlikely(!vdev))
  2931. goto fail;
  2932. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2933. == QDF_STATUS_E_FAILURE)) {
  2934. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2935. goto fail;
  2936. }
  2937. /* Unref count as it will again be taken inside dp_tx_exception */
  2938. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2939. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2940. fail:
  2941. if (vdev)
  2942. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2943. dp_verbose_debug("pkt send failed");
  2944. return nbuf;
  2945. }
  2946. /**
  2947. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2948. * @soc: DP soc handle
  2949. * @vdev_id: DP vdev handle
  2950. * @nbuf: skb
  2951. *
  2952. * Entry point for Core Tx layer (DP_TX) invoked from
  2953. * hard_start_xmit in OSIF/HDD
  2954. *
  2955. * Return: NULL on success,
  2956. * nbuf when it fails to send
  2957. */
  2958. #ifdef MESH_MODE_SUPPORT
  2959. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2960. qdf_nbuf_t nbuf)
  2961. {
  2962. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2963. struct meta_hdr_s *mhdr;
  2964. qdf_nbuf_t nbuf_mesh = NULL;
  2965. qdf_nbuf_t nbuf_clone = NULL;
  2966. struct dp_vdev *vdev;
  2967. uint8_t no_enc_frame = 0;
  2968. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2969. if (!nbuf_mesh) {
  2970. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2971. "qdf_nbuf_unshare failed");
  2972. return nbuf;
  2973. }
  2974. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2975. if (!vdev) {
  2976. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2977. "vdev is NULL for vdev_id %d", vdev_id);
  2978. return nbuf;
  2979. }
  2980. nbuf = nbuf_mesh;
  2981. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2982. if ((vdev->sec_type != cdp_sec_type_none) &&
  2983. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2984. no_enc_frame = 1;
  2985. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2986. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2987. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2988. !no_enc_frame) {
  2989. nbuf_clone = qdf_nbuf_clone(nbuf);
  2990. if (!nbuf_clone) {
  2991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2992. "qdf_nbuf_clone failed");
  2993. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2994. return nbuf;
  2995. }
  2996. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2997. }
  2998. if (nbuf_clone) {
  2999. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3000. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3001. } else {
  3002. qdf_nbuf_free(nbuf_clone);
  3003. }
  3004. }
  3005. if (no_enc_frame)
  3006. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3007. else
  3008. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3009. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3010. if ((!nbuf) && no_enc_frame) {
  3011. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3012. }
  3013. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3014. return nbuf;
  3015. }
  3016. #else
  3017. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3018. qdf_nbuf_t nbuf)
  3019. {
  3020. return dp_tx_send(soc, vdev_id, nbuf);
  3021. }
  3022. #endif
  3023. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3024. static inline
  3025. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3026. {
  3027. if (nbuf) {
  3028. qdf_prefetch(&nbuf->len);
  3029. qdf_prefetch(&nbuf->data);
  3030. }
  3031. }
  3032. #else
  3033. static inline
  3034. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3035. {
  3036. }
  3037. #endif
  3038. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3039. /*
  3040. * dp_tx_drop() - Drop the frame on a given VAP
  3041. * @soc: DP soc handle
  3042. * @vdev_id: id of DP vdev handle
  3043. * @nbuf: skb
  3044. *
  3045. * Drop all the incoming packets
  3046. *
  3047. * Return: nbuf
  3048. *
  3049. */
  3050. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3051. qdf_nbuf_t nbuf)
  3052. {
  3053. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3054. struct dp_vdev *vdev = NULL;
  3055. vdev = soc->vdev_id_map[vdev_id];
  3056. if (qdf_unlikely(!vdev))
  3057. return nbuf;
  3058. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3059. return nbuf;
  3060. }
  3061. /*
  3062. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3063. * @soc: DP soc handle
  3064. * @vdev_id: id of DP vdev handle
  3065. * @nbuf: skb
  3066. * @tx_exc_metadata: Handle that holds exception path meta data
  3067. *
  3068. * Drop all the incoming packets
  3069. *
  3070. * Return: nbuf
  3071. *
  3072. */
  3073. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3074. qdf_nbuf_t nbuf,
  3075. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3076. {
  3077. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3078. }
  3079. #endif
  3080. /*
  3081. * dp_tx_send() - Transmit a frame on a given VAP
  3082. * @soc: DP soc handle
  3083. * @vdev_id: id of DP vdev handle
  3084. * @nbuf: skb
  3085. *
  3086. * Entry point for Core Tx layer (DP_TX) invoked from
  3087. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3088. * cases
  3089. *
  3090. * Return: NULL on success,
  3091. * nbuf when it fails to send
  3092. */
  3093. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3094. qdf_nbuf_t nbuf)
  3095. {
  3096. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3097. uint16_t peer_id = HTT_INVALID_PEER;
  3098. /*
  3099. * doing a memzero is causing additional function call overhead
  3100. * so doing static stack clearing
  3101. */
  3102. struct dp_tx_msdu_info_s msdu_info = {0};
  3103. struct dp_vdev *vdev = NULL;
  3104. qdf_nbuf_t end_nbuf = NULL;
  3105. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3106. return nbuf;
  3107. /*
  3108. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3109. * this in per packet path.
  3110. *
  3111. * As in this path vdev memory is already protected with netdev
  3112. * tx lock
  3113. */
  3114. vdev = soc->vdev_id_map[vdev_id];
  3115. if (qdf_unlikely(!vdev))
  3116. return nbuf;
  3117. /*
  3118. * Set Default Host TID value to invalid TID
  3119. * (TID override disabled)
  3120. */
  3121. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3122. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3123. if (qdf_unlikely(vdev->mesh_vdev)) {
  3124. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3125. &msdu_info);
  3126. if (!nbuf_mesh) {
  3127. dp_verbose_debug("Extracting mesh metadata failed");
  3128. return nbuf;
  3129. }
  3130. nbuf = nbuf_mesh;
  3131. }
  3132. /*
  3133. * Get HW Queue to use for this frame.
  3134. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3135. * dedicated for data and 1 for command.
  3136. * "queue_id" maps to one hardware ring.
  3137. * With each ring, we also associate a unique Tx descriptor pool
  3138. * to minimize lock contention for these resources.
  3139. */
  3140. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3141. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3142. 1);
  3143. /*
  3144. * TCL H/W supports 2 DSCP-TID mapping tables.
  3145. * Table 1 - Default DSCP-TID mapping table
  3146. * Table 2 - 1 DSCP-TID override table
  3147. *
  3148. * If we need a different DSCP-TID mapping for this vap,
  3149. * call tid_classify to extract DSCP/ToS from frame and
  3150. * map to a TID and store in msdu_info. This is later used
  3151. * to fill in TCL Input descriptor (per-packet TID override).
  3152. */
  3153. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3154. /*
  3155. * Classify the frame and call corresponding
  3156. * "prepare" function which extracts the segment (TSO)
  3157. * and fragmentation information (for TSO , SG, ME, or Raw)
  3158. * into MSDU_INFO structure which is later used to fill
  3159. * SW and HW descriptors.
  3160. */
  3161. if (qdf_nbuf_is_tso(nbuf)) {
  3162. dp_verbose_debug("TSO frame %pK", vdev);
  3163. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3164. qdf_nbuf_len(nbuf));
  3165. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3166. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3167. qdf_nbuf_len(nbuf));
  3168. return nbuf;
  3169. }
  3170. goto send_multiple;
  3171. }
  3172. /* SG */
  3173. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3174. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3175. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3176. return nbuf;
  3177. } else {
  3178. struct dp_tx_seg_info_s seg_info = {0};
  3179. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3180. &msdu_info);
  3181. if (!nbuf)
  3182. return NULL;
  3183. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3184. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3185. qdf_nbuf_len(nbuf));
  3186. goto send_multiple;
  3187. }
  3188. }
  3189. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3190. return NULL;
  3191. /* RAW */
  3192. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3193. struct dp_tx_seg_info_s seg_info = {0};
  3194. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3195. if (!nbuf)
  3196. return NULL;
  3197. dp_verbose_debug("Raw frame %pK", vdev);
  3198. goto send_multiple;
  3199. }
  3200. if (qdf_unlikely(vdev->nawds_enabled)) {
  3201. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3202. qdf_nbuf_data(nbuf);
  3203. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3204. uint16_t sa_peer_id = DP_INVALID_PEER;
  3205. if (!soc->ast_offload_support) {
  3206. struct dp_ast_entry *ast_entry = NULL;
  3207. qdf_spin_lock_bh(&soc->ast_lock);
  3208. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3209. (soc,
  3210. (uint8_t *)(eh->ether_shost),
  3211. vdev->pdev->pdev_id);
  3212. if (ast_entry)
  3213. sa_peer_id = ast_entry->peer_id;
  3214. qdf_spin_unlock_bh(&soc->ast_lock);
  3215. }
  3216. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3217. sa_peer_id);
  3218. }
  3219. peer_id = DP_INVALID_PEER;
  3220. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3221. 1, qdf_nbuf_len(nbuf));
  3222. }
  3223. /* Single linear frame */
  3224. /*
  3225. * If nbuf is a simple linear frame, use send_single function to
  3226. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3227. * SRNG. There is no need to setup a MSDU extension descriptor.
  3228. */
  3229. dp_tx_prefetch_nbuf_data(nbuf);
  3230. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3231. peer_id, end_nbuf);
  3232. return nbuf;
  3233. send_multiple:
  3234. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3235. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3236. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3237. return nbuf;
  3238. }
  3239. /**
  3240. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3241. * case to vaoid check in perpkt path.
  3242. * @soc: DP soc handle
  3243. * @vdev_id: id of DP vdev handle
  3244. * @nbuf: skb
  3245. *
  3246. * Entry point for Core Tx layer (DP_TX) invoked from
  3247. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3248. * with special condition to avoid per pkt check in dp_tx_send
  3249. *
  3250. * Return: NULL on success,
  3251. * nbuf when it fails to send
  3252. */
  3253. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3254. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3255. {
  3256. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3257. struct dp_vdev *vdev = NULL;
  3258. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3259. return nbuf;
  3260. /*
  3261. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3262. * this in per packet path.
  3263. *
  3264. * As in this path vdev memory is already protected with netdev
  3265. * tx lock
  3266. */
  3267. vdev = soc->vdev_id_map[vdev_id];
  3268. if (qdf_unlikely(!vdev))
  3269. return nbuf;
  3270. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3271. == QDF_STATUS_E_FAILURE)) {
  3272. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3273. return nbuf;
  3274. }
  3275. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3276. }
  3277. #ifdef UMAC_SUPPORT_PROXY_ARP
  3278. /**
  3279. * dp_tx_proxy_arp() - Tx proxy arp handler
  3280. * @vdev: datapath vdev handle
  3281. * @buf: sk buffer
  3282. *
  3283. * Return: status
  3284. */
  3285. static inline
  3286. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3287. {
  3288. if (vdev->osif_proxy_arp)
  3289. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3290. /*
  3291. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3292. * osif_proxy_arp has a valid function pointer assigned
  3293. * to it
  3294. */
  3295. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3296. return QDF_STATUS_NOT_INITIALIZED;
  3297. }
  3298. #else
  3299. /**
  3300. * dp_tx_proxy_arp() - Tx proxy arp handler
  3301. * @vdev: datapath vdev handle
  3302. * @buf: sk buffer
  3303. *
  3304. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3305. * is not defined.
  3306. *
  3307. * Return: status
  3308. */
  3309. static inline
  3310. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3311. {
  3312. return QDF_STATUS_SUCCESS;
  3313. }
  3314. #endif
  3315. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3316. #ifdef WLAN_MCAST_MLO
  3317. static bool
  3318. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3319. struct dp_tx_desc_s *tx_desc,
  3320. qdf_nbuf_t nbuf,
  3321. uint8_t reinject_reason)
  3322. {
  3323. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3324. if (soc->arch_ops.dp_tx_mcast_handler)
  3325. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3326. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3327. return true;
  3328. }
  3329. return false;
  3330. }
  3331. #else /* WLAN_MCAST_MLO */
  3332. static inline bool
  3333. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3334. struct dp_tx_desc_s *tx_desc,
  3335. qdf_nbuf_t nbuf,
  3336. uint8_t reinject_reason)
  3337. {
  3338. return false;
  3339. }
  3340. #endif /* WLAN_MCAST_MLO */
  3341. #else
  3342. static inline bool
  3343. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3344. struct dp_tx_desc_s *tx_desc,
  3345. qdf_nbuf_t nbuf,
  3346. uint8_t reinject_reason)
  3347. {
  3348. return false;
  3349. }
  3350. #endif
  3351. /**
  3352. * dp_tx_reinject_handler() - Tx Reinject Handler
  3353. * @soc: datapath soc handle
  3354. * @vdev: datapath vdev handle
  3355. * @tx_desc: software descriptor head pointer
  3356. * @status : Tx completion status from HTT descriptor
  3357. * @reinject_reason : reinject reason from HTT descriptor
  3358. *
  3359. * This function reinjects frames back to Target.
  3360. * Todo - Host queue needs to be added
  3361. *
  3362. * Return: none
  3363. */
  3364. void dp_tx_reinject_handler(struct dp_soc *soc,
  3365. struct dp_vdev *vdev,
  3366. struct dp_tx_desc_s *tx_desc,
  3367. uint8_t *status,
  3368. uint8_t reinject_reason)
  3369. {
  3370. struct dp_peer *peer = NULL;
  3371. uint32_t peer_id = HTT_INVALID_PEER;
  3372. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3373. qdf_nbuf_t nbuf_copy = NULL;
  3374. struct dp_tx_msdu_info_s msdu_info;
  3375. #ifdef WDS_VENDOR_EXTENSION
  3376. int is_mcast = 0, is_ucast = 0;
  3377. int num_peers_3addr = 0;
  3378. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3379. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3380. #endif
  3381. struct dp_txrx_peer *txrx_peer;
  3382. qdf_assert(vdev);
  3383. dp_tx_debug("Tx reinject path");
  3384. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3385. qdf_nbuf_len(tx_desc->nbuf));
  3386. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3387. return;
  3388. #ifdef WDS_VENDOR_EXTENSION
  3389. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3390. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3391. } else {
  3392. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3393. }
  3394. is_ucast = !is_mcast;
  3395. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3396. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3397. txrx_peer = dp_get_txrx_peer(peer);
  3398. if (!txrx_peer || txrx_peer->bss_peer)
  3399. continue;
  3400. /* Detect wds peers that use 3-addr framing for mcast.
  3401. * if there are any, the bss_peer is used to send the
  3402. * the mcast frame using 3-addr format. all wds enabled
  3403. * peers that use 4-addr framing for mcast frames will
  3404. * be duplicated and sent as 4-addr frames below.
  3405. */
  3406. if (!txrx_peer->wds_enabled ||
  3407. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3408. num_peers_3addr = 1;
  3409. break;
  3410. }
  3411. }
  3412. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3413. #endif
  3414. if (qdf_unlikely(vdev->mesh_vdev)) {
  3415. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3416. } else {
  3417. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3418. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3419. txrx_peer = dp_get_txrx_peer(peer);
  3420. if (!txrx_peer)
  3421. continue;
  3422. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3423. #ifdef WDS_VENDOR_EXTENSION
  3424. /*
  3425. * . if 3-addr STA, then send on BSS Peer
  3426. * . if Peer WDS enabled and accept 4-addr mcast,
  3427. * send mcast on that peer only
  3428. * . if Peer WDS enabled and accept 4-addr ucast,
  3429. * send ucast on that peer only
  3430. */
  3431. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3432. (txrx_peer->wds_enabled &&
  3433. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3434. (is_ucast &&
  3435. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3436. #else
  3437. (txrx_peer->bss_peer &&
  3438. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3439. #endif
  3440. peer_id = DP_INVALID_PEER;
  3441. nbuf_copy = qdf_nbuf_copy(nbuf);
  3442. if (!nbuf_copy) {
  3443. dp_tx_debug("nbuf copy failed");
  3444. break;
  3445. }
  3446. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3447. dp_tx_get_queue(vdev, nbuf,
  3448. &msdu_info.tx_queue);
  3449. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3450. nbuf_copy,
  3451. &msdu_info,
  3452. peer_id,
  3453. NULL);
  3454. if (nbuf_copy) {
  3455. dp_tx_debug("pkt send failed");
  3456. qdf_nbuf_free(nbuf_copy);
  3457. }
  3458. }
  3459. }
  3460. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3461. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3462. QDF_DMA_TO_DEVICE, nbuf->len);
  3463. qdf_nbuf_free(nbuf);
  3464. }
  3465. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3466. }
  3467. /**
  3468. * dp_tx_inspect_handler() - Tx Inspect Handler
  3469. * @soc: datapath soc handle
  3470. * @vdev: datapath vdev handle
  3471. * @tx_desc: software descriptor head pointer
  3472. * @status : Tx completion status from HTT descriptor
  3473. *
  3474. * Handles Tx frames sent back to Host for inspection
  3475. * (ProxyARP)
  3476. *
  3477. * Return: none
  3478. */
  3479. void dp_tx_inspect_handler(struct dp_soc *soc,
  3480. struct dp_vdev *vdev,
  3481. struct dp_tx_desc_s *tx_desc,
  3482. uint8_t *status)
  3483. {
  3484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3485. "%s Tx inspect path",
  3486. __func__);
  3487. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3488. qdf_nbuf_len(tx_desc->nbuf));
  3489. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3490. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3491. }
  3492. #ifdef MESH_MODE_SUPPORT
  3493. /**
  3494. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3495. * in mesh meta header
  3496. * @tx_desc: software descriptor head pointer
  3497. * @ts: pointer to tx completion stats
  3498. * Return: none
  3499. */
  3500. static
  3501. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3502. struct hal_tx_completion_status *ts)
  3503. {
  3504. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3505. if (!tx_desc->msdu_ext_desc) {
  3506. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3507. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3508. "netbuf %pK offset %d",
  3509. netbuf, tx_desc->pkt_offset);
  3510. return;
  3511. }
  3512. }
  3513. }
  3514. #else
  3515. static
  3516. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3517. struct hal_tx_completion_status *ts)
  3518. {
  3519. }
  3520. #endif
  3521. #ifdef CONFIG_SAWF
  3522. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3523. struct dp_vdev *vdev,
  3524. struct dp_txrx_peer *txrx_peer,
  3525. struct dp_tx_desc_s *tx_desc,
  3526. struct hal_tx_completion_status *ts,
  3527. uint8_t tid)
  3528. {
  3529. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3530. ts, tid);
  3531. }
  3532. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3533. uint32_t nw_delay,
  3534. uint32_t sw_delay,
  3535. uint32_t hw_delay)
  3536. {
  3537. dp_peer_tid_delay_avg(tx_delay,
  3538. nw_delay,
  3539. sw_delay,
  3540. hw_delay);
  3541. }
  3542. #else
  3543. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3544. struct dp_vdev *vdev,
  3545. struct dp_txrx_peer *txrx_peer,
  3546. struct dp_tx_desc_s *tx_desc,
  3547. struct hal_tx_completion_status *ts,
  3548. uint8_t tid)
  3549. {
  3550. }
  3551. static inline void
  3552. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3553. uint32_t nw_delay, uint32_t sw_delay,
  3554. uint32_t hw_delay)
  3555. {
  3556. }
  3557. #endif
  3558. #ifdef QCA_PEER_EXT_STATS
  3559. #ifdef WLAN_CONFIG_TX_DELAY
  3560. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3561. struct dp_tx_desc_s *tx_desc,
  3562. struct hal_tx_completion_status *ts,
  3563. struct dp_vdev *vdev)
  3564. {
  3565. struct dp_soc *soc = vdev->pdev->soc;
  3566. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3567. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3568. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3569. if (!ts->valid)
  3570. return;
  3571. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3572. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3573. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3574. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3575. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3576. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3577. &fwhw_transmit_delay))
  3578. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3579. fwhw_transmit_delay);
  3580. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3581. fwhw_transmit_delay);
  3582. }
  3583. #else
  3584. /*
  3585. * dp_tx_compute_tid_delay() - Compute per TID delay
  3586. * @stats: Per TID delay stats
  3587. * @tx_desc: Software Tx descriptor
  3588. * @ts: Tx completion status
  3589. * @vdev: vdev
  3590. *
  3591. * Compute the software enqueue and hw enqueue delays and
  3592. * update the respective histograms
  3593. *
  3594. * Return: void
  3595. */
  3596. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3597. struct dp_tx_desc_s *tx_desc,
  3598. struct hal_tx_completion_status *ts,
  3599. struct dp_vdev *vdev)
  3600. {
  3601. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3602. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3603. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3604. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3605. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3606. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3607. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3608. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3609. timestamp_hw_enqueue);
  3610. /*
  3611. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3612. */
  3613. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3614. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3615. }
  3616. #endif
  3617. /*
  3618. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3619. * @txrx_peer: DP peer context
  3620. * @tx_desc: Tx software descriptor
  3621. * @tid: Transmission ID
  3622. * @ring_id: Rx CPU context ID/CPU_ID
  3623. *
  3624. * Update the peer extended stats. These are enhanced other
  3625. * delay stats per msdu level.
  3626. *
  3627. * Return: void
  3628. */
  3629. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3630. struct dp_tx_desc_s *tx_desc,
  3631. struct hal_tx_completion_status *ts,
  3632. uint8_t ring_id)
  3633. {
  3634. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3635. struct dp_soc *soc = NULL;
  3636. struct dp_peer_delay_stats *delay_stats = NULL;
  3637. uint8_t tid;
  3638. soc = pdev->soc;
  3639. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3640. return;
  3641. tid = ts->tid;
  3642. delay_stats = txrx_peer->delay_stats;
  3643. qdf_assert(delay_stats);
  3644. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3645. /*
  3646. * For non-TID packets use the TID 9
  3647. */
  3648. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3649. tid = CDP_MAX_DATA_TIDS - 1;
  3650. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3651. tx_desc, ts, txrx_peer->vdev);
  3652. }
  3653. #else
  3654. static inline
  3655. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3656. struct dp_tx_desc_s *tx_desc,
  3657. struct hal_tx_completion_status *ts,
  3658. uint8_t ring_id)
  3659. {
  3660. }
  3661. #endif
  3662. #ifdef WLAN_PEER_JITTER
  3663. /*
  3664. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3665. * @curr_delay: Current delay
  3666. * @prev_Delay: Previous delay
  3667. * @avg_jitter: Average Jitter
  3668. * Return: Newly Computed Average Jitter
  3669. */
  3670. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3671. uint32_t prev_delay,
  3672. uint32_t avg_jitter)
  3673. {
  3674. uint32_t curr_jitter;
  3675. int32_t jitter_diff;
  3676. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3677. if (!avg_jitter)
  3678. return curr_jitter;
  3679. jitter_diff = curr_jitter - avg_jitter;
  3680. if (jitter_diff < 0)
  3681. avg_jitter = avg_jitter -
  3682. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3683. else
  3684. avg_jitter = avg_jitter +
  3685. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3686. return avg_jitter;
  3687. }
  3688. /*
  3689. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3690. * @curr_delay: Current delay
  3691. * @avg_Delay: Average delay
  3692. * Return: Newly Computed Average Delay
  3693. */
  3694. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3695. uint32_t avg_delay)
  3696. {
  3697. int32_t delay_diff;
  3698. if (!avg_delay)
  3699. return curr_delay;
  3700. delay_diff = curr_delay - avg_delay;
  3701. if (delay_diff < 0)
  3702. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3703. DP_AVG_DELAY_WEIGHT_DENOM);
  3704. else
  3705. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3706. DP_AVG_DELAY_WEIGHT_DENOM);
  3707. return avg_delay;
  3708. }
  3709. #ifdef WLAN_CONFIG_TX_DELAY
  3710. /*
  3711. * dp_tx_compute_cur_delay() - get the current delay
  3712. * @soc: soc handle
  3713. * @vdev: vdev structure for data path state
  3714. * @ts: Tx completion status
  3715. * @curr_delay: current delay
  3716. * @tx_desc: tx descriptor
  3717. * Return: void
  3718. */
  3719. static
  3720. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3721. struct dp_vdev *vdev,
  3722. struct hal_tx_completion_status *ts,
  3723. uint32_t *curr_delay,
  3724. struct dp_tx_desc_s *tx_desc)
  3725. {
  3726. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3727. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3728. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3729. curr_delay);
  3730. return status;
  3731. }
  3732. #else
  3733. static
  3734. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3735. struct dp_vdev *vdev,
  3736. struct hal_tx_completion_status *ts,
  3737. uint32_t *curr_delay,
  3738. struct dp_tx_desc_s *tx_desc)
  3739. {
  3740. int64_t current_timestamp, timestamp_hw_enqueue;
  3741. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3742. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3743. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3744. return QDF_STATUS_SUCCESS;
  3745. }
  3746. #endif
  3747. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3748. * @jiiter - per tid per ring jitter stats
  3749. * @ts: Tx completion status
  3750. * @vdev - vdev structure for data path state
  3751. * @tx_desc - tx descriptor
  3752. * Return: void
  3753. */
  3754. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3755. struct hal_tx_completion_status *ts,
  3756. struct dp_vdev *vdev,
  3757. struct dp_tx_desc_s *tx_desc)
  3758. {
  3759. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3760. struct dp_soc *soc = vdev->pdev->soc;
  3761. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3762. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3763. jitter->tx_drop += 1;
  3764. return;
  3765. }
  3766. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3767. tx_desc);
  3768. if (QDF_IS_STATUS_SUCCESS(status)) {
  3769. avg_delay = jitter->tx_avg_delay;
  3770. avg_jitter = jitter->tx_avg_jitter;
  3771. prev_delay = jitter->tx_prev_delay;
  3772. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3773. prev_delay,
  3774. avg_jitter);
  3775. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3776. jitter->tx_avg_delay = avg_delay;
  3777. jitter->tx_avg_jitter = avg_jitter;
  3778. jitter->tx_prev_delay = curr_delay;
  3779. jitter->tx_total_success += 1;
  3780. } else if (status == QDF_STATUS_E_FAILURE) {
  3781. jitter->tx_avg_err += 1;
  3782. }
  3783. }
  3784. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3785. * @txrx_peer: DP peer context
  3786. * @tx_desc: Tx software descriptor
  3787. * @ts: Tx completion status
  3788. * @ring_id: Rx CPU context ID/CPU_ID
  3789. * Return: void
  3790. */
  3791. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3792. struct dp_tx_desc_s *tx_desc,
  3793. struct hal_tx_completion_status *ts,
  3794. uint8_t ring_id)
  3795. {
  3796. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3797. struct dp_soc *soc = pdev->soc;
  3798. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3799. uint8_t tid;
  3800. struct cdp_peer_tid_stats *rx_tid = NULL;
  3801. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3802. return;
  3803. tid = ts->tid;
  3804. jitter_stats = txrx_peer->jitter_stats;
  3805. qdf_assert_always(jitter_stats);
  3806. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3807. /*
  3808. * For non-TID packets use the TID 9
  3809. */
  3810. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3811. tid = CDP_MAX_DATA_TIDS - 1;
  3812. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3813. dp_tx_compute_tid_jitter(rx_tid,
  3814. ts, txrx_peer->vdev, tx_desc);
  3815. }
  3816. #else
  3817. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3818. struct dp_tx_desc_s *tx_desc,
  3819. struct hal_tx_completion_status *ts,
  3820. uint8_t ring_id)
  3821. {
  3822. }
  3823. #endif
  3824. #ifdef HW_TX_DELAY_STATS_ENABLE
  3825. /**
  3826. * dp_update_tx_delay_stats() - update the delay stats
  3827. * @vdev: vdev handle
  3828. * @delay: delay in ms or us based on the flag delay_in_us
  3829. * @tid: tid value
  3830. * @mode: type of tx delay mode
  3831. * @ring id: ring number
  3832. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3833. *
  3834. * Return: none
  3835. */
  3836. static inline
  3837. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3838. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3839. {
  3840. struct cdp_tid_tx_stats *tstats =
  3841. &vdev->stats.tid_tx_stats[ring_id][tid];
  3842. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3843. delay_in_us);
  3844. }
  3845. #else
  3846. static inline
  3847. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3848. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3849. {
  3850. struct cdp_tid_tx_stats *tstats =
  3851. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3852. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3853. delay_in_us);
  3854. }
  3855. #endif
  3856. /**
  3857. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3858. * to pass in correct fields
  3859. *
  3860. * @vdev: pdev handle
  3861. * @tx_desc: tx descriptor
  3862. * @tid: tid value
  3863. * @ring_id: TCL or WBM ring number for transmit path
  3864. * Return: none
  3865. */
  3866. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3867. uint8_t tid, uint8_t ring_id)
  3868. {
  3869. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3870. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3871. uint32_t fwhw_transmit_delay_us;
  3872. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3873. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3874. return;
  3875. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3876. fwhw_transmit_delay_us =
  3877. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3878. qdf_ktime_to_us(tx_desc->timestamp);
  3879. /*
  3880. * Delay between packet enqueued to HW and Tx completion in us
  3881. */
  3882. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3883. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3884. ring_id, true);
  3885. /*
  3886. * For MCL, only enqueue to completion delay is required
  3887. * so return if the vdev flag is enabled.
  3888. */
  3889. return;
  3890. }
  3891. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3892. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3893. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3894. timestamp_hw_enqueue);
  3895. /*
  3896. * Delay between packet enqueued to HW and Tx completion in ms
  3897. */
  3898. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3899. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3900. false);
  3901. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3902. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3903. interframe_delay = (uint32_t)(timestamp_ingress -
  3904. vdev->prev_tx_enq_tstamp);
  3905. /*
  3906. * Delay in software enqueue
  3907. */
  3908. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3909. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3910. false);
  3911. /*
  3912. * Update interframe delay stats calculated at hardstart receive point.
  3913. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3914. * interframe delay will not be calculate correctly for 1st frame.
  3915. * On the other side, this will help in avoiding extra per packet check
  3916. * of !vdev->prev_tx_enq_tstamp.
  3917. */
  3918. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3919. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3920. false);
  3921. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3922. }
  3923. #ifdef DISABLE_DP_STATS
  3924. static
  3925. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3926. struct dp_txrx_peer *txrx_peer)
  3927. {
  3928. }
  3929. #else
  3930. static inline void
  3931. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3932. {
  3933. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3934. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3935. if (subtype != QDF_PROTO_INVALID)
  3936. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3937. 1);
  3938. }
  3939. #endif
  3940. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3941. #ifdef DP_PEER_EXTENDED_API
  3942. static inline uint8_t
  3943. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3944. {
  3945. return txrx_peer->mpdu_retry_threshold;
  3946. }
  3947. #else
  3948. static inline uint8_t
  3949. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3950. {
  3951. return 0;
  3952. }
  3953. #endif
  3954. /**
  3955. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3956. *
  3957. * @ts: Tx compltion status
  3958. * @txrx_peer: datapath txrx_peer handle
  3959. *
  3960. * Return: void
  3961. */
  3962. static inline void
  3963. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3964. struct dp_txrx_peer *txrx_peer)
  3965. {
  3966. uint8_t mcs, pkt_type, dst_mcs_idx;
  3967. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3968. mcs = ts->mcs;
  3969. pkt_type = ts->pkt_type;
  3970. /* do HW to SW pkt type conversion */
  3971. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3972. hal_2_dp_pkt_type_map[pkt_type]);
  3973. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3974. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3975. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3976. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3977. 1);
  3978. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3979. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3980. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3981. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3982. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3983. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3984. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3985. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3986. if (ts->first_msdu) {
  3987. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3988. ts->transmit_cnt > 1);
  3989. if (!retry_threshold)
  3990. return;
  3991. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3992. qdf_do_div(ts->transmit_cnt,
  3993. retry_threshold),
  3994. ts->transmit_cnt > retry_threshold);
  3995. }
  3996. }
  3997. #else
  3998. static inline void
  3999. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4000. struct dp_txrx_peer *txrx_peer)
  4001. {
  4002. }
  4003. #endif
  4004. /**
  4005. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4006. * per wbm ring
  4007. *
  4008. * @tx_desc: software descriptor head pointer
  4009. * @ts: Tx completion status
  4010. * @peer: peer handle
  4011. * @ring_id: ring number
  4012. *
  4013. * Return: None
  4014. */
  4015. static inline void
  4016. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4017. struct hal_tx_completion_status *ts,
  4018. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  4019. {
  4020. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4021. uint8_t tid = ts->tid;
  4022. uint32_t length;
  4023. struct cdp_tid_tx_stats *tid_stats;
  4024. if (!pdev)
  4025. return;
  4026. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4027. tid = CDP_MAX_DATA_TIDS - 1;
  4028. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4029. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4030. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4031. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4032. return;
  4033. }
  4034. length = qdf_nbuf_len(tx_desc->nbuf);
  4035. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4036. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4037. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4038. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4039. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4040. tid_stats->tqm_status_cnt[ts->status]++;
  4041. }
  4042. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4043. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4044. ts->transmit_cnt > 1);
  4045. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4046. 1, ts->transmit_cnt > 2);
  4047. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4048. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4049. ts->msdu_part_of_amsdu);
  4050. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4051. !ts->msdu_part_of_amsdu);
  4052. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4053. qdf_system_ticks();
  4054. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4055. return;
  4056. }
  4057. /*
  4058. * tx_failed is ideally supposed to be updated from HTT ppdu
  4059. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4060. * hw limitation there are no completions for failed cases.
  4061. * Hence updating tx_failed from data path. Please note that
  4062. * if tx_failed is fixed to be from ppdu, then this has to be
  4063. * removed
  4064. */
  4065. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4066. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4067. ts->transmit_cnt > DP_RETRY_COUNT);
  4068. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4069. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4070. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4071. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4072. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4073. length);
  4074. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4075. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4076. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4077. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4078. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4079. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4080. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4081. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4082. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4083. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4084. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4085. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4086. tx.dropped.fw_rem_queue_disable, 1);
  4087. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4088. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4089. tx.dropped.fw_rem_no_match, 1);
  4090. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4091. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4092. tx.dropped.drop_threshold, 1);
  4093. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4094. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4095. tx.dropped.drop_link_desc_na, 1);
  4096. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4097. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4098. tx.dropped.invalid_drop, 1);
  4099. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4100. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4101. tx.dropped.mcast_vdev_drop, 1);
  4102. } else {
  4103. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4104. }
  4105. }
  4106. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4107. /**
  4108. * dp_tx_flow_pool_lock() - take flow pool lock
  4109. * @soc: core txrx main context
  4110. * @tx_desc: tx desc
  4111. *
  4112. * Return: None
  4113. */
  4114. static inline
  4115. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4116. struct dp_tx_desc_s *tx_desc)
  4117. {
  4118. struct dp_tx_desc_pool_s *pool;
  4119. uint8_t desc_pool_id;
  4120. desc_pool_id = tx_desc->pool_id;
  4121. pool = &soc->tx_desc[desc_pool_id];
  4122. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4123. }
  4124. /**
  4125. * dp_tx_flow_pool_unlock() - release flow pool lock
  4126. * @soc: core txrx main context
  4127. * @tx_desc: tx desc
  4128. *
  4129. * Return: None
  4130. */
  4131. static inline
  4132. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4133. struct dp_tx_desc_s *tx_desc)
  4134. {
  4135. struct dp_tx_desc_pool_s *pool;
  4136. uint8_t desc_pool_id;
  4137. desc_pool_id = tx_desc->pool_id;
  4138. pool = &soc->tx_desc[desc_pool_id];
  4139. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4140. }
  4141. #else
  4142. static inline
  4143. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4144. {
  4145. }
  4146. static inline
  4147. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4148. {
  4149. }
  4150. #endif
  4151. /**
  4152. * dp_tx_notify_completion() - Notify tx completion for this desc
  4153. * @soc: core txrx main context
  4154. * @vdev: datapath vdev handle
  4155. * @tx_desc: tx desc
  4156. * @netbuf: buffer
  4157. * @status: tx status
  4158. *
  4159. * Return: none
  4160. */
  4161. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4162. struct dp_vdev *vdev,
  4163. struct dp_tx_desc_s *tx_desc,
  4164. qdf_nbuf_t netbuf,
  4165. uint8_t status)
  4166. {
  4167. void *osif_dev;
  4168. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4169. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4170. qdf_assert(tx_desc);
  4171. if (!vdev ||
  4172. !vdev->osif_vdev) {
  4173. return;
  4174. }
  4175. osif_dev = vdev->osif_vdev;
  4176. tx_compl_cbk = vdev->tx_comp;
  4177. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4178. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4179. if (tx_compl_cbk)
  4180. tx_compl_cbk(netbuf, osif_dev, flag);
  4181. }
  4182. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4183. * @pdev: pdev handle
  4184. * @tid: tid value
  4185. * @txdesc_ts: timestamp from txdesc
  4186. * @ppdu_id: ppdu id
  4187. *
  4188. * Return: none
  4189. */
  4190. #ifdef FEATURE_PERPKT_INFO
  4191. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4192. struct dp_txrx_peer *txrx_peer,
  4193. uint8_t tid,
  4194. uint64_t txdesc_ts,
  4195. uint32_t ppdu_id)
  4196. {
  4197. uint64_t delta_ms;
  4198. struct cdp_tx_sojourn_stats *sojourn_stats;
  4199. struct dp_peer *primary_link_peer = NULL;
  4200. struct dp_soc *link_peer_soc = NULL;
  4201. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4202. return;
  4203. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4204. tid >= CDP_DATA_TID_MAX))
  4205. return;
  4206. if (qdf_unlikely(!pdev->sojourn_buf))
  4207. return;
  4208. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4209. txrx_peer->peer_id,
  4210. DP_MOD_ID_TX_COMP);
  4211. if (qdf_unlikely(!primary_link_peer))
  4212. return;
  4213. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4214. qdf_nbuf_data(pdev->sojourn_buf);
  4215. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4216. sojourn_stats->cookie = (void *)
  4217. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4218. primary_link_peer);
  4219. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4220. txdesc_ts;
  4221. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4222. delta_ms);
  4223. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4224. sojourn_stats->num_msdus[tid] = 1;
  4225. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4226. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4227. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4228. pdev->sojourn_buf, HTT_INVALID_PEER,
  4229. WDI_NO_VAL, pdev->pdev_id);
  4230. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4231. sojourn_stats->num_msdus[tid] = 0;
  4232. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4233. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4234. }
  4235. #else
  4236. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4237. struct dp_txrx_peer *txrx_peer,
  4238. uint8_t tid,
  4239. uint64_t txdesc_ts,
  4240. uint32_t ppdu_id)
  4241. {
  4242. }
  4243. #endif
  4244. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4245. /**
  4246. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4247. * @soc: dp_soc handle
  4248. * @desc: Tx Descriptor
  4249. * @ts: HAL Tx completion descriptor contents
  4250. *
  4251. * This function is used to send tx completion to packet capture
  4252. */
  4253. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4254. struct dp_tx_desc_s *desc,
  4255. struct hal_tx_completion_status *ts)
  4256. {
  4257. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4258. desc, ts->peer_id,
  4259. WDI_NO_VAL, desc->pdev->pdev_id);
  4260. }
  4261. #endif
  4262. /**
  4263. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4264. * @soc: DP Soc handle
  4265. * @tx_desc: software Tx descriptor
  4266. * @ts : Tx completion status from HAL/HTT descriptor
  4267. *
  4268. * Return: none
  4269. */
  4270. void
  4271. dp_tx_comp_process_desc(struct dp_soc *soc,
  4272. struct dp_tx_desc_s *desc,
  4273. struct hal_tx_completion_status *ts,
  4274. struct dp_txrx_peer *txrx_peer)
  4275. {
  4276. uint64_t time_latency = 0;
  4277. uint16_t peer_id = DP_INVALID_PEER_ID;
  4278. /*
  4279. * m_copy/tx_capture modes are not supported for
  4280. * scatter gather packets
  4281. */
  4282. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4283. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4284. qdf_ktime_to_ms(desc->timestamp));
  4285. }
  4286. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4287. if (dp_tx_pkt_tracepoints_enabled())
  4288. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4289. desc->msdu_ext_desc ?
  4290. desc->msdu_ext_desc->tso_desc : NULL,
  4291. qdf_ktime_to_ms(desc->timestamp));
  4292. if (!(desc->msdu_ext_desc)) {
  4293. dp_tx_enh_unmap(soc, desc);
  4294. if (txrx_peer)
  4295. peer_id = txrx_peer->peer_id;
  4296. if (QDF_STATUS_SUCCESS ==
  4297. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4298. return;
  4299. }
  4300. if (QDF_STATUS_SUCCESS ==
  4301. dp_get_completion_indication_for_stack(soc,
  4302. desc->pdev,
  4303. txrx_peer, ts,
  4304. desc->nbuf,
  4305. time_latency)) {
  4306. dp_send_completion_to_stack(soc,
  4307. desc->pdev,
  4308. ts->peer_id,
  4309. ts->ppdu_id,
  4310. desc->nbuf);
  4311. return;
  4312. }
  4313. }
  4314. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4315. dp_tx_comp_free_buf(soc, desc, false);
  4316. }
  4317. #ifdef DISABLE_DP_STATS
  4318. /**
  4319. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4320. * @soc: core txrx main context
  4321. * @tx_desc: tx desc
  4322. * @status: tx status
  4323. *
  4324. * Return: none
  4325. */
  4326. static inline
  4327. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4328. struct dp_vdev *vdev,
  4329. struct dp_tx_desc_s *tx_desc,
  4330. uint8_t status)
  4331. {
  4332. }
  4333. #else
  4334. static inline
  4335. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4336. struct dp_vdev *vdev,
  4337. struct dp_tx_desc_s *tx_desc,
  4338. uint8_t status)
  4339. {
  4340. void *osif_dev;
  4341. ol_txrx_stats_rx_fp stats_cbk;
  4342. uint8_t pkt_type;
  4343. qdf_assert(tx_desc);
  4344. if (!vdev ||
  4345. !vdev->osif_vdev ||
  4346. !vdev->stats_cb)
  4347. return;
  4348. osif_dev = vdev->osif_vdev;
  4349. stats_cbk = vdev->stats_cb;
  4350. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4351. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4352. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4353. &pkt_type);
  4354. }
  4355. #endif
  4356. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4357. QDF_STATUS
  4358. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4359. uint32_t delta_tsf,
  4360. uint32_t *delay_us)
  4361. {
  4362. uint32_t buffer_ts;
  4363. uint32_t delay;
  4364. if (!delay_us)
  4365. return QDF_STATUS_E_INVAL;
  4366. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4367. if (!ts->valid)
  4368. return QDF_STATUS_E_INVAL;
  4369. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4370. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4371. * valid up to 29 bits.
  4372. */
  4373. buffer_ts = ts->buffer_timestamp << 10;
  4374. delay = ts->tsf - buffer_ts - delta_tsf;
  4375. if (qdf_unlikely(delay & 0x80000000)) {
  4376. dp_err_rl("delay = 0x%x (-ve)\n"
  4377. "release_src = %d\n"
  4378. "ppdu_id = 0x%x\n"
  4379. "peer_id = 0x%x\n"
  4380. "tid = 0x%x\n"
  4381. "release_reason = %d\n"
  4382. "tsf = %u (0x%x)\n"
  4383. "buffer_timestamp = %u (0x%x)\n"
  4384. "delta_tsf = %u (0x%x)\n",
  4385. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4386. ts->tid, ts->status, ts->tsf, ts->tsf,
  4387. ts->buffer_timestamp, ts->buffer_timestamp,
  4388. delta_tsf, delta_tsf);
  4389. delay = 0;
  4390. goto end;
  4391. }
  4392. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4393. if (delay > 0x1000000) {
  4394. dp_info_rl("----------------------\n"
  4395. "Tx completion status:\n"
  4396. "----------------------\n"
  4397. "release_src = %d\n"
  4398. "ppdu_id = 0x%x\n"
  4399. "release_reason = %d\n"
  4400. "tsf = %u (0x%x)\n"
  4401. "buffer_timestamp = %u (0x%x)\n"
  4402. "delta_tsf = %u (0x%x)\n",
  4403. ts->release_src, ts->ppdu_id, ts->status,
  4404. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4405. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4406. return QDF_STATUS_E_FAILURE;
  4407. }
  4408. end:
  4409. *delay_us = delay;
  4410. return QDF_STATUS_SUCCESS;
  4411. }
  4412. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4413. uint32_t delta_tsf)
  4414. {
  4415. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4416. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4417. DP_MOD_ID_CDP);
  4418. if (!vdev) {
  4419. dp_err_rl("vdev %d does not exist", vdev_id);
  4420. return;
  4421. }
  4422. vdev->delta_tsf = delta_tsf;
  4423. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4424. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4425. }
  4426. #endif
  4427. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4428. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4429. uint8_t vdev_id, bool enable)
  4430. {
  4431. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4432. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4433. DP_MOD_ID_CDP);
  4434. if (!vdev) {
  4435. dp_err_rl("vdev %d does not exist", vdev_id);
  4436. return QDF_STATUS_E_FAILURE;
  4437. }
  4438. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4439. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4440. return QDF_STATUS_SUCCESS;
  4441. }
  4442. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4443. uint32_t *val)
  4444. {
  4445. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4446. struct dp_vdev *vdev;
  4447. uint32_t delay_accum;
  4448. uint32_t pkts_accum;
  4449. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4450. if (!vdev) {
  4451. dp_err_rl("vdev %d does not exist", vdev_id);
  4452. return QDF_STATUS_E_FAILURE;
  4453. }
  4454. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4455. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4456. return QDF_STATUS_E_FAILURE;
  4457. }
  4458. /* Average uplink delay based on current accumulated values */
  4459. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4460. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4461. *val = delay_accum / pkts_accum;
  4462. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4463. delay_accum, pkts_accum);
  4464. /* Reset accumulated values to 0 */
  4465. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4466. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4467. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4468. return QDF_STATUS_SUCCESS;
  4469. }
  4470. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4471. struct hal_tx_completion_status *ts)
  4472. {
  4473. uint32_t ul_delay;
  4474. if (qdf_unlikely(!vdev)) {
  4475. dp_info_rl("vdev is null or delete in progress");
  4476. return;
  4477. }
  4478. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4479. return;
  4480. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4481. vdev->delta_tsf,
  4482. &ul_delay)))
  4483. return;
  4484. ul_delay /= 1000; /* in unit of ms */
  4485. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4486. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4487. }
  4488. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4489. static inline
  4490. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4491. struct hal_tx_completion_status *ts)
  4492. {
  4493. }
  4494. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4495. /**
  4496. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4497. * @soc: DP soc handle
  4498. * @tx_desc: software descriptor head pointer
  4499. * @ts: Tx completion status
  4500. * @txrx_peer: txrx peer handle
  4501. * @ring_id: ring number
  4502. *
  4503. * Return: none
  4504. */
  4505. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4506. struct dp_tx_desc_s *tx_desc,
  4507. struct hal_tx_completion_status *ts,
  4508. struct dp_txrx_peer *txrx_peer,
  4509. uint8_t ring_id)
  4510. {
  4511. uint32_t length;
  4512. qdf_ether_header_t *eh;
  4513. struct dp_vdev *vdev = NULL;
  4514. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4515. enum qdf_dp_tx_rx_status dp_status;
  4516. if (!nbuf) {
  4517. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4518. goto out;
  4519. }
  4520. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4521. length = qdf_nbuf_len(nbuf);
  4522. dp_status = dp_tx_hw_to_qdf(ts->status);
  4523. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4524. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4525. QDF_TRACE_DEFAULT_PDEV_ID,
  4526. qdf_nbuf_data_addr(nbuf),
  4527. sizeof(qdf_nbuf_data(nbuf)),
  4528. tx_desc->id, ts->status, dp_status));
  4529. dp_tx_comp_debug("-------------------- \n"
  4530. "Tx Completion Stats: \n"
  4531. "-------------------- \n"
  4532. "ack_frame_rssi = %d \n"
  4533. "first_msdu = %d \n"
  4534. "last_msdu = %d \n"
  4535. "msdu_part_of_amsdu = %d \n"
  4536. "rate_stats valid = %d \n"
  4537. "bw = %d \n"
  4538. "pkt_type = %d \n"
  4539. "stbc = %d \n"
  4540. "ldpc = %d \n"
  4541. "sgi = %d \n"
  4542. "mcs = %d \n"
  4543. "ofdma = %d \n"
  4544. "tones_in_ru = %d \n"
  4545. "tsf = %d \n"
  4546. "ppdu_id = %d \n"
  4547. "transmit_cnt = %d \n"
  4548. "tid = %d \n"
  4549. "peer_id = %d\n"
  4550. "tx_status = %d\n",
  4551. ts->ack_frame_rssi, ts->first_msdu,
  4552. ts->last_msdu, ts->msdu_part_of_amsdu,
  4553. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4554. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4555. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4556. ts->transmit_cnt, ts->tid, ts->peer_id,
  4557. ts->status);
  4558. /* Update SoC level stats */
  4559. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4560. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4561. if (!txrx_peer) {
  4562. dp_info_rl("peer is null or deletion in progress");
  4563. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4564. goto out;
  4565. }
  4566. vdev = txrx_peer->vdev;
  4567. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4568. dp_tx_update_uplink_delay(soc, vdev, ts);
  4569. /* check tx complete notification */
  4570. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4571. dp_tx_notify_completion(soc, vdev, tx_desc,
  4572. nbuf, ts->status);
  4573. /* Update per-packet stats for mesh mode */
  4574. if (qdf_unlikely(vdev->mesh_vdev) &&
  4575. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4576. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4577. /* Update peer level stats */
  4578. if (qdf_unlikely(txrx_peer->bss_peer &&
  4579. vdev->opmode == wlan_op_mode_ap)) {
  4580. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4581. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4582. length);
  4583. if (txrx_peer->vdev->tx_encap_type ==
  4584. htt_cmn_pkt_type_ethernet &&
  4585. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4586. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4587. tx.bcast, 1,
  4588. length);
  4589. }
  4590. }
  4591. } else {
  4592. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4593. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4594. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4595. 1, length);
  4596. if (qdf_unlikely(txrx_peer->in_twt)) {
  4597. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4598. tx.tx_success_twt,
  4599. 1, length);
  4600. }
  4601. }
  4602. }
  4603. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4604. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4605. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4606. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4607. ts, ts->tid);
  4608. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4609. #ifdef QCA_SUPPORT_RDK_STATS
  4610. if (soc->peerstats_enabled)
  4611. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4612. qdf_ktime_to_ms(tx_desc->timestamp),
  4613. ts->ppdu_id);
  4614. #endif
  4615. out:
  4616. return;
  4617. }
  4618. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4619. defined(QCA_ENHANCED_STATS_SUPPORT)
  4620. /*
  4621. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4622. * @txrx_peer: Datapath txrx_peer handle
  4623. * @length: Length of the packet
  4624. * @tx_status: Tx status from TQM/FW
  4625. * @update: enhanced flag value present in dp_pdev
  4626. *
  4627. * Return: none
  4628. */
  4629. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4630. uint32_t length, uint8_t tx_status,
  4631. bool update)
  4632. {
  4633. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4634. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4635. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4636. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4637. }
  4638. }
  4639. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4640. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4641. uint32_t length, uint8_t tx_status,
  4642. bool update)
  4643. {
  4644. if (!txrx_peer->hw_txrx_stats_en) {
  4645. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4646. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4647. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4648. }
  4649. }
  4650. #else
  4651. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4652. uint32_t length, uint8_t tx_status,
  4653. bool update)
  4654. {
  4655. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4656. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4657. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4658. }
  4659. #endif
  4660. /*
  4661. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4662. * @nbuf: skb buffer
  4663. *
  4664. * Return: none
  4665. */
  4666. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4667. static inline
  4668. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4669. {
  4670. qdf_nbuf_t nbuf = NULL;
  4671. if (next)
  4672. nbuf = next->nbuf;
  4673. if (nbuf) {
  4674. /* prefetch skb->next and first few bytes of skb->cb */
  4675. qdf_prefetch(next->shinfo_addr);
  4676. qdf_prefetch(nbuf);
  4677. /* prefetch skb fields present in different cachelines */
  4678. qdf_prefetch(&nbuf->len);
  4679. qdf_prefetch(&nbuf->users);
  4680. }
  4681. }
  4682. #else
  4683. static inline
  4684. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4685. {
  4686. }
  4687. #endif
  4688. /**
  4689. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4690. * @soc: core txrx main context
  4691. * @desc: software descriptor
  4692. *
  4693. * Return: true when packet is reinjected
  4694. */
  4695. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4696. defined(WLAN_MCAST_MLO)
  4697. static inline bool
  4698. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4699. {
  4700. struct dp_vdev *vdev = NULL;
  4701. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4702. if (!soc->arch_ops.dp_tx_mcast_handler)
  4703. return false;
  4704. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4705. DP_MOD_ID_REINJECT);
  4706. if (qdf_unlikely(!vdev)) {
  4707. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4708. desc->id);
  4709. return false;
  4710. }
  4711. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4712. qdf_nbuf_len(desc->nbuf));
  4713. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4714. dp_tx_desc_release(desc, desc->pool_id);
  4715. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4716. return true;
  4717. }
  4718. return false;
  4719. }
  4720. #else
  4721. static inline bool
  4722. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4723. {
  4724. return false;
  4725. }
  4726. #endif
  4727. /**
  4728. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4729. * @soc: core txrx main context
  4730. * @comp_head: software descriptor head pointer
  4731. * @ring_id: ring number
  4732. *
  4733. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4734. * and release the software descriptors after processing is complete
  4735. *
  4736. * Return: none
  4737. */
  4738. static void
  4739. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4740. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4741. {
  4742. struct dp_tx_desc_s *desc;
  4743. struct dp_tx_desc_s *next;
  4744. struct hal_tx_completion_status ts;
  4745. struct dp_txrx_peer *txrx_peer = NULL;
  4746. uint16_t peer_id = DP_INVALID_PEER;
  4747. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4748. desc = comp_head;
  4749. while (desc) {
  4750. next = desc->next;
  4751. dp_tx_prefetch_next_nbuf_data(next);
  4752. if (peer_id != desc->peer_id) {
  4753. if (txrx_peer)
  4754. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4755. DP_MOD_ID_TX_COMP);
  4756. peer_id = desc->peer_id;
  4757. txrx_peer =
  4758. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4759. &txrx_ref_handle,
  4760. DP_MOD_ID_TX_COMP);
  4761. }
  4762. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4763. desc = next;
  4764. continue;
  4765. }
  4766. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4767. if (qdf_likely(txrx_peer))
  4768. dp_tx_update_peer_basic_stats(txrx_peer,
  4769. desc->length,
  4770. desc->tx_status,
  4771. false);
  4772. qdf_nbuf_free(desc->nbuf);
  4773. dp_ppeds_tx_desc_free(soc, desc);
  4774. desc = next;
  4775. continue;
  4776. }
  4777. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4778. struct dp_pdev *pdev = desc->pdev;
  4779. if (qdf_likely(txrx_peer))
  4780. dp_tx_update_peer_basic_stats(txrx_peer,
  4781. desc->length,
  4782. desc->tx_status,
  4783. false);
  4784. qdf_assert(pdev);
  4785. dp_tx_outstanding_dec(pdev);
  4786. /*
  4787. * Calling a QDF WRAPPER here is creating significant
  4788. * performance impact so avoided the wrapper call here
  4789. */
  4790. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4791. desc->id, DP_TX_COMP_UNMAP);
  4792. dp_tx_nbuf_unmap(soc, desc);
  4793. qdf_nbuf_free_simple(desc->nbuf);
  4794. dp_tx_desc_free(soc, desc, desc->pool_id);
  4795. desc = next;
  4796. continue;
  4797. }
  4798. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4799. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4800. ring_id);
  4801. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4802. dp_tx_desc_release(desc, desc->pool_id);
  4803. desc = next;
  4804. }
  4805. if (txrx_peer)
  4806. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4807. }
  4808. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4809. static inline
  4810. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4811. int max_reap_limit)
  4812. {
  4813. bool limit_hit = false;
  4814. limit_hit =
  4815. (num_reaped >= max_reap_limit) ? true : false;
  4816. if (limit_hit)
  4817. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4818. return limit_hit;
  4819. }
  4820. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4821. {
  4822. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4823. }
  4824. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4825. {
  4826. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4827. return cfg->tx_comp_loop_pkt_limit;
  4828. }
  4829. #else
  4830. static inline
  4831. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4832. int max_reap_limit)
  4833. {
  4834. return false;
  4835. }
  4836. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4837. {
  4838. return false;
  4839. }
  4840. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4841. {
  4842. return 0;
  4843. }
  4844. #endif
  4845. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4846. static inline int
  4847. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4848. int *max_reap_limit)
  4849. {
  4850. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4851. max_reap_limit);
  4852. }
  4853. #else
  4854. static inline int
  4855. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4856. int *max_reap_limit)
  4857. {
  4858. return 0;
  4859. }
  4860. #endif
  4861. #ifdef DP_TX_TRACKING
  4862. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4863. {
  4864. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4865. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4866. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4867. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4868. }
  4869. }
  4870. #endif
  4871. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4872. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4873. uint32_t quota)
  4874. {
  4875. void *tx_comp_hal_desc;
  4876. void *last_prefetched_hw_desc = NULL;
  4877. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4878. hal_soc_handle_t hal_soc;
  4879. uint8_t buffer_src;
  4880. struct dp_tx_desc_s *tx_desc = NULL;
  4881. struct dp_tx_desc_s *head_desc = NULL;
  4882. struct dp_tx_desc_s *tail_desc = NULL;
  4883. uint32_t num_processed = 0;
  4884. uint32_t count;
  4885. uint32_t num_avail_for_reap = 0;
  4886. bool force_break = false;
  4887. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4888. int max_reap_limit, ring_near_full;
  4889. DP_HIST_INIT();
  4890. more_data:
  4891. hal_soc = soc->hal_soc;
  4892. /* Re-initialize local variables to be re-used */
  4893. head_desc = NULL;
  4894. tail_desc = NULL;
  4895. count = 0;
  4896. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4897. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4898. &max_reap_limit);
  4899. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4900. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4901. return 0;
  4902. }
  4903. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4904. if (num_avail_for_reap >= quota)
  4905. num_avail_for_reap = quota;
  4906. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4907. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  4908. hal_ring_hdl,
  4909. num_avail_for_reap);
  4910. /* Find head descriptor from completion ring */
  4911. while (qdf_likely(num_avail_for_reap--)) {
  4912. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4913. if (qdf_unlikely(!tx_comp_hal_desc))
  4914. break;
  4915. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4916. tx_comp_hal_desc);
  4917. /* If this buffer was not released by TQM or FW, then it is not
  4918. * Tx completion indication, assert */
  4919. if (qdf_unlikely(buffer_src !=
  4920. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4921. (qdf_unlikely(buffer_src !=
  4922. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4923. uint8_t wbm_internal_error;
  4924. dp_err_rl(
  4925. "Tx comp release_src != TQM | FW but from %d",
  4926. buffer_src);
  4927. hal_dump_comp_desc(tx_comp_hal_desc);
  4928. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4929. /* When WBM sees NULL buffer_addr_info in any of
  4930. * ingress rings it sends an error indication,
  4931. * with wbm_internal_error=1, to a specific ring.
  4932. * The WBM2SW ring used to indicate these errors is
  4933. * fixed in HW, and that ring is being used as Tx
  4934. * completion ring. These errors are not related to
  4935. * Tx completions, and should just be ignored
  4936. */
  4937. wbm_internal_error = hal_get_wbm_internal_error(
  4938. hal_soc,
  4939. tx_comp_hal_desc);
  4940. if (wbm_internal_error) {
  4941. dp_err_rl("Tx comp wbm_internal_error!!");
  4942. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4943. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4944. buffer_src)
  4945. dp_handle_wbm_internal_error(
  4946. soc,
  4947. tx_comp_hal_desc,
  4948. hal_tx_comp_get_buffer_type(
  4949. tx_comp_hal_desc));
  4950. } else {
  4951. dp_err_rl("Tx comp wbm_internal_error false");
  4952. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4953. }
  4954. continue;
  4955. }
  4956. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4957. tx_comp_hal_desc,
  4958. &tx_desc);
  4959. if (!tx_desc) {
  4960. dp_err("unable to retrieve tx_desc!");
  4961. QDF_BUG(0);
  4962. continue;
  4963. }
  4964. tx_desc->buffer_src = buffer_src;
  4965. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  4966. goto add_to_pool2;
  4967. /*
  4968. * If the release source is FW, process the HTT status
  4969. */
  4970. if (qdf_unlikely(buffer_src ==
  4971. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4972. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4973. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4974. htt_tx_status);
  4975. /* Collect hw completion contents */
  4976. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4977. &tx_desc->comp, 1);
  4978. soc->arch_ops.dp_tx_process_htt_completion(
  4979. soc,
  4980. tx_desc,
  4981. htt_tx_status,
  4982. ring_id);
  4983. } else {
  4984. tx_desc->tx_status =
  4985. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4986. tx_desc->buffer_src = buffer_src;
  4987. /*
  4988. * If the fast completion mode is enabled extended
  4989. * metadata from descriptor is not copied
  4990. */
  4991. if (qdf_likely(tx_desc->flags &
  4992. DP_TX_DESC_FLAG_SIMPLE))
  4993. goto add_to_pool;
  4994. /*
  4995. * If the descriptor is already freed in vdev_detach,
  4996. * continue to next descriptor
  4997. */
  4998. if (qdf_unlikely
  4999. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5000. !tx_desc->flags)) {
  5001. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5002. tx_desc->id);
  5003. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5004. dp_tx_desc_check_corruption(tx_desc);
  5005. continue;
  5006. }
  5007. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5008. dp_tx_comp_info_rl("pdev in down state %d",
  5009. tx_desc->id);
  5010. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5011. dp_tx_comp_free_buf(soc, tx_desc, false);
  5012. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5013. goto next_desc;
  5014. }
  5015. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5016. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5017. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5018. tx_desc->flags, tx_desc->id);
  5019. qdf_assert_always(0);
  5020. }
  5021. /* Collect hw completion contents */
  5022. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5023. &tx_desc->comp, 1);
  5024. add_to_pool:
  5025. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5026. add_to_pool2:
  5027. /* First ring descriptor on the cycle */
  5028. if (!head_desc) {
  5029. head_desc = tx_desc;
  5030. tail_desc = tx_desc;
  5031. }
  5032. tail_desc->next = tx_desc;
  5033. tx_desc->next = NULL;
  5034. tail_desc = tx_desc;
  5035. }
  5036. next_desc:
  5037. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5038. /*
  5039. * Processed packet count is more than given quota
  5040. * stop to processing
  5041. */
  5042. count++;
  5043. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5044. num_avail_for_reap,
  5045. hal_ring_hdl,
  5046. &last_prefetched_hw_desc,
  5047. &last_prefetched_sw_desc);
  5048. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5049. break;
  5050. }
  5051. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5052. /* Process the reaped descriptors */
  5053. if (head_desc)
  5054. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5055. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5056. /*
  5057. * If we are processing in near-full condition, there are 3 scenario
  5058. * 1) Ring entries has reached critical state
  5059. * 2) Ring entries are still near high threshold
  5060. * 3) Ring entries are below the safe level
  5061. *
  5062. * One more loop will move the state to normal processing and yield
  5063. */
  5064. if (ring_near_full)
  5065. goto more_data;
  5066. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5067. if (num_processed >= quota)
  5068. force_break = true;
  5069. if (!force_break &&
  5070. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5071. hal_ring_hdl)) {
  5072. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5073. if (!hif_exec_should_yield(soc->hif_handle,
  5074. int_ctx->dp_intr_id))
  5075. goto more_data;
  5076. }
  5077. }
  5078. DP_TX_HIST_STATS_PER_PDEV();
  5079. return num_processed;
  5080. }
  5081. #ifdef FEATURE_WLAN_TDLS
  5082. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5083. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5084. {
  5085. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5086. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5087. DP_MOD_ID_TDLS);
  5088. if (!vdev) {
  5089. dp_err("vdev handle for id %d is NULL", vdev_id);
  5090. return NULL;
  5091. }
  5092. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5093. vdev->is_tdls_frame = true;
  5094. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5095. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5096. }
  5097. #endif
  5098. /**
  5099. * dp_tx_vdev_attach() - attach vdev to dp tx
  5100. * @vdev: virtual device instance
  5101. *
  5102. * Return: QDF_STATUS_SUCCESS: success
  5103. * QDF_STATUS_E_RESOURCES: Error return
  5104. */
  5105. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5106. {
  5107. int pdev_id;
  5108. /*
  5109. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5110. */
  5111. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5112. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5113. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5114. vdev->vdev_id);
  5115. pdev_id =
  5116. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5117. vdev->pdev->pdev_id);
  5118. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5119. /*
  5120. * Set HTT Extension Valid bit to 0 by default
  5121. */
  5122. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5123. dp_tx_vdev_update_search_flags(vdev);
  5124. return QDF_STATUS_SUCCESS;
  5125. }
  5126. #ifndef FEATURE_WDS
  5127. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5128. {
  5129. return false;
  5130. }
  5131. #endif
  5132. /**
  5133. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5134. * @vdev: virtual device instance
  5135. *
  5136. * Return: void
  5137. *
  5138. */
  5139. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5140. {
  5141. struct dp_soc *soc = vdev->pdev->soc;
  5142. /*
  5143. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5144. * for TDLS link
  5145. *
  5146. * Enable AddrY (SA based search) only for non-WDS STA and
  5147. * ProxySTA VAP (in HKv1) modes.
  5148. *
  5149. * In all other VAP modes, only DA based search should be
  5150. * enabled
  5151. */
  5152. if (vdev->opmode == wlan_op_mode_sta &&
  5153. vdev->tdls_link_connected)
  5154. vdev->hal_desc_addr_search_flags =
  5155. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5156. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5157. !dp_tx_da_search_override(vdev))
  5158. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5159. else
  5160. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5161. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5162. vdev->search_type = soc->sta_mode_search_policy;
  5163. else
  5164. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5165. }
  5166. static inline bool
  5167. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5168. struct dp_vdev *vdev,
  5169. struct dp_tx_desc_s *tx_desc)
  5170. {
  5171. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5172. return false;
  5173. /*
  5174. * if vdev is given, then only check whether desc
  5175. * vdev match. if vdev is NULL, then check whether
  5176. * desc pdev match.
  5177. */
  5178. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5179. (tx_desc->pdev == pdev);
  5180. }
  5181. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5182. /**
  5183. * dp_tx_desc_flush() - release resources associated
  5184. * to TX Desc
  5185. *
  5186. * @dp_pdev: Handle to DP pdev structure
  5187. * @vdev: virtual device instance
  5188. * NULL: no specific Vdev is required and check all allcated TX desc
  5189. * on this pdev.
  5190. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5191. *
  5192. * @force_free:
  5193. * true: flush the TX desc.
  5194. * false: only reset the Vdev in each allocated TX desc
  5195. * that associated to current Vdev.
  5196. *
  5197. * This function will go through the TX desc pool to flush
  5198. * the outstanding TX data or reset Vdev to NULL in associated TX
  5199. * Desc.
  5200. */
  5201. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5202. bool force_free)
  5203. {
  5204. uint8_t i;
  5205. uint32_t j;
  5206. uint32_t num_desc, page_id, offset;
  5207. uint16_t num_desc_per_page;
  5208. struct dp_soc *soc = pdev->soc;
  5209. struct dp_tx_desc_s *tx_desc = NULL;
  5210. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5211. if (!vdev && !force_free) {
  5212. dp_err("Reset TX desc vdev, Vdev param is required!");
  5213. return;
  5214. }
  5215. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5216. tx_desc_pool = &soc->tx_desc[i];
  5217. if (!(tx_desc_pool->pool_size) ||
  5218. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5219. !(tx_desc_pool->desc_pages.cacheable_pages))
  5220. continue;
  5221. /*
  5222. * Add flow pool lock protection in case pool is freed
  5223. * due to all tx_desc is recycled when handle TX completion.
  5224. * this is not necessary when do force flush as:
  5225. * a. double lock will happen if dp_tx_desc_release is
  5226. * also trying to acquire it.
  5227. * b. dp interrupt has been disabled before do force TX desc
  5228. * flush in dp_pdev_deinit().
  5229. */
  5230. if (!force_free)
  5231. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5232. num_desc = tx_desc_pool->pool_size;
  5233. num_desc_per_page =
  5234. tx_desc_pool->desc_pages.num_element_per_page;
  5235. for (j = 0; j < num_desc; j++) {
  5236. page_id = j / num_desc_per_page;
  5237. offset = j % num_desc_per_page;
  5238. if (qdf_unlikely(!(tx_desc_pool->
  5239. desc_pages.cacheable_pages)))
  5240. break;
  5241. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5242. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5243. /*
  5244. * Free TX desc if force free is
  5245. * required, otherwise only reset vdev
  5246. * in this TX desc.
  5247. */
  5248. if (force_free) {
  5249. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5250. dp_tx_comp_free_buf(soc, tx_desc,
  5251. false);
  5252. dp_tx_desc_release(tx_desc, i);
  5253. } else {
  5254. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5255. }
  5256. }
  5257. }
  5258. if (!force_free)
  5259. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5260. }
  5261. }
  5262. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5263. /**
  5264. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5265. *
  5266. * @soc: Handle to DP soc structure
  5267. * @tx_desc: pointer of one TX desc
  5268. * @desc_pool_id: TX Desc pool id
  5269. */
  5270. static inline void
  5271. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5272. uint8_t desc_pool_id)
  5273. {
  5274. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5275. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5276. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5277. }
  5278. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5279. bool force_free)
  5280. {
  5281. uint8_t i, num_pool;
  5282. uint32_t j;
  5283. uint32_t num_desc, page_id, offset;
  5284. uint16_t num_desc_per_page;
  5285. struct dp_soc *soc = pdev->soc;
  5286. struct dp_tx_desc_s *tx_desc = NULL;
  5287. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5288. if (!vdev && !force_free) {
  5289. dp_err("Reset TX desc vdev, Vdev param is required!");
  5290. return;
  5291. }
  5292. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5293. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5294. for (i = 0; i < num_pool; i++) {
  5295. tx_desc_pool = &soc->tx_desc[i];
  5296. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5297. continue;
  5298. num_desc_per_page =
  5299. tx_desc_pool->desc_pages.num_element_per_page;
  5300. for (j = 0; j < num_desc; j++) {
  5301. page_id = j / num_desc_per_page;
  5302. offset = j % num_desc_per_page;
  5303. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5304. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5305. if (force_free) {
  5306. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5307. dp_tx_comp_free_buf(soc, tx_desc,
  5308. false);
  5309. dp_tx_desc_release(tx_desc, i);
  5310. } else {
  5311. dp_tx_desc_reset_vdev(soc, tx_desc,
  5312. i);
  5313. }
  5314. }
  5315. }
  5316. }
  5317. }
  5318. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5319. /**
  5320. * dp_tx_vdev_detach() - detach vdev from dp tx
  5321. * @vdev: virtual device instance
  5322. *
  5323. * Return: QDF_STATUS_SUCCESS: success
  5324. * QDF_STATUS_E_RESOURCES: Error return
  5325. */
  5326. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5327. {
  5328. struct dp_pdev *pdev = vdev->pdev;
  5329. /* Reset TX desc associated to this Vdev as NULL */
  5330. dp_tx_desc_flush(pdev, vdev, false);
  5331. return QDF_STATUS_SUCCESS;
  5332. }
  5333. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5334. /* Pools will be allocated dynamically */
  5335. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5336. int num_desc)
  5337. {
  5338. uint8_t i;
  5339. for (i = 0; i < num_pool; i++) {
  5340. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5341. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5342. }
  5343. return QDF_STATUS_SUCCESS;
  5344. }
  5345. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5346. uint32_t num_desc)
  5347. {
  5348. return QDF_STATUS_SUCCESS;
  5349. }
  5350. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5351. {
  5352. }
  5353. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5354. {
  5355. uint8_t i;
  5356. for (i = 0; i < num_pool; i++)
  5357. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5358. }
  5359. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5360. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5361. uint32_t num_desc)
  5362. {
  5363. uint8_t i, count;
  5364. /* Allocate software Tx descriptor pools */
  5365. for (i = 0; i < num_pool; i++) {
  5366. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5367. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5368. FL("Tx Desc Pool alloc %d failed %pK"),
  5369. i, soc);
  5370. goto fail;
  5371. }
  5372. }
  5373. return QDF_STATUS_SUCCESS;
  5374. fail:
  5375. for (count = 0; count < i; count++)
  5376. dp_tx_desc_pool_free(soc, count);
  5377. return QDF_STATUS_E_NOMEM;
  5378. }
  5379. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5380. uint32_t num_desc)
  5381. {
  5382. uint8_t i;
  5383. for (i = 0; i < num_pool; i++) {
  5384. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5385. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5386. FL("Tx Desc Pool init %d failed %pK"),
  5387. i, soc);
  5388. return QDF_STATUS_E_NOMEM;
  5389. }
  5390. }
  5391. return QDF_STATUS_SUCCESS;
  5392. }
  5393. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5394. {
  5395. uint8_t i;
  5396. for (i = 0; i < num_pool; i++)
  5397. dp_tx_desc_pool_deinit(soc, i);
  5398. }
  5399. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5400. {
  5401. uint8_t i;
  5402. for (i = 0; i < num_pool; i++)
  5403. dp_tx_desc_pool_free(soc, i);
  5404. }
  5405. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5406. /**
  5407. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5408. * @soc: core txrx main context
  5409. * @num_pool: number of pools
  5410. *
  5411. */
  5412. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5413. {
  5414. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5415. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5416. }
  5417. /**
  5418. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5419. * @soc: core txrx main context
  5420. * @num_pool: number of pools
  5421. *
  5422. */
  5423. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5424. {
  5425. dp_tx_tso_desc_pool_free(soc, num_pool);
  5426. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5427. }
  5428. /**
  5429. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5430. * @soc: core txrx main context
  5431. *
  5432. * This function frees all tx related descriptors as below
  5433. * 1. Regular TX descriptors (static pools)
  5434. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5435. * 3. TSO descriptors
  5436. *
  5437. */
  5438. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5439. {
  5440. uint8_t num_pool;
  5441. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5442. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5443. dp_tx_ext_desc_pool_free(soc, num_pool);
  5444. dp_tx_delete_static_pools(soc, num_pool);
  5445. }
  5446. /**
  5447. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5448. * @soc: core txrx main context
  5449. *
  5450. * This function de-initializes all tx related descriptors as below
  5451. * 1. Regular TX descriptors (static pools)
  5452. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5453. * 3. TSO descriptors
  5454. *
  5455. */
  5456. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5457. {
  5458. uint8_t num_pool;
  5459. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5460. dp_tx_flow_control_deinit(soc);
  5461. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5462. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5463. dp_tx_deinit_static_pools(soc, num_pool);
  5464. }
  5465. /**
  5466. * dp_tso_attach() - TSO attach handler
  5467. * @txrx_soc: Opaque Dp handle
  5468. *
  5469. * Reserve TSO descriptor buffers
  5470. *
  5471. * Return: QDF_STATUS_E_FAILURE on failure or
  5472. * QDF_STATUS_SUCCESS on success
  5473. */
  5474. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5475. uint8_t num_pool,
  5476. uint32_t num_desc)
  5477. {
  5478. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5479. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5480. return QDF_STATUS_E_FAILURE;
  5481. }
  5482. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5483. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5484. num_pool, soc);
  5485. return QDF_STATUS_E_FAILURE;
  5486. }
  5487. return QDF_STATUS_SUCCESS;
  5488. }
  5489. /**
  5490. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5491. * @soc: DP soc handle
  5492. * @num_pool: Number of pools
  5493. * @num_desc: Number of descriptors
  5494. *
  5495. * Initialize TSO descriptor pools
  5496. *
  5497. * Return: QDF_STATUS_E_FAILURE on failure or
  5498. * QDF_STATUS_SUCCESS on success
  5499. */
  5500. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5501. uint8_t num_pool,
  5502. uint32_t num_desc)
  5503. {
  5504. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5505. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5506. return QDF_STATUS_E_FAILURE;
  5507. }
  5508. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5509. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5510. num_pool, soc);
  5511. return QDF_STATUS_E_FAILURE;
  5512. }
  5513. return QDF_STATUS_SUCCESS;
  5514. }
  5515. /**
  5516. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5517. * @soc: core txrx main context
  5518. *
  5519. * This function allocates memory for following descriptor pools
  5520. * 1. regular sw tx descriptor pools (static pools)
  5521. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5522. * 3. TSO descriptor pools
  5523. *
  5524. * Return: QDF_STATUS_SUCCESS: success
  5525. * QDF_STATUS_E_RESOURCES: Error return
  5526. */
  5527. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5528. {
  5529. uint8_t num_pool;
  5530. uint32_t num_desc;
  5531. uint32_t num_ext_desc;
  5532. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5533. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5534. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5535. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5536. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5537. __func__, num_pool, num_desc);
  5538. if ((num_pool > MAX_TXDESC_POOLS) ||
  5539. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5540. goto fail1;
  5541. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5542. goto fail1;
  5543. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5544. goto fail2;
  5545. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5546. return QDF_STATUS_SUCCESS;
  5547. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5548. goto fail3;
  5549. return QDF_STATUS_SUCCESS;
  5550. fail3:
  5551. dp_tx_ext_desc_pool_free(soc, num_pool);
  5552. fail2:
  5553. dp_tx_delete_static_pools(soc, num_pool);
  5554. fail1:
  5555. return QDF_STATUS_E_RESOURCES;
  5556. }
  5557. /**
  5558. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5559. * @soc: core txrx main context
  5560. *
  5561. * This function initializes the following TX descriptor pools
  5562. * 1. regular sw tx descriptor pools (static pools)
  5563. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5564. * 3. TSO descriptor pools
  5565. *
  5566. * Return: QDF_STATUS_SUCCESS: success
  5567. * QDF_STATUS_E_RESOURCES: Error return
  5568. */
  5569. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5570. {
  5571. uint8_t num_pool;
  5572. uint32_t num_desc;
  5573. uint32_t num_ext_desc;
  5574. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5575. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5576. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5577. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5578. goto fail1;
  5579. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5580. goto fail2;
  5581. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5582. return QDF_STATUS_SUCCESS;
  5583. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5584. goto fail3;
  5585. dp_tx_flow_control_init(soc);
  5586. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5587. return QDF_STATUS_SUCCESS;
  5588. fail3:
  5589. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5590. fail2:
  5591. dp_tx_deinit_static_pools(soc, num_pool);
  5592. fail1:
  5593. return QDF_STATUS_E_RESOURCES;
  5594. }
  5595. /**
  5596. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5597. * @txrx_soc: dp soc handle
  5598. *
  5599. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5600. * QDF_STATUS_E_FAILURE
  5601. */
  5602. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5603. {
  5604. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5605. uint8_t num_pool;
  5606. uint32_t num_desc;
  5607. uint32_t num_ext_desc;
  5608. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5609. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5610. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5611. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5612. return QDF_STATUS_E_FAILURE;
  5613. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5614. return QDF_STATUS_E_FAILURE;
  5615. return QDF_STATUS_SUCCESS;
  5616. }
  5617. /**
  5618. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5619. * @txrx_soc: dp soc handle
  5620. *
  5621. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5622. */
  5623. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5624. {
  5625. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5626. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5627. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5628. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5629. return QDF_STATUS_SUCCESS;
  5630. }
  5631. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5632. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5633. enum qdf_pkt_timestamp_index index, uint64_t time,
  5634. qdf_nbuf_t nbuf)
  5635. {
  5636. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5637. uint64_t tsf_time;
  5638. if (vdev->get_tsf_time) {
  5639. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5640. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5641. }
  5642. }
  5643. }
  5644. void dp_pkt_get_timestamp(uint64_t *time)
  5645. {
  5646. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5647. *time = qdf_get_log_timestamp();
  5648. }
  5649. #endif