dp_be.c 60 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. #ifdef WLAN_SUPPORT_PPEDS
  33. #include "be/dp_ppeds.h"
  34. #include <ppe_vp_public.h>
  35. #endif
  36. /* Generic AST entry aging timer value */
  37. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  38. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  39. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  40. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  41. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  42. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  43. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  44. #ifdef QCA_WIFI_KIWI_V2
  45. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  46. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  47. #else
  48. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  49. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  50. #endif
  51. };
  52. #else
  53. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  54. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  55. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  56. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  57. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  58. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  59. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  60. };
  61. #endif
  62. #ifdef WLAN_SUPPORT_PPEDS
  63. static struct cdp_ppe_txrx_ops dp_ops_ppe_be = {
  64. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  65. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  66. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  67. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  68. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  69. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  70. };
  71. static void dp_ppeds_rings_status(struct dp_soc *soc)
  72. {
  73. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  74. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  75. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  76. }
  77. #endif
  78. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  79. {
  80. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  81. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  82. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  83. /* this is used only when dmac mode is enabled */
  84. soc->num_rx_refill_buf_rings = 1;
  85. soc->wlan_cfg_ctx->notify_frame_support =
  86. DP_MARK_NOTIFY_FRAME_SUPPORT;
  87. }
  88. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  89. {
  90. switch (context_type) {
  91. case DP_CONTEXT_TYPE_SOC:
  92. return sizeof(struct dp_soc_be);
  93. case DP_CONTEXT_TYPE_PDEV:
  94. return sizeof(struct dp_pdev_be);
  95. case DP_CONTEXT_TYPE_VDEV:
  96. return sizeof(struct dp_vdev_be);
  97. case DP_CONTEXT_TYPE_PEER:
  98. return sizeof(struct dp_peer_be);
  99. default:
  100. return 0;
  101. }
  102. }
  103. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  104. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  105. /**
  106. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  107. per wbm2sw ring
  108. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  109. *
  110. * Return: None
  111. */
  112. static inline
  113. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  114. {
  115. cc_cfg->wbm2sw6_cc_en = 1;
  116. cc_cfg->wbm2sw5_cc_en = 1;
  117. cc_cfg->wbm2sw4_cc_en = 1;
  118. cc_cfg->wbm2sw3_cc_en = 1;
  119. cc_cfg->wbm2sw2_cc_en = 1;
  120. /* disable wbm2sw1 hw cc as it's for FW */
  121. cc_cfg->wbm2sw1_cc_en = 0;
  122. cc_cfg->wbm2sw0_cc_en = 1;
  123. cc_cfg->wbm2fw_cc_en = 0;
  124. }
  125. #else
  126. static inline
  127. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  128. {
  129. cc_cfg->wbm2sw6_cc_en = 1;
  130. cc_cfg->wbm2sw5_cc_en = 1;
  131. cc_cfg->wbm2sw4_cc_en = 1;
  132. cc_cfg->wbm2sw3_cc_en = 1;
  133. cc_cfg->wbm2sw2_cc_en = 1;
  134. cc_cfg->wbm2sw1_cc_en = 1;
  135. cc_cfg->wbm2sw0_cc_en = 1;
  136. cc_cfg->wbm2fw_cc_en = 0;
  137. }
  138. #endif
  139. #if defined(WLAN_SUPPORT_RX_FISA)
  140. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  141. {
  142. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  143. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  144. /* get CMEM for cookie conversion */
  145. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  146. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  147. return QDF_STATUS_E_NOMEM;
  148. }
  149. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  150. soc->fst_cmem_base = soc->cmem_base +
  151. (soc->cmem_total_size - soc->cmem_avail_size);
  152. soc->cmem_avail_size -= soc->fst_cmem_size;
  153. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  154. soc->fst_cmem_base, soc->fst_cmem_size);
  155. return QDF_STATUS_SUCCESS;
  156. }
  157. #else /* !WLAN_SUPPORT_RX_FISA */
  158. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  159. {
  160. return QDF_STATUS_SUCCESS;
  161. }
  162. #endif
  163. /**
  164. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  165. conversion register
  166. * @soc: SOC handle
  167. * @is_4k_align: page address 4k aligned
  168. *
  169. * Return: None
  170. */
  171. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  172. bool is_4k_align)
  173. {
  174. struct hal_hw_cc_config cc_cfg = { 0 };
  175. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  176. if (soc->cdp_soc.ol_ops->get_con_mode &&
  177. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  178. return;
  179. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  180. dp_info("INI skip HW CC register setting");
  181. return;
  182. }
  183. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  184. cc_cfg.cc_global_en = true;
  185. cc_cfg.page_4k_align = is_4k_align;
  186. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  187. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  188. /* 36th bit should be 1 then HW know this is CMEM address */
  189. cc_cfg.lut_base_addr_39_32 = 0x10;
  190. cc_cfg.error_path_cookie_conv_en = true;
  191. cc_cfg.release_path_cookie_conv_en = true;
  192. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  193. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  194. }
  195. /**
  196. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  197. * @hal_soc_hdl: HAL SOC handle
  198. * @offset: CMEM address
  199. * @value: value to write
  200. *
  201. * Return: None.
  202. */
  203. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  204. uint32_t offset,
  205. uint32_t value)
  206. {
  207. hal_cmem_write(hal_soc_hdl, offset, value);
  208. }
  209. /**
  210. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  211. HW cookie conversion
  212. * @soc: SOC handle
  213. * @cc_ctx: cookie conversion context pointer
  214. *
  215. * Return: 0 in case of success, else error value
  216. */
  217. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  218. {
  219. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  220. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  221. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  222. /* get CMEM for cookie conversion */
  223. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  224. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  225. return QDF_STATUS_E_RESOURCES;
  226. }
  227. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  228. DP_CC_MEM_OFFSET_IN_CMEM);
  229. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  230. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  231. be_soc->cc_cmem_base, soc->cmem_avail_size);
  232. return QDF_STATUS_SUCCESS;
  233. }
  234. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  235. uint8_t for_feature)
  236. {
  237. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  238. switch (for_feature) {
  239. case COOKIE_CONVERSION:
  240. status = dp_hw_cc_cmem_addr_init(soc);
  241. break;
  242. case FISA_FST:
  243. status = dp_fisa_fst_cmem_addr_init(soc);
  244. break;
  245. default:
  246. dp_err("Invalid CMEM request");
  247. }
  248. return status;
  249. }
  250. #else
  251. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  252. bool is_4k_align) {}
  253. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  254. uint32_t offset,
  255. uint32_t value)
  256. { }
  257. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  258. {
  259. return QDF_STATUS_SUCCESS;
  260. }
  261. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  262. uint8_t for_feature)
  263. {
  264. return QDF_STATUS_SUCCESS;
  265. }
  266. #endif
  267. QDF_STATUS
  268. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  269. struct dp_hw_cookie_conversion_t *cc_ctx,
  270. uint32_t num_descs,
  271. enum dp_desc_type desc_type,
  272. uint8_t desc_pool_id)
  273. {
  274. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  275. uint32_t num_spt_pages, i = 0;
  276. struct dp_spt_page_desc *spt_desc;
  277. struct qdf_mem_dma_page_t *dma_page;
  278. uint8_t chip_id;
  279. /* estimate how many SPT DDR pages needed */
  280. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  281. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  282. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  283. dp_info("num_spt_pages needed %d", num_spt_pages);
  284. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  285. &cc_ctx->page_pool, qdf_page_size,
  286. num_spt_pages, 0, false);
  287. if (!cc_ctx->page_pool.dma_pages) {
  288. dp_err("spt ddr pages allocation failed");
  289. return QDF_STATUS_E_RESOURCES;
  290. }
  291. cc_ctx->page_desc_base = qdf_mem_malloc(
  292. num_spt_pages * sizeof(struct dp_spt_page_desc));
  293. if (!cc_ctx->page_desc_base) {
  294. dp_err("spt page descs allocation failed");
  295. goto fail_0;
  296. }
  297. chip_id = dp_mlo_get_chip_id(soc);
  298. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  299. desc_type);
  300. /* initial page desc */
  301. spt_desc = cc_ctx->page_desc_base;
  302. dma_page = cc_ctx->page_pool.dma_pages;
  303. while (i < num_spt_pages) {
  304. /* check if page address 4K aligned */
  305. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  306. dp_err("non-4k aligned pages addr %pK",
  307. (void *)dma_page[i].page_p_addr);
  308. goto fail_1;
  309. }
  310. spt_desc[i].page_v_addr =
  311. dma_page[i].page_v_addr_start;
  312. spt_desc[i].page_p_addr =
  313. dma_page[i].page_p_addr;
  314. i++;
  315. }
  316. cc_ctx->total_page_num = num_spt_pages;
  317. qdf_spinlock_create(&cc_ctx->cc_lock);
  318. return QDF_STATUS_SUCCESS;
  319. fail_1:
  320. qdf_mem_free(cc_ctx->page_desc_base);
  321. fail_0:
  322. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  323. &cc_ctx->page_pool, 0, false);
  324. return QDF_STATUS_E_FAILURE;
  325. }
  326. QDF_STATUS
  327. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  328. struct dp_hw_cookie_conversion_t *cc_ctx)
  329. {
  330. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  331. qdf_mem_free(cc_ctx->page_desc_base);
  332. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  333. &cc_ctx->page_pool, 0, false);
  334. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  335. return QDF_STATUS_SUCCESS;
  336. }
  337. QDF_STATUS
  338. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  339. struct dp_hw_cookie_conversion_t *cc_ctx)
  340. {
  341. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  342. uint32_t i = 0;
  343. struct dp_spt_page_desc *spt_desc;
  344. uint32_t ppt_index;
  345. uint32_t ppt_id_start;
  346. if (!cc_ctx->total_page_num) {
  347. dp_err("total page num is 0");
  348. return QDF_STATUS_E_INVAL;
  349. }
  350. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  351. spt_desc = cc_ctx->page_desc_base;
  352. while (i < cc_ctx->total_page_num) {
  353. /* write page PA to CMEM */
  354. dp_hw_cc_cmem_write(soc->hal_soc,
  355. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  356. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  357. (spt_desc[i].page_p_addr >>
  358. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  359. ppt_index = ppt_id_start + i;
  360. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  361. qdf_assert_always(0);
  362. spt_desc[i].ppt_index = ppt_index;
  363. be_soc->page_desc_base[ppt_index].page_v_addr =
  364. spt_desc[i].page_v_addr;
  365. i++;
  366. }
  367. return QDF_STATUS_SUCCESS;
  368. }
  369. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  370. QDF_STATUS
  371. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  372. struct dp_hw_cookie_conversion_t *cc_ctx)
  373. {
  374. uint32_t ppt_index;
  375. struct dp_spt_page_desc *spt_desc;
  376. int i = 0;
  377. spt_desc = cc_ctx->page_desc_base;
  378. while (i < cc_ctx->total_page_num) {
  379. ppt_index = spt_desc[i].ppt_index;
  380. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  381. i++;
  382. }
  383. return QDF_STATUS_SUCCESS;
  384. }
  385. #else
  386. QDF_STATUS
  387. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  388. struct dp_hw_cookie_conversion_t *cc_ctx)
  389. {
  390. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  391. uint32_t ppt_index;
  392. struct dp_spt_page_desc *spt_desc;
  393. int i = 0;
  394. spt_desc = cc_ctx->page_desc_base;
  395. while (i < cc_ctx->total_page_num) {
  396. /* reset PA in CMEM to NULL */
  397. dp_hw_cc_cmem_write(soc->hal_soc,
  398. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  399. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  400. 0);
  401. ppt_index = spt_desc[i].ppt_index;
  402. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  403. i++;
  404. }
  405. return QDF_STATUS_SUCCESS;
  406. }
  407. #endif
  408. #ifdef WLAN_SUPPORT_PPEDS
  409. static QDF_STATUS dp_soc_ppe_attach_be(struct dp_soc *soc)
  410. {
  411. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  412. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  413. /*
  414. * Check if PPE DS is enabled.
  415. */
  416. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc->wlan_cfg_ctx))
  417. return QDF_STATUS_SUCCESS;
  418. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  419. return QDF_STATUS_SUCCESS;
  420. cdp_ops->ppe_ops = &dp_ops_ppe_be;
  421. return QDF_STATUS_SUCCESS;
  422. }
  423. static QDF_STATUS dp_soc_ppe_detach_be(struct dp_soc *soc)
  424. {
  425. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  426. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  427. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc->wlan_cfg_ctx))
  428. return QDF_STATUS_E_FAILURE;
  429. dp_ppeds_detach_soc_be(be_soc);
  430. cdp_ops->ppe_ops = NULL;
  431. return QDF_STATUS_SUCCESS;
  432. }
  433. static QDF_STATUS dp_peer_setup_ppe_be(struct dp_soc *soc,
  434. struct dp_peer_be *be_peer,
  435. struct dp_vdev_be *be_vdev)
  436. {
  437. uint16_t service_code;
  438. uint8_t priority_valid;
  439. struct dp_ppe_vp_profile *ppe_vp_profile = &be_vdev->ppe_vp_profile;
  440. uint16_t src_info = ppe_vp_profile->vp_num;
  441. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  442. uint8_t use_ppe = PEER_ROUTING_USE_PPE;
  443. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  444. QDF_STATUS status = QDF_STATUS_SUCCESS;
  445. /*
  446. * Get these Values from INIT
  447. */
  448. service_code = 0;
  449. priority_valid = be_peer->priority_valid;
  450. if (soc->cdp_soc.ol_ops->peer_set_ppe_default_routing) {
  451. status =
  452. soc->cdp_soc.ol_ops->peer_set_ppe_default_routing
  453. (soc->ctrl_psoc,
  454. be_peer->peer.mac_addr.raw,
  455. service_code, priority_valid,
  456. src_info, vdev_id, use_ppe,
  457. peer_routing_enabled);
  458. if (status != QDF_STATUS_SUCCESS) {
  459. qdf_err("vdev_id: %d, PPE peer routing mac:"
  460. QDF_MAC_ADDR_FMT, vdev_id,
  461. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  462. return QDF_STATUS_E_FAILURE;
  463. }
  464. }
  465. return QDF_STATUS_SUCCESS;
  466. }
  467. #else
  468. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  469. {
  470. return QDF_STATUS_SUCCESS;
  471. }
  472. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  473. {
  474. return QDF_STATUS_SUCCESS;
  475. }
  476. static inline QDF_STATUS dp_soc_ppe_attach_be(struct dp_soc *soc)
  477. {
  478. return QDF_STATUS_SUCCESS;
  479. }
  480. static inline QDF_STATUS dp_soc_ppe_detach_be(struct dp_soc *soc)
  481. {
  482. return QDF_STATUS_SUCCESS;
  483. }
  484. static inline
  485. QDF_STATUS dp_peer_setup_ppe_be(struct dp_soc *soc,
  486. struct dp_peer_be *be_peer,
  487. struct dp_vdev_be *be_vdev)
  488. {
  489. return QDF_STATUS_SUCCESS;
  490. }
  491. #endif /* WLAN_SUPPORT_PPEDS */
  492. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  493. {
  494. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  495. int i = 0;
  496. dp_soc_ppe_detach_be(soc);
  497. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  498. dp_hw_cookie_conversion_detach(be_soc,
  499. &be_soc->tx_cc_ctx[i]);
  500. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  501. dp_hw_cookie_conversion_detach(be_soc,
  502. &be_soc->rx_cc_ctx[i]);
  503. qdf_mem_free(be_soc->page_desc_base);
  504. be_soc->page_desc_base = NULL;
  505. return QDF_STATUS_SUCCESS;
  506. }
  507. #ifdef WLAN_MLO_MULTI_CHIP
  508. #ifdef WLAN_MCAST_MLO
  509. static inline void
  510. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  511. {
  512. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  513. be_vdev->mcast_primary = false;
  514. be_vdev->seq_num = 0;
  515. dp_tx_mcast_mlo_reinject_routing_set(soc,
  516. (void *)&be_vdev->mcast_primary);
  517. if (vdev->opmode == wlan_op_mode_ap) {
  518. if (vdev->mlo_vdev)
  519. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  520. vdev->vdev_id,
  521. HAL_TX_MCAST_CTRL_DROP);
  522. else
  523. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  524. vdev->vdev_id,
  525. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  526. }
  527. }
  528. static inline void
  529. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  530. {
  531. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  532. be_vdev->seq_num = 0;
  533. be_vdev->mcast_primary = false;
  534. vdev->mlo_vdev = false;
  535. }
  536. #else
  537. static inline void
  538. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  539. {
  540. }
  541. static inline void
  542. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  543. {
  544. }
  545. #endif
  546. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  547. {
  548. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  549. qdf_mem_set(be_vdev->partner_vdev_list,
  550. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  551. CDP_INVALID_VDEV_ID);
  552. }
  553. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  554. struct cdp_lro_hash_config *lro_hash)
  555. {
  556. dp_mlo_get_rx_hash_key(soc, lro_hash);
  557. }
  558. #else
  559. static inline void
  560. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  561. {
  562. }
  563. static inline void
  564. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  565. {
  566. }
  567. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  568. {
  569. }
  570. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  571. struct cdp_lro_hash_config *lro_hash)
  572. {
  573. dp_get_rx_hash_key_bytes(lro_hash);
  574. }
  575. #endif
  576. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  577. struct cdp_soc_attach_params *params)
  578. {
  579. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  580. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  581. uint32_t max_tx_rx_desc_num, num_spt_pages;
  582. uint32_t num_entries;
  583. int i = 0;
  584. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  585. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  586. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  587. /* estimate how many SPT DDR pages needed */
  588. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  589. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  590. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  591. be_soc->page_desc_base = qdf_mem_malloc(
  592. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  593. if (!be_soc->page_desc_base) {
  594. dp_err("spt page descs allocation failed");
  595. return QDF_STATUS_E_NOMEM;
  596. }
  597. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  598. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  599. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  600. goto fail;
  601. dp_soc_mlo_fill_params(soc, params);
  602. qdf_status = dp_soc_ppe_attach_be(soc);
  603. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  604. goto fail;
  605. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  606. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  607. qdf_status =
  608. dp_hw_cookie_conversion_attach(be_soc,
  609. &be_soc->tx_cc_ctx[i],
  610. num_entries,
  611. DP_TX_DESC_TYPE, i);
  612. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  613. goto fail;
  614. }
  615. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  616. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  617. goto fail;
  618. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  619. num_entries =
  620. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  621. qdf_status =
  622. dp_hw_cookie_conversion_attach(be_soc,
  623. &be_soc->rx_cc_ctx[i],
  624. num_entries,
  625. DP_RX_DESC_BUF_TYPE, i);
  626. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  627. goto fail;
  628. }
  629. return qdf_status;
  630. fail:
  631. dp_soc_detach_be(soc);
  632. return qdf_status;
  633. }
  634. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  635. {
  636. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  637. int i = 0;
  638. dp_tx_deinit_bank_profiles(be_soc);
  639. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  640. dp_hw_cookie_conversion_deinit(be_soc,
  641. &be_soc->tx_cc_ctx[i]);
  642. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  643. dp_hw_cookie_conversion_deinit(be_soc,
  644. &be_soc->rx_cc_ctx[i]);
  645. dp_ppeds_deinit_soc_be(soc);
  646. return QDF_STATUS_SUCCESS;
  647. }
  648. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  649. {
  650. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  651. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  652. int i = 0;
  653. dp_ppeds_init_soc_be(soc);
  654. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  655. qdf_status =
  656. dp_hw_cookie_conversion_init(be_soc,
  657. &be_soc->tx_cc_ctx[i]);
  658. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  659. goto fail;
  660. }
  661. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  662. qdf_status =
  663. dp_hw_cookie_conversion_init(be_soc,
  664. &be_soc->rx_cc_ctx[i]);
  665. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  666. goto fail;
  667. }
  668. /* route vdev_id mismatch notification via FW completion */
  669. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  670. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  671. qdf_status = dp_tx_init_bank_profiles(be_soc);
  672. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  673. goto fail;
  674. /* write WBM/REO cookie conversion CFG register */
  675. dp_cc_reg_cfg_init(soc, true);
  676. return qdf_status;
  677. fail:
  678. dp_soc_deinit_be(soc);
  679. return qdf_status;
  680. }
  681. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  682. struct cdp_pdev_attach_params *params)
  683. {
  684. dp_pdev_mlo_fill_params(pdev, params);
  685. dp_mlo_update_link_to_pdev_map(pdev->soc, pdev);
  686. return QDF_STATUS_SUCCESS;
  687. }
  688. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  689. {
  690. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  691. return QDF_STATUS_SUCCESS;
  692. }
  693. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  694. {
  695. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  696. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  697. struct dp_pdev *pdev = vdev->pdev;
  698. if (vdev->opmode == wlan_op_mode_monitor)
  699. return QDF_STATUS_SUCCESS;
  700. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  701. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  702. vdev->bank_id = be_vdev->bank_id;
  703. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  704. QDF_BUG(0);
  705. return QDF_STATUS_E_FAULT;
  706. }
  707. if (vdev->opmode == wlan_op_mode_sta) {
  708. if (soc->cdp_soc.ol_ops->set_mec_timer)
  709. soc->cdp_soc.ol_ops->set_mec_timer(
  710. soc->ctrl_psoc,
  711. vdev->vdev_id,
  712. DP_AST_AGING_TIMER_DEFAULT_MS);
  713. if (pdev->isolation)
  714. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  715. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  716. else
  717. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  718. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  719. }
  720. dp_mlo_mcast_init(soc, vdev);
  721. dp_mlo_init_ptnr_list(vdev);
  722. return QDF_STATUS_SUCCESS;
  723. }
  724. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  725. {
  726. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  727. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  728. if (vdev->opmode == wlan_op_mode_monitor)
  729. return QDF_STATUS_SUCCESS;
  730. if (vdev->opmode == wlan_op_mode_ap)
  731. dp_mlo_mcast_deinit(soc, vdev);
  732. dp_tx_put_bank_profile(be_soc, be_vdev);
  733. dp_clr_mlo_ptnr_list(soc, vdev);
  734. return QDF_STATUS_SUCCESS;
  735. }
  736. #ifdef WLAN_SUPPORT_PPEDS
  737. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  738. {
  739. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  740. struct dp_vdev_be *be_vdev;
  741. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  742. if (!be_peer) {
  743. qdf_err("BE peer is null");
  744. return QDF_STATUS_E_NULL_VALUE;
  745. }
  746. be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev);
  747. if (!be_vdev) {
  748. qdf_err("BE vap is null");
  749. return QDF_STATUS_E_NULL_VALUE;
  750. }
  751. /*
  752. * Check if PPE routing is enabled on the associated vap.
  753. */
  754. if (be_vdev->ppe_vp_enabled == PPE_VP_USER_TYPE_DS)
  755. qdf_status = dp_peer_setup_ppe_be(soc, be_peer, be_vdev);
  756. return qdf_status;
  757. }
  758. #else
  759. static QDF_STATUS dp_peer_setup_be(struct dp_soc *soc, struct dp_peer *peer)
  760. {
  761. return QDF_STATUS_SUCCESS;
  762. }
  763. #endif
  764. qdf_size_t dp_get_soc_context_size_be(void)
  765. {
  766. return sizeof(struct dp_soc_be);
  767. }
  768. #ifdef CONFIG_WORD_BASED_TLV
  769. /**
  770. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  771. * @soc: Common DP soc handle
  772. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  773. *
  774. * Return: none
  775. */
  776. static inline void
  777. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  778. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  779. {
  780. htt_tlv_filter->rx_msdu_end_wmask =
  781. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  782. htt_tlv_filter->rx_mpdu_start_wmask =
  783. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  784. }
  785. #else
  786. static inline void
  787. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  788. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  789. {
  790. }
  791. #endif
  792. #ifdef NO_RX_PKT_HDR_TLV
  793. /**
  794. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  795. * @soc: Common DP soc handle
  796. *
  797. * Return: QDF_STATUS
  798. */
  799. static QDF_STATUS
  800. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  801. {
  802. int i;
  803. int mac_id;
  804. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  805. struct dp_srng *rx_mac_srng;
  806. QDF_STATUS status = QDF_STATUS_SUCCESS;
  807. /*
  808. * In Beryllium chipset msdu_start, mpdu_end
  809. * and rx_attn are part of msdu_end/mpdu_start
  810. */
  811. htt_tlv_filter.msdu_start = 0;
  812. htt_tlv_filter.mpdu_end = 0;
  813. htt_tlv_filter.attention = 0;
  814. htt_tlv_filter.mpdu_start = 1;
  815. htt_tlv_filter.msdu_end = 1;
  816. htt_tlv_filter.packet = 1;
  817. htt_tlv_filter.packet_header = 0;
  818. htt_tlv_filter.ppdu_start = 0;
  819. htt_tlv_filter.ppdu_end = 0;
  820. htt_tlv_filter.ppdu_end_user_stats = 0;
  821. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  822. htt_tlv_filter.ppdu_end_status_done = 0;
  823. htt_tlv_filter.enable_fp = 1;
  824. htt_tlv_filter.enable_md = 0;
  825. htt_tlv_filter.enable_md = 0;
  826. htt_tlv_filter.enable_mo = 0;
  827. htt_tlv_filter.fp_mgmt_filter = 0;
  828. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  829. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  830. FILTER_DATA_MCAST |
  831. FILTER_DATA_DATA);
  832. htt_tlv_filter.mo_mgmt_filter = 0;
  833. htt_tlv_filter.mo_ctrl_filter = 0;
  834. htt_tlv_filter.mo_data_filter = 0;
  835. htt_tlv_filter.md_data_filter = 0;
  836. htt_tlv_filter.offset_valid = true;
  837. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  838. htt_tlv_filter.rx_mpdu_end_offset = 0;
  839. htt_tlv_filter.rx_msdu_start_offset = 0;
  840. htt_tlv_filter.rx_attn_offset = 0;
  841. /*
  842. * For monitor mode, the packet hdr tlv is enabled later during
  843. * filter update
  844. */
  845. if (soc->cdp_soc.ol_ops->get_con_mode &&
  846. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  847. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  848. else
  849. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  850. /*Not subscribing rx_pkt_header*/
  851. htt_tlv_filter.rx_header_offset = 0;
  852. htt_tlv_filter.rx_mpdu_start_offset =
  853. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  854. htt_tlv_filter.rx_msdu_end_offset =
  855. hal_rx_msdu_end_offset_get(soc->hal_soc);
  856. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  857. for (i = 0; i < MAX_PDEV_CNT; i++) {
  858. struct dp_pdev *pdev = soc->pdev_list[i];
  859. if (!pdev)
  860. continue;
  861. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  862. int mac_for_pdev =
  863. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  864. /*
  865. * Obtain lmac id from pdev to access the LMAC ring
  866. * in soc context
  867. */
  868. int lmac_id =
  869. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  870. pdev->pdev_id);
  871. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  872. if (!rx_mac_srng->hal_srng)
  873. continue;
  874. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  875. rx_mac_srng->hal_srng,
  876. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  877. &htt_tlv_filter);
  878. }
  879. }
  880. return status;
  881. }
  882. #else
  883. /**
  884. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  885. * @soc: Common DP soc handle
  886. *
  887. * Return: QDF_STATUS
  888. */
  889. static QDF_STATUS
  890. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  891. {
  892. int i;
  893. int mac_id;
  894. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  895. struct dp_srng *rx_mac_srng;
  896. QDF_STATUS status = QDF_STATUS_SUCCESS;
  897. /*
  898. * In Beryllium chipset msdu_start, mpdu_end
  899. * and rx_attn are part of msdu_end/mpdu_start
  900. */
  901. htt_tlv_filter.msdu_start = 0;
  902. htt_tlv_filter.mpdu_end = 0;
  903. htt_tlv_filter.attention = 0;
  904. htt_tlv_filter.mpdu_start = 1;
  905. htt_tlv_filter.msdu_end = 1;
  906. htt_tlv_filter.packet = 1;
  907. htt_tlv_filter.packet_header = 1;
  908. htt_tlv_filter.ppdu_start = 0;
  909. htt_tlv_filter.ppdu_end = 0;
  910. htt_tlv_filter.ppdu_end_user_stats = 0;
  911. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  912. htt_tlv_filter.ppdu_end_status_done = 0;
  913. htt_tlv_filter.enable_fp = 1;
  914. htt_tlv_filter.enable_md = 0;
  915. htt_tlv_filter.enable_md = 0;
  916. htt_tlv_filter.enable_mo = 0;
  917. htt_tlv_filter.fp_mgmt_filter = 0;
  918. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  919. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  920. FILTER_DATA_MCAST |
  921. FILTER_DATA_DATA);
  922. htt_tlv_filter.mo_mgmt_filter = 0;
  923. htt_tlv_filter.mo_ctrl_filter = 0;
  924. htt_tlv_filter.mo_data_filter = 0;
  925. htt_tlv_filter.md_data_filter = 0;
  926. htt_tlv_filter.offset_valid = true;
  927. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  928. htt_tlv_filter.rx_mpdu_end_offset = 0;
  929. htt_tlv_filter.rx_msdu_start_offset = 0;
  930. htt_tlv_filter.rx_attn_offset = 0;
  931. /*
  932. * For monitor mode, the packet hdr tlv is enabled later during
  933. * filter update
  934. */
  935. if (soc->cdp_soc.ol_ops->get_con_mode &&
  936. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  937. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  938. else
  939. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  940. htt_tlv_filter.rx_header_offset =
  941. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  942. htt_tlv_filter.rx_mpdu_start_offset =
  943. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  944. htt_tlv_filter.rx_msdu_end_offset =
  945. hal_rx_msdu_end_offset_get(soc->hal_soc);
  946. dp_info("TLV subscription\n"
  947. "msdu_start %d, mpdu_end %d, attention %d"
  948. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  949. "TLV offsets\n"
  950. "msdu_start %d, mpdu_end %d, attention %d"
  951. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  952. htt_tlv_filter.msdu_start,
  953. htt_tlv_filter.mpdu_end,
  954. htt_tlv_filter.attention,
  955. htt_tlv_filter.mpdu_start,
  956. htt_tlv_filter.msdu_end,
  957. htt_tlv_filter.packet_header,
  958. htt_tlv_filter.packet,
  959. htt_tlv_filter.rx_msdu_start_offset,
  960. htt_tlv_filter.rx_mpdu_end_offset,
  961. htt_tlv_filter.rx_attn_offset,
  962. htt_tlv_filter.rx_mpdu_start_offset,
  963. htt_tlv_filter.rx_msdu_end_offset,
  964. htt_tlv_filter.rx_header_offset,
  965. htt_tlv_filter.rx_packet_offset);
  966. for (i = 0; i < MAX_PDEV_CNT; i++) {
  967. struct dp_pdev *pdev = soc->pdev_list[i];
  968. if (!pdev)
  969. continue;
  970. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  971. int mac_for_pdev =
  972. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  973. /*
  974. * Obtain lmac id from pdev to access the LMAC ring
  975. * in soc context
  976. */
  977. int lmac_id =
  978. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  979. pdev->pdev_id);
  980. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  981. if (!rx_mac_srng->hal_srng)
  982. continue;
  983. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  984. rx_mac_srng->hal_srng,
  985. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  986. &htt_tlv_filter);
  987. }
  988. }
  989. return status;
  990. }
  991. #endif
  992. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  993. /**
  994. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  995. * near-full IRQs.
  996. * @soc: Datapath SoC handle
  997. * @int_ctx: Interrupt context
  998. * @dp_budget: Budget of the work that can be done in the bottom half
  999. *
  1000. * Return: work done in the handler
  1001. */
  1002. static uint32_t
  1003. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1004. uint32_t dp_budget)
  1005. {
  1006. int ring = 0;
  1007. int budget = dp_budget;
  1008. uint32_t work_done = 0;
  1009. uint32_t remaining_quota = dp_budget;
  1010. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1011. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1012. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1013. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1014. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1015. rx_near_full_grp_2_mask;
  1016. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1017. rx_near_full_mask,
  1018. tx_ring_near_full_mask);
  1019. if (rx_near_full_mask) {
  1020. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1021. if (!(rx_near_full_mask & (1 << ring)))
  1022. continue;
  1023. work_done = dp_rx_nf_process(int_ctx,
  1024. soc->reo_dest_ring[ring].hal_srng,
  1025. ring, remaining_quota);
  1026. if (work_done) {
  1027. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1028. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1029. rx_near_full_mask, ring,
  1030. work_done,
  1031. budget);
  1032. budget -= work_done;
  1033. if (budget <= 0)
  1034. goto budget_done;
  1035. remaining_quota = budget;
  1036. }
  1037. }
  1038. }
  1039. if (tx_ring_near_full_mask) {
  1040. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1041. if (!(tx_ring_near_full_mask & (1 << ring)))
  1042. continue;
  1043. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1044. soc->tx_comp_ring[ring].hal_srng,
  1045. ring, remaining_quota);
  1046. if (work_done) {
  1047. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1048. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1049. tx_ring_near_full_mask, ring,
  1050. work_done, budget);
  1051. budget -= work_done;
  1052. if (budget <= 0)
  1053. break;
  1054. remaining_quota = budget;
  1055. }
  1056. }
  1057. }
  1058. intr_stats->num_near_full_masks++;
  1059. budget_done:
  1060. return dp_budget - budget;
  1061. }
  1062. /**
  1063. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1064. * state and set the reap_limit appropriately
  1065. * as per the near full state
  1066. * @soc: Datapath soc handle
  1067. * @dp_srng: Datapath handle for SRNG
  1068. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1069. * the srng near-full state
  1070. *
  1071. * Return: 1, if the srng is in near-full state
  1072. * 0, if the srng is not in near-full state
  1073. */
  1074. static int
  1075. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1076. struct dp_srng *dp_srng,
  1077. int *max_reap_limit)
  1078. {
  1079. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1080. }
  1081. /**
  1082. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1083. * near full IRQ handling operations.
  1084. * @arch_ops: arch ops handle
  1085. *
  1086. * Return: none
  1087. */
  1088. static inline void
  1089. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1090. {
  1091. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1092. arch_ops->dp_srng_test_and_update_nf_params =
  1093. dp_srng_test_and_update_nf_params_be;
  1094. }
  1095. #else
  1096. static inline void
  1097. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1098. {
  1099. }
  1100. #endif
  1101. #ifdef WLAN_SUPPORT_PPEDS
  1102. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  1103. {
  1104. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1105. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1106. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1107. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1108. return;
  1109. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  1110. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  1111. be_soc->ppe_release_ring.alloc_size,
  1112. soc->ctrl_psoc,
  1113. WLAN_MD_DP_SRNG_PPE_RELEASE,
  1114. "ppe_release_ring");
  1115. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1116. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1117. be_soc->ppe2tcl_ring.alloc_size,
  1118. soc->ctrl_psoc,
  1119. WLAN_MD_DP_SRNG_PPE2TCL,
  1120. "ppe2tcl_ring");
  1121. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1122. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1123. be_soc->reo2ppe_ring.alloc_size,
  1124. soc->ctrl_psoc,
  1125. WLAN_MD_DP_SRNG_REO2PPE,
  1126. "reo2ppe_ring");
  1127. }
  1128. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  1129. {
  1130. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1131. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1132. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1133. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1134. return;
  1135. dp_srng_free(soc, &be_soc->ppe_release_ring);
  1136. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1137. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1138. }
  1139. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  1140. {
  1141. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1142. uint32_t entries;
  1143. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1144. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1145. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1146. return QDF_STATUS_SUCCESS;
  1147. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1148. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1149. entries, 0)) {
  1150. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1151. goto fail;
  1152. }
  1153. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1154. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1155. entries, 0)) {
  1156. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1157. goto fail;
  1158. }
  1159. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  1160. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  1161. entries, 0)) {
  1162. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  1163. goto fail;
  1164. }
  1165. return QDF_STATUS_SUCCESS;
  1166. fail:
  1167. dp_soc_ppe_srng_free(soc);
  1168. return QDF_STATUS_E_NOMEM;
  1169. }
  1170. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1171. {
  1172. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1173. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1174. hal_soc_handle_t hal_soc = soc->hal_soc;
  1175. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1176. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1177. return QDF_STATUS_SUCCESS;
  1178. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  1179. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1180. goto fail;
  1181. }
  1182. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1183. be_soc->reo2ppe_ring.alloc_size,
  1184. soc->ctrl_psoc,
  1185. WLAN_MD_DP_SRNG_REO2PPE,
  1186. "reo2ppe_ring");
  1187. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1188. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  1189. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1190. goto fail;
  1191. }
  1192. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1193. be_soc->ppe2tcl_ring.alloc_size,
  1194. soc->ctrl_psoc,
  1195. WLAN_MD_DP_SRNG_PPE2TCL,
  1196. "ppe2tcl_ring");
  1197. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  1198. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  1199. goto fail;
  1200. }
  1201. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  1202. be_soc->ppe_release_ring.alloc_size,
  1203. soc->ctrl_psoc,
  1204. WLAN_MD_DP_SRNG_PPE_RELEASE,
  1205. "ppe_release_ring");
  1206. #ifdef WLAN_SUPPORT_PPEDS
  1207. if (dp_ppeds_register_soc_be(be_soc)) {
  1208. dp_err("%pK: ppeds registration failed", soc);
  1209. goto fail;
  1210. }
  1211. #endif
  1212. return QDF_STATUS_SUCCESS;
  1213. fail:
  1214. dp_soc_ppe_srng_deinit(soc);
  1215. return QDF_STATUS_E_NOMEM;
  1216. }
  1217. #else
  1218. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  1219. {
  1220. }
  1221. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  1222. {
  1223. }
  1224. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  1225. {
  1226. return QDF_STATUS_SUCCESS;
  1227. }
  1228. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1229. {
  1230. return QDF_STATUS_SUCCESS;
  1231. }
  1232. #endif
  1233. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1234. {
  1235. uint32_t i;
  1236. dp_soc_ppe_srng_deinit(soc);
  1237. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1238. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1239. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1240. RXDMA_BUF, 0);
  1241. }
  1242. }
  1243. }
  1244. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1245. {
  1246. uint32_t i;
  1247. dp_soc_ppe_srng_free(soc);
  1248. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1249. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1250. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1251. }
  1252. }
  1253. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1254. {
  1255. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1256. uint32_t ring_size;
  1257. uint32_t i;
  1258. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1259. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1260. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1261. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1262. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1263. RXDMA_BUF, ring_size, 0)) {
  1264. dp_err("%pK: dp_srng_alloc failed refill ring",
  1265. soc);
  1266. goto fail;
  1267. }
  1268. }
  1269. }
  1270. if (dp_soc_ppe_srng_alloc(soc)) {
  1271. dp_err("%pK: ppe rings alloc failed",
  1272. soc);
  1273. goto fail;
  1274. }
  1275. return QDF_STATUS_SUCCESS;
  1276. fail:
  1277. dp_soc_srng_free_be(soc);
  1278. return QDF_STATUS_E_NOMEM;
  1279. }
  1280. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1281. {
  1282. int i = 0;
  1283. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1284. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1285. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1286. RXDMA_BUF, 0, 0)) {
  1287. dp_err("%pK: dp_srng_init failed refill ring",
  1288. soc);
  1289. goto fail;
  1290. }
  1291. }
  1292. }
  1293. if (dp_soc_ppe_srng_init(soc)) {
  1294. dp_err("%pK: ppe rings init failed",
  1295. soc);
  1296. goto fail;
  1297. }
  1298. return QDF_STATUS_SUCCESS;
  1299. fail:
  1300. dp_soc_srng_deinit_be(soc);
  1301. return QDF_STATUS_E_NOMEM;
  1302. }
  1303. #ifdef WLAN_FEATURE_11BE_MLO
  1304. static inline unsigned
  1305. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1306. union dp_align_mac_addr *mac_addr)
  1307. {
  1308. uint32_t index;
  1309. index =
  1310. mac_addr->align2.bytes_ab ^
  1311. mac_addr->align2.bytes_cd ^
  1312. mac_addr->align2.bytes_ef;
  1313. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1314. index &= mld_hash_obj->mld_peer_hash.mask;
  1315. return index;
  1316. }
  1317. QDF_STATUS
  1318. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1319. int hash_elems)
  1320. {
  1321. int i, log2;
  1322. if (!mld_hash_obj)
  1323. return QDF_STATUS_E_FAILURE;
  1324. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1325. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1326. log2 = dp_log2_ceil(hash_elems);
  1327. hash_elems = 1 << log2;
  1328. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1329. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1330. /* allocate an array of TAILQ peer object lists */
  1331. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1332. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1333. if (!mld_hash_obj->mld_peer_hash.bins)
  1334. return QDF_STATUS_E_NOMEM;
  1335. for (i = 0; i < hash_elems; i++)
  1336. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1337. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1338. return QDF_STATUS_SUCCESS;
  1339. }
  1340. void
  1341. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1342. {
  1343. if (!mld_hash_obj)
  1344. return;
  1345. if (mld_hash_obj->mld_peer_hash.bins) {
  1346. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1347. mld_hash_obj->mld_peer_hash.bins = NULL;
  1348. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1349. }
  1350. }
  1351. #ifdef WLAN_MLO_MULTI_CHIP
  1352. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1353. {
  1354. /* In case of MULTI chip MLO peer hash table when MLO global object
  1355. * is created, avoid from SOC attach path
  1356. */
  1357. return QDF_STATUS_SUCCESS;
  1358. }
  1359. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1360. {
  1361. }
  1362. #else
  1363. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1364. {
  1365. dp_mld_peer_hash_obj_t mld_hash_obj;
  1366. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1367. if (!mld_hash_obj)
  1368. return QDF_STATUS_E_FAILURE;
  1369. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1370. }
  1371. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1372. {
  1373. dp_mld_peer_hash_obj_t mld_hash_obj;
  1374. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1375. if (!mld_hash_obj)
  1376. return;
  1377. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1378. }
  1379. #endif
  1380. static struct dp_peer *
  1381. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1382. uint8_t *peer_mac_addr,
  1383. int mac_addr_is_aligned,
  1384. enum dp_mod_id mod_id,
  1385. uint8_t vdev_id)
  1386. {
  1387. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1388. uint32_t index;
  1389. struct dp_peer *peer;
  1390. struct dp_vdev *vdev;
  1391. dp_mld_peer_hash_obj_t mld_hash_obj;
  1392. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1393. if (!mld_hash_obj)
  1394. return NULL;
  1395. if (!mld_hash_obj->mld_peer_hash.bins)
  1396. return NULL;
  1397. if (mac_addr_is_aligned) {
  1398. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1399. } else {
  1400. qdf_mem_copy(
  1401. &local_mac_addr_aligned.raw[0],
  1402. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1403. mac_addr = &local_mac_addr_aligned;
  1404. }
  1405. if (vdev_id != DP_VDEV_ALL) {
  1406. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1407. if (!vdev) {
  1408. dp_err("vdev is null\n");
  1409. return NULL;
  1410. }
  1411. } else {
  1412. vdev = NULL;
  1413. }
  1414. /* search mld peer table if no link peer for given mac address */
  1415. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1416. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1417. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1418. hash_list_elem) {
  1419. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1420. if ((vdev_id == DP_VDEV_ALL) || (
  1421. dp_peer_find_mac_addr_cmp(
  1422. &peer->vdev->mld_mac_addr,
  1423. &vdev->mld_mac_addr) == 0)) {
  1424. /* take peer reference before returning */
  1425. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1426. QDF_STATUS_SUCCESS)
  1427. peer = NULL;
  1428. if (vdev)
  1429. dp_vdev_unref_delete(soc, vdev, mod_id);
  1430. qdf_spin_unlock_bh(
  1431. &mld_hash_obj->mld_peer_hash_lock);
  1432. return peer;
  1433. }
  1434. }
  1435. }
  1436. if (vdev)
  1437. dp_vdev_unref_delete(soc, vdev, mod_id);
  1438. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1439. return NULL; /* failure */
  1440. }
  1441. static void
  1442. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1443. {
  1444. uint32_t index;
  1445. struct dp_peer *tmppeer = NULL;
  1446. int found = 0;
  1447. dp_mld_peer_hash_obj_t mld_hash_obj;
  1448. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1449. if (!mld_hash_obj)
  1450. return;
  1451. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1452. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1453. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1454. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1455. hash_list_elem) {
  1456. if (tmppeer == peer) {
  1457. found = 1;
  1458. break;
  1459. }
  1460. }
  1461. QDF_ASSERT(found);
  1462. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1463. hash_list_elem);
  1464. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1465. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1466. }
  1467. static void
  1468. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1469. {
  1470. uint32_t index;
  1471. dp_mld_peer_hash_obj_t mld_hash_obj;
  1472. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1473. if (!mld_hash_obj)
  1474. return;
  1475. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1476. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1477. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1478. DP_MOD_ID_CONFIG))) {
  1479. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1480. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1481. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1482. return;
  1483. }
  1484. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1485. hash_list_elem);
  1486. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1487. }
  1488. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1489. {
  1490. uint32_t index;
  1491. struct dp_peer *peer;
  1492. dp_mld_peer_hash_obj_t mld_hash_obj;
  1493. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1494. if (!mld_hash_obj)
  1495. return;
  1496. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1497. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1498. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1499. hash_list_elem) {
  1500. dp_print_peer_ast_entries(soc, peer, NULL);
  1501. }
  1502. }
  1503. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1504. }
  1505. #endif
  1506. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1507. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1508. struct dp_vdev *vdev)
  1509. {
  1510. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1511. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1512. hal_soc_handle_t hal_soc = soc->hal_soc;
  1513. uint8_t vdev_id = vdev->vdev_id;
  1514. if (vdev->opmode == wlan_op_mode_sta) {
  1515. if (vdev->pdev->isolation)
  1516. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1517. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1518. else
  1519. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1520. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1521. } else if (vdev->opmode == wlan_op_mode_ap) {
  1522. if (vdev->mlo_vdev) {
  1523. if (be_vdev->mcast_primary) {
  1524. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1525. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1526. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1527. vdev_id + 128,
  1528. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1529. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1530. dp_tx_mcast_mlo_reinject_routing_set,
  1531. (void *)&be_vdev->mcast_primary);
  1532. } else {
  1533. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1534. HAL_TX_MCAST_CTRL_DROP);
  1535. }
  1536. } else {
  1537. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1538. vdev_id,
  1539. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1540. }
  1541. }
  1542. }
  1543. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1544. {
  1545. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1546. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1547. union hal_tx_bank_config *bank_config;
  1548. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1549. return;
  1550. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1551. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1552. be_vdev->bank_id);
  1553. }
  1554. #endif
  1555. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1556. defined(WLAN_MCAST_MLO)
  1557. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1558. struct dp_vdev_be *be_vdev,
  1559. cdp_config_param_type val)
  1560. {
  1561. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1562. be_vdev->vdev.pdev->soc);
  1563. hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
  1564. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  1565. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1566. if (be_vdev->mcast_primary) {
  1567. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1568. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1569. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
  1570. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1571. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1572. dp_tx_mcast_mlo_reinject_routing_set,
  1573. (void *)&be_vdev->mcast_primary);
  1574. } else {
  1575. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1576. HAL_TX_MCAST_CTRL_DROP);
  1577. }
  1578. }
  1579. #else
  1580. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1581. struct dp_vdev_be *be_vdev,
  1582. cdp_config_param_type val)
  1583. {
  1584. }
  1585. #endif
  1586. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1587. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1588. uint8_t tx_ring_id,
  1589. uint8_t bm_id)
  1590. {
  1591. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1592. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1593. bm_id);
  1594. }
  1595. #else
  1596. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1597. uint8_t tx_ring_id,
  1598. uint8_t bm_id)
  1599. {
  1600. }
  1601. #endif
  1602. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1603. struct dp_vdev *vdev,
  1604. enum cdp_vdev_param_type param,
  1605. cdp_config_param_type val)
  1606. {
  1607. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1608. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1609. switch (param) {
  1610. case CDP_TX_ENCAP_TYPE:
  1611. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1612. case CDP_UPDATE_TDLS_FLAGS:
  1613. dp_tx_update_bank_profile(be_soc, be_vdev);
  1614. break;
  1615. case CDP_ENABLE_CIPHER:
  1616. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1617. dp_tx_update_bank_profile(be_soc, be_vdev);
  1618. break;
  1619. case CDP_SET_MCAST_VDEV:
  1620. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1621. break;
  1622. default:
  1623. dp_warn("invalid param %d", param);
  1624. break;
  1625. }
  1626. return QDF_STATUS_SUCCESS;
  1627. }
  1628. #ifdef WLAN_FEATURE_11BE_MLO
  1629. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1630. static inline void
  1631. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1632. {
  1633. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1634. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1635. /*
  1636. * Double the peers since we use ML indication bit
  1637. * alongwith peer_id to find peers.
  1638. */
  1639. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1640. }
  1641. #else
  1642. static inline void
  1643. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1644. {
  1645. soc->max_peer_id =
  1646. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1647. }
  1648. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1649. #else
  1650. static inline void
  1651. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1652. {
  1653. soc->max_peer_id = soc->max_peers;
  1654. }
  1655. #endif /* WLAN_FEATURE_11BE_MLO */
  1656. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1657. {
  1658. if (soc->host_ast_db_enable)
  1659. dp_peer_ast_hash_detach(soc);
  1660. }
  1661. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1662. {
  1663. QDF_STATUS status;
  1664. if (soc->host_ast_db_enable) {
  1665. status = dp_peer_ast_hash_attach(soc);
  1666. if (QDF_IS_STATUS_ERROR(status))
  1667. return status;
  1668. }
  1669. dp_soc_max_peer_id_set(soc);
  1670. return QDF_STATUS_SUCCESS;
  1671. }
  1672. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1673. uint8_t *dest_mac,
  1674. uint8_t vdev_id)
  1675. {
  1676. struct dp_peer *peer = NULL;
  1677. struct dp_peer *tgt_peer = NULL;
  1678. struct dp_ast_entry *ast_entry = NULL;
  1679. uint16_t peer_id;
  1680. qdf_spin_lock_bh(&soc->ast_lock);
  1681. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  1682. if (!ast_entry) {
  1683. qdf_spin_unlock_bh(&soc->ast_lock);
  1684. dp_err("NULL ast entry");
  1685. return NULL;
  1686. }
  1687. peer_id = ast_entry->peer_id;
  1688. qdf_spin_unlock_bh(&soc->ast_lock);
  1689. if (peer_id == HTT_INVALID_PEER)
  1690. return NULL;
  1691. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  1692. if (!peer) {
  1693. dp_err("NULL peer for peer_id:%d", peer_id);
  1694. return NULL;
  1695. }
  1696. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1697. /*
  1698. * Once tgt_peer is obtained,
  1699. * release the ref taken for original peer.
  1700. */
  1701. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  1702. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  1703. return tgt_peer;
  1704. }
  1705. #ifdef WLAN_FEATURE_11BE_MLO
  1706. #ifdef WLAN_MCAST_MLO
  1707. static inline void
  1708. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1709. {
  1710. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1711. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1712. }
  1713. #else /* WLAN_MCAST_MLO */
  1714. static inline void
  1715. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1716. {
  1717. }
  1718. #endif /* WLAN_MCAST_MLO */
  1719. #ifdef WLAN_MLO_MULTI_CHIP
  1720. static inline void
  1721. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  1722. {
  1723. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  1724. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  1725. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  1726. }
  1727. #else
  1728. static inline void
  1729. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  1730. {
  1731. }
  1732. #endif
  1733. static inline void
  1734. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1735. {
  1736. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1737. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  1738. arch_ops->mlo_peer_find_hash_detach =
  1739. dp_mlo_peer_find_hash_detach_wrapper;
  1740. arch_ops->mlo_peer_find_hash_attach =
  1741. dp_mlo_peer_find_hash_attach_wrapper;
  1742. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1743. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1744. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1745. }
  1746. #else /* WLAN_FEATURE_11BE_MLO */
  1747. static inline void
  1748. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1749. {
  1750. }
  1751. #endif /* WLAN_FEATURE_11BE_MLO */
  1752. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  1753. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  1754. #define DP_LMAC_PEER_ID_MSB_MLO 3
  1755. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1756. struct cdp_peer_setup_info *setup_info,
  1757. enum cdp_host_reo_dest_ring *reo_dest,
  1758. bool *hash_based,
  1759. uint8_t *lmac_peer_id_msb)
  1760. {
  1761. struct dp_soc *soc = vdev->pdev->soc;
  1762. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1763. if (!be_soc->mlo_enabled)
  1764. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1765. hash_based);
  1766. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1767. *reo_dest = vdev->pdev->reo_dest;
  1768. /* Not a ML link peer use non-mlo */
  1769. if (!setup_info) {
  1770. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1771. return;
  1772. }
  1773. /* For STA ML VAP we do not have num links info at this point
  1774. * use MLO case always
  1775. */
  1776. if (vdev->opmode == wlan_op_mode_sta) {
  1777. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1778. return;
  1779. }
  1780. /* For AP ML VAP consider the peer as ML only it associates with
  1781. * multiple links
  1782. */
  1783. if (setup_info->num_links == 1) {
  1784. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1785. return;
  1786. }
  1787. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1788. }
  1789. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1790. uint32_t *remap0,
  1791. uint32_t *remap1,
  1792. uint32_t *remap2)
  1793. {
  1794. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1795. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  1796. uint32_t reo_mlo_config =
  1797. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  1798. if (!be_soc->mlo_enabled)
  1799. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1800. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1801. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  1802. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1803. return true;
  1804. }
  1805. #else
  1806. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1807. struct cdp_peer_setup_info *setup_info,
  1808. enum cdp_host_reo_dest_ring *reo_dest,
  1809. bool *hash_based,
  1810. uint8_t *lmac_peer_id_msb)
  1811. {
  1812. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1813. }
  1814. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1815. uint32_t *remap0,
  1816. uint32_t *remap1,
  1817. uint32_t *remap2)
  1818. {
  1819. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1820. }
  1821. #endif
  1822. #ifdef IPA_OFFLOAD
  1823. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  1824. {
  1825. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1826. return be_soc->ipa_bank_id;
  1827. }
  1828. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  1829. {
  1830. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  1831. }
  1832. #else /* !IPA_OFFLOAD */
  1833. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  1834. {
  1835. }
  1836. #endif /* IPA_OFFLOAD */
  1837. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1838. {
  1839. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1840. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1841. arch_ops->dp_rx_process = dp_rx_process_be;
  1842. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  1843. arch_ops->tx_comp_get_params_from_hal_desc =
  1844. dp_tx_comp_get_params_from_hal_desc_be;
  1845. arch_ops->dp_tx_process_htt_completion =
  1846. dp_tx_process_htt_completion_be;
  1847. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1848. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1849. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1850. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1851. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1852. dp_wbm_get_rx_desc_from_hal_desc_be;
  1853. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  1854. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  1855. #endif
  1856. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1857. #ifdef WIFI_MONITOR_SUPPORT
  1858. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1859. #endif
  1860. arch_ops->dp_rx_desc_cookie_2_va =
  1861. dp_rx_desc_cookie_2_va_be;
  1862. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1863. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  1864. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1865. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1866. arch_ops->txrx_soc_init = dp_soc_init_be;
  1867. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1868. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1869. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1870. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1871. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1872. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1873. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1874. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1875. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1876. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  1877. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1878. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1879. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1880. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1881. dp_rx_peer_metadata_peer_id_get_be;
  1882. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1883. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1884. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1885. dp_initialize_arch_ops_be_mlo(arch_ops);
  1886. arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
  1887. arch_ops->dp_peer_rx_reorder_queue_setup =
  1888. dp_peer_rx_reorder_queue_setup_be;
  1889. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1890. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  1891. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1892. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  1893. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  1894. dp_reconfig_tx_vdev_mcast_ctrl_be;
  1895. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  1896. #endif
  1897. #ifdef WLAN_SUPPORT_PPEDS
  1898. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  1899. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  1900. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  1901. #else
  1902. arch_ops->dp_txrx_ppeds_rings_status = NULL;
  1903. arch_ops->txrx_soc_ppeds_start = NULL;
  1904. arch_ops->txrx_soc_ppeds_stop = NULL;
  1905. #endif
  1906. dp_init_near_full_arch_ops_be(arch_ops);
  1907. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  1908. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  1909. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  1910. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1911. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1912. dp_initialize_arch_ops_be_ipa(arch_ops);
  1913. }