wcd937x.c 98 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include <asoc/msm-cdc-supply.h>
  23. #include "wcd937x-registers.h"
  24. #include "wcd937x.h"
  25. #include "internal.h"
  26. #include "asoc/bolero-slave-internal.h"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. #define NUM_ATTEMPTS 5
  35. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  36. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  37. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  38. SNDRV_PCM_RATE_384000)
  39. /* Fractional Rates */
  40. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  41. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  42. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  43. SNDRV_PCM_FMTBIT_S24_LE |\
  44. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  45. enum {
  46. CODEC_TX = 0,
  47. CODEC_RX,
  48. };
  49. enum {
  50. ALLOW_BUCK_DISABLE,
  51. HPH_COMP_DELAY,
  52. HPH_PA_DELAY,
  53. AMIC2_BCS_ENABLE,
  54. };
  55. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  56. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  57. static int wcd937x_handle_post_irq(void *data);
  58. static int wcd937x_reset(struct device *dev);
  59. static int wcd937x_reset_low(struct device *dev);
  60. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  61. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  81. };
  82. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  83. .name = "wcd937x",
  84. .irqs = wcd937x_irqs,
  85. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  86. .num_regs = 3,
  87. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  88. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  89. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  90. .use_ack = 1,
  91. #if IS_ENABLED(CONFIG_AUDIO_QGKI)
  92. .clear_ack = 1,
  93. #endif
  94. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  95. .runtime_pm = false,
  96. .handle_post_irq = wcd937x_handle_post_irq,
  97. .irq_drv_data = NULL,
  98. };
  99. static struct snd_soc_dai_driver wcd937x_dai[] = {
  100. {
  101. .name = "wcd937x_cdc",
  102. .playback = {
  103. .stream_name = "WCD937X_AIF Playback",
  104. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  105. .formats = WCD937X_FORMATS,
  106. .rate_max = 384000,
  107. .rate_min = 8000,
  108. .channels_min = 1,
  109. .channels_max = 4,
  110. },
  111. .capture = {
  112. .stream_name = "WCD937X_AIF Capture",
  113. .rates = WCD937X_RATES,
  114. .formats = WCD937X_FORMATS,
  115. .rate_max = 192000,
  116. .rate_min = 8000,
  117. .channels_min = 1,
  118. .channels_max = 4,
  119. },
  120. },
  121. };
  122. static int wcd937x_handle_post_irq(void *data)
  123. {
  124. struct wcd937x_priv *wcd937x = data;
  125. u32 status1 = 0, status2 = 0, status3 = 0;
  126. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  127. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  128. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  129. wcd937x->tx_swr_dev->slave_irq_pending =
  130. ((status1 || status2 || status3) ? true : false);
  131. return IRQ_HANDLED;
  132. }
  133. static int wcd937x_init_reg(struct snd_soc_component *component)
  134. {
  135. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  136. 0x0E, 0x0E);
  137. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  138. 0x80, 0x80);
  139. usleep_range(1000, 1010);
  140. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  141. 0x40, 0x40);
  142. usleep_range(1000, 1010);
  143. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  144. 0x10, 0x00);
  145. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  146. 0xF0, 0x80);
  147. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  148. 0x80, 0x80);
  149. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  150. 0x40, 0x40);
  151. usleep_range(10000, 10010);
  152. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  153. 0x40, 0x00);
  154. snd_soc_component_update_bits(component,
  155. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  156. 0xFF, 0xD9);
  157. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  158. 0xFF, 0xFA);
  159. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  160. 0xFF, 0xFA);
  161. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  162. 0xFF, 0xFA);
  163. return 0;
  164. }
  165. static int wcd937x_set_port_params(struct snd_soc_component *component,
  166. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  167. u8 *ch_mask, u32 *ch_rate,
  168. u8 *port_type, u8 path)
  169. {
  170. int i, j;
  171. u8 num_ports = 0;
  172. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  173. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  174. switch (path) {
  175. case CODEC_RX:
  176. map = &wcd937x->rx_port_mapping;
  177. num_ports = wcd937x->num_rx_ports;
  178. break;
  179. case CODEC_TX:
  180. map = &wcd937x->tx_port_mapping;
  181. num_ports = wcd937x->num_tx_ports;
  182. break;
  183. default:
  184. dev_err(component->dev, "%s Invalid path selected %u\n",
  185. __func__, path);
  186. return -EINVAL;
  187. }
  188. for (i = 0; i <= num_ports; i++) {
  189. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  190. if ((*map)[i][j].slave_port_type == slv_prt_type)
  191. goto found;
  192. }
  193. }
  194. found:
  195. if (i > num_ports || j == MAX_CH_PER_PORT) {
  196. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  197. __func__, slv_prt_type);
  198. return -EINVAL;
  199. }
  200. *port_id = i;
  201. *num_ch = (*map)[i][j].num_ch;
  202. *ch_mask = (*map)[i][j].ch_mask;
  203. *ch_rate = (*map)[i][j].ch_rate;
  204. *port_type = (*map)[i][j].master_port_type;
  205. return 0;
  206. }
  207. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  208. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  209. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  210. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  211. static int wcd937x_parse_port_params(struct device *dev,
  212. char *prop, u8 path)
  213. {
  214. u32 *dt_array, map_size, max_uc;
  215. int ret = 0;
  216. u32 cnt = 0;
  217. u32 i, j;
  218. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  219. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  220. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  221. switch (path) {
  222. case CODEC_TX:
  223. map = &wcd937x->tx_port_params;
  224. map_uc = &wcd937x->swr_tx_port_params;
  225. break;
  226. default:
  227. ret = -EINVAL;
  228. goto err_port_map;
  229. }
  230. if (!of_find_property(dev->of_node, prop,
  231. &map_size)) {
  232. dev_err(dev, "missing port mapping prop %s\n", prop);
  233. ret = -EINVAL;
  234. goto err_port_map;
  235. }
  236. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  237. if (max_uc != SWR_UC_MAX) {
  238. dev_err(dev, "%s: port params not provided for all usecases\n",
  239. __func__);
  240. ret = -EINVAL;
  241. goto err_port_map;
  242. }
  243. dt_array = kzalloc(map_size, GFP_KERNEL);
  244. if (!dt_array) {
  245. ret = -ENOMEM;
  246. goto err_alloc;
  247. }
  248. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  249. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  250. if (ret) {
  251. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  252. __func__, prop);
  253. goto err_pdata_fail;
  254. }
  255. for (i = 0; i < max_uc; i++) {
  256. for (j = 0; j < SWR_NUM_PORTS; j++) {
  257. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  258. (*map)[i][j].offset1 = dt_array[cnt];
  259. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  260. }
  261. (*map_uc)[i].pp = &(*map)[i][0];
  262. }
  263. kfree(dt_array);
  264. return 0;
  265. err_pdata_fail:
  266. kfree(dt_array);
  267. err_alloc:
  268. err_port_map:
  269. return ret;
  270. }
  271. static int wcd937x_parse_port_mapping(struct device *dev,
  272. char *prop, u8 path)
  273. {
  274. u32 *dt_array, map_size, map_length;
  275. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  276. u32 slave_port_type, master_port_type;
  277. u32 i, ch_iter = 0;
  278. int ret = 0;
  279. u8 *num_ports = NULL;
  280. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  281. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  282. switch (path) {
  283. case CODEC_RX:
  284. map = &wcd937x->rx_port_mapping;
  285. num_ports = &wcd937x->num_rx_ports;
  286. break;
  287. case CODEC_TX:
  288. map = &wcd937x->tx_port_mapping;
  289. num_ports = &wcd937x->num_tx_ports;
  290. break;
  291. default:
  292. dev_err(dev, "%s Invalid path selected %u\n",
  293. __func__, path);
  294. return -EINVAL;
  295. }
  296. if (!of_find_property(dev->of_node, prop,
  297. &map_size)) {
  298. dev_err(dev, "missing port mapping prop %s\n", prop);
  299. ret = -EINVAL;
  300. goto err;
  301. }
  302. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  303. dt_array = kzalloc(map_size, GFP_KERNEL);
  304. if (!dt_array) {
  305. ret = -ENOMEM;
  306. goto err;
  307. }
  308. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  309. NUM_SWRS_DT_PARAMS * map_length);
  310. if (ret) {
  311. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  312. __func__, prop);
  313. ret = -EINVAL;
  314. goto err_pdata_fail;
  315. }
  316. for (i = 0; i < map_length; i++) {
  317. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  318. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  319. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  320. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  321. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  322. if (port_num != old_port_num)
  323. ch_iter = 0;
  324. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  325. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  326. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  327. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  328. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  329. old_port_num = port_num;
  330. }
  331. *num_ports = port_num;
  332. kfree(dt_array);
  333. return 0;
  334. err_pdata_fail:
  335. kfree(dt_array);
  336. err:
  337. return ret;
  338. }
  339. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  340. u8 slv_port_type, u8 enable)
  341. {
  342. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  343. u8 port_id;
  344. u8 num_ch;
  345. u8 ch_mask;
  346. u32 ch_rate;
  347. u8 ch_type = 0;
  348. int slave_ch_idx;
  349. u8 num_port = 1;
  350. int ret = 0;
  351. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  352. &num_ch, &ch_mask, &ch_rate,
  353. &ch_type, CODEC_TX);
  354. if (ret)
  355. return ret;
  356. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  357. if (slave_ch_idx != -EINVAL)
  358. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  359. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  360. __func__, slave_ch_idx, ch_type);
  361. if (enable)
  362. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  363. num_port, &ch_mask, &ch_rate,
  364. &num_ch, &ch_type);
  365. else
  366. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  367. num_port, &ch_mask, &ch_type);
  368. return ret;
  369. }
  370. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  371. u8 slv_port_type, u8 enable)
  372. {
  373. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  374. u8 port_id;
  375. u8 num_ch;
  376. u8 ch_mask;
  377. u32 ch_rate;
  378. u8 port_type;
  379. u8 num_port = 1;
  380. int ret = 0;
  381. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  382. &num_ch, &ch_mask, &ch_rate,
  383. &port_type, CODEC_RX);
  384. if (ret)
  385. return ret;
  386. if (enable)
  387. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  388. num_port, &ch_mask, &ch_rate,
  389. &num_ch, &port_type);
  390. else
  391. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  392. num_port, &ch_mask, &port_type);
  393. return ret;
  394. }
  395. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  396. {
  397. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  398. if (wcd937x->rx_clk_cnt == 0) {
  399. snd_soc_component_update_bits(component,
  400. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  401. snd_soc_component_update_bits(component,
  402. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  403. snd_soc_component_update_bits(component,
  404. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  405. snd_soc_component_update_bits(component,
  406. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  407. snd_soc_component_update_bits(component,
  408. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  409. snd_soc_component_update_bits(component,
  410. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  411. snd_soc_component_update_bits(component,
  412. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  413. }
  414. wcd937x->rx_clk_cnt++;
  415. return 0;
  416. }
  417. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  418. {
  419. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  420. if (wcd937x->rx_clk_cnt == 0) {
  421. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  422. return 0;
  423. }
  424. wcd937x->rx_clk_cnt--;
  425. if (wcd937x->rx_clk_cnt == 0) {
  426. snd_soc_component_update_bits(component,
  427. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  428. snd_soc_component_update_bits(component,
  429. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  430. 0x02, 0x00);
  431. snd_soc_component_update_bits(component,
  432. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  433. 0x01, 0x00);
  434. }
  435. return 0;
  436. }
  437. /*
  438. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  439. * @component: handle to snd_soc_component *
  440. *
  441. * return wcd937x_mbhc handle or error code in case of failure
  442. */
  443. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  444. {
  445. struct wcd937x_priv *wcd937x;
  446. if (!component) {
  447. pr_err("%s: Invalid params, NULL component\n", __func__);
  448. return NULL;
  449. }
  450. wcd937x = snd_soc_component_get_drvdata(component);
  451. if (!wcd937x) {
  452. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  453. return NULL;
  454. }
  455. return wcd937x->mbhc;
  456. }
  457. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  458. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  459. struct snd_kcontrol *kcontrol,
  460. int event)
  461. {
  462. struct snd_soc_component *component =
  463. snd_soc_dapm_to_component(w->dapm);
  464. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  465. int hph_mode = wcd937x->hph_mode;
  466. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  467. w->name, event);
  468. switch (event) {
  469. case SND_SOC_DAPM_PRE_PMU:
  470. wcd937x_rx_clk_enable(component);
  471. snd_soc_component_update_bits(component,
  472. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  473. 0x01, 0x01);
  474. snd_soc_component_update_bits(component,
  475. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  476. 0x04, 0x04);
  477. snd_soc_component_update_bits(component,
  478. WCD937X_HPH_RDAC_CLK_CTL1,
  479. 0x80, 0x00);
  480. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  481. break;
  482. case SND_SOC_DAPM_POST_PMU:
  483. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  484. snd_soc_component_update_bits(component,
  485. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  486. 0x0F, 0x02);
  487. else if (hph_mode == CLS_H_LOHIFI)
  488. snd_soc_component_update_bits(component,
  489. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  490. 0x0F, 0x06);
  491. if (wcd937x->comp1_enable) {
  492. snd_soc_component_update_bits(component,
  493. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  494. 0x02, 0x02);
  495. snd_soc_component_update_bits(component,
  496. WCD937X_HPH_L_EN, 0x20, 0x00);
  497. if (wcd937x->comp2_enable) {
  498. snd_soc_component_update_bits(component,
  499. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  500. 0x01, 0x01);
  501. snd_soc_component_update_bits(component,
  502. WCD937X_HPH_R_EN, 0x20, 0x00);
  503. }
  504. /*
  505. * 5ms sleep is required after COMP is enabled as per
  506. * HW requirement
  507. */
  508. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  509. usleep_range(5000, 5100);
  510. clear_bit(HPH_COMP_DELAY,
  511. &wcd937x->status_mask);
  512. }
  513. } else {
  514. snd_soc_component_update_bits(component,
  515. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  516. 0x02, 0x00);
  517. snd_soc_component_update_bits(component,
  518. WCD937X_HPH_L_EN, 0x20, 0x20);
  519. }
  520. snd_soc_component_update_bits(component,
  521. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. snd_soc_component_update_bits(component,
  525. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  526. 0x0F, 0x01);
  527. break;
  528. }
  529. return 0;
  530. }
  531. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  532. struct snd_kcontrol *kcontrol,
  533. int event)
  534. {
  535. struct snd_soc_component *component =
  536. snd_soc_dapm_to_component(w->dapm);
  537. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  538. int hph_mode = wcd937x->hph_mode;
  539. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  540. w->name, event);
  541. switch (event) {
  542. case SND_SOC_DAPM_PRE_PMU:
  543. wcd937x_rx_clk_enable(component);
  544. snd_soc_component_update_bits(component,
  545. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  546. snd_soc_component_update_bits(component,
  547. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  548. snd_soc_component_update_bits(component,
  549. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  550. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  551. break;
  552. case SND_SOC_DAPM_POST_PMU:
  553. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  554. snd_soc_component_update_bits(component,
  555. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  556. 0x0F, 0x02);
  557. else if (hph_mode == CLS_H_LOHIFI)
  558. snd_soc_component_update_bits(component,
  559. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  560. 0x0F, 0x06);
  561. if (wcd937x->comp2_enable) {
  562. snd_soc_component_update_bits(component,
  563. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  564. 0x01, 0x01);
  565. snd_soc_component_update_bits(component,
  566. WCD937X_HPH_R_EN, 0x20, 0x00);
  567. if (wcd937x->comp1_enable) {
  568. snd_soc_component_update_bits(component,
  569. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  570. 0x02, 0x02);
  571. snd_soc_component_update_bits(component,
  572. WCD937X_HPH_L_EN, 0x20, 0x00);
  573. }
  574. /*
  575. * 5ms sleep is required after COMP is enabled as per
  576. * HW requirement
  577. */
  578. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  579. usleep_range(5000, 5100);
  580. clear_bit(HPH_COMP_DELAY,
  581. &wcd937x->status_mask);
  582. }
  583. } else {
  584. snd_soc_component_update_bits(component,
  585. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  586. 0x01, 0x00);
  587. snd_soc_component_update_bits(component,
  588. WCD937X_HPH_R_EN, 0x20, 0x20);
  589. }
  590. snd_soc_component_update_bits(component,
  591. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  592. break;
  593. case SND_SOC_DAPM_POST_PMD:
  594. snd_soc_component_update_bits(component,
  595. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  596. 0x0F, 0x01);
  597. break;
  598. }
  599. return 0;
  600. }
  601. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  602. struct snd_kcontrol *kcontrol,
  603. int event)
  604. {
  605. struct snd_soc_component *component =
  606. snd_soc_dapm_to_component(w->dapm);
  607. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  608. int hph_mode = wcd937x->hph_mode;
  609. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  610. w->name, event);
  611. switch (event) {
  612. case SND_SOC_DAPM_PRE_PMU:
  613. wcd937x_rx_clk_enable(component);
  614. snd_soc_component_update_bits(component,
  615. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  616. 0x04, 0x04);
  617. snd_soc_component_update_bits(component,
  618. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  619. 0x01, 0x01);
  620. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  621. snd_soc_component_update_bits(component,
  622. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  623. 0x0F, 0x02);
  624. else if (hph_mode == CLS_H_LOHIFI)
  625. snd_soc_component_update_bits(component,
  626. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  627. 0x0F, 0x06);
  628. if (wcd937x->comp1_enable)
  629. snd_soc_component_update_bits(component,
  630. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  631. 0x02, 0x02);
  632. usleep_range(5000, 5010);
  633. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  634. 0x04, 0x00);
  635. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  636. WCD_CLSH_EVENT_PRE_DAC,
  637. WCD_CLSH_STATE_EAR,
  638. hph_mode);
  639. break;
  640. case SND_SOC_DAPM_POST_PMD:
  641. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  642. hph_mode == CLS_H_HIFI)
  643. snd_soc_component_update_bits(component,
  644. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  645. 0x0F, 0x01);
  646. if (wcd937x->comp1_enable)
  647. snd_soc_component_update_bits(component,
  648. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  649. 0x02, 0x00);
  650. break;
  651. };
  652. return 0;
  653. }
  654. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  655. struct snd_kcontrol *kcontrol,
  656. int event)
  657. {
  658. struct snd_soc_component *component =
  659. snd_soc_dapm_to_component(w->dapm);
  660. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  661. int hph_mode = wcd937x->hph_mode;
  662. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  663. w->name, event);
  664. switch (event) {
  665. case SND_SOC_DAPM_PRE_PMU:
  666. wcd937x_rx_clk_enable(component);
  667. snd_soc_component_update_bits(component,
  668. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  669. 0x04, 0x04);
  670. snd_soc_component_update_bits(component,
  671. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  672. 0x04, 0x04);
  673. snd_soc_component_update_bits(component,
  674. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  675. 0x01, 0x01);
  676. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  677. WCD_CLSH_EVENT_PRE_DAC,
  678. WCD_CLSH_STATE_AUX,
  679. hph_mode);
  680. break;
  681. case SND_SOC_DAPM_POST_PMD:
  682. snd_soc_component_update_bits(component,
  683. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  684. 0x04, 0x00);
  685. break;
  686. };
  687. return 0;
  688. }
  689. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  690. struct snd_kcontrol *kcontrol,
  691. int event)
  692. {
  693. struct snd_soc_component *component =
  694. snd_soc_dapm_to_component(w->dapm);
  695. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  696. int ret = 0;
  697. int hph_mode = wcd937x->hph_mode;
  698. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  699. w->name, event);
  700. switch (event) {
  701. case SND_SOC_DAPM_PRE_PMU:
  702. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  703. wcd937x->rx_swr_dev->dev_num,
  704. true);
  705. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  706. WCD_CLSH_EVENT_PRE_DAC,
  707. WCD_CLSH_STATE_HPHR,
  708. hph_mode);
  709. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  710. 0x10, 0x10);
  711. usleep_range(100, 110);
  712. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  713. snd_soc_component_update_bits(component,
  714. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  715. break;
  716. case SND_SOC_DAPM_POST_PMU:
  717. /*
  718. * 7ms sleep is required after PA is enabled as per
  719. * HW requirement. If compander is disabled, then
  720. * 20ms delay is required.
  721. */
  722. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  723. if (!wcd937x->comp2_enable)
  724. usleep_range(20000, 20100);
  725. else
  726. usleep_range(7000, 7100);
  727. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  728. }
  729. snd_soc_component_update_bits(component,
  730. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  731. 0x02, 0x02);
  732. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  733. snd_soc_component_update_bits(component,
  734. WCD937X_ANA_RX_SUPPLIES,
  735. 0x02, 0x02);
  736. if (wcd937x->update_wcd_event)
  737. wcd937x->update_wcd_event(wcd937x->handle,
  738. SLV_BOLERO_EVT_RX_MUTE,
  739. (WCD_RX2 << 0x10));
  740. wcd_enable_irq(&wcd937x->irq_info,
  741. WCD937X_IRQ_HPHR_PDM_WD_INT);
  742. break;
  743. case SND_SOC_DAPM_PRE_PMD:
  744. wcd_disable_irq(&wcd937x->irq_info,
  745. WCD937X_IRQ_HPHR_PDM_WD_INT);
  746. if (wcd937x->update_wcd_event)
  747. wcd937x->update_wcd_event(wcd937x->handle,
  748. SLV_BOLERO_EVT_RX_MUTE,
  749. (WCD_RX2 << 0x10 | 0x1));
  750. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  751. WCD_EVENT_PRE_HPHR_PA_OFF,
  752. &wcd937x->mbhc->wcd_mbhc);
  753. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  754. break;
  755. case SND_SOC_DAPM_POST_PMD:
  756. /*
  757. * 7ms sleep is required after PA is disabled as per
  758. * HW requirement. If compander is disabled, then
  759. * 20ms delay is required.
  760. */
  761. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  762. if (!wcd937x->comp2_enable)
  763. usleep_range(20000, 20100);
  764. else
  765. usleep_range(7000, 7100);
  766. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  767. }
  768. snd_soc_component_update_bits(component,
  769. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  770. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  771. WCD_EVENT_POST_HPHR_PA_OFF,
  772. &wcd937x->mbhc->wcd_mbhc);
  773. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  774. 0x10, 0x00);
  775. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  776. WCD_CLSH_EVENT_POST_PA,
  777. WCD_CLSH_STATE_HPHR,
  778. hph_mode);
  779. break;
  780. };
  781. return ret;
  782. }
  783. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  784. struct snd_kcontrol *kcontrol,
  785. int event)
  786. {
  787. struct snd_soc_component *component =
  788. snd_soc_dapm_to_component(w->dapm);
  789. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  790. int ret = 0;
  791. int hph_mode = wcd937x->hph_mode;
  792. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  793. w->name, event);
  794. switch (event) {
  795. case SND_SOC_DAPM_PRE_PMU:
  796. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  797. wcd937x->rx_swr_dev->dev_num,
  798. true);
  799. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  800. WCD_CLSH_EVENT_PRE_DAC,
  801. WCD_CLSH_STATE_HPHL,
  802. hph_mode);
  803. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  804. 0x20, 0x20);
  805. usleep_range(100, 110);
  806. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  807. snd_soc_component_update_bits(component,
  808. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  809. break;
  810. case SND_SOC_DAPM_POST_PMU:
  811. /*
  812. * 7ms sleep is required after PA is enabled as per
  813. * HW requirement. If compander is disabled, then
  814. * 20ms delay is required.
  815. */
  816. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  817. if (!wcd937x->comp1_enable)
  818. usleep_range(20000, 20100);
  819. else
  820. usleep_range(7000, 7100);
  821. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  822. }
  823. snd_soc_component_update_bits(component,
  824. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  825. 0x02, 0x02);
  826. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  827. snd_soc_component_update_bits(component,
  828. WCD937X_ANA_RX_SUPPLIES,
  829. 0x02, 0x02);
  830. if (wcd937x->update_wcd_event)
  831. wcd937x->update_wcd_event(wcd937x->handle,
  832. SLV_BOLERO_EVT_RX_MUTE,
  833. (WCD_RX1 << 0x10));
  834. wcd_enable_irq(&wcd937x->irq_info,
  835. WCD937X_IRQ_HPHL_PDM_WD_INT);
  836. break;
  837. case SND_SOC_DAPM_PRE_PMD:
  838. wcd_disable_irq(&wcd937x->irq_info,
  839. WCD937X_IRQ_HPHL_PDM_WD_INT);
  840. if (wcd937x->update_wcd_event)
  841. wcd937x->update_wcd_event(wcd937x->handle,
  842. SLV_BOLERO_EVT_RX_MUTE,
  843. (WCD_RX1 << 0x10 | 0x1));
  844. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  845. WCD_EVENT_PRE_HPHL_PA_OFF,
  846. &wcd937x->mbhc->wcd_mbhc);
  847. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  848. break;
  849. case SND_SOC_DAPM_POST_PMD:
  850. /*
  851. * 7ms sleep is required after PA is disabled as per
  852. * HW requirement. If compander is disabled, then
  853. * 20ms delay is required.
  854. */
  855. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  856. if (!wcd937x->comp1_enable)
  857. usleep_range(20000, 20100);
  858. else
  859. usleep_range(7000, 7100);
  860. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  861. }
  862. snd_soc_component_update_bits(component,
  863. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  864. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  865. WCD_EVENT_POST_HPHL_PA_OFF,
  866. &wcd937x->mbhc->wcd_mbhc);
  867. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  868. 0x20, 0x00);
  869. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  870. WCD_CLSH_EVENT_POST_PA,
  871. WCD_CLSH_STATE_HPHL,
  872. hph_mode);
  873. break;
  874. };
  875. return ret;
  876. }
  877. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  878. struct snd_kcontrol *kcontrol,
  879. int event)
  880. {
  881. struct snd_soc_component *component =
  882. snd_soc_dapm_to_component(w->dapm);
  883. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  884. int hph_mode = wcd937x->hph_mode;
  885. int ret = 0;
  886. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  887. w->name, event);
  888. switch (event) {
  889. case SND_SOC_DAPM_PRE_PMU:
  890. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  891. wcd937x->rx_swr_dev->dev_num,
  892. true);
  893. snd_soc_component_update_bits(component,
  894. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  895. break;
  896. case SND_SOC_DAPM_POST_PMU:
  897. usleep_range(1000, 1010);
  898. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  899. snd_soc_component_update_bits(component,
  900. WCD937X_ANA_RX_SUPPLIES,
  901. 0x02, 0x02);
  902. if (wcd937x->update_wcd_event)
  903. wcd937x->update_wcd_event(wcd937x->handle,
  904. SLV_BOLERO_EVT_RX_MUTE,
  905. (WCD_RX3 << 0x10));
  906. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  907. break;
  908. case SND_SOC_DAPM_PRE_PMD:
  909. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  910. if (wcd937x->update_wcd_event)
  911. wcd937x->update_wcd_event(wcd937x->handle,
  912. SLV_BOLERO_EVT_RX_MUTE,
  913. (WCD_RX3 << 0x10 | 0x1));
  914. break;
  915. case SND_SOC_DAPM_POST_PMD:
  916. /* Add delay as per hw requirement */
  917. usleep_range(2000, 2010);
  918. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  919. WCD_CLSH_EVENT_POST_PA,
  920. WCD_CLSH_STATE_AUX,
  921. hph_mode);
  922. snd_soc_component_update_bits(component,
  923. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  924. break;
  925. };
  926. return ret;
  927. }
  928. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  929. struct snd_kcontrol *kcontrol,
  930. int event)
  931. {
  932. struct snd_soc_component *component =
  933. snd_soc_dapm_to_component(w->dapm);
  934. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  935. int hph_mode = wcd937x->hph_mode;
  936. int ret = 0;
  937. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  938. w->name, event);
  939. switch (event) {
  940. case SND_SOC_DAPM_PRE_PMU:
  941. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  942. wcd937x->rx_swr_dev->dev_num,
  943. true);
  944. /*
  945. * Enable watchdog interrupt for HPHL or AUX
  946. * depending on mux value
  947. */
  948. wcd937x->ear_rx_path =
  949. snd_soc_component_read(
  950. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  951. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  952. snd_soc_component_update_bits(component,
  953. WCD937X_DIGITAL_PDM_WD_CTL2,
  954. 0x05, 0x05);
  955. else
  956. snd_soc_component_update_bits(component,
  957. WCD937X_DIGITAL_PDM_WD_CTL0,
  958. 0x17, 0x13);
  959. if (!wcd937x->comp1_enable)
  960. snd_soc_component_update_bits(component,
  961. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  962. break;
  963. case SND_SOC_DAPM_POST_PMU:
  964. usleep_range(6000, 6010);
  965. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  966. snd_soc_component_update_bits(component,
  967. WCD937X_ANA_RX_SUPPLIES,
  968. 0x02, 0x02);
  969. if (wcd937x->update_wcd_event)
  970. wcd937x->update_wcd_event(wcd937x->handle,
  971. SLV_BOLERO_EVT_RX_MUTE,
  972. (WCD_RX1 << 0x10));
  973. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  974. wcd_enable_irq(&wcd937x->irq_info,
  975. WCD937X_IRQ_AUX_PDM_WD_INT);
  976. else
  977. wcd_enable_irq(&wcd937x->irq_info,
  978. WCD937X_IRQ_HPHL_PDM_WD_INT);
  979. break;
  980. case SND_SOC_DAPM_PRE_PMD:
  981. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  982. wcd_disable_irq(&wcd937x->irq_info,
  983. WCD937X_IRQ_AUX_PDM_WD_INT);
  984. else
  985. wcd_disable_irq(&wcd937x->irq_info,
  986. WCD937X_IRQ_HPHL_PDM_WD_INT);
  987. if (wcd937x->update_wcd_event)
  988. wcd937x->update_wcd_event(wcd937x->handle,
  989. SLV_BOLERO_EVT_RX_MUTE,
  990. (WCD_RX1 << 0x10 | 0x1));
  991. break;
  992. case SND_SOC_DAPM_POST_PMD:
  993. if (!wcd937x->comp1_enable)
  994. snd_soc_component_update_bits(component,
  995. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  996. usleep_range(7000, 7010);
  997. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  998. WCD_CLSH_EVENT_POST_PA,
  999. WCD_CLSH_STATE_EAR,
  1000. hph_mode);
  1001. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  1002. 0x04, 0x04);
  1003. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1004. snd_soc_component_update_bits(component,
  1005. WCD937X_DIGITAL_PDM_WD_CTL2,
  1006. 0x05, 0x00);
  1007. else
  1008. snd_soc_component_update_bits(component,
  1009. WCD937X_DIGITAL_PDM_WD_CTL0,
  1010. 0x17, 0x00);
  1011. break;
  1012. };
  1013. return ret;
  1014. }
  1015. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  1016. struct snd_kcontrol *kcontrol,
  1017. int event)
  1018. {
  1019. struct snd_soc_component *component =
  1020. snd_soc_dapm_to_component(w->dapm);
  1021. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1022. int mode = wcd937x->hph_mode;
  1023. int ret = 0;
  1024. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1025. w->name, event);
  1026. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1027. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1028. wcd937x_rx_connect_port(component, CLSH,
  1029. SND_SOC_DAPM_EVENT_ON(event));
  1030. }
  1031. if (SND_SOC_DAPM_EVENT_OFF(event))
  1032. ret = swr_slvdev_datapath_control(
  1033. wcd937x->rx_swr_dev,
  1034. wcd937x->rx_swr_dev->dev_num,
  1035. false);
  1036. return ret;
  1037. }
  1038. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  1039. struct snd_kcontrol *kcontrol,
  1040. int event)
  1041. {
  1042. struct snd_soc_component *component =
  1043. snd_soc_dapm_to_component(w->dapm);
  1044. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1045. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1046. w->name, event);
  1047. switch (event) {
  1048. case SND_SOC_DAPM_PRE_PMU:
  1049. wcd937x_rx_connect_port(component, HPH_L, true);
  1050. if (wcd937x->comp1_enable)
  1051. wcd937x_rx_connect_port(component, COMP_L, true);
  1052. break;
  1053. case SND_SOC_DAPM_POST_PMD:
  1054. wcd937x_rx_connect_port(component, HPH_L, false);
  1055. if (wcd937x->comp1_enable)
  1056. wcd937x_rx_connect_port(component, COMP_L, false);
  1057. wcd937x_rx_clk_disable(component);
  1058. snd_soc_component_update_bits(component,
  1059. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1060. 0x01, 0x00);
  1061. break;
  1062. };
  1063. return 0;
  1064. }
  1065. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1066. struct snd_kcontrol *kcontrol, int event)
  1067. {
  1068. struct snd_soc_component *component =
  1069. snd_soc_dapm_to_component(w->dapm);
  1070. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1071. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1072. w->name, event);
  1073. switch (event) {
  1074. case SND_SOC_DAPM_PRE_PMU:
  1075. wcd937x_rx_connect_port(component, HPH_R, true);
  1076. if (wcd937x->comp2_enable)
  1077. wcd937x_rx_connect_port(component, COMP_R, true);
  1078. break;
  1079. case SND_SOC_DAPM_POST_PMD:
  1080. wcd937x_rx_connect_port(component, HPH_R, false);
  1081. if (wcd937x->comp2_enable)
  1082. wcd937x_rx_connect_port(component, COMP_R, false);
  1083. wcd937x_rx_clk_disable(component);
  1084. snd_soc_component_update_bits(component,
  1085. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1086. 0x02, 0x00);
  1087. break;
  1088. };
  1089. return 0;
  1090. }
  1091. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1092. struct snd_kcontrol *kcontrol,
  1093. int event)
  1094. {
  1095. struct snd_soc_component *component =
  1096. snd_soc_dapm_to_component(w->dapm);
  1097. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1098. w->name, event);
  1099. switch (event) {
  1100. case SND_SOC_DAPM_PRE_PMU:
  1101. wcd937x_rx_connect_port(component, LO, true);
  1102. break;
  1103. case SND_SOC_DAPM_POST_PMD:
  1104. wcd937x_rx_connect_port(component, LO, false);
  1105. usleep_range(6000, 6010);
  1106. wcd937x_rx_clk_disable(component);
  1107. snd_soc_component_update_bits(component,
  1108. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1109. break;
  1110. }
  1111. return 0;
  1112. }
  1113. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1114. struct snd_kcontrol *kcontrol,
  1115. int event)
  1116. {
  1117. struct snd_soc_component *component =
  1118. snd_soc_dapm_to_component(w->dapm);
  1119. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1120. u16 dmic_clk_reg;
  1121. s32 *dmic_clk_cnt;
  1122. unsigned int dmic;
  1123. char *wname;
  1124. int ret = 0;
  1125. wname = strpbrk(w->name, "012345");
  1126. if (!wname) {
  1127. dev_err(component->dev, "%s: widget not found\n", __func__);
  1128. return -EINVAL;
  1129. }
  1130. ret = kstrtouint(wname, 10, &dmic);
  1131. if (ret < 0) {
  1132. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1133. __func__);
  1134. return -EINVAL;
  1135. }
  1136. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1137. w->name, event);
  1138. switch (dmic) {
  1139. case 0:
  1140. case 1:
  1141. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1142. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1143. break;
  1144. case 2:
  1145. case 3:
  1146. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1147. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1148. break;
  1149. case 4:
  1150. case 5:
  1151. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1152. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1153. break;
  1154. default:
  1155. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1156. __func__);
  1157. return -EINVAL;
  1158. };
  1159. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1160. __func__, event, dmic, *dmic_clk_cnt);
  1161. switch (event) {
  1162. case SND_SOC_DAPM_PRE_PMU:
  1163. snd_soc_component_update_bits(component,
  1164. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1165. snd_soc_component_update_bits(component,
  1166. dmic_clk_reg, 0x07, 0x02);
  1167. snd_soc_component_update_bits(component,
  1168. dmic_clk_reg, 0x08, 0x08);
  1169. snd_soc_component_update_bits(component,
  1170. dmic_clk_reg, 0x70, 0x20);
  1171. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1172. wcd937x->tx_swr_dev->dev_num,
  1173. true);
  1174. break;
  1175. case SND_SOC_DAPM_POST_PMD:
  1176. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1177. break;
  1178. };
  1179. return 0;
  1180. }
  1181. /*
  1182. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1183. * @micb_mv: micbias in mv
  1184. *
  1185. * return register value converted
  1186. */
  1187. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1188. {
  1189. /* min micbias voltage is 1V and maximum is 2.85V */
  1190. if (micb_mv < 1000 || micb_mv > 2850) {
  1191. pr_err("%s: unsupported micbias voltage\n", __func__);
  1192. return -EINVAL;
  1193. }
  1194. return (micb_mv - 1000) / 50;
  1195. }
  1196. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1197. /*
  1198. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1199. * @component: handle to snd_soc_component *
  1200. * @req_volt: micbias voltage to be set
  1201. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1202. *
  1203. * return 0 if adjustment is success or error code in case of failure
  1204. */
  1205. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1206. int req_volt, int micb_num)
  1207. {
  1208. struct wcd937x_priv *wcd937x =
  1209. snd_soc_component_get_drvdata(component);
  1210. int cur_vout_ctl, req_vout_ctl;
  1211. int micb_reg, micb_val, micb_en;
  1212. int ret = 0;
  1213. switch (micb_num) {
  1214. case MIC_BIAS_1:
  1215. micb_reg = WCD937X_ANA_MICB1;
  1216. break;
  1217. case MIC_BIAS_2:
  1218. micb_reg = WCD937X_ANA_MICB2;
  1219. break;
  1220. case MIC_BIAS_3:
  1221. micb_reg = WCD937X_ANA_MICB3;
  1222. break;
  1223. default:
  1224. return -EINVAL;
  1225. }
  1226. mutex_lock(&wcd937x->micb_lock);
  1227. /*
  1228. * If requested micbias voltage is same as current micbias
  1229. * voltage, then just return. Otherwise, adjust voltage as
  1230. * per requested value. If micbias is already enabled, then
  1231. * to avoid slow micbias ramp-up or down enable pull-up
  1232. * momentarily, change the micbias value and then re-enable
  1233. * micbias.
  1234. */
  1235. micb_val = snd_soc_component_read(component, micb_reg);
  1236. micb_en = (micb_val & 0xC0) >> 6;
  1237. cur_vout_ctl = micb_val & 0x3F;
  1238. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1239. if (req_vout_ctl < 0) {
  1240. ret = -EINVAL;
  1241. goto exit;
  1242. }
  1243. if (cur_vout_ctl == req_vout_ctl) {
  1244. ret = 0;
  1245. goto exit;
  1246. }
  1247. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1248. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1249. req_volt, micb_en);
  1250. if (micb_en == 0x1)
  1251. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1252. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1253. if (micb_en == 0x1) {
  1254. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1255. /*
  1256. * Add 2ms delay as per HW requirement after enabling
  1257. * micbias
  1258. */
  1259. usleep_range(2000, 2100);
  1260. }
  1261. exit:
  1262. mutex_unlock(&wcd937x->micb_lock);
  1263. return ret;
  1264. }
  1265. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1266. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1267. struct snd_kcontrol *kcontrol,
  1268. int event)
  1269. {
  1270. struct snd_soc_component *component =
  1271. snd_soc_dapm_to_component(w->dapm);
  1272. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1273. int ret = 0;
  1274. switch (event) {
  1275. case SND_SOC_DAPM_PRE_PMU:
  1276. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1277. /* Enable BCS for Headset mic */
  1278. if (w->shift == 1 && !(snd_soc_component_read(component,
  1279. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1280. wcd937x_tx_connect_port(component, MBHC, true);
  1281. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1282. }
  1283. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1284. } else {
  1285. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1286. }
  1287. break;
  1288. case SND_SOC_DAPM_POST_PMD:
  1289. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1290. wcd937x->tx_swr_dev->dev_num,
  1291. false);
  1292. break;
  1293. };
  1294. return ret;
  1295. }
  1296. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1297. struct snd_kcontrol *kcontrol,
  1298. int event){
  1299. struct snd_soc_component *component =
  1300. snd_soc_dapm_to_component(w->dapm);
  1301. struct wcd937x_priv *wcd937x =
  1302. snd_soc_component_get_drvdata(component);
  1303. int ret = 0;
  1304. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1305. w->name, event);
  1306. switch (event) {
  1307. case SND_SOC_DAPM_PRE_PMU:
  1308. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1309. wcd937x->ana_clk_count++;
  1310. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1311. snd_soc_component_update_bits(component,
  1312. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1313. snd_soc_component_update_bits(component,
  1314. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1315. snd_soc_component_update_bits(component,
  1316. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1317. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1318. wcd937x->tx_swr_dev->dev_num,
  1319. true);
  1320. break;
  1321. case SND_SOC_DAPM_POST_PMD:
  1322. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1323. if (w->shift == 1 &&
  1324. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1325. wcd937x_tx_connect_port(component, MBHC, false);
  1326. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1327. }
  1328. snd_soc_component_update_bits(component,
  1329. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1330. break;
  1331. };
  1332. return ret;
  1333. }
  1334. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1335. struct snd_kcontrol *kcontrol, int event)
  1336. {
  1337. struct snd_soc_component *component =
  1338. snd_soc_dapm_to_component(w->dapm);
  1339. struct wcd937x_priv *wcd937x =
  1340. snd_soc_component_get_drvdata(component);
  1341. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1342. w->name, event);
  1343. switch (event) {
  1344. case SND_SOC_DAPM_PRE_PMU:
  1345. snd_soc_component_update_bits(component,
  1346. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1347. snd_soc_component_update_bits(component,
  1348. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1349. snd_soc_component_update_bits(component,
  1350. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1351. snd_soc_component_update_bits(component,
  1352. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1353. snd_soc_component_update_bits(component,
  1354. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1355. snd_soc_component_update_bits(component,
  1356. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1357. snd_soc_component_update_bits(component,
  1358. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1359. snd_soc_component_update_bits(component,
  1360. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1361. snd_soc_component_update_bits(component,
  1362. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1363. break;
  1364. case SND_SOC_DAPM_POST_PMD:
  1365. snd_soc_component_update_bits(component,
  1366. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1367. snd_soc_component_update_bits(component,
  1368. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1369. snd_soc_component_update_bits(component,
  1370. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1371. snd_soc_component_update_bits(component,
  1372. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1373. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1374. wcd937x->ana_clk_count--;
  1375. if (wcd937x->ana_clk_count <= 0) {
  1376. snd_soc_component_update_bits(component,
  1377. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1378. wcd937x->ana_clk_count = 0;
  1379. }
  1380. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1381. snd_soc_component_update_bits(component,
  1382. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1383. break;
  1384. };
  1385. return 0;
  1386. }
  1387. int wcd937x_micbias_control(struct snd_soc_component *component,
  1388. int micb_num, int req, bool is_dapm)
  1389. {
  1390. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1391. int micb_index = micb_num - 1;
  1392. u16 micb_reg;
  1393. int pre_off_event = 0, post_off_event = 0;
  1394. int post_on_event = 0, post_dapm_off = 0;
  1395. int post_dapm_on = 0;
  1396. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1397. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1398. __func__, micb_index);
  1399. return -EINVAL;
  1400. }
  1401. switch (micb_num) {
  1402. case MIC_BIAS_1:
  1403. micb_reg = WCD937X_ANA_MICB1;
  1404. break;
  1405. case MIC_BIAS_2:
  1406. micb_reg = WCD937X_ANA_MICB2;
  1407. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1408. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1409. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1410. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1411. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1412. break;
  1413. case MIC_BIAS_3:
  1414. micb_reg = WCD937X_ANA_MICB3;
  1415. break;
  1416. default:
  1417. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1418. __func__, micb_num);
  1419. return -EINVAL;
  1420. };
  1421. mutex_lock(&wcd937x->micb_lock);
  1422. switch (req) {
  1423. case MICB_PULLUP_ENABLE:
  1424. wcd937x->pullup_ref[micb_index]++;
  1425. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1426. (wcd937x->micb_ref[micb_index] == 0))
  1427. snd_soc_component_update_bits(component, micb_reg,
  1428. 0xC0, 0x80);
  1429. break;
  1430. case MICB_PULLUP_DISABLE:
  1431. if (wcd937x->pullup_ref[micb_index] > 0)
  1432. wcd937x->pullup_ref[micb_index]--;
  1433. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1434. (wcd937x->micb_ref[micb_index] == 0))
  1435. snd_soc_component_update_bits(component, micb_reg,
  1436. 0xC0, 0x00);
  1437. break;
  1438. case MICB_ENABLE:
  1439. wcd937x->micb_ref[micb_index]++;
  1440. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1441. wcd937x->ana_clk_count++;
  1442. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1443. if (wcd937x->micb_ref[micb_index] == 1) {
  1444. snd_soc_component_update_bits(component,
  1445. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1446. snd_soc_component_update_bits(component,
  1447. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1448. snd_soc_component_update_bits(component,
  1449. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1450. snd_soc_component_update_bits(component,
  1451. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1452. snd_soc_component_update_bits(component,
  1453. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1454. snd_soc_component_update_bits(component,
  1455. micb_reg, 0xC0, 0x40);
  1456. if (post_on_event)
  1457. blocking_notifier_call_chain(
  1458. &wcd937x->mbhc->notifier, post_on_event,
  1459. &wcd937x->mbhc->wcd_mbhc);
  1460. }
  1461. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1462. blocking_notifier_call_chain(
  1463. &wcd937x->mbhc->notifier, post_dapm_on,
  1464. &wcd937x->mbhc->wcd_mbhc);
  1465. break;
  1466. case MICB_DISABLE:
  1467. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1468. wcd937x->ana_clk_count--;
  1469. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1470. if (wcd937x->micb_ref[micb_index] > 0)
  1471. wcd937x->micb_ref[micb_index]--;
  1472. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1473. (wcd937x->pullup_ref[micb_index] > 0))
  1474. snd_soc_component_update_bits(component, micb_reg,
  1475. 0xC0, 0x80);
  1476. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1477. (wcd937x->pullup_ref[micb_index] == 0)) {
  1478. if (pre_off_event && wcd937x->mbhc)
  1479. blocking_notifier_call_chain(
  1480. &wcd937x->mbhc->notifier, pre_off_event,
  1481. &wcd937x->mbhc->wcd_mbhc);
  1482. snd_soc_component_update_bits(component, micb_reg,
  1483. 0xC0, 0x00);
  1484. if (post_off_event && wcd937x->mbhc)
  1485. blocking_notifier_call_chain(
  1486. &wcd937x->mbhc->notifier,
  1487. post_off_event,
  1488. &wcd937x->mbhc->wcd_mbhc);
  1489. }
  1490. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1491. if (wcd937x->ana_clk_count <= 0) {
  1492. snd_soc_component_update_bits(component,
  1493. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1494. 0x10, 0x00);
  1495. wcd937x->ana_clk_count = 0;
  1496. }
  1497. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1498. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1499. blocking_notifier_call_chain(
  1500. &wcd937x->mbhc->notifier, post_dapm_off,
  1501. &wcd937x->mbhc->wcd_mbhc);
  1502. break;
  1503. };
  1504. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1505. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1506. wcd937x->pullup_ref[micb_index]);
  1507. mutex_unlock(&wcd937x->micb_lock);
  1508. return 0;
  1509. }
  1510. EXPORT_SYMBOL(wcd937x_micbias_control);
  1511. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1512. bool bcs_disable)
  1513. {
  1514. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1515. if (wcd937x->update_wcd_event) {
  1516. if (bcs_disable)
  1517. wcd937x->update_wcd_event(wcd937x->handle,
  1518. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1519. else
  1520. wcd937x->update_wcd_event(wcd937x->handle,
  1521. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1522. }
  1523. }
  1524. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1525. {
  1526. int ret = 0;
  1527. uint8_t devnum = 0;
  1528. int num_retry = NUM_ATTEMPTS;
  1529. do {
  1530. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1531. if (ret) {
  1532. dev_err(&swr_dev->dev,
  1533. "%s get devnum %d for dev addr %lx failed\n",
  1534. __func__, devnum, swr_dev->addr);
  1535. /* retry after 1ms */
  1536. usleep_range(1000, 1010);
  1537. }
  1538. } while (ret && --num_retry);
  1539. swr_dev->dev_num = devnum;
  1540. return 0;
  1541. }
  1542. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1543. struct wcd_mbhc_config *mbhc_cfg)
  1544. {
  1545. if (mbhc_cfg->enable_usbc_analog) {
  1546. if (!(snd_soc_component_read(component, WCD937X_ANA_MBHC_MECH)
  1547. & 0x20))
  1548. return true;
  1549. }
  1550. return false;
  1551. }
  1552. static int wcd937x_event_notify(struct notifier_block *block,
  1553. unsigned long val,
  1554. void *data)
  1555. {
  1556. u16 event = (val & 0xffff);
  1557. u16 amic = (val >> 0x10);
  1558. u16 mask = 0x40, reg = 0x0;
  1559. int ret = 0;
  1560. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1561. struct snd_soc_component *component = wcd937x->component;
  1562. struct wcd_mbhc *mbhc;
  1563. switch (event) {
  1564. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1565. if (amic == 0x1 || amic == 0x2)
  1566. reg = WCD937X_ANA_TX_CH2;
  1567. else if (amic == 0x3)
  1568. reg = WCD937X_ANA_TX_CH3_HPF;
  1569. else
  1570. return 0;
  1571. if (amic == 0x2)
  1572. mask = 0x20;
  1573. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1574. break;
  1575. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1576. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1577. 0xC0, 0x00);
  1578. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1579. 0x80, 0x00);
  1580. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1581. 0x80, 0x00);
  1582. break;
  1583. case BOLERO_SLV_EVT_SSR_DOWN:
  1584. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1585. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1586. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1587. mbhc->mbhc_cfg);
  1588. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1589. wcd937x_reset_low(wcd937x->dev);
  1590. break;
  1591. case BOLERO_SLV_EVT_SSR_UP:
  1592. wcd937x_reset(wcd937x->dev);
  1593. /* allow reset to take effect */
  1594. usleep_range(10000, 10010);
  1595. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1596. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1597. wcd937x_init_reg(component);
  1598. regcache_mark_dirty(wcd937x->regmap);
  1599. regcache_sync(wcd937x->regmap);
  1600. /* Initialize MBHC module */
  1601. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1602. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1603. if (ret) {
  1604. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1605. __func__);
  1606. } else {
  1607. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1608. if (wcd937x->usbc_hs_status)
  1609. mdelay(500);
  1610. }
  1611. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1612. break;
  1613. default:
  1614. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1615. event);
  1616. break;
  1617. }
  1618. return 0;
  1619. }
  1620. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1621. int event)
  1622. {
  1623. struct snd_soc_component *component =
  1624. snd_soc_dapm_to_component(w->dapm);
  1625. int micb_num;
  1626. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1627. __func__, w->name, event);
  1628. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1629. micb_num = MIC_BIAS_1;
  1630. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1631. micb_num = MIC_BIAS_2;
  1632. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1633. micb_num = MIC_BIAS_3;
  1634. else
  1635. return -EINVAL;
  1636. switch (event) {
  1637. case SND_SOC_DAPM_PRE_PMU:
  1638. wcd937x_micbias_control(component, micb_num,
  1639. MICB_ENABLE, true);
  1640. break;
  1641. case SND_SOC_DAPM_POST_PMU:
  1642. usleep_range(1000, 1100);
  1643. break;
  1644. case SND_SOC_DAPM_POST_PMD:
  1645. wcd937x_micbias_control(component, micb_num,
  1646. MICB_DISABLE, true);
  1647. break;
  1648. };
  1649. return 0;
  1650. }
  1651. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1652. struct snd_kcontrol *kcontrol,
  1653. int event)
  1654. {
  1655. return __wcd937x_codec_enable_micbias(w, event);
  1656. }
  1657. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1658. int event)
  1659. {
  1660. struct snd_soc_component *component =
  1661. snd_soc_dapm_to_component(w->dapm);
  1662. int micb_num;
  1663. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1664. __func__, w->name, event);
  1665. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1666. micb_num = MIC_BIAS_1;
  1667. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1668. micb_num = MIC_BIAS_2;
  1669. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1670. micb_num = MIC_BIAS_3;
  1671. else
  1672. return -EINVAL;
  1673. switch (event) {
  1674. case SND_SOC_DAPM_PRE_PMU:
  1675. wcd937x_micbias_control(component, micb_num,
  1676. MICB_PULLUP_ENABLE, true);
  1677. break;
  1678. case SND_SOC_DAPM_POST_PMU:
  1679. /* 1 msec delay as per HW requirement */
  1680. usleep_range(1000, 1100);
  1681. break;
  1682. case SND_SOC_DAPM_POST_PMD:
  1683. wcd937x_micbias_control(component, micb_num,
  1684. MICB_PULLUP_DISABLE, true);
  1685. break;
  1686. };
  1687. return 0;
  1688. }
  1689. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1690. struct snd_kcontrol *kcontrol,
  1691. int event)
  1692. {
  1693. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1694. }
  1695. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1696. struct snd_ctl_elem_value *ucontrol)
  1697. {
  1698. struct snd_soc_component *component =
  1699. snd_soc_kcontrol_component(kcontrol);
  1700. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1701. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1702. return 0;
  1703. }
  1704. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1705. struct snd_ctl_elem_value *ucontrol)
  1706. {
  1707. struct snd_soc_component *component =
  1708. snd_soc_kcontrol_component(kcontrol);
  1709. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1710. u32 mode_val;
  1711. mode_val = ucontrol->value.enumerated.item[0];
  1712. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1713. if (mode_val == 0) {
  1714. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1715. __func__);
  1716. mode_val = 3; /* enum will be updated later */
  1717. }
  1718. wcd937x->hph_mode = mode_val;
  1719. return 0;
  1720. }
  1721. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1722. struct snd_ctl_elem_value *ucontrol)
  1723. {
  1724. struct snd_soc_component *component =
  1725. snd_soc_kcontrol_component(kcontrol);
  1726. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1727. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1728. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1729. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1730. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1731. return 0;
  1732. }
  1733. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1734. struct snd_ctl_elem_value *ucontrol)
  1735. {
  1736. struct snd_soc_component *component =
  1737. snd_soc_kcontrol_component(kcontrol);
  1738. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1739. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1740. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1741. __func__, pwr_level);
  1742. if (strnstr(kcontrol->id.name, "CH1",
  1743. sizeof(kcontrol->id.name))) {
  1744. snd_soc_component_update_bits(component,
  1745. WCD937X_ANA_TX_CH1, 0x60,
  1746. pwr_level << 0x5);
  1747. wcd937x->tx_ch_pwr[0] = pwr_level;
  1748. } else if (strnstr(kcontrol->id.name, "CH3",
  1749. sizeof(kcontrol->id.name))) {
  1750. snd_soc_component_update_bits(component,
  1751. WCD937X_ANA_TX_CH3, 0x60,
  1752. pwr_level << 0x5);
  1753. wcd937x->tx_ch_pwr[1] = pwr_level;
  1754. }
  1755. return 0;
  1756. }
  1757. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1758. struct snd_ctl_elem_value *ucontrol)
  1759. {
  1760. u8 ear_pa_gain = 0;
  1761. struct snd_soc_component *component =
  1762. snd_soc_kcontrol_component(kcontrol);
  1763. ear_pa_gain = snd_soc_component_read(component,
  1764. WCD937X_ANA_EAR_COMPANDER_CTL);
  1765. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1766. ucontrol->value.integer.value[0] = ear_pa_gain;
  1767. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1768. ear_pa_gain);
  1769. return 0;
  1770. }
  1771. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1772. struct snd_ctl_elem_value *ucontrol)
  1773. {
  1774. u8 ear_pa_gain = 0;
  1775. struct snd_soc_component *component =
  1776. snd_soc_kcontrol_component(kcontrol);
  1777. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1778. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1779. __func__, ucontrol->value.integer.value[0]);
  1780. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1781. if (!wcd937x->comp1_enable) {
  1782. snd_soc_component_update_bits(component,
  1783. WCD937X_ANA_EAR_COMPANDER_CTL,
  1784. 0x7C, ear_pa_gain);
  1785. }
  1786. return 0;
  1787. }
  1788. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1789. struct snd_ctl_elem_value *ucontrol)
  1790. {
  1791. struct snd_soc_component *component =
  1792. snd_soc_kcontrol_component(kcontrol);
  1793. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1794. bool hphr;
  1795. struct soc_multi_mixer_control *mc;
  1796. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1797. hphr = mc->shift;
  1798. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1799. wcd937x->comp1_enable;
  1800. return 0;
  1801. }
  1802. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1803. struct snd_ctl_elem_value *ucontrol)
  1804. {
  1805. struct snd_soc_component *component =
  1806. snd_soc_kcontrol_component(kcontrol);
  1807. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1808. int value = ucontrol->value.integer.value[0];
  1809. bool hphr;
  1810. struct soc_multi_mixer_control *mc;
  1811. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1812. hphr = mc->shift;
  1813. if (hphr)
  1814. wcd937x->comp2_enable = value;
  1815. else
  1816. wcd937x->comp1_enable = value;
  1817. return 0;
  1818. }
  1819. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1820. struct snd_kcontrol *kcontrol,
  1821. int event)
  1822. {
  1823. struct snd_soc_component *component =
  1824. snd_soc_dapm_to_component(w->dapm);
  1825. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1826. struct wcd937x_pdata *pdata = NULL;
  1827. int ret = 0;
  1828. pdata = dev_get_platdata(wcd937x->dev);
  1829. if (!pdata) {
  1830. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1831. return -EINVAL;
  1832. }
  1833. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1834. w->name, event);
  1835. switch (event) {
  1836. case SND_SOC_DAPM_PRE_PMU:
  1837. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1838. dev_dbg(component->dev,
  1839. "%s: buck already in enabled state\n",
  1840. __func__);
  1841. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1842. return 0;
  1843. }
  1844. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1845. wcd937x->supplies,
  1846. pdata->regulator,
  1847. pdata->num_supplies,
  1848. "cdc-vdd-buck");
  1849. if (ret == -EINVAL) {
  1850. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1851. __func__);
  1852. return ret;
  1853. }
  1854. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1855. /*
  1856. * 200us sleep is required after LDO15 is enabled as per
  1857. * HW requirement
  1858. */
  1859. usleep_range(200, 250);
  1860. break;
  1861. case SND_SOC_DAPM_POST_PMD:
  1862. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1863. break;
  1864. }
  1865. return 0;
  1866. }
  1867. static const char * const rx_hph_mode_mux_text[] = {
  1868. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1869. "CLS_H_ULP", "CLS_AB_HIFI",
  1870. };
  1871. const char * const tx_master_ch_text[] = {
  1872. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1873. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1874. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1875. "SWRM_PCM_IN",
  1876. };
  1877. const struct soc_enum tx_master_ch_enum =
  1878. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1879. tx_master_ch_text);
  1880. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1881. {
  1882. u8 ch_type = 0;
  1883. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1884. ch_type = ADC1;
  1885. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1886. ch_type = ADC2;
  1887. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1888. ch_type = ADC3;
  1889. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1890. ch_type = DMIC0;
  1891. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1892. ch_type = DMIC1;
  1893. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1894. ch_type = MBHC;
  1895. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1896. ch_type = DMIC2;
  1897. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1898. ch_type = DMIC3;
  1899. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1900. ch_type = DMIC4;
  1901. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1902. ch_type = DMIC5;
  1903. else
  1904. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1905. if (ch_type)
  1906. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1907. else
  1908. *ch_idx = -EINVAL;
  1909. }
  1910. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1911. struct snd_ctl_elem_value *ucontrol)
  1912. {
  1913. struct snd_soc_component *component =
  1914. snd_soc_kcontrol_component(kcontrol);
  1915. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1916. int slave_ch_idx;
  1917. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1918. if (slave_ch_idx != -EINVAL)
  1919. ucontrol->value.integer.value[0] =
  1920. wcd937x_slave_get_master_ch_val(
  1921. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1922. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1923. __func__, ucontrol->value.integer.value[0]);
  1924. return 0;
  1925. }
  1926. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1927. struct snd_ctl_elem_value *ucontrol)
  1928. {
  1929. struct snd_soc_component *component =
  1930. snd_soc_kcontrol_component(kcontrol);
  1931. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1932. int slave_ch_idx;
  1933. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1934. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1935. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1936. __func__, ucontrol->value.enumerated.item[0]);
  1937. if (slave_ch_idx != -EINVAL)
  1938. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1939. wcd937x_slave_get_master_ch(
  1940. ucontrol->value.enumerated.item[0]);
  1941. return 0;
  1942. }
  1943. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1944. "L0", "L1", "L2", "L3",
  1945. };
  1946. static const char * const wcd937x_ear_pa_gain_text[] = {
  1947. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1948. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1949. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1950. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1951. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1952. };
  1953. static const struct soc_enum rx_hph_mode_mux_enum =
  1954. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1955. rx_hph_mode_mux_text);
  1956. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1957. wcd937x_ear_pa_gain_text);
  1958. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1959. wcd937x_tx_ch_pwr_level_text);
  1960. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1961. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1962. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1963. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1964. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1965. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1966. wcd937x_get_compander, wcd937x_set_compander),
  1967. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1968. wcd937x_get_compander, wcd937x_set_compander),
  1969. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1970. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1971. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1972. analog_gain),
  1973. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1974. analog_gain),
  1975. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1976. analog_gain),
  1977. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1978. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1979. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1980. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1981. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1982. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1983. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  1984. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1985. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  1986. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1987. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  1988. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1989. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  1990. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1991. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  1992. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1993. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  1994. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1995. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  1996. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1997. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  1998. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1999. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  2000. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2001. };
  2002. static const struct snd_kcontrol_new adc1_switch[] = {
  2003. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2004. };
  2005. static const struct snd_kcontrol_new adc2_switch[] = {
  2006. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2007. };
  2008. static const struct snd_kcontrol_new adc3_switch[] = {
  2009. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2010. };
  2011. static const struct snd_kcontrol_new dmic1_switch[] = {
  2012. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2013. };
  2014. static const struct snd_kcontrol_new dmic2_switch[] = {
  2015. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2016. };
  2017. static const struct snd_kcontrol_new dmic3_switch[] = {
  2018. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2019. };
  2020. static const struct snd_kcontrol_new dmic4_switch[] = {
  2021. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2022. };
  2023. static const struct snd_kcontrol_new dmic5_switch[] = {
  2024. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2025. };
  2026. static const struct snd_kcontrol_new dmic6_switch[] = {
  2027. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2028. };
  2029. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2030. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2031. };
  2032. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2033. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2034. };
  2035. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2036. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2037. };
  2038. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2039. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2040. };
  2041. static const char * const adc2_mux_text[] = {
  2042. "INP2", "INP3"
  2043. };
  2044. static const char * const rdac3_mux_text[] = {
  2045. "RX1", "RX3"
  2046. };
  2047. static const struct soc_enum adc2_enum =
  2048. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  2049. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2050. static const struct soc_enum rdac3_enum =
  2051. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2052. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2053. static const struct snd_kcontrol_new tx_adc2_mux =
  2054. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2055. static const struct snd_kcontrol_new rx_rdac3_mux =
  2056. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2057. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  2058. /*input widgets*/
  2059. SND_SOC_DAPM_INPUT("AMIC1"),
  2060. SND_SOC_DAPM_INPUT("AMIC2"),
  2061. SND_SOC_DAPM_INPUT("AMIC3"),
  2062. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2063. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2064. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2065. /*
  2066. * These dummy widgets are null connected to WCD937x dapm input and
  2067. * output widgets which are not actual path endpoints. This ensures
  2068. * dapm doesnt set these dapm input and output widgets as endpoints.
  2069. */
  2070. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2071. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2072. /*tx widgets*/
  2073. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2074. wcd937x_codec_enable_adc,
  2075. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2076. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2077. wcd937x_codec_enable_adc,
  2078. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2079. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2080. NULL, 0, wcd937x_enable_req,
  2081. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2082. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2083. NULL, 0, wcd937x_enable_req,
  2084. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2085. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2086. &tx_adc2_mux),
  2087. /*tx mixers*/
  2088. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2089. adc1_switch, ARRAY_SIZE(adc1_switch),
  2090. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2091. SND_SOC_DAPM_POST_PMD),
  2092. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2093. adc2_switch, ARRAY_SIZE(adc2_switch),
  2094. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2095. SND_SOC_DAPM_POST_PMD),
  2096. /* micbias widgets*/
  2097. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2098. wcd937x_codec_enable_micbias,
  2099. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2100. SND_SOC_DAPM_POST_PMD),
  2101. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2102. wcd937x_codec_enable_micbias,
  2103. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2104. SND_SOC_DAPM_POST_PMD),
  2105. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2106. wcd937x_codec_enable_micbias,
  2107. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2108. SND_SOC_DAPM_POST_PMD),
  2109. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2110. wcd937x_codec_enable_vdd_buck,
  2111. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2112. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2113. wcd937x_enable_clsh,
  2114. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2115. /*rx widgets*/
  2116. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2117. wcd937x_codec_enable_ear_pa,
  2118. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2119. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2120. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2121. wcd937x_codec_enable_aux_pa,
  2122. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2123. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2124. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2125. wcd937x_codec_enable_hphl_pa,
  2126. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2127. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2128. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2129. wcd937x_codec_enable_hphr_pa,
  2130. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2131. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2132. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2133. wcd937x_codec_hphl_dac_event,
  2134. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2135. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2136. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2137. wcd937x_codec_hphr_dac_event,
  2138. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2139. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2140. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2141. wcd937x_codec_ear_dac_event,
  2142. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2143. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2144. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2145. wcd937x_codec_aux_dac_event,
  2146. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2147. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2148. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2149. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2150. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2151. SND_SOC_DAPM_POST_PMD),
  2152. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2153. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2154. SND_SOC_DAPM_POST_PMD),
  2155. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2156. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2157. SND_SOC_DAPM_POST_PMD),
  2158. /* rx mixer widgets*/
  2159. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2160. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2161. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2162. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2163. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2164. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2165. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2166. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2167. /*output widgets tx*/
  2168. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2169. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2170. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2171. /*output widgets rx*/
  2172. SND_SOC_DAPM_OUTPUT("EAR"),
  2173. SND_SOC_DAPM_OUTPUT("AUX"),
  2174. SND_SOC_DAPM_OUTPUT("HPHL"),
  2175. SND_SOC_DAPM_OUTPUT("HPHR"),
  2176. /* micbias pull up widgets*/
  2177. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2178. wcd937x_codec_enable_micbias_pullup,
  2179. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2180. SND_SOC_DAPM_POST_PMD),
  2181. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2182. wcd937x_codec_enable_micbias_pullup,
  2183. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2184. SND_SOC_DAPM_POST_PMD),
  2185. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2186. wcd937x_codec_enable_micbias_pullup,
  2187. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2188. SND_SOC_DAPM_POST_PMD),
  2189. };
  2190. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2191. /*input widgets*/
  2192. SND_SOC_DAPM_INPUT("AMIC4"),
  2193. /*tx widgets*/
  2194. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2195. wcd937x_codec_enable_adc,
  2196. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2197. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2198. NULL, 0, wcd937x_enable_req,
  2199. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2200. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2201. wcd937x_codec_enable_dmic,
  2202. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2203. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2204. wcd937x_codec_enable_dmic,
  2205. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2206. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2207. wcd937x_codec_enable_dmic,
  2208. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2209. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2210. wcd937x_codec_enable_dmic,
  2211. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2212. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2213. wcd937x_codec_enable_dmic,
  2214. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2215. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2216. wcd937x_codec_enable_dmic,
  2217. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2218. /*tx mixer widgets*/
  2219. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2220. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2221. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2222. SND_SOC_DAPM_POST_PMD),
  2223. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2224. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2225. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2226. SND_SOC_DAPM_POST_PMD),
  2227. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2228. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2229. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2230. SND_SOC_DAPM_POST_PMD),
  2231. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2232. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2233. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2234. SND_SOC_DAPM_POST_PMD),
  2235. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2236. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2237. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2238. SND_SOC_DAPM_POST_PMD),
  2239. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2240. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2241. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2242. SND_SOC_DAPM_POST_PMD),
  2243. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2244. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2245. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2246. /*output widgets*/
  2247. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2248. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2249. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2250. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2251. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2252. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2253. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2254. };
  2255. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2256. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2257. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2258. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2259. {"ADC1 REQ", NULL, "ADC1"},
  2260. {"ADC1", NULL, "AMIC1"},
  2261. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2262. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2263. {"ADC2 REQ", NULL, "ADC2"},
  2264. {"ADC2", NULL, "ADC2 MUX"},
  2265. {"ADC2 MUX", "INP3", "AMIC3"},
  2266. {"ADC2 MUX", "INP2", "AMIC2"},
  2267. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2268. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2269. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2270. {"RX1", NULL, "IN1_HPHL"},
  2271. {"RDAC1", NULL, "RX1"},
  2272. {"HPHL_RDAC", "Switch", "RDAC1"},
  2273. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2274. {"HPHL", NULL, "HPHL PGA"},
  2275. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2276. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2277. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2278. {"RX2", NULL, "IN2_HPHR"},
  2279. {"RDAC2", NULL, "RX2"},
  2280. {"HPHR_RDAC", "Switch", "RDAC2"},
  2281. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2282. {"HPHR", NULL, "HPHR PGA"},
  2283. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2284. {"IN3_AUX", NULL, "VDD_BUCK"},
  2285. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2286. {"RX3", NULL, "IN3_AUX"},
  2287. {"RDAC4", NULL, "RX3"},
  2288. {"AUX_RDAC", "Switch", "RDAC4"},
  2289. {"AUX PGA", NULL, "AUX_RDAC"},
  2290. {"AUX", NULL, "AUX PGA"},
  2291. {"RDAC3_MUX", "RX3", "RX3"},
  2292. {"RDAC3_MUX", "RX1", "RX1"},
  2293. {"RDAC3", NULL, "RDAC3_MUX"},
  2294. {"EAR_RDAC", "Switch", "RDAC3"},
  2295. {"EAR PGA", NULL, "EAR_RDAC"},
  2296. {"EAR", NULL, "EAR PGA"},
  2297. };
  2298. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2299. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2300. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2301. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2302. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2303. {"ADC3 REQ", NULL, "ADC3"},
  2304. {"ADC3", NULL, "AMIC4"},
  2305. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2306. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2307. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2308. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2309. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2310. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2311. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2312. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2313. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2314. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2315. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2316. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2317. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2318. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2319. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2320. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2321. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2322. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2323. };
  2324. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2325. void *file_private_data,
  2326. struct file *file,
  2327. char __user *buf, size_t count,
  2328. loff_t pos)
  2329. {
  2330. struct wcd937x_priv *priv;
  2331. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2332. int len = 0;
  2333. priv = (struct wcd937x_priv *) entry->private_data;
  2334. if (!priv) {
  2335. pr_err("%s: wcd937x priv is null\n", __func__);
  2336. return -EINVAL;
  2337. }
  2338. switch (priv->version) {
  2339. case WCD937X_VERSION_1_0:
  2340. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2341. break;
  2342. default:
  2343. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2344. }
  2345. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2346. }
  2347. static struct snd_info_entry_ops wcd937x_info_ops = {
  2348. .read = wcd937x_version_read,
  2349. };
  2350. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2351. void *file_private_data,
  2352. struct file *file,
  2353. char __user *buf, size_t count,
  2354. loff_t pos)
  2355. {
  2356. struct wcd937x_priv *priv;
  2357. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2358. int len = 0;
  2359. priv = (struct wcd937x_priv *) entry->private_data;
  2360. if (!priv) {
  2361. pr_err("%s: wcd937x priv is null\n", __func__);
  2362. return -EINVAL;
  2363. }
  2364. switch (priv->variant) {
  2365. case WCD9370_VARIANT:
  2366. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2367. break;
  2368. case WCD9375_VARIANT:
  2369. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2370. break;
  2371. default:
  2372. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2373. }
  2374. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2375. }
  2376. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2377. .read = wcd937x_variant_read,
  2378. };
  2379. /*
  2380. * wcd937x_info_create_codec_entry - creates wcd937x module
  2381. * @codec_root: The parent directory
  2382. * @component: component instance
  2383. *
  2384. * Creates wcd937x module, variant and version entry under the given
  2385. * parent directory.
  2386. *
  2387. * Return: 0 on success or negative error code on failure.
  2388. */
  2389. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2390. struct snd_soc_component *component)
  2391. {
  2392. struct snd_info_entry *version_entry;
  2393. struct snd_info_entry *variant_entry;
  2394. struct wcd937x_priv *priv;
  2395. struct snd_soc_card *card;
  2396. if (!codec_root || !component)
  2397. return -EINVAL;
  2398. priv = snd_soc_component_get_drvdata(component);
  2399. if (priv->entry) {
  2400. dev_dbg(priv->dev,
  2401. "%s:wcd937x module already created\n", __func__);
  2402. return 0;
  2403. }
  2404. card = component->card;
  2405. priv->entry = snd_info_create_module_entry(codec_root->module,
  2406. "wcd937x", codec_root);
  2407. if (!priv->entry) {
  2408. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2409. __func__);
  2410. return -ENOMEM;
  2411. }
  2412. priv->entry->mode = S_IFDIR | 0555;
  2413. if (snd_info_register(priv->entry) < 0) {
  2414. snd_info_free_entry(priv->entry);
  2415. return -ENOMEM;
  2416. }
  2417. version_entry = snd_info_create_card_entry(card->snd_card,
  2418. "version",
  2419. priv->entry);
  2420. if (!version_entry) {
  2421. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2422. __func__);
  2423. snd_info_free_entry(priv->entry);
  2424. return -ENOMEM;
  2425. }
  2426. version_entry->private_data = priv;
  2427. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2428. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2429. version_entry->c.ops = &wcd937x_info_ops;
  2430. if (snd_info_register(version_entry) < 0) {
  2431. snd_info_free_entry(version_entry);
  2432. snd_info_free_entry(priv->entry);
  2433. return -ENOMEM;
  2434. }
  2435. priv->version_entry = version_entry;
  2436. variant_entry = snd_info_create_card_entry(card->snd_card,
  2437. "variant",
  2438. priv->entry);
  2439. if (!variant_entry) {
  2440. dev_dbg(component->dev,
  2441. "%s: failed to create wcd937x variant entry\n",
  2442. __func__);
  2443. snd_info_free_entry(version_entry);
  2444. snd_info_free_entry(priv->entry);
  2445. return -ENOMEM;
  2446. }
  2447. variant_entry->private_data = priv;
  2448. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2449. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2450. variant_entry->c.ops = &wcd937x_variant_ops;
  2451. if (snd_info_register(variant_entry) < 0) {
  2452. snd_info_free_entry(variant_entry);
  2453. snd_info_free_entry(version_entry);
  2454. snd_info_free_entry(priv->entry);
  2455. return -ENOMEM;
  2456. }
  2457. priv->variant_entry = variant_entry;
  2458. return 0;
  2459. }
  2460. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2461. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2462. struct wcd937x_pdata *pdata)
  2463. {
  2464. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2465. int rc = 0;
  2466. if (!pdata) {
  2467. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2468. return -ENODEV;
  2469. }
  2470. /* set micbias voltage */
  2471. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2472. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2473. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2474. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2475. rc = -EINVAL;
  2476. goto done;
  2477. }
  2478. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2479. vout_ctl_1);
  2480. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2481. vout_ctl_2);
  2482. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2483. vout_ctl_3);
  2484. done:
  2485. return rc;
  2486. }
  2487. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2488. {
  2489. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2490. struct snd_soc_dapm_context *dapm =
  2491. snd_soc_component_get_dapm(component);
  2492. int variant;
  2493. int ret = -EINVAL;
  2494. dev_info(component->dev, "%s()\n", __func__);
  2495. wcd937x = snd_soc_component_get_drvdata(component);
  2496. if (!wcd937x)
  2497. return -EINVAL;
  2498. wcd937x->component = component;
  2499. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2500. variant = (snd_soc_component_read(
  2501. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2502. wcd937x->variant = variant;
  2503. wcd937x->fw_data = devm_kzalloc(component->dev,
  2504. sizeof(*(wcd937x->fw_data)),
  2505. GFP_KERNEL);
  2506. if (!wcd937x->fw_data) {
  2507. dev_err(component->dev, "Failed to allocate fw_data\n");
  2508. ret = -ENOMEM;
  2509. goto err;
  2510. }
  2511. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2512. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2513. WCD9XXX_CODEC_HWDEP_NODE, component);
  2514. if (ret < 0) {
  2515. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2516. goto err_hwdep;
  2517. }
  2518. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2519. if (ret) {
  2520. pr_err("%s: mbhc initialization failed\n", __func__);
  2521. goto err_hwdep;
  2522. }
  2523. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2524. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2525. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2526. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2527. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2528. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2529. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2530. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2531. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2532. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2533. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2534. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2535. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2536. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2537. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2538. snd_soc_dapm_sync(dapm);
  2539. wcd_cls_h_init(&wcd937x->clsh_info);
  2540. wcd937x_init_reg(component);
  2541. if (wcd937x->variant == WCD9375_VARIANT) {
  2542. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2543. ARRAY_SIZE(wcd9375_dapm_widgets));
  2544. if (ret < 0) {
  2545. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2546. __func__);
  2547. goto err_hwdep;
  2548. }
  2549. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2550. ARRAY_SIZE(wcd9375_audio_map));
  2551. if (ret < 0) {
  2552. dev_err(component->dev, "%s: Failed to add routes\n",
  2553. __func__);
  2554. goto err_hwdep;
  2555. }
  2556. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2557. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2558. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2559. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2560. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2561. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2562. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2563. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2564. snd_soc_dapm_sync(dapm);
  2565. }
  2566. wcd937x->version = WCD937X_VERSION_1_0;
  2567. /* Register event notifier */
  2568. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2569. if (wcd937x->register_notifier) {
  2570. ret = wcd937x->register_notifier(wcd937x->handle,
  2571. &wcd937x->nblock,
  2572. true);
  2573. if (ret) {
  2574. dev_err(component->dev,
  2575. "%s: Failed to register notifier %d\n",
  2576. __func__, ret);
  2577. return ret;
  2578. }
  2579. }
  2580. return ret;
  2581. err_hwdep:
  2582. wcd937x->fw_data = NULL;
  2583. err:
  2584. return ret;
  2585. }
  2586. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2587. {
  2588. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2589. if (!wcd937x)
  2590. return;
  2591. if (wcd937x->register_notifier)
  2592. wcd937x->register_notifier(wcd937x->handle,
  2593. &wcd937x->nblock,
  2594. false);
  2595. return;
  2596. }
  2597. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2598. .name = WCD937X_DRV_NAME,
  2599. .probe = wcd937x_soc_codec_probe,
  2600. .remove = wcd937x_soc_codec_remove,
  2601. .controls = wcd937x_snd_controls,
  2602. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2603. .dapm_widgets = wcd937x_dapm_widgets,
  2604. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2605. .dapm_routes = wcd937x_audio_map,
  2606. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2607. };
  2608. #ifdef CONFIG_PM_SLEEP
  2609. static int wcd937x_suspend(struct device *dev)
  2610. {
  2611. struct wcd937x_priv *wcd937x = NULL;
  2612. int ret = 0;
  2613. struct wcd937x_pdata *pdata = NULL;
  2614. if (!dev)
  2615. return -ENODEV;
  2616. wcd937x = dev_get_drvdata(dev);
  2617. if (!wcd937x)
  2618. return -EINVAL;
  2619. pdata = dev_get_platdata(wcd937x->dev);
  2620. if (!pdata) {
  2621. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2622. return -EINVAL;
  2623. }
  2624. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2625. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2626. wcd937x->supplies,
  2627. pdata->regulator,
  2628. pdata->num_supplies,
  2629. "cdc-vdd-buck");
  2630. if (ret == -EINVAL) {
  2631. dev_err(dev, "%s: vdd buck is not disabled\n",
  2632. __func__);
  2633. return 0;
  2634. }
  2635. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2636. }
  2637. return 0;
  2638. }
  2639. static int wcd937x_resume(struct device *dev)
  2640. {
  2641. return 0;
  2642. }
  2643. #endif
  2644. static int wcd937x_reset(struct device *dev)
  2645. {
  2646. struct wcd937x_priv *wcd937x = NULL;
  2647. int rc = 0;
  2648. int value = 0;
  2649. if (!dev)
  2650. return -ENODEV;
  2651. wcd937x = dev_get_drvdata(dev);
  2652. if (!wcd937x)
  2653. return -EINVAL;
  2654. if (!wcd937x->rst_np) {
  2655. dev_err(dev, "%s: reset gpio device node not specified\n",
  2656. __func__);
  2657. return -EINVAL;
  2658. }
  2659. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2660. if (value > 0)
  2661. return 0;
  2662. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2663. if (rc) {
  2664. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2665. __func__);
  2666. return rc;
  2667. }
  2668. /* 20ms sleep required after pulling the reset gpio to LOW */
  2669. usleep_range(20, 30);
  2670. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2671. if (rc) {
  2672. dev_err(dev, "%s: wcd active state request fail!\n",
  2673. __func__);
  2674. return rc;
  2675. }
  2676. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2677. usleep_range(20, 30);
  2678. return rc;
  2679. }
  2680. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2681. u32 *val)
  2682. {
  2683. int rc = 0;
  2684. rc = of_property_read_u32(dev->of_node, name, val);
  2685. if (rc)
  2686. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2687. __func__, name, dev->of_node->full_name);
  2688. return rc;
  2689. }
  2690. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2691. struct wcd937x_micbias_setting *mb)
  2692. {
  2693. u32 prop_val = 0;
  2694. int rc = 0;
  2695. /* MB1 */
  2696. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2697. NULL)) {
  2698. rc = wcd937x_read_of_property_u32(dev,
  2699. "qcom,cdc-micbias1-mv",
  2700. &prop_val);
  2701. if (!rc)
  2702. mb->micb1_mv = prop_val;
  2703. } else {
  2704. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2705. __func__);
  2706. }
  2707. /* MB2 */
  2708. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2709. NULL)) {
  2710. rc = wcd937x_read_of_property_u32(dev,
  2711. "qcom,cdc-micbias2-mv",
  2712. &prop_val);
  2713. if (!rc)
  2714. mb->micb2_mv = prop_val;
  2715. } else {
  2716. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2717. __func__);
  2718. }
  2719. /* MB3 */
  2720. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2721. NULL)) {
  2722. rc = wcd937x_read_of_property_u32(dev,
  2723. "qcom,cdc-micbias3-mv",
  2724. &prop_val);
  2725. if (!rc)
  2726. mb->micb3_mv = prop_val;
  2727. } else {
  2728. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2729. __func__);
  2730. }
  2731. }
  2732. static int wcd937x_reset_low(struct device *dev)
  2733. {
  2734. struct wcd937x_priv *wcd937x = NULL;
  2735. int rc = 0;
  2736. if (!dev)
  2737. return -ENODEV;
  2738. wcd937x = dev_get_drvdata(dev);
  2739. if (!wcd937x)
  2740. return -EINVAL;
  2741. if (!wcd937x->rst_np) {
  2742. dev_err(dev, "%s: reset gpio device node not specified\n",
  2743. __func__);
  2744. return -EINVAL;
  2745. }
  2746. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2747. if (rc) {
  2748. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2749. __func__);
  2750. return rc;
  2751. }
  2752. /* 20ms sleep required after pulling the reset gpio to LOW */
  2753. usleep_range(20, 30);
  2754. return rc;
  2755. }
  2756. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2757. {
  2758. struct wcd937x_pdata *pdata = NULL;
  2759. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2760. GFP_KERNEL);
  2761. if (!pdata)
  2762. return NULL;
  2763. pdata->rst_np = of_parse_phandle(dev->of_node,
  2764. "qcom,wcd-rst-gpio-node", 0);
  2765. if (!pdata->rst_np) {
  2766. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2767. __func__, "qcom,wcd-rst-gpio-node",
  2768. dev->of_node->full_name);
  2769. return NULL;
  2770. }
  2771. /* Parse power supplies */
  2772. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2773. &pdata->num_supplies);
  2774. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2775. dev_err(dev, "%s: no power supplies defined for codec\n",
  2776. __func__);
  2777. return NULL;
  2778. }
  2779. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2780. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2781. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2782. return pdata;
  2783. }
  2784. static int wcd937x_wakeup(void *handle, bool enable)
  2785. {
  2786. struct wcd937x_priv *priv;
  2787. if (!handle) {
  2788. pr_err("%s: NULL handle\n", __func__);
  2789. return -EINVAL;
  2790. }
  2791. priv = (struct wcd937x_priv *)handle;
  2792. if (!priv->tx_swr_dev) {
  2793. pr_err("%s: tx swr dev is NULL\n", __func__);
  2794. return -EINVAL;
  2795. }
  2796. if (enable)
  2797. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2798. else
  2799. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2800. }
  2801. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2802. {
  2803. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2804. __func__, irq);
  2805. return IRQ_HANDLED;
  2806. }
  2807. static int wcd937x_bind(struct device *dev)
  2808. {
  2809. int ret = 0, i = 0;
  2810. struct wcd937x_priv *wcd937x = NULL;
  2811. struct wcd937x_pdata *pdata = NULL;
  2812. struct wcd_ctrl_platform_data *plat_data = NULL;
  2813. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2814. if (!wcd937x)
  2815. return -ENOMEM;
  2816. dev_set_drvdata(dev, wcd937x);
  2817. pdata = wcd937x_populate_dt_data(dev);
  2818. if (!pdata) {
  2819. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2820. return -EINVAL;
  2821. }
  2822. wcd937x->dev = dev;
  2823. wcd937x->dev->platform_data = pdata;
  2824. wcd937x->rst_np = pdata->rst_np;
  2825. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2826. pdata->regulator, pdata->num_supplies);
  2827. if (!wcd937x->supplies) {
  2828. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2829. __func__);
  2830. goto err_bind_all;
  2831. }
  2832. plat_data = dev_get_platdata(dev->parent);
  2833. if (!plat_data) {
  2834. dev_err(dev, "%s: platform data from parent is NULL\n",
  2835. __func__);
  2836. ret = -EINVAL;
  2837. goto err_bind_all;
  2838. }
  2839. wcd937x->handle = (void *)plat_data->handle;
  2840. if (!wcd937x->handle) {
  2841. dev_err(dev, "%s: handle is NULL\n", __func__);
  2842. ret = -EINVAL;
  2843. goto err_bind_all;
  2844. }
  2845. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2846. if (!wcd937x->update_wcd_event) {
  2847. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2848. __func__);
  2849. ret = -EINVAL;
  2850. goto err_bind_all;
  2851. }
  2852. wcd937x->register_notifier = plat_data->register_notifier;
  2853. if (!wcd937x->register_notifier) {
  2854. dev_err(dev, "%s: register_notifier api is null!\n",
  2855. __func__);
  2856. ret = -EINVAL;
  2857. goto err_bind_all;
  2858. }
  2859. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2860. pdata->regulator,
  2861. pdata->num_supplies);
  2862. if (ret) {
  2863. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2864. __func__);
  2865. goto err_bind_all;
  2866. }
  2867. wcd937x_reset(dev);
  2868. /*
  2869. * Add 5msec delay to provide sufficient time for
  2870. * soundwire auto enumeration of slave devices as
  2871. * as per HW requirement.
  2872. */
  2873. usleep_range(5000, 5010);
  2874. wcd937x->wakeup = wcd937x_wakeup;
  2875. ret = component_bind_all(dev, wcd937x);
  2876. if (ret) {
  2877. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2878. __func__, ret);
  2879. goto err_bind_all;
  2880. }
  2881. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2882. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2883. if (ret) {
  2884. dev_err(dev, "Failed to read port mapping\n");
  2885. goto err;
  2886. }
  2887. ret = wcd937x_parse_port_params(dev, "qcom,swr-tx-port-params",
  2888. CODEC_TX);
  2889. if (ret) {
  2890. dev_err(dev, "Failed to read port params\n");
  2891. goto err;
  2892. }
  2893. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2894. if (!wcd937x->rx_swr_dev) {
  2895. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2896. __func__);
  2897. ret = -ENODEV;
  2898. goto err;
  2899. }
  2900. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2901. if (!wcd937x->tx_swr_dev) {
  2902. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2903. __func__);
  2904. ret = -ENODEV;
  2905. goto err;
  2906. }
  2907. swr_init_port_params(wcd937x->tx_swr_dev, SWR_NUM_PORTS,
  2908. wcd937x->swr_tx_port_params);
  2909. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2910. &wcd937x_regmap_config);
  2911. if (!wcd937x->regmap) {
  2912. dev_err(dev, "%s: Regmap init failed\n",
  2913. __func__);
  2914. goto err;
  2915. }
  2916. /* Set all interupts as edge triggered */
  2917. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2918. regmap_write(wcd937x->regmap,
  2919. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2920. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2921. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2922. wcd937x->irq_info.codec_name = "WCD937X";
  2923. wcd937x->irq_info.regmap = wcd937x->regmap;
  2924. wcd937x->irq_info.dev = dev;
  2925. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2926. if (ret) {
  2927. dev_err(dev, "%s: IRQ init failed: %d\n",
  2928. __func__, ret);
  2929. goto err;
  2930. }
  2931. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2932. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2933. if (ret < 0) {
  2934. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2935. goto err_irq;
  2936. }
  2937. /* default L1 power setting */
  2938. wcd937x->tx_ch_pwr[0] = 1;
  2939. wcd937x->tx_ch_pwr[1] = 1;
  2940. mutex_init(&wcd937x->micb_lock);
  2941. mutex_init(&wcd937x->ana_tx_clk_lock);
  2942. /* Request for watchdog interrupt */
  2943. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2944. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2945. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2946. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2947. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2948. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2949. /* Disable watchdog interrupt for HPH and AUX */
  2950. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2951. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2952. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2953. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2954. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2955. if (ret) {
  2956. dev_err(dev, "%s: Codec registration failed\n",
  2957. __func__);
  2958. goto err_irq;
  2959. }
  2960. return ret;
  2961. err_irq:
  2962. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2963. err:
  2964. component_unbind_all(dev, wcd937x);
  2965. err_bind_all:
  2966. dev_set_drvdata(dev, NULL);
  2967. kfree(pdata);
  2968. kfree(wcd937x);
  2969. return ret;
  2970. }
  2971. static void wcd937x_unbind(struct device *dev)
  2972. {
  2973. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2974. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2975. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2976. snd_soc_unregister_component(dev);
  2977. component_unbind_all(dev, wcd937x);
  2978. mutex_destroy(&wcd937x->micb_lock);
  2979. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2980. dev_set_drvdata(dev, NULL);
  2981. kfree(pdata);
  2982. kfree(wcd937x);
  2983. }
  2984. static const struct of_device_id wcd937x_dt_match[] = {
  2985. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  2986. {}
  2987. };
  2988. static const struct component_master_ops wcd937x_comp_ops = {
  2989. .bind = wcd937x_bind,
  2990. .unbind = wcd937x_unbind,
  2991. };
  2992. static int wcd937x_compare_of(struct device *dev, void *data)
  2993. {
  2994. return dev->of_node == data;
  2995. }
  2996. static void wcd937x_release_of(struct device *dev, void *data)
  2997. {
  2998. of_node_put(data);
  2999. }
  3000. static int wcd937x_add_slave_components(struct device *dev,
  3001. struct component_match **matchptr)
  3002. {
  3003. struct device_node *np, *rx_node, *tx_node;
  3004. np = dev->of_node;
  3005. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3006. if (!rx_node) {
  3007. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3008. return -ENODEV;
  3009. }
  3010. of_node_get(rx_node);
  3011. component_match_add_release(dev, matchptr,
  3012. wcd937x_release_of,
  3013. wcd937x_compare_of,
  3014. rx_node);
  3015. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3016. if (!tx_node) {
  3017. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3018. return -ENODEV;
  3019. }
  3020. of_node_get(tx_node);
  3021. component_match_add_release(dev, matchptr,
  3022. wcd937x_release_of,
  3023. wcd937x_compare_of,
  3024. tx_node);
  3025. return 0;
  3026. }
  3027. static int wcd937x_probe(struct platform_device *pdev)
  3028. {
  3029. struct component_match *match = NULL;
  3030. int ret;
  3031. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  3032. if (ret)
  3033. return ret;
  3034. return component_master_add_with_match(&pdev->dev,
  3035. &wcd937x_comp_ops, match);
  3036. }
  3037. static int wcd937x_remove(struct platform_device *pdev)
  3038. {
  3039. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  3040. dev_set_drvdata(&pdev->dev, NULL);
  3041. return 0;
  3042. }
  3043. #ifdef CONFIG_PM_SLEEP
  3044. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  3045. SET_SYSTEM_SLEEP_PM_OPS(
  3046. wcd937x_suspend,
  3047. wcd937x_resume
  3048. )
  3049. };
  3050. #endif
  3051. static struct platform_driver wcd937x_codec_driver = {
  3052. .probe = wcd937x_probe,
  3053. .remove = wcd937x_remove,
  3054. .driver = {
  3055. .name = "wcd937x_codec",
  3056. .owner = THIS_MODULE,
  3057. .of_match_table = of_match_ptr(wcd937x_dt_match),
  3058. #ifdef CONFIG_PM_SLEEP
  3059. .pm = &wcd937x_dev_pm_ops,
  3060. #endif
  3061. .suppress_bind_attrs = true,
  3062. },
  3063. };
  3064. module_platform_driver(wcd937x_codec_driver);
  3065. MODULE_DESCRIPTION("WCD937X Codec driver");
  3066. MODULE_LICENSE("GPL v2");