hal_8074v2_rx.h 16 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "hal_hw_headers.h"
  19. #include "hal_internal.h"
  20. #include "cdp_txrx_mon_struct.h"
  21. #include "qdf_trace.h"
  22. #include "hal_rx.h"
  23. #include "hal_tx.h"
  24. #include "dp_types.h"
  25. #include "hal_api_mon.h"
  26. #ifndef QCA_WIFI_QCA6018
  27. #include "phyrx_other_receive_info_su_evm_details.h"
  28. #endif
  29. #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
  30. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  31. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
  32. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
  33. RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
  34. #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
  35. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  36. RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
  37. RX_MSDU_END_5_DA_IS_MCBC_MASK, \
  38. RX_MSDU_END_5_DA_IS_MCBC_LSB))
  39. #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
  40. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  41. RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
  42. RX_MSDU_END_5_SA_IS_VALID_MASK, \
  43. RX_MSDU_END_5_SA_IS_VALID_LSB))
  44. #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
  45. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  46. RX_MSDU_END_13_SA_IDX_OFFSET)), \
  47. RX_MSDU_END_13_SA_IDX_MASK, \
  48. RX_MSDU_END_13_SA_IDX_LSB))
  49. #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
  50. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  51. RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
  52. RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
  53. RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
  54. #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
  55. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  56. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
  57. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \
  58. RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB))
  59. #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
  60. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  61. RX_MPDU_INFO_4_PN_31_0_OFFSET)), \
  62. RX_MPDU_INFO_4_PN_31_0_MASK, \
  63. RX_MPDU_INFO_4_PN_31_0_LSB))
  64. #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
  65. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  66. RX_MPDU_INFO_5_PN_63_32_OFFSET)), \
  67. RX_MPDU_INFO_5_PN_63_32_MASK, \
  68. RX_MPDU_INFO_5_PN_63_32_LSB))
  69. #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
  70. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  71. RX_MPDU_INFO_6_PN_95_64_OFFSET)), \
  72. RX_MPDU_INFO_6_PN_95_64_MASK, \
  73. RX_MPDU_INFO_6_PN_95_64_LSB))
  74. #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
  75. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  76. RX_MPDU_INFO_7_PN_127_96_OFFSET)), \
  77. RX_MPDU_INFO_7_PN_127_96_MASK, \
  78. RX_MPDU_INFO_7_PN_127_96_LSB))
  79. #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
  80. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  81. RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \
  82. RX_MSDU_END_5_FIRST_MSDU_MASK, \
  83. RX_MSDU_END_5_FIRST_MSDU_LSB))
  84. #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
  85. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  86. RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
  87. RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
  88. RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
  89. #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
  90. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  91. RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \
  92. RX_MSDU_END_5_DA_IS_VALID_MASK, \
  93. RX_MSDU_END_5_DA_IS_VALID_LSB))
  94. /*
  95. * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS
  96. * Interval from rx_msdu_start
  97. *
  98. * @buf: pointer to the start of RX PKT TLV header
  99. * Return: uint32_t(nss)
  100. */
  101. static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf)
  102. {
  103. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  104. struct rx_msdu_start *msdu_start =
  105. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  106. uint8_t mimo_ss_bitmap;
  107. mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
  108. return qdf_get_hweight8(mimo_ss_bitmap);
  109. }
  110. /**
  111. * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status
  112. *
  113. * @ hw_desc_addr: Start address of Rx HW TLVs
  114. * @ rs: Status for monitor mode
  115. *
  116. * Return: void
  117. */
  118. static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr,
  119. struct mon_rx_status *rs)
  120. {
  121. struct rx_msdu_start *rx_msdu_start;
  122. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  123. uint32_t reg_value;
  124. const uint32_t sgi_hw_to_cdp[] = {
  125. CDP_SGI_0_8_US,
  126. CDP_SGI_0_4_US,
  127. CDP_SGI_1_6_US,
  128. CDP_SGI_3_2_US,
  129. };
  130. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  131. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  132. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  133. RX_MSDU_START_5, USER_RSSI);
  134. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  135. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  136. rs->sgi = sgi_hw_to_cdp[reg_value];
  137. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  138. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  139. /* TODO: rs->beamformed should be set for SU beamforming also */
  140. }
  141. #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
  142. static uint32_t hal_get_link_desc_size_8074v2(void)
  143. {
  144. return LINK_DESC_SIZE;
  145. }
  146. /*
  147. * hal_rx_get_tlv_8074v2(): API to get the tlv
  148. *
  149. * @rx_tlv: TLV data extracted from the rx packet
  150. * Return: uint8_t
  151. */
  152. static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv)
  153. {
  154. return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  155. }
  156. #ifndef QCA_WIFI_QCA6018
  157. #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \
  158. (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \
  159. PHYRX_OTHER_RECEIVE_INFO, \
  160. SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM)
  161. static inline void
  162. hal_rx_update_su_evm_info(void *rx_tlv,
  163. void *ppdu_info_hdl)
  164. {
  165. struct hal_rx_ppdu_info *ppdu_info =
  166. (struct hal_rx_ppdu_info *)ppdu_info_hdl;
  167. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0);
  168. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1);
  169. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2);
  170. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3);
  171. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4);
  172. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5);
  173. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6);
  174. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7);
  175. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8);
  176. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9);
  177. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10);
  178. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11);
  179. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12);
  180. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13);
  181. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14);
  182. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15);
  183. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16);
  184. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17);
  185. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18);
  186. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19);
  187. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20);
  188. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21);
  189. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22);
  190. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23);
  191. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24);
  192. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25);
  193. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26);
  194. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27);
  195. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28);
  196. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29);
  197. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30);
  198. HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31);
  199. }
  200. /**
  201. * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2()
  202. * -process other receive info TLV
  203. * @rx_tlv_hdr: pointer to TLV header
  204. * @ppdu_info: pointer to ppdu_info
  205. *
  206. * Return: None
  207. */
  208. static
  209. void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr,
  210. void *ppdu_info_hdl)
  211. {
  212. uint16_t tlv_tag;
  213. void *rx_tlv;
  214. struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
  215. /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the
  216. * embedded TLVs inside
  217. */
  218. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  219. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  220. switch (tlv_tag) {
  221. case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E:
  222. /* Skip TLV length to get TLV content */
  223. rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  224. ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv,
  225. PHYRX_OTHER_RECEIVE_INFO,
  226. SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS);
  227. ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv,
  228. PHYRX_OTHER_RECEIVE_INFO,
  229. SU_EVM_DETAILS_0_PILOT_COUNT);
  230. ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv,
  231. PHYRX_OTHER_RECEIVE_INFO,
  232. SU_EVM_DETAILS_0_NSS_COUNT);
  233. hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl);
  234. break;
  235. }
  236. }
  237. #else
  238. static inline
  239. void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr,
  240. void *ppdu_info_hdl)
  241. {
  242. }
  243. #endif
  244. /**
  245. * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured
  246. * human readable format.
  247. * @ msdu_start: pointer the msdu_start TLV in pkt.
  248. * @ dbg_level: log level.
  249. *
  250. * Return: void
  251. */
  252. static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart,
  253. uint8_t dbg_level)
  254. {
  255. struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
  256. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  257. "rx_msdu_start tlv - "
  258. "rxpcu_mpdu_filter_in_category: %d "
  259. "sw_frame_group_id: %d "
  260. "phy_ppdu_id: %d "
  261. "msdu_length: %d "
  262. "ipsec_esp: %d "
  263. "l3_offset: %d "
  264. "ipsec_ah: %d "
  265. "l4_offset: %d "
  266. "msdu_number: %d "
  267. "decap_format: %d "
  268. "ipv4_proto: %d "
  269. "ipv6_proto: %d "
  270. "tcp_proto: %d "
  271. "udp_proto: %d "
  272. "ip_frag: %d "
  273. "tcp_only_ack: %d "
  274. "da_is_bcast_mcast: %d "
  275. "ip4_protocol_ip6_next_header: %d "
  276. "toeplitz_hash_2_or_4: %d "
  277. "flow_id_toeplitz: %d "
  278. "user_rssi: %d "
  279. "pkt_type: %d "
  280. "stbc: %d "
  281. "sgi: %d "
  282. "rate_mcs: %d "
  283. "receive_bandwidth: %d "
  284. "reception_type: %d "
  285. "ppdu_start_timestamp: %d "
  286. "sw_phy_meta_data: %d ",
  287. msdu_start->rxpcu_mpdu_filter_in_category,
  288. msdu_start->sw_frame_group_id,
  289. msdu_start->phy_ppdu_id,
  290. msdu_start->msdu_length,
  291. msdu_start->ipsec_esp,
  292. msdu_start->l3_offset,
  293. msdu_start->ipsec_ah,
  294. msdu_start->l4_offset,
  295. msdu_start->msdu_number,
  296. msdu_start->decap_format,
  297. msdu_start->ipv4_proto,
  298. msdu_start->ipv6_proto,
  299. msdu_start->tcp_proto,
  300. msdu_start->udp_proto,
  301. msdu_start->ip_frag,
  302. msdu_start->tcp_only_ack,
  303. msdu_start->da_is_bcast_mcast,
  304. msdu_start->ip4_protocol_ip6_next_header,
  305. msdu_start->toeplitz_hash_2_or_4,
  306. msdu_start->flow_id_toeplitz,
  307. msdu_start->user_rssi,
  308. msdu_start->pkt_type,
  309. msdu_start->stbc,
  310. msdu_start->sgi,
  311. msdu_start->rate_mcs,
  312. msdu_start->receive_bandwidth,
  313. msdu_start->reception_type,
  314. msdu_start->ppdu_start_timestamp,
  315. msdu_start->sw_phy_meta_data);
  316. }
  317. /**
  318. * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured
  319. * human readable format.
  320. * @ msdu_end: pointer the msdu_end TLV in pkt.
  321. * @ dbg_level: log level.
  322. *
  323. * Return: void
  324. */
  325. static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend,
  326. uint8_t dbg_level)
  327. {
  328. struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
  329. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  330. "rx_msdu_end tlv - "
  331. "rxpcu_mpdu_filter_in_category: %d "
  332. "sw_frame_group_id: %d "
  333. "phy_ppdu_id: %d "
  334. "ip_hdr_chksum: %d "
  335. "tcp_udp_chksum: %d "
  336. "key_id_octet: %d "
  337. "cce_super_rule: %d "
  338. "cce_classify_not_done_truncat: %d "
  339. "cce_classify_not_done_cce_dis: %d "
  340. "ext_wapi_pn_63_48: %d "
  341. "ext_wapi_pn_95_64: %d "
  342. "ext_wapi_pn_127_96: %d "
  343. "reported_mpdu_length: %d "
  344. "first_msdu: %d "
  345. "last_msdu: %d "
  346. "sa_idx_timeout: %d "
  347. "da_idx_timeout: %d "
  348. "msdu_limit_error: %d "
  349. "flow_idx_timeout: %d "
  350. "flow_idx_invalid: %d "
  351. "wifi_parser_error: %d "
  352. "amsdu_parser_error: %d "
  353. "sa_is_valid: %d "
  354. "da_is_valid: %d "
  355. "da_is_mcbc: %d "
  356. "l3_header_padding: %d "
  357. "ipv6_options_crc: %d "
  358. "tcp_seq_number: %d "
  359. "tcp_ack_number: %d "
  360. "tcp_flag: %d "
  361. "lro_eligible: %d "
  362. "window_size: %d "
  363. "da_offset: %d "
  364. "sa_offset: %d "
  365. "da_offset_valid: %d "
  366. "sa_offset_valid: %d "
  367. "rule_indication_31_0: %d "
  368. "rule_indication_63_32: %d "
  369. "sa_idx: %d "
  370. "msdu_drop: %d "
  371. "reo_destination_indication: %d "
  372. "flow_idx: %d "
  373. "fse_metadata: %d "
  374. "cce_metadata: %d "
  375. "sa_sw_peer_id: %d ",
  376. msdu_end->rxpcu_mpdu_filter_in_category,
  377. msdu_end->sw_frame_group_id,
  378. msdu_end->phy_ppdu_id,
  379. msdu_end->ip_hdr_chksum,
  380. msdu_end->tcp_udp_chksum,
  381. msdu_end->key_id_octet,
  382. msdu_end->cce_super_rule,
  383. msdu_end->cce_classify_not_done_truncate,
  384. msdu_end->cce_classify_not_done_cce_dis,
  385. msdu_end->ext_wapi_pn_63_48,
  386. msdu_end->ext_wapi_pn_95_64,
  387. msdu_end->ext_wapi_pn_127_96,
  388. msdu_end->reported_mpdu_length,
  389. msdu_end->first_msdu,
  390. msdu_end->last_msdu,
  391. msdu_end->sa_idx_timeout,
  392. msdu_end->da_idx_timeout,
  393. msdu_end->msdu_limit_error,
  394. msdu_end->flow_idx_timeout,
  395. msdu_end->flow_idx_invalid,
  396. msdu_end->wifi_parser_error,
  397. msdu_end->amsdu_parser_error,
  398. msdu_end->sa_is_valid,
  399. msdu_end->da_is_valid,
  400. msdu_end->da_is_mcbc,
  401. msdu_end->l3_header_padding,
  402. msdu_end->ipv6_options_crc,
  403. msdu_end->tcp_seq_number,
  404. msdu_end->tcp_ack_number,
  405. msdu_end->tcp_flag,
  406. msdu_end->lro_eligible,
  407. msdu_end->window_size,
  408. msdu_end->da_offset,
  409. msdu_end->sa_offset,
  410. msdu_end->da_offset_valid,
  411. msdu_end->sa_offset_valid,
  412. msdu_end->rule_indication_31_0,
  413. msdu_end->rule_indication_63_32,
  414. msdu_end->sa_idx,
  415. msdu_end->msdu_drop,
  416. msdu_end->reo_destination_indication,
  417. msdu_end->flow_idx,
  418. msdu_end->fse_metadata,
  419. msdu_end->cce_metadata,
  420. msdu_end->sa_sw_peer_id);
  421. }
  422. /*
  423. * Get tid from RX_MPDU_START
  424. */
  425. #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
  426. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  427. RX_MPDU_INFO_3_TID_OFFSET)), \
  428. RX_MPDU_INFO_3_TID_MASK, \
  429. RX_MPDU_INFO_3_TID_LSB))
  430. static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf)
  431. {
  432. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  433. struct rx_mpdu_start *mpdu_start =
  434. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  435. uint32_t tid;
  436. tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
  437. return tid;
  438. }
  439. #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
  440. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  441. RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
  442. RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
  443. RX_MSDU_START_5_RECEPTION_TYPE_LSB))
  444. /*
  445. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  446. * Interval from rx_msdu_start
  447. *
  448. * @buf: pointer to the start of RX PKT TLV header
  449. * Return: uint32_t(reception_type)
  450. */
  451. static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf)
  452. {
  453. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  454. struct rx_msdu_start *msdu_start =
  455. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  456. uint32_t reception_type;
  457. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  458. return reception_type;
  459. }
  460. /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */
  461. #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
  462. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  463. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
  464. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \
  465. RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB))
  466. /**
  467. * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx
  468. * from rx_msdu_end TLV
  469. *
  470. * @ buf: pointer to the start of RX PKT TLV headers
  471. * Return: da index
  472. */
  473. static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf)
  474. {
  475. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  476. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  477. uint16_t da_idx;
  478. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  479. return da_idx;
  480. }