dsi_display.c 216 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/list.h>
  6. #include <linux/of.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/err.h>
  9. #include "msm_drv.h"
  10. #include "sde_connector.h"
  11. #include "msm_mmu.h"
  12. #include "dsi_display.h"
  13. #include "dsi_panel.h"
  14. #include "dsi_ctrl.h"
  15. #include "dsi_ctrl_hw.h"
  16. #include "dsi_drm.h"
  17. #include "dsi_clk.h"
  18. #include "dsi_pwr.h"
  19. #include "sde_dbg.h"
  20. #include "dsi_parser.h"
  21. #define to_dsi_display(x) container_of(x, struct dsi_display, host)
  22. #define INT_BASE_10 10
  23. #define MISR_BUFF_SIZE 256
  24. #define ESD_MODE_STRING_MAX_LEN 256
  25. #define ESD_TRIGGER_STRING_MAX_LEN 10
  26. #define MAX_NAME_SIZE 64
  27. #define MAX_TE_RECHECKS 5
  28. #define DSI_CLOCK_BITRATE_RADIX 10
  29. #define MAX_TE_SOURCE_ID 2
  30. #define SEC_PANEL_NAME_MAX_LEN 256
  31. u8 dbgfs_tx_cmd_buf[SZ_4K];
  32. static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN];
  33. static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN];
  34. static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = {
  35. {.boot_param = dsi_display_primary},
  36. {.boot_param = dsi_display_secondary},
  37. };
  38. static void dsi_display_panel_id_notification(struct dsi_display *display);
  39. static const struct of_device_id dsi_display_dt_match[] = {
  40. {.compatible = "qcom,dsi-display"},
  41. {}
  42. };
  43. bool is_skip_op_required(struct dsi_display *display)
  44. {
  45. if (!display)
  46. return false;
  47. return (display->is_cont_splash_enabled || display->trusted_vm_env);
  48. }
  49. static bool is_sim_panel(struct dsi_display *display)
  50. {
  51. if (!display || !display->panel)
  52. return false;
  53. return display->panel->te_using_watchdog_timer;
  54. }
  55. static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display,
  56. u32 mask, bool enable)
  57. {
  58. int i;
  59. struct dsi_display_ctrl *ctrl;
  60. if (!display)
  61. return;
  62. display_for_each_ctrl(i, display) {
  63. ctrl = &display->ctrl[i];
  64. if ((!ctrl) || (!ctrl->ctrl))
  65. continue;
  66. mutex_lock(&ctrl->ctrl->ctrl_lock);
  67. dsi_ctrl_mask_error_status_interrupts(ctrl->ctrl, mask, enable);
  68. mutex_unlock(&ctrl->ctrl->ctrl_lock);
  69. }
  70. }
  71. static int dsi_display_config_clk_gating(struct dsi_display *display,
  72. bool enable)
  73. {
  74. int rc = 0, i = 0;
  75. struct dsi_display_ctrl *mctrl, *ctrl;
  76. enum dsi_clk_gate_type clk_selection;
  77. enum dsi_clk_gate_type const default_clk_select = PIXEL_CLK | DSI_PHY;
  78. if (!display) {
  79. DSI_ERR("Invalid params\n");
  80. return -EINVAL;
  81. }
  82. if (display->panel->host_config.force_hs_clk_lane) {
  83. DSI_DEBUG("no dsi clock gating for continuous clock mode\n");
  84. return 0;
  85. }
  86. mctrl = &display->ctrl[display->clk_master_idx];
  87. if (!mctrl) {
  88. DSI_ERR("Invalid controller\n");
  89. return -EINVAL;
  90. }
  91. clk_selection = display->clk_gating_config;
  92. if (!enable) {
  93. /* for disable path, make sure to disable all clk gating */
  94. clk_selection = DSI_CLK_ALL;
  95. } else if (!clk_selection || clk_selection > DSI_CLK_NONE) {
  96. /* Default selection, no overrides */
  97. clk_selection = default_clk_select;
  98. } else if (clk_selection == DSI_CLK_NONE) {
  99. clk_selection = 0;
  100. }
  101. DSI_DEBUG("%s clock gating Byte:%s Pixel:%s PHY:%s\n",
  102. enable ? "Enabling" : "Disabling",
  103. clk_selection & BYTE_CLK ? "yes" : "no",
  104. clk_selection & PIXEL_CLK ? "yes" : "no",
  105. clk_selection & DSI_PHY ? "yes" : "no");
  106. rc = dsi_ctrl_config_clk_gating(mctrl->ctrl, enable, clk_selection);
  107. if (rc) {
  108. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  109. display->name, enable ? "enable" : "disable",
  110. clk_selection, rc);
  111. return rc;
  112. }
  113. display_for_each_ctrl(i, display) {
  114. ctrl = &display->ctrl[i];
  115. if (!ctrl->ctrl || (ctrl == mctrl))
  116. continue;
  117. /**
  118. * In Split DSI usecase we should not enable clock gating on
  119. * DSI PHY1 to ensure no display atrifacts are seen.
  120. */
  121. clk_selection &= ~DSI_PHY;
  122. rc = dsi_ctrl_config_clk_gating(ctrl->ctrl, enable,
  123. clk_selection);
  124. if (rc) {
  125. DSI_ERR("[%s] failed to %s clk gating for clocks %d, rc=%d\n",
  126. display->name, enable ? "enable" : "disable",
  127. clk_selection, rc);
  128. return rc;
  129. }
  130. }
  131. return 0;
  132. }
  133. static void dsi_display_set_ctrl_esd_check_flag(struct dsi_display *display,
  134. bool enable)
  135. {
  136. int i;
  137. struct dsi_display_ctrl *ctrl;
  138. if (!display)
  139. return;
  140. display_for_each_ctrl(i, display) {
  141. ctrl = &display->ctrl[i];
  142. if (!ctrl)
  143. continue;
  144. ctrl->ctrl->esd_check_underway = enable;
  145. }
  146. }
  147. static void dsi_display_ctrl_irq_update(struct dsi_display *display, bool en)
  148. {
  149. int i;
  150. struct dsi_display_ctrl *ctrl;
  151. if (!display)
  152. return;
  153. display_for_each_ctrl(i, display) {
  154. ctrl = &display->ctrl[i];
  155. if (!ctrl)
  156. continue;
  157. dsi_ctrl_irq_update(ctrl->ctrl, en);
  158. }
  159. }
  160. void dsi_rect_intersect(const struct dsi_rect *r1,
  161. const struct dsi_rect *r2,
  162. struct dsi_rect *result)
  163. {
  164. int l, t, r, b;
  165. if (!r1 || !r2 || !result)
  166. return;
  167. l = max(r1->x, r2->x);
  168. t = max(r1->y, r2->y);
  169. r = min((r1->x + r1->w), (r2->x + r2->w));
  170. b = min((r1->y + r1->h), (r2->y + r2->h));
  171. if (r <= l || b <= t) {
  172. memset(result, 0, sizeof(*result));
  173. } else {
  174. result->x = l;
  175. result->y = t;
  176. result->w = r - l;
  177. result->h = b - t;
  178. }
  179. }
  180. int dsi_display_set_backlight(struct drm_connector *connector,
  181. void *display, u32 bl_lvl)
  182. {
  183. struct dsi_display *dsi_display = display;
  184. struct dsi_panel *panel;
  185. u32 bl_scale, bl_scale_sv;
  186. u64 bl_temp;
  187. int rc = 0;
  188. if (dsi_display == NULL || dsi_display->panel == NULL)
  189. return -EINVAL;
  190. panel = dsi_display->panel;
  191. mutex_lock(&panel->panel_lock);
  192. if (!dsi_panel_initialized(panel)) {
  193. rc = -EINVAL;
  194. goto error;
  195. }
  196. panel->bl_config.bl_level = bl_lvl;
  197. /* scale backlight */
  198. bl_scale = panel->bl_config.bl_scale;
  199. bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL;
  200. bl_scale_sv = panel->bl_config.bl_scale_sv;
  201. bl_temp = (u32)bl_temp * bl_scale_sv / MAX_SV_BL_SCALE_LEVEL;
  202. if (bl_temp > panel->bl_config.bl_max_level)
  203. bl_temp = panel->bl_config.bl_max_level;
  204. DSI_DEBUG("bl_scale = %u, bl_scale_sv = %u, bl_lvl = %u\n",
  205. bl_scale, bl_scale_sv, (u32)bl_temp);
  206. rc = dsi_panel_set_backlight(panel, (u32)bl_temp);
  207. if (rc)
  208. DSI_ERR("unable to set backlight\n");
  209. error:
  210. mutex_unlock(&panel->panel_lock);
  211. return rc;
  212. }
  213. static int dsi_display_cmd_engine_enable(struct dsi_display *display)
  214. {
  215. int rc = 0;
  216. int i;
  217. struct dsi_display_ctrl *m_ctrl, *ctrl;
  218. bool skip_op = is_skip_op_required(display);
  219. m_ctrl = &display->ctrl[display->cmd_master_idx];
  220. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  221. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  222. DSI_CTRL_ENGINE_ON, skip_op);
  223. if (rc) {
  224. DSI_ERR("[%s] enable mcmd engine failed, skip_op:%d rc:%d\n",
  225. display->name, skip_op, rc);
  226. goto done;
  227. }
  228. display_for_each_ctrl(i, display) {
  229. ctrl = &display->ctrl[i];
  230. if (!ctrl->ctrl || (ctrl == m_ctrl))
  231. continue;
  232. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  233. DSI_CTRL_ENGINE_ON, skip_op);
  234. if (rc) {
  235. DSI_ERR(
  236. "[%s] enable cmd engine failed, skip_op:%d rc:%d\n",
  237. display->name, skip_op, rc);
  238. goto error_disable_master;
  239. }
  240. }
  241. goto done;
  242. error_disable_master:
  243. (void)dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  244. DSI_CTRL_ENGINE_OFF, skip_op);
  245. done:
  246. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  247. return rc;
  248. }
  249. static int dsi_display_cmd_engine_disable(struct dsi_display *display)
  250. {
  251. int rc = 0;
  252. int i;
  253. struct dsi_display_ctrl *m_ctrl, *ctrl;
  254. bool skip_op = is_skip_op_required(display);
  255. m_ctrl = &display->ctrl[display->cmd_master_idx];
  256. mutex_lock(&m_ctrl->ctrl->ctrl_lock);
  257. display_for_each_ctrl(i, display) {
  258. ctrl = &display->ctrl[i];
  259. if (!ctrl->ctrl || (ctrl == m_ctrl))
  260. continue;
  261. rc = dsi_ctrl_set_cmd_engine_state(ctrl->ctrl,
  262. DSI_CTRL_ENGINE_OFF, skip_op);
  263. if (rc)
  264. DSI_ERR(
  265. "[%s] disable cmd engine failed, skip_op:%d rc:%d\n",
  266. display->name, skip_op, rc);
  267. }
  268. rc = dsi_ctrl_set_cmd_engine_state(m_ctrl->ctrl,
  269. DSI_CTRL_ENGINE_OFF, skip_op);
  270. if (rc)
  271. DSI_ERR("[%s] disable mcmd engine failed, skip_op:%d rc:%d\n",
  272. display->name, skip_op, rc);
  273. mutex_unlock(&m_ctrl->ctrl->ctrl_lock);
  274. return rc;
  275. }
  276. static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach)
  277. {
  278. struct dsi_display *display;
  279. struct dsi_display_ctrl *display_ctrl;
  280. int rc, cnt;
  281. if (!cb_data) {
  282. DSI_ERR("aspace cb called with invalid cb_data\n");
  283. return;
  284. }
  285. display = (struct dsi_display *)cb_data;
  286. /*
  287. * acquire panel_lock to make sure no commands are in-progress
  288. * while detaching the non-secure context banks
  289. */
  290. dsi_panel_acquire_panel_lock(display->panel);
  291. if (is_detach) {
  292. /* invalidate the stored iova */
  293. display->cmd_buffer_iova = 0;
  294. /* return the virtual address mapping */
  295. msm_gem_put_vaddr(display->tx_cmd_buf);
  296. msm_gem_vunmap(display->tx_cmd_buf, OBJ_LOCK_NORMAL);
  297. } else {
  298. rc = msm_gem_get_iova(display->tx_cmd_buf,
  299. display->aspace, &(display->cmd_buffer_iova));
  300. if (rc) {
  301. DSI_ERR("failed to get the iova rc %d\n", rc);
  302. goto end;
  303. }
  304. display->vaddr =
  305. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  306. if (IS_ERR_OR_NULL(display->vaddr)) {
  307. DSI_ERR("failed to get va rc %d\n", rc);
  308. goto end;
  309. }
  310. }
  311. display_for_each_ctrl(cnt, display) {
  312. display_ctrl = &display->ctrl[cnt];
  313. display_ctrl->ctrl->cmd_buffer_size = display->cmd_buffer_size;
  314. display_ctrl->ctrl->cmd_buffer_iova = display->cmd_buffer_iova;
  315. display_ctrl->ctrl->vaddr = display->vaddr;
  316. display_ctrl->ctrl->secure_mode = is_detach;
  317. }
  318. end:
  319. /* release panel_lock */
  320. dsi_panel_release_panel_lock(display->panel);
  321. }
  322. static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data)
  323. {
  324. struct dsi_display *display = (struct dsi_display *)data;
  325. /*
  326. * This irq handler is used for sole purpose of identifying
  327. * ESD attacks on panel and we can safely assume IRQ_HANDLED
  328. * in case of display not being initialized yet
  329. */
  330. if (!display)
  331. return IRQ_HANDLED;
  332. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  333. complete_all(&display->esd_te_gate);
  334. return IRQ_HANDLED;
  335. }
  336. static void dsi_display_change_te_irq_status(struct dsi_display *display,
  337. bool enable)
  338. {
  339. if (!display) {
  340. DSI_ERR("Invalid params\n");
  341. return;
  342. }
  343. /* Handle unbalanced irq enable/disable calls */
  344. if (enable && !display->is_te_irq_enabled) {
  345. enable_irq(gpio_to_irq(display->disp_te_gpio));
  346. display->is_te_irq_enabled = true;
  347. } else if (!enable && display->is_te_irq_enabled) {
  348. disable_irq(gpio_to_irq(display->disp_te_gpio));
  349. display->is_te_irq_enabled = false;
  350. }
  351. }
  352. static void dsi_display_register_te_irq(struct dsi_display *display)
  353. {
  354. int rc = 0;
  355. struct platform_device *pdev;
  356. struct device *dev;
  357. unsigned int te_irq;
  358. pdev = display->pdev;
  359. if (!pdev) {
  360. DSI_ERR("invalid platform device\n");
  361. return;
  362. }
  363. dev = &pdev->dev;
  364. if (!dev) {
  365. DSI_ERR("invalid device\n");
  366. return;
  367. }
  368. if (display->trusted_vm_env) {
  369. DSI_INFO("GPIO's are not enabled in trusted VM\n");
  370. return;
  371. }
  372. if (!gpio_is_valid(display->disp_te_gpio)) {
  373. rc = -EINVAL;
  374. goto error;
  375. }
  376. init_completion(&display->esd_te_gate);
  377. te_irq = gpio_to_irq(display->disp_te_gpio);
  378. /* Avoid deferred spurious irqs with disable_irq() */
  379. irq_set_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  380. rc = devm_request_irq(dev, te_irq, dsi_display_panel_te_irq_handler,
  381. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  382. "TE_GPIO", display);
  383. if (rc) {
  384. DSI_ERR("TE request_irq failed for ESD rc:%d\n", rc);
  385. irq_clear_status_flags(te_irq, IRQ_DISABLE_UNLAZY);
  386. goto error;
  387. }
  388. disable_irq(te_irq);
  389. display->is_te_irq_enabled = false;
  390. return;
  391. error:
  392. /* disable the TE based ESD check */
  393. DSI_WARN("Unable to register for TE IRQ\n");
  394. if (display->panel->esd_config.status_mode == ESD_MODE_PANEL_TE)
  395. display->panel->esd_config.esd_enabled = false;
  396. }
  397. /* Allocate memory for cmd dma tx buffer */
  398. static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display)
  399. {
  400. int rc = 0, cnt = 0;
  401. struct dsi_display_ctrl *display_ctrl;
  402. display->tx_cmd_buf = msm_gem_new(display->drm_dev,
  403. SZ_4K,
  404. MSM_BO_UNCACHED);
  405. if ((display->tx_cmd_buf) == NULL) {
  406. DSI_ERR("Failed to allocate cmd tx buf memory\n");
  407. rc = -ENOMEM;
  408. goto error;
  409. }
  410. display->cmd_buffer_size = SZ_4K;
  411. display->aspace = msm_gem_smmu_address_space_get(
  412. display->drm_dev, MSM_SMMU_DOMAIN_UNSECURE);
  413. if (PTR_ERR(display->aspace) == -ENODEV) {
  414. display->aspace = NULL;
  415. DSI_DEBUG("IOMMU not present, relying on VRAM\n");
  416. } else if (IS_ERR_OR_NULL(display->aspace)) {
  417. rc = PTR_ERR(display->aspace);
  418. display->aspace = NULL;
  419. DSI_ERR("failed to get aspace %d\n", rc);
  420. goto free_gem;
  421. } else if (display->aspace) {
  422. /* register to aspace */
  423. rc = msm_gem_address_space_register_cb(display->aspace,
  424. dsi_display_aspace_cb_locked, (void *)display);
  425. if (rc) {
  426. DSI_ERR("failed to register callback %d\n", rc);
  427. goto free_gem;
  428. }
  429. }
  430. rc = msm_gem_get_iova(display->tx_cmd_buf, display->aspace,
  431. &(display->cmd_buffer_iova));
  432. if (rc) {
  433. DSI_ERR("failed to get the iova rc %d\n", rc);
  434. goto free_aspace_cb;
  435. }
  436. display->vaddr =
  437. (void *) msm_gem_get_vaddr(display->tx_cmd_buf);
  438. if (IS_ERR_OR_NULL(display->vaddr)) {
  439. DSI_ERR("failed to get va rc %d\n", rc);
  440. rc = -EINVAL;
  441. goto put_iova;
  442. }
  443. display_for_each_ctrl(cnt, display) {
  444. display_ctrl = &display->ctrl[cnt];
  445. display_ctrl->ctrl->cmd_buffer_size = SZ_4K;
  446. display_ctrl->ctrl->cmd_buffer_iova =
  447. display->cmd_buffer_iova;
  448. display_ctrl->ctrl->vaddr = display->vaddr;
  449. display_ctrl->ctrl->tx_cmd_buf = display->tx_cmd_buf;
  450. }
  451. return rc;
  452. put_iova:
  453. msm_gem_put_iova(display->tx_cmd_buf, display->aspace);
  454. free_aspace_cb:
  455. msm_gem_address_space_unregister_cb(display->aspace,
  456. dsi_display_aspace_cb_locked, display);
  457. free_gem:
  458. mutex_lock(&display->drm_dev->struct_mutex);
  459. msm_gem_free_object(display->tx_cmd_buf);
  460. mutex_unlock(&display->drm_dev->struct_mutex);
  461. error:
  462. return rc;
  463. }
  464. static bool dsi_display_validate_reg_read(struct dsi_panel *panel)
  465. {
  466. int i, j = 0;
  467. int len = 0, *lenp;
  468. int group = 0, count = 0;
  469. struct drm_panel_esd_config *config;
  470. if (!panel)
  471. return false;
  472. config = &(panel->esd_config);
  473. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  474. count = config->status_cmd.count;
  475. for (i = 0; i < count; i++)
  476. len += lenp[i];
  477. for (i = 0; i < len; i++)
  478. j += len;
  479. for (j = 0; j < config->groups; ++j) {
  480. for (i = 0; i < len; ++i) {
  481. if (config->return_buf[i] !=
  482. config->status_value[group + i]) {
  483. DRM_ERROR("mismatch: 0x%x\n",
  484. config->return_buf[i]);
  485. break;
  486. }
  487. }
  488. if (i == len)
  489. return true;
  490. group += len;
  491. }
  492. return false;
  493. }
  494. static void dsi_display_parse_demura_data(struct dsi_display *display)
  495. {
  496. int rc = 0;
  497. display->panel_id = ~0x0;
  498. if (display->fw) {
  499. DSI_DEBUG("FW definition unsupported for Demura panel data\n");
  500. return;
  501. }
  502. rc = of_property_read_u64(display->pdev->dev.of_node,
  503. "qcom,demura-panel-id", &display->panel_id);
  504. if (rc) {
  505. DSI_DEBUG("No panel ID is present for this display\n");
  506. } else if (!display->panel_id) {
  507. DSI_DEBUG("Dummy panel ID node present for this display\n");
  508. display->panel_id = ~0x0;
  509. } else {
  510. DSI_DEBUG("panel id found: %lx\n", display->panel_id);
  511. }
  512. }
  513. static void dsi_display_parse_te_data(struct dsi_display *display)
  514. {
  515. struct platform_device *pdev;
  516. struct device *dev;
  517. int rc = 0;
  518. u32 val = 0;
  519. pdev = display->pdev;
  520. if (!pdev) {
  521. DSI_ERR("Invalid platform device\n");
  522. return;
  523. }
  524. dev = &pdev->dev;
  525. if (!dev) {
  526. DSI_ERR("Invalid platform device\n");
  527. return;
  528. }
  529. display->disp_te_gpio = of_get_named_gpio(dev->of_node,
  530. "qcom,platform-te-gpio", 0);
  531. if (display->fw)
  532. rc = dsi_parser_read_u32(display->parser_node,
  533. "qcom,panel-te-source", &val);
  534. else
  535. rc = of_property_read_u32(dev->of_node,
  536. "qcom,panel-te-source", &val);
  537. if (rc || (val > MAX_TE_SOURCE_ID)) {
  538. DSI_ERR("invalid vsync source selection\n");
  539. val = 0;
  540. }
  541. display->te_source = val;
  542. }
  543. static void dsi_display_set_cmd_tx_ctrl_flags(struct dsi_display *display,
  544. struct dsi_cmd_desc *cmd)
  545. {
  546. struct dsi_display_ctrl *ctrl, *m_ctrl;
  547. struct mipi_dsi_msg *msg = &cmd->msg;
  548. u32 flags = 0;
  549. int i = 0;
  550. m_ctrl = &display->ctrl[display->clk_master_idx];
  551. display_for_each_ctrl(i, display) {
  552. ctrl = &display->ctrl[i];
  553. if (!ctrl->ctrl)
  554. continue;
  555. /*
  556. * Set cmd transfer mode flags.
  557. * 1) Default selection is CMD fetch from memory.
  558. * 2) In secure session override and use FIFO rather than
  559. * memory.
  560. * 3) If cmd_len is greater than FIFO size non embedded mode of
  561. * tx is used.
  562. */
  563. flags = DSI_CTRL_CMD_FETCH_MEMORY;
  564. if (ctrl->ctrl->secure_mode) {
  565. flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
  566. flags |= DSI_CTRL_CMD_FIFO_STORE;
  567. } else if (msg->tx_len > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) {
  568. flags |= DSI_CTRL_CMD_NON_EMBEDDED_MODE;
  569. }
  570. /* Set flags needed for broadcast. Read commands are always unicast */
  571. if (!(msg->flags & MIPI_DSI_MSG_UNICAST_COMMAND) && (display->ctrl_count > 1))
  572. flags |= DSI_CTRL_CMD_BROADCAST | DSI_CTRL_CMD_DEFER_TRIGGER;
  573. /*
  574. * Set flags for command scheduling.
  575. * 1) In video mode command DMA scheduling is default.
  576. * 2) In command mode command DMA scheduling depends on message
  577. * flag and TE needs to be running.
  578. */
  579. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  580. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  581. } else {
  582. if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED)
  583. flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  584. if (!display->enabled)
  585. flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
  586. }
  587. /* Set flags for last command */
  588. if (!(msg->flags & MIPI_DSI_MSG_BATCH_COMMAND))
  589. flags |= DSI_CTRL_CMD_LAST_COMMAND;
  590. /*
  591. * Set flags for asynchronous wait.
  592. * Asynchronous wait is supported in the following scenarios
  593. * 1) queue_cmd_waits is set by connector and
  594. * - commands are not sent using DSI FIFO memory
  595. * - commands are not sent in non-embedded mode
  596. * - no explicit msg post_wait_ms is specified
  597. * - not a read command
  598. * 2) if async override msg flag is present
  599. */
  600. if (display->queue_cmd_waits)
  601. if (!(flags & DSI_CTRL_CMD_FIFO_STORE) &&
  602. !(flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) &&
  603. (cmd->post_wait_ms == 0) &&
  604. !(cmd->ctrl_flags & DSI_CTRL_CMD_READ))
  605. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  606. if (msg->flags & MIPI_DSI_MSG_ASYNC_OVERRIDE)
  607. flags |= DSI_CTRL_CMD_ASYNC_WAIT;
  608. }
  609. cmd->ctrl_flags |= flags;
  610. }
  611. static int dsi_display_read_status(struct dsi_display_ctrl *ctrl,
  612. struct dsi_display *display)
  613. {
  614. int i, rc = 0, count = 0, start = 0, *lenp;
  615. struct drm_panel_esd_config *config;
  616. struct dsi_cmd_desc *cmds;
  617. struct dsi_panel *panel;
  618. u32 flags = 0;
  619. if (!display->panel || !ctrl || !ctrl->ctrl)
  620. return -EINVAL;
  621. panel = display->panel;
  622. /*
  623. * When DSI controller is not in initialized state, we do not want to
  624. * report a false ESD failure and hence we defer until next read
  625. * happen.
  626. */
  627. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  628. return 1;
  629. config = &(panel->esd_config);
  630. lenp = config->status_valid_params ?: config->status_cmds_rlen;
  631. count = config->status_cmd.count;
  632. cmds = config->status_cmd.cmds;
  633. flags = DSI_CTRL_CMD_READ;
  634. for (i = 0; i < count; ++i) {
  635. memset(config->status_buf, 0x0, SZ_4K);
  636. if (config->status_cmd.state == DSI_CMD_SET_STATE_LP)
  637. cmds[i].msg.flags |= MIPI_DSI_MSG_USE_LPM;
  638. cmds[i].msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  639. cmds[i].msg.rx_buf = config->status_buf;
  640. cmds[i].msg.rx_len = config->status_cmds_rlen[i];
  641. cmds[i].ctrl_flags = flags;
  642. dsi_display_set_cmd_tx_ctrl_flags(display,&cmds[i]);
  643. rc = dsi_ctrl_transfer_prepare(ctrl->ctrl, cmds[i].ctrl_flags);
  644. if (rc) {
  645. DSI_ERR("prepare for rx cmd transfer failed rc=%d\n", rc);
  646. return rc;
  647. }
  648. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &cmds[i]);
  649. if (rc <= 0) {
  650. DSI_ERR("rx cmd transfer failed rc=%d\n", rc);
  651. } else {
  652. memcpy(config->return_buf + start,
  653. config->status_buf, lenp[i]);
  654. start += lenp[i];
  655. }
  656. dsi_ctrl_transfer_unprepare(ctrl->ctrl, cmds[i].ctrl_flags);
  657. }
  658. return rc;
  659. }
  660. static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl,
  661. struct dsi_display *display)
  662. {
  663. int rc = 0;
  664. rc = dsi_display_read_status(ctrl, display);
  665. if (rc <= 0) {
  666. goto exit;
  667. } else {
  668. /*
  669. * panel status read successfully.
  670. * check for validity of the data read back.
  671. */
  672. rc = dsi_display_validate_reg_read(display->panel);
  673. if (!rc) {
  674. rc = -EINVAL;
  675. goto exit;
  676. }
  677. }
  678. exit:
  679. return rc;
  680. }
  681. static int dsi_display_status_reg_read(struct dsi_display *display)
  682. {
  683. int rc = 0, i;
  684. struct dsi_display_ctrl *m_ctrl, *ctrl;
  685. DSI_DEBUG(" ++\n");
  686. m_ctrl = &display->ctrl[display->cmd_master_idx];
  687. if (display->tx_cmd_buf == NULL) {
  688. rc = dsi_host_alloc_cmd_tx_buffer(display);
  689. if (rc) {
  690. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  691. goto done;
  692. }
  693. }
  694. rc = dsi_display_validate_status(m_ctrl, display);
  695. if (rc <= 0) {
  696. DSI_ERR("[%s] read status failed on master,rc=%d\n",
  697. display->name, rc);
  698. goto done;
  699. }
  700. if (!display->panel->sync_broadcast_en)
  701. goto done;
  702. display_for_each_ctrl(i, display) {
  703. ctrl = &display->ctrl[i];
  704. if (ctrl == m_ctrl)
  705. continue;
  706. rc = dsi_display_validate_status(ctrl, display);
  707. if (rc <= 0) {
  708. DSI_ERR("[%s] read status failed on slave,rc=%d\n",
  709. display->name, rc);
  710. goto done;
  711. }
  712. }
  713. done:
  714. return rc;
  715. }
  716. static int dsi_display_status_bta_request(struct dsi_display *display)
  717. {
  718. int rc = 0;
  719. DSI_DEBUG(" ++\n");
  720. /* TODO: trigger SW BTA and wait for acknowledgment */
  721. return rc;
  722. }
  723. static void dsi_display_release_te_irq(struct dsi_display *display)
  724. {
  725. int te_irq = 0;
  726. te_irq = gpio_to_irq(display->disp_te_gpio);
  727. if (te_irq)
  728. free_irq(te_irq, display);
  729. }
  730. static int dsi_display_status_check_te(struct dsi_display *display,
  731. int rechecks)
  732. {
  733. int rc = 1, i = 0;
  734. int const esd_te_timeout = msecs_to_jiffies(3*20);
  735. if (!rechecks)
  736. return rc;
  737. /* register te irq handler */
  738. dsi_display_register_te_irq(display);
  739. dsi_display_change_te_irq_status(display, true);
  740. for (i = 0; i < rechecks; i++) {
  741. reinit_completion(&display->esd_te_gate);
  742. if (!wait_for_completion_timeout(&display->esd_te_gate,
  743. esd_te_timeout)) {
  744. DSI_ERR("TE check failed\n");
  745. dsi_display_change_te_irq_status(display, false);
  746. return -EINVAL;
  747. }
  748. }
  749. dsi_display_change_te_irq_status(display, false);
  750. dsi_display_release_te_irq(display);
  751. return rc;
  752. }
  753. int dsi_display_check_status(struct drm_connector *connector, void *display,
  754. bool te_check_override)
  755. {
  756. struct dsi_display *dsi_display = display;
  757. struct dsi_panel *panel;
  758. u32 status_mode;
  759. int rc = 0x1;
  760. int te_rechecks = 1;
  761. if (!dsi_display || !dsi_display->panel)
  762. return -EINVAL;
  763. panel = dsi_display->panel;
  764. dsi_panel_acquire_panel_lock(panel);
  765. if (!panel->panel_initialized) {
  766. DSI_DEBUG("Panel not initialized\n");
  767. goto release_panel_lock;
  768. }
  769. /* Prevent another ESD check,when ESD recovery is underway */
  770. if (atomic_read(&panel->esd_recovery_pending))
  771. goto release_panel_lock;
  772. status_mode = panel->esd_config.status_mode;
  773. if ((status_mode == ESD_MODE_SW_SIM_SUCCESS) || is_sim_panel(display))
  774. goto release_panel_lock;
  775. if (status_mode == ESD_MODE_SW_SIM_FAILURE) {
  776. rc = -EINVAL;
  777. goto release_panel_lock;
  778. }
  779. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, status_mode, te_check_override);
  780. if (te_check_override)
  781. te_rechecks = MAX_TE_RECHECKS;
  782. if ((dsi_display->trusted_vm_env) ||
  783. (panel->panel_mode == DSI_OP_VIDEO_MODE))
  784. te_rechecks = 0;
  785. dsi_display_set_ctrl_esd_check_flag(dsi_display, true);
  786. if (status_mode == ESD_MODE_REG_READ) {
  787. rc = dsi_display_status_reg_read(dsi_display);
  788. } else if (status_mode == ESD_MODE_SW_BTA) {
  789. rc = dsi_display_status_bta_request(dsi_display);
  790. } else if (status_mode == ESD_MODE_PANEL_TE) {
  791. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  792. te_check_override = false;
  793. } else {
  794. DSI_WARN("Unsupported check status mode: %d\n", status_mode);
  795. panel->esd_config.esd_enabled = false;
  796. }
  797. if (rc <= 0 && te_check_override)
  798. rc = dsi_display_status_check_te(dsi_display, te_rechecks);
  799. if (rc > 0) {
  800. dsi_display_set_ctrl_esd_check_flag(dsi_display, false);
  801. if (te_check_override && panel->esd_config.esd_enabled == false)
  802. rc = dsi_display_status_check_te(dsi_display,
  803. te_rechecks);
  804. }
  805. /* Handle Panel failures during display disable sequence */
  806. if (rc <=0)
  807. atomic_set(&panel->esd_recovery_pending, 1);
  808. release_panel_lock:
  809. dsi_panel_release_panel_lock(panel);
  810. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, rc);
  811. return rc;
  812. }
  813. static int dsi_display_ctrl_get_host_init_state(struct dsi_display *dsi_display,
  814. bool *state)
  815. {
  816. struct dsi_display_ctrl *ctrl;
  817. int i, rc = -EINVAL;
  818. display_for_each_ctrl(i, dsi_display) {
  819. ctrl = &dsi_display->ctrl[i];
  820. rc = dsi_ctrl_get_host_engine_init_state(ctrl->ctrl, state);
  821. if (rc)
  822. break;
  823. }
  824. return rc;
  825. }
  826. static int dsi_display_cmd_rx(struct dsi_display *display,
  827. struct dsi_cmd_desc *cmd)
  828. {
  829. struct dsi_display_ctrl *m_ctrl = NULL;
  830. u32 flags = 0;
  831. int rc = 0;
  832. if (!display || !display->panel)
  833. return -EINVAL;
  834. m_ctrl = &display->ctrl[display->cmd_master_idx];
  835. if (!m_ctrl || !m_ctrl->ctrl)
  836. return -EINVAL;
  837. /* acquire panel_lock to make sure no commands are in progress */
  838. dsi_panel_acquire_panel_lock(display->panel);
  839. if (!display->panel->panel_initialized) {
  840. DSI_DEBUG("panel not initialized\n");
  841. goto release_panel_lock;
  842. }
  843. flags = DSI_CTRL_CMD_READ;
  844. cmd->ctrl_flags = flags;
  845. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  846. rc = dsi_ctrl_transfer_prepare(m_ctrl->ctrl, cmd->ctrl_flags);
  847. if (rc) {
  848. DSI_ERR("prepare for rx cmd transfer failed rc = %d\n", rc);
  849. goto release_panel_lock;
  850. }
  851. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  852. if (rc <= 0)
  853. DSI_ERR("rx cmd transfer failed rc = %d\n", rc);
  854. dsi_ctrl_transfer_unprepare(m_ctrl->ctrl, cmd->ctrl_flags);
  855. release_panel_lock:
  856. dsi_panel_release_panel_lock(display->panel);
  857. return rc;
  858. }
  859. int dsi_display_cmd_transfer(struct drm_connector *connector,
  860. void *display, const char *cmd_buf,
  861. u32 cmd_buf_len)
  862. {
  863. struct dsi_display *dsi_display = display;
  864. int rc = 0, cnt = 0, i = 0;
  865. bool state = false, transfer = false;
  866. struct dsi_panel_cmd_set *set;
  867. if (!dsi_display || !cmd_buf) {
  868. DSI_ERR("[DSI] invalid params\n");
  869. return -EINVAL;
  870. }
  871. DSI_DEBUG("[DSI] Display command transfer\n");
  872. if (!(cmd_buf[3] & MIPI_DSI_MSG_BATCH_COMMAND))
  873. transfer = true;
  874. mutex_lock(&dsi_display->display_lock);
  875. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  876. /**
  877. * Handle scenario where a command transfer is initiated through
  878. * sysfs interface when device is in suepnd state.
  879. */
  880. if (!rc && !state) {
  881. pr_warn_ratelimited("Command xfer attempted while device is in suspend state\n"
  882. );
  883. rc = -EPERM;
  884. goto end;
  885. }
  886. if (rc || !state) {
  887. DSI_ERR("[DSI] Invalid host state %d rc %d\n",
  888. state, rc);
  889. rc = -EPERM;
  890. goto end;
  891. }
  892. /*
  893. * Reset the dbgfs buffer if the commands sent exceed the available
  894. * buffer size. For video mode, limiting the buffer size to 2K to
  895. * ensure no performance issues.
  896. */
  897. if (dsi_display->panel->panel_mode == DSI_OP_CMD_MODE) {
  898. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_4K) {
  899. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  900. dsi_display->tx_cmd_buf_ndx = 0;
  901. }
  902. } else {
  903. if ((dsi_display->tx_cmd_buf_ndx + cmd_buf_len) > SZ_2K) {
  904. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  905. dsi_display->tx_cmd_buf_ndx = 0;
  906. }
  907. }
  908. memcpy(&dbgfs_tx_cmd_buf[dsi_display->tx_cmd_buf_ndx], cmd_buf,
  909. cmd_buf_len);
  910. dsi_display->tx_cmd_buf_ndx += cmd_buf_len;
  911. if (transfer) {
  912. struct dsi_cmd_desc *cmds;
  913. set = &dsi_display->cmd_set;
  914. set->count = 0;
  915. dsi_panel_get_cmd_pkt_count(dbgfs_tx_cmd_buf,
  916. dsi_display->tx_cmd_buf_ndx, &cnt);
  917. dsi_panel_alloc_cmd_packets(set, cnt);
  918. dsi_panel_create_cmd_packets(dbgfs_tx_cmd_buf,
  919. dsi_display->tx_cmd_buf_ndx, cnt, set->cmds);
  920. cmds = set->cmds;
  921. dsi_display->tx_cmd_buf_ndx = 0;
  922. for (i = 0; i < cnt; i++) {
  923. rc = dsi_host_transfer_sub(&dsi_display->host, cmds);
  924. if (rc < 0) {
  925. DSI_ERR("failed to send command, rc=%d\n", rc);
  926. break;
  927. }
  928. if (cmds->post_wait_ms)
  929. usleep_range(cmds->post_wait_ms*1000,
  930. ((cmds->post_wait_ms*1000)+10));
  931. cmds++;
  932. }
  933. memset(dbgfs_tx_cmd_buf, 0, SZ_4K);
  934. dsi_panel_destroy_cmd_packets(set);
  935. dsi_panel_dealloc_cmd_packets(set);
  936. }
  937. end:
  938. mutex_unlock(&dsi_display->display_lock);
  939. return rc;
  940. }
  941. static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
  942. bool enable)
  943. {
  944. int i;
  945. struct dsi_display_ctrl *ctrl;
  946. if (!display || !display->panel->host_config.force_hs_clk_lane)
  947. return;
  948. display_for_each_ctrl(i, display) {
  949. ctrl = &display->ctrl[i];
  950. /*
  951. * For phy ver 4.0 chipsets, configure DSI controller and
  952. * DSI PHY to force clk lane to HS mode always whereas
  953. * for other phy ver chipsets, configure DSI controller only.
  954. */
  955. if (ctrl->phy->hw.ops.set_continuous_clk) {
  956. dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
  957. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  958. dsi_phy_set_continuous_clk(ctrl->phy, enable);
  959. } else {
  960. dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
  961. }
  962. }
  963. }
  964. int dsi_display_cmd_receive(void *display, const char *cmd_buf,
  965. u32 cmd_buf_len, u8 *recv_buf, u32 recv_buf_len)
  966. {
  967. struct dsi_display *dsi_display = display;
  968. struct dsi_cmd_desc cmd = {};
  969. bool state = false;
  970. int rc = -1;
  971. if (!dsi_display || !cmd_buf || !recv_buf) {
  972. DSI_ERR("[DSI] invalid params\n");
  973. return -EINVAL;
  974. }
  975. rc = dsi_panel_create_cmd_packets(cmd_buf, cmd_buf_len, 1, &cmd);
  976. if (rc) {
  977. DSI_ERR("[DSI] command packet create failed, rc = %d\n", rc);
  978. return rc;
  979. }
  980. cmd.msg.rx_buf = recv_buf;
  981. cmd.msg.rx_len = recv_buf_len;
  982. cmd.msg.flags |= MIPI_DSI_MSG_UNICAST_COMMAND;
  983. mutex_lock(&dsi_display->display_lock);
  984. if (is_sim_panel(display)) {
  985. DSI_DEBUG("Simulation panel doesn't support read commands\n");
  986. goto end;
  987. }
  988. rc = dsi_display_ctrl_get_host_init_state(dsi_display, &state);
  989. if (rc || !state) {
  990. DSI_ERR("[DSI] Invalid host state = %d rc = %d\n",
  991. state, rc);
  992. rc = -EPERM;
  993. goto end;
  994. }
  995. rc = dsi_display_cmd_rx(dsi_display, &cmd);
  996. if (rc <= 0)
  997. DSI_ERR("[DSI] Display command receive failed, rc=%d\n", rc);
  998. end:
  999. mutex_unlock(&dsi_display->display_lock);
  1000. return rc;
  1001. }
  1002. int dsi_display_soft_reset(void *display)
  1003. {
  1004. struct dsi_display *dsi_display;
  1005. struct dsi_display_ctrl *ctrl;
  1006. int rc = 0;
  1007. int i;
  1008. if (!display)
  1009. return -EINVAL;
  1010. dsi_display = display;
  1011. display_for_each_ctrl(i, dsi_display) {
  1012. ctrl = &dsi_display->ctrl[i];
  1013. rc = dsi_ctrl_soft_reset(ctrl->ctrl);
  1014. if (rc) {
  1015. DSI_ERR("[%s] failed to soft reset host_%d, rc=%d\n",
  1016. dsi_display->name, i, rc);
  1017. break;
  1018. }
  1019. }
  1020. return rc;
  1021. }
  1022. enum dsi_pixel_format dsi_display_get_dst_format(
  1023. struct drm_connector *connector,
  1024. void *display)
  1025. {
  1026. enum dsi_pixel_format format = DSI_PIXEL_FORMAT_MAX;
  1027. struct dsi_display *dsi_display = (struct dsi_display *)display;
  1028. if (!dsi_display || !dsi_display->panel) {
  1029. DSI_ERR("Invalid params(s) dsi_display %pK, panel %pK\n",
  1030. dsi_display,
  1031. ((dsi_display) ? dsi_display->panel : NULL));
  1032. return format;
  1033. }
  1034. format = dsi_display->panel->host_config.dst_format;
  1035. return format;
  1036. }
  1037. static void _dsi_display_setup_misr(struct dsi_display *display)
  1038. {
  1039. int i;
  1040. display_for_each_ctrl(i, display) {
  1041. dsi_ctrl_setup_misr(display->ctrl[i].ctrl,
  1042. display->misr_enable,
  1043. display->misr_frame_count);
  1044. }
  1045. }
  1046. int dsi_display_set_power(struct drm_connector *connector,
  1047. int power_mode, void *disp)
  1048. {
  1049. struct dsi_display *display = disp;
  1050. int rc = 0;
  1051. if (!display || !display->panel) {
  1052. DSI_ERR("invalid display/panel\n");
  1053. return -EINVAL;
  1054. }
  1055. switch (power_mode) {
  1056. case SDE_MODE_DPMS_LP1:
  1057. rc = dsi_panel_set_lp1(display->panel);
  1058. break;
  1059. case SDE_MODE_DPMS_LP2:
  1060. rc = dsi_panel_set_lp2(display->panel);
  1061. break;
  1062. case SDE_MODE_DPMS_ON:
  1063. if ((display->panel->power_mode == SDE_MODE_DPMS_LP1) ||
  1064. (display->panel->power_mode == SDE_MODE_DPMS_LP2))
  1065. rc = dsi_panel_set_nolp(display->panel);
  1066. break;
  1067. case SDE_MODE_DPMS_OFF:
  1068. default:
  1069. return rc;
  1070. }
  1071. SDE_EVT32(display->panel->power_mode, power_mode, rc);
  1072. DSI_DEBUG("Power mode transition from %d to %d %s",
  1073. display->panel->power_mode, power_mode,
  1074. rc ? "failed" : "successful");
  1075. if (!rc)
  1076. display->panel->power_mode = power_mode;
  1077. return rc;
  1078. }
  1079. #ifdef CONFIG_DEBUG_FS
  1080. static bool dsi_display_is_te_based_esd(struct dsi_display *display)
  1081. {
  1082. u32 status_mode = 0;
  1083. if (!display->panel) {
  1084. DSI_ERR("Invalid panel data\n");
  1085. return false;
  1086. }
  1087. status_mode = display->panel->esd_config.status_mode;
  1088. if (status_mode == ESD_MODE_PANEL_TE &&
  1089. gpio_is_valid(display->disp_te_gpio))
  1090. return true;
  1091. return false;
  1092. }
  1093. static ssize_t debugfs_dump_info_read(struct file *file,
  1094. char __user *user_buf,
  1095. size_t user_len,
  1096. loff_t *ppos)
  1097. {
  1098. struct dsi_display *display = file->private_data;
  1099. struct dsi_mode_info *m;
  1100. char *buf;
  1101. u32 len = 0;
  1102. int i;
  1103. if (!display)
  1104. return -ENODEV;
  1105. if (*ppos)
  1106. return 0;
  1107. buf = kzalloc(SZ_4K, GFP_KERNEL);
  1108. if (!buf)
  1109. return -ENOMEM;
  1110. m = &display->config.video_timing;
  1111. len += snprintf(buf + len, (SZ_4K - len), "name = %s\n", display->name);
  1112. len += snprintf(buf + len, (SZ_4K - len),
  1113. "\tResolution = %d(%d|%d|%d|%d)x%d(%d|%d|%d|%d)@%dfps %llu Hz\n",
  1114. m->h_active, m->h_back_porch, m->h_front_porch, m->h_sync_width,
  1115. m->h_sync_polarity, m->v_active, m->v_back_porch, m->v_front_porch,
  1116. m->v_sync_width, m->v_sync_polarity, m->refresh_rate, m->clk_rate_hz);
  1117. display_for_each_ctrl(i, display) {
  1118. len += snprintf(buf + len, (SZ_4K - len),
  1119. "\tCTRL_%d:\n\t\tctrl = %s\n\t\tphy = %s\n",
  1120. i, display->ctrl[i].ctrl->name,
  1121. display->ctrl[i].phy->name);
  1122. }
  1123. len += snprintf(buf + len, (SZ_4K - len),
  1124. "\tPanel = %s\n", display->panel->name);
  1125. len += snprintf(buf + len, (SZ_4K - len),
  1126. "\tClock master = %s\n",
  1127. display->ctrl[display->clk_master_idx].ctrl->name);
  1128. if (len > user_len)
  1129. len = user_len;
  1130. if (copy_to_user(user_buf, buf, len)) {
  1131. kfree(buf);
  1132. return -EFAULT;
  1133. }
  1134. *ppos += len;
  1135. kfree(buf);
  1136. return len;
  1137. }
  1138. static ssize_t debugfs_misr_setup(struct file *file,
  1139. const char __user *user_buf,
  1140. size_t user_len,
  1141. loff_t *ppos)
  1142. {
  1143. struct dsi_display *display = file->private_data;
  1144. char *buf;
  1145. int rc = 0;
  1146. size_t len;
  1147. u32 enable, frame_count;
  1148. if (!display)
  1149. return -ENODEV;
  1150. if (*ppos)
  1151. return 0;
  1152. buf = kzalloc(MISR_BUFF_SIZE, GFP_KERNEL);
  1153. if (!buf)
  1154. return -ENOMEM;
  1155. /* leave room for termination char */
  1156. len = min_t(size_t, user_len, MISR_BUFF_SIZE - 1);
  1157. if (copy_from_user(buf, user_buf, len)) {
  1158. rc = -EINVAL;
  1159. goto error;
  1160. }
  1161. buf[len] = '\0'; /* terminate the string */
  1162. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) {
  1163. rc = -EINVAL;
  1164. goto error;
  1165. }
  1166. display->misr_enable = enable;
  1167. display->misr_frame_count = frame_count;
  1168. mutex_lock(&display->display_lock);
  1169. if (!display->hw_ownership) {
  1170. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1171. display->name);
  1172. rc = -EOPNOTSUPP;
  1173. goto unlock;
  1174. }
  1175. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1176. DSI_CORE_CLK, DSI_CLK_ON);
  1177. if (rc) {
  1178. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1179. display->name, rc);
  1180. goto unlock;
  1181. }
  1182. _dsi_display_setup_misr(display);
  1183. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1184. DSI_CORE_CLK, DSI_CLK_OFF);
  1185. if (rc) {
  1186. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1187. display->name, rc);
  1188. goto unlock;
  1189. }
  1190. rc = user_len;
  1191. unlock:
  1192. mutex_unlock(&display->display_lock);
  1193. error:
  1194. kfree(buf);
  1195. return rc;
  1196. }
  1197. static ssize_t debugfs_misr_read(struct file *file,
  1198. char __user *user_buf,
  1199. size_t user_len,
  1200. loff_t *ppos)
  1201. {
  1202. struct dsi_display *display = file->private_data;
  1203. char *buf;
  1204. u32 len = 0;
  1205. int rc = 0;
  1206. struct dsi_ctrl *dsi_ctrl;
  1207. int i;
  1208. u32 misr;
  1209. size_t max_len = min_t(size_t, user_len, MISR_BUFF_SIZE);
  1210. if (!display)
  1211. return -ENODEV;
  1212. if (*ppos)
  1213. return 0;
  1214. buf = kzalloc(max_len, GFP_KERNEL);
  1215. if (ZERO_OR_NULL_PTR(buf))
  1216. return -ENOMEM;
  1217. mutex_lock(&display->display_lock);
  1218. if (!display->hw_ownership) {
  1219. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1220. display->name);
  1221. rc = -EOPNOTSUPP;
  1222. goto error;
  1223. }
  1224. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1225. DSI_CORE_CLK, DSI_CLK_ON);
  1226. if (rc) {
  1227. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  1228. display->name, rc);
  1229. goto error;
  1230. }
  1231. display_for_each_ctrl(i, display) {
  1232. dsi_ctrl = display->ctrl[i].ctrl;
  1233. misr = dsi_ctrl_collect_misr(display->ctrl[i].ctrl);
  1234. len += snprintf((buf + len), max_len - len,
  1235. "DSI_%d MISR: 0x%x\n", dsi_ctrl->cell_index, misr);
  1236. if (len >= max_len)
  1237. break;
  1238. }
  1239. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  1240. DSI_CORE_CLK, DSI_CLK_OFF);
  1241. if (rc) {
  1242. DSI_ERR("[%s] failed to disable DSI core clocks, rc=%d\n",
  1243. display->name, rc);
  1244. goto error;
  1245. }
  1246. if (copy_to_user(user_buf, buf, max_len)) {
  1247. rc = -EFAULT;
  1248. goto error;
  1249. }
  1250. *ppos += len;
  1251. error:
  1252. mutex_unlock(&display->display_lock);
  1253. kfree(buf);
  1254. return len;
  1255. }
  1256. static ssize_t debugfs_esd_trigger_check(struct file *file,
  1257. const char __user *user_buf,
  1258. size_t user_len,
  1259. loff_t *ppos)
  1260. {
  1261. struct dsi_display *display = file->private_data;
  1262. char *buf;
  1263. int rc = 0;
  1264. struct drm_panel_esd_config *esd_config = &display->panel->esd_config;
  1265. u32 esd_trigger;
  1266. size_t len;
  1267. if (!display)
  1268. return -ENODEV;
  1269. if (*ppos)
  1270. return 0;
  1271. if (user_len > sizeof(u32))
  1272. return -EINVAL;
  1273. if (!user_len || !user_buf)
  1274. return -EINVAL;
  1275. if (!display->panel ||
  1276. atomic_read(&display->panel->esd_recovery_pending))
  1277. return user_len;
  1278. if (!esd_config->esd_enabled) {
  1279. DSI_ERR("ESD feature is not enabled\n");
  1280. return -EINVAL;
  1281. }
  1282. buf = kzalloc(ESD_TRIGGER_STRING_MAX_LEN, GFP_KERNEL);
  1283. if (!buf)
  1284. return -ENOMEM;
  1285. len = min_t(size_t, user_len, ESD_TRIGGER_STRING_MAX_LEN - 1);
  1286. if (copy_from_user(buf, user_buf, len)) {
  1287. rc = -EINVAL;
  1288. goto error;
  1289. }
  1290. buf[len] = '\0'; /* terminate the string */
  1291. if (kstrtouint(buf, 10, &esd_trigger)) {
  1292. rc = -EINVAL;
  1293. goto error;
  1294. }
  1295. if (esd_trigger != 1) {
  1296. rc = -EINVAL;
  1297. goto error;
  1298. }
  1299. display->esd_trigger = esd_trigger;
  1300. mutex_lock(&display->display_lock);
  1301. if (!display->hw_ownership) {
  1302. DSI_DEBUG("[%s] op not supported due to HW unavailability\n",
  1303. display->name);
  1304. rc = -EOPNOTSUPP;
  1305. goto unlock;
  1306. }
  1307. if (display->esd_trigger) {
  1308. DSI_INFO("ESD attack triggered by user\n");
  1309. rc = dsi_panel_trigger_esd_attack(display->panel,
  1310. display->trusted_vm_env);
  1311. if (rc) {
  1312. DSI_ERR("Failed to trigger ESD attack\n");
  1313. goto error;
  1314. }
  1315. }
  1316. rc = len;
  1317. unlock:
  1318. mutex_unlock(&display->display_lock);
  1319. error:
  1320. kfree(buf);
  1321. return rc;
  1322. }
  1323. static ssize_t debugfs_alter_esd_check_mode(struct file *file,
  1324. const char __user *user_buf,
  1325. size_t user_len,
  1326. loff_t *ppos)
  1327. {
  1328. struct dsi_display *display = file->private_data;
  1329. struct drm_panel_esd_config *esd_config;
  1330. char *buf;
  1331. int rc = 0;
  1332. size_t len;
  1333. if (!display)
  1334. return -ENODEV;
  1335. if (*ppos)
  1336. return 0;
  1337. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1338. if (ZERO_OR_NULL_PTR(buf))
  1339. return -ENOMEM;
  1340. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1341. if (copy_from_user(buf, user_buf, len)) {
  1342. rc = -EINVAL;
  1343. goto error;
  1344. }
  1345. buf[len] = '\0'; /* terminate the string */
  1346. if (!display->panel) {
  1347. rc = -EINVAL;
  1348. goto error;
  1349. }
  1350. esd_config = &display->panel->esd_config;
  1351. if (!esd_config) {
  1352. DSI_ERR("Invalid panel esd config\n");
  1353. rc = -EINVAL;
  1354. goto error;
  1355. }
  1356. if (!esd_config->esd_enabled) {
  1357. rc = -EINVAL;
  1358. goto error;
  1359. }
  1360. if (!strcmp(buf, "te_signal_check\n")) {
  1361. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  1362. DSI_INFO("TE based ESD check for Video Mode panels is not allowed\n");
  1363. rc = -EINVAL;
  1364. goto error;
  1365. }
  1366. DSI_INFO("ESD check is switched to TE mode by user\n");
  1367. esd_config->status_mode = ESD_MODE_PANEL_TE;
  1368. dsi_display_change_te_irq_status(display, true);
  1369. }
  1370. if (!strcmp(buf, "reg_read\n")) {
  1371. DSI_INFO("ESD check is switched to reg read by user\n");
  1372. rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
  1373. if (rc) {
  1374. DSI_ERR("failed to alter esd check mode,rc=%d\n",
  1375. rc);
  1376. rc = user_len;
  1377. goto error;
  1378. }
  1379. esd_config->status_mode = ESD_MODE_REG_READ;
  1380. if (dsi_display_is_te_based_esd(display))
  1381. dsi_display_change_te_irq_status(display, false);
  1382. }
  1383. if (!strcmp(buf, "esd_sw_sim_success\n"))
  1384. esd_config->status_mode = ESD_MODE_SW_SIM_SUCCESS;
  1385. if (!strcmp(buf, "esd_sw_sim_failure\n"))
  1386. esd_config->status_mode = ESD_MODE_SW_SIM_FAILURE;
  1387. rc = len;
  1388. error:
  1389. kfree(buf);
  1390. return rc;
  1391. }
  1392. static ssize_t debugfs_read_esd_check_mode(struct file *file,
  1393. char __user *user_buf,
  1394. size_t user_len,
  1395. loff_t *ppos)
  1396. {
  1397. struct dsi_display *display = file->private_data;
  1398. struct drm_panel_esd_config *esd_config;
  1399. char *buf;
  1400. int rc = 0;
  1401. size_t len = 0;
  1402. if (!display)
  1403. return -ENODEV;
  1404. if (*ppos)
  1405. return 0;
  1406. if (!display->panel) {
  1407. DSI_ERR("invalid panel data\n");
  1408. return -EINVAL;
  1409. }
  1410. buf = kzalloc(ESD_MODE_STRING_MAX_LEN, GFP_KERNEL);
  1411. if (ZERO_OR_NULL_PTR(buf))
  1412. return -ENOMEM;
  1413. esd_config = &display->panel->esd_config;
  1414. if (!esd_config) {
  1415. DSI_ERR("Invalid panel esd config\n");
  1416. rc = -EINVAL;
  1417. goto error;
  1418. }
  1419. len = min_t(size_t, user_len, ESD_MODE_STRING_MAX_LEN - 1);
  1420. if (!esd_config->esd_enabled) {
  1421. rc = snprintf(buf, len, "ESD feature not enabled");
  1422. goto output_mode;
  1423. }
  1424. switch (esd_config->status_mode) {
  1425. case ESD_MODE_REG_READ:
  1426. rc = snprintf(buf, len, "reg_read");
  1427. break;
  1428. case ESD_MODE_PANEL_TE:
  1429. rc = snprintf(buf, len, "te_signal_check");
  1430. break;
  1431. case ESD_MODE_SW_SIM_FAILURE:
  1432. rc = snprintf(buf, len, "esd_sw_sim_failure");
  1433. break;
  1434. case ESD_MODE_SW_SIM_SUCCESS:
  1435. rc = snprintf(buf, len, "esd_sw_sim_success");
  1436. break;
  1437. default:
  1438. rc = snprintf(buf, len, "invalid");
  1439. break;
  1440. }
  1441. output_mode:
  1442. if (!rc) {
  1443. rc = -EINVAL;
  1444. goto error;
  1445. }
  1446. if (copy_to_user(user_buf, buf, len)) {
  1447. rc = -EFAULT;
  1448. goto error;
  1449. }
  1450. *ppos += len;
  1451. error:
  1452. kfree(buf);
  1453. return len;
  1454. }
  1455. static ssize_t debugfs_update_cmd_scheduling_params(struct file *file,
  1456. const char __user *user_buf,
  1457. size_t user_len,
  1458. loff_t *ppos)
  1459. {
  1460. struct dsi_display *display = file->private_data;
  1461. struct dsi_display_ctrl *display_ctrl;
  1462. char *buf;
  1463. int rc = 0;
  1464. u32 line = 0, window = 0;
  1465. size_t len;
  1466. int i;
  1467. if (!display)
  1468. return -ENODEV;
  1469. if (*ppos)
  1470. return 0;
  1471. buf = kzalloc(256, GFP_KERNEL);
  1472. if (ZERO_OR_NULL_PTR(buf))
  1473. return -ENOMEM;
  1474. len = min_t(size_t, user_len, 255);
  1475. if (copy_from_user(buf, user_buf, len)) {
  1476. rc = -EINVAL;
  1477. goto error;
  1478. }
  1479. buf[len] = '\0'; /* terminate the string */
  1480. if (sscanf(buf, "%d %d", &line, &window) != 2)
  1481. return -EFAULT;
  1482. display_for_each_ctrl(i, display) {
  1483. struct dsi_ctrl *ctrl;
  1484. display_ctrl = &display->ctrl[i];
  1485. if (!display_ctrl->ctrl)
  1486. continue;
  1487. ctrl = display_ctrl->ctrl;
  1488. ctrl->host_config.common_config.dma_sched_line = line;
  1489. ctrl->host_config.common_config.dma_sched_window = window;
  1490. }
  1491. rc = len;
  1492. error:
  1493. kfree(buf);
  1494. return rc;
  1495. }
  1496. static ssize_t debugfs_read_cmd_scheduling_params(struct file *file,
  1497. char __user *user_buf,
  1498. size_t user_len,
  1499. loff_t *ppos)
  1500. {
  1501. struct dsi_display *display = file->private_data;
  1502. struct dsi_display_ctrl *m_ctrl;
  1503. struct dsi_ctrl *ctrl;
  1504. char *buf;
  1505. u32 len = 0;
  1506. int rc = 0;
  1507. size_t max_len = min_t(size_t, user_len, SZ_4K);
  1508. if (!display)
  1509. return -ENODEV;
  1510. if (*ppos)
  1511. return 0;
  1512. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1513. ctrl = m_ctrl->ctrl;
  1514. buf = kzalloc(max_len, GFP_KERNEL);
  1515. if (ZERO_OR_NULL_PTR(buf))
  1516. return -ENOMEM;
  1517. len += scnprintf(buf, max_len, "Schedule command window start: %d\n",
  1518. ctrl->host_config.common_config.dma_sched_line);
  1519. len += scnprintf((buf + len), max_len - len,
  1520. "Schedule command window width: %d\n",
  1521. ctrl->host_config.common_config.dma_sched_window);
  1522. if (len > max_len)
  1523. len = max_len;
  1524. if (copy_to_user(user_buf, buf, len)) {
  1525. rc = -EFAULT;
  1526. goto error;
  1527. }
  1528. *ppos += len;
  1529. error:
  1530. kfree(buf);
  1531. return len;
  1532. }
  1533. static const struct file_operations dump_info_fops = {
  1534. .open = simple_open,
  1535. .read = debugfs_dump_info_read,
  1536. };
  1537. static const struct file_operations misr_data_fops = {
  1538. .open = simple_open,
  1539. .read = debugfs_misr_read,
  1540. .write = debugfs_misr_setup,
  1541. };
  1542. static const struct file_operations esd_trigger_fops = {
  1543. .open = simple_open,
  1544. .write = debugfs_esd_trigger_check,
  1545. };
  1546. static const struct file_operations esd_check_mode_fops = {
  1547. .open = simple_open,
  1548. .write = debugfs_alter_esd_check_mode,
  1549. .read = debugfs_read_esd_check_mode,
  1550. };
  1551. static const struct file_operations dsi_command_scheduling_fops = {
  1552. .open = simple_open,
  1553. .write = debugfs_update_cmd_scheduling_params,
  1554. .read = debugfs_read_cmd_scheduling_params,
  1555. };
  1556. static int dsi_display_debugfs_init(struct dsi_display *display)
  1557. {
  1558. int rc = 0;
  1559. struct dentry *dir, *dump_file, *misr_data;
  1560. char name[MAX_NAME_SIZE];
  1561. char panel_name[SEC_PANEL_NAME_MAX_LEN];
  1562. char secondary_panel_str[] = "_secondary";
  1563. int i;
  1564. strlcpy(panel_name, display->name, SEC_PANEL_NAME_MAX_LEN);
  1565. if (strcmp(display->display_type, "secondary") == 0)
  1566. strlcat(panel_name, secondary_panel_str, SEC_PANEL_NAME_MAX_LEN);
  1567. dir = debugfs_create_dir(panel_name, NULL);
  1568. if (IS_ERR_OR_NULL(dir)) {
  1569. rc = PTR_ERR(dir);
  1570. DSI_ERR("[%s] debugfs create dir failed, rc = %d\n",
  1571. display->name, rc);
  1572. goto error;
  1573. }
  1574. dump_file = debugfs_create_file("dump_info",
  1575. 0400,
  1576. dir,
  1577. display,
  1578. &dump_info_fops);
  1579. if (IS_ERR_OR_NULL(dump_file)) {
  1580. rc = PTR_ERR(dump_file);
  1581. DSI_ERR("[%s] debugfs create dump info file failed, rc=%d\n",
  1582. display->name, rc);
  1583. goto error_remove_dir;
  1584. }
  1585. dump_file = debugfs_create_file("esd_trigger",
  1586. 0644,
  1587. dir,
  1588. display,
  1589. &esd_trigger_fops);
  1590. if (IS_ERR_OR_NULL(dump_file)) {
  1591. rc = PTR_ERR(dump_file);
  1592. DSI_ERR("[%s] debugfs for esd trigger file failed, rc=%d\n",
  1593. display->name, rc);
  1594. goto error_remove_dir;
  1595. }
  1596. dump_file = debugfs_create_file("esd_check_mode",
  1597. 0644,
  1598. dir,
  1599. display,
  1600. &esd_check_mode_fops);
  1601. if (IS_ERR_OR_NULL(dump_file)) {
  1602. rc = PTR_ERR(dump_file);
  1603. DSI_ERR("[%s] debugfs for esd check mode failed, rc=%d\n",
  1604. display->name, rc);
  1605. goto error_remove_dir;
  1606. }
  1607. dump_file = debugfs_create_file("cmd_sched_params",
  1608. 0644,
  1609. dir,
  1610. display,
  1611. &dsi_command_scheduling_fops);
  1612. if (IS_ERR_OR_NULL(dump_file)) {
  1613. rc = PTR_ERR(dump_file);
  1614. DSI_ERR("[%s] debugfs for cmd scheduling file failed, rc=%d\n",
  1615. display->name, rc);
  1616. goto error_remove_dir;
  1617. }
  1618. misr_data = debugfs_create_file("misr_data",
  1619. 0600,
  1620. dir,
  1621. display,
  1622. &misr_data_fops);
  1623. if (IS_ERR_OR_NULL(misr_data)) {
  1624. rc = PTR_ERR(misr_data);
  1625. DSI_ERR("[%s] debugfs create misr datafile failed, rc=%d\n",
  1626. display->name, rc);
  1627. goto error_remove_dir;
  1628. }
  1629. display_for_each_ctrl(i, display) {
  1630. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1631. if (!phy || !phy->name)
  1632. continue;
  1633. snprintf(name, ARRAY_SIZE(name),
  1634. "%s_allow_phy_power_off", phy->name);
  1635. dump_file = debugfs_create_bool(name, 0600, dir,
  1636. &phy->allow_phy_power_off);
  1637. if (IS_ERR_OR_NULL(dump_file)) {
  1638. rc = PTR_ERR(dump_file);
  1639. DSI_ERR("[%s] debugfs create %s failed, rc=%d\n",
  1640. display->name, name, rc);
  1641. goto error_remove_dir;
  1642. }
  1643. snprintf(name, ARRAY_SIZE(name),
  1644. "%s_regulator_min_datarate_bps", phy->name);
  1645. debugfs_create_u32(name, 0600, dir, &phy->regulator_min_datarate_bps);
  1646. }
  1647. if (!debugfs_create_bool("ulps_feature_enable", 0600, dir,
  1648. &display->panel->ulps_feature_enabled)) {
  1649. DSI_ERR("[%s] debugfs create ulps feature enable file failed\n",
  1650. display->name);
  1651. goto error_remove_dir;
  1652. }
  1653. if (!debugfs_create_bool("ulps_suspend_feature_enable", 0600, dir,
  1654. &display->panel->ulps_suspend_enabled)) {
  1655. DSI_ERR("[%s] debugfs create ulps-suspend feature enable file failed\n",
  1656. display->name);
  1657. goto error_remove_dir;
  1658. }
  1659. if (!debugfs_create_bool("ulps_status", 0400, dir,
  1660. &display->ulps_enabled)) {
  1661. DSI_ERR("[%s] debugfs create ulps status file failed\n",
  1662. display->name);
  1663. goto error_remove_dir;
  1664. }
  1665. debugfs_create_u32("clk_gating_config", 0600, dir, &display->clk_gating_config);
  1666. display->root = dir;
  1667. dsi_parser_dbg_init(display->parser, dir);
  1668. return rc;
  1669. error_remove_dir:
  1670. debugfs_remove(dir);
  1671. error:
  1672. return rc;
  1673. }
  1674. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1675. {
  1676. if (display->root) {
  1677. debugfs_remove_recursive(display->root);
  1678. display->root = NULL;
  1679. }
  1680. return 0;
  1681. }
  1682. #else
  1683. static int dsi_display_debugfs_init(struct dsi_display *display)
  1684. {
  1685. return 0;
  1686. }
  1687. static int dsi_display_debugfs_deinit(struct dsi_display *display)
  1688. {
  1689. return 0;
  1690. }
  1691. #endif /* CONFIG_DEBUG_FS */
  1692. static void adjust_timing_by_ctrl_count(const struct dsi_display *display,
  1693. struct dsi_display_mode *mode)
  1694. {
  1695. struct dsi_host_common_cfg *host = &display->panel->host_config;
  1696. bool is_split_link = host->split_link.enabled;
  1697. u32 sublinks_count = host->split_link.num_sublinks;
  1698. if (is_split_link && sublinks_count > 1) {
  1699. mode->timing.h_active /= sublinks_count;
  1700. mode->timing.h_front_porch /= sublinks_count;
  1701. mode->timing.h_sync_width /= sublinks_count;
  1702. mode->timing.h_back_porch /= sublinks_count;
  1703. mode->timing.h_skew /= sublinks_count;
  1704. mode->pixel_clk_khz /= sublinks_count;
  1705. } else {
  1706. if (mode->priv_info->dsc_enabled)
  1707. mode->priv_info->dsc.config.pic_width =
  1708. mode->timing.h_active;
  1709. mode->timing.h_active /= display->ctrl_count;
  1710. mode->timing.h_front_porch /= display->ctrl_count;
  1711. mode->timing.h_sync_width /= display->ctrl_count;
  1712. mode->timing.h_back_porch /= display->ctrl_count;
  1713. mode->timing.h_skew /= display->ctrl_count;
  1714. mode->pixel_clk_khz /= display->ctrl_count;
  1715. }
  1716. }
  1717. static int dsi_display_is_ulps_req_valid(struct dsi_display *display,
  1718. bool enable)
  1719. {
  1720. /* TODO: make checks based on cont. splash */
  1721. DSI_DEBUG("checking ulps req validity\n");
  1722. if (atomic_read(&display->panel->esd_recovery_pending)) {
  1723. DSI_DEBUG("%s: ESD recovery sequence underway\n", __func__);
  1724. return false;
  1725. }
  1726. if (!dsi_panel_ulps_feature_enabled(display->panel) &&
  1727. !display->panel->ulps_suspend_enabled) {
  1728. DSI_DEBUG("%s: ULPS feature is not enabled\n", __func__);
  1729. return false;
  1730. }
  1731. if (!dsi_panel_initialized(display->panel) &&
  1732. !display->panel->ulps_suspend_enabled) {
  1733. DSI_DEBUG("%s: panel not yet initialized\n", __func__);
  1734. return false;
  1735. }
  1736. if (enable && display->ulps_enabled) {
  1737. DSI_DEBUG("ULPS already enabled\n");
  1738. return false;
  1739. } else if (!enable && !display->ulps_enabled) {
  1740. DSI_DEBUG("ULPS already disabled\n");
  1741. return false;
  1742. }
  1743. /*
  1744. * No need to enter ULPS when transitioning from splash screen to
  1745. * boot animation or trusted vm environments since it is expected
  1746. * that the clocks would be turned right back on.
  1747. */
  1748. if (enable && is_skip_op_required(display))
  1749. return false;
  1750. return true;
  1751. }
  1752. /**
  1753. * dsi_display_set_ulps() - set ULPS state for DSI lanes.
  1754. * @dsi_display: DSI display handle.
  1755. * @enable: enable/disable ULPS.
  1756. *
  1757. * ULPS can be enabled/disabled after DSI host engine is turned on.
  1758. *
  1759. * Return: error code.
  1760. */
  1761. static int dsi_display_set_ulps(struct dsi_display *display, bool enable)
  1762. {
  1763. int rc = 0;
  1764. int i = 0;
  1765. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1766. if (!display) {
  1767. DSI_ERR("Invalid params\n");
  1768. return -EINVAL;
  1769. }
  1770. if (!dsi_display_is_ulps_req_valid(display, enable)) {
  1771. DSI_DEBUG("%s: skipping ULPS config, enable=%d\n",
  1772. __func__, enable);
  1773. return 0;
  1774. }
  1775. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1776. /*
  1777. * ULPS entry-exit can be either through the DSI controller or
  1778. * the DSI PHY depending on hardware variation. For some chipsets,
  1779. * both controller version and phy version ulps entry-exit ops can
  1780. * be present. To handle such cases, send ulps request through PHY,
  1781. * if ulps request is handled in PHY, then no need to send request
  1782. * through controller.
  1783. */
  1784. rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable,
  1785. display->clamp_enabled);
  1786. if (rc == DSI_PHY_ULPS_ERROR) {
  1787. DSI_ERR("Ulps PHY state change(%d) failed\n", enable);
  1788. return -EINVAL;
  1789. }
  1790. else if (rc == DSI_PHY_ULPS_HANDLED) {
  1791. display_for_each_ctrl(i, display) {
  1792. ctrl = &display->ctrl[i];
  1793. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1794. continue;
  1795. rc = dsi_phy_set_ulps(ctrl->phy, &display->config,
  1796. enable, display->clamp_enabled);
  1797. if (rc == DSI_PHY_ULPS_ERROR) {
  1798. DSI_ERR("Ulps PHY state change(%d) failed\n",
  1799. enable);
  1800. return -EINVAL;
  1801. }
  1802. }
  1803. }
  1804. else if (rc == DSI_PHY_ULPS_NOT_HANDLED) {
  1805. rc = dsi_ctrl_set_ulps(m_ctrl->ctrl, enable);
  1806. if (rc) {
  1807. DSI_ERR("Ulps controller state change(%d) failed\n",
  1808. enable);
  1809. return rc;
  1810. }
  1811. display_for_each_ctrl(i, display) {
  1812. ctrl = &display->ctrl[i];
  1813. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1814. continue;
  1815. rc = dsi_ctrl_set_ulps(ctrl->ctrl, enable);
  1816. if (rc) {
  1817. DSI_ERR("Ulps controller state change(%d) failed\n",
  1818. enable);
  1819. return rc;
  1820. }
  1821. }
  1822. }
  1823. display->ulps_enabled = enable;
  1824. return 0;
  1825. }
  1826. /**
  1827. * dsi_display_set_clamp() - set clamp state for DSI IO.
  1828. * @dsi_display: DSI display handle.
  1829. * @enable: enable/disable clamping.
  1830. *
  1831. * Return: error code.
  1832. */
  1833. static int dsi_display_set_clamp(struct dsi_display *display, bool enable)
  1834. {
  1835. int rc = 0;
  1836. int i = 0;
  1837. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1838. bool ulps_enabled = false;
  1839. if (!display) {
  1840. DSI_ERR("Invalid params\n");
  1841. return -EINVAL;
  1842. }
  1843. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1844. ulps_enabled = display->ulps_enabled;
  1845. /*
  1846. * Clamp control can be either through the DSI controller or
  1847. * the DSI PHY depending on hardware variation
  1848. */
  1849. rc = dsi_ctrl_set_clamp_state(m_ctrl->ctrl, enable, ulps_enabled);
  1850. if (rc) {
  1851. DSI_ERR("DSI ctrl clamp state change(%d) failed\n", enable);
  1852. return rc;
  1853. }
  1854. rc = dsi_phy_set_clamp_state(m_ctrl->phy, enable);
  1855. if (rc) {
  1856. DSI_ERR("DSI phy clamp state change(%d) failed\n", enable);
  1857. return rc;
  1858. }
  1859. display_for_each_ctrl(i, display) {
  1860. ctrl = &display->ctrl[i];
  1861. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1862. continue;
  1863. rc = dsi_ctrl_set_clamp_state(ctrl->ctrl, enable, ulps_enabled);
  1864. if (rc) {
  1865. DSI_ERR("DSI Clamp state change(%d) failed\n", enable);
  1866. return rc;
  1867. }
  1868. rc = dsi_phy_set_clamp_state(ctrl->phy, enable);
  1869. if (rc) {
  1870. DSI_ERR("DSI phy clamp state change(%d) failed\n",
  1871. enable);
  1872. return rc;
  1873. }
  1874. DSI_DEBUG("Clamps %s for ctrl%d\n",
  1875. enable ? "enabled" : "disabled", i);
  1876. }
  1877. display->clamp_enabled = enable;
  1878. return 0;
  1879. }
  1880. /**
  1881. * dsi_display_setup_ctrl() - setup DSI controller.
  1882. * @dsi_display: DSI display handle.
  1883. *
  1884. * Return: error code.
  1885. */
  1886. static int dsi_display_ctrl_setup(struct dsi_display *display)
  1887. {
  1888. int rc = 0;
  1889. int i = 0;
  1890. struct dsi_display_ctrl *ctrl, *m_ctrl;
  1891. if (!display) {
  1892. DSI_ERR("Invalid params\n");
  1893. return -EINVAL;
  1894. }
  1895. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1896. rc = dsi_ctrl_setup(m_ctrl->ctrl);
  1897. if (rc) {
  1898. DSI_ERR("DSI controller setup failed\n");
  1899. return rc;
  1900. }
  1901. display_for_each_ctrl(i, display) {
  1902. ctrl = &display->ctrl[i];
  1903. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1904. continue;
  1905. rc = dsi_ctrl_setup(ctrl->ctrl);
  1906. if (rc) {
  1907. DSI_ERR("DSI controller setup failed\n");
  1908. return rc;
  1909. }
  1910. }
  1911. return 0;
  1912. }
  1913. static int dsi_display_phy_enable(struct dsi_display *display);
  1914. /**
  1915. * dsi_display_phy_idle_on() - enable DSI PHY while coming out of idle screen.
  1916. * @dsi_display: DSI display handle.
  1917. * @mmss_clamp: True if clamp is enabled.
  1918. *
  1919. * Return: error code.
  1920. */
  1921. static int dsi_display_phy_idle_on(struct dsi_display *display,
  1922. bool mmss_clamp)
  1923. {
  1924. int rc = 0;
  1925. int i = 0;
  1926. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1927. if (!display) {
  1928. DSI_ERR("Invalid params\n");
  1929. return -EINVAL;
  1930. }
  1931. if (mmss_clamp && !display->phy_idle_power_off) {
  1932. dsi_display_phy_enable(display);
  1933. return 0;
  1934. }
  1935. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1936. rc = dsi_phy_idle_ctrl(m_ctrl->phy, true);
  1937. if (rc) {
  1938. DSI_ERR("DSI controller setup failed\n");
  1939. return rc;
  1940. }
  1941. display_for_each_ctrl(i, display) {
  1942. ctrl = &display->ctrl[i];
  1943. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1944. continue;
  1945. rc = dsi_phy_idle_ctrl(ctrl->phy, true);
  1946. if (rc) {
  1947. DSI_ERR("DSI controller setup failed\n");
  1948. return rc;
  1949. }
  1950. }
  1951. display->phy_idle_power_off = false;
  1952. return 0;
  1953. }
  1954. /**
  1955. * dsi_display_phy_idle_off() - disable DSI PHY while going to idle screen.
  1956. * @dsi_display: DSI display handle.
  1957. *
  1958. * Return: error code.
  1959. */
  1960. static int dsi_display_phy_idle_off(struct dsi_display *display)
  1961. {
  1962. int rc = 0;
  1963. int i = 0;
  1964. struct dsi_display_ctrl *m_ctrl, *ctrl;
  1965. if (!display) {
  1966. DSI_ERR("Invalid params\n");
  1967. return -EINVAL;
  1968. }
  1969. display_for_each_ctrl(i, display) {
  1970. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  1971. if (!phy)
  1972. continue;
  1973. if (!phy->allow_phy_power_off) {
  1974. DSI_DEBUG("phy doesn't support this feature\n");
  1975. return 0;
  1976. }
  1977. }
  1978. m_ctrl = &display->ctrl[display->cmd_master_idx];
  1979. rc = dsi_phy_idle_ctrl(m_ctrl->phy, false);
  1980. if (rc) {
  1981. DSI_ERR("[%s] failed to enable cmd engine, rc=%d\n",
  1982. display->name, rc);
  1983. return rc;
  1984. }
  1985. display_for_each_ctrl(i, display) {
  1986. ctrl = &display->ctrl[i];
  1987. if (!ctrl->ctrl || (ctrl == m_ctrl))
  1988. continue;
  1989. rc = dsi_phy_idle_ctrl(ctrl->phy, false);
  1990. if (rc) {
  1991. DSI_ERR("DSI controller setup failed\n");
  1992. return rc;
  1993. }
  1994. }
  1995. display->phy_idle_power_off = true;
  1996. return 0;
  1997. }
  1998. void dsi_display_enable_event(struct drm_connector *connector,
  1999. struct dsi_display *display,
  2000. uint32_t event_idx, struct dsi_event_cb_info *event_info,
  2001. bool enable)
  2002. {
  2003. uint32_t irq_status_idx = DSI_STATUS_INTERRUPT_COUNT;
  2004. int i;
  2005. if (!display) {
  2006. DSI_ERR("invalid display\n");
  2007. return;
  2008. }
  2009. if (event_info)
  2010. event_info->event_idx = event_idx;
  2011. switch (event_idx) {
  2012. case SDE_CONN_EVENT_VID_DONE:
  2013. irq_status_idx = DSI_SINT_VIDEO_MODE_FRAME_DONE;
  2014. break;
  2015. case SDE_CONN_EVENT_CMD_DONE:
  2016. irq_status_idx = DSI_SINT_CMD_FRAME_DONE;
  2017. break;
  2018. case SDE_CONN_EVENT_VID_FIFO_OVERFLOW:
  2019. case SDE_CONN_EVENT_CMD_FIFO_UNDERFLOW:
  2020. if (event_info) {
  2021. display_for_each_ctrl(i, display)
  2022. display->ctrl[i].ctrl->recovery_cb =
  2023. *event_info;
  2024. }
  2025. break;
  2026. case SDE_CONN_EVENT_PANEL_ID:
  2027. if (event_info)
  2028. display_for_each_ctrl(i, display)
  2029. display->ctrl[i].ctrl->panel_id_cb
  2030. = *event_info;
  2031. dsi_display_panel_id_notification(display);
  2032. break;
  2033. default:
  2034. /* nothing to do */
  2035. DSI_DEBUG("[%s] unhandled event %d\n", display->name, event_idx);
  2036. return;
  2037. }
  2038. if (enable) {
  2039. display_for_each_ctrl(i, display)
  2040. dsi_ctrl_enable_status_interrupt(
  2041. display->ctrl[i].ctrl, irq_status_idx,
  2042. event_info);
  2043. } else {
  2044. display_for_each_ctrl(i, display)
  2045. dsi_ctrl_disable_status_interrupt(
  2046. display->ctrl[i].ctrl, irq_status_idx);
  2047. }
  2048. }
  2049. static int dsi_display_ctrl_power_on(struct dsi_display *display)
  2050. {
  2051. int rc = 0;
  2052. int i;
  2053. struct dsi_display_ctrl *ctrl;
  2054. /* Sequence does not matter for split dsi usecases */
  2055. display_for_each_ctrl(i, display) {
  2056. ctrl = &display->ctrl[i];
  2057. if (!ctrl->ctrl)
  2058. continue;
  2059. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2060. DSI_CTRL_POWER_VREG_ON);
  2061. if (rc) {
  2062. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2063. ctrl->ctrl->name, rc);
  2064. goto error;
  2065. }
  2066. }
  2067. return rc;
  2068. error:
  2069. for (i = i - 1; i >= 0; i--) {
  2070. ctrl = &display->ctrl[i];
  2071. if (!ctrl->ctrl)
  2072. continue;
  2073. (void)dsi_ctrl_set_power_state(ctrl->ctrl,
  2074. DSI_CTRL_POWER_VREG_OFF);
  2075. }
  2076. return rc;
  2077. }
  2078. static int dsi_display_ctrl_power_off(struct dsi_display *display)
  2079. {
  2080. int rc = 0;
  2081. int i;
  2082. struct dsi_display_ctrl *ctrl;
  2083. /* Sequence does not matter for split dsi usecases */
  2084. display_for_each_ctrl(i, display) {
  2085. ctrl = &display->ctrl[i];
  2086. if (!ctrl->ctrl)
  2087. continue;
  2088. rc = dsi_ctrl_set_power_state(ctrl->ctrl,
  2089. DSI_CTRL_POWER_VREG_OFF);
  2090. if (rc) {
  2091. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2092. ctrl->ctrl->name, rc);
  2093. goto error;
  2094. }
  2095. }
  2096. error:
  2097. return rc;
  2098. }
  2099. static void dsi_display_parse_cmdline_topology(struct dsi_display *display,
  2100. unsigned int display_type)
  2101. {
  2102. char *boot_str = NULL;
  2103. char *str = NULL;
  2104. char *sw_te = NULL;
  2105. unsigned long cmdline_topology = NO_OVERRIDE;
  2106. unsigned long cmdline_timing = NO_OVERRIDE;
  2107. if (display_type >= MAX_DSI_ACTIVE_DISPLAY) {
  2108. DSI_ERR("display_type=%d not supported\n", display_type);
  2109. goto end;
  2110. }
  2111. if (display_type == DSI_PRIMARY)
  2112. boot_str = dsi_display_primary;
  2113. else
  2114. boot_str = dsi_display_secondary;
  2115. sw_te = strnstr(boot_str, ":sim-swte", strlen(boot_str));
  2116. if (sw_te)
  2117. display->sw_te_using_wd = true;
  2118. str = strnstr(boot_str, ":config", strlen(boot_str));
  2119. if (str) {
  2120. if (sscanf(str, ":config%lu", &cmdline_topology) != 1) {
  2121. DSI_ERR("invalid config index override: %s\n",
  2122. boot_str);
  2123. goto end;
  2124. }
  2125. }
  2126. str = strnstr(boot_str, ":timing", strlen(boot_str));
  2127. if (str) {
  2128. if (sscanf(str, ":timing%lu", &cmdline_timing) != 1) {
  2129. DSI_ERR("invalid timing index override: %s\n",
  2130. boot_str);
  2131. cmdline_topology = NO_OVERRIDE;
  2132. goto end;
  2133. }
  2134. }
  2135. DSI_DEBUG("successfully parsed command line topology and timing\n");
  2136. end:
  2137. display->cmdline_topology = cmdline_topology;
  2138. display->cmdline_timing = cmdline_timing;
  2139. }
  2140. /**
  2141. * dsi_display_parse_boot_display_selection()- Parse DSI boot display name
  2142. *
  2143. * Return: returns error status
  2144. */
  2145. static int dsi_display_parse_boot_display_selection(void)
  2146. {
  2147. char *pos = NULL;
  2148. char disp_buf[MAX_CMDLINE_PARAM_LEN] = {'\0'};
  2149. int i, j;
  2150. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  2151. strlcpy(disp_buf, boot_displays[i].boot_param,
  2152. MAX_CMDLINE_PARAM_LEN);
  2153. pos = strnstr(disp_buf, ":", strlen(disp_buf));
  2154. /* Use ':' as a delimiter to retrieve the display name */
  2155. if (!pos) {
  2156. DSI_DEBUG("display name[%s]is not valid\n", disp_buf);
  2157. continue;
  2158. }
  2159. for (j = 0; (disp_buf + j) < pos; j++)
  2160. boot_displays[i].name[j] = *(disp_buf + j);
  2161. boot_displays[i].name[j] = '\0';
  2162. boot_displays[i].boot_disp_en = true;
  2163. }
  2164. return 0;
  2165. }
  2166. static int dsi_display_phy_power_on(struct dsi_display *display)
  2167. {
  2168. int rc = 0;
  2169. int i;
  2170. struct dsi_display_ctrl *ctrl;
  2171. /* Sequence does not matter for split dsi usecases */
  2172. display_for_each_ctrl(i, display) {
  2173. ctrl = &display->ctrl[i];
  2174. if (!ctrl->ctrl)
  2175. continue;
  2176. rc = dsi_phy_set_power_state(ctrl->phy, true);
  2177. if (rc) {
  2178. DSI_ERR("[%s] Failed to set power state, rc=%d\n",
  2179. ctrl->phy->name, rc);
  2180. goto error;
  2181. }
  2182. }
  2183. return rc;
  2184. error:
  2185. for (i = i - 1; i >= 0; i--) {
  2186. ctrl = &display->ctrl[i];
  2187. if (!ctrl->phy)
  2188. continue;
  2189. (void)dsi_phy_set_power_state(ctrl->phy, false);
  2190. }
  2191. return rc;
  2192. }
  2193. static int dsi_display_phy_power_off(struct dsi_display *display)
  2194. {
  2195. int rc = 0;
  2196. int i;
  2197. struct dsi_display_ctrl *ctrl;
  2198. /* Sequence does not matter for split dsi usecases */
  2199. display_for_each_ctrl(i, display) {
  2200. ctrl = &display->ctrl[i];
  2201. if (!ctrl->phy)
  2202. continue;
  2203. rc = dsi_phy_set_power_state(ctrl->phy, false);
  2204. if (rc) {
  2205. DSI_ERR("[%s] Failed to power off, rc=%d\n",
  2206. ctrl->ctrl->name, rc);
  2207. goto error;
  2208. }
  2209. }
  2210. error:
  2211. return rc;
  2212. }
  2213. static int dsi_display_set_clk_src(struct dsi_display *display, bool set_xo)
  2214. {
  2215. int rc = 0;
  2216. int i;
  2217. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2218. struct dsi_ctrl_clk_info *info;
  2219. if (display->trusted_vm_env)
  2220. return 0;
  2221. /*
  2222. * In case of split DSI usecases, the clock for master controller should
  2223. * be enabled before the other controller. Master controller in the
  2224. * clock context refers to the controller that sources the clock. While turning off the
  2225. * clocks, the source is set to xo.
  2226. */
  2227. m_ctrl = &display->ctrl[display->clk_master_idx];
  2228. info = &m_ctrl->ctrl->clk_info;
  2229. if (!set_xo)
  2230. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.pll_clks);
  2231. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2232. rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &info->xo_clk);
  2233. if (rc) {
  2234. DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc);
  2235. return rc;
  2236. }
  2237. /* Set source for the rest of the controllers */
  2238. display_for_each_ctrl(i, display) {
  2239. ctrl = &display->ctrl[i];
  2240. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2241. continue;
  2242. info = &ctrl->ctrl->clk_info;
  2243. if (!set_xo)
  2244. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &display->clock_info.pll_clks);
  2245. else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
  2246. rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &info->xo_clk);
  2247. if (rc) {
  2248. DSI_ERR("[%s] failed to set source clocks, rc=%d\n", display->name, rc);
  2249. return rc;
  2250. }
  2251. }
  2252. return 0;
  2253. }
  2254. int dsi_display_phy_pll_toggle(void *priv, bool prepare)
  2255. {
  2256. int rc = 0;
  2257. struct dsi_display *display = priv;
  2258. struct dsi_display_ctrl *m_ctrl;
  2259. if (!display) {
  2260. DSI_ERR("invalid arguments\n");
  2261. return -EINVAL;
  2262. }
  2263. if (is_skip_op_required(display))
  2264. return 0;
  2265. rc = dsi_display_set_clk_src(display, !prepare);
  2266. m_ctrl = &display->ctrl[display->clk_master_idx];
  2267. if (!m_ctrl->phy) {
  2268. DSI_ERR("[%s] PHY not found\n", display->name);
  2269. return -EINVAL;
  2270. }
  2271. rc = dsi_phy_pll_toggle(m_ctrl->phy, prepare);
  2272. return rc;
  2273. }
  2274. int dsi_display_phy_configure(void *priv, bool commit)
  2275. {
  2276. int rc = 0;
  2277. struct dsi_display *display = priv;
  2278. struct dsi_display_ctrl *m_ctrl;
  2279. struct dsi_pll_resource *pll_res;
  2280. struct dsi_ctrl *ctrl;
  2281. if (!display) {
  2282. DSI_ERR("invalid arguments\n");
  2283. return -EINVAL;
  2284. }
  2285. if (is_skip_op_required(display))
  2286. return 0;
  2287. m_ctrl = &display->ctrl[display->clk_master_idx];
  2288. if ((!m_ctrl->phy) || (!m_ctrl->ctrl)) {
  2289. DSI_ERR("[%s] PHY not found\n", display->name);
  2290. return -EINVAL;
  2291. }
  2292. pll_res = m_ctrl->phy->pll;
  2293. if (!pll_res) {
  2294. DSI_ERR("[%s] PLL res not found\n", display->name);
  2295. return -EINVAL;
  2296. }
  2297. ctrl = m_ctrl->ctrl;
  2298. pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
  2299. pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
  2300. rc = dsi_phy_configure(m_ctrl->phy, commit);
  2301. return rc;
  2302. }
  2303. static int dsi_display_phy_reset_config(struct dsi_display *display,
  2304. bool enable)
  2305. {
  2306. int rc = 0;
  2307. int i;
  2308. struct dsi_display_ctrl *ctrl;
  2309. display_for_each_ctrl(i, display) {
  2310. ctrl = &display->ctrl[i];
  2311. rc = dsi_ctrl_phy_reset_config(ctrl->ctrl, enable);
  2312. if (rc) {
  2313. DSI_ERR("[%s] failed to %s phy reset, rc=%d\n",
  2314. display->name, enable ? "mask" : "unmask", rc);
  2315. return rc;
  2316. }
  2317. }
  2318. return 0;
  2319. }
  2320. static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
  2321. {
  2322. struct dsi_display_ctrl *ctrl;
  2323. int i;
  2324. if (!display)
  2325. return;
  2326. display_for_each_ctrl(i, display) {
  2327. ctrl = &display->ctrl[i];
  2328. dsi_phy_toggle_resync_fifo(ctrl->phy);
  2329. }
  2330. /*
  2331. * After retime buffer synchronization we need to turn of clk_en_sel
  2332. * bit on each phy. Avoid this for Cphy.
  2333. */
  2334. if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY)
  2335. return;
  2336. display_for_each_ctrl(i, display) {
  2337. ctrl = &display->ctrl[i];
  2338. dsi_phy_reset_clk_en_sel(ctrl->phy);
  2339. }
  2340. }
  2341. static int dsi_display_ctrl_update(struct dsi_display *display)
  2342. {
  2343. int rc = 0;
  2344. int i;
  2345. struct dsi_display_ctrl *ctrl;
  2346. display_for_each_ctrl(i, display) {
  2347. ctrl = &display->ctrl[i];
  2348. rc = dsi_ctrl_host_timing_update(ctrl->ctrl);
  2349. if (rc) {
  2350. DSI_ERR("[%s] failed to update host_%d, rc=%d\n",
  2351. display->name, i, rc);
  2352. goto error_host_deinit;
  2353. }
  2354. }
  2355. return 0;
  2356. error_host_deinit:
  2357. for (i = i - 1; i >= 0; i--) {
  2358. ctrl = &display->ctrl[i];
  2359. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2360. }
  2361. return rc;
  2362. }
  2363. static int dsi_display_ctrl_init(struct dsi_display *display)
  2364. {
  2365. int rc = 0;
  2366. int i;
  2367. struct dsi_display_ctrl *ctrl;
  2368. bool skip_op = is_skip_op_required(display);
  2369. /* when ULPS suspend feature is enabled, we will keep the lanes in
  2370. * ULPS during suspend state and clamp DSI phy. Hence while resuming
  2371. * we will programe DSI controller as part of core clock enable.
  2372. * After that we should not re-configure DSI controller again here for
  2373. * usecases where we are resuming from ulps suspend as it might put
  2374. * the HW in bad state.
  2375. */
  2376. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  2377. display_for_each_ctrl(i, display) {
  2378. ctrl = &display->ctrl[i];
  2379. rc = dsi_ctrl_host_init(ctrl->ctrl, skip_op);
  2380. if (rc) {
  2381. DSI_ERR(
  2382. "[%s] failed to init host_%d, skip_op=%d, rc=%d\n",
  2383. display->name, i, skip_op, rc);
  2384. goto error_host_deinit;
  2385. }
  2386. }
  2387. } else {
  2388. display_for_each_ctrl(i, display) {
  2389. ctrl = &display->ctrl[i];
  2390. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2391. DSI_CTRL_OP_HOST_INIT,
  2392. true);
  2393. if (rc)
  2394. DSI_DEBUG("host init update failed rc=%d\n",
  2395. rc);
  2396. }
  2397. }
  2398. return rc;
  2399. error_host_deinit:
  2400. for (i = i - 1; i >= 0; i--) {
  2401. ctrl = &display->ctrl[i];
  2402. (void)dsi_ctrl_host_deinit(ctrl->ctrl);
  2403. }
  2404. return rc;
  2405. }
  2406. static int dsi_display_ctrl_deinit(struct dsi_display *display)
  2407. {
  2408. int rc = 0;
  2409. int i;
  2410. struct dsi_display_ctrl *ctrl;
  2411. display_for_each_ctrl(i, display) {
  2412. ctrl = &display->ctrl[i];
  2413. rc = dsi_ctrl_host_deinit(ctrl->ctrl);
  2414. if (rc) {
  2415. DSI_ERR("[%s] failed to deinit host_%d, rc=%d\n",
  2416. display->name, i, rc);
  2417. }
  2418. }
  2419. return rc;
  2420. }
  2421. static int dsi_display_ctrl_host_enable(struct dsi_display *display)
  2422. {
  2423. int rc = 0;
  2424. int i;
  2425. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2426. bool skip_op = is_skip_op_required(display);
  2427. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2428. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2429. DSI_CTRL_ENGINE_ON, skip_op);
  2430. if (rc) {
  2431. DSI_ERR("[%s]enable host engine failed, skip_op:%d rc:%d\n",
  2432. display->name, skip_op, rc);
  2433. goto error;
  2434. }
  2435. display_for_each_ctrl(i, display) {
  2436. ctrl = &display->ctrl[i];
  2437. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2438. continue;
  2439. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2440. DSI_CTRL_ENGINE_ON, skip_op);
  2441. if (rc) {
  2442. DSI_ERR(
  2443. "[%s] enable host engine failed, skip_op:%d rc:%d\n",
  2444. display->name, skip_op, rc);
  2445. goto error_disable_master;
  2446. }
  2447. }
  2448. return rc;
  2449. error_disable_master:
  2450. (void)dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2451. DSI_CTRL_ENGINE_OFF, skip_op);
  2452. error:
  2453. return rc;
  2454. }
  2455. static int dsi_display_ctrl_host_disable(struct dsi_display *display)
  2456. {
  2457. int rc = 0;
  2458. int i;
  2459. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2460. bool skip_op = is_skip_op_required(display);
  2461. /*
  2462. * This is a defensive check. In reality as this is called after panel OFF commands, which
  2463. * can never be ASYNC, the controller post_tx_queued flag will never be set when this API
  2464. * is called.
  2465. */
  2466. display_for_each_ctrl(i, display) {
  2467. ctrl = &display->ctrl[i];
  2468. if (!ctrl->ctrl || !(ctrl->ctrl->post_tx_queued))
  2469. continue;
  2470. flush_workqueue(display->post_cmd_tx_workq);
  2471. cancel_work_sync(&ctrl->ctrl->post_cmd_tx_work);
  2472. ctrl->ctrl->post_tx_queued = false;
  2473. }
  2474. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2475. /*
  2476. * For platforms where ULPS is controlled by DSI controller block,
  2477. * do not disable dsi controller block if lanes are to be
  2478. * kept in ULPS during suspend. So just update the SW state
  2479. * and return early.
  2480. */
  2481. if (display->panel->ulps_suspend_enabled &&
  2482. !m_ctrl->phy->hw.ops.ulps_ops.ulps_request) {
  2483. display_for_each_ctrl(i, display) {
  2484. ctrl = &display->ctrl[i];
  2485. rc = dsi_ctrl_update_host_state(ctrl->ctrl,
  2486. DSI_CTRL_OP_HOST_ENGINE,
  2487. false);
  2488. if (rc)
  2489. DSI_DEBUG("host state update failed %d\n", rc);
  2490. }
  2491. return rc;
  2492. }
  2493. display_for_each_ctrl(i, display) {
  2494. ctrl = &display->ctrl[i];
  2495. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2496. continue;
  2497. rc = dsi_ctrl_set_host_engine_state(ctrl->ctrl,
  2498. DSI_CTRL_ENGINE_OFF, skip_op);
  2499. if (rc)
  2500. DSI_ERR(
  2501. "[%s] disable host engine failed, skip_op:%d rc:%d\n",
  2502. display->name, skip_op, rc);
  2503. }
  2504. rc = dsi_ctrl_set_host_engine_state(m_ctrl->ctrl,
  2505. DSI_CTRL_ENGINE_OFF, skip_op);
  2506. if (rc) {
  2507. DSI_ERR("[%s] disable mhost engine failed, skip_op:%d rc:%d\n",
  2508. display->name, skip_op, rc);
  2509. goto error;
  2510. }
  2511. error:
  2512. return rc;
  2513. }
  2514. static int dsi_display_vid_engine_enable(struct dsi_display *display)
  2515. {
  2516. int rc = 0;
  2517. int i;
  2518. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2519. bool skip_op = is_skip_op_required(display);
  2520. m_ctrl = &display->ctrl[display->video_master_idx];
  2521. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2522. DSI_CTRL_ENGINE_ON, skip_op);
  2523. if (rc) {
  2524. DSI_ERR("[%s] enable mvid engine failed, skip_op:%d rc:%d\n",
  2525. display->name, skip_op, rc);
  2526. goto error;
  2527. }
  2528. display_for_each_ctrl(i, display) {
  2529. ctrl = &display->ctrl[i];
  2530. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2531. continue;
  2532. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2533. DSI_CTRL_ENGINE_ON, skip_op);
  2534. if (rc) {
  2535. DSI_ERR(
  2536. "[%s] enable vid engine failed, skip_op:%d rc:%d\n",
  2537. display->name, skip_op, rc);
  2538. goto error_disable_master;
  2539. }
  2540. }
  2541. return rc;
  2542. error_disable_master:
  2543. (void)dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2544. DSI_CTRL_ENGINE_OFF, skip_op);
  2545. error:
  2546. return rc;
  2547. }
  2548. static int dsi_display_vid_engine_disable(struct dsi_display *display)
  2549. {
  2550. int rc = 0;
  2551. int i;
  2552. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2553. bool skip_op = is_skip_op_required(display);
  2554. m_ctrl = &display->ctrl[display->video_master_idx];
  2555. display_for_each_ctrl(i, display) {
  2556. ctrl = &display->ctrl[i];
  2557. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2558. continue;
  2559. rc = dsi_ctrl_set_vid_engine_state(ctrl->ctrl,
  2560. DSI_CTRL_ENGINE_OFF, skip_op);
  2561. if (rc)
  2562. DSI_ERR(
  2563. "[%s] disable vid engine failed, skip_op:%d rc:%d\n",
  2564. display->name, skip_op, rc);
  2565. }
  2566. rc = dsi_ctrl_set_vid_engine_state(m_ctrl->ctrl,
  2567. DSI_CTRL_ENGINE_OFF, skip_op);
  2568. if (rc)
  2569. DSI_ERR("[%s] disable mvid engine failed, skip_op:%d rc:%d\n",
  2570. display->name, skip_op, rc);
  2571. return rc;
  2572. }
  2573. static int dsi_display_phy_enable(struct dsi_display *display)
  2574. {
  2575. int rc = 0;
  2576. int i;
  2577. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2578. enum dsi_phy_pll_source m_src = DSI_PLL_SOURCE_STANDALONE;
  2579. bool skip_op = is_skip_op_required(display);
  2580. m_ctrl = &display->ctrl[display->clk_master_idx];
  2581. if (display->ctrl_count > 1)
  2582. m_src = DSI_PLL_SOURCE_NATIVE;
  2583. rc = dsi_phy_enable(m_ctrl->phy, &display->config,
  2584. m_src, true, skip_op);
  2585. if (rc) {
  2586. DSI_ERR("[%s] failed to enable DSI PHY, skip_op=%d rc=%d\n",
  2587. display->name, skip_op, rc);
  2588. goto error;
  2589. }
  2590. display_for_each_ctrl(i, display) {
  2591. ctrl = &display->ctrl[i];
  2592. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2593. continue;
  2594. rc = dsi_phy_enable(ctrl->phy, &display->config,
  2595. DSI_PLL_SOURCE_NON_NATIVE, true, skip_op);
  2596. if (rc) {
  2597. DSI_ERR(
  2598. "[%s] failed to enable DSI PHY, skip_op: %d rc=%d\n",
  2599. display->name, skip_op, rc);
  2600. goto error_disable_master;
  2601. }
  2602. }
  2603. return rc;
  2604. error_disable_master:
  2605. (void)dsi_phy_disable(m_ctrl->phy, skip_op);
  2606. error:
  2607. return rc;
  2608. }
  2609. static int dsi_display_phy_disable(struct dsi_display *display)
  2610. {
  2611. int rc = 0;
  2612. int i;
  2613. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2614. bool skip_op = is_skip_op_required(display);
  2615. m_ctrl = &display->ctrl[display->clk_master_idx];
  2616. display_for_each_ctrl(i, display) {
  2617. ctrl = &display->ctrl[i];
  2618. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2619. continue;
  2620. rc = dsi_phy_disable(ctrl->phy, skip_op);
  2621. if (rc)
  2622. DSI_ERR(
  2623. "[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2624. display->name, skip_op, rc);
  2625. }
  2626. rc = dsi_phy_disable(m_ctrl->phy, skip_op);
  2627. if (rc)
  2628. DSI_ERR("[%s] failed to disable DSI PHY, skip_op=%d rc=%d\n",
  2629. display->name, skip_op, rc);
  2630. return rc;
  2631. }
  2632. static int dsi_display_wake_up(struct dsi_display *display)
  2633. {
  2634. return 0;
  2635. }
  2636. static int dsi_display_broadcast_cmd(struct dsi_display *display, struct dsi_cmd_desc *cmd)
  2637. {
  2638. int rc = 0;
  2639. struct dsi_display_ctrl *ctrl, *m_ctrl;
  2640. int i;
  2641. u32 flags = 0;
  2642. /*
  2643. * 1. Setup commands in FIFO
  2644. * 2. Trigger commands
  2645. */
  2646. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2647. display_for_each_ctrl(i, display) {
  2648. ctrl = &display->ctrl[i];
  2649. flags = cmd->ctrl_flags;
  2650. if (ctrl == m_ctrl)
  2651. flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2652. rc = dsi_ctrl_transfer_prepare(ctrl->ctrl, flags);
  2653. if (rc) {
  2654. DSI_ERR("[%s] prepare for cmd transfer failed,rc=%d\n",
  2655. display->name, rc);
  2656. if (ctrl != m_ctrl)
  2657. dsi_ctrl_transfer_unprepare(m_ctrl->ctrl, flags |
  2658. DSI_CTRL_CMD_BROADCAST_MASTER);
  2659. return rc;
  2660. }
  2661. }
  2662. cmd->ctrl_flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2663. rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, cmd);
  2664. if (rc) {
  2665. DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n",
  2666. display->name, rc);
  2667. goto error;
  2668. }
  2669. cmd->ctrl_flags &= ~DSI_CTRL_CMD_BROADCAST_MASTER;
  2670. display_for_each_ctrl(i, display) {
  2671. ctrl = &display->ctrl[i];
  2672. if (ctrl == m_ctrl)
  2673. continue;
  2674. rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, cmd);
  2675. if (rc) {
  2676. DSI_ERR("[%s] cmd transfer failed, rc=%d\n",
  2677. display->name, rc);
  2678. goto error;
  2679. }
  2680. rc = dsi_ctrl_cmd_tx_trigger(ctrl->ctrl, cmd->ctrl_flags);
  2681. if (rc) {
  2682. DSI_ERR("[%s] cmd trigger failed, rc=%d\n",
  2683. display->name, rc);
  2684. goto error;
  2685. }
  2686. }
  2687. rc = dsi_ctrl_cmd_tx_trigger(m_ctrl->ctrl, cmd->ctrl_flags | DSI_CTRL_CMD_BROADCAST_MASTER);
  2688. if (rc) {
  2689. DSI_ERR("[%s] cmd trigger failed for master, rc=%d\n",
  2690. display->name, rc);
  2691. goto error;
  2692. }
  2693. error:
  2694. display_for_each_ctrl(i, display) {
  2695. ctrl = &display->ctrl[i];
  2696. flags = cmd->ctrl_flags;
  2697. if (ctrl == m_ctrl)
  2698. flags |= DSI_CTRL_CMD_BROADCAST_MASTER;
  2699. dsi_ctrl_transfer_unprepare(ctrl->ctrl, flags);
  2700. }
  2701. return rc;
  2702. }
  2703. static int dsi_display_phy_sw_reset(struct dsi_display *display)
  2704. {
  2705. int rc = 0;
  2706. int i;
  2707. struct dsi_display_ctrl *m_ctrl, *ctrl;
  2708. /*
  2709. * For continuous splash and trusted vm environment,
  2710. * ctrl states are updated separately and hence we do
  2711. * an early return
  2712. */
  2713. if (is_skip_op_required(display)) {
  2714. DSI_DEBUG(
  2715. "cont splash/trusted vm use case, phy sw reset not required\n");
  2716. return 0;
  2717. }
  2718. m_ctrl = &display->ctrl[display->cmd_master_idx];
  2719. rc = dsi_ctrl_phy_sw_reset(m_ctrl->ctrl);
  2720. if (rc) {
  2721. DSI_ERR("[%s] failed to reset phy, rc=%d\n", display->name, rc);
  2722. goto error;
  2723. }
  2724. display_for_each_ctrl(i, display) {
  2725. ctrl = &display->ctrl[i];
  2726. if (!ctrl->ctrl || (ctrl == m_ctrl))
  2727. continue;
  2728. rc = dsi_ctrl_phy_sw_reset(ctrl->ctrl);
  2729. if (rc) {
  2730. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  2731. display->name, rc);
  2732. goto error;
  2733. }
  2734. }
  2735. error:
  2736. return rc;
  2737. }
  2738. static int dsi_host_attach(struct mipi_dsi_host *host,
  2739. struct mipi_dsi_device *dsi)
  2740. {
  2741. return 0;
  2742. }
  2743. static int dsi_host_detach(struct mipi_dsi_host *host,
  2744. struct mipi_dsi_device *dsi)
  2745. {
  2746. return 0;
  2747. }
  2748. int dsi_host_transfer_sub(struct mipi_dsi_host *host, struct dsi_cmd_desc *cmd)
  2749. {
  2750. struct dsi_display *display;
  2751. int rc = 0;
  2752. if (!host || !cmd) {
  2753. DSI_ERR("Invalid params\n");
  2754. return 0;
  2755. }
  2756. display = to_dsi_display(host);
  2757. /* Avoid sending DCS commands when ESD recovery is pending */
  2758. if (atomic_read(&display->panel->esd_recovery_pending)) {
  2759. DSI_DEBUG("ESD recovery pending\n");
  2760. return 0;
  2761. }
  2762. rc = dsi_display_wake_up(display);
  2763. if (rc) {
  2764. DSI_ERR("[%s] failed to wake up display, rc=%d\n", display->name, rc);
  2765. goto error;
  2766. }
  2767. if (display->tx_cmd_buf == NULL) {
  2768. rc = dsi_host_alloc_cmd_tx_buffer(display);
  2769. if (rc) {
  2770. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  2771. goto error;
  2772. }
  2773. }
  2774. dsi_display_set_cmd_tx_ctrl_flags(display, cmd);
  2775. if (cmd->ctrl_flags & DSI_CTRL_CMD_BROADCAST) {
  2776. rc = dsi_display_broadcast_cmd(display, cmd);
  2777. if (rc) {
  2778. DSI_ERR("[%s] cmd broadcast failed, rc=%d\n", display->name, rc);
  2779. goto error;
  2780. }
  2781. } else {
  2782. int idx = cmd->ctrl;
  2783. rc = dsi_ctrl_transfer_prepare(display->ctrl[idx].ctrl, cmd->ctrl_flags);
  2784. if (rc) {
  2785. DSI_ERR("failed to prepare for command transfer: %d\n", rc);
  2786. goto error;
  2787. }
  2788. rc = dsi_ctrl_cmd_transfer(display->ctrl[idx].ctrl, cmd);
  2789. if (rc)
  2790. DSI_ERR("[%s] cmd transfer failed, rc=%d\n", display->name, rc);
  2791. dsi_ctrl_transfer_unprepare(display->ctrl[idx].ctrl, cmd->ctrl_flags);
  2792. }
  2793. error:
  2794. return rc;
  2795. }
  2796. static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg)
  2797. {
  2798. int rc = 0;
  2799. struct dsi_cmd_desc cmd;
  2800. if (!msg) {
  2801. DSI_ERR("Invalid params\n");
  2802. return 0;
  2803. }
  2804. memcpy(&cmd.msg, msg, sizeof(*msg));
  2805. cmd.ctrl = 0;
  2806. cmd.post_wait_ms = 0;
  2807. cmd.ctrl_flags = 0;
  2808. rc = dsi_host_transfer_sub(host, &cmd);
  2809. return rc;
  2810. }
  2811. static struct mipi_dsi_host_ops dsi_host_ops = {
  2812. .attach = dsi_host_attach,
  2813. .detach = dsi_host_detach,
  2814. .transfer = dsi_host_transfer,
  2815. };
  2816. static int dsi_display_mipi_host_init(struct dsi_display *display)
  2817. {
  2818. int rc = 0;
  2819. struct mipi_dsi_host *host = &display->host;
  2820. host->dev = &display->pdev->dev;
  2821. host->ops = &dsi_host_ops;
  2822. rc = mipi_dsi_host_register(host);
  2823. if (rc) {
  2824. DSI_ERR("[%s] failed to register mipi dsi host, rc=%d\n",
  2825. display->name, rc);
  2826. goto error;
  2827. }
  2828. error:
  2829. return rc;
  2830. }
  2831. static int dsi_display_mipi_host_deinit(struct dsi_display *display)
  2832. {
  2833. int rc = 0;
  2834. struct mipi_dsi_host *host = &display->host;
  2835. mipi_dsi_host_unregister(host);
  2836. host->dev = NULL;
  2837. host->ops = NULL;
  2838. return rc;
  2839. }
  2840. static bool dsi_display_check_prefix(const char *clk_prefix,
  2841. const char *clk_name)
  2842. {
  2843. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  2844. }
  2845. static int dsi_display_get_clocks_count(struct dsi_display *display,
  2846. char *dsi_clk_name)
  2847. {
  2848. if (display->fw)
  2849. return dsi_parser_count_strings(display->parser_node,
  2850. dsi_clk_name);
  2851. else
  2852. return of_property_count_strings(display->panel_node,
  2853. dsi_clk_name);
  2854. }
  2855. static void dsi_display_get_clock_name(struct dsi_display *display,
  2856. char *dsi_clk_name, int index,
  2857. const char **clk_name)
  2858. {
  2859. if (display->fw)
  2860. dsi_parser_read_string_index(display->parser_node,
  2861. dsi_clk_name, index, clk_name);
  2862. else
  2863. of_property_read_string_index(display->panel_node,
  2864. dsi_clk_name, index, clk_name);
  2865. }
  2866. static int dsi_display_clocks_init(struct dsi_display *display)
  2867. {
  2868. int i, rc = 0, num_clk = 0;
  2869. const char *clk_name;
  2870. const char *pll_byte = "pll_byte", *pll_dsi = "pll_dsi";
  2871. struct clk *dsi_clk;
  2872. struct dsi_clk_link_set *pll = &display->clock_info.pll_clks;
  2873. char *dsi_clock_name;
  2874. if (!strcmp(display->display_type, "primary"))
  2875. dsi_clock_name = "qcom,dsi-select-clocks";
  2876. else
  2877. dsi_clock_name = "qcom,dsi-select-sec-clocks";
  2878. num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
  2879. for (i = 0; i < num_clk; i++) {
  2880. dsi_display_get_clock_name(display, dsi_clock_name, i,
  2881. &clk_name);
  2882. DSI_DEBUG("clock name:%s\n", clk_name);
  2883. dsi_clk = devm_clk_get(&display->pdev->dev, clk_name);
  2884. if (IS_ERR_OR_NULL(dsi_clk)) {
  2885. rc = PTR_ERR(dsi_clk);
  2886. DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
  2887. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2888. pll->byte_clk = NULL;
  2889. goto error;
  2890. }
  2891. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2892. pll->pixel_clk = NULL;
  2893. goto error;
  2894. }
  2895. }
  2896. if (dsi_display_check_prefix(pll_byte, clk_name)) {
  2897. pll->byte_clk = dsi_clk;
  2898. continue;
  2899. }
  2900. if (dsi_display_check_prefix(pll_dsi, clk_name)) {
  2901. pll->pixel_clk = dsi_clk;
  2902. continue;
  2903. }
  2904. }
  2905. return 0;
  2906. error:
  2907. return rc;
  2908. }
  2909. static int dsi_display_clk_ctrl_cb(void *priv,
  2910. struct dsi_clk_ctrl_info clk_state_info)
  2911. {
  2912. int rc = 0;
  2913. struct dsi_display *display = NULL;
  2914. void *clk_handle = NULL;
  2915. if (!priv) {
  2916. DSI_ERR("Invalid params\n");
  2917. return -EINVAL;
  2918. }
  2919. display = priv;
  2920. if (clk_state_info.client == DSI_CLK_REQ_MDP_CLIENT) {
  2921. clk_handle = display->mdp_clk_handle;
  2922. } else if (clk_state_info.client == DSI_CLK_REQ_DSI_CLIENT) {
  2923. clk_handle = display->dsi_clk_handle;
  2924. } else {
  2925. DSI_ERR("invalid clk handle, return error\n");
  2926. return -EINVAL;
  2927. }
  2928. /*
  2929. * TODO: Wait for CMD_MDP_DONE interrupt if MDP client tries
  2930. * to turn off DSI clocks.
  2931. */
  2932. rc = dsi_display_clk_ctrl(clk_handle,
  2933. clk_state_info.clk_type, clk_state_info.clk_state);
  2934. if (rc) {
  2935. DSI_ERR("[%s] failed to %d DSI %d clocks, rc=%d\n",
  2936. display->name, clk_state_info.clk_state,
  2937. clk_state_info.clk_type, rc);
  2938. return rc;
  2939. }
  2940. return 0;
  2941. }
  2942. static void dsi_display_ctrl_isr_configure(struct dsi_display *display, bool en)
  2943. {
  2944. int i;
  2945. struct dsi_display_ctrl *ctrl;
  2946. if (!display)
  2947. return;
  2948. display_for_each_ctrl(i, display) {
  2949. ctrl = &display->ctrl[i];
  2950. if (!ctrl)
  2951. continue;
  2952. dsi_ctrl_isr_configure(ctrl->ctrl, en);
  2953. }
  2954. }
  2955. int dsi_pre_clkoff_cb(void *priv,
  2956. enum dsi_clk_type clk,
  2957. enum dsi_lclk_type l_type,
  2958. enum dsi_clk_state new_state)
  2959. {
  2960. int rc = 0, i;
  2961. struct dsi_display *display = priv;
  2962. struct dsi_display_ctrl *ctrl;
  2963. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2964. (l_type & DSI_LINK_LP_CLK)) {
  2965. /*
  2966. * If continuous clock is enabled then disable it
  2967. * before entering into ULPS Mode.
  2968. */
  2969. if (display->panel->host_config.force_hs_clk_lane)
  2970. _dsi_display_continuous_clk_ctrl(display, false);
  2971. /*
  2972. * If ULPS feature is enabled, enter ULPS first.
  2973. * However, when blanking the panel, we should enter ULPS
  2974. * only if ULPS during suspend feature is enabled.
  2975. */
  2976. if (!dsi_panel_initialized(display->panel)) {
  2977. if (display->panel->ulps_suspend_enabled)
  2978. rc = dsi_display_set_ulps(display, true);
  2979. } else if (dsi_panel_ulps_feature_enabled(display->panel)) {
  2980. rc = dsi_display_set_ulps(display, true);
  2981. }
  2982. if (rc)
  2983. DSI_ERR("%s: failed enable ulps, rc = %d\n",
  2984. __func__, rc);
  2985. }
  2986. if ((clk & DSI_LINK_CLK) && (new_state == DSI_CLK_OFF) &&
  2987. (l_type & DSI_LINK_HS_CLK)) {
  2988. /*
  2989. * PHY clock gating should be disabled before the PLL and the
  2990. * branch clocks are turned off. Otherwise, it is possible that
  2991. * the clock RCGs may not be turned off correctly resulting
  2992. * in clock warnings.
  2993. */
  2994. rc = dsi_display_config_clk_gating(display, false);
  2995. if (rc)
  2996. DSI_ERR("[%s] failed to disable clk gating, rc=%d\n",
  2997. display->name, rc);
  2998. }
  2999. if ((clk & DSI_CORE_CLK) && (new_state == DSI_CLK_OFF)) {
  3000. /*
  3001. * Enable DSI clamps only if entering idle power collapse or
  3002. * when ULPS during suspend is enabled..
  3003. */
  3004. if (dsi_panel_initialized(display->panel) ||
  3005. display->panel->ulps_suspend_enabled) {
  3006. dsi_display_phy_idle_off(display);
  3007. rc = dsi_display_set_clamp(display, true);
  3008. if (rc)
  3009. DSI_ERR("%s: Failed to enable dsi clamps. rc=%d\n",
  3010. __func__, rc);
  3011. rc = dsi_display_phy_reset_config(display, false);
  3012. if (rc)
  3013. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3014. __func__, rc);
  3015. } else {
  3016. /* Make sure that controller is not in ULPS state when
  3017. * the DSI link is not active.
  3018. */
  3019. rc = dsi_display_set_ulps(display, false);
  3020. if (rc)
  3021. DSI_ERR("%s: failed to disable ulps. rc=%d\n",
  3022. __func__, rc);
  3023. }
  3024. /* dsi will not be able to serve irqs from here on */
  3025. dsi_display_ctrl_irq_update(display, false);
  3026. /* cache the MISR values */
  3027. display_for_each_ctrl(i, display) {
  3028. ctrl = &display->ctrl[i];
  3029. if (!ctrl->ctrl)
  3030. continue;
  3031. dsi_ctrl_cache_misr(ctrl->ctrl);
  3032. }
  3033. }
  3034. return rc;
  3035. }
  3036. int dsi_post_clkon_cb(void *priv,
  3037. enum dsi_clk_type clk,
  3038. enum dsi_lclk_type l_type,
  3039. enum dsi_clk_state curr_state)
  3040. {
  3041. int rc = 0;
  3042. struct dsi_display *display = priv;
  3043. bool mmss_clamp = false;
  3044. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_LP_CLK)) {
  3045. mmss_clamp = display->clamp_enabled;
  3046. /*
  3047. * controller setup is needed if coming out of idle
  3048. * power collapse with clamps enabled.
  3049. */
  3050. if (mmss_clamp)
  3051. dsi_display_ctrl_setup(display);
  3052. /*
  3053. * Phy setup is needed if coming out of idle
  3054. * power collapse with clamps enabled.
  3055. */
  3056. if (display->phy_idle_power_off || mmss_clamp)
  3057. dsi_display_phy_idle_on(display, mmss_clamp);
  3058. if (display->ulps_enabled && mmss_clamp) {
  3059. /*
  3060. * ULPS Entry Request. This is needed if the lanes were
  3061. * in ULPS prior to power collapse, since after
  3062. * power collapse and reset, the DSI controller resets
  3063. * back to idle state and not ULPS. This ulps entry
  3064. * request will transition the state of the DSI
  3065. * controller to ULPS which will match the state of the
  3066. * DSI phy. This needs to be done prior to disabling
  3067. * the DSI clamps.
  3068. *
  3069. * Also, reset the ulps flag so that ulps_config
  3070. * function would reconfigure the controller state to
  3071. * ULPS.
  3072. */
  3073. display->ulps_enabled = false;
  3074. rc = dsi_display_set_ulps(display, true);
  3075. if (rc) {
  3076. DSI_ERR("%s: Failed to enter ULPS. rc=%d\n",
  3077. __func__, rc);
  3078. goto error;
  3079. }
  3080. }
  3081. rc = dsi_display_phy_reset_config(display, true);
  3082. if (rc) {
  3083. DSI_ERR("%s: Failed to reset phy, rc=%d\n",
  3084. __func__, rc);
  3085. goto error;
  3086. }
  3087. rc = dsi_display_set_clamp(display, false);
  3088. if (rc) {
  3089. DSI_ERR("%s: Failed to disable dsi clamps. rc=%d\n",
  3090. __func__, rc);
  3091. goto error;
  3092. }
  3093. }
  3094. if ((clk & DSI_LINK_CLK) && (l_type & DSI_LINK_HS_CLK)) {
  3095. /*
  3096. * Toggle the resync FIFO everytime clock changes, except
  3097. * when cont-splash screen transition is going on.
  3098. * Toggling resync FIFO during cont splash transition
  3099. * can lead to blinks on the display.
  3100. */
  3101. if (!display->is_cont_splash_enabled)
  3102. dsi_display_toggle_resync_fifo(display);
  3103. if (display->ulps_enabled) {
  3104. rc = dsi_display_set_ulps(display, false);
  3105. if (rc) {
  3106. DSI_ERR("%s: failed to disable ulps, rc= %d\n",
  3107. __func__, rc);
  3108. goto error;
  3109. }
  3110. }
  3111. if (display->panel->host_config.force_hs_clk_lane)
  3112. _dsi_display_continuous_clk_ctrl(display, true);
  3113. rc = dsi_display_config_clk_gating(display, true);
  3114. if (rc) {
  3115. DSI_ERR("[%s] failed to enable clk gating %d\n",
  3116. display->name, rc);
  3117. goto error;
  3118. }
  3119. }
  3120. /* enable dsi to serve irqs */
  3121. if (clk & DSI_CORE_CLK)
  3122. dsi_display_ctrl_irq_update(display, true);
  3123. error:
  3124. return rc;
  3125. }
  3126. int dsi_post_clkoff_cb(void *priv,
  3127. enum dsi_clk_type clk_type,
  3128. enum dsi_lclk_type l_type,
  3129. enum dsi_clk_state curr_state)
  3130. {
  3131. int rc = 0;
  3132. struct dsi_display *display = priv;
  3133. if (!display) {
  3134. DSI_ERR("%s: Invalid arg\n", __func__);
  3135. return -EINVAL;
  3136. }
  3137. if ((clk_type & DSI_CORE_CLK) &&
  3138. (curr_state == DSI_CLK_OFF)) {
  3139. rc = dsi_display_phy_power_off(display);
  3140. if (rc)
  3141. DSI_ERR("[%s] failed to power off PHY, rc=%d\n",
  3142. display->name, rc);
  3143. rc = dsi_display_ctrl_power_off(display);
  3144. if (rc)
  3145. DSI_ERR("[%s] failed to power DSI vregs, rc=%d\n",
  3146. display->name, rc);
  3147. }
  3148. return rc;
  3149. }
  3150. int dsi_pre_clkon_cb(void *priv,
  3151. enum dsi_clk_type clk_type,
  3152. enum dsi_lclk_type l_type,
  3153. enum dsi_clk_state new_state)
  3154. {
  3155. int rc = 0;
  3156. struct dsi_display *display = priv;
  3157. if (!display) {
  3158. DSI_ERR("%s: invalid input\n", __func__);
  3159. return -EINVAL;
  3160. }
  3161. if ((clk_type & DSI_CORE_CLK) && (new_state == DSI_CLK_ON)) {
  3162. /*
  3163. * Enable DSI core power
  3164. * 1.> PANEL_PM are controlled as part of
  3165. * panel_power_ctrl. Needed not be handled here.
  3166. * 2.> CTRL_PM need to be enabled/disabled
  3167. * only during unblank/blank. Their state should
  3168. * not be changed during static screen.
  3169. */
  3170. DSI_DEBUG("updating power states for ctrl and phy\n");
  3171. rc = dsi_display_ctrl_power_on(display);
  3172. if (rc) {
  3173. DSI_ERR("[%s] failed to power on dsi controllers, rc=%d\n",
  3174. display->name, rc);
  3175. return rc;
  3176. }
  3177. rc = dsi_display_phy_power_on(display);
  3178. if (rc) {
  3179. DSI_ERR("[%s] failed to power on dsi phy, rc = %d\n",
  3180. display->name, rc);
  3181. return rc;
  3182. }
  3183. DSI_DEBUG("%s: Enable DSI core power\n", __func__);
  3184. }
  3185. return rc;
  3186. }
  3187. static void __set_lane_map_v2(u8 *lane_map_v2,
  3188. enum dsi_phy_data_lanes lane0,
  3189. enum dsi_phy_data_lanes lane1,
  3190. enum dsi_phy_data_lanes lane2,
  3191. enum dsi_phy_data_lanes lane3)
  3192. {
  3193. lane_map_v2[DSI_LOGICAL_LANE_0] = lane0;
  3194. lane_map_v2[DSI_LOGICAL_LANE_1] = lane1;
  3195. lane_map_v2[DSI_LOGICAL_LANE_2] = lane2;
  3196. lane_map_v2[DSI_LOGICAL_LANE_3] = lane3;
  3197. }
  3198. static int dsi_display_parse_lane_map(struct dsi_display *display)
  3199. {
  3200. int rc = 0, i = 0;
  3201. const char *data;
  3202. u8 temp[DSI_LANE_MAX - 1];
  3203. if (!display) {
  3204. DSI_ERR("invalid params\n");
  3205. return -EINVAL;
  3206. }
  3207. /* lane-map-v2 supersedes lane-map-v1 setting */
  3208. rc = of_property_read_u8_array(display->pdev->dev.of_node,
  3209. "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
  3210. if (!rc) {
  3211. for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
  3212. display->lane_map.lane_map_v2[i] = BIT(temp[i]);
  3213. return 0;
  3214. } else if (rc != EINVAL) {
  3215. DSI_DEBUG("Incorrect mapping, configure default\n");
  3216. goto set_default;
  3217. }
  3218. /* lane-map older version, for DSI controller version < 2.0 */
  3219. data = of_get_property(display->pdev->dev.of_node,
  3220. "qcom,lane-map", NULL);
  3221. if (!data)
  3222. goto set_default;
  3223. if (!strcmp(data, "lane_map_3012")) {
  3224. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3012;
  3225. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3226. DSI_PHYSICAL_LANE_1,
  3227. DSI_PHYSICAL_LANE_2,
  3228. DSI_PHYSICAL_LANE_3,
  3229. DSI_PHYSICAL_LANE_0);
  3230. } else if (!strcmp(data, "lane_map_2301")) {
  3231. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2301;
  3232. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3233. DSI_PHYSICAL_LANE_2,
  3234. DSI_PHYSICAL_LANE_3,
  3235. DSI_PHYSICAL_LANE_0,
  3236. DSI_PHYSICAL_LANE_1);
  3237. } else if (!strcmp(data, "lane_map_1230")) {
  3238. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1230;
  3239. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3240. DSI_PHYSICAL_LANE_3,
  3241. DSI_PHYSICAL_LANE_0,
  3242. DSI_PHYSICAL_LANE_1,
  3243. DSI_PHYSICAL_LANE_2);
  3244. } else if (!strcmp(data, "lane_map_0321")) {
  3245. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0321;
  3246. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3247. DSI_PHYSICAL_LANE_0,
  3248. DSI_PHYSICAL_LANE_3,
  3249. DSI_PHYSICAL_LANE_2,
  3250. DSI_PHYSICAL_LANE_1);
  3251. } else if (!strcmp(data, "lane_map_1032")) {
  3252. display->lane_map.lane_map_v1 = DSI_LANE_MAP_1032;
  3253. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3254. DSI_PHYSICAL_LANE_1,
  3255. DSI_PHYSICAL_LANE_0,
  3256. DSI_PHYSICAL_LANE_3,
  3257. DSI_PHYSICAL_LANE_2);
  3258. } else if (!strcmp(data, "lane_map_2103")) {
  3259. display->lane_map.lane_map_v1 = DSI_LANE_MAP_2103;
  3260. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3261. DSI_PHYSICAL_LANE_2,
  3262. DSI_PHYSICAL_LANE_1,
  3263. DSI_PHYSICAL_LANE_0,
  3264. DSI_PHYSICAL_LANE_3);
  3265. } else if (!strcmp(data, "lane_map_3210")) {
  3266. display->lane_map.lane_map_v1 = DSI_LANE_MAP_3210;
  3267. __set_lane_map_v2(display->lane_map.lane_map_v2,
  3268. DSI_PHYSICAL_LANE_3,
  3269. DSI_PHYSICAL_LANE_2,
  3270. DSI_PHYSICAL_LANE_1,
  3271. DSI_PHYSICAL_LANE_0);
  3272. } else {
  3273. DSI_WARN("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
  3274. __func__, data);
  3275. goto set_default;
  3276. }
  3277. return 0;
  3278. set_default:
  3279. /* default lane mapping */
  3280. __set_lane_map_v2(display->lane_map.lane_map_v2, DSI_PHYSICAL_LANE_0,
  3281. DSI_PHYSICAL_LANE_1, DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
  3282. display->lane_map.lane_map_v1 = DSI_LANE_MAP_0123;
  3283. return 0;
  3284. }
  3285. static int dsi_display_get_phandle_index(
  3286. struct dsi_display *display,
  3287. const char *propname, int count, int index)
  3288. {
  3289. struct device_node *disp_node = display->panel_node;
  3290. u32 *val = NULL;
  3291. int rc = 0;
  3292. val = kcalloc(count, sizeof(*val), GFP_KERNEL);
  3293. if (ZERO_OR_NULL_PTR(val)) {
  3294. rc = -ENOMEM;
  3295. goto end;
  3296. }
  3297. if (index >= count)
  3298. goto end;
  3299. if (display->fw)
  3300. rc = dsi_parser_read_u32_array(display->parser_node,
  3301. propname, val, count);
  3302. else
  3303. rc = of_property_read_u32_array(disp_node, propname,
  3304. val, count);
  3305. if (rc)
  3306. goto end;
  3307. rc = val[index];
  3308. DSI_DEBUG("%s index=%d\n", propname, rc);
  3309. end:
  3310. kfree(val);
  3311. return rc;
  3312. }
  3313. static bool dsi_display_validate_res(struct dsi_display *display)
  3314. {
  3315. struct device_node *of_node = display->pdev->dev.of_node;
  3316. struct of_phandle_iterator it;
  3317. bool ctrl_avail = false;
  3318. bool phy_avail = false;
  3319. /*
  3320. * At least if one of the controller or PHY is present or has been probed, the
  3321. * dsi_display_dev_probe can pass this check. Exact ctrl and PHY match will be
  3322. * done after the DT is parsed.
  3323. */
  3324. of_phandle_iterator_init(&it, of_node, "qcom,dsi-ctrl", NULL, 0);
  3325. while (of_phandle_iterator_next(&it) == 0)
  3326. ctrl_avail |= dsi_ctrl_check_resource(it.node);
  3327. of_phandle_iterator_init(&it, of_node, "qcom,dsi-phy", NULL, 0);
  3328. while (of_phandle_iterator_next(&it) == 0)
  3329. phy_avail |= dsi_phy_check_resource(it.node);
  3330. return (ctrl_avail & phy_avail);
  3331. }
  3332. static int dsi_display_get_phandle_count(struct dsi_display *display,
  3333. const char *propname)
  3334. {
  3335. if (display->fw)
  3336. return dsi_parser_count_u32_elems(display->parser_node,
  3337. propname);
  3338. else
  3339. return of_property_count_u32_elems(display->panel_node,
  3340. propname);
  3341. }
  3342. static int dsi_display_parse_dt(struct dsi_display *display)
  3343. {
  3344. int i, rc = 0;
  3345. u32 phy_count = 0;
  3346. struct device_node *of_node = display->pdev->dev.of_node;
  3347. char *dsi_ctrl_name, *dsi_phy_name;
  3348. if (!strcmp(display->display_type, "primary")) {
  3349. dsi_ctrl_name = "qcom,dsi-ctrl-num";
  3350. dsi_phy_name = "qcom,dsi-phy-num";
  3351. } else {
  3352. dsi_ctrl_name = "qcom,dsi-sec-ctrl-num";
  3353. dsi_phy_name = "qcom,dsi-sec-phy-num";
  3354. }
  3355. display->ctrl_count = dsi_display_get_phandle_count(display,
  3356. dsi_ctrl_name);
  3357. phy_count = dsi_display_get_phandle_count(display, dsi_phy_name);
  3358. DSI_DEBUG("ctrl count=%d, phy count=%d\n",
  3359. display->ctrl_count, phy_count);
  3360. if (!phy_count || !display->ctrl_count) {
  3361. DSI_ERR("no ctrl/phys found\n");
  3362. rc = -ENODEV;
  3363. goto error;
  3364. }
  3365. if (phy_count != display->ctrl_count) {
  3366. DSI_ERR("different ctrl and phy counts\n");
  3367. rc = -ENODEV;
  3368. goto error;
  3369. }
  3370. display_for_each_ctrl(i, display) {
  3371. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  3372. int index;
  3373. index = dsi_display_get_phandle_index(display, dsi_ctrl_name,
  3374. display->ctrl_count, i);
  3375. ctrl->ctrl_of_node = of_parse_phandle(of_node,
  3376. "qcom,dsi-ctrl", index);
  3377. of_node_put(ctrl->ctrl_of_node);
  3378. index = dsi_display_get_phandle_index(display, dsi_phy_name,
  3379. display->ctrl_count, i);
  3380. ctrl->phy_of_node = of_parse_phandle(of_node,
  3381. "qcom,dsi-phy", index);
  3382. of_node_put(ctrl->phy_of_node);
  3383. }
  3384. /* Parse TE data */
  3385. dsi_display_parse_te_data(display);
  3386. /* Parse all external bridges from port 0 */
  3387. display_for_each_ctrl(i, display) {
  3388. display->ext_bridge[i].node_of =
  3389. of_graph_get_remote_node(of_node, 0, i);
  3390. if (display->ext_bridge[i].node_of)
  3391. display->ext_bridge_cnt++;
  3392. else
  3393. break;
  3394. }
  3395. /* Parse Demura data */
  3396. dsi_display_parse_demura_data(display);
  3397. DSI_DEBUG("success\n");
  3398. error:
  3399. return rc;
  3400. }
  3401. static bool dsi_display_validate_panel_resources(struct dsi_display *display)
  3402. {
  3403. if (!is_sim_panel(display)) {
  3404. if (!gpio_is_valid(display->panel->reset_config.reset_gpio)) {
  3405. DSI_ERR("invalid reset gpio for the panel\n");
  3406. return false;
  3407. }
  3408. } else {
  3409. display->panel->power_info.count = 0;
  3410. DSI_DEBUG("no dir set and no request for gpios in sim panel\n");
  3411. }
  3412. return true;
  3413. }
  3414. static int dsi_display_res_init(struct dsi_display *display)
  3415. {
  3416. int rc = 0;
  3417. int i;
  3418. struct dsi_display_ctrl *ctrl;
  3419. display_for_each_ctrl(i, display) {
  3420. ctrl = &display->ctrl[i];
  3421. ctrl->ctrl = dsi_ctrl_get(ctrl->ctrl_of_node);
  3422. if (IS_ERR_OR_NULL(ctrl->ctrl)) {
  3423. rc = PTR_ERR(ctrl->ctrl);
  3424. DSI_ERR("failed to get dsi controller, rc=%d\n", rc);
  3425. ctrl->ctrl = NULL;
  3426. goto error_ctrl_put;
  3427. }
  3428. ctrl->phy = dsi_phy_get(ctrl->phy_of_node);
  3429. if (IS_ERR_OR_NULL(ctrl->phy)) {
  3430. rc = PTR_ERR(ctrl->phy);
  3431. DSI_ERR("failed to get phy controller, rc=%d\n", rc);
  3432. dsi_ctrl_put(ctrl->ctrl);
  3433. ctrl->phy = NULL;
  3434. goto error_ctrl_put;
  3435. }
  3436. }
  3437. display->panel = dsi_panel_get(&display->pdev->dev,
  3438. display->panel_node,
  3439. display->parser_node,
  3440. display->display_type,
  3441. display->cmdline_topology,
  3442. display->trusted_vm_env);
  3443. if (IS_ERR_OR_NULL(display->panel)) {
  3444. rc = PTR_ERR(display->panel);
  3445. DSI_ERR("failed to get panel, rc=%d\n", rc);
  3446. display->panel = NULL;
  3447. goto error_ctrl_put;
  3448. }
  3449. display->panel->te_using_watchdog_timer |= display->sw_te_using_wd;
  3450. if (!dsi_display_validate_panel_resources(display))
  3451. goto error_ctrl_put;
  3452. display_for_each_ctrl(i, display) {
  3453. struct msm_dsi_phy *phy = display->ctrl[i].phy;
  3454. struct dsi_host_common_cfg *host = &display->panel->host_config;
  3455. phy->cfg.force_clk_lane_hs =
  3456. display->panel->host_config.force_hs_clk_lane;
  3457. phy->cfg.phy_type =
  3458. display->panel->host_config.phy_type;
  3459. /*
  3460. * Parse the dynamic clock trim codes for PLL, for video mode panels that have
  3461. * dynamic clock property set.
  3462. */
  3463. if ((display->panel->dyn_clk_caps.dyn_clk_support) &&
  3464. (display->panel->panel_mode == DSI_OP_VIDEO_MODE))
  3465. dsi_phy_pll_parse_dfps_data(phy);
  3466. phy->cfg.split_link.enabled = host->split_link.enabled;
  3467. phy->cfg.split_link.num_sublinks = host->split_link.num_sublinks;
  3468. phy->cfg.split_link.lanes_per_sublink = host->split_link.lanes_per_sublink;
  3469. }
  3470. rc = dsi_display_parse_lane_map(display);
  3471. if (rc) {
  3472. DSI_ERR("Lane map not found, rc=%d\n", rc);
  3473. goto error_ctrl_put;
  3474. }
  3475. rc = dsi_display_clocks_init(display);
  3476. if (rc) {
  3477. DSI_ERR("Failed to parse clock data, rc=%d\n", rc);
  3478. goto error_ctrl_put;
  3479. }
  3480. /**
  3481. * In trusted vm, the connectors will not be enabled
  3482. * until the HW resources are assigned and accepted.
  3483. */
  3484. if (display->trusted_vm_env) {
  3485. display->is_active = false;
  3486. display->hw_ownership = false;
  3487. } else {
  3488. display->is_active = true;
  3489. display->hw_ownership = true;
  3490. }
  3491. return 0;
  3492. error_ctrl_put:
  3493. for (i = i - 1; i >= 0; i--) {
  3494. ctrl = &display->ctrl[i];
  3495. dsi_ctrl_put(ctrl->ctrl);
  3496. dsi_phy_put(ctrl->phy);
  3497. }
  3498. return rc;
  3499. }
  3500. static int dsi_display_res_deinit(struct dsi_display *display)
  3501. {
  3502. int rc = 0;
  3503. int i;
  3504. struct dsi_display_ctrl *ctrl;
  3505. display_for_each_ctrl(i, display) {
  3506. ctrl = &display->ctrl[i];
  3507. dsi_phy_put(ctrl->phy);
  3508. dsi_ctrl_put(ctrl->ctrl);
  3509. }
  3510. if (display->panel)
  3511. dsi_panel_put(display->panel);
  3512. return rc;
  3513. }
  3514. static int dsi_display_validate_mode_set(struct dsi_display *display,
  3515. struct dsi_display_mode *mode,
  3516. u32 flags)
  3517. {
  3518. int rc = 0;
  3519. int i;
  3520. struct dsi_display_ctrl *ctrl;
  3521. /*
  3522. * To set a mode:
  3523. * 1. Controllers should be turned off.
  3524. * 2. Link clocks should be off.
  3525. * 3. Phy should be disabled.
  3526. */
  3527. display_for_each_ctrl(i, display) {
  3528. ctrl = &display->ctrl[i];
  3529. if ((ctrl->power_state > DSI_CTRL_POWER_VREG_ON) ||
  3530. (ctrl->phy_enabled)) {
  3531. rc = -EINVAL;
  3532. goto error;
  3533. }
  3534. }
  3535. error:
  3536. return rc;
  3537. }
  3538. static bool dsi_display_is_seamless_dfps_possible(
  3539. const struct dsi_display *display,
  3540. const struct dsi_display_mode *tgt,
  3541. const enum dsi_dfps_type dfps_type)
  3542. {
  3543. struct dsi_display_mode *cur;
  3544. if (!display || !tgt || !display->panel) {
  3545. DSI_ERR("Invalid params\n");
  3546. return false;
  3547. }
  3548. cur = display->panel->cur_mode;
  3549. if (cur->timing.h_active != tgt->timing.h_active) {
  3550. DSI_DEBUG("timing.h_active differs %d %d\n",
  3551. cur->timing.h_active, tgt->timing.h_active);
  3552. return false;
  3553. }
  3554. if (cur->timing.h_back_porch != tgt->timing.h_back_porch) {
  3555. DSI_DEBUG("timing.h_back_porch differs %d %d\n",
  3556. cur->timing.h_back_porch,
  3557. tgt->timing.h_back_porch);
  3558. return false;
  3559. }
  3560. if (cur->timing.h_sync_width != tgt->timing.h_sync_width) {
  3561. DSI_DEBUG("timing.h_sync_width differs %d %d\n",
  3562. cur->timing.h_sync_width,
  3563. tgt->timing.h_sync_width);
  3564. return false;
  3565. }
  3566. if (cur->timing.h_front_porch != tgt->timing.h_front_porch) {
  3567. DSI_DEBUG("timing.h_front_porch differs %d %d\n",
  3568. cur->timing.h_front_porch,
  3569. tgt->timing.h_front_porch);
  3570. if (dfps_type != DSI_DFPS_IMMEDIATE_HFP)
  3571. return false;
  3572. }
  3573. if (cur->timing.h_skew != tgt->timing.h_skew) {
  3574. DSI_DEBUG("timing.h_skew differs %d %d\n",
  3575. cur->timing.h_skew,
  3576. tgt->timing.h_skew);
  3577. return false;
  3578. }
  3579. /* skip polarity comparison */
  3580. if (cur->timing.v_active != tgt->timing.v_active) {
  3581. DSI_DEBUG("timing.v_active differs %d %d\n",
  3582. cur->timing.v_active,
  3583. tgt->timing.v_active);
  3584. return false;
  3585. }
  3586. if (cur->timing.v_back_porch != tgt->timing.v_back_porch) {
  3587. DSI_DEBUG("timing.v_back_porch differs %d %d\n",
  3588. cur->timing.v_back_porch,
  3589. tgt->timing.v_back_porch);
  3590. return false;
  3591. }
  3592. if (cur->timing.v_sync_width != tgt->timing.v_sync_width) {
  3593. DSI_DEBUG("timing.v_sync_width differs %d %d\n",
  3594. cur->timing.v_sync_width,
  3595. tgt->timing.v_sync_width);
  3596. return false;
  3597. }
  3598. if (cur->timing.v_front_porch != tgt->timing.v_front_porch) {
  3599. DSI_DEBUG("timing.v_front_porch differs %d %d\n",
  3600. cur->timing.v_front_porch,
  3601. tgt->timing.v_front_porch);
  3602. if (dfps_type != DSI_DFPS_IMMEDIATE_VFP)
  3603. return false;
  3604. }
  3605. /* skip polarity comparison */
  3606. if (cur->timing.refresh_rate == tgt->timing.refresh_rate)
  3607. DSI_DEBUG("timing.refresh_rate identical %d %d\n",
  3608. cur->timing.refresh_rate,
  3609. tgt->timing.refresh_rate);
  3610. if (cur->pixel_clk_khz != tgt->pixel_clk_khz)
  3611. DSI_DEBUG("pixel_clk_khz differs %d %d\n",
  3612. cur->pixel_clk_khz, tgt->pixel_clk_khz);
  3613. if (cur->dsi_mode_flags != tgt->dsi_mode_flags)
  3614. DSI_DEBUG("flags differs %d %d\n",
  3615. cur->dsi_mode_flags, tgt->dsi_mode_flags);
  3616. return true;
  3617. }
  3618. void dsi_display_update_byte_intf_div(struct dsi_display *display)
  3619. {
  3620. struct dsi_host_common_cfg *config;
  3621. struct dsi_display_ctrl *m_ctrl;
  3622. int phy_ver;
  3623. m_ctrl = &display->ctrl[display->cmd_master_idx];
  3624. config = &display->panel->host_config;
  3625. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3626. if (phy_ver <= DSI_PHY_VERSION_2_0)
  3627. config->byte_intf_clk_div = 1;
  3628. else
  3629. config->byte_intf_clk_div = 2;
  3630. }
  3631. static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
  3632. u32 bit_clk_rate)
  3633. {
  3634. int rc = 0;
  3635. int i;
  3636. DSI_DEBUG("%s:bit rate:%d\n", __func__, bit_clk_rate);
  3637. if (!display->panel) {
  3638. DSI_ERR("Invalid params\n");
  3639. return -EINVAL;
  3640. }
  3641. if (bit_clk_rate == 0) {
  3642. DSI_ERR("Invalid bit clock rate\n");
  3643. return -EINVAL;
  3644. }
  3645. display->config.bit_clk_rate_hz = bit_clk_rate;
  3646. display_for_each_ctrl(i, display) {
  3647. struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];
  3648. struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;
  3649. u32 num_of_lanes = 0, bpp, byte_intf_clk_div;
  3650. u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,
  3651. byte_intf_clk_rate;
  3652. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  3653. struct dsi_host_common_cfg *host_cfg;
  3654. mutex_lock(&ctrl->ctrl_lock);
  3655. host_cfg = &display->panel->host_config;
  3656. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  3657. num_of_lanes++;
  3658. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  3659. num_of_lanes++;
  3660. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  3661. num_of_lanes++;
  3662. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  3663. num_of_lanes++;
  3664. if (num_of_lanes == 0) {
  3665. DSI_ERR("Invalid lane count\n");
  3666. rc = -EINVAL;
  3667. goto error;
  3668. }
  3669. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  3670. bit_rate = display->config.bit_clk_rate_hz * num_of_lanes;
  3671. bit_rate_per_lane = bit_rate;
  3672. do_div(bit_rate_per_lane, num_of_lanes);
  3673. pclk_rate = bit_rate;
  3674. do_div(pclk_rate, bpp);
  3675. if (host_cfg->phy_type == DSI_PHY_TYPE_DPHY) {
  3676. bit_rate_per_lane = bit_rate;
  3677. do_div(bit_rate_per_lane, num_of_lanes);
  3678. byte_clk_rate = bit_rate_per_lane;
  3679. do_div(byte_clk_rate, 8);
  3680. byte_intf_clk_rate = byte_clk_rate;
  3681. byte_intf_clk_div = host_cfg->byte_intf_clk_div;
  3682. do_div(byte_intf_clk_rate, byte_intf_clk_div);
  3683. } else {
  3684. bit_rate_per_lane = bit_clk_rate;
  3685. pclk_rate *= bits_per_symbol;
  3686. do_div(pclk_rate, num_of_symbols);
  3687. byte_clk_rate = bit_clk_rate;
  3688. do_div(byte_clk_rate, num_of_symbols);
  3689. /* For CPHY, byte_intf_clk is same as byte_clk */
  3690. byte_intf_clk_rate = byte_clk_rate;
  3691. }
  3692. DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
  3693. bit_rate, bit_rate_per_lane);
  3694. DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",
  3695. byte_clk_rate, byte_intf_clk_rate);
  3696. DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);
  3697. SDE_EVT32(i, bit_rate, byte_clk_rate, pclk_rate);
  3698. ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
  3699. ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
  3700. ctrl->clk_freq.pix_clk_rate = pclk_rate;
  3701. rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
  3702. ctrl->clk_freq, ctrl->cell_index);
  3703. if (rc) {
  3704. DSI_ERR("Failed to update link frequencies\n");
  3705. goto error;
  3706. }
  3707. ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
  3708. error:
  3709. mutex_unlock(&ctrl->ctrl_lock);
  3710. /* TODO: recover ctrl->clk_freq in case of failure */
  3711. if (rc)
  3712. return rc;
  3713. }
  3714. return 0;
  3715. }
  3716. static void _dsi_display_calc_pipe_delay(struct dsi_display *display,
  3717. struct dsi_dyn_clk_delay *delay,
  3718. struct dsi_display_mode *mode)
  3719. {
  3720. u32 esc_clk_rate_hz;
  3721. u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
  3722. u32 hsync_period = 0;
  3723. struct dsi_display_ctrl *m_ctrl;
  3724. struct dsi_ctrl *dsi_ctrl;
  3725. struct dsi_phy_cfg *cfg;
  3726. int phy_ver;
  3727. m_ctrl = &display->ctrl[display->clk_master_idx];
  3728. dsi_ctrl = m_ctrl->ctrl;
  3729. cfg = &(m_ctrl->phy->cfg);
  3730. esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate;
  3731. pclk_to_esc_ratio = (dsi_ctrl->clk_freq.pix_clk_rate /
  3732. esc_clk_rate_hz);
  3733. byte_to_esc_ratio = (dsi_ctrl->clk_freq.byte_clk_rate /
  3734. esc_clk_rate_hz);
  3735. hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4) /
  3736. esc_clk_rate_hz);
  3737. hsync_period = dsi_h_total_dce(&mode->timing);
  3738. delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
  3739. if (!display->panel->video_config.eof_bllp_lp11_en)
  3740. delay->pipe_delay += (17 / pclk_to_esc_ratio) +
  3741. ((21 + (display->config.common_config.t_clk_pre + 1) +
  3742. (display->config.common_config.t_clk_post + 1)) /
  3743. byte_to_esc_ratio) +
  3744. ((((cfg->timing.lane_v3[8] >> 1) + 1) +
  3745. ((cfg->timing.lane_v3[6] >> 1) + 1) +
  3746. ((cfg->timing.lane_v3[3] * 4) +
  3747. (cfg->timing.lane_v3[5] >> 1) + 1) +
  3748. ((cfg->timing.lane_v3[7] >> 1) + 1) +
  3749. ((cfg->timing.lane_v3[1] >> 1) + 1) +
  3750. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3751. hr_bit_to_esc_ratio);
  3752. delay->pipe_delay2 = 0;
  3753. if (display->panel->host_config.force_hs_clk_lane)
  3754. delay->pipe_delay2 = (6 / byte_to_esc_ratio) +
  3755. ((((cfg->timing.lane_v3[1] >> 1) + 1) +
  3756. ((cfg->timing.lane_v3[4] >> 1) + 1)) /
  3757. hr_bit_to_esc_ratio);
  3758. /*
  3759. * 100us pll delay recommended for phy ver 2.0 and 3.0
  3760. * 25us pll delay recommended for phy ver 4.0
  3761. */
  3762. phy_ver = dsi_phy_get_version(m_ctrl->phy);
  3763. if (phy_ver <= DSI_PHY_VERSION_3_0)
  3764. delay->pll_delay = 100;
  3765. else
  3766. delay->pll_delay = 25;
  3767. delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000);
  3768. }
  3769. /*
  3770. * dsi_display_is_type_cphy - check if panel type is cphy
  3771. * @display: Pointer to private display structure
  3772. * Returns: True if panel type is cphy
  3773. */
  3774. static inline bool dsi_display_is_type_cphy(struct dsi_display *display)
  3775. {
  3776. return (display->panel->host_config.phy_type ==
  3777. DSI_PHY_TYPE_CPHY) ? true : false;
  3778. }
  3779. static int _dsi_display_dyn_update_clks(struct dsi_display *display,
  3780. struct link_clk_freq *bkp_freq)
  3781. {
  3782. int rc = 0, i;
  3783. u8 ctrl_version;
  3784. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3785. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3786. struct dsi_clk_link_set *enable_clk;
  3787. m_ctrl = &display->ctrl[display->clk_master_idx];
  3788. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3789. ctrl_version = m_ctrl->ctrl->version;
  3790. enable_clk = &display->clock_info.pll_clks;
  3791. dsi_clk_prepare_enable(enable_clk);
  3792. dsi_display_phy_configure(display, false);
  3793. display_for_each_ctrl(i, display) {
  3794. ctrl = &display->ctrl[i];
  3795. if (!ctrl->ctrl)
  3796. continue;
  3797. rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3798. ctrl->ctrl->clk_freq.byte_clk_rate,
  3799. ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);
  3800. if (rc) {
  3801. DSI_ERR("failed to set byte rate for index:%d\n", i);
  3802. goto recover_byte_clk;
  3803. }
  3804. rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3805. ctrl->ctrl->clk_freq.pix_clk_rate, i);
  3806. if (rc) {
  3807. DSI_ERR("failed to set pix rate for index:%d\n", i);
  3808. goto recover_pix_clk;
  3809. }
  3810. }
  3811. display_for_each_ctrl(i, display) {
  3812. ctrl = &display->ctrl[i];
  3813. if (ctrl == m_ctrl)
  3814. continue;
  3815. dsi_phy_dynamic_refresh_trigger(ctrl->phy, false);
  3816. }
  3817. dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true);
  3818. /*
  3819. * Don't wait for dynamic refresh done for dsi ctrl greater than 2.5
  3820. * and with constant fps, as dynamic refresh will applied with
  3821. * next mdp intf ctrl flush.
  3822. */
  3823. if ((ctrl_version >= DSI_CTRL_VERSION_2_5) &&
  3824. (dyn_clk_caps->maintain_const_fps))
  3825. return 0;
  3826. /* wait for dynamic refresh done */
  3827. display_for_each_ctrl(i, display) {
  3828. ctrl = &display->ctrl[i];
  3829. rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl);
  3830. if (rc) {
  3831. DSI_ERR("wait4dynamic refresh failed for dsi:%d\n", i);
  3832. goto recover_pix_clk;
  3833. } else {
  3834. DSI_INFO("dynamic refresh done on dsi: %s\n",
  3835. i ? "slave" : "master");
  3836. }
  3837. }
  3838. display_for_each_ctrl(i, display) {
  3839. ctrl = &display->ctrl[i];
  3840. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  3841. }
  3842. if (rc)
  3843. DSI_ERR("could not switch back to src clks %d\n", rc);
  3844. dsi_clk_disable_unprepare(enable_clk);
  3845. return rc;
  3846. recover_pix_clk:
  3847. display_for_each_ctrl(i, display) {
  3848. ctrl = &display->ctrl[i];
  3849. if (!ctrl->ctrl)
  3850. continue;
  3851. dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle,
  3852. bkp_freq->pix_clk_rate, i);
  3853. }
  3854. recover_byte_clk:
  3855. display_for_each_ctrl(i, display) {
  3856. ctrl = &display->ctrl[i];
  3857. if (!ctrl->ctrl)
  3858. continue;
  3859. dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,
  3860. bkp_freq->byte_clk_rate,
  3861. bkp_freq->byte_intf_clk_rate, i);
  3862. }
  3863. return rc;
  3864. }
  3865. static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,
  3866. struct dsi_display_mode *mode)
  3867. {
  3868. int rc = 0, mask, i;
  3869. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3870. struct dsi_dyn_clk_delay delay;
  3871. struct link_clk_freq bkp_freq;
  3872. dsi_panel_acquire_panel_lock(display->panel);
  3873. m_ctrl = &display->ctrl[display->clk_master_idx];
  3874. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON);
  3875. /* mask PLL unlock, FIFO overflow and underflow errors */
  3876. mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) |
  3877. BIT(DSI_FIFO_OVERFLOW);
  3878. dsi_display_mask_ctrl_error_interrupts(display, mask, true);
  3879. /* update the phy timings based on new mode */
  3880. display_for_each_ctrl(i, display) {
  3881. ctrl = &display->ctrl[i];
  3882. dsi_phy_update_phy_timings(ctrl->phy, &display->config);
  3883. }
  3884. /* back up existing rates to handle failure case */
  3885. bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;
  3886. bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;
  3887. bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;
  3888. bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
  3889. rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz);
  3890. if (rc) {
  3891. DSI_ERR("failed set link frequencies %d\n", rc);
  3892. goto exit;
  3893. }
  3894. /* calculate pipe delays */
  3895. _dsi_display_calc_pipe_delay(display, &delay, mode);
  3896. /* configure dynamic refresh ctrl registers */
  3897. display_for_each_ctrl(i, display) {
  3898. ctrl = &display->ctrl[i];
  3899. if (!ctrl->phy)
  3900. continue;
  3901. if (ctrl == m_ctrl)
  3902. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true);
  3903. else
  3904. dsi_phy_config_dynamic_refresh(ctrl->phy, &delay,
  3905. false);
  3906. }
  3907. rc = _dsi_display_dyn_update_clks(display, &bkp_freq);
  3908. exit:
  3909. dsi_display_mask_ctrl_error_interrupts(display, mask, false);
  3910. dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS,
  3911. DSI_CLK_OFF);
  3912. /* store newly calculated phy timings in mode private info */
  3913. dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy,
  3914. mode->priv_info->phy_timing_val,
  3915. mode->priv_info->phy_timing_len);
  3916. dsi_panel_release_panel_lock(display->panel);
  3917. return rc;
  3918. }
  3919. static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
  3920. int clk_rate)
  3921. {
  3922. int rc = 0;
  3923. if (clk_rate <= 0) {
  3924. DSI_ERR("%s: bitrate should be greater than 0\n", __func__);
  3925. return -EINVAL;
  3926. }
  3927. if (clk_rate == display->cached_clk_rate) {
  3928. DSI_INFO("%s: ignore duplicated DSI clk setting\n", __func__);
  3929. return rc;
  3930. }
  3931. display->cached_clk_rate = clk_rate;
  3932. rc = dsi_display_update_dsi_bitrate(display, clk_rate);
  3933. if (!rc) {
  3934. DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
  3935. __func__, clk_rate);
  3936. atomic_set(&display->clkrate_change_pending, 1);
  3937. } else {
  3938. DSI_ERR("%s: Failed to prepare to configure '%d'. rc = %d\n",
  3939. __func__, clk_rate, rc);
  3940. /* Caching clock failed, so don't go on doing so. */
  3941. atomic_set(&display->clkrate_change_pending, 0);
  3942. display->cached_clk_rate = 0;
  3943. }
  3944. return rc;
  3945. }
  3946. static int dsi_display_dfps_update(struct dsi_display *display,
  3947. struct dsi_display_mode *dsi_mode)
  3948. {
  3949. struct dsi_mode_info *timing;
  3950. struct dsi_display_ctrl *m_ctrl, *ctrl;
  3951. struct dsi_display_mode *panel_mode;
  3952. struct dsi_dfps_capabilities dfps_caps;
  3953. int rc = 0;
  3954. int i = 0;
  3955. struct dsi_dyn_clk_caps *dyn_clk_caps;
  3956. if (!display || !dsi_mode || !display->panel) {
  3957. DSI_ERR("Invalid params\n");
  3958. return -EINVAL;
  3959. }
  3960. timing = &dsi_mode->timing;
  3961. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  3962. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  3963. if (!dfps_caps.dfps_support && !dyn_clk_caps->maintain_const_fps) {
  3964. DSI_ERR("dfps or constant fps not supported\n");
  3965. return -ENOTSUPP;
  3966. }
  3967. if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) {
  3968. DSI_ERR("dfps clock method not supported\n");
  3969. return -ENOTSUPP;
  3970. }
  3971. /* For split DSI, update the clock master first */
  3972. DSI_DEBUG("configuring seamless dynamic fps\n\n");
  3973. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  3974. m_ctrl = &display->ctrl[display->clk_master_idx];
  3975. rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing);
  3976. if (rc) {
  3977. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3978. display->name, i, rc);
  3979. goto error;
  3980. }
  3981. /* Update the rest of the controllers */
  3982. display_for_each_ctrl(i, display) {
  3983. ctrl = &display->ctrl[i];
  3984. if (!ctrl->ctrl || (ctrl == m_ctrl))
  3985. continue;
  3986. rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing);
  3987. if (rc) {
  3988. DSI_ERR("[%s] failed to dfps update host_%d, rc=%d\n",
  3989. display->name, i, rc);
  3990. goto error;
  3991. }
  3992. }
  3993. panel_mode = display->panel->cur_mode;
  3994. memcpy(panel_mode, dsi_mode, sizeof(*panel_mode));
  3995. /*
  3996. * dsi_mode_flags flags are used to communicate with other drm driver
  3997. * components, and are transient. They aren't inherently part of the
  3998. * display panel's mode and shouldn't be saved into the cached currently
  3999. * active mode.
  4000. */
  4001. panel_mode->dsi_mode_flags = 0;
  4002. error:
  4003. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  4004. return rc;
  4005. }
  4006. static int dsi_display_dfps_calc_front_porch(
  4007. u32 old_fps,
  4008. u32 new_fps,
  4009. u32 a_total,
  4010. u32 b_total,
  4011. u32 b_fp,
  4012. u32 *b_fp_out)
  4013. {
  4014. s32 b_fp_new;
  4015. int add_porches, diff;
  4016. if (!b_fp_out) {
  4017. DSI_ERR("Invalid params\n");
  4018. return -EINVAL;
  4019. }
  4020. if (!a_total || !new_fps) {
  4021. DSI_ERR("Invalid pixel total or new fps in mode request\n");
  4022. return -EINVAL;
  4023. }
  4024. /*
  4025. * Keep clock, other porches constant, use new fps, calc front porch
  4026. * new_vtotal = old_vtotal * (old_fps / new_fps )
  4027. * new_vfp - old_vfp = new_vtotal - old_vtotal
  4028. * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps)
  4029. */
  4030. diff = abs(old_fps - new_fps);
  4031. add_porches = mult_frac(b_total, diff, new_fps);
  4032. if (old_fps > new_fps)
  4033. b_fp_new = b_fp + add_porches;
  4034. else
  4035. b_fp_new = b_fp - add_porches;
  4036. DSI_DEBUG("fps %u a %u b %u b_fp %u new_fp %d\n",
  4037. new_fps, a_total, b_total, b_fp, b_fp_new);
  4038. if (b_fp_new < 0) {
  4039. DSI_ERR("Invalid new_hfp calcluated%d\n", b_fp_new);
  4040. return -EINVAL;
  4041. }
  4042. /**
  4043. * TODO: To differentiate from clock method when communicating to the
  4044. * other components, perhaps we should set clk here to original value
  4045. */
  4046. *b_fp_out = b_fp_new;
  4047. return 0;
  4048. }
  4049. /**
  4050. * dsi_display_get_dfps_timing() - Get the new dfps values.
  4051. * @display: DSI display handle.
  4052. * @adj_mode: Mode value structure to be changed.
  4053. * It contains old timing values and latest fps value.
  4054. * New timing values are updated based on new fps.
  4055. * @curr_refresh_rate: Current fps rate.
  4056. * If zero , current fps rate is taken from
  4057. * display->panel->cur_mode.
  4058. * Return: error code.
  4059. */
  4060. static int dsi_display_get_dfps_timing(struct dsi_display *display,
  4061. struct dsi_display_mode *adj_mode,
  4062. u32 curr_refresh_rate)
  4063. {
  4064. struct dsi_dfps_capabilities dfps_caps;
  4065. struct dsi_display_mode per_ctrl_mode;
  4066. struct dsi_mode_info *timing;
  4067. struct dsi_ctrl *m_ctrl;
  4068. int rc = 0;
  4069. if (!display || !adj_mode) {
  4070. DSI_ERR("Invalid params\n");
  4071. return -EINVAL;
  4072. }
  4073. m_ctrl = display->ctrl[display->clk_master_idx].ctrl;
  4074. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  4075. if (!dfps_caps.dfps_support) {
  4076. DSI_ERR("dfps not supported by panel\n");
  4077. return -EINVAL;
  4078. }
  4079. per_ctrl_mode = *adj_mode;
  4080. adjust_timing_by_ctrl_count(display, &per_ctrl_mode);
  4081. if (!curr_refresh_rate) {
  4082. if (!dsi_display_is_seamless_dfps_possible(display,
  4083. &per_ctrl_mode, dfps_caps.type)) {
  4084. DSI_ERR("seamless dynamic fps not supported for mode\n");
  4085. return -EINVAL;
  4086. }
  4087. if (display->panel->cur_mode) {
  4088. curr_refresh_rate =
  4089. display->panel->cur_mode->timing.refresh_rate;
  4090. } else {
  4091. DSI_ERR("cur_mode is not initialized\n");
  4092. return -EINVAL;
  4093. }
  4094. }
  4095. /* TODO: Remove this direct reference to the dsi_ctrl */
  4096. timing = &per_ctrl_mode.timing;
  4097. switch (dfps_caps.type) {
  4098. case DSI_DFPS_IMMEDIATE_VFP:
  4099. rc = dsi_display_dfps_calc_front_porch(
  4100. curr_refresh_rate,
  4101. timing->refresh_rate,
  4102. dsi_h_total_dce(timing),
  4103. DSI_V_TOTAL(timing),
  4104. timing->v_front_porch,
  4105. &adj_mode->timing.v_front_porch);
  4106. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, DSI_DFPS_IMMEDIATE_VFP,
  4107. curr_refresh_rate, timing->refresh_rate,
  4108. timing->v_front_porch, adj_mode->timing.v_front_porch);
  4109. break;
  4110. case DSI_DFPS_IMMEDIATE_HFP:
  4111. rc = dsi_display_dfps_calc_front_porch(
  4112. curr_refresh_rate,
  4113. timing->refresh_rate,
  4114. DSI_V_TOTAL(timing),
  4115. dsi_h_total_dce(timing),
  4116. timing->h_front_porch,
  4117. &adj_mode->timing.h_front_porch);
  4118. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, DSI_DFPS_IMMEDIATE_HFP,
  4119. curr_refresh_rate, timing->refresh_rate,
  4120. timing->h_front_porch, adj_mode->timing.h_front_porch);
  4121. if (!rc)
  4122. adj_mode->timing.h_front_porch *= display->ctrl_count;
  4123. break;
  4124. default:
  4125. DSI_ERR("Unsupported DFPS mode %d\n", dfps_caps.type);
  4126. rc = -ENOTSUPP;
  4127. }
  4128. return rc;
  4129. }
  4130. static bool dsi_display_validate_mode_seamless(struct dsi_display *display,
  4131. struct dsi_display_mode *adj_mode)
  4132. {
  4133. int rc = 0;
  4134. if (!display || !adj_mode) {
  4135. DSI_ERR("Invalid params\n");
  4136. return false;
  4137. }
  4138. /* Currently the only seamless transition is dynamic fps */
  4139. rc = dsi_display_get_dfps_timing(display, adj_mode, 0);
  4140. if (rc) {
  4141. DSI_DEBUG("Dynamic FPS not supported for seamless\n");
  4142. } else {
  4143. DSI_DEBUG("Mode switch is seamless Dynamic FPS\n");
  4144. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS |
  4145. DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  4146. }
  4147. return rc;
  4148. }
  4149. static void dsi_display_validate_dms_fps(struct dsi_display_mode *cur_mode,
  4150. struct dsi_display_mode *to_mode)
  4151. {
  4152. u32 cur_fps, to_fps;
  4153. u32 cur_h_active, to_h_active;
  4154. u32 cur_v_active, to_v_active;
  4155. cur_fps = cur_mode->timing.refresh_rate;
  4156. to_fps = to_mode->timing.refresh_rate;
  4157. cur_h_active = cur_mode->timing.h_active;
  4158. cur_v_active = cur_mode->timing.v_active;
  4159. to_h_active = to_mode->timing.h_active;
  4160. to_v_active = to_mode->timing.v_active;
  4161. if ((cur_h_active == to_h_active) && (cur_v_active == to_v_active) &&
  4162. (cur_fps != to_fps)) {
  4163. to_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS_FPS;
  4164. DSI_DEBUG("DMS Modeset with FPS change\n");
  4165. } else {
  4166. to_mode->dsi_mode_flags &= ~DSI_MODE_FLAG_DMS_FPS;
  4167. }
  4168. }
  4169. static int dsi_display_set_mode_sub(struct dsi_display *display,
  4170. struct dsi_display_mode *mode,
  4171. u32 flags)
  4172. {
  4173. int rc = 0, clk_rate = 0;
  4174. int i;
  4175. struct dsi_display_ctrl *ctrl;
  4176. struct dsi_display_ctrl *mctrl;
  4177. struct dsi_display_mode_priv_info *priv_info;
  4178. bool commit_phy_timing = false;
  4179. struct dsi_dyn_clk_caps *dyn_clk_caps;
  4180. priv_info = mode->priv_info;
  4181. if (!priv_info) {
  4182. DSI_ERR("[%s] failed to get private info of the display mode\n",
  4183. display->name);
  4184. return -EINVAL;
  4185. }
  4186. SDE_EVT32(mode->dsi_mode_flags, display->panel->panel_mode);
  4187. if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_VID)
  4188. display->panel->panel_mode = DSI_OP_VIDEO_MODE;
  4189. else if (mode->dsi_mode_flags & DSI_MODE_FLAG_POMS_TO_CMD)
  4190. display->panel->panel_mode = DSI_OP_CMD_MODE;
  4191. rc = dsi_panel_get_host_cfg_for_mode(display->panel,
  4192. mode,
  4193. &display->config);
  4194. if (rc) {
  4195. DSI_ERR("[%s] failed to get host config for mode, rc=%d\n",
  4196. display->name, rc);
  4197. goto error;
  4198. }
  4199. memcpy(&display->config.lane_map, &display->lane_map,
  4200. sizeof(display->lane_map));
  4201. mctrl = &display->ctrl[display->clk_master_idx];
  4202. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  4203. if (mode->dsi_mode_flags &
  4204. (DSI_MODE_FLAG_DFPS | DSI_MODE_FLAG_VRR)) {
  4205. display_for_each_ctrl(i, display) {
  4206. ctrl = &display->ctrl[i];
  4207. if (!ctrl->ctrl || (ctrl != mctrl))
  4208. continue;
  4209. ctrl->ctrl->hw.ops.set_timing_db(&ctrl->ctrl->hw,
  4210. true);
  4211. dsi_phy_dynamic_refresh_clear(ctrl->phy);
  4212. if ((ctrl->ctrl->version >= DSI_CTRL_VERSION_2_5) &&
  4213. (dyn_clk_caps->maintain_const_fps)) {
  4214. dsi_phy_dynamic_refresh_trigger_sel(ctrl->phy,
  4215. true);
  4216. }
  4217. }
  4218. rc = dsi_display_dfps_update(display, mode);
  4219. if (rc) {
  4220. DSI_ERR("[%s]DSI dfps update failed, rc=%d\n",
  4221. display->name, rc);
  4222. goto error;
  4223. }
  4224. display_for_each_ctrl(i, display) {
  4225. ctrl = &display->ctrl[i];
  4226. rc = dsi_ctrl_update_host_config(ctrl->ctrl,
  4227. &display->config, mode, mode->dsi_mode_flags,
  4228. display->dsi_clk_handle);
  4229. if (rc) {
  4230. DSI_ERR("failed to update ctrl config\n");
  4231. goto error;
  4232. }
  4233. }
  4234. if (priv_info->phy_timing_len) {
  4235. display_for_each_ctrl(i, display) {
  4236. ctrl = &display->ctrl[i];
  4237. rc = dsi_phy_set_timing_params(ctrl->phy,
  4238. priv_info->phy_timing_val,
  4239. priv_info->phy_timing_len,
  4240. commit_phy_timing);
  4241. if (rc)
  4242. DSI_ERR("Fail to add timing params\n");
  4243. }
  4244. }
  4245. if (!(mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))
  4246. return rc;
  4247. }
  4248. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) {
  4249. if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
  4250. rc = dsi_display_dynamic_clk_switch_vid(display, mode);
  4251. if (rc)
  4252. DSI_ERR("dynamic clk change failed %d\n", rc);
  4253. /*
  4254. * skip rest of the opearations since
  4255. * dsi_display_dynamic_clk_switch_vid() already takes
  4256. * care of them.
  4257. */
  4258. return rc;
  4259. } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) {
  4260. clk_rate = mode->timing.clk_rate_hz;
  4261. rc = dsi_display_dynamic_clk_configure_cmd(display,
  4262. clk_rate);
  4263. if (rc) {
  4264. DSI_ERR("Failed to configure dynamic clk\n");
  4265. return rc;
  4266. }
  4267. }
  4268. }
  4269. display_for_each_ctrl(i, display) {
  4270. ctrl = &display->ctrl[i];
  4271. rc = dsi_ctrl_update_host_config(ctrl->ctrl, &display->config,
  4272. mode, mode->dsi_mode_flags,
  4273. display->dsi_clk_handle);
  4274. if (rc) {
  4275. DSI_ERR("[%s] failed to update ctrl config, rc=%d\n",
  4276. display->name, rc);
  4277. goto error;
  4278. }
  4279. }
  4280. if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
  4281. (display->panel->panel_mode == DSI_OP_CMD_MODE)) {
  4282. u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
  4283. u64 to_bitclk = mode->timing.clk_rate_hz;
  4284. commit_phy_timing = true;
  4285. /* No need to set clkrate pending flag if clocks are same */
  4286. if ((!cur_bitclk && !to_bitclk) || (cur_bitclk != to_bitclk))
  4287. atomic_set(&display->clkrate_change_pending, 1);
  4288. dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
  4289. }
  4290. if (priv_info->phy_timing_len) {
  4291. display_for_each_ctrl(i, display) {
  4292. ctrl = &display->ctrl[i];
  4293. rc = dsi_phy_set_timing_params(ctrl->phy,
  4294. priv_info->phy_timing_val,
  4295. priv_info->phy_timing_len,
  4296. commit_phy_timing);
  4297. if (rc)
  4298. DSI_ERR("failed to add DSI PHY timing params\n");
  4299. }
  4300. }
  4301. error:
  4302. return rc;
  4303. }
  4304. /**
  4305. * _dsi_display_dev_init - initializes the display device
  4306. * Initialization will acquire references to the resources required for the
  4307. * display hardware to function.
  4308. * @display: Handle to the display
  4309. * Returns: Zero on success
  4310. */
  4311. static int _dsi_display_dev_init(struct dsi_display *display)
  4312. {
  4313. int rc = 0;
  4314. if (!display) {
  4315. DSI_ERR("invalid display\n");
  4316. return -EINVAL;
  4317. }
  4318. if (!display->panel_node && !display->fw)
  4319. return 0;
  4320. mutex_lock(&display->display_lock);
  4321. display->parser = dsi_parser_get(&display->pdev->dev);
  4322. if (display->fw && display->parser)
  4323. display->parser_node = dsi_parser_get_head_node(
  4324. display->parser, display->fw->data,
  4325. display->fw->size);
  4326. rc = dsi_display_parse_dt(display);
  4327. if (rc) {
  4328. DSI_ERR("[%s] failed to parse dt, rc=%d\n", display->name, rc);
  4329. goto error;
  4330. }
  4331. rc = dsi_display_res_init(display);
  4332. if (rc) {
  4333. DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
  4334. display->name, rc);
  4335. goto error;
  4336. }
  4337. error:
  4338. mutex_unlock(&display->display_lock);
  4339. return rc;
  4340. }
  4341. /**
  4342. * _dsi_display_dev_deinit - deinitializes the display device
  4343. * All the resources acquired during device init will be released.
  4344. * @display: Handle to the display
  4345. * Returns: Zero on success
  4346. */
  4347. static int _dsi_display_dev_deinit(struct dsi_display *display)
  4348. {
  4349. int rc = 0;
  4350. if (!display) {
  4351. DSI_ERR("invalid display\n");
  4352. return -EINVAL;
  4353. }
  4354. mutex_lock(&display->display_lock);
  4355. rc = dsi_display_res_deinit(display);
  4356. if (rc)
  4357. DSI_ERR("[%s] failed to deinitialize resource, rc=%d\n",
  4358. display->name, rc);
  4359. mutex_unlock(&display->display_lock);
  4360. return rc;
  4361. }
  4362. /**
  4363. * dsi_display_cont_splash_res_disable() - Disable resource votes added in probe
  4364. * @dsi_display: Pointer to dsi display
  4365. * Returns: Zero on success
  4366. */
  4367. int dsi_display_cont_splash_res_disable(void *dsi_display)
  4368. {
  4369. struct dsi_display *display = dsi_display;
  4370. int rc = 0;
  4371. /* Remove the panel vote that was added during dsi display probe */
  4372. rc = dsi_pwr_enable_regulator(&display->panel->power_info, false);
  4373. if (rc)
  4374. DSI_ERR("[%s] failed to disable vregs, rc=%d\n",
  4375. display->panel->name, rc);
  4376. return rc;
  4377. }
  4378. /**
  4379. * dsi_display_cont_splash_config() - Initialize resources for continuous splash
  4380. * @dsi_display: Pointer to dsi display
  4381. * Returns: Zero on success
  4382. */
  4383. int dsi_display_cont_splash_config(void *dsi_display)
  4384. {
  4385. struct dsi_display *display = dsi_display;
  4386. int rc = 0;
  4387. /* Vote for gdsc required to read register address space */
  4388. if (!display) {
  4389. DSI_ERR("invalid input display param\n");
  4390. return -EINVAL;
  4391. }
  4392. rc = pm_runtime_get_sync(display->drm_dev->dev);
  4393. if (rc < 0) {
  4394. DSI_ERR("failed to vote gdsc for continuous splash, rc=%d\n",
  4395. rc);
  4396. return rc;
  4397. }
  4398. mutex_lock(&display->display_lock);
  4399. display->is_cont_splash_enabled = true;
  4400. /* Update splash status for clock manager */
  4401. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4402. display->is_cont_splash_enabled);
  4403. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY, display->is_cont_splash_enabled);
  4404. /* Set up ctrl isr before enabling core clk */
  4405. dsi_display_ctrl_isr_configure(display, true);
  4406. /* Vote for Core clk and link clk. Votes on ctrl and phy
  4407. * regulator are inplicit from pre clk on callback
  4408. */
  4409. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4410. DSI_ALL_CLKS, DSI_CLK_ON);
  4411. if (rc) {
  4412. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  4413. display->name, rc);
  4414. goto clk_manager_update;
  4415. }
  4416. mutex_unlock(&display->display_lock);
  4417. /* Set the current brightness level */
  4418. dsi_panel_bl_handoff(display->panel);
  4419. return rc;
  4420. clk_manager_update:
  4421. dsi_display_ctrl_isr_configure(display, false);
  4422. /* Update splash status for clock manager */
  4423. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4424. false);
  4425. pm_runtime_put_sync(display->drm_dev->dev);
  4426. display->is_cont_splash_enabled = false;
  4427. mutex_unlock(&display->display_lock);
  4428. return rc;
  4429. }
  4430. /**
  4431. * dsi_display_splash_res_cleanup() - cleanup for continuous splash
  4432. * @display: Pointer to dsi display
  4433. * Returns: Zero on success
  4434. */
  4435. int dsi_display_splash_res_cleanup(struct dsi_display *display)
  4436. {
  4437. int rc = 0;
  4438. if (!display->is_cont_splash_enabled)
  4439. return 0;
  4440. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  4441. DSI_ALL_CLKS, DSI_CLK_OFF);
  4442. if (rc)
  4443. DSI_ERR("[%s] failed to disable DSI link clocks, rc=%d\n",
  4444. display->name, rc);
  4445. pm_runtime_put_sync(display->drm_dev->dev);
  4446. display->is_cont_splash_enabled = false;
  4447. /* Update splash status for clock manager */
  4448. dsi_display_clk_mngr_update_splash_status(display->clk_mngr,
  4449. display->is_cont_splash_enabled);
  4450. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT, display->is_cont_splash_enabled);
  4451. return rc;
  4452. }
  4453. static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
  4454. {
  4455. int rc = 0;
  4456. rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
  4457. if (!rc) {
  4458. DSI_DEBUG("dsi bit clk has been configured to %d\n",
  4459. display->cached_clk_rate);
  4460. atomic_set(&display->clkrate_change_pending, 0);
  4461. } else {
  4462. DSI_ERR("Failed to configure dsi bit clock '%d'. rc = %d\n",
  4463. display->cached_clk_rate, rc);
  4464. }
  4465. return rc;
  4466. }
  4467. static int dsi_display_validate_split_link(struct dsi_display *display)
  4468. {
  4469. int i, rc = 0;
  4470. struct dsi_display_ctrl *ctrl;
  4471. struct dsi_host_common_cfg *host = &display->panel->host_config;
  4472. if (!host->split_link.enabled)
  4473. return 0;
  4474. display_for_each_ctrl(i, display) {
  4475. ctrl = &display->ctrl[i];
  4476. if (!ctrl->ctrl->split_link_supported) {
  4477. DSI_ERR("[%s] split link is not supported by hw\n",
  4478. display->name);
  4479. rc = -ENOTSUPP;
  4480. goto error;
  4481. }
  4482. set_bit(DSI_PHY_SPLIT_LINK, ctrl->phy->hw.feature_map);
  4483. host->split_link.panel_mode = display->panel->panel_mode;
  4484. }
  4485. DSI_DEBUG("Split link is enabled\n");
  4486. return 0;
  4487. error:
  4488. host->split_link.enabled = false;
  4489. return rc;
  4490. }
  4491. static int dsi_display_get_io_resources(struct msm_io_res *io_res, void *data)
  4492. {
  4493. int rc = 0;
  4494. struct dsi_display *display;
  4495. if (!data)
  4496. return -EINVAL;
  4497. rc = dsi_ctrl_get_io_resources(io_res);
  4498. if (rc)
  4499. goto end;
  4500. rc = dsi_phy_get_io_resources(io_res);
  4501. if (rc)
  4502. goto end;
  4503. display = (struct dsi_display *)data;
  4504. rc = dsi_panel_get_io_resources(display->panel, io_res);
  4505. end:
  4506. return rc;
  4507. }
  4508. static int dsi_display_pre_release(void *data)
  4509. {
  4510. struct dsi_display *display;
  4511. if (!data)
  4512. return -EINVAL;
  4513. display = (struct dsi_display *)data;
  4514. mutex_lock(&display->display_lock);
  4515. display->hw_ownership = false;
  4516. mutex_unlock(&display->display_lock);
  4517. dsi_display_ctrl_irq_update(display, false);
  4518. return 0;
  4519. }
  4520. static int dsi_display_pre_acquire(void *data)
  4521. {
  4522. struct dsi_display *display;
  4523. if (!data)
  4524. return -EINVAL;
  4525. display = (struct dsi_display *)data;
  4526. mutex_lock(&display->display_lock);
  4527. display->hw_ownership = true;
  4528. mutex_unlock(&display->display_lock);
  4529. dsi_display_ctrl_irq_update((struct dsi_display *)data, true);
  4530. return 0;
  4531. }
  4532. /**
  4533. * dsi_display_bind - bind dsi device with controlling device
  4534. * @dev: Pointer to base of platform device
  4535. * @master: Pointer to container of drm device
  4536. * @data: Pointer to private data
  4537. * Returns: Zero on success
  4538. */
  4539. static int dsi_display_bind(struct device *dev,
  4540. struct device *master,
  4541. void *data)
  4542. {
  4543. struct dsi_display_ctrl *display_ctrl;
  4544. struct drm_device *drm;
  4545. struct dsi_display *display;
  4546. struct dsi_clk_info info;
  4547. struct clk_ctrl_cb clk_cb;
  4548. void *handle = NULL;
  4549. struct platform_device *pdev = to_platform_device(dev);
  4550. char *client1 = "dsi_clk_client";
  4551. char *client2 = "mdp_event_client";
  4552. struct msm_vm_ops vm_event_ops = {
  4553. .vm_get_io_resources = dsi_display_get_io_resources,
  4554. .vm_pre_hw_release = dsi_display_pre_release,
  4555. .vm_post_hw_acquire = dsi_display_pre_acquire,
  4556. };
  4557. int i, rc = 0;
  4558. if (!dev || !pdev || !master) {
  4559. DSI_ERR("invalid param(s), dev %pK, pdev %pK, master %pK\n",
  4560. dev, pdev, master);
  4561. return -EINVAL;
  4562. }
  4563. drm = dev_get_drvdata(master);
  4564. display = platform_get_drvdata(pdev);
  4565. if (!drm || !display) {
  4566. DSI_ERR("invalid param(s), drm %pK, display %pK\n",
  4567. drm, display);
  4568. return -EINVAL;
  4569. }
  4570. if (!display->panel_node && !display->fw)
  4571. return 0;
  4572. if (!display->fw)
  4573. display->name = display->panel_node->name;
  4574. /* defer bind if ext bridge driver is not loaded */
  4575. if (display->panel && display->panel->host_config.ext_bridge_mode) {
  4576. for (i = 0; i < display->ext_bridge_cnt; i++) {
  4577. if (!of_drm_find_bridge(
  4578. display->ext_bridge[i].node_of)) {
  4579. DSI_DEBUG("defer for bridge[%d] %s\n", i,
  4580. display->ext_bridge[i].node_of->full_name);
  4581. return -EPROBE_DEFER;
  4582. }
  4583. }
  4584. }
  4585. mutex_lock(&display->display_lock);
  4586. rc = dsi_display_validate_split_link(display);
  4587. if (rc) {
  4588. DSI_ERR("[%s] split link validation failed, rc=%d\n",
  4589. display->name, rc);
  4590. goto error;
  4591. }
  4592. rc = dsi_display_debugfs_init(display);
  4593. if (rc) {
  4594. DSI_ERR("[%s] debugfs init failed, rc=%d\n", display->name, rc);
  4595. goto error;
  4596. }
  4597. atomic_set(&display->clkrate_change_pending, 0);
  4598. display->cached_clk_rate = 0;
  4599. memset(&info, 0x0, sizeof(info));
  4600. display_for_each_ctrl(i, display) {
  4601. display_ctrl = &display->ctrl[i];
  4602. rc = dsi_ctrl_drv_init(display_ctrl->ctrl, display->root);
  4603. if (rc) {
  4604. DSI_ERR("[%s] failed to initialize ctrl[%d], rc=%d\n",
  4605. display->name, i, rc);
  4606. goto error_ctrl_deinit;
  4607. }
  4608. display_ctrl->ctrl->horiz_index = i;
  4609. rc = dsi_phy_drv_init(display_ctrl->phy);
  4610. if (rc) {
  4611. DSI_ERR("[%s] Failed to initialize phy[%d], rc=%d\n",
  4612. display->name, i, rc);
  4613. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4614. goto error_ctrl_deinit;
  4615. }
  4616. display_ctrl->ctrl->post_cmd_tx_workq = display->post_cmd_tx_workq;
  4617. memcpy(&info.c_clks[i],
  4618. (&display_ctrl->ctrl->clk_info.core_clks),
  4619. sizeof(struct dsi_core_clk_info));
  4620. memcpy(&info.l_hs_clks[i],
  4621. (&display_ctrl->ctrl->clk_info.hs_link_clks),
  4622. sizeof(struct dsi_link_hs_clk_info));
  4623. memcpy(&info.l_lp_clks[i],
  4624. (&display_ctrl->ctrl->clk_info.lp_link_clks),
  4625. sizeof(struct dsi_link_lp_clk_info));
  4626. info.c_clks[i].drm = drm;
  4627. info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
  4628. }
  4629. info.pre_clkoff_cb = dsi_pre_clkoff_cb;
  4630. info.pre_clkon_cb = dsi_pre_clkon_cb;
  4631. info.post_clkoff_cb = dsi_post_clkoff_cb;
  4632. info.post_clkon_cb = dsi_post_clkon_cb;
  4633. info.phy_config_cb = dsi_display_phy_configure;
  4634. info.phy_pll_toggle_cb = dsi_display_phy_pll_toggle;
  4635. info.priv_data = display;
  4636. info.master_ndx = display->clk_master_idx;
  4637. info.dsi_ctrl_count = display->ctrl_count;
  4638. snprintf(info.name, MAX_STRING_LEN,
  4639. "DSI_MNGR-%s", display->name);
  4640. display->clk_mngr = dsi_display_clk_mngr_register(&info);
  4641. if (IS_ERR_OR_NULL(display->clk_mngr)) {
  4642. rc = PTR_ERR(display->clk_mngr);
  4643. display->clk_mngr = NULL;
  4644. DSI_ERR("dsi clock registration failed, rc = %d\n", rc);
  4645. goto error_ctrl_deinit;
  4646. }
  4647. handle = dsi_register_clk_handle(display->clk_mngr, client1);
  4648. if (IS_ERR_OR_NULL(handle)) {
  4649. rc = PTR_ERR(handle);
  4650. DSI_ERR("failed to register %s client, rc = %d\n",
  4651. client1, rc);
  4652. goto error_clk_deinit;
  4653. } else {
  4654. display->dsi_clk_handle = handle;
  4655. }
  4656. handle = dsi_register_clk_handle(display->clk_mngr, client2);
  4657. if (IS_ERR_OR_NULL(handle)) {
  4658. rc = PTR_ERR(handle);
  4659. DSI_ERR("failed to register %s client, rc = %d\n",
  4660. client2, rc);
  4661. goto error_clk_client_deinit;
  4662. } else {
  4663. display->mdp_clk_handle = handle;
  4664. }
  4665. clk_cb.priv = display;
  4666. clk_cb.dsi_clk_cb = dsi_display_clk_ctrl_cb;
  4667. display_for_each_ctrl(i, display) {
  4668. display_ctrl = &display->ctrl[i];
  4669. rc = dsi_ctrl_clk_cb_register(display_ctrl->ctrl, &clk_cb);
  4670. if (rc) {
  4671. DSI_ERR("[%s] failed to register ctrl clk_cb[%d], rc=%d\n",
  4672. display->name, i, rc);
  4673. goto error_ctrl_deinit;
  4674. }
  4675. rc = dsi_phy_clk_cb_register(display_ctrl->phy, &clk_cb);
  4676. if (rc) {
  4677. DSI_ERR("[%s] failed to register phy clk_cb[%d], rc=%d\n",
  4678. display->name, i, rc);
  4679. goto error_ctrl_deinit;
  4680. }
  4681. }
  4682. dsi_display_update_byte_intf_div(display);
  4683. rc = dsi_display_mipi_host_init(display);
  4684. if (rc) {
  4685. DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",
  4686. display->name, rc);
  4687. goto error_ctrl_deinit;
  4688. }
  4689. rc = dsi_panel_drv_init(display->panel, &display->host);
  4690. if (rc) {
  4691. if (rc != -EPROBE_DEFER)
  4692. DSI_ERR("[%s] failed to initialize panel driver, rc=%d\n",
  4693. display->name, rc);
  4694. goto error_host_deinit;
  4695. }
  4696. DSI_INFO("Successfully bind display panel '%s %s'\n", display->name,
  4697. display->panel->te_using_watchdog_timer ? "as sim panel" : "");
  4698. display->drm_dev = drm;
  4699. display_for_each_ctrl(i, display) {
  4700. display_ctrl = &display->ctrl[i];
  4701. if (!display_ctrl->phy || !display_ctrl->ctrl)
  4702. continue;
  4703. display_ctrl->ctrl->drm_dev = drm;
  4704. rc = dsi_phy_set_clk_freq(display_ctrl->phy,
  4705. &display_ctrl->ctrl->clk_freq);
  4706. if (rc) {
  4707. DSI_ERR("[%s] failed to set phy clk freq, rc=%d\n",
  4708. display->name, rc);
  4709. goto error;
  4710. }
  4711. }
  4712. msm_register_vm_event(master, dev, &vm_event_ops, (void *)display);
  4713. goto error;
  4714. error_host_deinit:
  4715. (void)dsi_display_mipi_host_deinit(display);
  4716. error_clk_client_deinit:
  4717. (void)dsi_deregister_clk_handle(display->dsi_clk_handle);
  4718. error_clk_deinit:
  4719. (void)dsi_display_clk_mngr_deregister(display->clk_mngr);
  4720. error_ctrl_deinit:
  4721. for (i = i - 1; i >= 0; i--) {
  4722. display_ctrl = &display->ctrl[i];
  4723. (void)dsi_phy_drv_deinit(display_ctrl->phy);
  4724. (void)dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4725. dsi_ctrl_put(display_ctrl->ctrl);
  4726. dsi_phy_put(display_ctrl->phy);
  4727. }
  4728. (void)dsi_display_debugfs_deinit(display);
  4729. error:
  4730. mutex_unlock(&display->display_lock);
  4731. return rc;
  4732. }
  4733. /**
  4734. * dsi_display_unbind - unbind dsi from controlling device
  4735. * @dev: Pointer to base of platform device
  4736. * @master: Pointer to container of drm device
  4737. * @data: Pointer to private data
  4738. */
  4739. static void dsi_display_unbind(struct device *dev,
  4740. struct device *master, void *data)
  4741. {
  4742. struct dsi_display_ctrl *display_ctrl;
  4743. struct dsi_display *display;
  4744. struct platform_device *pdev = to_platform_device(dev);
  4745. int i, rc = 0;
  4746. if (!dev || !pdev || !master) {
  4747. DSI_ERR("invalid param(s)\n");
  4748. return;
  4749. }
  4750. display = platform_get_drvdata(pdev);
  4751. if (!display || !display->panel_node) {
  4752. DSI_ERR("invalid display\n");
  4753. return;
  4754. }
  4755. mutex_lock(&display->display_lock);
  4756. rc = dsi_display_mipi_host_deinit(display);
  4757. if (rc)
  4758. DSI_ERR("[%s] failed to deinit mipi hosts, rc=%d\n",
  4759. display->name,
  4760. rc);
  4761. display_for_each_ctrl(i, display) {
  4762. display_ctrl = &display->ctrl[i];
  4763. rc = dsi_phy_drv_deinit(display_ctrl->phy);
  4764. if (rc)
  4765. DSI_ERR("[%s] failed to deinit phy%d driver, rc=%d\n",
  4766. display->name, i, rc);
  4767. display->ctrl->ctrl->post_cmd_tx_workq = NULL;
  4768. rc = dsi_ctrl_drv_deinit(display_ctrl->ctrl);
  4769. if (rc)
  4770. DSI_ERR("[%s] failed to deinit ctrl%d driver, rc=%d\n",
  4771. display->name, i, rc);
  4772. }
  4773. atomic_set(&display->clkrate_change_pending, 0);
  4774. (void)dsi_display_debugfs_deinit(display);
  4775. mutex_unlock(&display->display_lock);
  4776. }
  4777. static const struct component_ops dsi_display_comp_ops = {
  4778. .bind = dsi_display_bind,
  4779. .unbind = dsi_display_unbind,
  4780. };
  4781. static struct platform_driver dsi_display_driver = {
  4782. .probe = dsi_display_dev_probe,
  4783. .remove = dsi_display_dev_remove,
  4784. .driver = {
  4785. .name = "msm-dsi-display",
  4786. .of_match_table = dsi_display_dt_match,
  4787. .suppress_bind_attrs = true,
  4788. },
  4789. };
  4790. static int dsi_display_init(struct dsi_display *display)
  4791. {
  4792. int rc = 0;
  4793. struct platform_device *pdev = display->pdev;
  4794. mutex_init(&display->display_lock);
  4795. rc = _dsi_display_dev_init(display);
  4796. if (rc) {
  4797. DSI_ERR("device init failed, rc=%d\n", rc);
  4798. goto end;
  4799. }
  4800. /*
  4801. * Vote on panel regulator is added to make sure panel regulators
  4802. * are ON for cont-splash enabled usecase.
  4803. * This panel regulator vote will be removed only in:
  4804. * 1) device suspend when cont-splash is enabled.
  4805. * 2) cont_splash_res_disable() when cont-splash is disabled.
  4806. * For GKI, adding this vote will make sure that sync_state
  4807. * kernel driver doesn't disable the panel regulators after
  4808. * dsi probe is complete.
  4809. */
  4810. if (display->panel) {
  4811. rc = dsi_pwr_enable_regulator(&display->panel->power_info,
  4812. true);
  4813. if (rc) {
  4814. DSI_ERR("[%s] failed to enable vregs, rc=%d\n",
  4815. display->panel->name, rc);
  4816. return rc;
  4817. }
  4818. }
  4819. rc = component_add(&pdev->dev, &dsi_display_comp_ops);
  4820. if (rc)
  4821. DSI_ERR("component add failed, rc=%d\n", rc);
  4822. DSI_DEBUG("component add success: %s\n", display->name);
  4823. end:
  4824. return rc;
  4825. }
  4826. static void dsi_display_firmware_display(const struct firmware *fw,
  4827. void *context)
  4828. {
  4829. struct dsi_display *display = context;
  4830. if (fw) {
  4831. DSI_INFO("reading data from firmware, size=%zd\n",
  4832. fw->size);
  4833. display->fw = fw;
  4834. if (!strcmp(display->display_type, "primary"))
  4835. display->name = "dsi_firmware_display";
  4836. else if (!strcmp(display->display_type, "secondary"))
  4837. display->name = "dsi_firmware_display_secondary";
  4838. } else {
  4839. DSI_INFO("no firmware available, fallback to device node\n");
  4840. }
  4841. if (dsi_display_init(display))
  4842. return;
  4843. DSI_DEBUG("success\n");
  4844. }
  4845. int dsi_display_dev_probe(struct platform_device *pdev)
  4846. {
  4847. struct dsi_display *display = NULL;
  4848. struct device_node *node = NULL, *panel_node = NULL, *mdp_node = NULL;
  4849. int rc = 0, index = DSI_PRIMARY;
  4850. bool firm_req = false;
  4851. struct dsi_display_boot_param *boot_disp;
  4852. if (!pdev || !pdev->dev.of_node) {
  4853. DSI_ERR("pdev not found\n");
  4854. rc = -ENODEV;
  4855. goto end;
  4856. }
  4857. display = devm_kzalloc(&pdev->dev, sizeof(*display), GFP_KERNEL);
  4858. if (!display) {
  4859. rc = -ENOMEM;
  4860. goto end;
  4861. }
  4862. display->post_cmd_tx_workq = create_singlethread_workqueue(
  4863. "dsi_post_cmd_tx_workq");
  4864. if (!display->post_cmd_tx_workq) {
  4865. DSI_ERR("failed to create work queue\n");
  4866. rc = -EINVAL;
  4867. goto end;
  4868. }
  4869. mdp_node = of_parse_phandle(pdev->dev.of_node, "qcom,mdp", 0);
  4870. if (!mdp_node) {
  4871. DSI_ERR("mdp_node not found\n");
  4872. rc = -ENODEV;
  4873. goto end;
  4874. }
  4875. display->trusted_vm_env = of_property_read_bool(mdp_node,
  4876. "qcom,sde-trusted-vm-env");
  4877. if (display->trusted_vm_env)
  4878. DSI_INFO("Display enabled with trusted vm path\n");
  4879. /* initialize panel id to UINT64_MAX */
  4880. display->panel_id = ~0x0;
  4881. display->display_type = of_get_property(pdev->dev.of_node,
  4882. "label", NULL);
  4883. if (!display->display_type)
  4884. display->display_type = "primary";
  4885. if (!strcmp(display->display_type, "secondary"))
  4886. index = DSI_SECONDARY;
  4887. boot_disp = &boot_displays[index];
  4888. node = pdev->dev.of_node;
  4889. if (boot_disp->boot_disp_en) {
  4890. /* The panel name should be same as UEFI name index */
  4891. panel_node = of_find_node_by_name(mdp_node, boot_disp->name);
  4892. if (!panel_node)
  4893. DSI_WARN("%s panel_node %s not found\n", display->display_type,
  4894. boot_disp->name);
  4895. } else {
  4896. panel_node = of_parse_phandle(node,
  4897. "qcom,dsi-default-panel", 0);
  4898. if (!panel_node)
  4899. DSI_WARN("%s default panel not found\n", display->display_type);
  4900. }
  4901. boot_disp->node = pdev->dev.of_node;
  4902. boot_disp->disp = display;
  4903. display->panel_node = panel_node;
  4904. display->pdev = pdev;
  4905. display->boot_disp = boot_disp;
  4906. dsi_display_parse_cmdline_topology(display, index);
  4907. platform_set_drvdata(pdev, display);
  4908. if (!dsi_display_validate_res(display)) {
  4909. rc = -EPROBE_DEFER;
  4910. DSI_ERR("resources required for display probe not present: rc=%d\n", rc);
  4911. goto end;
  4912. }
  4913. /* initialize display in firmware callback */
  4914. if (!(boot_displays[DSI_PRIMARY].boot_disp_en ||
  4915. boot_displays[DSI_SECONDARY].boot_disp_en) &&
  4916. IS_ENABLED(CONFIG_DSI_PARSER)) {
  4917. if (!strcmp(display->display_type, "primary"))
  4918. firm_req = !request_firmware_nowait(
  4919. THIS_MODULE, 1, "dsi_prop",
  4920. &pdev->dev, GFP_KERNEL, display,
  4921. dsi_display_firmware_display);
  4922. else if (!strcmp(display->display_type, "secondary"))
  4923. firm_req = !request_firmware_nowait(
  4924. THIS_MODULE, 1, "dsi_prop_sec",
  4925. &pdev->dev, GFP_KERNEL, display,
  4926. dsi_display_firmware_display);
  4927. }
  4928. if (!firm_req) {
  4929. rc = dsi_display_init(display);
  4930. if (rc)
  4931. goto end;
  4932. }
  4933. return 0;
  4934. end:
  4935. if (display)
  4936. devm_kfree(&pdev->dev, display);
  4937. return rc;
  4938. }
  4939. int dsi_display_dev_remove(struct platform_device *pdev)
  4940. {
  4941. int rc = 0, i = 0;
  4942. struct dsi_display *display;
  4943. struct dsi_display_ctrl *ctrl;
  4944. if (!pdev) {
  4945. DSI_ERR("Invalid device\n");
  4946. return -EINVAL;
  4947. }
  4948. display = platform_get_drvdata(pdev);
  4949. /* decrement ref count */
  4950. of_node_put(display->panel_node);
  4951. if (display->post_cmd_tx_workq) {
  4952. flush_workqueue(display->post_cmd_tx_workq);
  4953. destroy_workqueue(display->post_cmd_tx_workq);
  4954. display->post_cmd_tx_workq = NULL;
  4955. display_for_each_ctrl(i, display) {
  4956. ctrl = &display->ctrl[i];
  4957. if (!ctrl->ctrl)
  4958. continue;
  4959. ctrl->ctrl->post_cmd_tx_workq = NULL;
  4960. }
  4961. }
  4962. (void)_dsi_display_dev_deinit(display);
  4963. platform_set_drvdata(pdev, NULL);
  4964. devm_kfree(&pdev->dev, display);
  4965. return rc;
  4966. }
  4967. int dsi_display_get_num_of_displays(void)
  4968. {
  4969. int i, count = 0;
  4970. for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
  4971. struct dsi_display *display = boot_displays[i].disp;
  4972. if ((display && display->panel_node) ||
  4973. (display && display->fw))
  4974. count++;
  4975. }
  4976. return count;
  4977. }
  4978. int dsi_display_get_active_displays(void **display_array, u32 max_display_count)
  4979. {
  4980. int index = 0, count = 0;
  4981. if (!display_array || !max_display_count) {
  4982. DSI_ERR("invalid params\n");
  4983. return 0;
  4984. }
  4985. for (index = 0; index < MAX_DSI_ACTIVE_DISPLAY; index++) {
  4986. struct dsi_display *display = boot_displays[index].disp;
  4987. if ((display && display->panel_node) ||
  4988. (display && display->fw))
  4989. display_array[count++] = display;
  4990. }
  4991. return count;
  4992. }
  4993. void dsi_display_set_active_state(struct dsi_display *display, bool is_active)
  4994. {
  4995. if (!display)
  4996. return;
  4997. mutex_lock(&display->display_lock);
  4998. display->is_active = is_active;
  4999. mutex_unlock(&display->display_lock);
  5000. }
  5001. int dsi_display_drm_bridge_init(struct dsi_display *display,
  5002. struct drm_encoder *enc)
  5003. {
  5004. int rc = 0;
  5005. struct dsi_bridge *bridge;
  5006. struct msm_drm_private *priv = NULL;
  5007. if (!display || !display->drm_dev || !enc) {
  5008. DSI_ERR("invalid param(s)\n");
  5009. return -EINVAL;
  5010. }
  5011. mutex_lock(&display->display_lock);
  5012. priv = display->drm_dev->dev_private;
  5013. if (!priv) {
  5014. DSI_ERR("Private data is not present\n");
  5015. rc = -EINVAL;
  5016. goto error;
  5017. }
  5018. if (display->bridge) {
  5019. DSI_ERR("display is already initialize\n");
  5020. goto error;
  5021. }
  5022. bridge = dsi_drm_bridge_init(display, display->drm_dev, enc);
  5023. if (IS_ERR_OR_NULL(bridge)) {
  5024. rc = PTR_ERR(bridge);
  5025. DSI_ERR("[%s] brige init failed, %d\n", display->name, rc);
  5026. goto error;
  5027. }
  5028. display->bridge = bridge;
  5029. priv->bridges[priv->num_bridges++] = &bridge->base;
  5030. if (display->tx_cmd_buf == NULL) {
  5031. rc = dsi_host_alloc_cmd_tx_buffer(display);
  5032. if (rc)
  5033. DSI_ERR("failed to allocate cmd tx buffer memory\n");
  5034. }
  5035. error:
  5036. mutex_unlock(&display->display_lock);
  5037. return rc;
  5038. }
  5039. int dsi_display_drm_bridge_deinit(struct dsi_display *display)
  5040. {
  5041. int rc = 0;
  5042. if (!display) {
  5043. DSI_ERR("Invalid params\n");
  5044. return -EINVAL;
  5045. }
  5046. mutex_lock(&display->display_lock);
  5047. dsi_drm_bridge_cleanup(display->bridge);
  5048. display->bridge = NULL;
  5049. mutex_unlock(&display->display_lock);
  5050. return rc;
  5051. }
  5052. /* Hook functions to call external connector, pointer validation is
  5053. * done in dsi_display_drm_ext_bridge_init.
  5054. */
  5055. static enum drm_connector_status dsi_display_drm_ext_detect(
  5056. struct drm_connector *connector,
  5057. bool force,
  5058. void *disp)
  5059. {
  5060. struct dsi_display *display = disp;
  5061. return display->ext_conn->funcs->detect(display->ext_conn, force);
  5062. }
  5063. static int dsi_display_drm_ext_get_modes(
  5064. struct drm_connector *connector, void *disp,
  5065. const struct msm_resource_caps_info *avail_res)
  5066. {
  5067. struct dsi_display *display = disp;
  5068. struct drm_display_mode *pmode, *pt;
  5069. int count;
  5070. /* if there are modes defined in panel, ignore external modes */
  5071. if (display->panel->num_timing_nodes)
  5072. return dsi_connector_get_modes(connector, disp, avail_res);
  5073. count = display->ext_conn->helper_private->get_modes(
  5074. display->ext_conn);
  5075. list_for_each_entry_safe(pmode, pt,
  5076. &display->ext_conn->probed_modes, head) {
  5077. list_move_tail(&pmode->head, &connector->probed_modes);
  5078. }
  5079. connector->display_info = display->ext_conn->display_info;
  5080. return count;
  5081. }
  5082. static enum drm_mode_status dsi_display_drm_ext_mode_valid(
  5083. struct drm_connector *connector,
  5084. struct drm_display_mode *mode,
  5085. void *disp, const struct msm_resource_caps_info *avail_res)
  5086. {
  5087. struct dsi_display *display = disp;
  5088. enum drm_mode_status status;
  5089. /* always do internal mode_valid check */
  5090. status = dsi_conn_mode_valid(connector, mode, disp, avail_res);
  5091. if (status != MODE_OK)
  5092. return status;
  5093. return display->ext_conn->helper_private->mode_valid(
  5094. display->ext_conn, mode);
  5095. }
  5096. static int dsi_display_drm_ext_atomic_check(struct drm_connector *connector,
  5097. void *disp,
  5098. struct drm_atomic_state *state)
  5099. {
  5100. struct dsi_display *display = disp;
  5101. struct drm_connector_state *c_state;
  5102. c_state = drm_atomic_get_new_connector_state(state, connector);
  5103. return display->ext_conn->helper_private->atomic_check(
  5104. display->ext_conn, state);
  5105. }
  5106. static int dsi_display_ext_get_info(struct drm_connector *connector,
  5107. struct msm_display_info *info, void *disp)
  5108. {
  5109. struct dsi_display *display;
  5110. int i;
  5111. if (!info || !disp) {
  5112. DSI_ERR("invalid params\n");
  5113. return -EINVAL;
  5114. }
  5115. display = disp;
  5116. if (!display->panel) {
  5117. DSI_ERR("invalid display panel\n");
  5118. return -EINVAL;
  5119. }
  5120. mutex_lock(&display->display_lock);
  5121. memset(info, 0, sizeof(struct msm_display_info));
  5122. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5123. info->num_of_h_tiles = display->ctrl_count;
  5124. for (i = 0; i < info->num_of_h_tiles; i++)
  5125. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5126. info->is_connected = connector->status != connector_status_disconnected;
  5127. if (!strcmp(display->display_type, "primary"))
  5128. info->display_type = SDE_CONNECTOR_PRIMARY;
  5129. else if (!strcmp(display->display_type, "secondary"))
  5130. info->display_type = SDE_CONNECTOR_SECONDARY;
  5131. info->capabilities |= (MSM_DISPLAY_CAP_VID_MODE |
  5132. MSM_DISPLAY_CAP_EDID | MSM_DISPLAY_CAP_HOT_PLUG);
  5133. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5134. mutex_unlock(&display->display_lock);
  5135. return 0;
  5136. }
  5137. static int dsi_display_ext_get_mode_info(struct drm_connector *connector,
  5138. const struct drm_display_mode *drm_mode, struct msm_sub_mode *sub_mode,
  5139. struct msm_mode_info *mode_info,
  5140. void *display, const struct msm_resource_caps_info *avail_res)
  5141. {
  5142. struct msm_display_topology *topology;
  5143. if (!drm_mode || !mode_info ||
  5144. !avail_res || !avail_res->max_mixer_width)
  5145. return -EINVAL;
  5146. memset(mode_info, 0, sizeof(*mode_info));
  5147. mode_info->frame_rate = drm_mode_vrefresh(drm_mode);
  5148. mode_info->vtotal = drm_mode->vtotal;
  5149. topology = &mode_info->topology;
  5150. topology->num_lm = (avail_res->max_mixer_width
  5151. <= drm_mode->hdisplay) ? 2 : 1;
  5152. topology->num_enc = 0;
  5153. topology->num_intf = topology->num_lm;
  5154. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  5155. return 0;
  5156. }
  5157. static struct dsi_display_ext_bridge *dsi_display_ext_get_bridge(
  5158. struct drm_bridge *bridge)
  5159. {
  5160. struct msm_drm_private *priv;
  5161. struct sde_kms *sde_kms;
  5162. struct drm_connector *conn;
  5163. struct drm_connector_list_iter conn_iter;
  5164. struct sde_connector *sde_conn;
  5165. struct dsi_display *display;
  5166. struct dsi_display_ext_bridge *dsi_bridge = NULL;
  5167. int i;
  5168. if (!bridge || !bridge->encoder) {
  5169. SDE_ERROR("invalid argument\n");
  5170. return NULL;
  5171. }
  5172. priv = bridge->dev->dev_private;
  5173. sde_kms = to_sde_kms(priv->kms);
  5174. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  5175. drm_for_each_connector_iter(conn, &conn_iter) {
  5176. sde_conn = to_sde_connector(conn);
  5177. if (sde_conn->encoder == bridge->encoder) {
  5178. display = sde_conn->display;
  5179. display_for_each_ctrl(i, display) {
  5180. if (display->ext_bridge[i].bridge == bridge) {
  5181. dsi_bridge = &display->ext_bridge[i];
  5182. break;
  5183. }
  5184. }
  5185. }
  5186. }
  5187. drm_connector_list_iter_end(&conn_iter);
  5188. return dsi_bridge;
  5189. }
  5190. static void dsi_display_drm_ext_adjust_timing(
  5191. const struct dsi_display *display,
  5192. struct drm_display_mode *mode)
  5193. {
  5194. mode->hdisplay /= display->ctrl_count;
  5195. mode->hsync_start /= display->ctrl_count;
  5196. mode->hsync_end /= display->ctrl_count;
  5197. mode->htotal /= display->ctrl_count;
  5198. mode->hskew /= display->ctrl_count;
  5199. mode->clock /= display->ctrl_count;
  5200. }
  5201. static enum drm_mode_status dsi_display_drm_ext_bridge_mode_valid(
  5202. struct drm_bridge *bridge,
  5203. const struct drm_display_info *info,
  5204. const struct drm_display_mode *mode)
  5205. {
  5206. struct dsi_display_ext_bridge *ext_bridge;
  5207. struct drm_display_mode tmp;
  5208. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5209. if (!ext_bridge)
  5210. return MODE_ERROR;
  5211. tmp = *mode;
  5212. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5213. return ext_bridge->orig_funcs->mode_valid(bridge, info, &tmp);
  5214. }
  5215. static bool dsi_display_drm_ext_bridge_mode_fixup(
  5216. struct drm_bridge *bridge,
  5217. const struct drm_display_mode *mode,
  5218. struct drm_display_mode *adjusted_mode)
  5219. {
  5220. struct dsi_display_ext_bridge *ext_bridge;
  5221. struct drm_display_mode tmp;
  5222. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5223. if (!ext_bridge)
  5224. return false;
  5225. tmp = *mode;
  5226. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5227. return ext_bridge->orig_funcs->mode_fixup(bridge, &tmp, &tmp);
  5228. }
  5229. static void dsi_display_drm_ext_bridge_mode_set(
  5230. struct drm_bridge *bridge,
  5231. const struct drm_display_mode *mode,
  5232. const struct drm_display_mode *adjusted_mode)
  5233. {
  5234. struct dsi_display_ext_bridge *ext_bridge;
  5235. struct drm_display_mode tmp;
  5236. ext_bridge = dsi_display_ext_get_bridge(bridge);
  5237. if (!ext_bridge)
  5238. return;
  5239. tmp = *mode;
  5240. dsi_display_drm_ext_adjust_timing(ext_bridge->display, &tmp);
  5241. ext_bridge->orig_funcs->mode_set(bridge, &tmp, &tmp);
  5242. }
  5243. static int dsi_host_ext_attach(struct mipi_dsi_host *host,
  5244. struct mipi_dsi_device *dsi)
  5245. {
  5246. struct dsi_display *display = to_dsi_display(host);
  5247. struct dsi_panel *panel;
  5248. if (!host || !dsi || !display->panel) {
  5249. DSI_ERR("Invalid param\n");
  5250. return -EINVAL;
  5251. }
  5252. DSI_DEBUG("DSI[%s]: channel=%d, lanes=%d, format=%d, mode_flags=%lx\n",
  5253. dsi->name, dsi->channel, dsi->lanes,
  5254. dsi->format, dsi->mode_flags);
  5255. panel = display->panel;
  5256. panel->host_config.data_lanes = 0;
  5257. if (dsi->lanes > 0)
  5258. panel->host_config.data_lanes |= DSI_DATA_LANE_0;
  5259. if (dsi->lanes > 1)
  5260. panel->host_config.data_lanes |= DSI_DATA_LANE_1;
  5261. if (dsi->lanes > 2)
  5262. panel->host_config.data_lanes |= DSI_DATA_LANE_2;
  5263. if (dsi->lanes > 3)
  5264. panel->host_config.data_lanes |= DSI_DATA_LANE_3;
  5265. switch (dsi->format) {
  5266. case MIPI_DSI_FMT_RGB888:
  5267. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
  5268. break;
  5269. case MIPI_DSI_FMT_RGB666:
  5270. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666_LOOSE;
  5271. break;
  5272. case MIPI_DSI_FMT_RGB666_PACKED:
  5273. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB666;
  5274. break;
  5275. case MIPI_DSI_FMT_RGB565:
  5276. default:
  5277. panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB565;
  5278. break;
  5279. }
  5280. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  5281. panel->panel_mode = DSI_OP_VIDEO_MODE;
  5282. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  5283. panel->video_config.traffic_mode =
  5284. DSI_VIDEO_TRAFFIC_BURST_MODE;
  5285. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  5286. panel->video_config.traffic_mode =
  5287. DSI_VIDEO_TRAFFIC_SYNC_PULSES;
  5288. else
  5289. panel->video_config.traffic_mode =
  5290. DSI_VIDEO_TRAFFIC_SYNC_START_EVENTS;
  5291. panel->video_config.hsa_lp11_en =
  5292. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA;
  5293. panel->video_config.hbp_lp11_en =
  5294. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP;
  5295. panel->video_config.hfp_lp11_en =
  5296. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP;
  5297. panel->video_config.pulse_mode_hsa_he =
  5298. dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE;
  5299. } else {
  5300. panel->panel_mode = DSI_OP_CMD_MODE;
  5301. DSI_ERR("command mode not supported by ext bridge\n");
  5302. return -ENOTSUPP;
  5303. }
  5304. panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN;
  5305. return 0;
  5306. }
  5307. static struct mipi_dsi_host_ops dsi_host_ext_ops = {
  5308. .attach = dsi_host_ext_attach,
  5309. .detach = dsi_host_detach,
  5310. .transfer = dsi_host_transfer,
  5311. };
  5312. struct drm_panel *dsi_display_get_drm_panel(struct dsi_display *display)
  5313. {
  5314. if (!display || !display->panel) {
  5315. pr_err("invalid param(s)\n");
  5316. return NULL;
  5317. }
  5318. return &display->panel->drm_panel;
  5319. }
  5320. bool dsi_display_has_dsc_switch_support(struct dsi_display *display)
  5321. {
  5322. if (!display || !display->panel) {
  5323. pr_err("invalid param(s)\n");
  5324. return false;
  5325. }
  5326. return display->panel->dsc_switch_supported;
  5327. }
  5328. int dsi_display_drm_ext_bridge_init(struct dsi_display *display,
  5329. struct drm_encoder *encoder, struct drm_connector *connector)
  5330. {
  5331. struct drm_device *drm;
  5332. struct drm_bridge *bridge;
  5333. struct drm_bridge *ext_bridge;
  5334. struct drm_connector *ext_conn;
  5335. struct sde_connector *sde_conn;
  5336. struct drm_bridge *prev_bridge;
  5337. int rc = 0, i;
  5338. if (!display || !encoder || !connector)
  5339. return -EINVAL;
  5340. drm = encoder->dev;
  5341. bridge = drm_bridge_chain_get_first_bridge(encoder);
  5342. sde_conn = to_sde_connector(connector);
  5343. prev_bridge = bridge;
  5344. if (display->panel && !display->panel->host_config.ext_bridge_mode)
  5345. return 0;
  5346. if (!bridge)
  5347. return -EINVAL;
  5348. for (i = 0; i < display->ext_bridge_cnt; i++) {
  5349. struct dsi_display_ext_bridge *ext_bridge_info =
  5350. &display->ext_bridge[i];
  5351. struct drm_encoder *c_encoder;
  5352. /* return if ext bridge is already initialized */
  5353. if (ext_bridge_info->bridge)
  5354. return 0;
  5355. ext_bridge = of_drm_find_bridge(ext_bridge_info->node_of);
  5356. if (IS_ERR_OR_NULL(ext_bridge)) {
  5357. rc = PTR_ERR(ext_bridge);
  5358. DSI_ERR("failed to find ext bridge\n");
  5359. goto error;
  5360. }
  5361. /* override functions for mode adjustment */
  5362. if (display->ext_bridge_cnt > 1) {
  5363. ext_bridge_info->bridge_funcs = *ext_bridge->funcs;
  5364. if (ext_bridge->funcs->mode_fixup)
  5365. ext_bridge_info->bridge_funcs.mode_fixup =
  5366. dsi_display_drm_ext_bridge_mode_fixup;
  5367. if (ext_bridge->funcs->mode_valid)
  5368. ext_bridge_info->bridge_funcs.mode_valid =
  5369. dsi_display_drm_ext_bridge_mode_valid;
  5370. if (ext_bridge->funcs->mode_set)
  5371. ext_bridge_info->bridge_funcs.mode_set =
  5372. dsi_display_drm_ext_bridge_mode_set;
  5373. ext_bridge_info->orig_funcs = ext_bridge->funcs;
  5374. ext_bridge->funcs = &ext_bridge_info->bridge_funcs;
  5375. }
  5376. rc = drm_bridge_attach(encoder, ext_bridge, prev_bridge, 0);
  5377. if (rc) {
  5378. DSI_ERR("[%s] ext brige attach failed, %d\n",
  5379. display->name, rc);
  5380. goto error;
  5381. }
  5382. ext_bridge_info->display = display;
  5383. ext_bridge_info->bridge = ext_bridge;
  5384. prev_bridge = ext_bridge;
  5385. /* ext bridge will init its own connector during attach,
  5386. * we need to extract it out of the connector list
  5387. */
  5388. spin_lock_irq(&drm->mode_config.connector_list_lock);
  5389. ext_conn = list_last_entry(&drm->mode_config.connector_list,
  5390. struct drm_connector, head);
  5391. if (!ext_conn) {
  5392. DSI_ERR("failed to get external connector\n");
  5393. rc = PTR_ERR(ext_conn);
  5394. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5395. goto error;
  5396. }
  5397. drm_connector_for_each_possible_encoder(ext_conn, c_encoder)
  5398. break;
  5399. if (!c_encoder) {
  5400. DSI_ERR("failed to get encoder\n");
  5401. rc = PTR_ERR(c_encoder);
  5402. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5403. goto error;
  5404. }
  5405. if (ext_conn && ext_conn != connector &&
  5406. c_encoder->base.id == bridge->encoder->base.id) {
  5407. list_del_init(&ext_conn->head);
  5408. display->ext_conn = ext_conn;
  5409. }
  5410. spin_unlock_irq(&drm->mode_config.connector_list_lock);
  5411. /* if there is no valid external connector created, or in split
  5412. * mode, default setting is used from panel defined in DT file.
  5413. */
  5414. if (!display->ext_conn ||
  5415. !display->ext_conn->funcs ||
  5416. !display->ext_conn->helper_private ||
  5417. display->ext_bridge_cnt > 1) {
  5418. display->ext_conn = NULL;
  5419. continue;
  5420. }
  5421. /* otherwise, hook up the functions to use external connector */
  5422. if (display->ext_conn->funcs->detect)
  5423. sde_conn->ops.detect = dsi_display_drm_ext_detect;
  5424. if (display->ext_conn->helper_private->get_modes)
  5425. sde_conn->ops.get_modes =
  5426. dsi_display_drm_ext_get_modes;
  5427. if (display->ext_conn->helper_private->mode_valid)
  5428. sde_conn->ops.mode_valid =
  5429. dsi_display_drm_ext_mode_valid;
  5430. if (display->ext_conn->helper_private->atomic_check)
  5431. sde_conn->ops.atomic_check =
  5432. dsi_display_drm_ext_atomic_check;
  5433. sde_conn->ops.get_info =
  5434. dsi_display_ext_get_info;
  5435. sde_conn->ops.get_mode_info =
  5436. dsi_display_ext_get_mode_info;
  5437. /* add support to attach/detach */
  5438. display->host.ops = &dsi_host_ext_ops;
  5439. }
  5440. return 0;
  5441. error:
  5442. return rc;
  5443. }
  5444. int dsi_display_get_info(struct drm_connector *connector,
  5445. struct msm_display_info *info, void *disp)
  5446. {
  5447. struct dsi_display *display;
  5448. struct dsi_panel_phy_props phy_props;
  5449. struct dsi_host_common_cfg *host;
  5450. int i, rc;
  5451. if (!info || !disp) {
  5452. DSI_ERR("invalid params\n");
  5453. return -EINVAL;
  5454. }
  5455. display = disp;
  5456. if (!display->panel) {
  5457. DSI_ERR("invalid display panel\n");
  5458. return -EINVAL;
  5459. }
  5460. mutex_lock(&display->display_lock);
  5461. rc = dsi_panel_get_phy_props(display->panel, &phy_props);
  5462. if (rc) {
  5463. DSI_ERR("[%s] failed to get panel phy props, rc=%d\n",
  5464. display->name, rc);
  5465. goto error;
  5466. }
  5467. memset(info, 0, sizeof(struct msm_display_info));
  5468. info->intf_type = DRM_MODE_CONNECTOR_DSI;
  5469. info->num_of_h_tiles = display->ctrl_count;
  5470. for (i = 0; i < info->num_of_h_tiles; i++)
  5471. info->h_tile_instance[i] = display->ctrl[i].ctrl->cell_index;
  5472. info->is_connected = display->is_active;
  5473. if (!strcmp(display->display_type, "primary"))
  5474. info->display_type = SDE_CONNECTOR_PRIMARY;
  5475. else if (!strcmp(display->display_type, "secondary"))
  5476. info->display_type = SDE_CONNECTOR_SECONDARY;
  5477. info->width_mm = phy_props.panel_width_mm;
  5478. info->height_mm = phy_props.panel_height_mm;
  5479. info->max_width = 1920;
  5480. info->max_height = 1080;
  5481. info->qsync_min_fps = display->panel->qsync_caps.qsync_min_fps;
  5482. info->has_qsync_min_fps_list = (display->panel->qsync_caps.qsync_min_fps_list_len > 0);
  5483. info->has_avr_step_req = (display->panel->avr_caps.avr_step_fps_list_len > 0);
  5484. info->poms_align_vsync = display->panel->poms_align_vsync;
  5485. switch (display->panel->panel_mode) {
  5486. case DSI_OP_VIDEO_MODE:
  5487. info->curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  5488. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5489. if (display->panel->panel_mode_switch_enabled)
  5490. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5491. break;
  5492. case DSI_OP_CMD_MODE:
  5493. info->curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  5494. info->capabilities |= MSM_DISPLAY_CAP_CMD_MODE;
  5495. if (display->panel->panel_mode_switch_enabled)
  5496. info->capabilities |= MSM_DISPLAY_CAP_VID_MODE;
  5497. info->is_te_using_watchdog_timer = is_sim_panel(display);
  5498. break;
  5499. default:
  5500. DSI_ERR("unknwown dsi panel mode %d\n",
  5501. display->panel->panel_mode);
  5502. break;
  5503. }
  5504. if (display->panel->esd_config.esd_enabled && !is_sim_panel(display))
  5505. info->capabilities |= MSM_DISPLAY_ESD_ENABLED;
  5506. info->te_source = display->te_source;
  5507. host = &display->panel->host_config;
  5508. if (host->split_link.enabled)
  5509. info->capabilities |= MSM_DISPLAY_SPLIT_LINK;
  5510. info->dsc_count = display->panel->dsc_count;
  5511. info->lm_count = display->panel->lm_count;
  5512. error:
  5513. mutex_unlock(&display->display_lock);
  5514. return rc;
  5515. }
  5516. int dsi_display_get_mode_count(struct dsi_display *display,
  5517. u32 *count)
  5518. {
  5519. if (!display || !display->panel) {
  5520. DSI_ERR("invalid display:%d panel:%d\n", display != NULL,
  5521. display ? display->panel != NULL : 0);
  5522. return -EINVAL;
  5523. }
  5524. mutex_lock(&display->display_lock);
  5525. *count = display->panel->num_display_modes;
  5526. mutex_unlock(&display->display_lock);
  5527. return 0;
  5528. }
  5529. void dsi_display_adjust_mode_timing(struct dsi_display *display,
  5530. struct dsi_display_mode *dsi_mode,
  5531. int lanes, int bpp)
  5532. {
  5533. u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
  5534. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5535. u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
  5536. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5537. /* Constant FPS is not supported on command mode */
  5538. if (!(dsi_mode->panel_mode_caps & DSI_OP_VIDEO_MODE))
  5539. return;
  5540. if (!dyn_clk_caps->maintain_const_fps)
  5541. return;
  5542. /*
  5543. * When there is a dynamic clock switch, there is small change
  5544. * in FPS. To compensate for this difference in FPS, hfp or vfp
  5545. * is adjusted. It has been assumed that the refined porch values
  5546. * are supported by the panel. This logic can be enhanced further
  5547. * in future by taking min/max porches supported by the panel.
  5548. */
  5549. switch (dyn_clk_caps->type) {
  5550. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_HFP:
  5551. vtotal = DSI_V_TOTAL(&dsi_mode->timing);
  5552. old_htotal = dsi_h_total_dce(&dsi_mode->timing);
  5553. do_div(old_htotal, display->ctrl_count);
  5554. new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
  5555. div = bpp * vtotal * dsi_mode->timing.refresh_rate;
  5556. if (dsi_display_is_type_cphy(display)) {
  5557. new_htotal = new_htotal * bits_per_symbol;
  5558. div = div * num_of_symbols;
  5559. }
  5560. do_div(new_htotal, div);
  5561. if (old_htotal > new_htotal)
  5562. dsi_mode->timing.h_front_porch -=
  5563. ((old_htotal - new_htotal) * display->ctrl_count);
  5564. else
  5565. dsi_mode->timing.h_front_porch +=
  5566. ((new_htotal - old_htotal) * display->ctrl_count);
  5567. break;
  5568. case DSI_DYN_CLK_TYPE_CONST_FPS_ADJUST_VFP:
  5569. htotal = dsi_h_total_dce(&dsi_mode->timing);
  5570. do_div(htotal, display->ctrl_count);
  5571. new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
  5572. div = bpp * htotal * dsi_mode->timing.refresh_rate;
  5573. if (dsi_display_is_type_cphy(display)) {
  5574. new_vtotal = new_vtotal * bits_per_symbol;
  5575. div = div * num_of_symbols;
  5576. }
  5577. do_div(new_vtotal, div);
  5578. dsi_mode->timing.v_front_porch = new_vtotal -
  5579. dsi_mode->timing.v_back_porch -
  5580. dsi_mode->timing.v_sync_width -
  5581. dsi_mode->timing.v_active;
  5582. break;
  5583. default:
  5584. break;
  5585. }
  5586. }
  5587. static void _dsi_display_populate_bit_clks(struct dsi_display *display, int start, int end)
  5588. {
  5589. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5590. struct dsi_display_mode *src;
  5591. struct dsi_host_common_cfg *cfg;
  5592. int i, bpp, lanes = 0;
  5593. if (!display)
  5594. return;
  5595. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5596. if (!dyn_clk_caps->dyn_clk_support)
  5597. return;
  5598. cfg = &(display->panel->host_config);
  5599. bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
  5600. if (cfg->data_lanes & DSI_DATA_LANE_0)
  5601. lanes++;
  5602. if (cfg->data_lanes & DSI_DATA_LANE_1)
  5603. lanes++;
  5604. if (cfg->data_lanes & DSI_DATA_LANE_2)
  5605. lanes++;
  5606. if (cfg->data_lanes & DSI_DATA_LANE_3)
  5607. lanes++;
  5608. for (i = start; i < end; i++) {
  5609. src = &display->modes[i];
  5610. if (!src)
  5611. return;
  5612. if (!src->priv_info->bit_clk_list.count)
  5613. continue;
  5614. src->timing.clk_rate_hz = src->priv_info->bit_clk_list.rates[0];
  5615. dsi_display_adjust_mode_timing(display, src, lanes, bpp);
  5616. src->pixel_clk_khz = div_u64(src->timing.clk_rate_hz * lanes, bpp);
  5617. src->pixel_clk_khz /= 1000;
  5618. src->pixel_clk_khz *= display->ctrl_count;
  5619. }
  5620. }
  5621. int dsi_display_restore_bit_clk(struct dsi_display *display, struct dsi_display_mode *mode)
  5622. {
  5623. int i;
  5624. u32 clk_rate_hz = 0;
  5625. if (!display || !mode || !mode->priv_info) {
  5626. DSI_ERR("invalid arguments\n");
  5627. return -EINVAL;
  5628. }
  5629. clk_rate_hz = display->cached_clk_rate;
  5630. if (mode->priv_info->bit_clk_list.count) {
  5631. /* use first entry as the default bit clk rate */
  5632. clk_rate_hz = mode->priv_info->bit_clk_list.rates[0];
  5633. for (i = 0; i < mode->priv_info->bit_clk_list.count; i++) {
  5634. if (display->dyn_bit_clk == mode->priv_info->bit_clk_list.rates[i])
  5635. clk_rate_hz = display->dyn_bit_clk;
  5636. }
  5637. }
  5638. mode->timing.clk_rate_hz = clk_rate_hz;
  5639. mode->priv_info->clk_rate_hz = clk_rate_hz;
  5640. SDE_EVT32(clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5641. DSI_DEBUG("clk_rate_hz:%u, cached_clk_rate:%u, dyn_bit_clk:%u\n",
  5642. clk_rate_hz, display->cached_clk_rate, display->dyn_bit_clk);
  5643. return 0;
  5644. }
  5645. void dsi_display_put_mode(struct dsi_display *display,
  5646. struct dsi_display_mode *mode)
  5647. {
  5648. dsi_panel_put_mode(mode);
  5649. }
  5650. int dsi_display_get_modes(struct dsi_display *display,
  5651. struct dsi_display_mode **out_modes)
  5652. {
  5653. struct dsi_dfps_capabilities dfps_caps;
  5654. struct dsi_display_ctrl *ctrl;
  5655. struct dsi_host_common_cfg *host = &display->panel->host_config;
  5656. bool is_split_link, support_cmd_mode, support_video_mode;
  5657. u32 num_dfps_rates, timing_mode_count, display_mode_count;
  5658. u32 sublinks_count, mode_idx, array_idx = 0;
  5659. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5660. int i, start, end, rc = -EINVAL;
  5661. int dsc_modes = 0, nondsc_modes = 0;
  5662. if (!display || !out_modes) {
  5663. DSI_ERR("Invalid params\n");
  5664. return -EINVAL;
  5665. }
  5666. *out_modes = NULL;
  5667. ctrl = &display->ctrl[0];
  5668. mutex_lock(&display->display_lock);
  5669. if (display->modes)
  5670. goto exit;
  5671. display_mode_count = display->panel->num_display_modes;
  5672. display->modes = kcalloc(display_mode_count, sizeof(*display->modes),
  5673. GFP_KERNEL);
  5674. if (!display->modes) {
  5675. rc = -ENOMEM;
  5676. goto error;
  5677. }
  5678. rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5679. if (rc) {
  5680. DSI_ERR("[%s] failed to get dfps caps from panel\n",
  5681. display->name);
  5682. goto error;
  5683. }
  5684. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5685. timing_mode_count = display->panel->num_timing_nodes;
  5686. /* Validate command line timing */
  5687. if ((display->cmdline_timing != NO_OVERRIDE) &&
  5688. (display->cmdline_timing >= timing_mode_count))
  5689. display->cmdline_timing = NO_OVERRIDE;
  5690. for (mode_idx = 0; mode_idx < timing_mode_count; mode_idx++) {
  5691. struct dsi_display_mode display_mode;
  5692. int topology_override = NO_OVERRIDE;
  5693. bool is_preferred = false;
  5694. u32 frame_threshold_us = ctrl->ctrl->frame_threshold_time_us;
  5695. memset(&display_mode, 0, sizeof(display_mode));
  5696. rc = dsi_panel_get_mode(display->panel, mode_idx,
  5697. &display_mode,
  5698. topology_override);
  5699. if (rc) {
  5700. DSI_ERR("[%s] failed to get mode idx %d from panel\n",
  5701. display->name, mode_idx);
  5702. goto error;
  5703. }
  5704. if (display->cmdline_timing == display_mode.mode_idx) {
  5705. topology_override = display->cmdline_topology;
  5706. is_preferred = true;
  5707. }
  5708. support_cmd_mode = display_mode.panel_mode_caps & DSI_OP_CMD_MODE;
  5709. support_video_mode = display_mode.panel_mode_caps & DSI_OP_VIDEO_MODE;
  5710. if (display_mode.priv_info->dsc_enabled)
  5711. dsc_modes++;
  5712. else
  5713. nondsc_modes++;
  5714. /* Setup widebus support */
  5715. display_mode.priv_info->widebus_support =
  5716. ctrl->ctrl->hw.widebus_support;
  5717. num_dfps_rates = ((!dfps_caps.dfps_support ||
  5718. !support_video_mode) ? 1 : dfps_caps.dfps_list_len);
  5719. /* Calculate dsi frame transfer time */
  5720. if (support_cmd_mode) {
  5721. dsi_panel_calc_dsi_transfer_time(
  5722. &display->panel->host_config,
  5723. &display_mode, frame_threshold_us);
  5724. display_mode.priv_info->dsi_transfer_time_us =
  5725. display_mode.timing.dsi_transfer_time_us;
  5726. display_mode.priv_info->min_dsi_clk_hz =
  5727. display_mode.timing.min_dsi_clk_hz;
  5728. display_mode.priv_info->mdp_transfer_time_us =
  5729. display_mode.timing.mdp_transfer_time_us;
  5730. }
  5731. is_split_link = host->split_link.enabled;
  5732. sublinks_count = host->split_link.num_sublinks;
  5733. if (is_split_link && sublinks_count > 1) {
  5734. display_mode.timing.h_active *= sublinks_count;
  5735. display_mode.timing.h_front_porch *= sublinks_count;
  5736. display_mode.timing.h_sync_width *= sublinks_count;
  5737. display_mode.timing.h_back_porch *= sublinks_count;
  5738. display_mode.timing.h_skew *= sublinks_count;
  5739. display_mode.pixel_clk_khz *= sublinks_count;
  5740. } else {
  5741. display_mode.timing.h_active *= display->ctrl_count;
  5742. display_mode.timing.h_front_porch *=
  5743. display->ctrl_count;
  5744. display_mode.timing.h_sync_width *=
  5745. display->ctrl_count;
  5746. display_mode.timing.h_back_porch *=
  5747. display->ctrl_count;
  5748. display_mode.timing.h_skew *= display->ctrl_count;
  5749. display_mode.pixel_clk_khz *= display->ctrl_count;
  5750. }
  5751. start = array_idx;
  5752. for (i = 0; i < num_dfps_rates; i++) {
  5753. struct dsi_display_mode *sub_mode =
  5754. &display->modes[array_idx];
  5755. u32 curr_refresh_rate;
  5756. if (!sub_mode) {
  5757. DSI_ERR("invalid mode data\n");
  5758. rc = -EFAULT;
  5759. goto error;
  5760. }
  5761. memcpy(sub_mode, &display_mode, sizeof(display_mode));
  5762. array_idx++;
  5763. if (!dfps_caps.dfps_support || !support_video_mode)
  5764. continue;
  5765. sub_mode->mode_idx += (array_idx - 1);
  5766. curr_refresh_rate = sub_mode->timing.refresh_rate;
  5767. sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i];
  5768. dsi_display_get_dfps_timing(display, sub_mode,
  5769. curr_refresh_rate);
  5770. sub_mode->panel_mode_caps = DSI_OP_VIDEO_MODE;
  5771. }
  5772. end = array_idx;
  5773. _dsi_display_populate_bit_clks(display, start, end);
  5774. if (is_preferred) {
  5775. /* Set first timing sub mode as preferred mode */
  5776. display->modes[start].is_preferred = true;
  5777. }
  5778. }
  5779. if (dsc_modes && nondsc_modes)
  5780. display->panel->dsc_switch_supported = true;
  5781. exit:
  5782. *out_modes = display->modes;
  5783. rc = 0;
  5784. error:
  5785. if (rc)
  5786. kfree(display->modes);
  5787. mutex_unlock(&display->display_lock);
  5788. return rc;
  5789. }
  5790. int dsi_display_get_panel_vfp(void *dsi_display,
  5791. int h_active, int v_active)
  5792. {
  5793. int i, rc = 0;
  5794. u32 count, refresh_rate = 0;
  5795. struct dsi_dfps_capabilities dfps_caps;
  5796. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5797. struct dsi_host_common_cfg *host;
  5798. if (!display || !display->panel)
  5799. return -EINVAL;
  5800. mutex_lock(&display->display_lock);
  5801. count = display->panel->num_display_modes;
  5802. if (display->panel->cur_mode)
  5803. refresh_rate = display->panel->cur_mode->timing.refresh_rate;
  5804. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  5805. if (dfps_caps.dfps_support)
  5806. refresh_rate = dfps_caps.max_refresh_rate;
  5807. if (!refresh_rate) {
  5808. mutex_unlock(&display->display_lock);
  5809. DSI_ERR("Null Refresh Rate\n");
  5810. return -EINVAL;
  5811. }
  5812. host = &display->panel->host_config;
  5813. if (host->split_link.enabled)
  5814. h_active *= host->split_link.num_sublinks;
  5815. else
  5816. h_active *= display->ctrl_count;
  5817. for (i = 0; i < count; i++) {
  5818. struct dsi_display_mode *m = &display->modes[i];
  5819. if (m && v_active == m->timing.v_active &&
  5820. h_active == m->timing.h_active &&
  5821. refresh_rate == m->timing.refresh_rate) {
  5822. rc = m->timing.v_front_porch;
  5823. break;
  5824. }
  5825. }
  5826. mutex_unlock(&display->display_lock);
  5827. return rc;
  5828. }
  5829. int dsi_display_get_default_lms(void *dsi_display, u32 *num_lm)
  5830. {
  5831. struct dsi_display *display = (struct dsi_display *)dsi_display;
  5832. u32 count, i;
  5833. int rc = 0;
  5834. *num_lm = 0;
  5835. mutex_lock(&display->display_lock);
  5836. count = display->panel->num_display_modes;
  5837. mutex_unlock(&display->display_lock);
  5838. if (!display->modes) {
  5839. struct dsi_display_mode *m;
  5840. rc = dsi_display_get_modes(display, &m);
  5841. if (rc)
  5842. return rc;
  5843. }
  5844. mutex_lock(&display->display_lock);
  5845. for (i = 0; i < count; i++) {
  5846. struct dsi_display_mode *m = &display->modes[i];
  5847. *num_lm = max(m->priv_info->topology.num_lm, *num_lm);
  5848. }
  5849. mutex_unlock(&display->display_lock);
  5850. return rc;
  5851. }
  5852. int dsi_display_get_qsync_min_fps(void *display_dsi, u32 mode_fps)
  5853. {
  5854. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5855. struct dsi_panel *panel;
  5856. u32 i;
  5857. if (display == NULL || display->panel == NULL)
  5858. return -EINVAL;
  5859. panel = display->panel;
  5860. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5861. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5862. return panel->qsync_caps.qsync_min_fps_list[i];
  5863. }
  5864. SDE_EVT32(mode_fps);
  5865. DSI_DEBUG("Invalid mode_fps %d\n", mode_fps);
  5866. return -EINVAL;
  5867. }
  5868. int dsi_display_get_avr_step_req_fps(void *display_dsi, u32 mode_fps)
  5869. {
  5870. struct dsi_display *display = (struct dsi_display *)display_dsi;
  5871. struct dsi_panel *panel;
  5872. u32 i, step = 0;
  5873. if (!display || !display->panel)
  5874. return -EINVAL;
  5875. panel = display->panel;
  5876. /* support a single fixed rate, or rate corresponding to dfps list entry */
  5877. if (panel->avr_caps.avr_step_fps_list_len == 1) {
  5878. step = panel->avr_caps.avr_step_fps_list[0];
  5879. } else if (panel->avr_caps.avr_step_fps_list_len > 1) {
  5880. for (i = 0; i < panel->dfps_caps.dfps_list_len; i++) {
  5881. if (panel->dfps_caps.dfps_list[i] == mode_fps)
  5882. step = panel->avr_caps.avr_step_fps_list[i];
  5883. }
  5884. }
  5885. DSI_DEBUG("mode_fps %u, avr_step fps %u\n", mode_fps, step);
  5886. return step;
  5887. }
  5888. static bool dsi_display_match_timings(const struct dsi_display_mode *mode1,
  5889. struct dsi_display_mode *mode2, unsigned int match_flags)
  5890. {
  5891. bool is_matching = false;
  5892. if (match_flags & DSI_MODE_MATCH_ACTIVE_TIMINGS) {
  5893. is_matching = mode1->timing.h_active == mode2->timing.h_active &&
  5894. mode1->timing.v_active == mode2->timing.v_active &&
  5895. mode1->timing.refresh_rate == mode2->timing.refresh_rate;
  5896. if (!is_matching)
  5897. goto end;
  5898. }
  5899. if (match_flags & DSI_MODE_MATCH_PORCH_TIMINGS)
  5900. is_matching = mode1->timing.h_back_porch == mode2->timing.h_back_porch &&
  5901. mode1->timing.h_front_porch == mode2->timing.h_front_porch &&
  5902. mode1->timing.h_sync_width == mode2->timing.h_sync_width &&
  5903. mode1->timing.h_skew == mode2->timing.h_skew &&
  5904. mode1->timing.v_back_porch == mode2->timing.v_back_porch &&
  5905. mode1->timing.v_front_porch == mode2->timing.v_front_porch &&
  5906. mode1->timing.v_sync_width == mode2->timing.v_sync_width;
  5907. end:
  5908. return is_matching;
  5909. }
  5910. bool dsi_display_mode_match(const struct dsi_display_mode *mode1,
  5911. struct dsi_display_mode *mode2, unsigned int match_flags)
  5912. {
  5913. if (!mode1 && !mode2)
  5914. return true;
  5915. if (!mode1 || !mode2)
  5916. return false;
  5917. if ((match_flags & DSI_MODE_MATCH_FULL_TIMINGS) &&
  5918. !dsi_display_match_timings(mode1, mode2, match_flags))
  5919. return false;
  5920. if ((match_flags & DSI_MODE_MATCH_DSC_CONFIG) &&
  5921. mode1->priv_info->dsc_enabled != mode2->priv_info->dsc_enabled)
  5922. return false;
  5923. return true;
  5924. }
  5925. int dsi_display_find_mode(struct dsi_display *display,
  5926. struct dsi_display_mode *cmp,
  5927. struct msm_sub_mode *sub_mode,
  5928. struct dsi_display_mode **out_mode)
  5929. {
  5930. u32 count, i;
  5931. int rc;
  5932. struct dsi_display_mode *m;
  5933. struct dsi_dyn_clk_caps *dyn_clk_caps;
  5934. unsigned int match_flags = DSI_MODE_MATCH_FULL_TIMINGS;
  5935. struct dsi_display_mode_priv_info priv_info;
  5936. if (!display || !out_mode)
  5937. return -EINVAL;
  5938. *out_mode = NULL;
  5939. mutex_lock(&display->display_lock);
  5940. count = display->panel->num_display_modes;
  5941. mutex_unlock(&display->display_lock);
  5942. if (!display->modes) {
  5943. rc = dsi_display_get_modes(display, &m);
  5944. if (rc)
  5945. return rc;
  5946. }
  5947. mutex_lock(&display->display_lock);
  5948. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  5949. for (i = 0; i < count; i++) {
  5950. m = &display->modes[i];
  5951. /**
  5952. * When dynamic bit clock is enabled with contants FPS,
  5953. * the adjusted mode porches value may not match the panel
  5954. * default mode porches and panel mode lookup will fail.
  5955. * In that case we omit porches in mode matching function.
  5956. */
  5957. if (dyn_clk_caps->maintain_const_fps)
  5958. match_flags = DSI_MODE_MATCH_ACTIVE_TIMINGS;
  5959. if (sub_mode && sub_mode->dsc_mode) {
  5960. match_flags |= DSI_MODE_MATCH_DSC_CONFIG;
  5961. cmp->priv_info = &priv_info;
  5962. memset(cmp->priv_info, 0,
  5963. sizeof(struct dsi_display_mode_priv_info));
  5964. cmp->priv_info->dsc_enabled = (sub_mode->dsc_mode ==
  5965. MSM_DISPLAY_DSC_MODE_ENABLED) ? true : false;
  5966. }
  5967. if (dsi_display_mode_match(cmp, m, match_flags)) {
  5968. *out_mode = m;
  5969. rc = 0;
  5970. break;
  5971. }
  5972. }
  5973. mutex_unlock(&display->display_lock);
  5974. if (!*out_mode) {
  5975. DSI_ERR("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n",
  5976. display->name, cmp->timing.v_active,
  5977. cmp->timing.h_active, cmp->timing.refresh_rate,
  5978. cmp->pixel_clk_khz);
  5979. rc = -ENOENT;
  5980. }
  5981. return rc;
  5982. }
  5983. static inline bool dsi_display_mode_switch_dfps(struct dsi_display_mode *cur,
  5984. struct dsi_display_mode *adj)
  5985. {
  5986. /*
  5987. * If there is a change in the hfp or vfp of the current and adjoining
  5988. * mode,then either it is a dfps mode switch or dynamic clk change with
  5989. * constant fps.
  5990. */
  5991. if ((cur->timing.h_front_porch != adj->timing.h_front_porch) ||
  5992. (cur->timing.v_front_porch != adj->timing.v_front_porch))
  5993. return true;
  5994. else
  5995. return false;
  5996. }
  5997. /**
  5998. * dsi_display_validate_mode_change() - Validate mode change case.
  5999. * @display: DSI display handle.
  6000. * @cur_mode: Current mode.
  6001. * @adj_mode: Mode to be set.
  6002. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there
  6003. * is change in hfp or vfp but vactive and hactive are same.
  6004. * DSI_MODE_FLAG_DYN_CLK flag is set if there
  6005. * is change in clk but vactive and hactive are same.
  6006. * Return: error code.
  6007. */
  6008. int dsi_display_validate_mode_change(struct dsi_display *display,
  6009. struct dsi_display_mode *cur_mode,
  6010. struct dsi_display_mode *adj_mode)
  6011. {
  6012. int rc = 0;
  6013. struct dsi_dfps_capabilities dfps_caps;
  6014. struct dsi_dyn_clk_caps *dyn_clk_caps;
  6015. struct sde_connector *sde_conn;
  6016. if (!display || !adj_mode || !display->drm_conn) {
  6017. DSI_ERR("Invalid params\n");
  6018. return -EINVAL;
  6019. }
  6020. if (!display->panel || !display->panel->cur_mode) {
  6021. DSI_DEBUG("Current panel mode not set\n");
  6022. return rc;
  6023. }
  6024. if ((cur_mode->timing.v_active != adj_mode->timing.v_active) ||
  6025. (cur_mode->timing.h_active != adj_mode->timing.h_active)) {
  6026. DSI_DEBUG("Avoid VRR and POMS when resolution is changed\n");
  6027. return rc;
  6028. }
  6029. sde_conn = to_sde_connector(display->drm_conn);
  6030. mutex_lock(&display->display_lock);
  6031. if (sde_conn->expected_panel_mode == MSM_DISPLAY_VIDEO_MODE &&
  6032. display->config.panel_mode == DSI_OP_CMD_MODE) {
  6033. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_VID;
  6034. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1, sde_conn->expected_panel_mode,
  6035. display->config.panel_mode);
  6036. DSI_DEBUG("Panel operating mode change to video detected\n");
  6037. } else if (sde_conn->expected_panel_mode == MSM_DISPLAY_CMD_MODE &&
  6038. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6039. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS_TO_CMD;
  6040. SDE_EVT32(SDE_EVTLOG_FUNC_CASE2, sde_conn->expected_panel_mode,
  6041. display->config.panel_mode);
  6042. DSI_DEBUG("Panel operating mode change to command detected\n");
  6043. } else if (cur_mode->timing.dsc_enabled != adj_mode->timing.dsc_enabled) {
  6044. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  6045. SDE_EVT32(SDE_EVTLOG_FUNC_CASE3, cur_mode->timing.dsc_enabled,
  6046. adj_mode->timing.dsc_enabled);
  6047. DSI_DEBUG("DSC mode change detected\n");
  6048. } else {
  6049. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  6050. /* dfps and dynamic clock with const fps use case */
  6051. if (dsi_display_mode_switch_dfps(cur_mode, adj_mode)) {
  6052. dsi_panel_get_dfps_caps(display->panel, &dfps_caps);
  6053. if (dfps_caps.dfps_support ||
  6054. dyn_clk_caps->maintain_const_fps) {
  6055. DSI_DEBUG("Mode switch is seamless variable refresh\n");
  6056. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6057. SDE_EVT32(SDE_EVTLOG_FUNC_CASE4,
  6058. cur_mode->timing.refresh_rate,
  6059. adj_mode->timing.refresh_rate,
  6060. cur_mode->timing.h_front_porch,
  6061. adj_mode->timing.h_front_porch,
  6062. cur_mode->timing.v_front_porch,
  6063. adj_mode->timing.v_front_porch);
  6064. }
  6065. }
  6066. /* dynamic clk change use case */
  6067. if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) {
  6068. if (dyn_clk_caps->dyn_clk_support) {
  6069. DSI_DEBUG("dynamic clk change detected\n");
  6070. if ((adj_mode->dsi_mode_flags &
  6071. DSI_MODE_FLAG_VRR) &&
  6072. (!dyn_clk_caps->maintain_const_fps)) {
  6073. DSI_ERR("dfps and dyn clk not supported in same commit\n");
  6074. rc = -ENOTSUPP;
  6075. goto error;
  6076. }
  6077. /**
  6078. * Set VRR flag whenever there is a dynamic clock
  6079. * change on video mode panel as dynamic refresh is
  6080. * always required when fps compensation is enabled.
  6081. */
  6082. if ((display->config.panel_mode == DSI_OP_VIDEO_MODE) &&
  6083. dyn_clk_caps->maintain_const_fps)
  6084. adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  6085. adj_mode->dsi_mode_flags |=
  6086. DSI_MODE_FLAG_DYN_CLK;
  6087. SDE_EVT32(SDE_EVTLOG_FUNC_CASE5,
  6088. cur_mode->pixel_clk_khz,
  6089. adj_mode->pixel_clk_khz);
  6090. }
  6091. }
  6092. }
  6093. error:
  6094. mutex_unlock(&display->display_lock);
  6095. return rc;
  6096. }
  6097. int dsi_display_validate_mode(struct dsi_display *display,
  6098. struct dsi_display_mode *mode,
  6099. u32 flags)
  6100. {
  6101. int rc = 0;
  6102. int i;
  6103. struct dsi_display_ctrl *ctrl;
  6104. struct dsi_display_mode adj_mode;
  6105. if (!display || !mode) {
  6106. DSI_ERR("Invalid params\n");
  6107. return -EINVAL;
  6108. }
  6109. mutex_lock(&display->display_lock);
  6110. adj_mode = *mode;
  6111. adjust_timing_by_ctrl_count(display, &adj_mode);
  6112. rc = dsi_panel_validate_mode(display->panel, &adj_mode);
  6113. if (rc) {
  6114. DSI_ERR("[%s] panel mode validation failed, rc=%d\n",
  6115. display->name, rc);
  6116. goto error;
  6117. }
  6118. display_for_each_ctrl(i, display) {
  6119. ctrl = &display->ctrl[i];
  6120. rc = dsi_ctrl_validate_timing(ctrl->ctrl, &adj_mode.timing);
  6121. if (rc) {
  6122. DSI_ERR("[%s] ctrl mode validation failed, rc=%d\n",
  6123. display->name, rc);
  6124. goto error;
  6125. }
  6126. rc = dsi_phy_validate_mode(ctrl->phy, &adj_mode.timing);
  6127. if (rc) {
  6128. DSI_ERR("[%s] phy mode validation failed, rc=%d\n",
  6129. display->name, rc);
  6130. goto error;
  6131. }
  6132. }
  6133. if ((flags & DSI_VALIDATE_FLAG_ALLOW_ADJUST) &&
  6134. (mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)) {
  6135. rc = dsi_display_validate_mode_seamless(display, mode);
  6136. if (rc) {
  6137. DSI_ERR("[%s] seamless not possible rc=%d\n",
  6138. display->name, rc);
  6139. goto error;
  6140. }
  6141. }
  6142. error:
  6143. mutex_unlock(&display->display_lock);
  6144. return rc;
  6145. }
  6146. int dsi_display_set_mode(struct dsi_display *display,
  6147. struct dsi_display_mode *mode,
  6148. u32 flags)
  6149. {
  6150. int rc = 0;
  6151. struct dsi_display_mode adj_mode;
  6152. struct dsi_mode_info timing;
  6153. if (!display || !mode || !display->panel) {
  6154. DSI_ERR("Invalid params\n");
  6155. return -EINVAL;
  6156. }
  6157. mutex_lock(&display->display_lock);
  6158. adj_mode = *mode;
  6159. timing = adj_mode.timing;
  6160. adjust_timing_by_ctrl_count(display, &adj_mode);
  6161. if (!display->panel->cur_mode) {
  6162. display->panel->cur_mode =
  6163. kzalloc(sizeof(struct dsi_display_mode), GFP_KERNEL);
  6164. if (!display->panel->cur_mode) {
  6165. rc = -ENOMEM;
  6166. goto error;
  6167. }
  6168. }
  6169. rc = dsi_display_restore_bit_clk(display, &adj_mode);
  6170. if (rc) {
  6171. DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
  6172. goto error;
  6173. }
  6174. rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
  6175. if (rc) {
  6176. DSI_ERR("[%s] mode cannot be set\n", display->name);
  6177. goto error;
  6178. }
  6179. rc = dsi_display_set_mode_sub(display, &adj_mode, flags);
  6180. if (rc) {
  6181. DSI_ERR("[%s] failed to set mode\n", display->name);
  6182. goto error;
  6183. }
  6184. DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d, clk_rate=%llu\n",
  6185. adj_mode.priv_info->mdp_transfer_time_us,
  6186. timing.h_active, timing.v_active, timing.refresh_rate,
  6187. adj_mode.priv_info->clk_rate_hz);
  6188. SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
  6189. timing.h_active, timing.v_active, timing.refresh_rate,
  6190. adj_mode.priv_info->clk_rate_hz);
  6191. memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
  6192. error:
  6193. mutex_unlock(&display->display_lock);
  6194. return rc;
  6195. }
  6196. int dsi_display_set_tpg_state(struct dsi_display *display, bool enable)
  6197. {
  6198. int rc = 0;
  6199. int i;
  6200. struct dsi_display_ctrl *ctrl;
  6201. if (!display) {
  6202. DSI_ERR("Invalid params\n");
  6203. return -EINVAL;
  6204. }
  6205. display_for_each_ctrl(i, display) {
  6206. ctrl = &display->ctrl[i];
  6207. rc = dsi_ctrl_set_tpg_state(ctrl->ctrl, enable);
  6208. if (rc) {
  6209. DSI_ERR("[%s] failed to set tpg state for host_%d\n",
  6210. display->name, i);
  6211. goto error;
  6212. }
  6213. }
  6214. display->is_tpg_enabled = enable;
  6215. error:
  6216. return rc;
  6217. }
  6218. static int dsi_display_pre_switch(struct dsi_display *display)
  6219. {
  6220. int rc = 0;
  6221. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6222. DSI_CORE_CLK, DSI_CLK_ON);
  6223. if (rc) {
  6224. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6225. display->name, rc);
  6226. goto error;
  6227. }
  6228. rc = dsi_display_ctrl_update(display);
  6229. if (rc) {
  6230. DSI_ERR("[%s] failed to update DSI controller, rc=%d\n",
  6231. display->name, rc);
  6232. goto error_ctrl_clk_off;
  6233. }
  6234. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6235. DSI_LINK_CLK, DSI_CLK_ON);
  6236. if (rc) {
  6237. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6238. display->name, rc);
  6239. goto error_ctrl_deinit;
  6240. }
  6241. goto error;
  6242. error_ctrl_deinit:
  6243. (void)dsi_display_ctrl_deinit(display);
  6244. error_ctrl_clk_off:
  6245. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6246. DSI_CORE_CLK, DSI_CLK_OFF);
  6247. error:
  6248. return rc;
  6249. }
  6250. static bool _dsi_display_validate_host_state(struct dsi_display *display)
  6251. {
  6252. int i;
  6253. struct dsi_display_ctrl *ctrl;
  6254. display_for_each_ctrl(i, display) {
  6255. ctrl = &display->ctrl[i];
  6256. if (!ctrl->ctrl)
  6257. continue;
  6258. if (!dsi_ctrl_validate_host_state(ctrl->ctrl))
  6259. return false;
  6260. }
  6261. return true;
  6262. }
  6263. static void dsi_display_handle_fifo_underflow(struct work_struct *work)
  6264. {
  6265. struct dsi_display *display = NULL;
  6266. display = container_of(work, struct dsi_display, fifo_underflow_work);
  6267. if (!display || !display->panel ||
  6268. atomic_read(&display->panel->esd_recovery_pending)) {
  6269. DSI_DEBUG("Invalid recovery use case\n");
  6270. return;
  6271. }
  6272. mutex_lock(&display->display_lock);
  6273. if (!_dsi_display_validate_host_state(display)) {
  6274. mutex_unlock(&display->display_lock);
  6275. return;
  6276. }
  6277. DSI_INFO("handle DSI FIFO underflow error\n");
  6278. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6279. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6280. DSI_ALL_CLKS, DSI_CLK_ON);
  6281. dsi_display_soft_reset(display);
  6282. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6283. DSI_ALL_CLKS, DSI_CLK_OFF);
  6284. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6285. mutex_unlock(&display->display_lock);
  6286. }
  6287. static void dsi_display_handle_fifo_overflow(struct work_struct *work)
  6288. {
  6289. struct dsi_display *display = NULL;
  6290. struct dsi_display_ctrl *ctrl;
  6291. int i, rc;
  6292. int mask = BIT(20); /* clock lane */
  6293. int (*cb_func)(void *event_usr_ptr,
  6294. uint32_t event_idx, uint32_t instance_idx,
  6295. uint32_t data0, uint32_t data1,
  6296. uint32_t data2, uint32_t data3);
  6297. void *data;
  6298. u32 version = 0;
  6299. display = container_of(work, struct dsi_display, fifo_overflow_work);
  6300. if (!display || !display->panel ||
  6301. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6302. atomic_read(&display->panel->esd_recovery_pending)) {
  6303. DSI_DEBUG("Invalid recovery use case\n");
  6304. return;
  6305. }
  6306. mutex_lock(&display->display_lock);
  6307. if (!_dsi_display_validate_host_state(display)) {
  6308. mutex_unlock(&display->display_lock);
  6309. return;
  6310. }
  6311. DSI_INFO("handle DSI FIFO overflow error\n");
  6312. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6313. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6314. DSI_ALL_CLKS, DSI_CLK_ON);
  6315. /*
  6316. * below recovery sequence is not applicable to
  6317. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6318. */
  6319. ctrl = &display->ctrl[display->clk_master_idx];
  6320. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6321. if (!version || (version < 0x20020001))
  6322. goto end;
  6323. /* reset ctrl and lanes */
  6324. display_for_each_ctrl(i, display) {
  6325. ctrl = &display->ctrl[i];
  6326. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6327. rc = dsi_phy_lane_reset(ctrl->phy);
  6328. }
  6329. /* wait for display line count to be in active area */
  6330. ctrl = &display->ctrl[display->clk_master_idx];
  6331. if (ctrl->ctrl->recovery_cb.event_cb) {
  6332. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6333. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6334. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6335. display->clk_master_idx, 0, 0, 0, 0);
  6336. if (rc < 0) {
  6337. DSI_DEBUG("sde callback failed\n");
  6338. goto end;
  6339. }
  6340. }
  6341. /* Enable Video mode for DSI controller */
  6342. display_for_each_ctrl(i, display) {
  6343. ctrl = &display->ctrl[i];
  6344. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6345. }
  6346. /*
  6347. * Add sufficient delay to make sure
  6348. * pixel transmission has started
  6349. */
  6350. udelay(200);
  6351. end:
  6352. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6353. DSI_ALL_CLKS, DSI_CLK_OFF);
  6354. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6355. mutex_unlock(&display->display_lock);
  6356. }
  6357. static void dsi_display_handle_lp_rx_timeout(struct work_struct *work)
  6358. {
  6359. struct dsi_display *display = NULL;
  6360. struct dsi_display_ctrl *ctrl;
  6361. int i, rc;
  6362. int mask = (BIT(20) | (0xF << 16)); /* clock lane and 4 data lane */
  6363. int (*cb_func)(void *event_usr_ptr,
  6364. uint32_t event_idx, uint32_t instance_idx,
  6365. uint32_t data0, uint32_t data1,
  6366. uint32_t data2, uint32_t data3);
  6367. void *data;
  6368. u32 version = 0;
  6369. display = container_of(work, struct dsi_display, lp_rx_timeout_work);
  6370. if (!display || !display->panel ||
  6371. (display->panel->panel_mode != DSI_OP_VIDEO_MODE) ||
  6372. atomic_read(&display->panel->esd_recovery_pending)) {
  6373. DSI_DEBUG("Invalid recovery use case\n");
  6374. return;
  6375. }
  6376. mutex_lock(&display->display_lock);
  6377. if (!_dsi_display_validate_host_state(display)) {
  6378. mutex_unlock(&display->display_lock);
  6379. return;
  6380. }
  6381. DSI_INFO("handle DSI LP RX Timeout error\n");
  6382. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6383. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6384. DSI_ALL_CLKS, DSI_CLK_ON);
  6385. /*
  6386. * below recovery sequence is not applicable to
  6387. * hw version 2.0.0, 2.1.0 and 2.2.0, so return early.
  6388. */
  6389. ctrl = &display->ctrl[display->clk_master_idx];
  6390. version = dsi_ctrl_get_hw_version(ctrl->ctrl);
  6391. if (!version || (version < 0x20020001))
  6392. goto end;
  6393. /* reset ctrl and lanes */
  6394. display_for_each_ctrl(i, display) {
  6395. ctrl = &display->ctrl[i];
  6396. rc = dsi_ctrl_reset(ctrl->ctrl, mask);
  6397. rc = dsi_phy_lane_reset(ctrl->phy);
  6398. }
  6399. ctrl = &display->ctrl[display->clk_master_idx];
  6400. if (ctrl->ctrl->recovery_cb.event_cb) {
  6401. cb_func = ctrl->ctrl->recovery_cb.event_cb;
  6402. data = ctrl->ctrl->recovery_cb.event_usr_ptr;
  6403. rc = cb_func(data, SDE_CONN_EVENT_VID_FIFO_OVERFLOW,
  6404. display->clk_master_idx, 0, 0, 0, 0);
  6405. if (rc < 0) {
  6406. DSI_DEBUG("Target is in suspend/shutdown\n");
  6407. goto end;
  6408. }
  6409. }
  6410. /* Enable Video mode for DSI controller */
  6411. display_for_each_ctrl(i, display) {
  6412. ctrl = &display->ctrl[i];
  6413. dsi_ctrl_vid_engine_en(ctrl->ctrl, true);
  6414. }
  6415. /*
  6416. * Add sufficient delay to make sure
  6417. * pixel transmission as started
  6418. */
  6419. udelay(200);
  6420. end:
  6421. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6422. DSI_ALL_CLKS, DSI_CLK_OFF);
  6423. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6424. mutex_unlock(&display->display_lock);
  6425. }
  6426. static int dsi_display_cb_error_handler(void *data,
  6427. uint32_t event_idx, uint32_t instance_idx,
  6428. uint32_t data0, uint32_t data1,
  6429. uint32_t data2, uint32_t data3)
  6430. {
  6431. struct dsi_display *display = data;
  6432. if (!display || !(display->err_workq))
  6433. return -EINVAL;
  6434. switch (event_idx) {
  6435. case DSI_FIFO_UNDERFLOW:
  6436. queue_work(display->err_workq, &display->fifo_underflow_work);
  6437. break;
  6438. case DSI_FIFO_OVERFLOW:
  6439. queue_work(display->err_workq, &display->fifo_overflow_work);
  6440. break;
  6441. case DSI_LP_Rx_TIMEOUT:
  6442. queue_work(display->err_workq, &display->lp_rx_timeout_work);
  6443. break;
  6444. default:
  6445. DSI_WARN("unhandled error interrupt: %d\n", event_idx);
  6446. break;
  6447. }
  6448. return 0;
  6449. }
  6450. static void dsi_display_register_error_handler(struct dsi_display *display)
  6451. {
  6452. int i = 0;
  6453. struct dsi_display_ctrl *ctrl;
  6454. struct dsi_event_cb_info event_info;
  6455. if (!display)
  6456. return;
  6457. display->err_workq = create_singlethread_workqueue("dsi_err_workq");
  6458. if (!display->err_workq) {
  6459. DSI_ERR("failed to create dsi workq!\n");
  6460. return;
  6461. }
  6462. INIT_WORK(&display->fifo_underflow_work,
  6463. dsi_display_handle_fifo_underflow);
  6464. INIT_WORK(&display->fifo_overflow_work,
  6465. dsi_display_handle_fifo_overflow);
  6466. INIT_WORK(&display->lp_rx_timeout_work,
  6467. dsi_display_handle_lp_rx_timeout);
  6468. memset(&event_info, 0, sizeof(event_info));
  6469. event_info.event_cb = dsi_display_cb_error_handler;
  6470. event_info.event_usr_ptr = display;
  6471. display_for_each_ctrl(i, display) {
  6472. ctrl = &display->ctrl[i];
  6473. ctrl->ctrl->irq_info.irq_err_cb = event_info;
  6474. }
  6475. }
  6476. static void dsi_display_unregister_error_handler(struct dsi_display *display)
  6477. {
  6478. int i = 0;
  6479. struct dsi_display_ctrl *ctrl;
  6480. if (!display)
  6481. return;
  6482. display_for_each_ctrl(i, display) {
  6483. ctrl = &display->ctrl[i];
  6484. memset(&ctrl->ctrl->irq_info.irq_err_cb,
  6485. 0, sizeof(struct dsi_event_cb_info));
  6486. }
  6487. if (display->err_workq) {
  6488. destroy_workqueue(display->err_workq);
  6489. display->err_workq = NULL;
  6490. }
  6491. }
  6492. int dsi_display_prepare(struct dsi_display *display)
  6493. {
  6494. int rc = 0;
  6495. struct dsi_display_mode *mode;
  6496. if (!display) {
  6497. DSI_ERR("Invalid params\n");
  6498. return -EINVAL;
  6499. }
  6500. if (!display->panel->cur_mode) {
  6501. DSI_ERR("no valid mode set for the display\n");
  6502. return -EINVAL;
  6503. }
  6504. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6505. mutex_lock(&display->display_lock);
  6506. display->hw_ownership = true;
  6507. mode = display->panel->cur_mode;
  6508. dsi_display_set_ctrl_esd_check_flag(display, false);
  6509. /* Set up ctrl isr before enabling core clk */
  6510. if (!display->trusted_vm_env)
  6511. dsi_display_ctrl_isr_configure(display, true);
  6512. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6513. if (display->is_cont_splash_enabled &&
  6514. display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6515. DSI_ERR("DMS not supported on first frame\n");
  6516. rc = -EINVAL;
  6517. goto error;
  6518. }
  6519. if (!is_skip_op_required(display)) {
  6520. /* update dsi ctrl for new mode */
  6521. rc = dsi_display_pre_switch(display);
  6522. if (rc)
  6523. DSI_ERR("[%s] panel pre-switch failed, rc=%d\n",
  6524. display->name, rc);
  6525. goto error;
  6526. }
  6527. }
  6528. if (!display->poms_pending &&
  6529. (!is_skip_op_required(display))) {
  6530. /*
  6531. * For continuous splash/trusted vm, we skip panel
  6532. * pre prepare since the regulator vote is already
  6533. * taken care in splash resource init
  6534. */
  6535. rc = dsi_panel_pre_prepare(display->panel);
  6536. if (rc) {
  6537. DSI_ERR("[%s] panel pre-prepare failed, rc=%d\n",
  6538. display->name, rc);
  6539. goto error;
  6540. }
  6541. }
  6542. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6543. DSI_CORE_CLK, DSI_CLK_ON);
  6544. if (rc) {
  6545. DSI_ERR("[%s] failed to enable DSI core clocks, rc=%d\n",
  6546. display->name, rc);
  6547. goto error_panel_post_unprep;
  6548. }
  6549. /*
  6550. * If ULPS during suspend feature is enabled, then DSI PHY was
  6551. * left on during suspend. In this case, we do not need to reset/init
  6552. * PHY. This would have already been done when the CORE clocks are
  6553. * turned on. However, if cont splash is disabled, the first time DSI
  6554. * is powered on, phy init needs to be done unconditionally.
  6555. */
  6556. if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) {
  6557. rc = dsi_display_phy_sw_reset(display);
  6558. if (rc) {
  6559. DSI_ERR("[%s] failed to reset phy, rc=%d\n",
  6560. display->name, rc);
  6561. goto error_ctrl_clk_off;
  6562. }
  6563. rc = dsi_display_phy_enable(display);
  6564. if (rc) {
  6565. DSI_ERR("[%s] failed to enable DSI PHY, rc=%d\n",
  6566. display->name, rc);
  6567. goto error_ctrl_clk_off;
  6568. }
  6569. }
  6570. rc = dsi_display_ctrl_init(display);
  6571. if (rc) {
  6572. DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
  6573. display->name, rc);
  6574. goto error_phy_disable;
  6575. }
  6576. /* Set up DSI ERROR event callback */
  6577. dsi_display_register_error_handler(display);
  6578. rc = dsi_display_ctrl_host_enable(display);
  6579. if (rc) {
  6580. DSI_ERR("[%s] failed to enable DSI host, rc=%d\n",
  6581. display->name, rc);
  6582. goto error_ctrl_deinit;
  6583. }
  6584. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  6585. DSI_LINK_CLK, DSI_CLK_ON);
  6586. if (rc) {
  6587. DSI_ERR("[%s] failed to enable DSI link clocks, rc=%d\n",
  6588. display->name, rc);
  6589. goto error_host_engine_off;
  6590. }
  6591. if (!is_skip_op_required(display)) {
  6592. /*
  6593. * For continuous splash/trusted vm, skip panel prepare and
  6594. * ctl reset since the pnael and ctrl is already in active
  6595. * state and panel on commands are not needed
  6596. */
  6597. rc = dsi_display_soft_reset(display);
  6598. if (rc) {
  6599. DSI_ERR("[%s] failed soft reset, rc=%d\n",
  6600. display->name, rc);
  6601. goto error_ctrl_link_off;
  6602. }
  6603. if (!display->poms_pending) {
  6604. rc = dsi_panel_prepare(display->panel);
  6605. if (rc) {
  6606. DSI_ERR("[%s] panel prepare failed, rc=%d\n",
  6607. display->name, rc);
  6608. goto error_ctrl_link_off;
  6609. }
  6610. }
  6611. }
  6612. goto error;
  6613. error_ctrl_link_off:
  6614. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6615. DSI_LINK_CLK, DSI_CLK_OFF);
  6616. error_host_engine_off:
  6617. (void)dsi_display_ctrl_host_disable(display);
  6618. error_ctrl_deinit:
  6619. (void)dsi_display_ctrl_deinit(display);
  6620. error_phy_disable:
  6621. (void)dsi_display_phy_disable(display);
  6622. error_ctrl_clk_off:
  6623. (void)dsi_display_clk_ctrl(display->dsi_clk_handle,
  6624. DSI_CORE_CLK, DSI_CLK_OFF);
  6625. error_panel_post_unprep:
  6626. (void)dsi_panel_post_unprepare(display->panel);
  6627. error:
  6628. mutex_unlock(&display->display_lock);
  6629. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6630. return rc;
  6631. }
  6632. static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
  6633. const struct dsi_display_ctrl *ctrl,
  6634. const struct msm_roi_list *req_rois,
  6635. struct dsi_rect *out_roi)
  6636. {
  6637. const struct dsi_rect *bounds = &ctrl->ctrl->mode_bounds;
  6638. struct dsi_display_mode *cur_mode;
  6639. struct msm_roi_caps *roi_caps;
  6640. struct dsi_rect req_roi = { 0 };
  6641. int rc = 0;
  6642. cur_mode = display->panel->cur_mode;
  6643. if (!cur_mode)
  6644. return 0;
  6645. roi_caps = &cur_mode->priv_info->roi_caps;
  6646. if (req_rois->num_rects > roi_caps->num_roi) {
  6647. DSI_ERR("request for %d rois greater than max %d\n",
  6648. req_rois->num_rects,
  6649. roi_caps->num_roi);
  6650. rc = -EINVAL;
  6651. goto exit;
  6652. }
  6653. /**
  6654. * if no rois, user wants to reset back to full resolution
  6655. * note: h_active is already divided by ctrl_count
  6656. */
  6657. if (!req_rois->num_rects) {
  6658. *out_roi = *bounds;
  6659. goto exit;
  6660. }
  6661. /* intersect with the bounds */
  6662. req_roi.x = req_rois->roi[0].x1;
  6663. req_roi.y = req_rois->roi[0].y1;
  6664. req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
  6665. req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
  6666. dsi_rect_intersect(&req_roi, bounds, out_roi);
  6667. exit:
  6668. /* adjust the ctrl origin to be top left within the ctrl */
  6669. out_roi->x = out_roi->x - bounds->x;
  6670. DSI_DEBUG("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out (%d,%d,%d,%d)\n",
  6671. ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
  6672. req_roi.x, req_roi.y, req_roi.w, req_roi.h,
  6673. bounds->x, bounds->y, bounds->w, bounds->h,
  6674. out_roi->x, out_roi->y, out_roi->w, out_roi->h);
  6675. return rc;
  6676. }
  6677. static int dsi_display_qsync(struct dsi_display *display, bool enable)
  6678. {
  6679. int i;
  6680. int rc = 0;
  6681. if (!display->panel->qsync_caps.qsync_min_fps) {
  6682. DSI_ERR("%s:ERROR: qsync set, but no fps\n", __func__);
  6683. return 0;
  6684. }
  6685. mutex_lock(&display->display_lock);
  6686. display_for_each_ctrl(i, display) {
  6687. if (enable) {
  6688. /* send the commands to enable qsync */
  6689. rc = dsi_panel_send_qsync_on_dcs(display->panel, i);
  6690. if (rc) {
  6691. DSI_ERR("fail qsync ON cmds rc:%d\n", rc);
  6692. goto exit;
  6693. }
  6694. } else {
  6695. /* send the commands to enable qsync */
  6696. rc = dsi_panel_send_qsync_off_dcs(display->panel, i);
  6697. if (rc) {
  6698. DSI_ERR("fail qsync OFF cmds rc:%d\n", rc);
  6699. goto exit;
  6700. }
  6701. }
  6702. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  6703. }
  6704. exit:
  6705. SDE_EVT32(enable, display->panel->qsync_caps.qsync_min_fps, rc);
  6706. mutex_unlock(&display->display_lock);
  6707. return rc;
  6708. }
  6709. static int dsi_display_set_roi(struct dsi_display *display,
  6710. struct msm_roi_list *rois)
  6711. {
  6712. struct dsi_display_mode *cur_mode;
  6713. struct msm_roi_caps *roi_caps;
  6714. int rc = 0;
  6715. int i;
  6716. if (!display || !rois || !display->panel)
  6717. return -EINVAL;
  6718. cur_mode = display->panel->cur_mode;
  6719. if (!cur_mode)
  6720. return 0;
  6721. roi_caps = &cur_mode->priv_info->roi_caps;
  6722. if (!roi_caps->enabled)
  6723. return 0;
  6724. display_for_each_ctrl(i, display) {
  6725. struct dsi_display_ctrl *ctrl = &display->ctrl[i];
  6726. struct dsi_rect ctrl_roi;
  6727. bool changed = false;
  6728. rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, &ctrl_roi);
  6729. if (rc) {
  6730. DSI_ERR("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
  6731. return rc;
  6732. }
  6733. rc = dsi_ctrl_set_roi(ctrl->ctrl, &ctrl_roi, &changed);
  6734. if (rc) {
  6735. DSI_ERR("dsi_ctrl_set_roi failed rc %d\n", rc);
  6736. return rc;
  6737. }
  6738. if (!changed)
  6739. continue;
  6740. /* send the new roi to the panel via dcs commands */
  6741. rc = dsi_panel_send_roi_dcs(display->panel, i, &ctrl_roi);
  6742. if (rc) {
  6743. DSI_ERR("dsi_panel_set_roi failed rc %d\n", rc);
  6744. return rc;
  6745. }
  6746. /* re-program the ctrl with the timing based on the new roi */
  6747. rc = dsi_ctrl_timing_setup(ctrl->ctrl);
  6748. if (rc) {
  6749. DSI_ERR("dsi_ctrl_setup failed rc %d\n", rc);
  6750. return rc;
  6751. }
  6752. }
  6753. return rc;
  6754. }
  6755. int dsi_display_pre_kickoff(struct drm_connector *connector,
  6756. struct dsi_display *display,
  6757. struct msm_display_kickoff_params *params)
  6758. {
  6759. int rc = 0, ret = 0;
  6760. int i;
  6761. /* check and setup MISR */
  6762. if (display->misr_enable)
  6763. _dsi_display_setup_misr(display);
  6764. /* dynamic DSI clock setting */
  6765. if (atomic_read(&display->clkrate_change_pending)) {
  6766. mutex_lock(&display->display_lock);
  6767. /*
  6768. * acquire panel_lock to make sure no commands are in progress
  6769. */
  6770. dsi_panel_acquire_panel_lock(display->panel);
  6771. /*
  6772. * Wait for DSI command engine not to be busy sending data
  6773. * from display engine.
  6774. * If waiting fails, return "rc" instead of below "ret" so as
  6775. * not to impact DRM commit. The clock updating would be
  6776. * deferred to the next DRM commit.
  6777. */
  6778. display_for_each_ctrl(i, display) {
  6779. struct dsi_ctrl *ctrl = display->ctrl[i].ctrl;
  6780. ret = dsi_ctrl_wait_for_cmd_mode_mdp_idle(ctrl);
  6781. if (ret)
  6782. goto wait_failure;
  6783. }
  6784. /*
  6785. * Don't check the return value so as not to impact DRM commit
  6786. * when error occurs.
  6787. */
  6788. (void)dsi_display_force_update_dsi_clk(display);
  6789. wait_failure:
  6790. /* release panel_lock */
  6791. dsi_panel_release_panel_lock(display->panel);
  6792. mutex_unlock(&display->display_lock);
  6793. }
  6794. if (!ret)
  6795. rc = dsi_display_set_roi(display, params->rois);
  6796. return rc;
  6797. }
  6798. int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
  6799. {
  6800. int rc = 0;
  6801. if (!display || !display->panel) {
  6802. DSI_ERR("Invalid params\n");
  6803. return -EINVAL;
  6804. }
  6805. if (!display->panel->cur_mode) {
  6806. DSI_ERR("no valid mode set for the display\n");
  6807. return -EINVAL;
  6808. }
  6809. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6810. rc = dsi_display_vid_engine_enable(display);
  6811. if (rc) {
  6812. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6813. display->name, rc);
  6814. goto error_out;
  6815. }
  6816. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6817. rc = dsi_display_cmd_engine_enable(display);
  6818. if (rc) {
  6819. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6820. display->name, rc);
  6821. goto error_out;
  6822. }
  6823. } else {
  6824. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6825. rc = -EINVAL;
  6826. }
  6827. error_out:
  6828. return rc;
  6829. }
  6830. int dsi_display_pre_commit(void *display,
  6831. struct msm_display_conn_params *params)
  6832. {
  6833. bool enable = false;
  6834. int rc = 0;
  6835. if (!display || !params) {
  6836. pr_err("Invalid params\n");
  6837. return -EINVAL;
  6838. }
  6839. if (params->qsync_update) {
  6840. enable = (params->qsync_mode > 0) ? true : false;
  6841. rc = dsi_display_qsync(display, enable);
  6842. if (rc)
  6843. pr_err("%s failed to send qsync commands\n",
  6844. __func__);
  6845. SDE_EVT32(params->qsync_mode, rc);
  6846. }
  6847. return rc;
  6848. }
  6849. static void dsi_display_panel_id_notification(struct dsi_display *display)
  6850. {
  6851. if (display->panel_id != ~0x0 &&
  6852. display->ctrl[0].ctrl->panel_id_cb.event_cb) {
  6853. display->ctrl[0].ctrl->panel_id_cb.event_cb(
  6854. display->ctrl[0].ctrl->panel_id_cb.event_usr_ptr,
  6855. display->ctrl[0].ctrl->panel_id_cb.event_idx,
  6856. 0, ((display->panel_id & 0xffffffff00000000) >> 32),
  6857. (display->panel_id & 0xffffffff), 0, 0);
  6858. }
  6859. }
  6860. int dsi_display_enable(struct dsi_display *display)
  6861. {
  6862. int rc = 0;
  6863. struct dsi_display_mode *mode;
  6864. if (!display || !display->panel) {
  6865. DSI_ERR("Invalid params\n");
  6866. return -EINVAL;
  6867. }
  6868. if (!display->panel->cur_mode) {
  6869. DSI_ERR("no valid mode set for the display\n");
  6870. return -EINVAL;
  6871. }
  6872. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  6873. /*
  6874. * Engine states and panel states are populated during splash
  6875. * resource/trusted vm and hence we return early
  6876. */
  6877. if (is_skip_op_required(display)) {
  6878. dsi_display_config_ctrl_for_cont_splash(display);
  6879. rc = dsi_display_splash_res_cleanup(display);
  6880. if (rc) {
  6881. DSI_ERR("Continuous splash res cleanup failed, rc=%d\n",
  6882. rc);
  6883. return -EINVAL;
  6884. }
  6885. display->panel->panel_initialized = true;
  6886. DSI_DEBUG("cont splash enabled, display enable not required\n");
  6887. dsi_display_panel_id_notification(display);
  6888. return 0;
  6889. }
  6890. mutex_lock(&display->display_lock);
  6891. mode = display->panel->cur_mode;
  6892. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6893. rc = dsi_panel_post_switch(display->panel);
  6894. if (rc) {
  6895. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6896. display->name, rc);
  6897. goto error;
  6898. }
  6899. } else if (!display->poms_pending) {
  6900. rc = dsi_panel_enable(display->panel);
  6901. if (rc) {
  6902. DSI_ERR("[%s] failed to enable DSI panel, rc=%d\n",
  6903. display->name, rc);
  6904. goto error;
  6905. }
  6906. }
  6907. dsi_display_panel_id_notification(display);
  6908. /* Block sending pps command if modeset is due to fps difference */
  6909. if ((mode->priv_info->dsc_enabled ||
  6910. mode->priv_info->vdc_enabled) &&
  6911. !(mode->dsi_mode_flags & DSI_MODE_FLAG_DMS_FPS)) {
  6912. rc = dsi_panel_update_pps(display->panel);
  6913. if (rc) {
  6914. DSI_ERR("[%s] panel pps cmd update failed, rc=%d\n",
  6915. display->name, rc);
  6916. goto error;
  6917. }
  6918. }
  6919. if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) {
  6920. rc = dsi_panel_switch(display->panel);
  6921. if (rc)
  6922. DSI_ERR("[%s] failed to switch DSI panel mode, rc=%d\n",
  6923. display->name, rc);
  6924. goto error;
  6925. }
  6926. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  6927. DSI_DEBUG("%s:enable video timing eng\n", __func__);
  6928. rc = dsi_display_vid_engine_enable(display);
  6929. if (rc) {
  6930. DSI_ERR("[%s]failed to enable DSI video engine, rc=%d\n",
  6931. display->name, rc);
  6932. goto error_disable_panel;
  6933. }
  6934. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  6935. DSI_DEBUG("%s:enable command timing eng\n", __func__);
  6936. rc = dsi_display_cmd_engine_enable(display);
  6937. if (rc) {
  6938. DSI_ERR("[%s]failed to enable DSI cmd engine, rc=%d\n",
  6939. display->name, rc);
  6940. goto error_disable_panel;
  6941. }
  6942. } else {
  6943. DSI_ERR("[%s] Invalid configuration\n", display->name);
  6944. rc = -EINVAL;
  6945. goto error_disable_panel;
  6946. }
  6947. goto error;
  6948. error_disable_panel:
  6949. (void)dsi_panel_disable(display->panel);
  6950. error:
  6951. mutex_unlock(&display->display_lock);
  6952. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  6953. return rc;
  6954. }
  6955. int dsi_display_post_enable(struct dsi_display *display)
  6956. {
  6957. int rc = 0;
  6958. if (!display) {
  6959. DSI_ERR("Invalid params\n");
  6960. return -EINVAL;
  6961. }
  6962. mutex_lock(&display->display_lock);
  6963. if (display->panel->cur_mode->dsi_mode_flags &
  6964. DSI_MODE_FLAG_POMS_TO_CMD) {
  6965. dsi_panel_switch_cmd_mode_in(display->panel);
  6966. } else if (display->panel->cur_mode->dsi_mode_flags &
  6967. DSI_MODE_FLAG_POMS_TO_VID)
  6968. dsi_panel_switch_video_mode_in(display->panel);
  6969. else {
  6970. rc = dsi_panel_post_enable(display->panel);
  6971. if (rc)
  6972. DSI_ERR("[%s] panel post-enable failed, rc=%d\n",
  6973. display->name, rc);
  6974. }
  6975. /* remove the clk vote for CMD mode panels */
  6976. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6977. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6978. DSI_ALL_CLKS, DSI_CLK_OFF);
  6979. mutex_unlock(&display->display_lock);
  6980. return rc;
  6981. }
  6982. int dsi_display_pre_disable(struct dsi_display *display)
  6983. {
  6984. int rc = 0;
  6985. if (!display) {
  6986. DSI_ERR("Invalid params\n");
  6987. return -EINVAL;
  6988. }
  6989. mutex_lock(&display->display_lock);
  6990. /* enable the clk vote for CMD mode panels */
  6991. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6992. dsi_display_clk_ctrl(display->dsi_clk_handle,
  6993. DSI_ALL_CLKS, DSI_CLK_ON);
  6994. if (display->poms_pending) {
  6995. if (display->config.panel_mode == DSI_OP_CMD_MODE)
  6996. dsi_panel_switch_cmd_mode_out(display->panel);
  6997. if (display->config.panel_mode == DSI_OP_VIDEO_MODE)
  6998. dsi_panel_switch_video_mode_out(display->panel);
  6999. } else {
  7000. rc = dsi_panel_pre_disable(display->panel);
  7001. if (rc)
  7002. DSI_ERR("[%s] panel pre-disable failed, rc=%d\n",
  7003. display->name, rc);
  7004. }
  7005. mutex_unlock(&display->display_lock);
  7006. return rc;
  7007. }
  7008. static void dsi_display_handle_poms_te(struct work_struct *work)
  7009. {
  7010. struct dsi_display *display = NULL;
  7011. struct delayed_work *dw = to_delayed_work(work);
  7012. struct mipi_dsi_device *dsi = NULL;
  7013. struct dsi_panel *panel = NULL;
  7014. int rc = 0;
  7015. display = container_of(dw, struct dsi_display, poms_te_work);
  7016. if (!display || !display->panel) {
  7017. DSI_ERR("Invalid params\n");
  7018. return;
  7019. }
  7020. panel = display->panel;
  7021. mutex_lock(&panel->panel_lock);
  7022. if (!dsi_panel_initialized(panel)) {
  7023. rc = -EINVAL;
  7024. goto error;
  7025. }
  7026. dsi = &panel->mipi_device;
  7027. rc = mipi_dsi_dcs_set_tear_off(dsi);
  7028. error:
  7029. mutex_unlock(&panel->panel_lock);
  7030. if (rc < 0)
  7031. DSI_ERR("failed to set tear off\n");
  7032. }
  7033. int dsi_display_disable(struct dsi_display *display)
  7034. {
  7035. int rc = 0;
  7036. if (!display) {
  7037. DSI_ERR("Invalid params\n");
  7038. return -EINVAL;
  7039. }
  7040. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7041. mutex_lock(&display->display_lock);
  7042. /* cancel delayed work */
  7043. if (display->poms_pending &&
  7044. display->panel->poms_align_vsync)
  7045. cancel_delayed_work_sync(&display->poms_te_work);
  7046. rc = dsi_display_wake_up(display);
  7047. if (rc)
  7048. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7049. display->name, rc);
  7050. if (display->config.panel_mode == DSI_OP_VIDEO_MODE) {
  7051. rc = dsi_display_vid_engine_disable(display);
  7052. if (rc)
  7053. DSI_ERR("[%s]failed to disable DSI vid engine, rc=%d\n",
  7054. display->name, rc);
  7055. } else if (display->config.panel_mode == DSI_OP_CMD_MODE) {
  7056. /**
  7057. * On POMS request , disable panel TE through
  7058. * delayed work queue.
  7059. */
  7060. if (display->poms_pending &&
  7061. display->panel->poms_align_vsync) {
  7062. INIT_DELAYED_WORK(&display->poms_te_work,
  7063. dsi_display_handle_poms_te);
  7064. queue_delayed_work(system_wq,
  7065. &display->poms_te_work,
  7066. msecs_to_jiffies(100));
  7067. }
  7068. rc = dsi_display_cmd_engine_disable(display);
  7069. if (rc)
  7070. DSI_ERR("[%s]failed to disable DSI cmd engine, rc=%d\n",
  7071. display->name, rc);
  7072. } else {
  7073. DSI_ERR("[%s] Invalid configuration\n", display->name);
  7074. rc = -EINVAL;
  7075. }
  7076. if (!display->poms_pending && !is_skip_op_required(display)) {
  7077. rc = dsi_panel_disable(display->panel);
  7078. if (rc)
  7079. DSI_ERR("[%s] failed to disable DSI panel, rc=%d\n",
  7080. display->name, rc);
  7081. }
  7082. if (is_skip_op_required(display)) {
  7083. /* applicable only for trusted vm */
  7084. display->panel->panel_initialized = false;
  7085. display->panel->power_mode = SDE_MODE_DPMS_OFF;
  7086. }
  7087. mutex_unlock(&display->display_lock);
  7088. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7089. return rc;
  7090. }
  7091. int dsi_display_update_pps(char *pps_cmd, void *disp)
  7092. {
  7093. struct dsi_display *display;
  7094. if (pps_cmd == NULL || disp == NULL) {
  7095. DSI_ERR("Invalid parameter\n");
  7096. return -EINVAL;
  7097. }
  7098. display = disp;
  7099. mutex_lock(&display->display_lock);
  7100. memcpy(display->panel->dce_pps_cmd, pps_cmd, DSI_CMD_PPS_SIZE);
  7101. mutex_unlock(&display->display_lock);
  7102. return 0;
  7103. }
  7104. int dsi_display_update_dyn_bit_clk(struct dsi_display *display,
  7105. struct dsi_display_mode *mode)
  7106. {
  7107. struct dsi_dyn_clk_caps *dyn_clk_caps;
  7108. struct dsi_host_common_cfg *host_cfg;
  7109. int bpp, lanes = 0;
  7110. if (!display || !mode) {
  7111. DSI_ERR("invalid arguments\n");
  7112. return -EINVAL;
  7113. }
  7114. dyn_clk_caps = &(display->panel->dyn_clk_caps);
  7115. if (!dyn_clk_caps->dyn_clk_support) {
  7116. DSI_DEBUG("dynamic bit clock support not enabled\n");
  7117. return 0;
  7118. } else if (!display->dyn_bit_clk_pending) {
  7119. DSI_DEBUG("dynamic bit clock rate not updated\n");
  7120. return 0;
  7121. } else if (!display->dyn_bit_clk) {
  7122. DSI_DEBUG("dynamic bit clock rate cleared\n");
  7123. return 0;
  7124. } else if (display->dyn_bit_clk < mode->priv_info->min_dsi_clk_hz) {
  7125. DSI_ERR("dynamic bit clock rate %llu smaller than minimum value:%llu\n",
  7126. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz);
  7127. return -EINVAL;
  7128. }
  7129. /* update mode clk rate with user value */
  7130. mode->timing.clk_rate_hz = display->dyn_bit_clk;
  7131. mode->priv_info->clk_rate_hz = display->dyn_bit_clk;
  7132. host_cfg = &(display->panel->host_config);
  7133. bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format);
  7134. if (host_cfg->data_lanes & DSI_DATA_LANE_0)
  7135. lanes++;
  7136. if (host_cfg->data_lanes & DSI_DATA_LANE_1)
  7137. lanes++;
  7138. if (host_cfg->data_lanes & DSI_DATA_LANE_2)
  7139. lanes++;
  7140. if (host_cfg->data_lanes & DSI_DATA_LANE_3)
  7141. lanes++;
  7142. dsi_display_adjust_mode_timing(display, mode, lanes, bpp);
  7143. /* adjust pixel clock based on dynamic bit clock */
  7144. mode->pixel_clk_khz = div_u64(mode->timing.clk_rate_hz * lanes, bpp);
  7145. do_div(mode->pixel_clk_khz, 1000);
  7146. mode->pixel_clk_khz *= display->ctrl_count;
  7147. SDE_EVT32(display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, mode->pixel_clk_khz);
  7148. DSI_DEBUG("dynamic bit clk:%u, min dsi clk:%llu, lanes:%d, bpp:%d, pck:%d Khz\n",
  7149. display->dyn_bit_clk, mode->priv_info->min_dsi_clk_hz, lanes, bpp,
  7150. mode->pixel_clk_khz);
  7151. display->dyn_bit_clk_pending = false;
  7152. return 0;
  7153. }
  7154. int dsi_display_dump_clks_state(struct dsi_display *display)
  7155. {
  7156. int rc = 0;
  7157. if (!display) {
  7158. DSI_ERR("invalid display argument\n");
  7159. return -EINVAL;
  7160. }
  7161. if (!display->clk_mngr) {
  7162. DSI_ERR("invalid clk manager\n");
  7163. return -EINVAL;
  7164. }
  7165. if (!display->dsi_clk_handle || !display->mdp_clk_handle) {
  7166. DSI_ERR("invalid clk handles\n");
  7167. return -EINVAL;
  7168. }
  7169. mutex_lock(&display->display_lock);
  7170. rc = dsi_display_dump_clk_handle_state(display->dsi_clk_handle);
  7171. if (rc) {
  7172. DSI_ERR("failed to dump dsi clock state\n");
  7173. goto end;
  7174. }
  7175. rc = dsi_display_dump_clk_handle_state(display->mdp_clk_handle);
  7176. if (rc) {
  7177. DSI_ERR("failed to dump mdp clock state\n");
  7178. goto end;
  7179. }
  7180. end:
  7181. mutex_unlock(&display->display_lock);
  7182. return rc;
  7183. }
  7184. int dsi_display_unprepare(struct dsi_display *display)
  7185. {
  7186. int rc = 0;
  7187. if (!display) {
  7188. DSI_ERR("Invalid params\n");
  7189. return -EINVAL;
  7190. }
  7191. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  7192. mutex_lock(&display->display_lock);
  7193. rc = dsi_display_wake_up(display);
  7194. if (rc)
  7195. DSI_ERR("[%s] display wake up failed, rc=%d\n",
  7196. display->name, rc);
  7197. if (!display->poms_pending && !is_skip_op_required(display)) {
  7198. rc = dsi_panel_unprepare(display->panel);
  7199. if (rc)
  7200. DSI_ERR("[%s] panel unprepare failed, rc=%d\n",
  7201. display->name, rc);
  7202. }
  7203. rc = dsi_display_ctrl_host_disable(display);
  7204. if (rc)
  7205. DSI_ERR("[%s] failed to disable DSI host, rc=%d\n",
  7206. display->name, rc);
  7207. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7208. DSI_LINK_CLK, DSI_CLK_OFF);
  7209. if (rc)
  7210. DSI_ERR("[%s] failed to disable Link clocks, rc=%d\n",
  7211. display->name, rc);
  7212. rc = dsi_display_ctrl_deinit(display);
  7213. if (rc)
  7214. DSI_ERR("[%s] failed to deinit controller, rc=%d\n",
  7215. display->name, rc);
  7216. if (!display->panel->ulps_suspend_enabled) {
  7217. rc = dsi_display_phy_disable(display);
  7218. if (rc)
  7219. DSI_ERR("[%s] failed to disable DSI PHY, rc=%d\n",
  7220. display->name, rc);
  7221. }
  7222. rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
  7223. DSI_CORE_CLK, DSI_CLK_OFF);
  7224. if (rc)
  7225. DSI_ERR("[%s] failed to disable DSI clocks, rc=%d\n",
  7226. display->name, rc);
  7227. /* destrory dsi isr set up */
  7228. dsi_display_ctrl_isr_configure(display, false);
  7229. if (!display->poms_pending && !is_skip_op_required(display)) {
  7230. rc = dsi_panel_post_unprepare(display->panel);
  7231. if (rc)
  7232. DSI_ERR("[%s] panel post-unprepare failed, rc=%d\n",
  7233. display->name, rc);
  7234. }
  7235. display->hw_ownership = false;
  7236. mutex_unlock(&display->display_lock);
  7237. /* Free up DSI ERROR event callback */
  7238. dsi_display_unregister_error_handler(display);
  7239. SDE_EVT32(SDE_EVTLOG_FUNC_EXIT);
  7240. return rc;
  7241. }
  7242. void __init dsi_display_register(void)
  7243. {
  7244. dsi_phy_drv_register();
  7245. dsi_ctrl_drv_register();
  7246. dsi_display_parse_boot_display_selection();
  7247. platform_driver_register(&dsi_display_driver);
  7248. }
  7249. void __exit dsi_display_unregister(void)
  7250. {
  7251. platform_driver_unregister(&dsi_display_driver);
  7252. dsi_ctrl_drv_unregister();
  7253. dsi_phy_drv_unregister();
  7254. }
  7255. module_param_string(dsi_display0, dsi_display_primary, MAX_CMDLINE_PARAM_LEN,
  7256. 0600);
  7257. MODULE_PARM_DESC(dsi_display0,
  7258. "msm_drm.dsi_display0=<display node>:<configX> where <display node> is 'primary dsi display node name' and <configX> where x represents index in the topology list");
  7259. module_param_string(dsi_display1, dsi_display_secondary, MAX_CMDLINE_PARAM_LEN,
  7260. 0600);
  7261. MODULE_PARM_DESC(dsi_display1,
  7262. "msm_drm.dsi_display1=<display node>:<configX> where <display node> is 'secondary dsi display node name' and <configX> where x represents index in the topology list");