kona.c 222 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  69. enum {
  70. TDM_0 = 0,
  71. TDM_1,
  72. TDM_2,
  73. TDM_3,
  74. TDM_4,
  75. TDM_5,
  76. TDM_6,
  77. TDM_7,
  78. TDM_PORT_MAX,
  79. };
  80. enum {
  81. TDM_PRI = 0,
  82. TDM_SEC,
  83. TDM_TERT,
  84. TDM_QUAT,
  85. TDM_QUIN,
  86. TDM_SEN,
  87. TDM_INTERFACE_MAX,
  88. };
  89. enum {
  90. PRIM_AUX_PCM = 0,
  91. SEC_AUX_PCM,
  92. TERT_AUX_PCM,
  93. QUAT_AUX_PCM,
  94. QUIN_AUX_PCM,
  95. SEN_AUX_PCM,
  96. AUX_PCM_MAX,
  97. };
  98. enum {
  99. PRIM_MI2S = 0,
  100. SEC_MI2S,
  101. TERT_MI2S,
  102. QUAT_MI2S,
  103. QUIN_MI2S,
  104. SEN_MI2S,
  105. MI2S_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_RX_0 = 0,
  109. WSA_CDC_DMA_RX_1,
  110. RX_CDC_DMA_RX_0,
  111. RX_CDC_DMA_RX_1,
  112. RX_CDC_DMA_RX_2,
  113. RX_CDC_DMA_RX_3,
  114. RX_CDC_DMA_RX_5,
  115. CDC_DMA_RX_MAX,
  116. };
  117. enum {
  118. WSA_CDC_DMA_TX_0 = 0,
  119. WSA_CDC_DMA_TX_1,
  120. WSA_CDC_DMA_TX_2,
  121. TX_CDC_DMA_TX_0,
  122. TX_CDC_DMA_TX_3,
  123. TX_CDC_DMA_TX_4,
  124. VA_CDC_DMA_TX_0,
  125. VA_CDC_DMA_TX_1,
  126. VA_CDC_DMA_TX_2,
  127. CDC_DMA_TX_MAX,
  128. };
  129. enum {
  130. SLIM_RX_7 = 0,
  131. SLIM_RX_MAX,
  132. };
  133. enum {
  134. SLIM_TX_7 = 0,
  135. SLIM_TX_8,
  136. SLIM_TX_MAX,
  137. };
  138. enum {
  139. AFE_LOOPBACK_TX_IDX = 0,
  140. AFE_LOOPBACK_TX_IDX_MAX,
  141. };
  142. struct msm_asoc_mach_data {
  143. struct snd_info_entry *codec_root;
  144. int usbc_en2_gpio; /* used by gpio driver API */
  145. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  146. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  147. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  148. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  149. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  150. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  151. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  152. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  153. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  154. bool is_afe_config_done;
  155. struct device_node *fsa_handle;
  156. };
  157. struct tdm_port {
  158. u32 mode;
  159. u32 channel;
  160. };
  161. enum {
  162. EXT_DISP_RX_IDX_DP = 0,
  163. EXT_DISP_RX_IDX_MAX,
  164. };
  165. struct msm_wsa881x_dev_info {
  166. struct device_node *of_node;
  167. u32 index;
  168. };
  169. struct aux_codec_dev_info {
  170. struct device_node *of_node;
  171. u32 index;
  172. };
  173. struct dev_config {
  174. u32 sample_rate;
  175. u32 bit_format;
  176. u32 channels;
  177. };
  178. /* Default configuration of slimbus channels */
  179. static struct dev_config slim_rx_cfg[] = {
  180. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  181. };
  182. static struct dev_config slim_tx_cfg[] = {
  183. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  184. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  185. };
  186. /* Default configuration of external display BE */
  187. static struct dev_config ext_disp_rx_cfg[] = {
  188. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  189. };
  190. static struct dev_config usb_rx_cfg = {
  191. .sample_rate = SAMPLING_RATE_48KHZ,
  192. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  193. .channels = 2,
  194. };
  195. static struct dev_config usb_tx_cfg = {
  196. .sample_rate = SAMPLING_RATE_48KHZ,
  197. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  198. .channels = 1,
  199. };
  200. static struct dev_config proxy_rx_cfg = {
  201. .sample_rate = SAMPLING_RATE_48KHZ,
  202. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  203. .channels = 2,
  204. };
  205. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  206. {
  207. AFE_API_VERSION_I2S_CONFIG,
  208. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  209. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  210. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  211. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  212. 0,
  213. },
  214. {
  215. AFE_API_VERSION_I2S_CONFIG,
  216. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  217. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  218. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  219. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  220. 0,
  221. },
  222. {
  223. AFE_API_VERSION_I2S_CONFIG,
  224. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  225. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  226. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  227. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  228. 0,
  229. },
  230. {
  231. AFE_API_VERSION_I2S_CONFIG,
  232. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  233. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  234. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  235. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  236. 0,
  237. },
  238. {
  239. AFE_API_VERSION_I2S_CONFIG,
  240. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  241. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  242. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  243. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  244. 0,
  245. },
  246. {
  247. AFE_API_VERSION_I2S_CONFIG,
  248. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  249. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  250. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  251. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  252. 0,
  253. },
  254. };
  255. struct mi2s_conf {
  256. struct mutex lock;
  257. u32 ref_cnt;
  258. u32 msm_is_mi2s_master;
  259. };
  260. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  261. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  262. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  263. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  264. };
  265. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  266. /* Default configuration of TDM channels */
  267. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  268. { /* PRI TDM */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  277. },
  278. { /* SEC TDM */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  287. },
  288. { /* TERT TDM */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  297. },
  298. { /* QUAT TDM */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  307. },
  308. { /* QUIN TDM */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  317. },
  318. { /* SEN TDM */
  319. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  320. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  327. },
  328. };
  329. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  330. { /* PRI TDM */
  331. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  332. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  333. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  334. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  335. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  336. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  337. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  338. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  339. },
  340. { /* SEC TDM */
  341. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  342. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  343. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  344. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  345. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  346. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  347. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  348. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  349. },
  350. { /* TERT TDM */
  351. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  352. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  353. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  354. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  355. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  356. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  357. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  358. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  359. },
  360. { /* QUAT TDM */
  361. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  362. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  363. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  364. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  365. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  366. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  367. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  368. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  369. },
  370. { /* QUIN TDM */
  371. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  372. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  373. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  374. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  375. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  376. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  377. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  378. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  379. },
  380. { /* SEN TDM */
  381. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  382. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  383. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  384. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  385. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  386. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  387. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  388. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  389. },
  390. };
  391. /* Default configuration of AUX PCM channels */
  392. static struct dev_config aux_pcm_rx_cfg[] = {
  393. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. };
  400. static struct dev_config aux_pcm_tx_cfg[] = {
  401. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  405. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  406. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  407. };
  408. /* Default configuration of MI2S channels */
  409. static struct dev_config mi2s_rx_cfg[] = {
  410. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  411. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  412. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  413. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  414. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  415. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  416. };
  417. static struct dev_config mi2s_tx_cfg[] = {
  418. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  419. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  420. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  421. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  422. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  423. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  424. };
  425. /* Default configuration of Codec DMA Interface RX */
  426. static struct dev_config cdc_dma_rx_cfg[] = {
  427. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  428. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  429. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  430. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  431. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  432. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  433. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  434. };
  435. /* Default configuration of Codec DMA Interface TX */
  436. static struct dev_config cdc_dma_tx_cfg[] = {
  437. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  438. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  439. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  440. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  441. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  442. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  443. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  444. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  445. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  446. };
  447. static struct dev_config afe_loopback_tx_cfg[] = {
  448. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  449. };
  450. static int msm_vi_feed_tx_ch = 2;
  451. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  452. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  453. "S32_LE"};
  454. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  455. "Six", "Seven", "Eight"};
  456. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  457. "KHZ_16", "KHZ_22P05",
  458. "KHZ_32", "KHZ_44P1", "KHZ_48",
  459. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  460. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  461. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  462. "Five", "Six", "Seven",
  463. "Eight"};
  464. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  465. "KHZ_48", "KHZ_176P4",
  466. "KHZ_352P8"};
  467. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  468. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  469. "Five", "Six", "Seven", "Eight"};
  470. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  471. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  472. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  473. "KHZ_48", "KHZ_96", "KHZ_192"};
  474. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  475. "Five", "Six", "Seven",
  476. "Eight"};
  477. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  478. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  479. "Five", "Six", "Seven",
  480. "Eight"};
  481. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  482. "KHZ_16", "KHZ_22P05",
  483. "KHZ_32", "KHZ_44P1", "KHZ_48",
  484. "KHZ_88P2", "KHZ_96",
  485. "KHZ_176P4", "KHZ_192",
  486. "KHZ_352P8", "KHZ_384"};
  487. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  488. "S24_3LE"};
  489. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  490. "KHZ_192", "KHZ_32", "KHZ_44P1",
  491. "KHZ_88P2", "KHZ_176P4"};
  492. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  493. "KHZ_44P1", "KHZ_48",
  494. "KHZ_88P2", "KHZ_96"};
  495. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  496. "KHZ_44P1", "KHZ_48",
  497. "KHZ_88P2", "KHZ_96"};
  498. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  499. "KHZ_44P1", "KHZ_48",
  500. "KHZ_88P2", "KHZ_96"};
  501. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  502. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  588. cdc_dma_sample_rate_text);
  589. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  590. cdc_dma_sample_rate_text);
  591. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  592. cdc_dma_sample_rate_text);
  593. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  594. cdc_dma_sample_rate_text);
  595. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  596. cdc_dma_sample_rate_text);
  597. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  598. cdc_dma_sample_rate_text);
  599. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  600. cdc_dma_sample_rate_text);
  601. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  602. cdc_dma_sample_rate_text);
  603. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  604. cdc_dma_sample_rate_text);
  605. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  606. cdc_dma_sample_rate_text);
  607. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  608. cdc_dma_sample_rate_text);
  609. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  610. cdc_dma_sample_rate_text);
  611. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  612. cdc_dma_sample_rate_text);
  613. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  614. cdc_dma_sample_rate_text);
  615. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  616. cdc_dma_sample_rate_text);
  617. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  618. cdc_dma_sample_rate_text);
  619. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  620. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  621. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  622. ext_disp_sample_rate_text);
  623. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  624. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  625. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  626. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  627. static bool is_initial_boot;
  628. static bool codec_reg_done;
  629. static struct snd_soc_aux_dev *msm_aux_dev;
  630. static struct snd_soc_codec_conf *msm_codec_conf;
  631. static struct snd_soc_card snd_soc_card_kona_msm;
  632. static int dmic_0_1_gpio_cnt;
  633. static int dmic_2_3_gpio_cnt;
  634. static int dmic_4_5_gpio_cnt;
  635. static void *def_wcd_mbhc_cal(void);
  636. /*
  637. * Need to report LINEIN
  638. * if R/L channel impedance is larger than 5K ohm
  639. */
  640. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  641. .read_fw_bin = false,
  642. .calibration = NULL,
  643. .detect_extn_cable = true,
  644. .mono_stero_detection = false,
  645. .swap_gnd_mic = NULL,
  646. .hs_ext_micbias = true,
  647. .key_code[0] = KEY_MEDIA,
  648. .key_code[1] = KEY_VOICECOMMAND,
  649. .key_code[2] = KEY_VOLUMEUP,
  650. .key_code[3] = KEY_VOLUMEDOWN,
  651. .key_code[4] = 0,
  652. .key_code[5] = 0,
  653. .key_code[6] = 0,
  654. .key_code[7] = 0,
  655. .linein_th = 5000,
  656. .moisture_en = false,
  657. .mbhc_micbias = MIC_BIAS_2,
  658. .anc_micbias = MIC_BIAS_2,
  659. .enable_anc_mic_detect = false,
  660. .moisture_duty_cycle_en = true,
  661. };
  662. static inline int param_is_mask(int p)
  663. {
  664. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  665. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  666. }
  667. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  668. int n)
  669. {
  670. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  671. }
  672. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  673. unsigned int bit)
  674. {
  675. if (bit >= SNDRV_MASK_MAX)
  676. return;
  677. if (param_is_mask(n)) {
  678. struct snd_mask *m = param_to_mask(p, n);
  679. m->bits[0] = 0;
  680. m->bits[1] = 0;
  681. m->bits[bit >> 5] |= (1 << (bit & 31));
  682. }
  683. }
  684. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  685. struct snd_ctl_elem_value *ucontrol)
  686. {
  687. int sample_rate_val = 0;
  688. switch (usb_rx_cfg.sample_rate) {
  689. case SAMPLING_RATE_384KHZ:
  690. sample_rate_val = 12;
  691. break;
  692. case SAMPLING_RATE_352P8KHZ:
  693. sample_rate_val = 11;
  694. break;
  695. case SAMPLING_RATE_192KHZ:
  696. sample_rate_val = 10;
  697. break;
  698. case SAMPLING_RATE_176P4KHZ:
  699. sample_rate_val = 9;
  700. break;
  701. case SAMPLING_RATE_96KHZ:
  702. sample_rate_val = 8;
  703. break;
  704. case SAMPLING_RATE_88P2KHZ:
  705. sample_rate_val = 7;
  706. break;
  707. case SAMPLING_RATE_48KHZ:
  708. sample_rate_val = 6;
  709. break;
  710. case SAMPLING_RATE_44P1KHZ:
  711. sample_rate_val = 5;
  712. break;
  713. case SAMPLING_RATE_32KHZ:
  714. sample_rate_val = 4;
  715. break;
  716. case SAMPLING_RATE_22P05KHZ:
  717. sample_rate_val = 3;
  718. break;
  719. case SAMPLING_RATE_16KHZ:
  720. sample_rate_val = 2;
  721. break;
  722. case SAMPLING_RATE_11P025KHZ:
  723. sample_rate_val = 1;
  724. break;
  725. case SAMPLING_RATE_8KHZ:
  726. default:
  727. sample_rate_val = 0;
  728. break;
  729. }
  730. ucontrol->value.integer.value[0] = sample_rate_val;
  731. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  732. usb_rx_cfg.sample_rate);
  733. return 0;
  734. }
  735. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  736. struct snd_ctl_elem_value *ucontrol)
  737. {
  738. switch (ucontrol->value.integer.value[0]) {
  739. case 12:
  740. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  741. break;
  742. case 11:
  743. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  744. break;
  745. case 10:
  746. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  747. break;
  748. case 9:
  749. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  750. break;
  751. case 8:
  752. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  753. break;
  754. case 7:
  755. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  756. break;
  757. case 6:
  758. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  759. break;
  760. case 5:
  761. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  762. break;
  763. case 4:
  764. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  765. break;
  766. case 3:
  767. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  768. break;
  769. case 2:
  770. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  771. break;
  772. case 1:
  773. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  774. break;
  775. case 0:
  776. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  777. break;
  778. default:
  779. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  780. break;
  781. }
  782. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  783. __func__, ucontrol->value.integer.value[0],
  784. usb_rx_cfg.sample_rate);
  785. return 0;
  786. }
  787. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  788. struct snd_ctl_elem_value *ucontrol)
  789. {
  790. int sample_rate_val = 0;
  791. switch (usb_tx_cfg.sample_rate) {
  792. case SAMPLING_RATE_384KHZ:
  793. sample_rate_val = 12;
  794. break;
  795. case SAMPLING_RATE_352P8KHZ:
  796. sample_rate_val = 11;
  797. break;
  798. case SAMPLING_RATE_192KHZ:
  799. sample_rate_val = 10;
  800. break;
  801. case SAMPLING_RATE_176P4KHZ:
  802. sample_rate_val = 9;
  803. break;
  804. case SAMPLING_RATE_96KHZ:
  805. sample_rate_val = 8;
  806. break;
  807. case SAMPLING_RATE_88P2KHZ:
  808. sample_rate_val = 7;
  809. break;
  810. case SAMPLING_RATE_48KHZ:
  811. sample_rate_val = 6;
  812. break;
  813. case SAMPLING_RATE_44P1KHZ:
  814. sample_rate_val = 5;
  815. break;
  816. case SAMPLING_RATE_32KHZ:
  817. sample_rate_val = 4;
  818. break;
  819. case SAMPLING_RATE_22P05KHZ:
  820. sample_rate_val = 3;
  821. break;
  822. case SAMPLING_RATE_16KHZ:
  823. sample_rate_val = 2;
  824. break;
  825. case SAMPLING_RATE_11P025KHZ:
  826. sample_rate_val = 1;
  827. break;
  828. case SAMPLING_RATE_8KHZ:
  829. sample_rate_val = 0;
  830. break;
  831. default:
  832. sample_rate_val = 6;
  833. break;
  834. }
  835. ucontrol->value.integer.value[0] = sample_rate_val;
  836. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  837. usb_tx_cfg.sample_rate);
  838. return 0;
  839. }
  840. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  841. struct snd_ctl_elem_value *ucontrol)
  842. {
  843. switch (ucontrol->value.integer.value[0]) {
  844. case 12:
  845. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  846. break;
  847. case 11:
  848. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  849. break;
  850. case 10:
  851. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  852. break;
  853. case 9:
  854. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  855. break;
  856. case 8:
  857. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  858. break;
  859. case 7:
  860. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  861. break;
  862. case 6:
  863. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  864. break;
  865. case 5:
  866. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  867. break;
  868. case 4:
  869. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  870. break;
  871. case 3:
  872. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  873. break;
  874. case 2:
  875. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  876. break;
  877. case 1:
  878. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  879. break;
  880. case 0:
  881. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  882. break;
  883. default:
  884. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  885. break;
  886. }
  887. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  888. __func__, ucontrol->value.integer.value[0],
  889. usb_tx_cfg.sample_rate);
  890. return 0;
  891. }
  892. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  893. struct snd_ctl_elem_value *ucontrol)
  894. {
  895. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  896. afe_loopback_tx_cfg[0].channels);
  897. ucontrol->value.enumerated.item[0] =
  898. afe_loopback_tx_cfg[0].channels - 1;
  899. return 0;
  900. }
  901. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  902. struct snd_ctl_elem_value *ucontrol)
  903. {
  904. afe_loopback_tx_cfg[0].channels =
  905. ucontrol->value.enumerated.item[0] + 1;
  906. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  907. afe_loopback_tx_cfg[0].channels);
  908. return 1;
  909. }
  910. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  911. struct snd_ctl_elem_value *ucontrol)
  912. {
  913. switch (usb_rx_cfg.bit_format) {
  914. case SNDRV_PCM_FORMAT_S32_LE:
  915. ucontrol->value.integer.value[0] = 3;
  916. break;
  917. case SNDRV_PCM_FORMAT_S24_3LE:
  918. ucontrol->value.integer.value[0] = 2;
  919. break;
  920. case SNDRV_PCM_FORMAT_S24_LE:
  921. ucontrol->value.integer.value[0] = 1;
  922. break;
  923. case SNDRV_PCM_FORMAT_S16_LE:
  924. default:
  925. ucontrol->value.integer.value[0] = 0;
  926. break;
  927. }
  928. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  929. __func__, usb_rx_cfg.bit_format,
  930. ucontrol->value.integer.value[0]);
  931. return 0;
  932. }
  933. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  934. struct snd_ctl_elem_value *ucontrol)
  935. {
  936. int rc = 0;
  937. switch (ucontrol->value.integer.value[0]) {
  938. case 3:
  939. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  940. break;
  941. case 2:
  942. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  943. break;
  944. case 1:
  945. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  946. break;
  947. case 0:
  948. default:
  949. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  950. break;
  951. }
  952. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  953. __func__, usb_rx_cfg.bit_format,
  954. ucontrol->value.integer.value[0]);
  955. return rc;
  956. }
  957. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  958. struct snd_ctl_elem_value *ucontrol)
  959. {
  960. switch (usb_tx_cfg.bit_format) {
  961. case SNDRV_PCM_FORMAT_S32_LE:
  962. ucontrol->value.integer.value[0] = 3;
  963. break;
  964. case SNDRV_PCM_FORMAT_S24_3LE:
  965. ucontrol->value.integer.value[0] = 2;
  966. break;
  967. case SNDRV_PCM_FORMAT_S24_LE:
  968. ucontrol->value.integer.value[0] = 1;
  969. break;
  970. case SNDRV_PCM_FORMAT_S16_LE:
  971. default:
  972. ucontrol->value.integer.value[0] = 0;
  973. break;
  974. }
  975. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  976. __func__, usb_tx_cfg.bit_format,
  977. ucontrol->value.integer.value[0]);
  978. return 0;
  979. }
  980. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  981. struct snd_ctl_elem_value *ucontrol)
  982. {
  983. int rc = 0;
  984. switch (ucontrol->value.integer.value[0]) {
  985. case 3:
  986. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  987. break;
  988. case 2:
  989. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  990. break;
  991. case 1:
  992. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  993. break;
  994. case 0:
  995. default:
  996. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  997. break;
  998. }
  999. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1000. __func__, usb_tx_cfg.bit_format,
  1001. ucontrol->value.integer.value[0]);
  1002. return rc;
  1003. }
  1004. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1005. struct snd_ctl_elem_value *ucontrol)
  1006. {
  1007. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1008. usb_rx_cfg.channels);
  1009. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1010. return 0;
  1011. }
  1012. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1013. struct snd_ctl_elem_value *ucontrol)
  1014. {
  1015. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1016. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1017. return 1;
  1018. }
  1019. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1020. struct snd_ctl_elem_value *ucontrol)
  1021. {
  1022. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1023. usb_tx_cfg.channels);
  1024. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1025. return 0;
  1026. }
  1027. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1028. struct snd_ctl_elem_value *ucontrol)
  1029. {
  1030. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1031. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1032. return 1;
  1033. }
  1034. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1035. struct snd_ctl_elem_value *ucontrol)
  1036. {
  1037. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1038. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1039. ucontrol->value.integer.value[0]);
  1040. return 0;
  1041. }
  1042. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1043. struct snd_ctl_elem_value *ucontrol)
  1044. {
  1045. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1046. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1047. return 1;
  1048. }
  1049. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1050. {
  1051. int idx = 0;
  1052. if (strnstr(kcontrol->id.name, "Display Port RX",
  1053. sizeof("Display Port RX"))) {
  1054. idx = EXT_DISP_RX_IDX_DP;
  1055. } else {
  1056. pr_err("%s: unsupported BE: %s\n",
  1057. __func__, kcontrol->id.name);
  1058. idx = -EINVAL;
  1059. }
  1060. return idx;
  1061. }
  1062. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1063. struct snd_ctl_elem_value *ucontrol)
  1064. {
  1065. int idx = ext_disp_get_port_idx(kcontrol);
  1066. if (idx < 0)
  1067. return idx;
  1068. switch (ext_disp_rx_cfg[idx].bit_format) {
  1069. case SNDRV_PCM_FORMAT_S24_3LE:
  1070. ucontrol->value.integer.value[0] = 2;
  1071. break;
  1072. case SNDRV_PCM_FORMAT_S24_LE:
  1073. ucontrol->value.integer.value[0] = 1;
  1074. break;
  1075. case SNDRV_PCM_FORMAT_S16_LE:
  1076. default:
  1077. ucontrol->value.integer.value[0] = 0;
  1078. break;
  1079. }
  1080. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1081. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1082. ucontrol->value.integer.value[0]);
  1083. return 0;
  1084. }
  1085. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1086. struct snd_ctl_elem_value *ucontrol)
  1087. {
  1088. int idx = ext_disp_get_port_idx(kcontrol);
  1089. if (idx < 0)
  1090. return idx;
  1091. switch (ucontrol->value.integer.value[0]) {
  1092. case 2:
  1093. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1094. break;
  1095. case 1:
  1096. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1097. break;
  1098. case 0:
  1099. default:
  1100. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1101. break;
  1102. }
  1103. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1104. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1105. ucontrol->value.integer.value[0]);
  1106. return 0;
  1107. }
  1108. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1109. struct snd_ctl_elem_value *ucontrol)
  1110. {
  1111. int idx = ext_disp_get_port_idx(kcontrol);
  1112. if (idx < 0)
  1113. return idx;
  1114. ucontrol->value.integer.value[0] =
  1115. ext_disp_rx_cfg[idx].channels - 2;
  1116. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1117. idx, ext_disp_rx_cfg[idx].channels);
  1118. return 0;
  1119. }
  1120. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1121. struct snd_ctl_elem_value *ucontrol)
  1122. {
  1123. int idx = ext_disp_get_port_idx(kcontrol);
  1124. if (idx < 0)
  1125. return idx;
  1126. ext_disp_rx_cfg[idx].channels =
  1127. ucontrol->value.integer.value[0] + 2;
  1128. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1129. idx, ext_disp_rx_cfg[idx].channels);
  1130. return 1;
  1131. }
  1132. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1133. struct snd_ctl_elem_value *ucontrol)
  1134. {
  1135. int sample_rate_val;
  1136. int idx = ext_disp_get_port_idx(kcontrol);
  1137. if (idx < 0)
  1138. return idx;
  1139. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1140. case SAMPLING_RATE_176P4KHZ:
  1141. sample_rate_val = 6;
  1142. break;
  1143. case SAMPLING_RATE_88P2KHZ:
  1144. sample_rate_val = 5;
  1145. break;
  1146. case SAMPLING_RATE_44P1KHZ:
  1147. sample_rate_val = 4;
  1148. break;
  1149. case SAMPLING_RATE_32KHZ:
  1150. sample_rate_val = 3;
  1151. break;
  1152. case SAMPLING_RATE_192KHZ:
  1153. sample_rate_val = 2;
  1154. break;
  1155. case SAMPLING_RATE_96KHZ:
  1156. sample_rate_val = 1;
  1157. break;
  1158. case SAMPLING_RATE_48KHZ:
  1159. default:
  1160. sample_rate_val = 0;
  1161. break;
  1162. }
  1163. ucontrol->value.integer.value[0] = sample_rate_val;
  1164. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1165. idx, ext_disp_rx_cfg[idx].sample_rate);
  1166. return 0;
  1167. }
  1168. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1169. struct snd_ctl_elem_value *ucontrol)
  1170. {
  1171. int idx = ext_disp_get_port_idx(kcontrol);
  1172. if (idx < 0)
  1173. return idx;
  1174. switch (ucontrol->value.integer.value[0]) {
  1175. case 6:
  1176. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1177. break;
  1178. case 5:
  1179. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1180. break;
  1181. case 4:
  1182. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1183. break;
  1184. case 3:
  1185. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1186. break;
  1187. case 2:
  1188. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1189. break;
  1190. case 1:
  1191. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1192. break;
  1193. case 0:
  1194. default:
  1195. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1196. break;
  1197. }
  1198. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1199. __func__, ucontrol->value.integer.value[0], idx,
  1200. ext_disp_rx_cfg[idx].sample_rate);
  1201. return 0;
  1202. }
  1203. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1204. struct snd_ctl_elem_value *ucontrol)
  1205. {
  1206. pr_debug("%s: proxy_rx channels = %d\n",
  1207. __func__, proxy_rx_cfg.channels);
  1208. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1209. return 0;
  1210. }
  1211. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1212. struct snd_ctl_elem_value *ucontrol)
  1213. {
  1214. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1215. pr_debug("%s: proxy_rx channels = %d\n",
  1216. __func__, proxy_rx_cfg.channels);
  1217. return 1;
  1218. }
  1219. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1220. struct tdm_port *port)
  1221. {
  1222. if (port) {
  1223. if (strnstr(kcontrol->id.name, "PRI",
  1224. sizeof(kcontrol->id.name))) {
  1225. port->mode = TDM_PRI;
  1226. } else if (strnstr(kcontrol->id.name, "SEC",
  1227. sizeof(kcontrol->id.name))) {
  1228. port->mode = TDM_SEC;
  1229. } else if (strnstr(kcontrol->id.name, "TERT",
  1230. sizeof(kcontrol->id.name))) {
  1231. port->mode = TDM_TERT;
  1232. } else if (strnstr(kcontrol->id.name, "QUAT",
  1233. sizeof(kcontrol->id.name))) {
  1234. port->mode = TDM_QUAT;
  1235. } else if (strnstr(kcontrol->id.name, "QUIN",
  1236. sizeof(kcontrol->id.name))) {
  1237. port->mode = TDM_QUIN;
  1238. } else if (strnstr(kcontrol->id.name, "SEN",
  1239. sizeof(kcontrol->id.name))) {
  1240. port->mode = TDM_SEN;
  1241. } else {
  1242. pr_err("%s: unsupported mode in: %s\n",
  1243. __func__, kcontrol->id.name);
  1244. return -EINVAL;
  1245. }
  1246. if (strnstr(kcontrol->id.name, "RX_0",
  1247. sizeof(kcontrol->id.name)) ||
  1248. strnstr(kcontrol->id.name, "TX_0",
  1249. sizeof(kcontrol->id.name))) {
  1250. port->channel = TDM_0;
  1251. } else if (strnstr(kcontrol->id.name, "RX_1",
  1252. sizeof(kcontrol->id.name)) ||
  1253. strnstr(kcontrol->id.name, "TX_1",
  1254. sizeof(kcontrol->id.name))) {
  1255. port->channel = TDM_1;
  1256. } else if (strnstr(kcontrol->id.name, "RX_2",
  1257. sizeof(kcontrol->id.name)) ||
  1258. strnstr(kcontrol->id.name, "TX_2",
  1259. sizeof(kcontrol->id.name))) {
  1260. port->channel = TDM_2;
  1261. } else if (strnstr(kcontrol->id.name, "RX_3",
  1262. sizeof(kcontrol->id.name)) ||
  1263. strnstr(kcontrol->id.name, "TX_3",
  1264. sizeof(kcontrol->id.name))) {
  1265. port->channel = TDM_3;
  1266. } else if (strnstr(kcontrol->id.name, "RX_4",
  1267. sizeof(kcontrol->id.name)) ||
  1268. strnstr(kcontrol->id.name, "TX_4",
  1269. sizeof(kcontrol->id.name))) {
  1270. port->channel = TDM_4;
  1271. } else if (strnstr(kcontrol->id.name, "RX_5",
  1272. sizeof(kcontrol->id.name)) ||
  1273. strnstr(kcontrol->id.name, "TX_5",
  1274. sizeof(kcontrol->id.name))) {
  1275. port->channel = TDM_5;
  1276. } else if (strnstr(kcontrol->id.name, "RX_6",
  1277. sizeof(kcontrol->id.name)) ||
  1278. strnstr(kcontrol->id.name, "TX_6",
  1279. sizeof(kcontrol->id.name))) {
  1280. port->channel = TDM_6;
  1281. } else if (strnstr(kcontrol->id.name, "RX_7",
  1282. sizeof(kcontrol->id.name)) ||
  1283. strnstr(kcontrol->id.name, "TX_7",
  1284. sizeof(kcontrol->id.name))) {
  1285. port->channel = TDM_7;
  1286. } else {
  1287. pr_err("%s: unsupported channel in: %s\n",
  1288. __func__, kcontrol->id.name);
  1289. return -EINVAL;
  1290. }
  1291. } else {
  1292. return -EINVAL;
  1293. }
  1294. return 0;
  1295. }
  1296. static int tdm_get_sample_rate(int value)
  1297. {
  1298. int sample_rate = 0;
  1299. switch (value) {
  1300. case 0:
  1301. sample_rate = SAMPLING_RATE_8KHZ;
  1302. break;
  1303. case 1:
  1304. sample_rate = SAMPLING_RATE_16KHZ;
  1305. break;
  1306. case 2:
  1307. sample_rate = SAMPLING_RATE_32KHZ;
  1308. break;
  1309. case 3:
  1310. sample_rate = SAMPLING_RATE_48KHZ;
  1311. break;
  1312. case 4:
  1313. sample_rate = SAMPLING_RATE_176P4KHZ;
  1314. break;
  1315. case 5:
  1316. sample_rate = SAMPLING_RATE_352P8KHZ;
  1317. break;
  1318. default:
  1319. sample_rate = SAMPLING_RATE_48KHZ;
  1320. break;
  1321. }
  1322. return sample_rate;
  1323. }
  1324. static int tdm_get_sample_rate_val(int sample_rate)
  1325. {
  1326. int sample_rate_val = 0;
  1327. switch (sample_rate) {
  1328. case SAMPLING_RATE_8KHZ:
  1329. sample_rate_val = 0;
  1330. break;
  1331. case SAMPLING_RATE_16KHZ:
  1332. sample_rate_val = 1;
  1333. break;
  1334. case SAMPLING_RATE_32KHZ:
  1335. sample_rate_val = 2;
  1336. break;
  1337. case SAMPLING_RATE_48KHZ:
  1338. sample_rate_val = 3;
  1339. break;
  1340. case SAMPLING_RATE_176P4KHZ:
  1341. sample_rate_val = 4;
  1342. break;
  1343. case SAMPLING_RATE_352P8KHZ:
  1344. sample_rate_val = 5;
  1345. break;
  1346. default:
  1347. sample_rate_val = 3;
  1348. break;
  1349. }
  1350. return sample_rate_val;
  1351. }
  1352. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1353. struct snd_ctl_elem_value *ucontrol)
  1354. {
  1355. struct tdm_port port;
  1356. int ret = tdm_get_port_idx(kcontrol, &port);
  1357. if (ret) {
  1358. pr_err("%s: unsupported control: %s\n",
  1359. __func__, kcontrol->id.name);
  1360. } else {
  1361. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1362. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1363. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1364. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1365. ucontrol->value.enumerated.item[0]);
  1366. }
  1367. return ret;
  1368. }
  1369. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1370. struct snd_ctl_elem_value *ucontrol)
  1371. {
  1372. struct tdm_port port;
  1373. int ret = tdm_get_port_idx(kcontrol, &port);
  1374. if (ret) {
  1375. pr_err("%s: unsupported control: %s\n",
  1376. __func__, kcontrol->id.name);
  1377. } else {
  1378. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1379. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1380. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1381. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1382. ucontrol->value.enumerated.item[0]);
  1383. }
  1384. return ret;
  1385. }
  1386. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1387. struct snd_ctl_elem_value *ucontrol)
  1388. {
  1389. struct tdm_port port;
  1390. int ret = tdm_get_port_idx(kcontrol, &port);
  1391. if (ret) {
  1392. pr_err("%s: unsupported control: %s\n",
  1393. __func__, kcontrol->id.name);
  1394. } else {
  1395. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1396. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1397. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1398. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1399. ucontrol->value.enumerated.item[0]);
  1400. }
  1401. return ret;
  1402. }
  1403. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1404. struct snd_ctl_elem_value *ucontrol)
  1405. {
  1406. struct tdm_port port;
  1407. int ret = tdm_get_port_idx(kcontrol, &port);
  1408. if (ret) {
  1409. pr_err("%s: unsupported control: %s\n",
  1410. __func__, kcontrol->id.name);
  1411. } else {
  1412. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1413. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1414. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1415. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1416. ucontrol->value.enumerated.item[0]);
  1417. }
  1418. return ret;
  1419. }
  1420. static int tdm_get_format(int value)
  1421. {
  1422. int format = 0;
  1423. switch (value) {
  1424. case 0:
  1425. format = SNDRV_PCM_FORMAT_S16_LE;
  1426. break;
  1427. case 1:
  1428. format = SNDRV_PCM_FORMAT_S24_LE;
  1429. break;
  1430. case 2:
  1431. format = SNDRV_PCM_FORMAT_S32_LE;
  1432. break;
  1433. default:
  1434. format = SNDRV_PCM_FORMAT_S16_LE;
  1435. break;
  1436. }
  1437. return format;
  1438. }
  1439. static int tdm_get_format_val(int format)
  1440. {
  1441. int value = 0;
  1442. switch (format) {
  1443. case SNDRV_PCM_FORMAT_S16_LE:
  1444. value = 0;
  1445. break;
  1446. case SNDRV_PCM_FORMAT_S24_LE:
  1447. value = 1;
  1448. break;
  1449. case SNDRV_PCM_FORMAT_S32_LE:
  1450. value = 2;
  1451. break;
  1452. default:
  1453. value = 0;
  1454. break;
  1455. }
  1456. return value;
  1457. }
  1458. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1459. struct snd_ctl_elem_value *ucontrol)
  1460. {
  1461. struct tdm_port port;
  1462. int ret = tdm_get_port_idx(kcontrol, &port);
  1463. if (ret) {
  1464. pr_err("%s: unsupported control: %s\n",
  1465. __func__, kcontrol->id.name);
  1466. } else {
  1467. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1468. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1469. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1470. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1471. ucontrol->value.enumerated.item[0]);
  1472. }
  1473. return ret;
  1474. }
  1475. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1476. struct snd_ctl_elem_value *ucontrol)
  1477. {
  1478. struct tdm_port port;
  1479. int ret = tdm_get_port_idx(kcontrol, &port);
  1480. if (ret) {
  1481. pr_err("%s: unsupported control: %s\n",
  1482. __func__, kcontrol->id.name);
  1483. } else {
  1484. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1485. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1486. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1487. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1488. ucontrol->value.enumerated.item[0]);
  1489. }
  1490. return ret;
  1491. }
  1492. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1493. struct snd_ctl_elem_value *ucontrol)
  1494. {
  1495. struct tdm_port port;
  1496. int ret = tdm_get_port_idx(kcontrol, &port);
  1497. if (ret) {
  1498. pr_err("%s: unsupported control: %s\n",
  1499. __func__, kcontrol->id.name);
  1500. } else {
  1501. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1502. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1503. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1504. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1505. ucontrol->value.enumerated.item[0]);
  1506. }
  1507. return ret;
  1508. }
  1509. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1510. struct snd_ctl_elem_value *ucontrol)
  1511. {
  1512. struct tdm_port port;
  1513. int ret = tdm_get_port_idx(kcontrol, &port);
  1514. if (ret) {
  1515. pr_err("%s: unsupported control: %s\n",
  1516. __func__, kcontrol->id.name);
  1517. } else {
  1518. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1519. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1520. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1521. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1522. ucontrol->value.enumerated.item[0]);
  1523. }
  1524. return ret;
  1525. }
  1526. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1527. struct snd_ctl_elem_value *ucontrol)
  1528. {
  1529. struct tdm_port port;
  1530. int ret = tdm_get_port_idx(kcontrol, &port);
  1531. if (ret) {
  1532. pr_err("%s: unsupported control: %s\n",
  1533. __func__, kcontrol->id.name);
  1534. } else {
  1535. ucontrol->value.enumerated.item[0] =
  1536. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1537. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1538. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1539. ucontrol->value.enumerated.item[0]);
  1540. }
  1541. return ret;
  1542. }
  1543. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1544. struct snd_ctl_elem_value *ucontrol)
  1545. {
  1546. struct tdm_port port;
  1547. int ret = tdm_get_port_idx(kcontrol, &port);
  1548. if (ret) {
  1549. pr_err("%s: unsupported control: %s\n",
  1550. __func__, kcontrol->id.name);
  1551. } else {
  1552. tdm_rx_cfg[port.mode][port.channel].channels =
  1553. ucontrol->value.enumerated.item[0] + 1;
  1554. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1555. tdm_rx_cfg[port.mode][port.channel].channels,
  1556. ucontrol->value.enumerated.item[0] + 1);
  1557. }
  1558. return ret;
  1559. }
  1560. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1561. struct snd_ctl_elem_value *ucontrol)
  1562. {
  1563. struct tdm_port port;
  1564. int ret = tdm_get_port_idx(kcontrol, &port);
  1565. if (ret) {
  1566. pr_err("%s: unsupported control: %s\n",
  1567. __func__, kcontrol->id.name);
  1568. } else {
  1569. ucontrol->value.enumerated.item[0] =
  1570. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1571. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1572. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1573. ucontrol->value.enumerated.item[0]);
  1574. }
  1575. return ret;
  1576. }
  1577. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1578. struct snd_ctl_elem_value *ucontrol)
  1579. {
  1580. struct tdm_port port;
  1581. int ret = tdm_get_port_idx(kcontrol, &port);
  1582. if (ret) {
  1583. pr_err("%s: unsupported control: %s\n",
  1584. __func__, kcontrol->id.name);
  1585. } else {
  1586. tdm_tx_cfg[port.mode][port.channel].channels =
  1587. ucontrol->value.enumerated.item[0] + 1;
  1588. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1589. tdm_tx_cfg[port.mode][port.channel].channels,
  1590. ucontrol->value.enumerated.item[0] + 1);
  1591. }
  1592. return ret;
  1593. }
  1594. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1595. {
  1596. int idx = 0;
  1597. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1598. sizeof("PRIM_AUX_PCM"))) {
  1599. idx = PRIM_AUX_PCM;
  1600. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1601. sizeof("SEC_AUX_PCM"))) {
  1602. idx = SEC_AUX_PCM;
  1603. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1604. sizeof("TERT_AUX_PCM"))) {
  1605. idx = TERT_AUX_PCM;
  1606. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1607. sizeof("QUAT_AUX_PCM"))) {
  1608. idx = QUAT_AUX_PCM;
  1609. } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  1610. sizeof("QUIN_AUX_PCM"))) {
  1611. idx = QUIN_AUX_PCM;
  1612. } else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  1613. sizeof("SEN_AUX_PCM"))) {
  1614. idx = SEN_AUX_PCM;
  1615. } else {
  1616. pr_err("%s: unsupported port: %s\n",
  1617. __func__, kcontrol->id.name);
  1618. idx = -EINVAL;
  1619. }
  1620. return idx;
  1621. }
  1622. static int aux_pcm_get_sample_rate(int value)
  1623. {
  1624. int sample_rate = 0;
  1625. switch (value) {
  1626. case 1:
  1627. sample_rate = SAMPLING_RATE_16KHZ;
  1628. break;
  1629. case 0:
  1630. default:
  1631. sample_rate = SAMPLING_RATE_8KHZ;
  1632. break;
  1633. }
  1634. return sample_rate;
  1635. }
  1636. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1637. {
  1638. int sample_rate_val = 0;
  1639. switch (sample_rate) {
  1640. case SAMPLING_RATE_16KHZ:
  1641. sample_rate_val = 1;
  1642. break;
  1643. case SAMPLING_RATE_8KHZ:
  1644. default:
  1645. sample_rate_val = 0;
  1646. break;
  1647. }
  1648. return sample_rate_val;
  1649. }
  1650. static int mi2s_auxpcm_get_format(int value)
  1651. {
  1652. int format = 0;
  1653. switch (value) {
  1654. case 0:
  1655. format = SNDRV_PCM_FORMAT_S16_LE;
  1656. break;
  1657. case 1:
  1658. format = SNDRV_PCM_FORMAT_S24_LE;
  1659. break;
  1660. case 2:
  1661. format = SNDRV_PCM_FORMAT_S24_3LE;
  1662. break;
  1663. case 3:
  1664. format = SNDRV_PCM_FORMAT_S32_LE;
  1665. break;
  1666. default:
  1667. format = SNDRV_PCM_FORMAT_S16_LE;
  1668. break;
  1669. }
  1670. return format;
  1671. }
  1672. static int mi2s_auxpcm_get_format_value(int format)
  1673. {
  1674. int value = 0;
  1675. switch (format) {
  1676. case SNDRV_PCM_FORMAT_S16_LE:
  1677. value = 0;
  1678. break;
  1679. case SNDRV_PCM_FORMAT_S24_LE:
  1680. value = 1;
  1681. break;
  1682. case SNDRV_PCM_FORMAT_S24_3LE:
  1683. value = 2;
  1684. break;
  1685. case SNDRV_PCM_FORMAT_S32_LE:
  1686. value = 3;
  1687. break;
  1688. default:
  1689. value = 0;
  1690. break;
  1691. }
  1692. return value;
  1693. }
  1694. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1695. struct snd_ctl_elem_value *ucontrol)
  1696. {
  1697. int idx = aux_pcm_get_port_idx(kcontrol);
  1698. if (idx < 0)
  1699. return idx;
  1700. ucontrol->value.enumerated.item[0] =
  1701. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1702. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1703. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1704. ucontrol->value.enumerated.item[0]);
  1705. return 0;
  1706. }
  1707. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1708. struct snd_ctl_elem_value *ucontrol)
  1709. {
  1710. int idx = aux_pcm_get_port_idx(kcontrol);
  1711. if (idx < 0)
  1712. return idx;
  1713. aux_pcm_rx_cfg[idx].sample_rate =
  1714. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1715. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1716. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1717. ucontrol->value.enumerated.item[0]);
  1718. return 0;
  1719. }
  1720. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1721. struct snd_ctl_elem_value *ucontrol)
  1722. {
  1723. int idx = aux_pcm_get_port_idx(kcontrol);
  1724. if (idx < 0)
  1725. return idx;
  1726. ucontrol->value.enumerated.item[0] =
  1727. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1728. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1729. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1730. ucontrol->value.enumerated.item[0]);
  1731. return 0;
  1732. }
  1733. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1734. struct snd_ctl_elem_value *ucontrol)
  1735. {
  1736. int idx = aux_pcm_get_port_idx(kcontrol);
  1737. if (idx < 0)
  1738. return idx;
  1739. aux_pcm_tx_cfg[idx].sample_rate =
  1740. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1741. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1742. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1743. ucontrol->value.enumerated.item[0]);
  1744. return 0;
  1745. }
  1746. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1747. struct snd_ctl_elem_value *ucontrol)
  1748. {
  1749. int idx = aux_pcm_get_port_idx(kcontrol);
  1750. if (idx < 0)
  1751. return idx;
  1752. ucontrol->value.enumerated.item[0] =
  1753. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1754. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1755. idx, aux_pcm_rx_cfg[idx].bit_format,
  1756. ucontrol->value.enumerated.item[0]);
  1757. return 0;
  1758. }
  1759. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1760. struct snd_ctl_elem_value *ucontrol)
  1761. {
  1762. int idx = aux_pcm_get_port_idx(kcontrol);
  1763. if (idx < 0)
  1764. return idx;
  1765. aux_pcm_rx_cfg[idx].bit_format =
  1766. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1767. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1768. idx, aux_pcm_rx_cfg[idx].bit_format,
  1769. ucontrol->value.enumerated.item[0]);
  1770. return 0;
  1771. }
  1772. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1773. struct snd_ctl_elem_value *ucontrol)
  1774. {
  1775. int idx = aux_pcm_get_port_idx(kcontrol);
  1776. if (idx < 0)
  1777. return idx;
  1778. ucontrol->value.enumerated.item[0] =
  1779. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1780. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1781. idx, aux_pcm_tx_cfg[idx].bit_format,
  1782. ucontrol->value.enumerated.item[0]);
  1783. return 0;
  1784. }
  1785. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1786. struct snd_ctl_elem_value *ucontrol)
  1787. {
  1788. int idx = aux_pcm_get_port_idx(kcontrol);
  1789. if (idx < 0)
  1790. return idx;
  1791. aux_pcm_tx_cfg[idx].bit_format =
  1792. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1793. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1794. idx, aux_pcm_tx_cfg[idx].bit_format,
  1795. ucontrol->value.enumerated.item[0]);
  1796. return 0;
  1797. }
  1798. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1799. {
  1800. int idx = 0;
  1801. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1802. sizeof("PRIM_MI2S_RX"))) {
  1803. idx = PRIM_MI2S;
  1804. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1805. sizeof("SEC_MI2S_RX"))) {
  1806. idx = SEC_MI2S;
  1807. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1808. sizeof("TERT_MI2S_RX"))) {
  1809. idx = TERT_MI2S;
  1810. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1811. sizeof("QUAT_MI2S_RX"))) {
  1812. idx = QUAT_MI2S;
  1813. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  1814. sizeof("QUIN_MI2S_RX"))) {
  1815. idx = QUIN_MI2S;
  1816. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  1817. sizeof("SEN_MI2S_RX"))) {
  1818. idx = SEN_MI2S;
  1819. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1820. sizeof("PRIM_MI2S_TX"))) {
  1821. idx = PRIM_MI2S;
  1822. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1823. sizeof("SEC_MI2S_TX"))) {
  1824. idx = SEC_MI2S;
  1825. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1826. sizeof("TERT_MI2S_TX"))) {
  1827. idx = TERT_MI2S;
  1828. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1829. sizeof("QUAT_MI2S_TX"))) {
  1830. idx = QUAT_MI2S;
  1831. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1832. sizeof("QUIN_MI2S_TX"))) {
  1833. idx = QUIN_MI2S;
  1834. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  1835. sizeof("SEN_MI2S_TX"))) {
  1836. idx = SEN_MI2S;
  1837. } else {
  1838. pr_err("%s: unsupported channel: %s\n",
  1839. __func__, kcontrol->id.name);
  1840. idx = -EINVAL;
  1841. }
  1842. return idx;
  1843. }
  1844. static int mi2s_get_sample_rate(int value)
  1845. {
  1846. int sample_rate = 0;
  1847. switch (value) {
  1848. case 0:
  1849. sample_rate = SAMPLING_RATE_8KHZ;
  1850. break;
  1851. case 1:
  1852. sample_rate = SAMPLING_RATE_11P025KHZ;
  1853. break;
  1854. case 2:
  1855. sample_rate = SAMPLING_RATE_16KHZ;
  1856. break;
  1857. case 3:
  1858. sample_rate = SAMPLING_RATE_22P05KHZ;
  1859. break;
  1860. case 4:
  1861. sample_rate = SAMPLING_RATE_32KHZ;
  1862. break;
  1863. case 5:
  1864. sample_rate = SAMPLING_RATE_44P1KHZ;
  1865. break;
  1866. case 6:
  1867. sample_rate = SAMPLING_RATE_48KHZ;
  1868. break;
  1869. case 7:
  1870. sample_rate = SAMPLING_RATE_96KHZ;
  1871. break;
  1872. case 8:
  1873. sample_rate = SAMPLING_RATE_192KHZ;
  1874. break;
  1875. default:
  1876. sample_rate = SAMPLING_RATE_48KHZ;
  1877. break;
  1878. }
  1879. return sample_rate;
  1880. }
  1881. static int mi2s_get_sample_rate_val(int sample_rate)
  1882. {
  1883. int sample_rate_val = 0;
  1884. switch (sample_rate) {
  1885. case SAMPLING_RATE_8KHZ:
  1886. sample_rate_val = 0;
  1887. break;
  1888. case SAMPLING_RATE_11P025KHZ:
  1889. sample_rate_val = 1;
  1890. break;
  1891. case SAMPLING_RATE_16KHZ:
  1892. sample_rate_val = 2;
  1893. break;
  1894. case SAMPLING_RATE_22P05KHZ:
  1895. sample_rate_val = 3;
  1896. break;
  1897. case SAMPLING_RATE_32KHZ:
  1898. sample_rate_val = 4;
  1899. break;
  1900. case SAMPLING_RATE_44P1KHZ:
  1901. sample_rate_val = 5;
  1902. break;
  1903. case SAMPLING_RATE_48KHZ:
  1904. sample_rate_val = 6;
  1905. break;
  1906. case SAMPLING_RATE_96KHZ:
  1907. sample_rate_val = 7;
  1908. break;
  1909. case SAMPLING_RATE_192KHZ:
  1910. sample_rate_val = 8;
  1911. break;
  1912. default:
  1913. sample_rate_val = 6;
  1914. break;
  1915. }
  1916. return sample_rate_val;
  1917. }
  1918. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1919. struct snd_ctl_elem_value *ucontrol)
  1920. {
  1921. int idx = mi2s_get_port_idx(kcontrol);
  1922. if (idx < 0)
  1923. return idx;
  1924. ucontrol->value.enumerated.item[0] =
  1925. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1926. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1927. idx, mi2s_rx_cfg[idx].sample_rate,
  1928. ucontrol->value.enumerated.item[0]);
  1929. return 0;
  1930. }
  1931. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1932. struct snd_ctl_elem_value *ucontrol)
  1933. {
  1934. int idx = mi2s_get_port_idx(kcontrol);
  1935. if (idx < 0)
  1936. return idx;
  1937. mi2s_rx_cfg[idx].sample_rate =
  1938. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1939. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1940. idx, mi2s_rx_cfg[idx].sample_rate,
  1941. ucontrol->value.enumerated.item[0]);
  1942. return 0;
  1943. }
  1944. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1945. struct snd_ctl_elem_value *ucontrol)
  1946. {
  1947. int idx = mi2s_get_port_idx(kcontrol);
  1948. if (idx < 0)
  1949. return idx;
  1950. ucontrol->value.enumerated.item[0] =
  1951. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1952. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1953. idx, mi2s_tx_cfg[idx].sample_rate,
  1954. ucontrol->value.enumerated.item[0]);
  1955. return 0;
  1956. }
  1957. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1958. struct snd_ctl_elem_value *ucontrol)
  1959. {
  1960. int idx = mi2s_get_port_idx(kcontrol);
  1961. if (idx < 0)
  1962. return idx;
  1963. mi2s_tx_cfg[idx].sample_rate =
  1964. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1965. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1966. idx, mi2s_tx_cfg[idx].sample_rate,
  1967. ucontrol->value.enumerated.item[0]);
  1968. return 0;
  1969. }
  1970. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1971. struct snd_ctl_elem_value *ucontrol)
  1972. {
  1973. int idx = mi2s_get_port_idx(kcontrol);
  1974. if (idx < 0)
  1975. return idx;
  1976. ucontrol->value.enumerated.item[0] =
  1977. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1978. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1979. idx, mi2s_rx_cfg[idx].bit_format,
  1980. ucontrol->value.enumerated.item[0]);
  1981. return 0;
  1982. }
  1983. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1984. struct snd_ctl_elem_value *ucontrol)
  1985. {
  1986. int idx = mi2s_get_port_idx(kcontrol);
  1987. if (idx < 0)
  1988. return idx;
  1989. mi2s_rx_cfg[idx].bit_format =
  1990. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1991. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1992. idx, mi2s_rx_cfg[idx].bit_format,
  1993. ucontrol->value.enumerated.item[0]);
  1994. return 0;
  1995. }
  1996. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1997. struct snd_ctl_elem_value *ucontrol)
  1998. {
  1999. int idx = mi2s_get_port_idx(kcontrol);
  2000. if (idx < 0)
  2001. return idx;
  2002. ucontrol->value.enumerated.item[0] =
  2003. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2004. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2005. idx, mi2s_tx_cfg[idx].bit_format,
  2006. ucontrol->value.enumerated.item[0]);
  2007. return 0;
  2008. }
  2009. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2010. struct snd_ctl_elem_value *ucontrol)
  2011. {
  2012. int idx = mi2s_get_port_idx(kcontrol);
  2013. if (idx < 0)
  2014. return idx;
  2015. mi2s_tx_cfg[idx].bit_format =
  2016. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2017. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2018. idx, mi2s_tx_cfg[idx].bit_format,
  2019. ucontrol->value.enumerated.item[0]);
  2020. return 0;
  2021. }
  2022. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2023. struct snd_ctl_elem_value *ucontrol)
  2024. {
  2025. int idx = mi2s_get_port_idx(kcontrol);
  2026. if (idx < 0)
  2027. return idx;
  2028. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2029. idx, mi2s_rx_cfg[idx].channels);
  2030. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2031. return 0;
  2032. }
  2033. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2034. struct snd_ctl_elem_value *ucontrol)
  2035. {
  2036. int idx = mi2s_get_port_idx(kcontrol);
  2037. if (idx < 0)
  2038. return idx;
  2039. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2040. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2041. idx, mi2s_rx_cfg[idx].channels);
  2042. return 1;
  2043. }
  2044. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2045. struct snd_ctl_elem_value *ucontrol)
  2046. {
  2047. int idx = mi2s_get_port_idx(kcontrol);
  2048. if (idx < 0)
  2049. return idx;
  2050. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2051. idx, mi2s_tx_cfg[idx].channels);
  2052. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2053. return 0;
  2054. }
  2055. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2056. struct snd_ctl_elem_value *ucontrol)
  2057. {
  2058. int idx = mi2s_get_port_idx(kcontrol);
  2059. if (idx < 0)
  2060. return idx;
  2061. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2062. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2063. idx, mi2s_tx_cfg[idx].channels);
  2064. return 1;
  2065. }
  2066. static int msm_get_port_id(int be_id)
  2067. {
  2068. int afe_port_id = 0;
  2069. switch (be_id) {
  2070. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2071. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2072. break;
  2073. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2074. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2075. break;
  2076. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2077. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2078. break;
  2079. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2080. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2081. break;
  2082. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2083. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2084. break;
  2085. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2086. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2087. break;
  2088. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2089. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2090. break;
  2091. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2092. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2093. break;
  2094. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2095. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2096. break;
  2097. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2098. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2099. break;
  2100. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  2101. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  2102. break;
  2103. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  2104. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  2105. break;
  2106. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2107. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2108. break;
  2109. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2110. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2111. break;
  2112. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2113. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2114. break;
  2115. default:
  2116. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2117. afe_port_id = -EINVAL;
  2118. }
  2119. return afe_port_id;
  2120. }
  2121. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2122. {
  2123. u32 bit_per_sample = 0;
  2124. switch (bit_format) {
  2125. case SNDRV_PCM_FORMAT_S32_LE:
  2126. case SNDRV_PCM_FORMAT_S24_3LE:
  2127. case SNDRV_PCM_FORMAT_S24_LE:
  2128. bit_per_sample = 32;
  2129. break;
  2130. case SNDRV_PCM_FORMAT_S16_LE:
  2131. default:
  2132. bit_per_sample = 16;
  2133. break;
  2134. }
  2135. return bit_per_sample;
  2136. }
  2137. static void update_mi2s_clk_val(int dai_id, int stream)
  2138. {
  2139. u32 bit_per_sample = 0;
  2140. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2141. bit_per_sample =
  2142. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2143. mi2s_clk[dai_id].clk_freq_in_hz =
  2144. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2145. } else {
  2146. bit_per_sample =
  2147. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2148. mi2s_clk[dai_id].clk_freq_in_hz =
  2149. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2150. }
  2151. }
  2152. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2153. {
  2154. int ret = 0;
  2155. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2156. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2157. int port_id = 0;
  2158. int index = cpu_dai->id;
  2159. port_id = msm_get_port_id(rtd->dai_link->id);
  2160. if (port_id < 0) {
  2161. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2162. ret = port_id;
  2163. goto err;
  2164. }
  2165. if (enable) {
  2166. update_mi2s_clk_val(index, substream->stream);
  2167. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2168. mi2s_clk[index].clk_freq_in_hz);
  2169. }
  2170. mi2s_clk[index].enable = enable;
  2171. ret = afe_set_lpass_clock_v2(port_id,
  2172. &mi2s_clk[index]);
  2173. if (ret < 0) {
  2174. dev_err(rtd->card->dev,
  2175. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2176. __func__, port_id, ret);
  2177. goto err;
  2178. }
  2179. err:
  2180. return ret;
  2181. }
  2182. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2183. {
  2184. int idx = 0;
  2185. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  2186. sizeof("WSA_CDC_DMA_RX_0")))
  2187. idx = WSA_CDC_DMA_RX_0;
  2188. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2189. sizeof("WSA_CDC_DMA_RX_0")))
  2190. idx = WSA_CDC_DMA_RX_1;
  2191. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2192. sizeof("RX_CDC_DMA_RX_0")))
  2193. idx = RX_CDC_DMA_RX_0;
  2194. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2195. sizeof("RX_CDC_DMA_RX_1")))
  2196. idx = RX_CDC_DMA_RX_1;
  2197. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2198. sizeof("RX_CDC_DMA_RX_2")))
  2199. idx = RX_CDC_DMA_RX_2;
  2200. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2201. sizeof("RX_CDC_DMA_RX_3")))
  2202. idx = RX_CDC_DMA_RX_3;
  2203. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2204. sizeof("RX_CDC_DMA_RX_5")))
  2205. idx = RX_CDC_DMA_RX_5;
  2206. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2207. sizeof("WSA_CDC_DMA_TX_0")))
  2208. idx = WSA_CDC_DMA_TX_0;
  2209. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2210. sizeof("WSA_CDC_DMA_TX_1")))
  2211. idx = WSA_CDC_DMA_TX_1;
  2212. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2213. sizeof("WSA_CDC_DMA_TX_2")))
  2214. idx = WSA_CDC_DMA_TX_2;
  2215. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2216. sizeof("TX_CDC_DMA_TX_0")))
  2217. idx = TX_CDC_DMA_TX_0;
  2218. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2219. sizeof("TX_CDC_DMA_TX_3")))
  2220. idx = TX_CDC_DMA_TX_3;
  2221. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2222. sizeof("TX_CDC_DMA_TX_4")))
  2223. idx = TX_CDC_DMA_TX_4;
  2224. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2225. sizeof("VA_CDC_DMA_TX_0")))
  2226. idx = VA_CDC_DMA_TX_0;
  2227. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2228. sizeof("VA_CDC_DMA_TX_1")))
  2229. idx = VA_CDC_DMA_TX_1;
  2230. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2231. sizeof("VA_CDC_DMA_TX_2")))
  2232. idx = VA_CDC_DMA_TX_2;
  2233. else {
  2234. pr_err("%s: unsupported channel: %s\n",
  2235. __func__, kcontrol->id.name);
  2236. return -EINVAL;
  2237. }
  2238. return idx;
  2239. }
  2240. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2241. struct snd_ctl_elem_value *ucontrol)
  2242. {
  2243. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2244. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2245. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2246. return ch_num;
  2247. }
  2248. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2249. cdc_dma_rx_cfg[ch_num].channels - 1);
  2250. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2251. return 0;
  2252. }
  2253. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2254. struct snd_ctl_elem_value *ucontrol)
  2255. {
  2256. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2257. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2258. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2259. return ch_num;
  2260. }
  2261. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2262. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2263. cdc_dma_rx_cfg[ch_num].channels);
  2264. return 1;
  2265. }
  2266. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2267. struct snd_ctl_elem_value *ucontrol)
  2268. {
  2269. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2270. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2271. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2272. return ch_num;
  2273. }
  2274. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2275. case SNDRV_PCM_FORMAT_S32_LE:
  2276. ucontrol->value.integer.value[0] = 3;
  2277. break;
  2278. case SNDRV_PCM_FORMAT_S24_3LE:
  2279. ucontrol->value.integer.value[0] = 2;
  2280. break;
  2281. case SNDRV_PCM_FORMAT_S24_LE:
  2282. ucontrol->value.integer.value[0] = 1;
  2283. break;
  2284. case SNDRV_PCM_FORMAT_S16_LE:
  2285. default:
  2286. ucontrol->value.integer.value[0] = 0;
  2287. break;
  2288. }
  2289. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2290. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2291. ucontrol->value.integer.value[0]);
  2292. return 0;
  2293. }
  2294. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2295. struct snd_ctl_elem_value *ucontrol)
  2296. {
  2297. int rc = 0;
  2298. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2299. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2300. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2301. return ch_num;
  2302. }
  2303. switch (ucontrol->value.integer.value[0]) {
  2304. case 3:
  2305. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2306. break;
  2307. case 2:
  2308. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2309. break;
  2310. case 1:
  2311. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2312. break;
  2313. case 0:
  2314. default:
  2315. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2316. break;
  2317. }
  2318. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2319. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2320. ucontrol->value.integer.value[0]);
  2321. return rc;
  2322. }
  2323. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2324. {
  2325. int sample_rate_val = 0;
  2326. switch (sample_rate) {
  2327. case SAMPLING_RATE_8KHZ:
  2328. sample_rate_val = 0;
  2329. break;
  2330. case SAMPLING_RATE_11P025KHZ:
  2331. sample_rate_val = 1;
  2332. break;
  2333. case SAMPLING_RATE_16KHZ:
  2334. sample_rate_val = 2;
  2335. break;
  2336. case SAMPLING_RATE_22P05KHZ:
  2337. sample_rate_val = 3;
  2338. break;
  2339. case SAMPLING_RATE_32KHZ:
  2340. sample_rate_val = 4;
  2341. break;
  2342. case SAMPLING_RATE_44P1KHZ:
  2343. sample_rate_val = 5;
  2344. break;
  2345. case SAMPLING_RATE_48KHZ:
  2346. sample_rate_val = 6;
  2347. break;
  2348. case SAMPLING_RATE_88P2KHZ:
  2349. sample_rate_val = 7;
  2350. break;
  2351. case SAMPLING_RATE_96KHZ:
  2352. sample_rate_val = 8;
  2353. break;
  2354. case SAMPLING_RATE_176P4KHZ:
  2355. sample_rate_val = 9;
  2356. break;
  2357. case SAMPLING_RATE_192KHZ:
  2358. sample_rate_val = 10;
  2359. break;
  2360. case SAMPLING_RATE_352P8KHZ:
  2361. sample_rate_val = 11;
  2362. break;
  2363. case SAMPLING_RATE_384KHZ:
  2364. sample_rate_val = 12;
  2365. break;
  2366. default:
  2367. sample_rate_val = 6;
  2368. break;
  2369. }
  2370. return sample_rate_val;
  2371. }
  2372. static int cdc_dma_get_sample_rate(int value)
  2373. {
  2374. int sample_rate = 0;
  2375. switch (value) {
  2376. case 0:
  2377. sample_rate = SAMPLING_RATE_8KHZ;
  2378. break;
  2379. case 1:
  2380. sample_rate = SAMPLING_RATE_11P025KHZ;
  2381. break;
  2382. case 2:
  2383. sample_rate = SAMPLING_RATE_16KHZ;
  2384. break;
  2385. case 3:
  2386. sample_rate = SAMPLING_RATE_22P05KHZ;
  2387. break;
  2388. case 4:
  2389. sample_rate = SAMPLING_RATE_32KHZ;
  2390. break;
  2391. case 5:
  2392. sample_rate = SAMPLING_RATE_44P1KHZ;
  2393. break;
  2394. case 6:
  2395. sample_rate = SAMPLING_RATE_48KHZ;
  2396. break;
  2397. case 7:
  2398. sample_rate = SAMPLING_RATE_88P2KHZ;
  2399. break;
  2400. case 8:
  2401. sample_rate = SAMPLING_RATE_96KHZ;
  2402. break;
  2403. case 9:
  2404. sample_rate = SAMPLING_RATE_176P4KHZ;
  2405. break;
  2406. case 10:
  2407. sample_rate = SAMPLING_RATE_192KHZ;
  2408. break;
  2409. case 11:
  2410. sample_rate = SAMPLING_RATE_352P8KHZ;
  2411. break;
  2412. case 12:
  2413. sample_rate = SAMPLING_RATE_384KHZ;
  2414. break;
  2415. default:
  2416. sample_rate = SAMPLING_RATE_48KHZ;
  2417. break;
  2418. }
  2419. return sample_rate;
  2420. }
  2421. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2422. struct snd_ctl_elem_value *ucontrol)
  2423. {
  2424. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2425. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2426. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2427. return ch_num;
  2428. }
  2429. ucontrol->value.enumerated.item[0] =
  2430. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2431. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2432. cdc_dma_rx_cfg[ch_num].sample_rate);
  2433. return 0;
  2434. }
  2435. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2436. struct snd_ctl_elem_value *ucontrol)
  2437. {
  2438. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2439. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2440. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2441. return ch_num;
  2442. }
  2443. cdc_dma_rx_cfg[ch_num].sample_rate =
  2444. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2445. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2446. __func__, ucontrol->value.enumerated.item[0],
  2447. cdc_dma_rx_cfg[ch_num].sample_rate);
  2448. return 0;
  2449. }
  2450. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2451. struct snd_ctl_elem_value *ucontrol)
  2452. {
  2453. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2454. if (ch_num < 0) {
  2455. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2456. return ch_num;
  2457. }
  2458. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2459. cdc_dma_tx_cfg[ch_num].channels);
  2460. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2461. return 0;
  2462. }
  2463. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2464. struct snd_ctl_elem_value *ucontrol)
  2465. {
  2466. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2467. if (ch_num < 0) {
  2468. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2469. return ch_num;
  2470. }
  2471. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2472. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2473. cdc_dma_tx_cfg[ch_num].channels);
  2474. return 1;
  2475. }
  2476. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2477. struct snd_ctl_elem_value *ucontrol)
  2478. {
  2479. int sample_rate_val;
  2480. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2481. if (ch_num < 0) {
  2482. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2483. return ch_num;
  2484. }
  2485. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2486. case SAMPLING_RATE_384KHZ:
  2487. sample_rate_val = 12;
  2488. break;
  2489. case SAMPLING_RATE_352P8KHZ:
  2490. sample_rate_val = 11;
  2491. break;
  2492. case SAMPLING_RATE_192KHZ:
  2493. sample_rate_val = 10;
  2494. break;
  2495. case SAMPLING_RATE_176P4KHZ:
  2496. sample_rate_val = 9;
  2497. break;
  2498. case SAMPLING_RATE_96KHZ:
  2499. sample_rate_val = 8;
  2500. break;
  2501. case SAMPLING_RATE_88P2KHZ:
  2502. sample_rate_val = 7;
  2503. break;
  2504. case SAMPLING_RATE_48KHZ:
  2505. sample_rate_val = 6;
  2506. break;
  2507. case SAMPLING_RATE_44P1KHZ:
  2508. sample_rate_val = 5;
  2509. break;
  2510. case SAMPLING_RATE_32KHZ:
  2511. sample_rate_val = 4;
  2512. break;
  2513. case SAMPLING_RATE_22P05KHZ:
  2514. sample_rate_val = 3;
  2515. break;
  2516. case SAMPLING_RATE_16KHZ:
  2517. sample_rate_val = 2;
  2518. break;
  2519. case SAMPLING_RATE_11P025KHZ:
  2520. sample_rate_val = 1;
  2521. break;
  2522. case SAMPLING_RATE_8KHZ:
  2523. sample_rate_val = 0;
  2524. break;
  2525. default:
  2526. sample_rate_val = 6;
  2527. break;
  2528. }
  2529. ucontrol->value.integer.value[0] = sample_rate_val;
  2530. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2531. cdc_dma_tx_cfg[ch_num].sample_rate);
  2532. return 0;
  2533. }
  2534. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2535. struct snd_ctl_elem_value *ucontrol)
  2536. {
  2537. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2538. if (ch_num < 0) {
  2539. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2540. return ch_num;
  2541. }
  2542. switch (ucontrol->value.integer.value[0]) {
  2543. case 12:
  2544. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2545. break;
  2546. case 11:
  2547. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2548. break;
  2549. case 10:
  2550. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2551. break;
  2552. case 9:
  2553. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2554. break;
  2555. case 8:
  2556. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2557. break;
  2558. case 7:
  2559. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2560. break;
  2561. case 6:
  2562. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2563. break;
  2564. case 5:
  2565. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2566. break;
  2567. case 4:
  2568. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2569. break;
  2570. case 3:
  2571. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2572. break;
  2573. case 2:
  2574. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2575. break;
  2576. case 1:
  2577. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2578. break;
  2579. case 0:
  2580. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2581. break;
  2582. default:
  2583. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2584. break;
  2585. }
  2586. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2587. __func__, ucontrol->value.integer.value[0],
  2588. cdc_dma_tx_cfg[ch_num].sample_rate);
  2589. return 0;
  2590. }
  2591. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2592. struct snd_ctl_elem_value *ucontrol)
  2593. {
  2594. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2595. if (ch_num < 0) {
  2596. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2597. return ch_num;
  2598. }
  2599. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2600. case SNDRV_PCM_FORMAT_S32_LE:
  2601. ucontrol->value.integer.value[0] = 3;
  2602. break;
  2603. case SNDRV_PCM_FORMAT_S24_3LE:
  2604. ucontrol->value.integer.value[0] = 2;
  2605. break;
  2606. case SNDRV_PCM_FORMAT_S24_LE:
  2607. ucontrol->value.integer.value[0] = 1;
  2608. break;
  2609. case SNDRV_PCM_FORMAT_S16_LE:
  2610. default:
  2611. ucontrol->value.integer.value[0] = 0;
  2612. break;
  2613. }
  2614. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2615. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2616. ucontrol->value.integer.value[0]);
  2617. return 0;
  2618. }
  2619. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2620. struct snd_ctl_elem_value *ucontrol)
  2621. {
  2622. int rc = 0;
  2623. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2624. if (ch_num < 0) {
  2625. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2626. return ch_num;
  2627. }
  2628. switch (ucontrol->value.integer.value[0]) {
  2629. case 3:
  2630. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2631. break;
  2632. case 2:
  2633. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2634. break;
  2635. case 1:
  2636. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2637. break;
  2638. case 0:
  2639. default:
  2640. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2641. break;
  2642. }
  2643. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2644. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2645. ucontrol->value.integer.value[0]);
  2646. return rc;
  2647. }
  2648. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2649. {
  2650. int idx = 0;
  2651. switch (be_id) {
  2652. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2653. idx = WSA_CDC_DMA_RX_0;
  2654. break;
  2655. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2656. idx = WSA_CDC_DMA_TX_0;
  2657. break;
  2658. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2659. idx = WSA_CDC_DMA_RX_1;
  2660. break;
  2661. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2662. idx = WSA_CDC_DMA_TX_1;
  2663. break;
  2664. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2665. idx = WSA_CDC_DMA_TX_2;
  2666. break;
  2667. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2668. idx = RX_CDC_DMA_RX_0;
  2669. break;
  2670. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2671. idx = RX_CDC_DMA_RX_1;
  2672. break;
  2673. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2674. idx = RX_CDC_DMA_RX_2;
  2675. break;
  2676. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2677. idx = RX_CDC_DMA_RX_3;
  2678. break;
  2679. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2680. idx = RX_CDC_DMA_RX_5;
  2681. break;
  2682. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2683. idx = TX_CDC_DMA_TX_0;
  2684. break;
  2685. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2686. idx = TX_CDC_DMA_TX_3;
  2687. break;
  2688. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2689. idx = TX_CDC_DMA_TX_4;
  2690. break;
  2691. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2692. idx = VA_CDC_DMA_TX_0;
  2693. break;
  2694. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2695. idx = VA_CDC_DMA_TX_1;
  2696. break;
  2697. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2698. idx = VA_CDC_DMA_TX_2;
  2699. break;
  2700. default:
  2701. idx = RX_CDC_DMA_RX_0;
  2702. break;
  2703. }
  2704. return idx;
  2705. }
  2706. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2707. struct snd_ctl_elem_value *ucontrol)
  2708. {
  2709. /*
  2710. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2711. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2712. * value.
  2713. */
  2714. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2715. case SAMPLING_RATE_96KHZ:
  2716. ucontrol->value.integer.value[0] = 5;
  2717. break;
  2718. case SAMPLING_RATE_88P2KHZ:
  2719. ucontrol->value.integer.value[0] = 4;
  2720. break;
  2721. case SAMPLING_RATE_48KHZ:
  2722. ucontrol->value.integer.value[0] = 3;
  2723. break;
  2724. case SAMPLING_RATE_44P1KHZ:
  2725. ucontrol->value.integer.value[0] = 2;
  2726. break;
  2727. case SAMPLING_RATE_16KHZ:
  2728. ucontrol->value.integer.value[0] = 1;
  2729. break;
  2730. case SAMPLING_RATE_8KHZ:
  2731. default:
  2732. ucontrol->value.integer.value[0] = 0;
  2733. break;
  2734. }
  2735. pr_debug("%s: sample rate = %d\n", __func__,
  2736. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2737. return 0;
  2738. }
  2739. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2740. struct snd_ctl_elem_value *ucontrol)
  2741. {
  2742. switch (ucontrol->value.integer.value[0]) {
  2743. case 1:
  2744. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2745. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2746. break;
  2747. case 2:
  2748. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2749. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2750. break;
  2751. case 3:
  2752. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2753. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2754. break;
  2755. case 4:
  2756. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2757. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2758. break;
  2759. case 5:
  2760. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2761. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2762. break;
  2763. case 0:
  2764. default:
  2765. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2766. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2767. break;
  2768. }
  2769. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2770. __func__,
  2771. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2772. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2773. ucontrol->value.enumerated.item[0]);
  2774. return 0;
  2775. }
  2776. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2777. struct snd_ctl_elem_value *ucontrol)
  2778. {
  2779. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2780. case SAMPLING_RATE_96KHZ:
  2781. ucontrol->value.integer.value[0] = 5;
  2782. break;
  2783. case SAMPLING_RATE_88P2KHZ:
  2784. ucontrol->value.integer.value[0] = 4;
  2785. break;
  2786. case SAMPLING_RATE_48KHZ:
  2787. ucontrol->value.integer.value[0] = 3;
  2788. break;
  2789. case SAMPLING_RATE_44P1KHZ:
  2790. ucontrol->value.integer.value[0] = 2;
  2791. break;
  2792. case SAMPLING_RATE_16KHZ:
  2793. ucontrol->value.integer.value[0] = 1;
  2794. break;
  2795. case SAMPLING_RATE_8KHZ:
  2796. default:
  2797. ucontrol->value.integer.value[0] = 0;
  2798. break;
  2799. }
  2800. pr_debug("%s: sample rate rx = %d\n", __func__,
  2801. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2802. return 0;
  2803. }
  2804. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2805. struct snd_ctl_elem_value *ucontrol)
  2806. {
  2807. switch (ucontrol->value.integer.value[0]) {
  2808. case 1:
  2809. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2810. break;
  2811. case 2:
  2812. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2813. break;
  2814. case 3:
  2815. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2816. break;
  2817. case 4:
  2818. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2819. break;
  2820. case 5:
  2821. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2822. break;
  2823. case 0:
  2824. default:
  2825. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2826. break;
  2827. }
  2828. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2829. __func__,
  2830. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2831. ucontrol->value.enumerated.item[0]);
  2832. return 0;
  2833. }
  2834. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2835. struct snd_ctl_elem_value *ucontrol)
  2836. {
  2837. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2838. case SAMPLING_RATE_96KHZ:
  2839. ucontrol->value.integer.value[0] = 5;
  2840. break;
  2841. case SAMPLING_RATE_88P2KHZ:
  2842. ucontrol->value.integer.value[0] = 4;
  2843. break;
  2844. case SAMPLING_RATE_48KHZ:
  2845. ucontrol->value.integer.value[0] = 3;
  2846. break;
  2847. case SAMPLING_RATE_44P1KHZ:
  2848. ucontrol->value.integer.value[0] = 2;
  2849. break;
  2850. case SAMPLING_RATE_16KHZ:
  2851. ucontrol->value.integer.value[0] = 1;
  2852. break;
  2853. case SAMPLING_RATE_8KHZ:
  2854. default:
  2855. ucontrol->value.integer.value[0] = 0;
  2856. break;
  2857. }
  2858. pr_debug("%s: sample rate tx = %d\n", __func__,
  2859. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2860. return 0;
  2861. }
  2862. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2863. struct snd_ctl_elem_value *ucontrol)
  2864. {
  2865. switch (ucontrol->value.integer.value[0]) {
  2866. case 1:
  2867. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2868. break;
  2869. case 2:
  2870. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2871. break;
  2872. case 3:
  2873. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2874. break;
  2875. case 4:
  2876. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2877. break;
  2878. case 5:
  2879. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2880. break;
  2881. case 0:
  2882. default:
  2883. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2884. break;
  2885. }
  2886. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2887. __func__,
  2888. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2889. ucontrol->value.enumerated.item[0]);
  2890. return 0;
  2891. }
  2892. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2893. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2894. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2895. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2896. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2897. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2898. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2899. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2900. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2901. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2902. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2903. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2904. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2905. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2906. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2907. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2908. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2909. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2910. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2911. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2912. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2913. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2914. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2915. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2916. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2917. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2918. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2919. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2920. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2921. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2922. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2923. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2924. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2925. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2926. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2927. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2928. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2929. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2930. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2931. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2932. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2933. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2934. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2935. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2936. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2937. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2938. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2939. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2940. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2941. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2942. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2943. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2944. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2945. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2946. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2947. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2948. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2949. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2950. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2951. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2952. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2953. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2954. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2955. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2956. wsa_cdc_dma_rx_0_sample_rate,
  2957. cdc_dma_rx_sample_rate_get,
  2958. cdc_dma_rx_sample_rate_put),
  2959. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2960. wsa_cdc_dma_rx_1_sample_rate,
  2961. cdc_dma_rx_sample_rate_get,
  2962. cdc_dma_rx_sample_rate_put),
  2963. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2964. rx_cdc_dma_rx_0_sample_rate,
  2965. cdc_dma_rx_sample_rate_get,
  2966. cdc_dma_rx_sample_rate_put),
  2967. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2968. rx_cdc_dma_rx_1_sample_rate,
  2969. cdc_dma_rx_sample_rate_get,
  2970. cdc_dma_rx_sample_rate_put),
  2971. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2972. rx_cdc_dma_rx_2_sample_rate,
  2973. cdc_dma_rx_sample_rate_get,
  2974. cdc_dma_rx_sample_rate_put),
  2975. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2976. rx_cdc_dma_rx_3_sample_rate,
  2977. cdc_dma_rx_sample_rate_get,
  2978. cdc_dma_rx_sample_rate_put),
  2979. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2980. rx_cdc_dma_rx_5_sample_rate,
  2981. cdc_dma_rx_sample_rate_get,
  2982. cdc_dma_rx_sample_rate_put),
  2983. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2984. wsa_cdc_dma_tx_0_sample_rate,
  2985. cdc_dma_tx_sample_rate_get,
  2986. cdc_dma_tx_sample_rate_put),
  2987. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2988. wsa_cdc_dma_tx_1_sample_rate,
  2989. cdc_dma_tx_sample_rate_get,
  2990. cdc_dma_tx_sample_rate_put),
  2991. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2992. wsa_cdc_dma_tx_2_sample_rate,
  2993. cdc_dma_tx_sample_rate_get,
  2994. cdc_dma_tx_sample_rate_put),
  2995. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2996. tx_cdc_dma_tx_0_sample_rate,
  2997. cdc_dma_tx_sample_rate_get,
  2998. cdc_dma_tx_sample_rate_put),
  2999. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  3000. tx_cdc_dma_tx_3_sample_rate,
  3001. cdc_dma_tx_sample_rate_get,
  3002. cdc_dma_tx_sample_rate_put),
  3003. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  3004. tx_cdc_dma_tx_4_sample_rate,
  3005. cdc_dma_tx_sample_rate_get,
  3006. cdc_dma_tx_sample_rate_put),
  3007. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3008. va_cdc_dma_tx_0_sample_rate,
  3009. cdc_dma_tx_sample_rate_get,
  3010. cdc_dma_tx_sample_rate_put),
  3011. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3012. va_cdc_dma_tx_1_sample_rate,
  3013. cdc_dma_tx_sample_rate_get,
  3014. cdc_dma_tx_sample_rate_put),
  3015. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  3016. va_cdc_dma_tx_2_sample_rate,
  3017. cdc_dma_tx_sample_rate_get,
  3018. cdc_dma_tx_sample_rate_put),
  3019. };
  3020. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3021. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3022. usb_audio_rx_sample_rate_get,
  3023. usb_audio_rx_sample_rate_put),
  3024. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3025. usb_audio_tx_sample_rate_get,
  3026. usb_audio_tx_sample_rate_put),
  3027. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3028. tdm_rx_sample_rate_get,
  3029. tdm_rx_sample_rate_put),
  3030. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3031. tdm_rx_sample_rate_get,
  3032. tdm_rx_sample_rate_put),
  3033. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3034. tdm_rx_sample_rate_get,
  3035. tdm_rx_sample_rate_put),
  3036. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3037. tdm_rx_sample_rate_get,
  3038. tdm_rx_sample_rate_put),
  3039. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3040. tdm_rx_sample_rate_get,
  3041. tdm_rx_sample_rate_put),
  3042. SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3043. tdm_rx_sample_rate_get,
  3044. tdm_rx_sample_rate_put),
  3045. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3046. tdm_tx_sample_rate_get,
  3047. tdm_tx_sample_rate_put),
  3048. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3049. tdm_tx_sample_rate_get,
  3050. tdm_tx_sample_rate_put),
  3051. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3052. tdm_tx_sample_rate_get,
  3053. tdm_tx_sample_rate_put),
  3054. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3055. tdm_tx_sample_rate_get,
  3056. tdm_tx_sample_rate_put),
  3057. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3058. tdm_tx_sample_rate_get,
  3059. tdm_tx_sample_rate_put),
  3060. SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3061. tdm_tx_sample_rate_get,
  3062. tdm_tx_sample_rate_put),
  3063. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3064. aux_pcm_rx_sample_rate_get,
  3065. aux_pcm_rx_sample_rate_put),
  3066. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3067. aux_pcm_rx_sample_rate_get,
  3068. aux_pcm_rx_sample_rate_put),
  3069. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3070. aux_pcm_rx_sample_rate_get,
  3071. aux_pcm_rx_sample_rate_put),
  3072. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3073. aux_pcm_rx_sample_rate_get,
  3074. aux_pcm_rx_sample_rate_put),
  3075. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3076. aux_pcm_rx_sample_rate_get,
  3077. aux_pcm_rx_sample_rate_put),
  3078. SOC_ENUM_EXT("SEN_AUX_PCM_RX SampleRate", sen_aux_pcm_rx_sample_rate,
  3079. aux_pcm_rx_sample_rate_get,
  3080. aux_pcm_rx_sample_rate_put),
  3081. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3082. aux_pcm_tx_sample_rate_get,
  3083. aux_pcm_tx_sample_rate_put),
  3084. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3085. aux_pcm_tx_sample_rate_get,
  3086. aux_pcm_tx_sample_rate_put),
  3087. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3088. aux_pcm_tx_sample_rate_get,
  3089. aux_pcm_tx_sample_rate_put),
  3090. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3091. aux_pcm_tx_sample_rate_get,
  3092. aux_pcm_tx_sample_rate_put),
  3093. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3094. aux_pcm_tx_sample_rate_get,
  3095. aux_pcm_tx_sample_rate_put),
  3096. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3097. aux_pcm_tx_sample_rate_get,
  3098. aux_pcm_tx_sample_rate_put),
  3099. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3100. mi2s_rx_sample_rate_get,
  3101. mi2s_rx_sample_rate_put),
  3102. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3103. mi2s_rx_sample_rate_get,
  3104. mi2s_rx_sample_rate_put),
  3105. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3106. mi2s_rx_sample_rate_get,
  3107. mi2s_rx_sample_rate_put),
  3108. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3109. mi2s_rx_sample_rate_get,
  3110. mi2s_rx_sample_rate_put),
  3111. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3112. mi2s_rx_sample_rate_get,
  3113. mi2s_rx_sample_rate_put),
  3114. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3115. mi2s_rx_sample_rate_get,
  3116. mi2s_rx_sample_rate_put),
  3117. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3118. mi2s_tx_sample_rate_get,
  3119. mi2s_tx_sample_rate_put),
  3120. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3121. mi2s_tx_sample_rate_get,
  3122. mi2s_tx_sample_rate_put),
  3123. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3124. mi2s_tx_sample_rate_get,
  3125. mi2s_tx_sample_rate_put),
  3126. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3127. mi2s_tx_sample_rate_get,
  3128. mi2s_tx_sample_rate_put),
  3129. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3130. mi2s_tx_sample_rate_get,
  3131. mi2s_tx_sample_rate_put),
  3132. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3133. mi2s_tx_sample_rate_get,
  3134. mi2s_tx_sample_rate_put),
  3135. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3136. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3137. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3138. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3139. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3140. tdm_rx_format_get,
  3141. tdm_rx_format_put),
  3142. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3143. tdm_rx_format_get,
  3144. tdm_rx_format_put),
  3145. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3146. tdm_rx_format_get,
  3147. tdm_rx_format_put),
  3148. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3149. tdm_rx_format_get,
  3150. tdm_rx_format_put),
  3151. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3152. tdm_rx_format_get,
  3153. tdm_rx_format_put),
  3154. SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format,
  3155. tdm_rx_format_get,
  3156. tdm_rx_format_put),
  3157. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3158. tdm_tx_format_get,
  3159. tdm_tx_format_put),
  3160. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3161. tdm_tx_format_get,
  3162. tdm_tx_format_put),
  3163. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3164. tdm_tx_format_get,
  3165. tdm_tx_format_put),
  3166. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3167. tdm_tx_format_get,
  3168. tdm_tx_format_put),
  3169. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3170. tdm_tx_format_get,
  3171. tdm_tx_format_put),
  3172. SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format,
  3173. tdm_tx_format_get,
  3174. tdm_tx_format_put),
  3175. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3176. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3177. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3178. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3179. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3180. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3181. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3182. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3183. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3184. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3185. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3186. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3187. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3188. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3189. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3190. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3191. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3192. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3193. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3194. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3195. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3196. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3197. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3198. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3199. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3200. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3201. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3202. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3203. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3204. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3205. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3206. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3207. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3208. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3209. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3210. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3211. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3212. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3213. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3214. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3215. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3216. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3217. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3218. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3219. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3220. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3221. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3222. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3223. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3224. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3225. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3226. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3227. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3228. proxy_rx_ch_get, proxy_rx_ch_put),
  3229. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3230. tdm_rx_ch_get,
  3231. tdm_rx_ch_put),
  3232. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3233. tdm_rx_ch_get,
  3234. tdm_rx_ch_put),
  3235. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3236. tdm_rx_ch_get,
  3237. tdm_rx_ch_put),
  3238. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3239. tdm_rx_ch_get,
  3240. tdm_rx_ch_put),
  3241. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3242. tdm_rx_ch_get,
  3243. tdm_rx_ch_put),
  3244. SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs,
  3245. tdm_rx_ch_get,
  3246. tdm_rx_ch_put),
  3247. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3248. tdm_tx_ch_get,
  3249. tdm_tx_ch_put),
  3250. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3251. tdm_tx_ch_get,
  3252. tdm_tx_ch_put),
  3253. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3254. tdm_tx_ch_get,
  3255. tdm_tx_ch_put),
  3256. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3257. tdm_tx_ch_get,
  3258. tdm_tx_ch_put),
  3259. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3260. tdm_tx_ch_get,
  3261. tdm_tx_ch_put),
  3262. SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
  3263. tdm_tx_ch_get,
  3264. tdm_tx_ch_put),
  3265. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3266. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3267. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3268. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3269. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3270. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3271. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3272. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3273. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3274. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3275. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3276. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3277. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3278. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3279. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3280. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3281. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3282. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3283. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3284. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3285. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3286. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3287. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3288. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3289. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  3290. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3291. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  3292. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3293. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  3294. ext_disp_rx_sample_rate_get,
  3295. ext_disp_rx_sample_rate_put),
  3296. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3297. msm_bt_sample_rate_get,
  3298. msm_bt_sample_rate_put),
  3299. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3300. msm_bt_sample_rate_rx_get,
  3301. msm_bt_sample_rate_rx_put),
  3302. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3303. msm_bt_sample_rate_tx_get,
  3304. msm_bt_sample_rate_tx_put),
  3305. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3306. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3307. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3308. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3309. };
  3310. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3311. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3312. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3313. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3314. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3315. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3316. aux_pcm_rx_sample_rate_get,
  3317. aux_pcm_rx_sample_rate_put),
  3318. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3319. aux_pcm_tx_sample_rate_get,
  3320. aux_pcm_tx_sample_rate_put),
  3321. };
  3322. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3323. {
  3324. int idx;
  3325. switch (be_id) {
  3326. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3327. idx = EXT_DISP_RX_IDX_DP;
  3328. break;
  3329. default:
  3330. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3331. idx = -EINVAL;
  3332. break;
  3333. }
  3334. return idx;
  3335. }
  3336. static int kona_send_island_va_config(int32_t be_id)
  3337. {
  3338. int rc = 0;
  3339. int port_id = 0xFFFF;
  3340. port_id = msm_get_port_id(be_id);
  3341. if (port_id < 0) {
  3342. pr_err("%s: Invalid island interface, be_id: %d\n",
  3343. __func__, be_id);
  3344. rc = -EINVAL;
  3345. } else {
  3346. /*
  3347. * send island mode config
  3348. * This should be the first configuration
  3349. */
  3350. rc = afe_send_port_island_mode(port_id);
  3351. if (rc)
  3352. pr_err("%s: afe send island mode failed %d\n",
  3353. __func__, rc);
  3354. }
  3355. return rc;
  3356. }
  3357. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3358. struct snd_pcm_hw_params *params)
  3359. {
  3360. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3361. struct snd_interval *rate = hw_param_interval(params,
  3362. SNDRV_PCM_HW_PARAM_RATE);
  3363. struct snd_interval *channels = hw_param_interval(params,
  3364. SNDRV_PCM_HW_PARAM_CHANNELS);
  3365. int idx = 0, rc = 0;
  3366. pr_debug("%s: format = %d, rate = %d\n",
  3367. __func__, params_format(params), params_rate(params));
  3368. switch (dai_link->id) {
  3369. case MSM_BACKEND_DAI_USB_RX:
  3370. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3371. usb_rx_cfg.bit_format);
  3372. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3373. channels->min = channels->max = usb_rx_cfg.channels;
  3374. break;
  3375. case MSM_BACKEND_DAI_USB_TX:
  3376. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3377. usb_tx_cfg.bit_format);
  3378. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3379. channels->min = channels->max = usb_tx_cfg.channels;
  3380. break;
  3381. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3382. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3383. if (idx < 0) {
  3384. pr_err("%s: Incorrect ext disp idx %d\n",
  3385. __func__, idx);
  3386. rc = idx;
  3387. goto done;
  3388. }
  3389. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3390. ext_disp_rx_cfg[idx].bit_format);
  3391. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3392. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3393. break;
  3394. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3395. channels->min = channels->max = proxy_rx_cfg.channels;
  3396. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3397. break;
  3398. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3399. channels->min = channels->max =
  3400. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3401. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3402. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3403. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3404. break;
  3405. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3406. channels->min = channels->max =
  3407. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3408. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3409. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3410. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3411. break;
  3412. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3413. channels->min = channels->max =
  3414. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3415. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3416. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3417. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3418. break;
  3419. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3420. channels->min = channels->max =
  3421. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3422. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3423. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3424. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3425. break;
  3426. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3427. channels->min = channels->max =
  3428. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3429. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3430. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3431. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3432. break;
  3433. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3434. channels->min = channels->max =
  3435. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3436. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3437. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3438. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3439. break;
  3440. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3441. channels->min = channels->max =
  3442. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3443. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3444. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3445. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3446. break;
  3447. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3448. channels->min = channels->max =
  3449. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3450. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3451. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3452. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3453. break;
  3454. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3455. channels->min = channels->max =
  3456. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3457. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3458. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3459. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3460. break;
  3461. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3462. channels->min = channels->max =
  3463. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3464. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3465. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3466. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3467. break;
  3468. case MSM_BACKEND_DAI_SEN_TDM_RX_0:
  3469. channels->min = channels->max =
  3470. tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3471. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3472. tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
  3473. rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
  3474. break;
  3475. case MSM_BACKEND_DAI_SEN_TDM_TX_0:
  3476. channels->min = channels->max =
  3477. tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3478. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3479. tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
  3480. rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
  3481. break;
  3482. case MSM_BACKEND_DAI_AUXPCM_RX:
  3483. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3484. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3485. rate->min = rate->max =
  3486. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3487. channels->min = channels->max =
  3488. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3489. break;
  3490. case MSM_BACKEND_DAI_AUXPCM_TX:
  3491. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3492. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3493. rate->min = rate->max =
  3494. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3495. channels->min = channels->max =
  3496. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3497. break;
  3498. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3499. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3500. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3501. rate->min = rate->max =
  3502. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3503. channels->min = channels->max =
  3504. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3505. break;
  3506. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3507. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3508. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3509. rate->min = rate->max =
  3510. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3511. channels->min = channels->max =
  3512. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3513. break;
  3514. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3515. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3516. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3517. rate->min = rate->max =
  3518. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3519. channels->min = channels->max =
  3520. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3521. break;
  3522. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3523. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3524. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3525. rate->min = rate->max =
  3526. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3527. channels->min = channels->max =
  3528. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3529. break;
  3530. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3531. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3532. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3533. rate->min = rate->max =
  3534. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3535. channels->min = channels->max =
  3536. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3537. break;
  3538. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3539. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3540. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3541. rate->min = rate->max =
  3542. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3543. channels->min = channels->max =
  3544. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3545. break;
  3546. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3547. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3548. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3549. rate->min = rate->max =
  3550. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3551. channels->min = channels->max =
  3552. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3553. break;
  3554. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3555. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3556. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3557. rate->min = rate->max =
  3558. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3559. channels->min = channels->max =
  3560. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3561. break;
  3562. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3563. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3564. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3565. rate->min = rate->max =
  3566. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3567. channels->min = channels->max =
  3568. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3569. break;
  3570. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3571. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3572. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3573. rate->min = rate->max =
  3574. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3575. channels->min = channels->max =
  3576. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3577. break;
  3578. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3579. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3580. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3581. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3582. channels->min = channels->max =
  3583. mi2s_rx_cfg[PRIM_MI2S].channels;
  3584. break;
  3585. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3586. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3587. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3588. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3589. channels->min = channels->max =
  3590. mi2s_tx_cfg[PRIM_MI2S].channels;
  3591. break;
  3592. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3593. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3594. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3595. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3596. channels->min = channels->max =
  3597. mi2s_rx_cfg[SEC_MI2S].channels;
  3598. break;
  3599. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3600. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3601. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3602. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3603. channels->min = channels->max =
  3604. mi2s_tx_cfg[SEC_MI2S].channels;
  3605. break;
  3606. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3607. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3608. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3609. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3610. channels->min = channels->max =
  3611. mi2s_rx_cfg[TERT_MI2S].channels;
  3612. break;
  3613. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3614. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3615. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3616. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3617. channels->min = channels->max =
  3618. mi2s_tx_cfg[TERT_MI2S].channels;
  3619. break;
  3620. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3621. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3622. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3623. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3624. channels->min = channels->max =
  3625. mi2s_rx_cfg[QUAT_MI2S].channels;
  3626. break;
  3627. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3628. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3629. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3630. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3631. channels->min = channels->max =
  3632. mi2s_tx_cfg[QUAT_MI2S].channels;
  3633. break;
  3634. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3635. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3636. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3637. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3638. channels->min = channels->max =
  3639. mi2s_rx_cfg[QUIN_MI2S].channels;
  3640. break;
  3641. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3642. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3643. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3644. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3645. channels->min = channels->max =
  3646. mi2s_tx_cfg[QUIN_MI2S].channels;
  3647. break;
  3648. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3649. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3650. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3651. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3652. channels->min = channels->max =
  3653. mi2s_rx_cfg[SEN_MI2S].channels;
  3654. break;
  3655. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3656. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3657. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3658. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3659. channels->min = channels->max =
  3660. mi2s_tx_cfg[SEN_MI2S].channels;
  3661. break;
  3662. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3663. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3664. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3665. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3666. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3667. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3668. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3669. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3670. cdc_dma_rx_cfg[idx].bit_format);
  3671. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3672. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3673. break;
  3674. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3675. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3676. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3677. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3678. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3679. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3680. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3681. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3682. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3683. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3684. cdc_dma_tx_cfg[idx].bit_format);
  3685. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3686. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3687. break;
  3688. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3689. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3690. SNDRV_PCM_FORMAT_S32_LE);
  3691. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3692. channels->min = channels->max = msm_vi_feed_tx_ch;
  3693. break;
  3694. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3695. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3696. slim_rx_cfg[SLIM_RX_7].bit_format);
  3697. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3698. channels->min = channels->max =
  3699. slim_rx_cfg[SLIM_RX_7].channels;
  3700. break;
  3701. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3702. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3703. channels->min = channels->max =
  3704. slim_tx_cfg[SLIM_TX_7].channels;
  3705. break;
  3706. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3707. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3708. channels->min = channels->max =
  3709. slim_tx_cfg[SLIM_TX_8].channels;
  3710. break;
  3711. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3712. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3713. afe_loopback_tx_cfg[idx].bit_format);
  3714. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3715. channels->min = channels->max =
  3716. afe_loopback_tx_cfg[idx].channels;
  3717. break;
  3718. default:
  3719. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3720. break;
  3721. }
  3722. done:
  3723. return rc;
  3724. }
  3725. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3726. {
  3727. struct snd_soc_card *card = component->card;
  3728. struct msm_asoc_mach_data *pdata =
  3729. snd_soc_card_get_drvdata(card);
  3730. if (!pdata->fsa_handle)
  3731. return false;
  3732. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3733. }
  3734. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3735. {
  3736. int value = 0;
  3737. bool ret = false;
  3738. struct snd_soc_card *card;
  3739. struct msm_asoc_mach_data *pdata;
  3740. if (!component) {
  3741. pr_err("%s component is NULL\n", __func__);
  3742. return false;
  3743. }
  3744. card = component->card;
  3745. pdata = snd_soc_card_get_drvdata(card);
  3746. if (!pdata)
  3747. return false;
  3748. if (wcd_mbhc_cfg.enable_usbc_analog)
  3749. return msm_usbc_swap_gnd_mic(component, active);
  3750. /* if usbc is not defined, swap using us_euro_gpio_p */
  3751. if (pdata->us_euro_gpio_p) {
  3752. value = msm_cdc_pinctrl_get_state(
  3753. pdata->us_euro_gpio_p);
  3754. if (value)
  3755. msm_cdc_pinctrl_select_sleep_state(
  3756. pdata->us_euro_gpio_p);
  3757. else
  3758. msm_cdc_pinctrl_select_active_state(
  3759. pdata->us_euro_gpio_p);
  3760. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3761. __func__, value, !value);
  3762. ret = true;
  3763. }
  3764. return ret;
  3765. }
  3766. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3767. struct snd_pcm_hw_params *params)
  3768. {
  3769. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3770. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3771. int ret = 0;
  3772. int slot_width = 32;
  3773. int channels, slots;
  3774. unsigned int slot_mask, rate, clk_freq;
  3775. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3776. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3777. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3778. switch (cpu_dai->id) {
  3779. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3780. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3781. break;
  3782. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3783. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3784. break;
  3785. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3786. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3787. break;
  3788. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3789. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3790. break;
  3791. case AFE_PORT_ID_QUINARY_TDM_RX:
  3792. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3793. break;
  3794. case AFE_PORT_ID_SENARY_TDM_RX:
  3795. slots = tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3796. break;
  3797. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3798. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3799. break;
  3800. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3801. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3802. break;
  3803. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3804. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3805. break;
  3806. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3807. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3808. break;
  3809. case AFE_PORT_ID_QUINARY_TDM_TX:
  3810. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3811. break;
  3812. case AFE_PORT_ID_SENARY_TDM_TX:
  3813. slots = tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3814. break;
  3815. default:
  3816. pr_err("%s: dai id 0x%x not supported\n",
  3817. __func__, cpu_dai->id);
  3818. return -EINVAL;
  3819. }
  3820. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3821. /*2 slot config - bits 0 and 1 set for the first two slots */
  3822. slot_mask = 0x0000FFFF >> (16 - slots);
  3823. channels = slots;
  3824. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3825. __func__, slot_width, slots);
  3826. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3827. slots, slot_width);
  3828. if (ret < 0) {
  3829. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3830. __func__, ret);
  3831. goto end;
  3832. }
  3833. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3834. 0, NULL, channels, slot_offset);
  3835. if (ret < 0) {
  3836. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3837. __func__, ret);
  3838. goto end;
  3839. }
  3840. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3841. /*2 slot config - bits 0 and 1 set for the first two slots */
  3842. slot_mask = 0x0000FFFF >> (16 - slots);
  3843. channels = slots;
  3844. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3845. __func__, slot_width, slots);
  3846. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3847. slots, slot_width);
  3848. if (ret < 0) {
  3849. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3850. __func__, ret);
  3851. goto end;
  3852. }
  3853. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3854. channels, slot_offset, 0, NULL);
  3855. if (ret < 0) {
  3856. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3857. __func__, ret);
  3858. goto end;
  3859. }
  3860. } else {
  3861. ret = -EINVAL;
  3862. pr_err("%s: invalid use case, err:%d\n",
  3863. __func__, ret);
  3864. goto end;
  3865. }
  3866. rate = params_rate(params);
  3867. clk_freq = rate * slot_width * slots;
  3868. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3869. if (ret < 0)
  3870. pr_err("%s: failed to set tdm clk, err:%d\n",
  3871. __func__, ret);
  3872. end:
  3873. return ret;
  3874. }
  3875. static int msm_get_tdm_mode(u32 port_id)
  3876. {
  3877. int tdm_mode;
  3878. switch (port_id) {
  3879. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3880. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3881. tdm_mode = TDM_PRI;
  3882. break;
  3883. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3884. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3885. tdm_mode = TDM_SEC;
  3886. break;
  3887. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3888. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3889. tdm_mode = TDM_TERT;
  3890. break;
  3891. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3892. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3893. tdm_mode = TDM_QUAT;
  3894. break;
  3895. case AFE_PORT_ID_QUINARY_TDM_RX:
  3896. case AFE_PORT_ID_QUINARY_TDM_TX:
  3897. tdm_mode = TDM_QUIN;
  3898. break;
  3899. case AFE_PORT_ID_SENARY_TDM_RX:
  3900. case AFE_PORT_ID_SENARY_TDM_TX:
  3901. tdm_mode = TDM_SEN;
  3902. break;
  3903. default:
  3904. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3905. tdm_mode = -EINVAL;
  3906. }
  3907. return tdm_mode;
  3908. }
  3909. static int kona_tdm_snd_startup(struct snd_pcm_substream *substream)
  3910. {
  3911. int ret = 0;
  3912. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3913. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3914. struct snd_soc_card *card = rtd->card;
  3915. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3916. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3917. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3918. ret = -EINVAL;
  3919. pr_err("%s: Invalid TDM interface %d\n",
  3920. __func__, ret);
  3921. return ret;
  3922. }
  3923. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3924. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3925. == 0) {
  3926. ret = msm_cdc_pinctrl_select_active_state(
  3927. pdata->mi2s_gpio_p[tdm_mode]);
  3928. if (ret) {
  3929. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3930. __func__, ret);
  3931. goto done;
  3932. }
  3933. }
  3934. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3935. }
  3936. done:
  3937. return ret;
  3938. }
  3939. static void kona_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3940. {
  3941. int ret = 0;
  3942. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3943. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3944. struct snd_soc_card *card = rtd->card;
  3945. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3946. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3947. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3948. ret = -EINVAL;
  3949. pr_err("%s: Invalid TDM interface %d\n",
  3950. __func__, ret);
  3951. return;
  3952. }
  3953. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3954. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3955. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3956. == 0) {
  3957. ret = msm_cdc_pinctrl_select_sleep_state(
  3958. pdata->mi2s_gpio_p[tdm_mode]);
  3959. if (ret)
  3960. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3961. __func__, ret);
  3962. }
  3963. }
  3964. }
  3965. static int kona_aux_snd_startup(struct snd_pcm_substream *substream)
  3966. {
  3967. int ret = 0;
  3968. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3969. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3970. struct snd_soc_card *card = rtd->card;
  3971. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3972. u32 aux_mode = cpu_dai->id - 1;
  3973. if (aux_mode >= AUX_PCM_MAX) {
  3974. ret = -EINVAL;
  3975. pr_err("%s: Invalid AUX interface %d\n",
  3976. __func__, ret);
  3977. return ret;
  3978. }
  3979. if (pdata->mi2s_gpio_p[aux_mode]) {
  3980. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3981. == 0) {
  3982. ret = msm_cdc_pinctrl_select_active_state(
  3983. pdata->mi2s_gpio_p[aux_mode]);
  3984. if (ret) {
  3985. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  3986. __func__, ret);
  3987. goto done;
  3988. }
  3989. }
  3990. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3991. }
  3992. done:
  3993. return ret;
  3994. }
  3995. static void kona_aux_snd_shutdown(struct snd_pcm_substream *substream)
  3996. {
  3997. int ret = 0;
  3998. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3999. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4000. struct snd_soc_card *card = rtd->card;
  4001. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4002. u32 aux_mode = cpu_dai->id - 1;
  4003. if (aux_mode >= AUX_PCM_MAX) {
  4004. pr_err("%s: Invalid AUX interface %d\n",
  4005. __func__, ret);
  4006. return;
  4007. }
  4008. if (pdata->mi2s_gpio_p[aux_mode]) {
  4009. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4010. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4011. == 0) {
  4012. ret = msm_cdc_pinctrl_select_sleep_state(
  4013. pdata->mi2s_gpio_p[aux_mode]);
  4014. if (ret)
  4015. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  4016. __func__, ret);
  4017. }
  4018. }
  4019. }
  4020. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4021. {
  4022. int ret = 0;
  4023. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4024. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4025. switch (dai_link->id) {
  4026. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4027. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4028. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4029. ret = kona_send_island_va_config(dai_link->id);
  4030. if (ret)
  4031. pr_err("%s: send island va cfg failed, err: %d\n",
  4032. __func__, ret);
  4033. break;
  4034. }
  4035. return ret;
  4036. }
  4037. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4038. struct snd_pcm_hw_params *params)
  4039. {
  4040. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4041. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4042. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4043. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4044. int ret = 0;
  4045. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4046. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4047. u32 user_set_tx_ch = 0;
  4048. u32 user_set_rx_ch = 0;
  4049. u32 ch_id;
  4050. ret = snd_soc_dai_get_channel_map(codec_dai,
  4051. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4052. &rx_ch_cdc_dma);
  4053. if (ret < 0) {
  4054. pr_err("%s: failed to get codec chan map, err:%d\n",
  4055. __func__, ret);
  4056. goto err;
  4057. }
  4058. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4059. switch (dai_link->id) {
  4060. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4061. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4062. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  4063. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  4064. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  4065. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  4066. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  4067. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  4068. {
  4069. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4070. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4071. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4072. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4073. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4074. user_set_rx_ch, &rx_ch_cdc_dma);
  4075. if (ret < 0) {
  4076. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4077. __func__, ret);
  4078. goto err;
  4079. }
  4080. }
  4081. break;
  4082. }
  4083. } else {
  4084. switch (dai_link->id) {
  4085. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4086. {
  4087. user_set_tx_ch = msm_vi_feed_tx_ch;
  4088. }
  4089. break;
  4090. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4091. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4092. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  4093. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  4094. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  4095. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4096. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4097. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4098. {
  4099. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4100. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4101. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4102. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4103. }
  4104. break;
  4105. }
  4106. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4107. &tx_ch_cdc_dma, 0, 0);
  4108. if (ret < 0) {
  4109. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4110. __func__, ret);
  4111. goto err;
  4112. }
  4113. }
  4114. err:
  4115. return ret;
  4116. }
  4117. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4118. {
  4119. cpumask_t mask;
  4120. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4121. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4122. cpumask_clear(&mask);
  4123. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4124. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4125. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4126. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4127. pm_qos_add_request(&substream->latency_pm_qos_req,
  4128. PM_QOS_CPU_DMA_LATENCY,
  4129. MSM_LL_QOS_VALUE);
  4130. return 0;
  4131. }
  4132. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4133. {
  4134. int ret = 0;
  4135. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4136. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4137. int index = cpu_dai->id;
  4138. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4139. struct snd_soc_card *card = rtd->card;
  4140. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4141. dev_dbg(rtd->card->dev,
  4142. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4143. __func__, substream->name, substream->stream,
  4144. cpu_dai->name, cpu_dai->id);
  4145. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4146. ret = -EINVAL;
  4147. dev_err(rtd->card->dev,
  4148. "%s: CPU DAI id (%d) out of range\n",
  4149. __func__, cpu_dai->id);
  4150. goto err;
  4151. }
  4152. /*
  4153. * Mutex protection in case the same MI2S
  4154. * interface using for both TX and RX so
  4155. * that the same clock won't be enable twice.
  4156. */
  4157. mutex_lock(&mi2s_intf_conf[index].lock);
  4158. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4159. /* Check if msm needs to provide the clock to the interface */
  4160. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4161. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4162. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4163. }
  4164. ret = msm_mi2s_set_sclk(substream, true);
  4165. if (ret < 0) {
  4166. dev_err(rtd->card->dev,
  4167. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4168. __func__, ret);
  4169. goto clean_up;
  4170. }
  4171. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4172. if (ret < 0) {
  4173. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4174. __func__, index, ret);
  4175. goto clk_off;
  4176. }
  4177. if (pdata->mi2s_gpio_p[index]) {
  4178. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4179. == 0) {
  4180. ret = msm_cdc_pinctrl_select_active_state(
  4181. pdata->mi2s_gpio_p[index]);
  4182. if (ret) {
  4183. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4184. __func__, ret);
  4185. goto clk_off;
  4186. }
  4187. }
  4188. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4189. }
  4190. }
  4191. clk_off:
  4192. if (ret < 0)
  4193. msm_mi2s_set_sclk(substream, false);
  4194. clean_up:
  4195. if (ret < 0)
  4196. mi2s_intf_conf[index].ref_cnt--;
  4197. mutex_unlock(&mi2s_intf_conf[index].lock);
  4198. err:
  4199. return ret;
  4200. }
  4201. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4202. {
  4203. int ret = 0;
  4204. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4205. int index = rtd->cpu_dai->id;
  4206. struct snd_soc_card *card = rtd->card;
  4207. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4208. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4209. substream->name, substream->stream);
  4210. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4211. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4212. return;
  4213. }
  4214. mutex_lock(&mi2s_intf_conf[index].lock);
  4215. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4216. if (pdata->mi2s_gpio_p[index]) {
  4217. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4218. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4219. == 0) {
  4220. ret = msm_cdc_pinctrl_select_sleep_state(
  4221. pdata->mi2s_gpio_p[index]);
  4222. if (ret)
  4223. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4224. __func__, ret);
  4225. }
  4226. }
  4227. ret = msm_mi2s_set_sclk(substream, false);
  4228. if (ret < 0)
  4229. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4230. __func__, index, ret);
  4231. }
  4232. mutex_unlock(&mi2s_intf_conf[index].lock);
  4233. }
  4234. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4235. struct snd_pcm_hw_params *params)
  4236. {
  4237. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4238. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4239. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4240. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4241. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4242. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4243. int ret = 0;
  4244. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4245. codec_dai->name, codec_dai->id);
  4246. ret = snd_soc_dai_get_channel_map(codec_dai,
  4247. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4248. if (ret) {
  4249. dev_err(rtd->dev,
  4250. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4251. __func__, ret);
  4252. goto err;
  4253. }
  4254. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4255. __func__, tx_ch_cnt, dai_link->id);
  4256. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4257. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4258. if (ret)
  4259. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4260. __func__, ret);
  4261. err:
  4262. return ret;
  4263. }
  4264. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4265. struct snd_pcm_hw_params *params)
  4266. {
  4267. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4268. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4269. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4270. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4271. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4272. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4273. int ret = 0;
  4274. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4275. codec_dai->name, codec_dai->id);
  4276. ret = snd_soc_dai_get_channel_map(codec_dai,
  4277. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4278. if (ret) {
  4279. dev_err(rtd->dev,
  4280. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4281. __func__, ret);
  4282. goto err;
  4283. }
  4284. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4285. __func__, tx_ch_cnt, dai_link->id);
  4286. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4287. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4288. if (ret)
  4289. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4290. __func__, ret);
  4291. err:
  4292. return ret;
  4293. }
  4294. static struct snd_soc_ops kona_aux_be_ops = {
  4295. .startup = kona_aux_snd_startup,
  4296. .shutdown = kona_aux_snd_shutdown
  4297. };
  4298. static struct snd_soc_ops kona_tdm_be_ops = {
  4299. .hw_params = kona_tdm_snd_hw_params,
  4300. .startup = kona_tdm_snd_startup,
  4301. .shutdown = kona_tdm_snd_shutdown
  4302. };
  4303. static struct snd_soc_ops msm_mi2s_be_ops = {
  4304. .startup = msm_mi2s_snd_startup,
  4305. .shutdown = msm_mi2s_snd_shutdown,
  4306. };
  4307. static struct snd_soc_ops msm_fe_qos_ops = {
  4308. .prepare = msm_fe_qos_prepare,
  4309. };
  4310. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4311. .startup = msm_snd_cdc_dma_startup,
  4312. .hw_params = msm_snd_cdc_dma_hw_params,
  4313. };
  4314. static struct snd_soc_ops msm_wcn_ops = {
  4315. .hw_params = msm_wcn_hw_params,
  4316. };
  4317. static struct snd_soc_ops msm_wcn_ops_lito = {
  4318. .hw_params = msm_wcn_hw_params_lito,
  4319. };
  4320. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4321. struct snd_kcontrol *kcontrol, int event)
  4322. {
  4323. struct msm_asoc_mach_data *pdata = NULL;
  4324. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  4325. int ret = 0;
  4326. u32 dmic_idx;
  4327. int *dmic_gpio_cnt;
  4328. struct device_node *dmic_gpio;
  4329. char *wname;
  4330. wname = strpbrk(w->name, "012345");
  4331. if (!wname) {
  4332. dev_err(component->dev, "%s: widget not found\n", __func__);
  4333. return -EINVAL;
  4334. }
  4335. ret = kstrtouint(wname, 10, &dmic_idx);
  4336. if (ret < 0) {
  4337. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4338. __func__);
  4339. return -EINVAL;
  4340. }
  4341. pdata = snd_soc_card_get_drvdata(component->card);
  4342. switch (dmic_idx) {
  4343. case 0:
  4344. case 1:
  4345. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4346. dmic_gpio = pdata->dmic01_gpio_p;
  4347. break;
  4348. case 2:
  4349. case 3:
  4350. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4351. dmic_gpio = pdata->dmic23_gpio_p;
  4352. break;
  4353. case 4:
  4354. case 5:
  4355. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4356. dmic_gpio = pdata->dmic45_gpio_p;
  4357. break;
  4358. default:
  4359. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4360. __func__);
  4361. return -EINVAL;
  4362. }
  4363. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4364. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4365. switch (event) {
  4366. case SND_SOC_DAPM_PRE_PMU:
  4367. (*dmic_gpio_cnt)++;
  4368. if (*dmic_gpio_cnt == 1) {
  4369. ret = msm_cdc_pinctrl_select_active_state(
  4370. dmic_gpio);
  4371. if (ret < 0) {
  4372. pr_err("%s: gpio set cannot be activated %sd",
  4373. __func__, "dmic_gpio");
  4374. return ret;
  4375. }
  4376. }
  4377. break;
  4378. case SND_SOC_DAPM_POST_PMD:
  4379. (*dmic_gpio_cnt)--;
  4380. if (*dmic_gpio_cnt == 0) {
  4381. ret = msm_cdc_pinctrl_select_sleep_state(
  4382. dmic_gpio);
  4383. if (ret < 0) {
  4384. pr_err("%s: gpio set cannot be de-activated %sd",
  4385. __func__, "dmic_gpio");
  4386. return ret;
  4387. }
  4388. }
  4389. break;
  4390. default:
  4391. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4392. return -EINVAL;
  4393. }
  4394. return 0;
  4395. }
  4396. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4397. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4398. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4399. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4400. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4401. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4402. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4403. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4404. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4405. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4406. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4407. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4408. };
  4409. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4410. {
  4411. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4412. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  4413. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4414. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4415. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4416. }
  4417. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4418. {
  4419. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4420. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4421. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4422. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4423. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4424. }
  4425. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4426. {
  4427. int ret = -EINVAL;
  4428. struct snd_soc_component *component;
  4429. struct snd_soc_dapm_context *dapm;
  4430. struct snd_card *card;
  4431. struct snd_info_entry *entry;
  4432. struct snd_soc_component *aux_comp;
  4433. struct msm_asoc_mach_data *pdata =
  4434. snd_soc_card_get_drvdata(rtd->card);
  4435. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4436. if (!component) {
  4437. pr_err("%s: could not find component for bolero_codec\n",
  4438. __func__);
  4439. return ret;
  4440. }
  4441. dapm = snd_soc_component_get_dapm(component);
  4442. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  4443. ARRAY_SIZE(msm_int_snd_controls));
  4444. if (ret < 0) {
  4445. pr_err("%s: add_component_controls failed: %d\n",
  4446. __func__, ret);
  4447. return ret;
  4448. }
  4449. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  4450. ARRAY_SIZE(msm_common_snd_controls));
  4451. if (ret < 0) {
  4452. pr_err("%s: add common snd controls failed: %d\n",
  4453. __func__, ret);
  4454. return ret;
  4455. }
  4456. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  4457. ARRAY_SIZE(msm_int_dapm_widgets));
  4458. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4459. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4460. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4461. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4462. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4463. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4464. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  4465. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  4466. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4467. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4468. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  4469. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4470. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4471. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4472. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4473. snd_soc_dapm_sync(dapm);
  4474. /*
  4475. * Send speaker configuration only for WSA8810.
  4476. * Default configuration is for WSA8815.
  4477. */
  4478. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4479. __func__, rtd->card->num_aux_devs);
  4480. if (rtd->card->num_aux_devs &&
  4481. !list_empty(&rtd->card->component_dev_list)) {
  4482. list_for_each_entry(aux_comp,
  4483. &rtd->card->aux_comp_list,
  4484. card_aux_list) {
  4485. if (aux_comp->name != NULL && (
  4486. !strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4487. !strcmp(aux_comp->name, WSA8810_NAME_2))) {
  4488. wsa_macro_set_spkr_mode(component,
  4489. WSA_MACRO_SPKR_MODE_1);
  4490. wsa_macro_set_spkr_gain_offset(component,
  4491. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4492. }
  4493. }
  4494. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  4495. sm_port_map);
  4496. }
  4497. card = rtd->card->snd_card;
  4498. if (!pdata->codec_root) {
  4499. entry = snd_info_create_subdir(card->module, "codecs",
  4500. card->proc_root);
  4501. if (!entry) {
  4502. pr_debug("%s: Cannot create codecs module entry\n",
  4503. __func__);
  4504. ret = 0;
  4505. goto err;
  4506. }
  4507. pdata->codec_root = entry;
  4508. }
  4509. bolero_info_create_codec_entry(pdata->codec_root, component);
  4510. bolero_register_wake_irq(component, false);
  4511. codec_reg_done = true;
  4512. return 0;
  4513. err:
  4514. return ret;
  4515. }
  4516. static void *def_wcd_mbhc_cal(void)
  4517. {
  4518. void *wcd_mbhc_cal;
  4519. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4520. u16 *btn_high;
  4521. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4522. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4523. if (!wcd_mbhc_cal)
  4524. return NULL;
  4525. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4526. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4527. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4528. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4529. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4530. btn_high[0] = 75;
  4531. btn_high[1] = 150;
  4532. btn_high[2] = 237;
  4533. btn_high[3] = 500;
  4534. btn_high[4] = 500;
  4535. btn_high[5] = 500;
  4536. btn_high[6] = 500;
  4537. btn_high[7] = 500;
  4538. return wcd_mbhc_cal;
  4539. }
  4540. /* Digital audio interface glue - connects codec <---> CPU */
  4541. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4542. /* FrontEnd DAI Links */
  4543. {/* hw:x,0 */
  4544. .name = MSM_DAILINK_NAME(Media1),
  4545. .stream_name = "MultiMedia1",
  4546. .cpu_dai_name = "MultiMedia1",
  4547. .platform_name = "msm-pcm-dsp.0",
  4548. .dynamic = 1,
  4549. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4550. .dpcm_playback = 1,
  4551. .dpcm_capture = 1,
  4552. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4553. SND_SOC_DPCM_TRIGGER_POST},
  4554. .codec_dai_name = "snd-soc-dummy-dai",
  4555. .codec_name = "snd-soc-dummy",
  4556. .ignore_suspend = 1,
  4557. /* this dainlink has playback support */
  4558. .ignore_pmdown_time = 1,
  4559. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4560. },
  4561. {/* hw:x,1 */
  4562. .name = MSM_DAILINK_NAME(Media2),
  4563. .stream_name = "MultiMedia2",
  4564. .cpu_dai_name = "MultiMedia2",
  4565. .platform_name = "msm-pcm-dsp.0",
  4566. .dynamic = 1,
  4567. .dpcm_playback = 1,
  4568. .dpcm_capture = 1,
  4569. .codec_dai_name = "snd-soc-dummy-dai",
  4570. .codec_name = "snd-soc-dummy",
  4571. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4572. SND_SOC_DPCM_TRIGGER_POST},
  4573. .ignore_suspend = 1,
  4574. /* this dainlink has playback support */
  4575. .ignore_pmdown_time = 1,
  4576. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4577. },
  4578. {/* hw:x,2 */
  4579. .name = "VoiceMMode1",
  4580. .stream_name = "VoiceMMode1",
  4581. .cpu_dai_name = "VoiceMMode1",
  4582. .platform_name = "msm-pcm-voice",
  4583. .dynamic = 1,
  4584. .dpcm_playback = 1,
  4585. .dpcm_capture = 1,
  4586. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4587. SND_SOC_DPCM_TRIGGER_POST},
  4588. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4589. .ignore_suspend = 1,
  4590. .ignore_pmdown_time = 1,
  4591. .codec_dai_name = "snd-soc-dummy-dai",
  4592. .codec_name = "snd-soc-dummy",
  4593. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4594. },
  4595. {/* hw:x,3 */
  4596. .name = "MSM VoIP",
  4597. .stream_name = "VoIP",
  4598. .cpu_dai_name = "VoIP",
  4599. .platform_name = "msm-voip-dsp",
  4600. .dynamic = 1,
  4601. .dpcm_playback = 1,
  4602. .dpcm_capture = 1,
  4603. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4604. SND_SOC_DPCM_TRIGGER_POST},
  4605. .codec_dai_name = "snd-soc-dummy-dai",
  4606. .codec_name = "snd-soc-dummy",
  4607. .ignore_suspend = 1,
  4608. /* this dainlink has playback support */
  4609. .ignore_pmdown_time = 1,
  4610. .id = MSM_FRONTEND_DAI_VOIP,
  4611. },
  4612. {/* hw:x,4 */
  4613. .name = MSM_DAILINK_NAME(ULL),
  4614. .stream_name = "MultiMedia3",
  4615. .cpu_dai_name = "MultiMedia3",
  4616. .platform_name = "msm-pcm-dsp.2",
  4617. .dynamic = 1,
  4618. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4619. .dpcm_playback = 1,
  4620. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4621. SND_SOC_DPCM_TRIGGER_POST},
  4622. .codec_dai_name = "snd-soc-dummy-dai",
  4623. .codec_name = "snd-soc-dummy",
  4624. .ignore_suspend = 1,
  4625. /* this dainlink has playback support */
  4626. .ignore_pmdown_time = 1,
  4627. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4628. },
  4629. {/* hw:x,5 */
  4630. .name = "MSM AFE-PCM RX",
  4631. .stream_name = "AFE-PROXY RX",
  4632. .cpu_dai_name = "msm-dai-q6-dev.241",
  4633. .codec_name = "msm-stub-codec.1",
  4634. .codec_dai_name = "msm-stub-rx",
  4635. .platform_name = "msm-pcm-afe",
  4636. .dpcm_playback = 1,
  4637. .ignore_suspend = 1,
  4638. /* this dainlink has playback support */
  4639. .ignore_pmdown_time = 1,
  4640. },
  4641. {/* hw:x,6 */
  4642. .name = "MSM AFE-PCM TX",
  4643. .stream_name = "AFE-PROXY TX",
  4644. .cpu_dai_name = "msm-dai-q6-dev.240",
  4645. .codec_name = "msm-stub-codec.1",
  4646. .codec_dai_name = "msm-stub-tx",
  4647. .platform_name = "msm-pcm-afe",
  4648. .dpcm_capture = 1,
  4649. .ignore_suspend = 1,
  4650. },
  4651. {/* hw:x,7 */
  4652. .name = MSM_DAILINK_NAME(Compress1),
  4653. .stream_name = "Compress1",
  4654. .cpu_dai_name = "MultiMedia4",
  4655. .platform_name = "msm-compress-dsp",
  4656. .dynamic = 1,
  4657. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4658. .dpcm_playback = 1,
  4659. .dpcm_capture = 1,
  4660. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4661. SND_SOC_DPCM_TRIGGER_POST},
  4662. .codec_dai_name = "snd-soc-dummy-dai",
  4663. .codec_name = "snd-soc-dummy",
  4664. .ignore_suspend = 1,
  4665. .ignore_pmdown_time = 1,
  4666. /* this dainlink has playback support */
  4667. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4668. },
  4669. /* Hostless PCM purpose */
  4670. {/* hw:x,8 */
  4671. .name = "AUXPCM Hostless",
  4672. .stream_name = "AUXPCM Hostless",
  4673. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4674. .platform_name = "msm-pcm-hostless",
  4675. .dynamic = 1,
  4676. .dpcm_playback = 1,
  4677. .dpcm_capture = 1,
  4678. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4679. SND_SOC_DPCM_TRIGGER_POST},
  4680. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4681. .ignore_suspend = 1,
  4682. /* this dainlink has playback support */
  4683. .ignore_pmdown_time = 1,
  4684. .codec_dai_name = "snd-soc-dummy-dai",
  4685. .codec_name = "snd-soc-dummy",
  4686. },
  4687. {/* hw:x,9 */
  4688. .name = MSM_DAILINK_NAME(LowLatency),
  4689. .stream_name = "MultiMedia5",
  4690. .cpu_dai_name = "MultiMedia5",
  4691. .platform_name = "msm-pcm-dsp.1",
  4692. .dynamic = 1,
  4693. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4694. .dpcm_playback = 1,
  4695. .dpcm_capture = 1,
  4696. .codec_dai_name = "snd-soc-dummy-dai",
  4697. .codec_name = "snd-soc-dummy",
  4698. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4699. SND_SOC_DPCM_TRIGGER_POST},
  4700. .ignore_suspend = 1,
  4701. /* this dainlink has playback support */
  4702. .ignore_pmdown_time = 1,
  4703. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4704. .ops = &msm_fe_qos_ops,
  4705. },
  4706. {/* hw:x,10 */
  4707. .name = "Listen 1 Audio Service",
  4708. .stream_name = "Listen 1 Audio Service",
  4709. .cpu_dai_name = "LSM1",
  4710. .platform_name = "msm-lsm-client",
  4711. .dynamic = 1,
  4712. .dpcm_capture = 1,
  4713. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4714. SND_SOC_DPCM_TRIGGER_POST },
  4715. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4716. .ignore_suspend = 1,
  4717. .codec_dai_name = "snd-soc-dummy-dai",
  4718. .codec_name = "snd-soc-dummy",
  4719. .id = MSM_FRONTEND_DAI_LSM1,
  4720. },
  4721. /* Multiple Tunnel instances */
  4722. {/* hw:x,11 */
  4723. .name = MSM_DAILINK_NAME(Compress2),
  4724. .stream_name = "Compress2",
  4725. .cpu_dai_name = "MultiMedia7",
  4726. .platform_name = "msm-compress-dsp",
  4727. .dynamic = 1,
  4728. .dpcm_playback = 1,
  4729. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4730. SND_SOC_DPCM_TRIGGER_POST},
  4731. .codec_dai_name = "snd-soc-dummy-dai",
  4732. .codec_name = "snd-soc-dummy",
  4733. .ignore_suspend = 1,
  4734. .ignore_pmdown_time = 1,
  4735. /* this dainlink has playback support */
  4736. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4737. },
  4738. {/* hw:x,12 */
  4739. .name = MSM_DAILINK_NAME(MultiMedia10),
  4740. .stream_name = "MultiMedia10",
  4741. .cpu_dai_name = "MultiMedia10",
  4742. .platform_name = "msm-pcm-dsp.1",
  4743. .dynamic = 1,
  4744. .dpcm_playback = 1,
  4745. .dpcm_capture = 1,
  4746. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4747. SND_SOC_DPCM_TRIGGER_POST},
  4748. .codec_dai_name = "snd-soc-dummy-dai",
  4749. .codec_name = "snd-soc-dummy",
  4750. .ignore_suspend = 1,
  4751. .ignore_pmdown_time = 1,
  4752. /* this dainlink has playback support */
  4753. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4754. },
  4755. {/* hw:x,13 */
  4756. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4757. .stream_name = "MM_NOIRQ",
  4758. .cpu_dai_name = "MultiMedia8",
  4759. .platform_name = "msm-pcm-dsp-noirq",
  4760. .dynamic = 1,
  4761. .dpcm_playback = 1,
  4762. .dpcm_capture = 1,
  4763. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4764. SND_SOC_DPCM_TRIGGER_POST},
  4765. .codec_dai_name = "snd-soc-dummy-dai",
  4766. .codec_name = "snd-soc-dummy",
  4767. .ignore_suspend = 1,
  4768. .ignore_pmdown_time = 1,
  4769. /* this dainlink has playback support */
  4770. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4771. .ops = &msm_fe_qos_ops,
  4772. },
  4773. /* HDMI Hostless */
  4774. {/* hw:x,14 */
  4775. .name = "HDMI_RX_HOSTLESS",
  4776. .stream_name = "HDMI_RX_HOSTLESS",
  4777. .cpu_dai_name = "HDMI_HOSTLESS",
  4778. .platform_name = "msm-pcm-hostless",
  4779. .dynamic = 1,
  4780. .dpcm_playback = 1,
  4781. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4782. SND_SOC_DPCM_TRIGGER_POST},
  4783. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4784. .ignore_suspend = 1,
  4785. .ignore_pmdown_time = 1,
  4786. .codec_dai_name = "snd-soc-dummy-dai",
  4787. .codec_name = "snd-soc-dummy",
  4788. },
  4789. {/* hw:x,15 */
  4790. .name = "VoiceMMode2",
  4791. .stream_name = "VoiceMMode2",
  4792. .cpu_dai_name = "VoiceMMode2",
  4793. .platform_name = "msm-pcm-voice",
  4794. .dynamic = 1,
  4795. .dpcm_playback = 1,
  4796. .dpcm_capture = 1,
  4797. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4798. SND_SOC_DPCM_TRIGGER_POST},
  4799. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4800. .ignore_suspend = 1,
  4801. .ignore_pmdown_time = 1,
  4802. .codec_dai_name = "snd-soc-dummy-dai",
  4803. .codec_name = "snd-soc-dummy",
  4804. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4805. },
  4806. /* LSM FE */
  4807. {/* hw:x,16 */
  4808. .name = "Listen 2 Audio Service",
  4809. .stream_name = "Listen 2 Audio Service",
  4810. .cpu_dai_name = "LSM2",
  4811. .platform_name = "msm-lsm-client",
  4812. .dynamic = 1,
  4813. .dpcm_capture = 1,
  4814. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4815. SND_SOC_DPCM_TRIGGER_POST },
  4816. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4817. .ignore_suspend = 1,
  4818. .codec_dai_name = "snd-soc-dummy-dai",
  4819. .codec_name = "snd-soc-dummy",
  4820. .id = MSM_FRONTEND_DAI_LSM2,
  4821. },
  4822. {/* hw:x,17 */
  4823. .name = "Listen 3 Audio Service",
  4824. .stream_name = "Listen 3 Audio Service",
  4825. .cpu_dai_name = "LSM3",
  4826. .platform_name = "msm-lsm-client",
  4827. .dynamic = 1,
  4828. .dpcm_capture = 1,
  4829. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4830. SND_SOC_DPCM_TRIGGER_POST },
  4831. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4832. .ignore_suspend = 1,
  4833. .codec_dai_name = "snd-soc-dummy-dai",
  4834. .codec_name = "snd-soc-dummy",
  4835. .id = MSM_FRONTEND_DAI_LSM3,
  4836. },
  4837. {/* hw:x,18 */
  4838. .name = "Listen 4 Audio Service",
  4839. .stream_name = "Listen 4 Audio Service",
  4840. .cpu_dai_name = "LSM4",
  4841. .platform_name = "msm-lsm-client",
  4842. .dynamic = 1,
  4843. .dpcm_capture = 1,
  4844. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4845. SND_SOC_DPCM_TRIGGER_POST },
  4846. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4847. .ignore_suspend = 1,
  4848. .codec_dai_name = "snd-soc-dummy-dai",
  4849. .codec_name = "snd-soc-dummy",
  4850. .id = MSM_FRONTEND_DAI_LSM4,
  4851. },
  4852. {/* hw:x,19 */
  4853. .name = "Listen 5 Audio Service",
  4854. .stream_name = "Listen 5 Audio Service",
  4855. .cpu_dai_name = "LSM5",
  4856. .platform_name = "msm-lsm-client",
  4857. .dynamic = 1,
  4858. .dpcm_capture = 1,
  4859. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4860. SND_SOC_DPCM_TRIGGER_POST },
  4861. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4862. .ignore_suspend = 1,
  4863. .codec_dai_name = "snd-soc-dummy-dai",
  4864. .codec_name = "snd-soc-dummy",
  4865. .id = MSM_FRONTEND_DAI_LSM5,
  4866. },
  4867. {/* hw:x,20 */
  4868. .name = "Listen 6 Audio Service",
  4869. .stream_name = "Listen 6 Audio Service",
  4870. .cpu_dai_name = "LSM6",
  4871. .platform_name = "msm-lsm-client",
  4872. .dynamic = 1,
  4873. .dpcm_capture = 1,
  4874. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4875. SND_SOC_DPCM_TRIGGER_POST },
  4876. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4877. .ignore_suspend = 1,
  4878. .codec_dai_name = "snd-soc-dummy-dai",
  4879. .codec_name = "snd-soc-dummy",
  4880. .id = MSM_FRONTEND_DAI_LSM6,
  4881. },
  4882. {/* hw:x,21 */
  4883. .name = "Listen 7 Audio Service",
  4884. .stream_name = "Listen 7 Audio Service",
  4885. .cpu_dai_name = "LSM7",
  4886. .platform_name = "msm-lsm-client",
  4887. .dynamic = 1,
  4888. .dpcm_capture = 1,
  4889. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4890. SND_SOC_DPCM_TRIGGER_POST },
  4891. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4892. .ignore_suspend = 1,
  4893. .codec_dai_name = "snd-soc-dummy-dai",
  4894. .codec_name = "snd-soc-dummy",
  4895. .id = MSM_FRONTEND_DAI_LSM7,
  4896. },
  4897. {/* hw:x,22 */
  4898. .name = "Listen 8 Audio Service",
  4899. .stream_name = "Listen 8 Audio Service",
  4900. .cpu_dai_name = "LSM8",
  4901. .platform_name = "msm-lsm-client",
  4902. .dynamic = 1,
  4903. .dpcm_capture = 1,
  4904. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4905. SND_SOC_DPCM_TRIGGER_POST },
  4906. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4907. .ignore_suspend = 1,
  4908. .codec_dai_name = "snd-soc-dummy-dai",
  4909. .codec_name = "snd-soc-dummy",
  4910. .id = MSM_FRONTEND_DAI_LSM8,
  4911. },
  4912. {/* hw:x,23 */
  4913. .name = MSM_DAILINK_NAME(Media9),
  4914. .stream_name = "MultiMedia9",
  4915. .cpu_dai_name = "MultiMedia9",
  4916. .platform_name = "msm-pcm-dsp.0",
  4917. .dynamic = 1,
  4918. .dpcm_playback = 1,
  4919. .dpcm_capture = 1,
  4920. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4921. SND_SOC_DPCM_TRIGGER_POST},
  4922. .codec_dai_name = "snd-soc-dummy-dai",
  4923. .codec_name = "snd-soc-dummy",
  4924. .ignore_suspend = 1,
  4925. /* this dainlink has playback support */
  4926. .ignore_pmdown_time = 1,
  4927. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4928. },
  4929. {/* hw:x,24 */
  4930. .name = MSM_DAILINK_NAME(Compress4),
  4931. .stream_name = "Compress4",
  4932. .cpu_dai_name = "MultiMedia11",
  4933. .platform_name = "msm-compress-dsp",
  4934. .dynamic = 1,
  4935. .dpcm_playback = 1,
  4936. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4937. SND_SOC_DPCM_TRIGGER_POST},
  4938. .codec_dai_name = "snd-soc-dummy-dai",
  4939. .codec_name = "snd-soc-dummy",
  4940. .ignore_suspend = 1,
  4941. .ignore_pmdown_time = 1,
  4942. /* this dainlink has playback support */
  4943. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4944. },
  4945. {/* hw:x,25 */
  4946. .name = MSM_DAILINK_NAME(Compress5),
  4947. .stream_name = "Compress5",
  4948. .cpu_dai_name = "MultiMedia12",
  4949. .platform_name = "msm-compress-dsp",
  4950. .dynamic = 1,
  4951. .dpcm_playback = 1,
  4952. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4953. SND_SOC_DPCM_TRIGGER_POST},
  4954. .codec_dai_name = "snd-soc-dummy-dai",
  4955. .codec_name = "snd-soc-dummy",
  4956. .ignore_suspend = 1,
  4957. .ignore_pmdown_time = 1,
  4958. /* this dainlink has playback support */
  4959. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4960. },
  4961. {/* hw:x,26 */
  4962. .name = MSM_DAILINK_NAME(Compress6),
  4963. .stream_name = "Compress6",
  4964. .cpu_dai_name = "MultiMedia13",
  4965. .platform_name = "msm-compress-dsp",
  4966. .dynamic = 1,
  4967. .dpcm_playback = 1,
  4968. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4969. SND_SOC_DPCM_TRIGGER_POST},
  4970. .codec_dai_name = "snd-soc-dummy-dai",
  4971. .codec_name = "snd-soc-dummy",
  4972. .ignore_suspend = 1,
  4973. .ignore_pmdown_time = 1,
  4974. /* this dainlink has playback support */
  4975. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4976. },
  4977. {/* hw:x,27 */
  4978. .name = MSM_DAILINK_NAME(Compress7),
  4979. .stream_name = "Compress7",
  4980. .cpu_dai_name = "MultiMedia14",
  4981. .platform_name = "msm-compress-dsp",
  4982. .dynamic = 1,
  4983. .dpcm_playback = 1,
  4984. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4985. SND_SOC_DPCM_TRIGGER_POST},
  4986. .codec_dai_name = "snd-soc-dummy-dai",
  4987. .codec_name = "snd-soc-dummy",
  4988. .ignore_suspend = 1,
  4989. .ignore_pmdown_time = 1,
  4990. /* this dainlink has playback support */
  4991. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4992. },
  4993. {/* hw:x,28 */
  4994. .name = MSM_DAILINK_NAME(Compress8),
  4995. .stream_name = "Compress8",
  4996. .cpu_dai_name = "MultiMedia15",
  4997. .platform_name = "msm-compress-dsp",
  4998. .dynamic = 1,
  4999. .dpcm_playback = 1,
  5000. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5001. SND_SOC_DPCM_TRIGGER_POST},
  5002. .codec_dai_name = "snd-soc-dummy-dai",
  5003. .codec_name = "snd-soc-dummy",
  5004. .ignore_suspend = 1,
  5005. .ignore_pmdown_time = 1,
  5006. /* this dainlink has playback support */
  5007. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5008. },
  5009. {/* hw:x,29 */
  5010. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5011. .stream_name = "MM_NOIRQ_2",
  5012. .cpu_dai_name = "MultiMedia16",
  5013. .platform_name = "msm-pcm-dsp-noirq",
  5014. .dynamic = 1,
  5015. .dpcm_playback = 1,
  5016. .dpcm_capture = 1,
  5017. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5018. SND_SOC_DPCM_TRIGGER_POST},
  5019. .codec_dai_name = "snd-soc-dummy-dai",
  5020. .codec_name = "snd-soc-dummy",
  5021. .ignore_suspend = 1,
  5022. .ignore_pmdown_time = 1,
  5023. /* this dainlink has playback support */
  5024. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5025. .ops = &msm_fe_qos_ops,
  5026. },
  5027. {/* hw:x,30 */
  5028. .name = "CDC_DMA Hostless",
  5029. .stream_name = "CDC_DMA Hostless",
  5030. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5031. .platform_name = "msm-pcm-hostless",
  5032. .dynamic = 1,
  5033. .dpcm_playback = 1,
  5034. .dpcm_capture = 1,
  5035. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5036. SND_SOC_DPCM_TRIGGER_POST},
  5037. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5038. .ignore_suspend = 1,
  5039. /* this dailink has playback support */
  5040. .ignore_pmdown_time = 1,
  5041. .codec_dai_name = "snd-soc-dummy-dai",
  5042. .codec_name = "snd-soc-dummy",
  5043. },
  5044. {/* hw:x,31 */
  5045. .name = "TX3_CDC_DMA Hostless",
  5046. .stream_name = "TX3_CDC_DMA Hostless",
  5047. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  5048. .platform_name = "msm-pcm-hostless",
  5049. .dynamic = 1,
  5050. .dpcm_capture = 1,
  5051. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5052. SND_SOC_DPCM_TRIGGER_POST},
  5053. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5054. .ignore_suspend = 1,
  5055. .codec_dai_name = "snd-soc-dummy-dai",
  5056. .codec_name = "snd-soc-dummy",
  5057. },
  5058. {/* hw:x,32 */
  5059. .name = "Tertiary MI2S TX_Hostless",
  5060. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  5061. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  5062. .platform_name = "msm-pcm-hostless",
  5063. .dynamic = 1,
  5064. .dpcm_capture = 1,
  5065. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5066. SND_SOC_DPCM_TRIGGER_POST},
  5067. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5068. .ignore_suspend = 1,
  5069. .ignore_pmdown_time = 1,
  5070. .codec_dai_name = "snd-soc-dummy-dai",
  5071. .codec_name = "snd-soc-dummy",
  5072. },
  5073. };
  5074. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5075. {/* hw:x,33 */
  5076. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5077. .stream_name = "WSA CDC DMA0 Capture",
  5078. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5079. .platform_name = "msm-pcm-hostless",
  5080. .codec_name = "bolero_codec",
  5081. .codec_dai_name = "wsa_macro_vifeedback",
  5082. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5083. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5084. .ignore_suspend = 1,
  5085. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5086. .ops = &msm_cdc_dma_be_ops,
  5087. },
  5088. };
  5089. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5090. {/* hw:x,34 */
  5091. .name = MSM_DAILINK_NAME(ASM Loopback),
  5092. .stream_name = "MultiMedia6",
  5093. .cpu_dai_name = "MultiMedia6",
  5094. .platform_name = "msm-pcm-loopback",
  5095. .dynamic = 1,
  5096. .dpcm_playback = 1,
  5097. .dpcm_capture = 1,
  5098. .codec_dai_name = "snd-soc-dummy-dai",
  5099. .codec_name = "snd-soc-dummy",
  5100. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5101. SND_SOC_DPCM_TRIGGER_POST},
  5102. .ignore_suspend = 1,
  5103. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5104. .ignore_pmdown_time = 1,
  5105. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5106. },
  5107. {/* hw:x,35 */
  5108. .name = "USB Audio Hostless",
  5109. .stream_name = "USB Audio Hostless",
  5110. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5111. .platform_name = "msm-pcm-hostless",
  5112. .dynamic = 1,
  5113. .dpcm_playback = 1,
  5114. .dpcm_capture = 1,
  5115. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5116. SND_SOC_DPCM_TRIGGER_POST},
  5117. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5118. .ignore_suspend = 1,
  5119. .ignore_pmdown_time = 1,
  5120. .codec_dai_name = "snd-soc-dummy-dai",
  5121. .codec_name = "snd-soc-dummy",
  5122. },
  5123. {/* hw:x,36 */
  5124. .name = "SLIMBUS_7 Hostless",
  5125. .stream_name = "SLIMBUS_7 Hostless",
  5126. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5127. .platform_name = "msm-pcm-hostless",
  5128. .dynamic = 1,
  5129. .dpcm_capture = 1,
  5130. .dpcm_playback = 1,
  5131. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5132. SND_SOC_DPCM_TRIGGER_POST},
  5133. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5134. .ignore_suspend = 1,
  5135. .ignore_pmdown_time = 1,
  5136. .codec_dai_name = "snd-soc-dummy-dai",
  5137. .codec_name = "snd-soc-dummy",
  5138. },
  5139. {/* hw:x,37 */
  5140. .name = "Compress Capture",
  5141. .stream_name = "Compress9",
  5142. .cpu_dai_name = "MultiMedia17",
  5143. .platform_name = "msm-compress-dsp",
  5144. .dynamic = 1,
  5145. .dpcm_capture = 1,
  5146. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5147. SND_SOC_DPCM_TRIGGER_POST},
  5148. .codec_dai_name = "snd-soc-dummy-dai",
  5149. .codec_name = "snd-soc-dummy",
  5150. .ignore_suspend = 1,
  5151. .ignore_pmdown_time = 1,
  5152. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  5153. },
  5154. {/* hw:x,38 */
  5155. .name = "SLIMBUS_8 Hostless",
  5156. .stream_name = "SLIMBUS_8 Hostless",
  5157. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5158. .platform_name = "msm-pcm-hostless",
  5159. .dynamic = 1,
  5160. .dpcm_capture = 1,
  5161. .dpcm_playback = 1,
  5162. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5163. SND_SOC_DPCM_TRIGGER_POST},
  5164. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5165. .ignore_suspend = 1,
  5166. .ignore_pmdown_time = 1,
  5167. .codec_dai_name = "snd-soc-dummy-dai",
  5168. .codec_name = "snd-soc-dummy",
  5169. },
  5170. {/* hw:x,39 */
  5171. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  5172. .stream_name = "TX CDC DMA5 Capture",
  5173. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  5174. .platform_name = "msm-pcm-hostless",
  5175. .codec_name = "bolero_codec",
  5176. .codec_dai_name = "tx_macro_tx3",
  5177. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  5178. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5179. .ignore_suspend = 1,
  5180. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5181. .ops = &msm_cdc_dma_be_ops,
  5182. },
  5183. };
  5184. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5185. /* Backend AFE DAI Links */
  5186. {
  5187. .name = LPASS_BE_AFE_PCM_RX,
  5188. .stream_name = "AFE Playback",
  5189. .cpu_dai_name = "msm-dai-q6-dev.224",
  5190. .platform_name = "msm-pcm-routing",
  5191. .codec_name = "msm-stub-codec.1",
  5192. .codec_dai_name = "msm-stub-rx",
  5193. .no_pcm = 1,
  5194. .dpcm_playback = 1,
  5195. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5196. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5197. /* this dainlink has playback support */
  5198. .ignore_pmdown_time = 1,
  5199. .ignore_suspend = 1,
  5200. },
  5201. {
  5202. .name = LPASS_BE_AFE_PCM_TX,
  5203. .stream_name = "AFE Capture",
  5204. .cpu_dai_name = "msm-dai-q6-dev.225",
  5205. .platform_name = "msm-pcm-routing",
  5206. .codec_name = "msm-stub-codec.1",
  5207. .codec_dai_name = "msm-stub-tx",
  5208. .no_pcm = 1,
  5209. .dpcm_capture = 1,
  5210. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5211. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5212. .ignore_suspend = 1,
  5213. },
  5214. /* Incall Record Uplink BACK END DAI Link */
  5215. {
  5216. .name = LPASS_BE_INCALL_RECORD_TX,
  5217. .stream_name = "Voice Uplink Capture",
  5218. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5219. .platform_name = "msm-pcm-routing",
  5220. .codec_name = "msm-stub-codec.1",
  5221. .codec_dai_name = "msm-stub-tx",
  5222. .no_pcm = 1,
  5223. .dpcm_capture = 1,
  5224. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5225. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5226. .ignore_suspend = 1,
  5227. },
  5228. /* Incall Record Downlink BACK END DAI Link */
  5229. {
  5230. .name = LPASS_BE_INCALL_RECORD_RX,
  5231. .stream_name = "Voice Downlink Capture",
  5232. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5233. .platform_name = "msm-pcm-routing",
  5234. .codec_name = "msm-stub-codec.1",
  5235. .codec_dai_name = "msm-stub-tx",
  5236. .no_pcm = 1,
  5237. .dpcm_capture = 1,
  5238. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5239. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5240. .ignore_suspend = 1,
  5241. },
  5242. /* Incall Music BACK END DAI Link */
  5243. {
  5244. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5245. .stream_name = "Voice Farend Playback",
  5246. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5247. .platform_name = "msm-pcm-routing",
  5248. .codec_name = "msm-stub-codec.1",
  5249. .codec_dai_name = "msm-stub-rx",
  5250. .no_pcm = 1,
  5251. .dpcm_playback = 1,
  5252. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5253. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5254. .ignore_suspend = 1,
  5255. .ignore_pmdown_time = 1,
  5256. },
  5257. /* Incall Music 2 BACK END DAI Link */
  5258. {
  5259. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5260. .stream_name = "Voice2 Farend Playback",
  5261. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5262. .platform_name = "msm-pcm-routing",
  5263. .codec_name = "msm-stub-codec.1",
  5264. .codec_dai_name = "msm-stub-rx",
  5265. .no_pcm = 1,
  5266. .dpcm_playback = 1,
  5267. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5268. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5269. .ignore_suspend = 1,
  5270. .ignore_pmdown_time = 1,
  5271. },
  5272. {
  5273. .name = LPASS_BE_USB_AUDIO_RX,
  5274. .stream_name = "USB Audio Playback",
  5275. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5276. .platform_name = "msm-pcm-routing",
  5277. .codec_name = "msm-stub-codec.1",
  5278. .codec_dai_name = "msm-stub-rx",
  5279. .dynamic_be = 1,
  5280. .no_pcm = 1,
  5281. .dpcm_playback = 1,
  5282. .id = MSM_BACKEND_DAI_USB_RX,
  5283. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5284. .ignore_pmdown_time = 1,
  5285. .ignore_suspend = 1,
  5286. },
  5287. {
  5288. .name = LPASS_BE_USB_AUDIO_TX,
  5289. .stream_name = "USB Audio Capture",
  5290. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5291. .platform_name = "msm-pcm-routing",
  5292. .codec_name = "msm-stub-codec.1",
  5293. .codec_dai_name = "msm-stub-tx",
  5294. .no_pcm = 1,
  5295. .dpcm_capture = 1,
  5296. .id = MSM_BACKEND_DAI_USB_TX,
  5297. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5298. .ignore_suspend = 1,
  5299. },
  5300. {
  5301. .name = LPASS_BE_PRI_TDM_RX_0,
  5302. .stream_name = "Primary TDM0 Playback",
  5303. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5304. .platform_name = "msm-pcm-routing",
  5305. .codec_name = "msm-stub-codec.1",
  5306. .codec_dai_name = "msm-stub-rx",
  5307. .no_pcm = 1,
  5308. .dpcm_playback = 1,
  5309. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5310. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5311. .ops = &kona_tdm_be_ops,
  5312. .ignore_suspend = 1,
  5313. .ignore_pmdown_time = 1,
  5314. },
  5315. {
  5316. .name = LPASS_BE_PRI_TDM_TX_0,
  5317. .stream_name = "Primary TDM0 Capture",
  5318. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5319. .platform_name = "msm-pcm-routing",
  5320. .codec_name = "msm-stub-codec.1",
  5321. .codec_dai_name = "msm-stub-tx",
  5322. .no_pcm = 1,
  5323. .dpcm_capture = 1,
  5324. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5325. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5326. .ops = &kona_tdm_be_ops,
  5327. .ignore_suspend = 1,
  5328. },
  5329. {
  5330. .name = LPASS_BE_SEC_TDM_RX_0,
  5331. .stream_name = "Secondary TDM0 Playback",
  5332. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5333. .platform_name = "msm-pcm-routing",
  5334. .codec_name = "msm-stub-codec.1",
  5335. .codec_dai_name = "msm-stub-rx",
  5336. .no_pcm = 1,
  5337. .dpcm_playback = 1,
  5338. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5339. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5340. .ops = &kona_tdm_be_ops,
  5341. .ignore_suspend = 1,
  5342. .ignore_pmdown_time = 1,
  5343. },
  5344. {
  5345. .name = LPASS_BE_SEC_TDM_TX_0,
  5346. .stream_name = "Secondary TDM0 Capture",
  5347. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5348. .platform_name = "msm-pcm-routing",
  5349. .codec_name = "msm-stub-codec.1",
  5350. .codec_dai_name = "msm-stub-tx",
  5351. .no_pcm = 1,
  5352. .dpcm_capture = 1,
  5353. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5354. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5355. .ops = &kona_tdm_be_ops,
  5356. .ignore_suspend = 1,
  5357. },
  5358. {
  5359. .name = LPASS_BE_TERT_TDM_RX_0,
  5360. .stream_name = "Tertiary TDM0 Playback",
  5361. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5362. .platform_name = "msm-pcm-routing",
  5363. .codec_name = "msm-stub-codec.1",
  5364. .codec_dai_name = "msm-stub-rx",
  5365. .no_pcm = 1,
  5366. .dpcm_playback = 1,
  5367. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5368. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5369. .ops = &kona_tdm_be_ops,
  5370. .ignore_suspend = 1,
  5371. .ignore_pmdown_time = 1,
  5372. },
  5373. {
  5374. .name = LPASS_BE_TERT_TDM_TX_0,
  5375. .stream_name = "Tertiary TDM0 Capture",
  5376. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5377. .platform_name = "msm-pcm-routing",
  5378. .codec_name = "msm-stub-codec.1",
  5379. .codec_dai_name = "msm-stub-tx",
  5380. .no_pcm = 1,
  5381. .dpcm_capture = 1,
  5382. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5383. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5384. .ops = &kona_tdm_be_ops,
  5385. .ignore_suspend = 1,
  5386. },
  5387. {
  5388. .name = LPASS_BE_QUAT_TDM_RX_0,
  5389. .stream_name = "Quaternary TDM0 Playback",
  5390. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5391. .platform_name = "msm-pcm-routing",
  5392. .codec_name = "msm-stub-codec.1",
  5393. .codec_dai_name = "msm-stub-rx",
  5394. .no_pcm = 1,
  5395. .dpcm_playback = 1,
  5396. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5397. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5398. .ops = &kona_tdm_be_ops,
  5399. .ignore_suspend = 1,
  5400. .ignore_pmdown_time = 1,
  5401. },
  5402. {
  5403. .name = LPASS_BE_QUAT_TDM_TX_0,
  5404. .stream_name = "Quaternary TDM0 Capture",
  5405. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5406. .platform_name = "msm-pcm-routing",
  5407. .codec_name = "msm-stub-codec.1",
  5408. .codec_dai_name = "msm-stub-tx",
  5409. .no_pcm = 1,
  5410. .dpcm_capture = 1,
  5411. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5412. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5413. .ops = &kona_tdm_be_ops,
  5414. .ignore_suspend = 1,
  5415. },
  5416. {
  5417. .name = LPASS_BE_QUIN_TDM_RX_0,
  5418. .stream_name = "Quinary TDM0 Playback",
  5419. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5420. .platform_name = "msm-pcm-routing",
  5421. .codec_name = "msm-stub-codec.1",
  5422. .codec_dai_name = "msm-stub-rx",
  5423. .no_pcm = 1,
  5424. .dpcm_playback = 1,
  5425. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5426. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5427. .ops = &kona_tdm_be_ops,
  5428. .ignore_suspend = 1,
  5429. .ignore_pmdown_time = 1,
  5430. },
  5431. {
  5432. .name = LPASS_BE_QUIN_TDM_TX_0,
  5433. .stream_name = "Quinary TDM0 Capture",
  5434. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5435. .platform_name = "msm-pcm-routing",
  5436. .codec_name = "msm-stub-codec.1",
  5437. .codec_dai_name = "msm-stub-tx",
  5438. .no_pcm = 1,
  5439. .dpcm_capture = 1,
  5440. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5441. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5442. .ops = &kona_tdm_be_ops,
  5443. .ignore_suspend = 1,
  5444. },
  5445. {
  5446. .name = LPASS_BE_SEN_TDM_RX_0,
  5447. .stream_name = "Senary TDM0 Playback",
  5448. .cpu_dai_name = "msm-dai-q6-tdm.36944",
  5449. .platform_name = "msm-pcm-routing",
  5450. .codec_name = "msm-stub-codec.1",
  5451. .codec_dai_name = "msm-stub-rx",
  5452. .no_pcm = 1,
  5453. .dpcm_playback = 1,
  5454. .id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
  5455. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5456. .ops = &kona_tdm_be_ops,
  5457. .ignore_suspend = 1,
  5458. .ignore_pmdown_time = 1,
  5459. },
  5460. {
  5461. .name = LPASS_BE_SEN_TDM_TX_0,
  5462. .stream_name = "Senary TDM0 Capture",
  5463. .cpu_dai_name = "msm-dai-q6-tdm.36945",
  5464. .platform_name = "msm-pcm-routing",
  5465. .codec_name = "msm-stub-codec.1",
  5466. .codec_dai_name = "msm-stub-tx",
  5467. .no_pcm = 1,
  5468. .dpcm_capture = 1,
  5469. .id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
  5470. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5471. .ops = &kona_tdm_be_ops,
  5472. .ignore_suspend = 1,
  5473. },
  5474. };
  5475. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5476. {
  5477. .name = LPASS_BE_SLIMBUS_7_RX,
  5478. .stream_name = "Slimbus7 Playback",
  5479. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5480. .platform_name = "msm-pcm-routing",
  5481. .codec_name = "btfmslim_slave",
  5482. /* BT codec driver determines capabilities based on
  5483. * dai name, bt codecdai name should always contains
  5484. * supported usecase information
  5485. */
  5486. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5487. .no_pcm = 1,
  5488. .dpcm_playback = 1,
  5489. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5490. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5491. .init = &msm_wcn_init,
  5492. .ops = &msm_wcn_ops,
  5493. /* dai link has playback support */
  5494. .ignore_pmdown_time = 1,
  5495. .ignore_suspend = 1,
  5496. },
  5497. {
  5498. .name = LPASS_BE_SLIMBUS_7_TX,
  5499. .stream_name = "Slimbus7 Capture",
  5500. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5501. .platform_name = "msm-pcm-routing",
  5502. .codec_name = "btfmslim_slave",
  5503. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5504. .no_pcm = 1,
  5505. .dpcm_capture = 1,
  5506. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5507. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5508. .ops = &msm_wcn_ops,
  5509. .ignore_suspend = 1,
  5510. },
  5511. };
  5512. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5513. {
  5514. .name = LPASS_BE_SLIMBUS_7_RX,
  5515. .stream_name = "Slimbus7 Playback",
  5516. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5517. .platform_name = "msm-pcm-routing",
  5518. .codec_name = "btfmslim_slave",
  5519. /* BT codec driver determines capabilities based on
  5520. * dai name, bt codecdai name should always contains
  5521. * supported usecase information
  5522. */
  5523. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5524. .no_pcm = 1,
  5525. .dpcm_playback = 1,
  5526. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5527. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5528. .init = &msm_wcn_init_lito,
  5529. .ops = &msm_wcn_ops_lito,
  5530. /* dai link has playback support */
  5531. .ignore_pmdown_time = 1,
  5532. .ignore_suspend = 1,
  5533. },
  5534. {
  5535. .name = LPASS_BE_SLIMBUS_7_TX,
  5536. .stream_name = "Slimbus7 Capture",
  5537. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5538. .platform_name = "msm-pcm-routing",
  5539. .codec_name = "btfmslim_slave",
  5540. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5541. .no_pcm = 1,
  5542. .dpcm_capture = 1,
  5543. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5544. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5545. .ops = &msm_wcn_ops_lito,
  5546. .ignore_suspend = 1,
  5547. },
  5548. {
  5549. .name = LPASS_BE_SLIMBUS_8_TX,
  5550. .stream_name = "Slimbus8 Capture",
  5551. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5552. .platform_name = "msm-pcm-routing",
  5553. .codec_name = "btfmslim_slave",
  5554. .codec_dai_name = "btfm_fm_slim_tx",
  5555. .no_pcm = 1,
  5556. .dpcm_capture = 1,
  5557. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5558. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5559. .ops = &msm_wcn_ops_lito,
  5560. .ignore_suspend = 1,
  5561. },
  5562. };
  5563. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  5564. /* DISP PORT BACK END DAI Link */
  5565. {
  5566. .name = LPASS_BE_DISPLAY_PORT,
  5567. .stream_name = "Display Port Playback",
  5568. .cpu_dai_name = "msm-dai-q6-dp.24608",
  5569. .platform_name = "msm-pcm-routing",
  5570. .codec_name = "msm-ext-disp-audio-codec-rx",
  5571. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  5572. .no_pcm = 1,
  5573. .dpcm_playback = 1,
  5574. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  5575. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5576. .ignore_pmdown_time = 1,
  5577. .ignore_suspend = 1,
  5578. },
  5579. /* DISP PORT 1 BACK END DAI Link */
  5580. {
  5581. .name = LPASS_BE_DISPLAY_PORT1,
  5582. .stream_name = "Display Port1 Playback",
  5583. .cpu_dai_name = "msm-dai-q6-dp.24608",
  5584. .platform_name = "msm-pcm-routing",
  5585. .codec_name = "msm-ext-disp-audio-codec-rx",
  5586. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  5587. .no_pcm = 1,
  5588. .dpcm_playback = 1,
  5589. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  5590. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5591. .ignore_pmdown_time = 1,
  5592. .ignore_suspend = 1,
  5593. },
  5594. };
  5595. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5596. {
  5597. .name = LPASS_BE_PRI_MI2S_RX,
  5598. .stream_name = "Primary MI2S Playback",
  5599. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5600. .platform_name = "msm-pcm-routing",
  5601. .codec_name = "msm-stub-codec.1",
  5602. .codec_dai_name = "msm-stub-rx",
  5603. .no_pcm = 1,
  5604. .dpcm_playback = 1,
  5605. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5606. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5607. .ops = &msm_mi2s_be_ops,
  5608. .ignore_suspend = 1,
  5609. .ignore_pmdown_time = 1,
  5610. },
  5611. {
  5612. .name = LPASS_BE_PRI_MI2S_TX,
  5613. .stream_name = "Primary MI2S Capture",
  5614. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5615. .platform_name = "msm-pcm-routing",
  5616. .codec_name = "msm-stub-codec.1",
  5617. .codec_dai_name = "msm-stub-tx",
  5618. .no_pcm = 1,
  5619. .dpcm_capture = 1,
  5620. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5621. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5622. .ops = &msm_mi2s_be_ops,
  5623. .ignore_suspend = 1,
  5624. },
  5625. {
  5626. .name = LPASS_BE_SEC_MI2S_RX,
  5627. .stream_name = "Secondary MI2S Playback",
  5628. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5629. .platform_name = "msm-pcm-routing",
  5630. .codec_name = "msm-stub-codec.1",
  5631. .codec_dai_name = "msm-stub-rx",
  5632. .no_pcm = 1,
  5633. .dpcm_playback = 1,
  5634. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5635. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5636. .ops = &msm_mi2s_be_ops,
  5637. .ignore_suspend = 1,
  5638. .ignore_pmdown_time = 1,
  5639. },
  5640. {
  5641. .name = LPASS_BE_SEC_MI2S_TX,
  5642. .stream_name = "Secondary MI2S Capture",
  5643. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5644. .platform_name = "msm-pcm-routing",
  5645. .codec_name = "msm-stub-codec.1",
  5646. .codec_dai_name = "msm-stub-tx",
  5647. .no_pcm = 1,
  5648. .dpcm_capture = 1,
  5649. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5650. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5651. .ops = &msm_mi2s_be_ops,
  5652. .ignore_suspend = 1,
  5653. },
  5654. {
  5655. .name = LPASS_BE_TERT_MI2S_RX,
  5656. .stream_name = "Tertiary MI2S Playback",
  5657. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5658. .platform_name = "msm-pcm-routing",
  5659. .codec_name = "msm-stub-codec.1",
  5660. .codec_dai_name = "msm-stub-rx",
  5661. .no_pcm = 1,
  5662. .dpcm_playback = 1,
  5663. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5664. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5665. .ops = &msm_mi2s_be_ops,
  5666. .ignore_suspend = 1,
  5667. .ignore_pmdown_time = 1,
  5668. },
  5669. {
  5670. .name = LPASS_BE_TERT_MI2S_TX,
  5671. .stream_name = "Tertiary MI2S Capture",
  5672. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5673. .platform_name = "msm-pcm-routing",
  5674. .codec_name = "msm-stub-codec.1",
  5675. .codec_dai_name = "msm-stub-tx",
  5676. .no_pcm = 1,
  5677. .dpcm_capture = 1,
  5678. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5679. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5680. .ops = &msm_mi2s_be_ops,
  5681. .ignore_suspend = 1,
  5682. },
  5683. {
  5684. .name = LPASS_BE_QUAT_MI2S_RX,
  5685. .stream_name = "Quaternary MI2S Playback",
  5686. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5687. .platform_name = "msm-pcm-routing",
  5688. .codec_name = "msm-stub-codec.1",
  5689. .codec_dai_name = "msm-stub-rx",
  5690. .no_pcm = 1,
  5691. .dpcm_playback = 1,
  5692. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5693. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5694. .ops = &msm_mi2s_be_ops,
  5695. .ignore_suspend = 1,
  5696. .ignore_pmdown_time = 1,
  5697. },
  5698. {
  5699. .name = LPASS_BE_QUAT_MI2S_TX,
  5700. .stream_name = "Quaternary MI2S Capture",
  5701. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5702. .platform_name = "msm-pcm-routing",
  5703. .codec_name = "msm-stub-codec.1",
  5704. .codec_dai_name = "msm-stub-tx",
  5705. .no_pcm = 1,
  5706. .dpcm_capture = 1,
  5707. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5708. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5709. .ops = &msm_mi2s_be_ops,
  5710. .ignore_suspend = 1,
  5711. },
  5712. {
  5713. .name = LPASS_BE_QUIN_MI2S_RX,
  5714. .stream_name = "Quinary MI2S Playback",
  5715. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5716. .platform_name = "msm-pcm-routing",
  5717. .codec_name = "msm-stub-codec.1",
  5718. .codec_dai_name = "msm-stub-rx",
  5719. .no_pcm = 1,
  5720. .dpcm_playback = 1,
  5721. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5722. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5723. .ops = &msm_mi2s_be_ops,
  5724. .ignore_suspend = 1,
  5725. .ignore_pmdown_time = 1,
  5726. },
  5727. {
  5728. .name = LPASS_BE_QUIN_MI2S_TX,
  5729. .stream_name = "Quinary MI2S Capture",
  5730. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5731. .platform_name = "msm-pcm-routing",
  5732. .codec_name = "msm-stub-codec.1",
  5733. .codec_dai_name = "msm-stub-tx",
  5734. .no_pcm = 1,
  5735. .dpcm_capture = 1,
  5736. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5737. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5738. .ops = &msm_mi2s_be_ops,
  5739. .ignore_suspend = 1,
  5740. },
  5741. {
  5742. .name = LPASS_BE_SENARY_MI2S_RX,
  5743. .stream_name = "Senary MI2S Playback",
  5744. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5745. .platform_name = "msm-pcm-routing",
  5746. .codec_name = "msm-stub-codec.1",
  5747. .codec_dai_name = "msm-stub-rx",
  5748. .no_pcm = 1,
  5749. .dpcm_playback = 1,
  5750. .id = MSM_BACKEND_DAI_SENARY_MI2S_RX,
  5751. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5752. .ops = &msm_mi2s_be_ops,
  5753. .ignore_suspend = 1,
  5754. .ignore_pmdown_time = 1,
  5755. },
  5756. {
  5757. .name = LPASS_BE_SENARY_MI2S_TX,
  5758. .stream_name = "Senary MI2S Capture",
  5759. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5760. .platform_name = "msm-pcm-routing",
  5761. .codec_name = "msm-stub-codec.1",
  5762. .codec_dai_name = "msm-stub-tx",
  5763. .no_pcm = 1,
  5764. .dpcm_capture = 1,
  5765. .id = MSM_BACKEND_DAI_SENARY_MI2S_TX,
  5766. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5767. .ops = &msm_mi2s_be_ops,
  5768. .ignore_suspend = 1,
  5769. },
  5770. };
  5771. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5772. /* Primary AUX PCM Backend DAI Links */
  5773. {
  5774. .name = LPASS_BE_AUXPCM_RX,
  5775. .stream_name = "AUX PCM Playback",
  5776. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5777. .platform_name = "msm-pcm-routing",
  5778. .codec_name = "msm-stub-codec.1",
  5779. .codec_dai_name = "msm-stub-rx",
  5780. .no_pcm = 1,
  5781. .dpcm_playback = 1,
  5782. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5783. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5784. .ops = &kona_aux_be_ops,
  5785. .ignore_pmdown_time = 1,
  5786. .ignore_suspend = 1,
  5787. },
  5788. {
  5789. .name = LPASS_BE_AUXPCM_TX,
  5790. .stream_name = "AUX PCM Capture",
  5791. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5792. .platform_name = "msm-pcm-routing",
  5793. .codec_name = "msm-stub-codec.1",
  5794. .codec_dai_name = "msm-stub-tx",
  5795. .no_pcm = 1,
  5796. .dpcm_capture = 1,
  5797. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5798. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5799. .ops = &kona_aux_be_ops,
  5800. .ignore_suspend = 1,
  5801. },
  5802. /* Secondary AUX PCM Backend DAI Links */
  5803. {
  5804. .name = LPASS_BE_SEC_AUXPCM_RX,
  5805. .stream_name = "Sec AUX PCM Playback",
  5806. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5807. .platform_name = "msm-pcm-routing",
  5808. .codec_name = "msm-stub-codec.1",
  5809. .codec_dai_name = "msm-stub-rx",
  5810. .no_pcm = 1,
  5811. .dpcm_playback = 1,
  5812. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5813. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5814. .ops = &kona_aux_be_ops,
  5815. .ignore_pmdown_time = 1,
  5816. .ignore_suspend = 1,
  5817. },
  5818. {
  5819. .name = LPASS_BE_SEC_AUXPCM_TX,
  5820. .stream_name = "Sec AUX PCM Capture",
  5821. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5822. .platform_name = "msm-pcm-routing",
  5823. .codec_name = "msm-stub-codec.1",
  5824. .codec_dai_name = "msm-stub-tx",
  5825. .no_pcm = 1,
  5826. .dpcm_capture = 1,
  5827. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5828. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5829. .ops = &kona_aux_be_ops,
  5830. .ignore_suspend = 1,
  5831. },
  5832. /* Tertiary AUX PCM Backend DAI Links */
  5833. {
  5834. .name = LPASS_BE_TERT_AUXPCM_RX,
  5835. .stream_name = "Tert AUX PCM Playback",
  5836. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5837. .platform_name = "msm-pcm-routing",
  5838. .codec_name = "msm-stub-codec.1",
  5839. .codec_dai_name = "msm-stub-rx",
  5840. .no_pcm = 1,
  5841. .dpcm_playback = 1,
  5842. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5843. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5844. .ops = &kona_aux_be_ops,
  5845. .ignore_suspend = 1,
  5846. },
  5847. {
  5848. .name = LPASS_BE_TERT_AUXPCM_TX,
  5849. .stream_name = "Tert AUX PCM Capture",
  5850. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5851. .platform_name = "msm-pcm-routing",
  5852. .codec_name = "msm-stub-codec.1",
  5853. .codec_dai_name = "msm-stub-tx",
  5854. .no_pcm = 1,
  5855. .dpcm_capture = 1,
  5856. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5857. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5858. .ops = &kona_aux_be_ops,
  5859. .ignore_suspend = 1,
  5860. },
  5861. /* Quaternary AUX PCM Backend DAI Links */
  5862. {
  5863. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5864. .stream_name = "Quat AUX PCM Playback",
  5865. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5866. .platform_name = "msm-pcm-routing",
  5867. .codec_name = "msm-stub-codec.1",
  5868. .codec_dai_name = "msm-stub-rx",
  5869. .no_pcm = 1,
  5870. .dpcm_playback = 1,
  5871. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5872. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5873. .ops = &kona_aux_be_ops,
  5874. .ignore_suspend = 1,
  5875. },
  5876. {
  5877. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5878. .stream_name = "Quat AUX PCM Capture",
  5879. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5880. .platform_name = "msm-pcm-routing",
  5881. .codec_name = "msm-stub-codec.1",
  5882. .codec_dai_name = "msm-stub-tx",
  5883. .no_pcm = 1,
  5884. .dpcm_capture = 1,
  5885. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5886. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5887. .ops = &kona_aux_be_ops,
  5888. .ignore_suspend = 1,
  5889. },
  5890. /* Quinary AUX PCM Backend DAI Links */
  5891. {
  5892. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5893. .stream_name = "Quin AUX PCM Playback",
  5894. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5895. .platform_name = "msm-pcm-routing",
  5896. .codec_name = "msm-stub-codec.1",
  5897. .codec_dai_name = "msm-stub-rx",
  5898. .no_pcm = 1,
  5899. .dpcm_playback = 1,
  5900. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5901. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5902. .ops = &kona_aux_be_ops,
  5903. .ignore_suspend = 1,
  5904. },
  5905. {
  5906. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5907. .stream_name = "Quin AUX PCM Capture",
  5908. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5909. .platform_name = "msm-pcm-routing",
  5910. .codec_name = "msm-stub-codec.1",
  5911. .codec_dai_name = "msm-stub-tx",
  5912. .no_pcm = 1,
  5913. .dpcm_capture = 1,
  5914. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5915. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5916. .ops = &kona_aux_be_ops,
  5917. .ignore_suspend = 1,
  5918. },
  5919. /* Senary AUX PCM Backend DAI Links */
  5920. {
  5921. .name = LPASS_BE_SEN_AUXPCM_RX,
  5922. .stream_name = "Sen AUX PCM Playback",
  5923. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  5924. .platform_name = "msm-pcm-routing",
  5925. .codec_name = "msm-stub-codec.1",
  5926. .codec_dai_name = "msm-stub-rx",
  5927. .no_pcm = 1,
  5928. .dpcm_playback = 1,
  5929. .id = MSM_BACKEND_DAI_SEN_AUXPCM_RX,
  5930. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5931. .ops = &kona_aux_be_ops,
  5932. .ignore_suspend = 1,
  5933. },
  5934. {
  5935. .name = LPASS_BE_SEN_AUXPCM_TX,
  5936. .stream_name = "Sen AUX PCM Capture",
  5937. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  5938. .platform_name = "msm-pcm-routing",
  5939. .codec_name = "msm-stub-codec.1",
  5940. .codec_dai_name = "msm-stub-tx",
  5941. .no_pcm = 1,
  5942. .dpcm_capture = 1,
  5943. .id = MSM_BACKEND_DAI_SEN_AUXPCM_TX,
  5944. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5945. .ops = &kona_aux_be_ops,
  5946. .ignore_suspend = 1,
  5947. },
  5948. };
  5949. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5950. /* WSA CDC DMA Backend DAI Links */
  5951. {
  5952. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5953. .stream_name = "WSA CDC DMA0 Playback",
  5954. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  5955. .platform_name = "msm-pcm-routing",
  5956. .codec_name = "bolero_codec",
  5957. .codec_dai_name = "wsa_macro_rx1",
  5958. .no_pcm = 1,
  5959. .dpcm_playback = 1,
  5960. .init = &msm_int_audrx_init,
  5961. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5962. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5963. .ignore_pmdown_time = 1,
  5964. .ignore_suspend = 1,
  5965. .ops = &msm_cdc_dma_be_ops,
  5966. },
  5967. {
  5968. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5969. .stream_name = "WSA CDC DMA1 Playback",
  5970. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  5971. .platform_name = "msm-pcm-routing",
  5972. .codec_name = "bolero_codec",
  5973. .codec_dai_name = "wsa_macro_rx_mix",
  5974. .no_pcm = 1,
  5975. .dpcm_playback = 1,
  5976. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5977. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5978. .ignore_pmdown_time = 1,
  5979. .ignore_suspend = 1,
  5980. .ops = &msm_cdc_dma_be_ops,
  5981. },
  5982. {
  5983. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5984. .stream_name = "WSA CDC DMA1 Capture",
  5985. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  5986. .platform_name = "msm-pcm-routing",
  5987. .codec_name = "bolero_codec",
  5988. .codec_dai_name = "wsa_macro_echo",
  5989. .no_pcm = 1,
  5990. .dpcm_capture = 1,
  5991. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5992. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5993. .ignore_suspend = 1,
  5994. .ops = &msm_cdc_dma_be_ops,
  5995. },
  5996. };
  5997. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5998. /* RX CDC DMA Backend DAI Links */
  5999. {
  6000. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  6001. .stream_name = "RX CDC DMA0 Playback",
  6002. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  6003. .platform_name = "msm-pcm-routing",
  6004. .codec_name = "bolero_codec",
  6005. .codec_dai_name = "rx_macro_rx1",
  6006. .dynamic_be = 1,
  6007. .no_pcm = 1,
  6008. .dpcm_playback = 1,
  6009. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  6010. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6011. .ignore_pmdown_time = 1,
  6012. .ignore_suspend = 1,
  6013. .ops = &msm_cdc_dma_be_ops,
  6014. },
  6015. {
  6016. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  6017. .stream_name = "RX CDC DMA1 Playback",
  6018. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  6019. .platform_name = "msm-pcm-routing",
  6020. .codec_name = "bolero_codec",
  6021. .codec_dai_name = "rx_macro_rx2",
  6022. .dynamic_be = 1,
  6023. .no_pcm = 1,
  6024. .dpcm_playback = 1,
  6025. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  6026. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6027. .ignore_pmdown_time = 1,
  6028. .ignore_suspend = 1,
  6029. .ops = &msm_cdc_dma_be_ops,
  6030. },
  6031. {
  6032. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  6033. .stream_name = "RX CDC DMA2 Playback",
  6034. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  6035. .platform_name = "msm-pcm-routing",
  6036. .codec_name = "bolero_codec",
  6037. .codec_dai_name = "rx_macro_rx3",
  6038. .dynamic_be = 1,
  6039. .no_pcm = 1,
  6040. .dpcm_playback = 1,
  6041. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  6042. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6043. .ignore_pmdown_time = 1,
  6044. .ignore_suspend = 1,
  6045. .ops = &msm_cdc_dma_be_ops,
  6046. },
  6047. {
  6048. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  6049. .stream_name = "RX CDC DMA3 Playback",
  6050. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  6051. .platform_name = "msm-pcm-routing",
  6052. .codec_name = "bolero_codec",
  6053. .codec_dai_name = "rx_macro_rx4",
  6054. .dynamic_be = 1,
  6055. .no_pcm = 1,
  6056. .dpcm_playback = 1,
  6057. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  6058. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6059. .ignore_pmdown_time = 1,
  6060. .ignore_suspend = 1,
  6061. .ops = &msm_cdc_dma_be_ops,
  6062. },
  6063. /* TX CDC DMA Backend DAI Links */
  6064. {
  6065. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  6066. .stream_name = "TX CDC DMA3 Capture",
  6067. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  6068. .platform_name = "msm-pcm-routing",
  6069. .codec_name = "bolero_codec",
  6070. .codec_dai_name = "tx_macro_tx1",
  6071. .no_pcm = 1,
  6072. .dpcm_capture = 1,
  6073. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  6074. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6075. .ignore_suspend = 1,
  6076. .ops = &msm_cdc_dma_be_ops,
  6077. },
  6078. {
  6079. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  6080. .stream_name = "TX CDC DMA4 Capture",
  6081. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  6082. .platform_name = "msm-pcm-routing",
  6083. .codec_name = "bolero_codec",
  6084. .codec_dai_name = "tx_macro_tx2",
  6085. .no_pcm = 1,
  6086. .dpcm_capture = 1,
  6087. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  6088. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6089. .ignore_suspend = 1,
  6090. .ops = &msm_cdc_dma_be_ops,
  6091. },
  6092. };
  6093. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6094. {
  6095. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6096. .stream_name = "VA CDC DMA0 Capture",
  6097. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6098. .platform_name = "msm-pcm-routing",
  6099. .codec_name = "bolero_codec",
  6100. .codec_dai_name = "va_macro_tx1",
  6101. .no_pcm = 1,
  6102. .dpcm_capture = 1,
  6103. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6104. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6105. .ignore_suspend = 1,
  6106. .ops = &msm_cdc_dma_be_ops,
  6107. },
  6108. {
  6109. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6110. .stream_name = "VA CDC DMA1 Capture",
  6111. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6112. .platform_name = "msm-pcm-routing",
  6113. .codec_name = "bolero_codec",
  6114. .codec_dai_name = "va_macro_tx2",
  6115. .no_pcm = 1,
  6116. .dpcm_capture = 1,
  6117. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6118. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6119. .ignore_suspend = 1,
  6120. .ops = &msm_cdc_dma_be_ops,
  6121. },
  6122. {
  6123. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  6124. .stream_name = "VA CDC DMA2 Capture",
  6125. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  6126. .platform_name = "msm-pcm-routing",
  6127. .codec_name = "bolero_codec",
  6128. .codec_dai_name = "va_macro_tx3",
  6129. .no_pcm = 1,
  6130. .dpcm_capture = 1,
  6131. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  6132. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6133. .ignore_suspend = 1,
  6134. .ops = &msm_cdc_dma_be_ops,
  6135. },
  6136. };
  6137. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6138. {
  6139. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6140. .stream_name = "AFE Loopback Capture",
  6141. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6142. .platform_name = "msm-pcm-routing",
  6143. .codec_name = "msm-stub-codec.1",
  6144. .codec_dai_name = "msm-stub-tx",
  6145. .no_pcm = 1,
  6146. .dpcm_capture = 1,
  6147. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6148. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6149. .ignore_pmdown_time = 1,
  6150. .ignore_suspend = 1,
  6151. },
  6152. };
  6153. static struct snd_soc_dai_link msm_kona_dai_links[
  6154. ARRAY_SIZE(msm_common_dai_links) +
  6155. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6156. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6157. ARRAY_SIZE(msm_common_be_dai_links) +
  6158. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6159. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6160. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6161. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  6162. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6163. ARRAY_SIZE(ext_disp_be_dai_link) +
  6164. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6165. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  6166. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  6167. static int msm_populate_dai_link_component_of_node(
  6168. struct snd_soc_card *card)
  6169. {
  6170. int i, index, ret = 0;
  6171. struct device *cdev = card->dev;
  6172. struct snd_soc_dai_link *dai_link = card->dai_link;
  6173. struct device_node *np;
  6174. if (!cdev) {
  6175. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  6176. return -ENODEV;
  6177. }
  6178. for (i = 0; i < card->num_links; i++) {
  6179. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6180. continue;
  6181. /* populate platform_of_node for snd card dai links */
  6182. if (dai_link[i].platform_name &&
  6183. !dai_link[i].platform_of_node) {
  6184. index = of_property_match_string(cdev->of_node,
  6185. "asoc-platform-names",
  6186. dai_link[i].platform_name);
  6187. if (index < 0) {
  6188. dev_err(cdev, "%s: No match found for platform name: %s\n",
  6189. __func__, dai_link[i].platform_name);
  6190. ret = index;
  6191. goto err;
  6192. }
  6193. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6194. index);
  6195. if (!np) {
  6196. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  6197. __func__, dai_link[i].platform_name,
  6198. index);
  6199. ret = -ENODEV;
  6200. goto err;
  6201. }
  6202. dai_link[i].platform_of_node = np;
  6203. dai_link[i].platform_name = NULL;
  6204. }
  6205. /* populate cpu_of_node for snd card dai links */
  6206. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6207. index = of_property_match_string(cdev->of_node,
  6208. "asoc-cpu-names",
  6209. dai_link[i].cpu_dai_name);
  6210. if (index >= 0) {
  6211. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6212. index);
  6213. if (!np) {
  6214. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  6215. __func__,
  6216. dai_link[i].cpu_dai_name);
  6217. ret = -ENODEV;
  6218. goto err;
  6219. }
  6220. dai_link[i].cpu_of_node = np;
  6221. dai_link[i].cpu_dai_name = NULL;
  6222. }
  6223. }
  6224. /* populate codec_of_node for snd card dai links */
  6225. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6226. index = of_property_match_string(cdev->of_node,
  6227. "asoc-codec-names",
  6228. dai_link[i].codec_name);
  6229. if (index < 0)
  6230. continue;
  6231. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6232. index);
  6233. if (!np) {
  6234. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  6235. __func__, dai_link[i].codec_name);
  6236. ret = -ENODEV;
  6237. goto err;
  6238. }
  6239. dai_link[i].codec_of_node = np;
  6240. dai_link[i].codec_name = NULL;
  6241. }
  6242. }
  6243. err:
  6244. return ret;
  6245. }
  6246. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6247. {
  6248. int ret = -EINVAL;
  6249. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  6250. if (!component) {
  6251. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  6252. return ret;
  6253. }
  6254. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  6255. ARRAY_SIZE(msm_snd_controls));
  6256. if (ret < 0) {
  6257. dev_err(component->dev,
  6258. "%s: add_codec_controls failed, err = %d\n",
  6259. __func__, ret);
  6260. return ret;
  6261. }
  6262. return ret;
  6263. }
  6264. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6265. struct snd_pcm_hw_params *params)
  6266. {
  6267. return 0;
  6268. }
  6269. static struct snd_soc_ops msm_stub_be_ops = {
  6270. .hw_params = msm_snd_stub_hw_params,
  6271. };
  6272. struct snd_soc_card snd_soc_card_stub_msm = {
  6273. .name = "kona-stub-snd-card",
  6274. };
  6275. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6276. /* FrontEnd DAI Links */
  6277. {
  6278. .name = "MSMSTUB Media1",
  6279. .stream_name = "MultiMedia1",
  6280. .cpu_dai_name = "MultiMedia1",
  6281. .platform_name = "msm-pcm-dsp.0",
  6282. .dynamic = 1,
  6283. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6284. .dpcm_playback = 1,
  6285. .dpcm_capture = 1,
  6286. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6287. SND_SOC_DPCM_TRIGGER_POST},
  6288. .codec_dai_name = "snd-soc-dummy-dai",
  6289. .codec_name = "snd-soc-dummy",
  6290. .ignore_suspend = 1,
  6291. /* this dainlink has playback support */
  6292. .ignore_pmdown_time = 1,
  6293. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6294. },
  6295. };
  6296. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6297. /* Backend DAI Links */
  6298. {
  6299. .name = LPASS_BE_AUXPCM_RX,
  6300. .stream_name = "AUX PCM Playback",
  6301. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6302. .platform_name = "msm-pcm-routing",
  6303. .codec_name = "msm-stub-codec.1",
  6304. .codec_dai_name = "msm-stub-rx",
  6305. .no_pcm = 1,
  6306. .dpcm_playback = 1,
  6307. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6308. .init = &msm_audrx_stub_init,
  6309. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6310. .ignore_pmdown_time = 1,
  6311. .ignore_suspend = 1,
  6312. .ops = &msm_stub_be_ops,
  6313. },
  6314. {
  6315. .name = LPASS_BE_AUXPCM_TX,
  6316. .stream_name = "AUX PCM Capture",
  6317. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6318. .platform_name = "msm-pcm-routing",
  6319. .codec_name = "msm-stub-codec.1",
  6320. .codec_dai_name = "msm-stub-tx",
  6321. .no_pcm = 1,
  6322. .dpcm_capture = 1,
  6323. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6324. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6325. .ignore_suspend = 1,
  6326. .ops = &msm_stub_be_ops,
  6327. },
  6328. };
  6329. static struct snd_soc_dai_link msm_stub_dai_links[
  6330. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6331. ARRAY_SIZE(msm_stub_be_dai_links)];
  6332. static const struct of_device_id kona_asoc_machine_of_match[] = {
  6333. { .compatible = "qcom,kona-asoc-snd",
  6334. .data = "codec"},
  6335. { .compatible = "qcom,kona-asoc-snd-stub",
  6336. .data = "stub_codec"},
  6337. {},
  6338. };
  6339. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6340. {
  6341. struct snd_soc_card *card = NULL;
  6342. struct snd_soc_dai_link *dailink = NULL;
  6343. int len_1 = 0;
  6344. int len_2 = 0;
  6345. int total_links = 0;
  6346. int rc = 0;
  6347. u32 mi2s_audio_intf = 0;
  6348. u32 auxpcm_audio_intf = 0;
  6349. u32 val = 0;
  6350. u32 wcn_btfm_intf = 0;
  6351. const struct of_device_id *match;
  6352. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  6353. if (!match) {
  6354. dev_err(dev, "%s: No DT match found for sound card\n",
  6355. __func__);
  6356. return NULL;
  6357. }
  6358. if (!strcmp(match->data, "codec")) {
  6359. card = &snd_soc_card_kona_msm;
  6360. memcpy(msm_kona_dai_links + total_links,
  6361. msm_common_dai_links,
  6362. sizeof(msm_common_dai_links));
  6363. total_links += ARRAY_SIZE(msm_common_dai_links);
  6364. memcpy(msm_kona_dai_links + total_links,
  6365. msm_bolero_fe_dai_links,
  6366. sizeof(msm_bolero_fe_dai_links));
  6367. total_links +=
  6368. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6369. memcpy(msm_kona_dai_links + total_links,
  6370. msm_common_misc_fe_dai_links,
  6371. sizeof(msm_common_misc_fe_dai_links));
  6372. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6373. memcpy(msm_kona_dai_links + total_links,
  6374. msm_common_be_dai_links,
  6375. sizeof(msm_common_be_dai_links));
  6376. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6377. memcpy(msm_kona_dai_links + total_links,
  6378. msm_wsa_cdc_dma_be_dai_links,
  6379. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6380. total_links +=
  6381. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6382. memcpy(msm_kona_dai_links + total_links,
  6383. msm_rx_tx_cdc_dma_be_dai_links,
  6384. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  6385. total_links +=
  6386. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  6387. memcpy(msm_kona_dai_links + total_links,
  6388. msm_va_cdc_dma_be_dai_links,
  6389. sizeof(msm_va_cdc_dma_be_dai_links));
  6390. total_links +=
  6391. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6392. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6393. &mi2s_audio_intf);
  6394. if (rc) {
  6395. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6396. __func__);
  6397. } else {
  6398. if (mi2s_audio_intf) {
  6399. memcpy(msm_kona_dai_links + total_links,
  6400. msm_mi2s_be_dai_links,
  6401. sizeof(msm_mi2s_be_dai_links));
  6402. total_links +=
  6403. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6404. }
  6405. }
  6406. rc = of_property_read_u32(dev->of_node,
  6407. "qcom,auxpcm-audio-intf",
  6408. &auxpcm_audio_intf);
  6409. if (rc) {
  6410. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6411. __func__);
  6412. } else {
  6413. if (auxpcm_audio_intf) {
  6414. memcpy(msm_kona_dai_links + total_links,
  6415. msm_auxpcm_be_dai_links,
  6416. sizeof(msm_auxpcm_be_dai_links));
  6417. total_links +=
  6418. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6419. }
  6420. }
  6421. rc = of_property_read_u32(dev->of_node,
  6422. "qcom,ext-disp-audio-rx", &val);
  6423. if (!rc && val) {
  6424. dev_dbg(dev, "%s(): ext disp audio support present\n",
  6425. __func__);
  6426. memcpy(msm_kona_dai_links + total_links,
  6427. ext_disp_be_dai_link,
  6428. sizeof(ext_disp_be_dai_link));
  6429. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  6430. }
  6431. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  6432. if (!rc && val) {
  6433. dev_dbg(dev, "%s(): WCN BT support present\n",
  6434. __func__);
  6435. memcpy(msm_kona_dai_links + total_links,
  6436. msm_wcn_be_dai_links,
  6437. sizeof(msm_wcn_be_dai_links));
  6438. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  6439. }
  6440. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  6441. &val);
  6442. if (!rc && val) {
  6443. memcpy(msm_kona_dai_links + total_links,
  6444. msm_afe_rxtx_lb_be_dai_link,
  6445. sizeof(msm_afe_rxtx_lb_be_dai_link));
  6446. total_links +=
  6447. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  6448. }
  6449. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6450. &wcn_btfm_intf);
  6451. if (rc) {
  6452. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  6453. __func__);
  6454. } else {
  6455. if (wcn_btfm_intf) {
  6456. memcpy(msm_kona_dai_links + total_links,
  6457. msm_wcn_btfm_be_dai_links,
  6458. sizeof(msm_wcn_btfm_be_dai_links));
  6459. total_links +=
  6460. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  6461. }
  6462. }
  6463. dailink = msm_kona_dai_links;
  6464. } else if(!strcmp(match->data, "stub_codec")) {
  6465. card = &snd_soc_card_stub_msm;
  6466. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  6467. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  6468. memcpy(msm_stub_dai_links,
  6469. msm_stub_fe_dai_links,
  6470. sizeof(msm_stub_fe_dai_links));
  6471. memcpy(msm_stub_dai_links + len_1,
  6472. msm_stub_be_dai_links,
  6473. sizeof(msm_stub_be_dai_links));
  6474. dailink = msm_stub_dai_links;
  6475. total_links = len_2;
  6476. }
  6477. if (card) {
  6478. card->dai_link = dailink;
  6479. card->num_links = total_links;
  6480. }
  6481. return card;
  6482. }
  6483. static int msm_wsa881x_init(struct snd_soc_component *component)
  6484. {
  6485. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6486. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6487. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6488. SPKR_L_BOOST, SPKR_L_VI};
  6489. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6490. SPKR_R_BOOST, SPKR_R_VI};
  6491. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6492. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6493. struct msm_asoc_mach_data *pdata;
  6494. struct snd_soc_dapm_context *dapm;
  6495. struct snd_card *card;
  6496. struct snd_info_entry *entry;
  6497. int ret = 0;
  6498. if (!component) {
  6499. pr_err("%s component is NULL\n", __func__);
  6500. return -EINVAL;
  6501. }
  6502. card = component->card->snd_card;
  6503. dapm = snd_soc_component_get_dapm(component);
  6504. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6505. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  6506. __func__, component->name);
  6507. wsa881x_set_channel_map(component, &spkleft_ports[0],
  6508. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6509. &ch_rate[0], &spkleft_port_types[0]);
  6510. if (dapm->component) {
  6511. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6512. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6513. }
  6514. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6515. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  6516. __func__, component->name);
  6517. wsa881x_set_channel_map(component, &spkright_ports[0],
  6518. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6519. &ch_rate[0], &spkright_port_types[0]);
  6520. if (dapm->component) {
  6521. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6522. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6523. }
  6524. } else {
  6525. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  6526. component->name);
  6527. ret = -EINVAL;
  6528. goto err;
  6529. }
  6530. pdata = snd_soc_card_get_drvdata(component->card);
  6531. if (!pdata->codec_root) {
  6532. entry = snd_info_create_subdir(card->module, "codecs",
  6533. card->proc_root);
  6534. if (!entry) {
  6535. pr_err("%s: Cannot create codecs module entry\n",
  6536. __func__);
  6537. ret = 0;
  6538. goto err;
  6539. }
  6540. pdata->codec_root = entry;
  6541. }
  6542. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6543. component);
  6544. err:
  6545. return ret;
  6546. }
  6547. static int msm_aux_codec_init(struct snd_soc_component *component)
  6548. {
  6549. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  6550. int ret = 0;
  6551. void *mbhc_calibration;
  6552. struct snd_info_entry *entry;
  6553. struct snd_card *card = component->card->snd_card;
  6554. struct msm_asoc_mach_data *pdata;
  6555. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  6556. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  6557. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  6558. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  6559. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  6560. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  6561. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  6562. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  6563. snd_soc_dapm_sync(dapm);
  6564. pdata = snd_soc_card_get_drvdata(component->card);
  6565. if (!pdata->codec_root) {
  6566. entry = snd_info_create_subdir(card->module, "codecs",
  6567. card->proc_root);
  6568. if (!entry) {
  6569. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  6570. __func__);
  6571. ret = 0;
  6572. goto mbhc_cfg_cal;
  6573. }
  6574. pdata->codec_root = entry;
  6575. }
  6576. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  6577. mbhc_cfg_cal:
  6578. mbhc_calibration = def_wcd_mbhc_cal();
  6579. if (!mbhc_calibration)
  6580. return -ENOMEM;
  6581. wcd_mbhc_cfg.calibration = mbhc_calibration;
  6582. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  6583. if (ret) {
  6584. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  6585. __func__, ret);
  6586. goto err_hs_detect;
  6587. }
  6588. return 0;
  6589. err_hs_detect:
  6590. kfree(mbhc_calibration);
  6591. return ret;
  6592. }
  6593. static int msm_init_aux_dev(struct platform_device *pdev,
  6594. struct snd_soc_card *card)
  6595. {
  6596. struct device_node *wsa_of_node;
  6597. struct device_node *aux_codec_of_node;
  6598. u32 wsa_max_devs;
  6599. u32 wsa_dev_cnt;
  6600. u32 codec_max_aux_devs = 0;
  6601. u32 codec_aux_dev_cnt = 0;
  6602. int i;
  6603. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6604. struct aux_codec_dev_info *aux_cdc_dev_info;
  6605. const char *auxdev_name_prefix[1];
  6606. char *dev_name_str = NULL;
  6607. int found = 0;
  6608. int codecs_found = 0;
  6609. int ret = 0;
  6610. /* Get maximum WSA device count for this platform */
  6611. ret = of_property_read_u32(pdev->dev.of_node,
  6612. "qcom,wsa-max-devs", &wsa_max_devs);
  6613. if (ret) {
  6614. dev_info(&pdev->dev,
  6615. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6616. __func__, pdev->dev.of_node->full_name, ret);
  6617. wsa_max_devs = 0;
  6618. goto codec_aux_dev;
  6619. }
  6620. if (wsa_max_devs == 0) {
  6621. dev_warn(&pdev->dev,
  6622. "%s: Max WSA devices is 0 for this target?\n",
  6623. __func__);
  6624. goto codec_aux_dev;
  6625. }
  6626. /* Get count of WSA device phandles for this platform */
  6627. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6628. "qcom,wsa-devs", NULL);
  6629. if (wsa_dev_cnt == -ENOENT) {
  6630. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6631. __func__);
  6632. goto err;
  6633. } else if (wsa_dev_cnt <= 0) {
  6634. dev_err(&pdev->dev,
  6635. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6636. __func__, wsa_dev_cnt);
  6637. ret = -EINVAL;
  6638. goto err;
  6639. }
  6640. /*
  6641. * Expect total phandles count to be NOT less than maximum possible
  6642. * WSA count. However, if it is less, then assign same value to
  6643. * max count as well.
  6644. */
  6645. if (wsa_dev_cnt < wsa_max_devs) {
  6646. dev_dbg(&pdev->dev,
  6647. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6648. __func__, wsa_max_devs, wsa_dev_cnt);
  6649. wsa_max_devs = wsa_dev_cnt;
  6650. }
  6651. /* Make sure prefix string passed for each WSA device */
  6652. ret = of_property_count_strings(pdev->dev.of_node,
  6653. "qcom,wsa-aux-dev-prefix");
  6654. if (ret != wsa_dev_cnt) {
  6655. dev_err(&pdev->dev,
  6656. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6657. __func__, wsa_dev_cnt, ret);
  6658. ret = -EINVAL;
  6659. goto err;
  6660. }
  6661. /*
  6662. * Alloc mem to store phandle and index info of WSA device, if already
  6663. * registered with ALSA core
  6664. */
  6665. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6666. sizeof(struct msm_wsa881x_dev_info),
  6667. GFP_KERNEL);
  6668. if (!wsa881x_dev_info) {
  6669. ret = -ENOMEM;
  6670. goto err;
  6671. }
  6672. /*
  6673. * search and check whether all WSA devices are already
  6674. * registered with ALSA core or not. If found a node, store
  6675. * the node and the index in a local array of struct for later
  6676. * use.
  6677. */
  6678. for (i = 0; i < wsa_dev_cnt; i++) {
  6679. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6680. "qcom,wsa-devs", i);
  6681. if (unlikely(!wsa_of_node)) {
  6682. /* we should not be here */
  6683. dev_err(&pdev->dev,
  6684. "%s: wsa dev node is not present\n",
  6685. __func__);
  6686. ret = -EINVAL;
  6687. goto err;
  6688. }
  6689. if (soc_find_component(wsa_of_node, NULL)) {
  6690. /* WSA device registered with ALSA core */
  6691. wsa881x_dev_info[found].of_node = wsa_of_node;
  6692. wsa881x_dev_info[found].index = i;
  6693. found++;
  6694. if (found == wsa_max_devs)
  6695. break;
  6696. }
  6697. }
  6698. if (found < wsa_max_devs) {
  6699. dev_dbg(&pdev->dev,
  6700. "%s: failed to find %d components. Found only %d\n",
  6701. __func__, wsa_max_devs, found);
  6702. return -EPROBE_DEFER;
  6703. }
  6704. dev_info(&pdev->dev,
  6705. "%s: found %d wsa881x devices registered with ALSA core\n",
  6706. __func__, found);
  6707. codec_aux_dev:
  6708. /* Get maximum aux codec device count for this platform */
  6709. ret = of_property_read_u32(pdev->dev.of_node,
  6710. "qcom,codec-max-aux-devs",
  6711. &codec_max_aux_devs);
  6712. if (ret) {
  6713. dev_err(&pdev->dev,
  6714. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  6715. __func__, pdev->dev.of_node->full_name, ret);
  6716. codec_max_aux_devs = 0;
  6717. goto aux_dev_register;
  6718. }
  6719. if (codec_max_aux_devs == 0) {
  6720. dev_dbg(&pdev->dev,
  6721. "%s: Max aux codec devices is 0 for this target?\n",
  6722. __func__);
  6723. goto aux_dev_register;
  6724. }
  6725. /* Get count of aux codec device phandles for this platform */
  6726. codec_aux_dev_cnt = of_count_phandle_with_args(
  6727. pdev->dev.of_node,
  6728. "qcom,codec-aux-devs", NULL);
  6729. if (codec_aux_dev_cnt == -ENOENT) {
  6730. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  6731. __func__);
  6732. goto err;
  6733. } else if (codec_aux_dev_cnt <= 0) {
  6734. dev_err(&pdev->dev,
  6735. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  6736. __func__, codec_aux_dev_cnt);
  6737. ret = -EINVAL;
  6738. goto err;
  6739. }
  6740. /*
  6741. * Expect total phandles count to be NOT less than maximum possible
  6742. * AUX device count. However, if it is less, then assign same value to
  6743. * max count as well.
  6744. */
  6745. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  6746. dev_dbg(&pdev->dev,
  6747. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  6748. __func__, codec_max_aux_devs,
  6749. codec_aux_dev_cnt);
  6750. codec_max_aux_devs = codec_aux_dev_cnt;
  6751. }
  6752. /*
  6753. * Alloc mem to store phandle and index info of aux codec
  6754. * if already registered with ALSA core
  6755. */
  6756. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  6757. sizeof(struct aux_codec_dev_info),
  6758. GFP_KERNEL);
  6759. if (!aux_cdc_dev_info) {
  6760. ret = -ENOMEM;
  6761. goto err;
  6762. }
  6763. /*
  6764. * search and check whether all aux codecs are already
  6765. * registered with ALSA core or not. If found a node, store
  6766. * the node and the index in a local array of struct for later
  6767. * use.
  6768. */
  6769. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6770. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  6771. "qcom,codec-aux-devs", i);
  6772. if (unlikely(!aux_codec_of_node)) {
  6773. /* we should not be here */
  6774. dev_err(&pdev->dev,
  6775. "%s: aux codec dev node is not present\n",
  6776. __func__);
  6777. ret = -EINVAL;
  6778. goto err;
  6779. }
  6780. if (soc_find_component(aux_codec_of_node, NULL)) {
  6781. /* AUX codec registered with ALSA core */
  6782. aux_cdc_dev_info[codecs_found].of_node =
  6783. aux_codec_of_node;
  6784. aux_cdc_dev_info[codecs_found].index = i;
  6785. codecs_found++;
  6786. }
  6787. }
  6788. if (codecs_found < codec_aux_dev_cnt) {
  6789. dev_dbg(&pdev->dev,
  6790. "%s: failed to find %d components. Found only %d\n",
  6791. __func__, codec_aux_dev_cnt, codecs_found);
  6792. return -EPROBE_DEFER;
  6793. }
  6794. dev_info(&pdev->dev,
  6795. "%s: found %d AUX codecs registered with ALSA core\n",
  6796. __func__, codecs_found);
  6797. aux_dev_register:
  6798. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  6799. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  6800. /* Alloc array of AUX devs struct */
  6801. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6802. sizeof(struct snd_soc_aux_dev),
  6803. GFP_KERNEL);
  6804. if (!msm_aux_dev) {
  6805. ret = -ENOMEM;
  6806. goto err;
  6807. }
  6808. /* Alloc array of codec conf struct */
  6809. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  6810. sizeof(struct snd_soc_codec_conf),
  6811. GFP_KERNEL);
  6812. if (!msm_codec_conf) {
  6813. ret = -ENOMEM;
  6814. goto err;
  6815. }
  6816. for (i = 0; i < wsa_max_devs; i++) {
  6817. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6818. GFP_KERNEL);
  6819. if (!dev_name_str) {
  6820. ret = -ENOMEM;
  6821. goto err;
  6822. }
  6823. ret = of_property_read_string_index(pdev->dev.of_node,
  6824. "qcom,wsa-aux-dev-prefix",
  6825. wsa881x_dev_info[i].index,
  6826. auxdev_name_prefix);
  6827. if (ret) {
  6828. dev_err(&pdev->dev,
  6829. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6830. __func__, ret);
  6831. ret = -EINVAL;
  6832. goto err;
  6833. }
  6834. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6835. msm_aux_dev[i].name = dev_name_str;
  6836. msm_aux_dev[i].codec_name = NULL;
  6837. msm_aux_dev[i].codec_of_node =
  6838. wsa881x_dev_info[i].of_node;
  6839. msm_aux_dev[i].init = msm_wsa881x_init;
  6840. msm_codec_conf[i].dev_name = NULL;
  6841. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  6842. msm_codec_conf[i].of_node =
  6843. wsa881x_dev_info[i].of_node;
  6844. }
  6845. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6846. msm_aux_dev[wsa_max_devs + i].name = NULL;
  6847. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  6848. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  6849. aux_cdc_dev_info[i].of_node;
  6850. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  6851. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  6852. msm_codec_conf[wsa_max_devs + i].name_prefix =
  6853. NULL;
  6854. msm_codec_conf[wsa_max_devs + i].of_node =
  6855. aux_cdc_dev_info[i].of_node;
  6856. }
  6857. card->codec_conf = msm_codec_conf;
  6858. card->aux_dev = msm_aux_dev;
  6859. err:
  6860. return ret;
  6861. }
  6862. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6863. {
  6864. int count = 0;
  6865. u32 mi2s_master_slave[MI2S_MAX];
  6866. int ret = 0;
  6867. for (count = 0; count < MI2S_MAX; count++) {
  6868. mutex_init(&mi2s_intf_conf[count].lock);
  6869. mi2s_intf_conf[count].ref_cnt = 0;
  6870. }
  6871. ret = of_property_read_u32_array(pdev->dev.of_node,
  6872. "qcom,msm-mi2s-master",
  6873. mi2s_master_slave, MI2S_MAX);
  6874. if (ret) {
  6875. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6876. __func__);
  6877. } else {
  6878. for (count = 0; count < MI2S_MAX; count++) {
  6879. mi2s_intf_conf[count].msm_is_mi2s_master =
  6880. mi2s_master_slave[count];
  6881. }
  6882. }
  6883. }
  6884. static void msm_i2s_auxpcm_deinit(void)
  6885. {
  6886. int count = 0;
  6887. for (count = 0; count < MI2S_MAX; count++) {
  6888. mutex_destroy(&mi2s_intf_conf[count].lock);
  6889. mi2s_intf_conf[count].ref_cnt = 0;
  6890. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6891. }
  6892. }
  6893. static int kona_ssr_enable(struct device *dev, void *data)
  6894. {
  6895. struct platform_device *pdev = to_platform_device(dev);
  6896. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6897. int ret = 0;
  6898. if (!card) {
  6899. dev_err(dev, "%s: card is NULL\n", __func__);
  6900. ret = -EINVAL;
  6901. goto err;
  6902. }
  6903. if (!strcmp(card->name, "kona-stub-snd-card")) {
  6904. /* TODO */
  6905. dev_dbg(dev, "%s: TODO \n", __func__);
  6906. }
  6907. snd_soc_card_change_online_state(card, 1);
  6908. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  6909. err:
  6910. return ret;
  6911. }
  6912. static void kona_ssr_disable(struct device *dev, void *data)
  6913. {
  6914. struct platform_device *pdev = to_platform_device(dev);
  6915. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6916. if (!card) {
  6917. dev_err(dev, "%s: card is NULL\n", __func__);
  6918. return;
  6919. }
  6920. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  6921. snd_soc_card_change_online_state(card, 0);
  6922. if (!strcmp(card->name, "kona-stub-snd-card")) {
  6923. /* TODO */
  6924. dev_dbg(dev, "%s: TODO \n", __func__);
  6925. }
  6926. }
  6927. static const struct snd_event_ops kona_ssr_ops = {
  6928. .enable = kona_ssr_enable,
  6929. .disable = kona_ssr_disable,
  6930. };
  6931. static int msm_audio_ssr_compare(struct device *dev, void *data)
  6932. {
  6933. struct device_node *node = data;
  6934. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  6935. __func__, dev->of_node, node);
  6936. return (dev->of_node && dev->of_node == node);
  6937. }
  6938. static int msm_audio_ssr_register(struct device *dev)
  6939. {
  6940. struct device_node *np = dev->of_node;
  6941. struct snd_event_clients *ssr_clients = NULL;
  6942. struct device_node *node = NULL;
  6943. int ret = 0;
  6944. int i = 0;
  6945. for (i = 0; ; i++) {
  6946. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  6947. if (!node)
  6948. break;
  6949. snd_event_mstr_add_client(&ssr_clients,
  6950. msm_audio_ssr_compare, node);
  6951. }
  6952. ret = snd_event_master_register(dev, &kona_ssr_ops,
  6953. ssr_clients, NULL);
  6954. if (!ret)
  6955. snd_event_notify(dev, SND_EVENT_UP);
  6956. return ret;
  6957. }
  6958. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6959. {
  6960. struct snd_soc_card *card = NULL;
  6961. struct msm_asoc_mach_data *pdata = NULL;
  6962. const char *mbhc_audio_jack_type = NULL;
  6963. int ret = 0;
  6964. uint index = 0;
  6965. if (!pdev->dev.of_node) {
  6966. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  6967. return -EINVAL;
  6968. }
  6969. pdata = devm_kzalloc(&pdev->dev,
  6970. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6971. if (!pdata)
  6972. return -ENOMEM;
  6973. card = populate_snd_card_dailinks(&pdev->dev);
  6974. if (!card) {
  6975. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6976. ret = -EINVAL;
  6977. goto err;
  6978. }
  6979. card->dev = &pdev->dev;
  6980. platform_set_drvdata(pdev, card);
  6981. snd_soc_card_set_drvdata(card, pdata);
  6982. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6983. if (ret) {
  6984. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  6985. __func__, ret);
  6986. goto err;
  6987. }
  6988. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6989. if (ret) {
  6990. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  6991. __func__, ret);
  6992. goto err;
  6993. }
  6994. ret = msm_populate_dai_link_component_of_node(card);
  6995. if (ret) {
  6996. ret = -EPROBE_DEFER;
  6997. goto err;
  6998. }
  6999. ret = msm_init_aux_dev(pdev, card);
  7000. if (ret)
  7001. goto err;
  7002. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7003. if (ret == -EPROBE_DEFER) {
  7004. if (codec_reg_done)
  7005. ret = -EINVAL;
  7006. goto err;
  7007. } else if (ret) {
  7008. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  7009. __func__, ret);
  7010. goto err;
  7011. }
  7012. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  7013. __func__, card->name);
  7014. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7015. "qcom,hph-en1-gpio", 0);
  7016. if (!pdata->hph_en1_gpio_p) {
  7017. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7018. __func__, "qcom,hph-en1-gpio",
  7019. pdev->dev.of_node->full_name);
  7020. }
  7021. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7022. "qcom,hph-en0-gpio", 0);
  7023. if (!pdata->hph_en0_gpio_p) {
  7024. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7025. __func__, "qcom,hph-en0-gpio",
  7026. pdev->dev.of_node->full_name);
  7027. }
  7028. ret = of_property_read_string(pdev->dev.of_node,
  7029. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  7030. if (ret) {
  7031. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  7032. __func__, "qcom,mbhc-audio-jack-type",
  7033. pdev->dev.of_node->full_name);
  7034. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  7035. } else {
  7036. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  7037. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7038. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  7039. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  7040. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7041. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  7042. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  7043. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7044. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  7045. } else {
  7046. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7047. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  7048. }
  7049. }
  7050. /*
  7051. * Parse US-Euro gpio info from DT. Report no error if us-euro
  7052. * entry is not found in DT file as some targets do not support
  7053. * US-Euro detection
  7054. */
  7055. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7056. "qcom,us-euro-gpios", 0);
  7057. if (!pdata->us_euro_gpio_p) {
  7058. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  7059. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  7060. } else {
  7061. dev_dbg(&pdev->dev, "%s detected\n",
  7062. "qcom,us-euro-gpios");
  7063. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  7064. }
  7065. if (wcd_mbhc_cfg.enable_usbc_analog)
  7066. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  7067. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  7068. "fsa4480-i2c-handle", 0);
  7069. if (!pdata->fsa_handle)
  7070. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  7071. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  7072. msm_i2s_auxpcm_init(pdev);
  7073. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7074. "qcom,cdc-dmic01-gpios",
  7075. 0);
  7076. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7077. "qcom,cdc-dmic23-gpios",
  7078. 0);
  7079. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7080. "qcom,cdc-dmic45-gpios",
  7081. 0);
  7082. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7083. "qcom,pri-mi2s-gpios", 0);
  7084. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7085. "qcom,sec-mi2s-gpios", 0);
  7086. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7087. "qcom,tert-mi2s-gpios", 0);
  7088. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7089. "qcom,quat-mi2s-gpios", 0);
  7090. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7091. "qcom,quin-mi2s-gpios", 0);
  7092. pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7093. "qcom,sen-mi2s-gpios", 0);
  7094. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  7095. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  7096. ret = msm_audio_ssr_register(&pdev->dev);
  7097. if (ret)
  7098. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  7099. __func__, ret);
  7100. is_initial_boot = true;
  7101. return 0;
  7102. err:
  7103. devm_kfree(&pdev->dev, pdata);
  7104. return ret;
  7105. }
  7106. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7107. {
  7108. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7109. snd_event_master_deregister(&pdev->dev);
  7110. snd_soc_unregister_card(card);
  7111. msm_i2s_auxpcm_deinit();
  7112. return 0;
  7113. }
  7114. static struct platform_driver kona_asoc_machine_driver = {
  7115. .driver = {
  7116. .name = DRV_NAME,
  7117. .owner = THIS_MODULE,
  7118. .pm = &snd_soc_pm_ops,
  7119. .of_match_table = kona_asoc_machine_of_match,
  7120. .suppress_bind_attrs = true,
  7121. },
  7122. .probe = msm_asoc_machine_probe,
  7123. .remove = msm_asoc_machine_remove,
  7124. };
  7125. module_platform_driver(kona_asoc_machine_driver);
  7126. MODULE_DESCRIPTION("ALSA SoC msm");
  7127. MODULE_LICENSE("GPL v2");
  7128. MODULE_ALIAS("platform:" DRV_NAME);
  7129. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);