wcd938x.c 84 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "internal.h"
  23. #include "wcd938x-registers.h"
  24. #define WCD938X_DRV_NAME "wcd938x_codec"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VERSION_1_0 1
  27. #define WCD938X_VERSION_ENTRY_SIZE 32
  28. #define ADC_MODE_VAL_HIFI 0x01
  29. #define ADC_MODE_VAL_LO_HIF 0x02
  30. #define ADC_MODE_VAL_NORMAL 0x03
  31. #define ADC_MODE_VAL_LP 0x05
  32. #define ADC_MODE_VAL_ULP1 0x09
  33. #define ADC_MODE_VAL_ULP2 0x0B
  34. enum {
  35. WCD9380 = 0,
  36. WCD9385 = 5,
  37. };
  38. enum {
  39. CODEC_TX = 0,
  40. CODEC_RX,
  41. };
  42. enum {
  43. WCD_ADC1 = 0,
  44. WCD_ADC2,
  45. WCD_ADC3,
  46. WCD_ADC4,
  47. ALLOW_BUCK_DISABLE,
  48. HPH_COMP_DELAY,
  49. HPH_PA_DELAY,
  50. };
  51. enum {
  52. ADC_MODE_INVALID = 0,
  53. ADC_MODE_HIFI,
  54. ADC_MODE_LO_HIF,
  55. ADC_MODE_NORMAL,
  56. ADC_MODE_LP,
  57. ADC_MODE_ULP1,
  58. ADC_MODE_ULP2,
  59. };
  60. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  61. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  62. static int wcd938x_handle_post_irq(void *data);
  63. static int wcd938x_reset(struct device *dev);
  64. static int wcd938x_reset_low(struct device *dev);
  65. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  66. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  67. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  68. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  69. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  70. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  71. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  72. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  73. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  74. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  75. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  76. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  77. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  78. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  79. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  80. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  81. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  82. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  83. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  84. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  85. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  86. };
  87. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  88. .name = "wcd938x",
  89. .irqs = wcd938x_irqs,
  90. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  91. .num_regs = 3,
  92. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  93. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  94. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  95. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  96. .use_ack = 1,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd938x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static int wcd938x_handle_post_irq(void *data)
  102. {
  103. struct wcd938x_priv *wcd938x = data;
  104. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  105. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  106. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  107. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  108. wcd938x->tx_swr_dev->slave_irq_pending =
  109. ((sts1 || sts2 || sts3) ? true : false);
  110. return IRQ_HANDLED;
  111. }
  112. static int wcd938x_init_reg(struct snd_soc_component *component)
  113. {
  114. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  115. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  116. /* 1 msec delay as per HW requirement */
  117. usleep_range(1000, 1010);
  118. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  119. /* 1 msec delay as per HW requirement */
  120. usleep_range(1000, 1010);
  121. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  122. 0x10, 0x00);
  123. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  124. 0xF0, 0x80);
  125. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  126. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  127. /* 10 msec delay as per HW requirement */
  128. usleep_range(10000, 10010);
  129. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  130. snd_soc_component_update_bits(component, WCD938X_HPH_OCP_CTL,
  131. 0xFF, 0x3A);
  132. snd_soc_component_update_bits(component, WCD938X_RX_OCP_CTL,
  133. 0x0F, 0x02);
  134. snd_soc_component_update_bits(component, WCD938X_HPH_R_TEST,
  135. 0x01, 0x01);
  136. snd_soc_component_update_bits(component, WCD938X_HPH_L_TEST,
  137. 0x01, 0x01);
  138. snd_soc_component_update_bits(component,
  139. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  140. 0xF0, 0x00);
  141. snd_soc_component_update_bits(component,
  142. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  143. 0x1F, 0x15);
  144. snd_soc_component_update_bits(component,
  145. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  146. 0x1F, 0x15);
  147. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  148. 0xC0, 0x80);
  149. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  150. 0x02, 0x02);
  151. return 0;
  152. }
  153. static int wcd938x_set_port_params(struct snd_soc_component *component,
  154. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  155. u8 *ch_mask, u32 *ch_rate,
  156. u8 *port_type, u8 path)
  157. {
  158. int i, j;
  159. u8 num_ports = 0;
  160. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  161. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  162. switch (path) {
  163. case CODEC_RX:
  164. map = &wcd938x->rx_port_mapping;
  165. num_ports = wcd938x->num_rx_ports;
  166. break;
  167. case CODEC_TX:
  168. map = &wcd938x->tx_port_mapping;
  169. num_ports = wcd938x->num_tx_ports;
  170. break;
  171. default:
  172. dev_err(component->dev, "%s Invalid path selected %u\n",
  173. __func__, path);
  174. return -EINVAL;
  175. }
  176. for (i = 0; i <= num_ports; i++) {
  177. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  178. if ((*map)[i][j].slave_port_type == slv_prt_type)
  179. goto found;
  180. }
  181. }
  182. found:
  183. if (i > num_ports || j == MAX_CH_PER_PORT) {
  184. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  185. __func__, slv_prt_type);
  186. return -EINVAL;
  187. }
  188. *port_id = i;
  189. *num_ch = (*map)[i][j].num_ch;
  190. *ch_mask = (*map)[i][j].ch_mask;
  191. *ch_rate = (*map)[i][j].ch_rate;
  192. *port_type = (*map)[i][j].master_port_type;
  193. return 0;
  194. }
  195. static int wcd938x_parse_port_mapping(struct device *dev,
  196. char *prop, u8 path)
  197. {
  198. u32 *dt_array, map_size, map_length;
  199. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  200. u32 slave_port_type, master_port_type;
  201. u32 i, ch_iter = 0;
  202. int ret = 0;
  203. u8 *num_ports = NULL;
  204. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  205. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  206. switch (path) {
  207. case CODEC_RX:
  208. map = &wcd938x->rx_port_mapping;
  209. num_ports = &wcd938x->num_rx_ports;
  210. break;
  211. case CODEC_TX:
  212. map = &wcd938x->tx_port_mapping;
  213. num_ports = &wcd938x->num_tx_ports;
  214. break;
  215. default:
  216. dev_err(dev, "%s Invalid path selected %u\n",
  217. __func__, path);
  218. return -EINVAL;
  219. }
  220. if (!of_find_property(dev->of_node, prop,
  221. &map_size)) {
  222. dev_err(dev, "missing port mapping prop %s\n", prop);
  223. ret = -EINVAL;
  224. goto err_port_map;
  225. }
  226. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  227. dt_array = kzalloc(map_size, GFP_KERNEL);
  228. if (!dt_array) {
  229. ret = -ENOMEM;
  230. goto err_alloc;
  231. }
  232. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  233. NUM_SWRS_DT_PARAMS * map_length);
  234. if (ret) {
  235. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  236. __func__, prop);
  237. goto err_pdata_fail;
  238. }
  239. for (i = 0; i < map_length; i++) {
  240. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  241. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  242. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  243. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  244. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  245. if (port_num != old_port_num)
  246. ch_iter = 0;
  247. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  248. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  249. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  250. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  251. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  252. old_port_num = port_num;
  253. }
  254. *num_ports = port_num;
  255. kfree(dt_array);
  256. return 0;
  257. err_pdata_fail:
  258. kfree(dt_array);
  259. err_alloc:
  260. err_port_map:
  261. return ret;
  262. }
  263. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  264. u8 slv_port_type, u8 enable)
  265. {
  266. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  267. u8 port_id, num_ch, ch_mask, port_type;
  268. u32 ch_rate;
  269. u8 num_port = 1;
  270. int ret = 0;
  271. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  272. &num_ch, &ch_mask, &ch_rate,
  273. &port_type, CODEC_TX);
  274. if (ret)
  275. return ret;
  276. if (enable)
  277. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  278. num_port, &ch_mask, &ch_rate,
  279. &num_ch, &port_type);
  280. else
  281. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  282. num_port, &ch_mask, &port_type);
  283. return ret;
  284. }
  285. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  286. u8 slv_port_type, u8 enable)
  287. {
  288. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  289. u8 port_id, num_ch, ch_mask, port_type;
  290. u32 ch_rate;
  291. u8 num_port = 1;
  292. int ret = 0;
  293. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  294. &num_ch, &ch_mask, &ch_rate,
  295. &port_type, CODEC_RX);
  296. if (ret)
  297. return ret;
  298. if (enable)
  299. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  300. num_port, &ch_mask, &ch_rate,
  301. &num_ch, &port_type);
  302. else
  303. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  304. num_port, &ch_mask, &port_type);
  305. return ret;
  306. }
  307. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  308. {
  309. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  310. if (wcd938x->rx_clk_cnt == 0) {
  311. snd_soc_component_update_bits(component,
  312. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  313. snd_soc_component_update_bits(component,
  314. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  315. snd_soc_component_update_bits(component,
  316. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  317. snd_soc_component_update_bits(component,
  318. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  319. snd_soc_component_update_bits(component,
  320. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  321. snd_soc_component_update_bits(component,
  322. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  323. }
  324. wcd938x->rx_clk_cnt++;
  325. return 0;
  326. }
  327. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  328. {
  329. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  330. wcd938x->rx_clk_cnt--;
  331. if (wcd938x->rx_clk_cnt == 0) {
  332. snd_soc_component_update_bits(component,
  333. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  334. snd_soc_component_update_bits(component,
  335. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  336. snd_soc_component_update_bits(component,
  337. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  338. snd_soc_component_update_bits(component,
  339. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  340. snd_soc_component_update_bits(component,
  341. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  342. }
  343. return 0;
  344. }
  345. /*
  346. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  347. * @component: handle to snd_soc_component *
  348. *
  349. * return wcd938x_mbhc handle or error code in case of failure
  350. */
  351. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  352. {
  353. struct wcd938x_priv *wcd938x;
  354. if (!component) {
  355. pr_err("%s: Invalid params, NULL component\n", __func__);
  356. return NULL;
  357. }
  358. wcd938x = snd_soc_component_get_drvdata(component);
  359. if (!wcd938x) {
  360. pr_err("%s: wcd938x is NULL\n", __func__);
  361. return NULL;
  362. }
  363. return wcd938x->mbhc;
  364. }
  365. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  366. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  367. struct snd_kcontrol *kcontrol,
  368. int event)
  369. {
  370. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  371. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  372. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  373. w->name, event);
  374. switch (event) {
  375. case SND_SOC_DAPM_PRE_PMU:
  376. wcd938x_rx_clk_enable(component);
  377. snd_soc_component_update_bits(component,
  378. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  379. snd_soc_component_update_bits(component,
  380. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  381. snd_soc_component_update_bits(component,
  382. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  383. break;
  384. case SND_SOC_DAPM_POST_PMU:
  385. snd_soc_component_update_bits(component,
  386. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  387. if (wcd938x->comp1_enable) {
  388. snd_soc_component_update_bits(component,
  389. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  390. /* 5msec compander delay as per HW requirement */
  391. if (!wcd938x->comp2_enable ||
  392. (snd_soc_component_read32(component,
  393. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  394. usleep_range(5000, 5010);
  395. snd_soc_component_update_bits(component,
  396. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  397. } else {
  398. snd_soc_component_update_bits(component,
  399. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  400. 0x02, 0x00);
  401. snd_soc_component_update_bits(component,
  402. WCD938X_HPH_L_EN, 0x20, 0x20);
  403. }
  404. break;
  405. case SND_SOC_DAPM_POST_PMD:
  406. snd_soc_component_update_bits(component,
  407. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  408. 0x0F, 0x01);
  409. break;
  410. }
  411. return 0;
  412. }
  413. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  414. struct snd_kcontrol *kcontrol,
  415. int event)
  416. {
  417. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  418. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  419. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  420. w->name, event);
  421. switch (event) {
  422. case SND_SOC_DAPM_PRE_PMU:
  423. wcd938x_rx_clk_enable(component);
  424. snd_soc_component_update_bits(component,
  425. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  426. snd_soc_component_update_bits(component,
  427. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  428. snd_soc_component_update_bits(component,
  429. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  430. break;
  431. case SND_SOC_DAPM_POST_PMU:
  432. snd_soc_component_update_bits(component,
  433. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  434. if (wcd938x->comp2_enable) {
  435. snd_soc_component_update_bits(component,
  436. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  437. /* 5msec compander delay as per HW requirement */
  438. if (!wcd938x->comp1_enable ||
  439. (snd_soc_component_read32(component,
  440. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  441. usleep_range(5000, 5010);
  442. snd_soc_component_update_bits(component,
  443. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  444. } else {
  445. snd_soc_component_update_bits(component,
  446. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  447. 0x01, 0x00);
  448. snd_soc_component_update_bits(component,
  449. WCD938X_HPH_R_EN, 0x20, 0x20);
  450. }
  451. break;
  452. case SND_SOC_DAPM_POST_PMD:
  453. snd_soc_component_update_bits(component,
  454. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  455. 0x0F, 0x01);
  456. break;
  457. }
  458. return 0;
  459. }
  460. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  461. struct snd_kcontrol *kcontrol,
  462. int event)
  463. {
  464. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  465. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  466. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  467. w->name, event);
  468. switch (event) {
  469. case SND_SOC_DAPM_PRE_PMU:
  470. wcd938x_rx_clk_enable(component);
  471. snd_soc_component_update_bits(component,
  472. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  473. snd_soc_component_update_bits(component,
  474. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  475. snd_soc_component_update_bits(component,
  476. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  477. /* 5 msec delay as per HW requirement */
  478. usleep_range(5000, 5010);
  479. snd_soc_component_update_bits(component, WCD938X_FLYBACK_EN,
  480. 0x04, 0x00);
  481. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  482. WCD_CLSH_EVENT_PRE_DAC,
  483. WCD_CLSH_STATE_EAR,
  484. wcd938x->hph_mode);
  485. break;
  486. case SND_SOC_DAPM_POST_PMD:
  487. break;
  488. };
  489. return 0;
  490. }
  491. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  492. struct snd_kcontrol *kcontrol,
  493. int event)
  494. {
  495. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  496. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  497. int ret = 0;
  498. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  499. w->name, event);
  500. switch (event) {
  501. case SND_SOC_DAPM_PRE_PMU:
  502. wcd938x_rx_clk_enable(component);
  503. snd_soc_component_update_bits(component,
  504. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  505. snd_soc_component_update_bits(component,
  506. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  507. snd_soc_component_update_bits(component,
  508. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  509. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  510. WCD_CLSH_EVENT_PRE_DAC,
  511. WCD_CLSH_STATE_AUX,
  512. wcd938x->hph_mode);
  513. break;
  514. case SND_SOC_DAPM_POST_PMD:
  515. wcd938x_rx_clk_disable(component);
  516. snd_soc_component_update_bits(component,
  517. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  518. break;
  519. };
  520. return ret;
  521. }
  522. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  523. struct snd_kcontrol *kcontrol,
  524. int event)
  525. {
  526. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  528. int ret = 0;
  529. int hph_mode = wcd938x->hph_mode;
  530. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  531. w->name, event);
  532. switch (event) {
  533. case SND_SOC_DAPM_PRE_PMU:
  534. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  535. wcd938x->rx_swr_dev->dev_num,
  536. true);
  537. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  538. WCD_CLSH_EVENT_PRE_DAC,
  539. WCD_CLSH_STATE_HPHR,
  540. hph_mode);
  541. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  542. 0x10, 0x10);
  543. /* 100 usec delay as per HW requirement */
  544. usleep_range(100, 110);
  545. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  546. break;
  547. case SND_SOC_DAPM_POST_PMU:
  548. /*
  549. * 7ms sleep is required if compander is enabled as per
  550. * HW requirement. If compander is disabled, then
  551. * 20ms delay is required.
  552. */
  553. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  554. if (!wcd938x->comp2_enable)
  555. usleep_range(20000, 20100);
  556. else
  557. usleep_range(7000, 7100);
  558. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  559. }
  560. snd_soc_component_update_bits(component,
  561. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  562. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  563. snd_soc_component_update_bits(component,
  564. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  565. if (wcd938x->update_wcd_event)
  566. wcd938x->update_wcd_event(wcd938x->handle,
  567. WCD_BOLERO_EVT_RX_MUTE,
  568. (WCD_RX2 << 0x10));
  569. break;
  570. case SND_SOC_DAPM_PRE_PMD:
  571. if (wcd938x->update_wcd_event)
  572. wcd938x->update_wcd_event(wcd938x->handle,
  573. WCD_BOLERO_EVT_RX_MUTE,
  574. (WCD_RX2 << 0x10 | 0x1));
  575. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  576. WCD_EVENT_PRE_HPHR_PA_OFF,
  577. &wcd938x->mbhc->wcd_mbhc);
  578. break;
  579. case SND_SOC_DAPM_POST_PMD:
  580. /* 7 msec delay as per HW requirement */
  581. usleep_range(7000, 7010);
  582. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  583. WCD_EVENT_POST_HPHR_PA_OFF,
  584. &wcd938x->mbhc->wcd_mbhc);
  585. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  586. 0x10, 0x00);
  587. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  588. WCD_CLSH_EVENT_POST_PA,
  589. WCD_CLSH_STATE_HPHR,
  590. hph_mode);
  591. break;
  592. };
  593. return ret;
  594. }
  595. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  596. struct snd_kcontrol *kcontrol,
  597. int event)
  598. {
  599. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  600. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  601. int ret = 0;
  602. int hph_mode = wcd938x->hph_mode;
  603. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  604. w->name, event);
  605. switch (event) {
  606. case SND_SOC_DAPM_PRE_PMU:
  607. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  608. wcd938x->rx_swr_dev->dev_num,
  609. true);
  610. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  611. WCD_CLSH_EVENT_PRE_DAC,
  612. WCD_CLSH_STATE_HPHL,
  613. hph_mode);
  614. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  615. 0x20, 0x20);
  616. /* 100 usec delay as per HW requirement */
  617. usleep_range(100, 110);
  618. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  619. break;
  620. case SND_SOC_DAPM_POST_PMU:
  621. /*
  622. * 7ms sleep is required if compander is enabled as per
  623. * HW requirement. If compander is disabled, then
  624. * 20ms delay is required.
  625. */
  626. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  627. if (!wcd938x->comp1_enable)
  628. usleep_range(20000, 20100);
  629. else
  630. usleep_range(7000, 7100);
  631. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  632. }
  633. snd_soc_component_update_bits(component,
  634. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  635. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  636. snd_soc_component_update_bits(component,
  637. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  638. if (wcd938x->update_wcd_event)
  639. wcd938x->update_wcd_event(wcd938x->handle,
  640. WCD_BOLERO_EVT_RX_MUTE,
  641. (WCD_RX1 << 0x10));
  642. break;
  643. case SND_SOC_DAPM_PRE_PMD:
  644. if (wcd938x->update_wcd_event)
  645. wcd938x->update_wcd_event(wcd938x->handle,
  646. WCD_BOLERO_EVT_RX_MUTE,
  647. (WCD_RX1 << 0x10 | 0x1));
  648. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  649. WCD_EVENT_PRE_HPHL_PA_OFF,
  650. &wcd938x->mbhc->wcd_mbhc);
  651. break;
  652. case SND_SOC_DAPM_POST_PMD:
  653. /* 7 msec delay as per HW requirement */
  654. usleep_range(7000, 7010);
  655. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  656. WCD_EVENT_POST_HPHL_PA_OFF,
  657. &wcd938x->mbhc->wcd_mbhc);
  658. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  659. 0x20, 0x00);
  660. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  661. WCD_CLSH_EVENT_POST_PA,
  662. WCD_CLSH_STATE_HPHL,
  663. hph_mode);
  664. break;
  665. };
  666. return ret;
  667. }
  668. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  669. struct snd_kcontrol *kcontrol,
  670. int event)
  671. {
  672. struct snd_soc_component *component =
  673. snd_soc_dapm_to_component(w->dapm);
  674. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  675. int hph_mode = wcd938x->hph_mode;
  676. int ret = 0;
  677. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  678. w->name, event);
  679. switch (event) {
  680. case SND_SOC_DAPM_PRE_PMU:
  681. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  682. wcd938x->rx_swr_dev->dev_num,
  683. true);
  684. break;
  685. case SND_SOC_DAPM_POST_PMU:
  686. /* 1 msec delay as per HW requirement */
  687. usleep_range(1000, 1010);
  688. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  689. snd_soc_component_update_bits(component,
  690. WCD938X_ANA_RX_SUPPLIES,
  691. 0x20, 0x20);
  692. if (wcd938x->update_wcd_event)
  693. wcd938x->update_wcd_event(wcd938x->handle,
  694. WCD_BOLERO_EVT_RX_MUTE,
  695. (WCD_RX3 << 0x10));
  696. break;
  697. case SND_SOC_DAPM_PRE_PMD:
  698. if (wcd938x->update_wcd_event)
  699. wcd938x->update_wcd_event(wcd938x->handle,
  700. WCD_BOLERO_EVT_RX_MUTE,
  701. (WCD_RX3 << 0x10 | 0x1));
  702. break;
  703. case SND_SOC_DAPM_POST_PMD:
  704. /* 1 msec delay as per HW requirement */
  705. usleep_range(1000, 1010);
  706. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  707. WCD_CLSH_EVENT_POST_PA,
  708. WCD_CLSH_STATE_AUX,
  709. hph_mode);
  710. break;
  711. };
  712. return ret;
  713. }
  714. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  715. struct snd_kcontrol *kcontrol,
  716. int event)
  717. {
  718. struct snd_soc_component *component =
  719. snd_soc_dapm_to_component(w->dapm);
  720. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  721. int hph_mode = wcd938x->hph_mode;
  722. int ret = 0;
  723. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  724. w->name, event);
  725. switch (event) {
  726. case SND_SOC_DAPM_PRE_PMU:
  727. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  728. wcd938x->rx_swr_dev->dev_num,
  729. true);
  730. break;
  731. case SND_SOC_DAPM_POST_PMU:
  732. /* 6 msec delay as per HW requirement */
  733. usleep_range(6000, 6010);
  734. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  735. snd_soc_component_update_bits(component,
  736. WCD938X_ANA_RX_SUPPLIES,
  737. 0x02, 0x02);
  738. if (wcd938x->update_wcd_event)
  739. wcd938x->update_wcd_event(wcd938x->handle,
  740. WCD_BOLERO_EVT_RX_MUTE,
  741. (WCD_RX1 << 0x10));
  742. break;
  743. case SND_SOC_DAPM_PRE_PMD:
  744. if (wcd938x->update_wcd_event)
  745. wcd938x->update_wcd_event(wcd938x->handle,
  746. WCD_BOLERO_EVT_RX_MUTE,
  747. (WCD_RX1 << 0x10 | 0x1));
  748. break;
  749. case SND_SOC_DAPM_POST_PMD:
  750. /* 7 msec delay as per HW requirement */
  751. usleep_range(7000, 7010);
  752. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  753. WCD_CLSH_EVENT_POST_PA,
  754. WCD_CLSH_STATE_EAR,
  755. hph_mode);
  756. snd_soc_component_update_bits(component, WCD938X_FLYBACK_EN,
  757. 0x04, 0x04);
  758. break;
  759. };
  760. return ret;
  761. }
  762. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  763. struct snd_kcontrol *kcontrol,
  764. int event)
  765. {
  766. struct snd_soc_component *component =
  767. snd_soc_dapm_to_component(w->dapm);
  768. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  769. int mode = wcd938x->hph_mode;
  770. int ret = 0;
  771. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  772. w->name, event);
  773. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  774. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  775. wcd938x_rx_connect_port(component, CLSH,
  776. SND_SOC_DAPM_EVENT_ON(event));
  777. }
  778. if (SND_SOC_DAPM_EVENT_OFF(event))
  779. ret = swr_slvdev_datapath_control(
  780. wcd938x->rx_swr_dev,
  781. wcd938x->rx_swr_dev->dev_num,
  782. false);
  783. return ret;
  784. }
  785. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  786. struct snd_kcontrol *kcontrol,
  787. int event)
  788. {
  789. struct snd_soc_component *component =
  790. snd_soc_dapm_to_component(w->dapm);
  791. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  792. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  793. w->name, event);
  794. switch (event) {
  795. case SND_SOC_DAPM_PRE_PMU:
  796. wcd938x_rx_connect_port(component, HPH_L, true);
  797. if (wcd938x->comp1_enable)
  798. wcd938x_rx_connect_port(component, COMP_L, true);
  799. break;
  800. case SND_SOC_DAPM_POST_PMD:
  801. wcd938x_rx_connect_port(component, HPH_L, false);
  802. if (wcd938x->comp1_enable)
  803. wcd938x_rx_connect_port(component, COMP_L, false);
  804. wcd938x_rx_clk_disable(component);
  805. snd_soc_component_update_bits(component,
  806. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  807. 0x01, 0x00);
  808. break;
  809. };
  810. return 0;
  811. }
  812. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  813. struct snd_kcontrol *kcontrol, int event)
  814. {
  815. struct snd_soc_component *component =
  816. snd_soc_dapm_to_component(w->dapm);
  817. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  818. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  819. w->name, event);
  820. switch (event) {
  821. case SND_SOC_DAPM_PRE_PMU:
  822. wcd938x_rx_connect_port(component, HPH_R, true);
  823. if (wcd938x->comp2_enable)
  824. wcd938x_rx_connect_port(component, COMP_R, true);
  825. break;
  826. case SND_SOC_DAPM_POST_PMD:
  827. wcd938x_rx_connect_port(component, HPH_R, false);
  828. if (wcd938x->comp2_enable)
  829. wcd938x_rx_connect_port(component, COMP_R, false);
  830. wcd938x_rx_clk_disable(component);
  831. snd_soc_component_update_bits(component,
  832. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  833. 0x02, 0x00);
  834. break;
  835. };
  836. return 0;
  837. }
  838. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  839. struct snd_kcontrol *kcontrol,
  840. int event)
  841. {
  842. struct snd_soc_component *component =
  843. snd_soc_dapm_to_component(w->dapm);
  844. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  845. w->name, event);
  846. switch (event) {
  847. case SND_SOC_DAPM_PRE_PMU:
  848. wcd938x_rx_connect_port(component, LO, true);
  849. break;
  850. case SND_SOC_DAPM_POST_PMD:
  851. wcd938x_rx_connect_port(component, LO, false);
  852. /* 6 msec delay as per HW requirement */
  853. usleep_range(6000, 6010);
  854. wcd938x_rx_clk_disable(component);
  855. snd_soc_component_update_bits(component,
  856. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  857. break;
  858. }
  859. return 0;
  860. }
  861. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  862. struct snd_kcontrol *kcontrol,
  863. int event)
  864. {
  865. struct snd_soc_component *component =
  866. snd_soc_dapm_to_component(w->dapm);
  867. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  868. u16 dmic_clk_reg, dmic_clk_en_reg;
  869. s32 *dmic_clk_cnt;
  870. u8 dmic_ctl_shift = 0;
  871. u8 dmic_clk_shift = 0;
  872. u8 dmic_clk_mask = 0;
  873. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  874. w->name, event);
  875. switch (w->shift) {
  876. case 0:
  877. case 1:
  878. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  879. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  880. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  881. dmic_clk_mask = 0x0F;
  882. dmic_clk_shift = 0x00;
  883. dmic_ctl_shift = 0x00;
  884. break;
  885. case 2:
  886. case 3:
  887. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  888. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  889. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  890. dmic_clk_mask = 0xF0;
  891. dmic_clk_shift = 0x04;
  892. dmic_ctl_shift = 0x01;
  893. break;
  894. case 4:
  895. case 5:
  896. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  897. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  898. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  899. dmic_clk_mask = 0x0F;
  900. dmic_clk_shift = 0x00;
  901. dmic_ctl_shift = 0x02;
  902. break;
  903. case 6:
  904. case 7:
  905. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  906. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  907. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  908. dmic_clk_mask = 0xF0;
  909. dmic_clk_shift = 0x04;
  910. dmic_ctl_shift = 0x03;
  911. break;
  912. default:
  913. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  914. __func__);
  915. return -EINVAL;
  916. };
  917. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  918. __func__, event, (w->shift +1), *dmic_clk_cnt);
  919. switch (event) {
  920. case SND_SOC_DAPM_PRE_PMU:
  921. snd_soc_component_update_bits(component,
  922. WCD938X_DIGITAL_CDC_AMIC_CTL,
  923. (0x01 << dmic_ctl_shift), 0x00);
  924. /* 250us sleep as per HW requirement */
  925. usleep_range(250, 260);
  926. /* Setting DMIC clock rate to 2.4MHz */
  927. snd_soc_component_update_bits(component,
  928. dmic_clk_reg, dmic_clk_mask,
  929. (0x03 << dmic_clk_shift));
  930. snd_soc_component_update_bits(component,
  931. dmic_clk_en_reg, 0x08, 0x08);
  932. /* enable clock scaling */
  933. snd_soc_component_update_bits(component,
  934. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  935. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
  936. break;
  937. case SND_SOC_DAPM_POST_PMD:
  938. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
  939. snd_soc_component_update_bits(component,
  940. WCD938X_DIGITAL_CDC_AMIC_CTL,
  941. (0x01 << dmic_ctl_shift),
  942. (0x01 << dmic_ctl_shift));
  943. snd_soc_component_update_bits(component,
  944. dmic_clk_en_reg, 0x08, 0x00);
  945. break;
  946. };
  947. return 0;
  948. }
  949. /*
  950. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  951. * @micb_mv: micbias in mv
  952. *
  953. * return register value converted
  954. */
  955. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  956. {
  957. /* min micbias voltage is 1V and maximum is 2.85V */
  958. if (micb_mv < 1000 || micb_mv > 2850) {
  959. pr_err("%s: unsupported micbias voltage\n", __func__);
  960. return -EINVAL;
  961. }
  962. return (micb_mv - 1000) / 50;
  963. }
  964. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  965. /*
  966. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  967. * @component: handle to snd_soc_component *
  968. * @req_volt: micbias voltage to be set
  969. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  970. *
  971. * return 0 if adjustment is success or error code in case of failure
  972. */
  973. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  974. int req_volt, int micb_num)
  975. {
  976. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  977. int cur_vout_ctl, req_vout_ctl;
  978. int micb_reg, micb_val, micb_en;
  979. int ret = 0;
  980. switch (micb_num) {
  981. case MIC_BIAS_1:
  982. micb_reg = WCD938X_ANA_MICB1;
  983. break;
  984. case MIC_BIAS_2:
  985. micb_reg = WCD938X_ANA_MICB2;
  986. break;
  987. case MIC_BIAS_3:
  988. micb_reg = WCD938X_ANA_MICB3;
  989. break;
  990. case MIC_BIAS_4:
  991. micb_reg = WCD938X_ANA_MICB4;
  992. break;
  993. default:
  994. return -EINVAL;
  995. }
  996. mutex_lock(&wcd938x->micb_lock);
  997. /*
  998. * If requested micbias voltage is same as current micbias
  999. * voltage, then just return. Otherwise, adjust voltage as
  1000. * per requested value. If micbias is already enabled, then
  1001. * to avoid slow micbias ramp-up or down enable pull-up
  1002. * momentarily, change the micbias value and then re-enable
  1003. * micbias.
  1004. */
  1005. micb_val = snd_soc_component_read32(component, micb_reg);
  1006. micb_en = (micb_val & 0xC0) >> 6;
  1007. cur_vout_ctl = micb_val & 0x3F;
  1008. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1009. if (req_vout_ctl < 0) {
  1010. ret = -EINVAL;
  1011. goto exit;
  1012. }
  1013. if (cur_vout_ctl == req_vout_ctl) {
  1014. ret = 0;
  1015. goto exit;
  1016. }
  1017. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1018. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1019. req_volt, micb_en);
  1020. if (micb_en == 0x1)
  1021. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1022. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1023. if (micb_en == 0x1) {
  1024. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1025. /*
  1026. * Add 2ms delay as per HW requirement after enabling
  1027. * micbias
  1028. */
  1029. usleep_range(2000, 2100);
  1030. }
  1031. exit:
  1032. mutex_unlock(&wcd938x->micb_lock);
  1033. return ret;
  1034. }
  1035. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1036. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1037. struct snd_kcontrol *kcontrol,
  1038. int event)
  1039. {
  1040. struct snd_soc_component *component =
  1041. snd_soc_dapm_to_component(w->dapm);
  1042. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1043. int ret = 0;
  1044. switch (event) {
  1045. case SND_SOC_DAPM_PRE_PMU:
  1046. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1047. wcd938x->tx_swr_dev->dev_num,
  1048. true);
  1049. break;
  1050. case SND_SOC_DAPM_POST_PMD:
  1051. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1052. wcd938x->tx_swr_dev->dev_num,
  1053. false);
  1054. break;
  1055. };
  1056. return ret;
  1057. }
  1058. static int wcd938x_get_adc_mode(int val)
  1059. {
  1060. int ret = 0;
  1061. switch (val) {
  1062. case ADC_MODE_INVALID:
  1063. ret = ADC_MODE_VAL_NORMAL;
  1064. break;
  1065. case ADC_MODE_HIFI:
  1066. ret = ADC_MODE_VAL_HIFI;
  1067. break;
  1068. case ADC_MODE_LO_HIF:
  1069. ret = ADC_MODE_VAL_LO_HIF;
  1070. break;
  1071. case ADC_MODE_NORMAL:
  1072. ret = ADC_MODE_VAL_NORMAL;
  1073. break;
  1074. case ADC_MODE_LP:
  1075. ret = ADC_MODE_VAL_LP;
  1076. break;
  1077. case ADC_MODE_ULP1:
  1078. ret = ADC_MODE_VAL_ULP1;
  1079. break;
  1080. case ADC_MODE_ULP2:
  1081. ret = ADC_MODE_VAL_ULP2;
  1082. break;
  1083. default:
  1084. ret = -EINVAL;
  1085. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1086. break;
  1087. }
  1088. return ret;
  1089. }
  1090. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1091. struct snd_kcontrol *kcontrol,
  1092. int event){
  1093. int mode;
  1094. struct snd_soc_component *component =
  1095. snd_soc_dapm_to_component(w->dapm);
  1096. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1097. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1098. w->name, event);
  1099. switch (event) {
  1100. case SND_SOC_DAPM_PRE_PMU:
  1101. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1102. if (mode < 0) {
  1103. dev_info(component->dev,
  1104. "%s: invalid mode, setting to normal mode\n",
  1105. __func__);
  1106. mode = ADC_MODE_VAL_NORMAL;
  1107. }
  1108. snd_soc_component_update_bits(component,
  1109. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1110. snd_soc_component_update_bits(component,
  1111. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1112. snd_soc_component_update_bits(component,
  1113. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1114. switch (w->shift) {
  1115. case 0:
  1116. snd_soc_component_update_bits(component,
  1117. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1118. mode);
  1119. break;
  1120. case 1:
  1121. snd_soc_component_update_bits(component,
  1122. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1123. mode << 4);
  1124. break;
  1125. case 2:
  1126. snd_soc_component_update_bits(component,
  1127. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1128. mode);
  1129. break;
  1130. case 3:
  1131. snd_soc_component_update_bits(component,
  1132. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1133. mode << 4);
  1134. break;
  1135. default:
  1136. break;
  1137. }
  1138. set_bit(w->shift, &wcd938x->status_mask);
  1139. wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
  1140. break;
  1141. case SND_SOC_DAPM_POST_PMD:
  1142. wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
  1143. snd_soc_component_update_bits(component,
  1144. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1145. clear_bit(w->shift, &wcd938x->status_mask);
  1146. break;
  1147. };
  1148. return 0;
  1149. }
  1150. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1151. int channel, int mode)
  1152. {
  1153. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1154. int ret = 0;
  1155. switch (channel) {
  1156. case 0:
  1157. reg = WCD938X_ANA_TX_CH2;
  1158. mask = 0x40;
  1159. break;
  1160. case 1:
  1161. reg = WCD938X_ANA_TX_CH2;
  1162. mask = 0x20;
  1163. break;
  1164. case 2:
  1165. reg = WCD938X_ANA_TX_CH4;
  1166. mask = 0x40;
  1167. break;
  1168. case 3:
  1169. reg = WCD938X_ANA_TX_CH4;
  1170. mask = 0x20;
  1171. break;
  1172. default:
  1173. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1174. ret = -EINVAL;
  1175. break;
  1176. }
  1177. if (!mode)
  1178. val = 0x00;
  1179. else
  1180. val = mask;
  1181. if (!ret)
  1182. snd_soc_component_update_bits(component, reg, mask, val);
  1183. return ret;
  1184. }
  1185. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1186. struct snd_kcontrol *kcontrol, int event)
  1187. {
  1188. struct snd_soc_component *component =
  1189. snd_soc_dapm_to_component(w->dapm);
  1190. int ret = 0;
  1191. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1192. w->name, event);
  1193. switch (event) {
  1194. case SND_SOC_DAPM_PRE_PMU:
  1195. snd_soc_component_update_bits(component,
  1196. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1197. snd_soc_component_update_bits(component,
  1198. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1199. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1200. snd_soc_component_update_bits(component,
  1201. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x30, 0x30);
  1202. snd_soc_component_update_bits(component,
  1203. WCD938X_ANA_TX_CH1, 0x80, 0x80);
  1204. snd_soc_component_update_bits(component,
  1205. WCD938X_ANA_TX_CH2, 0x80, 0x80);
  1206. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1207. break;
  1208. case SND_SOC_DAPM_POST_PMD:
  1209. snd_soc_component_update_bits(component,
  1210. WCD938X_ANA_TX_CH1, 0x80, 0x00);
  1211. snd_soc_component_update_bits(component,
  1212. WCD938X_ANA_TX_CH2, 0x80, 0x00);
  1213. snd_soc_component_update_bits(component,
  1214. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1215. snd_soc_component_update_bits(component,
  1216. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1217. snd_soc_component_update_bits(component,
  1218. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1219. break;
  1220. };
  1221. return ret;
  1222. }
  1223. int wcd938x_micbias_control(struct snd_soc_component *component,
  1224. int micb_num, int req, bool is_dapm)
  1225. {
  1226. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1227. int micb_index = micb_num - 1;
  1228. u16 micb_reg;
  1229. int pre_off_event = 0, post_off_event = 0;
  1230. int post_on_event = 0, post_dapm_off = 0;
  1231. int post_dapm_on = 0;
  1232. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1233. dev_err(component->dev,
  1234. "%s: Invalid micbias index, micb_ind:%d\n",
  1235. __func__, micb_index);
  1236. return -EINVAL;
  1237. }
  1238. if (NULL == wcd938x) {
  1239. dev_err(component->dev,
  1240. "%s: wcd938x private data is NULL\n", __func__);
  1241. return -EINVAL;
  1242. }
  1243. switch (micb_num) {
  1244. case MIC_BIAS_1:
  1245. micb_reg = WCD938X_ANA_MICB1;
  1246. break;
  1247. case MIC_BIAS_2:
  1248. micb_reg = WCD938X_ANA_MICB2;
  1249. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1250. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1251. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1252. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1253. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1254. break;
  1255. case MIC_BIAS_3:
  1256. micb_reg = WCD938X_ANA_MICB3;
  1257. break;
  1258. case MIC_BIAS_4:
  1259. micb_reg = WCD938X_ANA_MICB4;
  1260. break;
  1261. default:
  1262. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1263. __func__, micb_num);
  1264. return -EINVAL;
  1265. };
  1266. mutex_lock(&wcd938x->micb_lock);
  1267. switch (req) {
  1268. case MICB_PULLUP_ENABLE:
  1269. wcd938x->pullup_ref[micb_index]++;
  1270. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1271. (wcd938x->micb_ref[micb_index] == 0))
  1272. snd_soc_component_update_bits(component, micb_reg,
  1273. 0xC0, 0x80);
  1274. break;
  1275. case MICB_PULLUP_DISABLE:
  1276. if (wcd938x->pullup_ref[micb_index] > 0)
  1277. wcd938x->pullup_ref[micb_index]--;
  1278. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1279. (wcd938x->micb_ref[micb_index] == 0))
  1280. snd_soc_component_update_bits(component, micb_reg,
  1281. 0xC0, 0x00);
  1282. break;
  1283. case MICB_ENABLE:
  1284. wcd938x->micb_ref[micb_index]++;
  1285. if (wcd938x->micb_ref[micb_index] == 1) {
  1286. snd_soc_component_update_bits(component,
  1287. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  1288. snd_soc_component_update_bits(component,
  1289. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1290. snd_soc_component_update_bits(component,
  1291. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1292. snd_soc_component_update_bits(component,
  1293. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1294. snd_soc_component_update_bits(component,
  1295. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1296. snd_soc_component_update_bits(component,
  1297. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1298. snd_soc_component_update_bits(component,
  1299. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1300. snd_soc_component_update_bits(component,
  1301. micb_reg, 0xC0, 0x40);
  1302. if (post_on_event)
  1303. blocking_notifier_call_chain(
  1304. &wcd938x->mbhc->notifier,
  1305. post_on_event,
  1306. &wcd938x->mbhc->wcd_mbhc);
  1307. }
  1308. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1309. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1310. post_dapm_on,
  1311. &wcd938x->mbhc->wcd_mbhc);
  1312. break;
  1313. case MICB_DISABLE:
  1314. if (wcd938x->micb_ref[micb_index] > 0)
  1315. wcd938x->micb_ref[micb_index]--;
  1316. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1317. (wcd938x->pullup_ref[micb_index] > 0))
  1318. snd_soc_component_update_bits(component, micb_reg,
  1319. 0xC0, 0x80);
  1320. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1321. (wcd938x->pullup_ref[micb_index] == 0)) {
  1322. if (pre_off_event && wcd938x->mbhc)
  1323. blocking_notifier_call_chain(
  1324. &wcd938x->mbhc->notifier,
  1325. pre_off_event,
  1326. &wcd938x->mbhc->wcd_mbhc);
  1327. snd_soc_component_update_bits(component, micb_reg,
  1328. 0xC0, 0x00);
  1329. if (post_off_event && wcd938x->mbhc)
  1330. blocking_notifier_call_chain(
  1331. &wcd938x->mbhc->notifier,
  1332. post_off_event,
  1333. &wcd938x->mbhc->wcd_mbhc);
  1334. }
  1335. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1336. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1337. post_dapm_off,
  1338. &wcd938x->mbhc->wcd_mbhc);
  1339. break;
  1340. };
  1341. dev_dbg(component->dev,
  1342. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1343. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1344. wcd938x->pullup_ref[micb_index]);
  1345. mutex_unlock(&wcd938x->micb_lock);
  1346. return 0;
  1347. }
  1348. EXPORT_SYMBOL(wcd938x_micbias_control);
  1349. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1350. {
  1351. int ret = 0;
  1352. uint8_t devnum = 0;
  1353. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1354. if (ret) {
  1355. dev_err(&swr_dev->dev,
  1356. "%s get devnum %d for dev addr %lx failed\n",
  1357. __func__, devnum, swr_dev->addr);
  1358. swr_remove_device(swr_dev);
  1359. return ret;
  1360. }
  1361. swr_dev->dev_num = devnum;
  1362. return 0;
  1363. }
  1364. static int wcd938x_event_notify(struct notifier_block *block,
  1365. unsigned long val,
  1366. void *data)
  1367. {
  1368. u16 event = (val & 0xffff);
  1369. int ret = 0;
  1370. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1371. struct snd_soc_component *component = wcd938x->component;
  1372. struct wcd_mbhc *mbhc;
  1373. switch (event) {
  1374. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1375. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1376. snd_soc_component_update_bits(component,
  1377. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1378. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1379. }
  1380. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1381. snd_soc_component_update_bits(component,
  1382. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1383. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1384. }
  1385. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1386. snd_soc_component_update_bits(component,
  1387. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1388. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1389. }
  1390. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1391. snd_soc_component_update_bits(component,
  1392. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1393. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1394. }
  1395. break;
  1396. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1397. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1398. 0xC0, 0x00);
  1399. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1400. 0x80, 0x00);
  1401. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1402. 0x80, 0x00);
  1403. break;
  1404. case BOLERO_WCD_EVT_SSR_DOWN:
  1405. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1406. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1407. wcd938x_reset_low(wcd938x->dev);
  1408. break;
  1409. case BOLERO_WCD_EVT_SSR_UP:
  1410. wcd938x_reset(wcd938x->dev);
  1411. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1412. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1413. regcache_mark_dirty(wcd938x->regmap);
  1414. regcache_sync(wcd938x->regmap);
  1415. /* Initialize MBHC module */
  1416. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1417. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1418. if (ret) {
  1419. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1420. __func__);
  1421. } else {
  1422. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1423. }
  1424. break;
  1425. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1426. snd_soc_component_update_bits(component,
  1427. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1428. ((val >> 0x10) << 0x01));
  1429. break;
  1430. default:
  1431. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1432. break;
  1433. }
  1434. return 0;
  1435. }
  1436. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1437. int event)
  1438. {
  1439. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1440. int micb_num;
  1441. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1442. __func__, w->name, event);
  1443. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1444. micb_num = MIC_BIAS_1;
  1445. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1446. micb_num = MIC_BIAS_2;
  1447. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1448. micb_num = MIC_BIAS_3;
  1449. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1450. micb_num = MIC_BIAS_4;
  1451. else
  1452. return -EINVAL;
  1453. switch (event) {
  1454. case SND_SOC_DAPM_PRE_PMU:
  1455. wcd938x_micbias_control(component, micb_num,
  1456. MICB_ENABLE, true);
  1457. break;
  1458. case SND_SOC_DAPM_POST_PMU:
  1459. /* 1 msec delay as per HW requirement */
  1460. usleep_range(1000, 1100);
  1461. break;
  1462. case SND_SOC_DAPM_POST_PMD:
  1463. wcd938x_micbias_control(component, micb_num,
  1464. MICB_DISABLE, true);
  1465. break;
  1466. };
  1467. return 0;
  1468. }
  1469. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1470. struct snd_kcontrol *kcontrol,
  1471. int event)
  1472. {
  1473. return __wcd938x_codec_enable_micbias(w, event);
  1474. }
  1475. static inline int wcd938x_tx_path_get(const char *wname)
  1476. {
  1477. int ret = 0;
  1478. unsigned int path_num;
  1479. char *widget_name = NULL;
  1480. char *w_name = NULL;
  1481. char *path_num_char = NULL;
  1482. char *path_name = NULL;
  1483. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  1484. if (!widget_name)
  1485. return -EINVAL;
  1486. w_name = widget_name;
  1487. path_name = strsep(&widget_name, " ");
  1488. if (!path_name) {
  1489. pr_err("%s: Invalid widget name = %s\n",
  1490. __func__, widget_name);
  1491. ret = -EINVAL;
  1492. goto err;
  1493. }
  1494. path_name = widget_name;
  1495. path_num_char = strpbrk(path_name, "0123");
  1496. if (!path_num_char) {
  1497. pr_err("%s: tx path index not found\n",
  1498. __func__);
  1499. ret = -EINVAL;
  1500. goto err;
  1501. }
  1502. ret = kstrtouint(path_num_char, 10, &path_num);
  1503. if (ret < 0)
  1504. pr_err("%s: Invalid tx path = %s\n",
  1505. __func__, w_name);
  1506. err:
  1507. kfree(w_name);
  1508. return ret;
  1509. }
  1510. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_value *ucontrol)
  1512. {
  1513. struct snd_soc_dapm_widget *widget =
  1514. snd_soc_dapm_kcontrol_widget(kcontrol);
  1515. struct snd_soc_component *component =
  1516. snd_soc_kcontrol_component(kcontrol);
  1517. struct wcd938x_priv *wcd938x = NULL;
  1518. int path = 0;
  1519. if (!component)
  1520. return -EINVAL;
  1521. wcd938x = snd_soc_component_get_drvdata(component);
  1522. if (!widget || !widget->name || !wcd938x)
  1523. return -EINVAL;
  1524. path = wcd938x_tx_path_get(widget->name);
  1525. if (path < 0 || path >= TX_ADC_MAX)
  1526. return -EINVAL;
  1527. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  1528. return 0;
  1529. }
  1530. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  1531. struct snd_ctl_elem_value *ucontrol)
  1532. {
  1533. struct snd_soc_dapm_widget *widget =
  1534. snd_soc_dapm_kcontrol_widget(kcontrol);
  1535. struct snd_soc_component *component =
  1536. snd_soc_kcontrol_component(kcontrol);
  1537. struct wcd938x_priv *wcd938x = NULL;
  1538. u32 mode_val;
  1539. int path = 0;
  1540. if (!component)
  1541. return -EINVAL;
  1542. wcd938x = snd_soc_component_get_drvdata(component);
  1543. if (!widget || !widget->name || !wcd938x)
  1544. return -EINVAL;
  1545. path = wcd938x_tx_path_get(widget->name);
  1546. if (path < 0 || path >= TX_ADC_MAX)
  1547. return -EINVAL;
  1548. mode_val = ucontrol->value.enumerated.item[0];
  1549. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1550. wcd938x->tx_mode[path] = mode_val;
  1551. return 0;
  1552. }
  1553. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1554. struct snd_ctl_elem_value *ucontrol)
  1555. {
  1556. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1557. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1558. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  1559. return 0;
  1560. }
  1561. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1562. struct snd_ctl_elem_value *ucontrol)
  1563. {
  1564. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1565. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1566. u32 mode_val;
  1567. mode_val = ucontrol->value.enumerated.item[0];
  1568. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1569. if (mode_val == 0) {
  1570. dev_info(component->dev,
  1571. "%s:Invalid HPH Mode, default to class_AB\n",
  1572. __func__);
  1573. mode_val = 3; /* enum will be updated later */
  1574. }
  1575. wcd938x->hph_mode = mode_val;
  1576. return 0;
  1577. }
  1578. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  1579. struct snd_ctl_elem_value *ucontrol)
  1580. {
  1581. struct snd_soc_component *component =
  1582. snd_soc_kcontrol_component(kcontrol);
  1583. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1584. bool hphr;
  1585. struct soc_multi_mixer_control *mc;
  1586. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1587. hphr = mc->shift;
  1588. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  1589. wcd938x->comp1_enable;
  1590. return 0;
  1591. }
  1592. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  1593. struct snd_ctl_elem_value *ucontrol)
  1594. {
  1595. struct snd_soc_component *component =
  1596. snd_soc_kcontrol_component(kcontrol);
  1597. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1598. int value = ucontrol->value.integer.value[0];
  1599. bool hphr;
  1600. struct soc_multi_mixer_control *mc;
  1601. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1602. hphr = mc->shift;
  1603. if (hphr)
  1604. wcd938x->comp2_enable = value;
  1605. else
  1606. wcd938x->comp1_enable = value;
  1607. return 0;
  1608. }
  1609. static const char * const tx_mode_mux_text_wcd9380[] = {
  1610. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1611. };
  1612. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  1613. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  1614. tx_mode_mux_text_wcd9380);
  1615. static const char * const tx_mode_mux_text[] = {
  1616. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  1617. "ADC_ULP1", "ADC_ULP2",
  1618. };
  1619. static const struct soc_enum tx_mode_mux_enum =
  1620. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  1621. tx_mode_mux_text);
  1622. static const char * const rx_hph_mode_mux_text[] = {
  1623. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1624. "CLS_H_ULP", "CLS_AB_HIFI",
  1625. };
  1626. static const struct soc_enum rx_hph_mode_mux_enum =
  1627. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1628. rx_hph_mode_mux_text);
  1629. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  1630. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  1631. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1632. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  1633. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1634. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  1635. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1636. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  1637. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1638. };
  1639. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  1640. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  1641. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1642. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  1643. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1644. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  1645. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1646. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  1647. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  1648. };
  1649. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  1650. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1651. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  1652. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1653. wcd938x_get_compander, wcd938x_set_compander),
  1654. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1655. wcd938x_get_compander, wcd938x_set_compander),
  1656. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  1657. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  1658. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  1659. analog_gain),
  1660. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  1661. analog_gain),
  1662. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  1663. analog_gain),
  1664. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  1665. analog_gain),
  1666. };
  1667. static const struct snd_kcontrol_new adc1_switch[] = {
  1668. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1669. };
  1670. static const struct snd_kcontrol_new adc2_switch[] = {
  1671. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1672. };
  1673. static const struct snd_kcontrol_new adc3_switch[] = {
  1674. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1675. };
  1676. static const struct snd_kcontrol_new adc4_switch[] = {
  1677. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1678. };
  1679. static const struct snd_kcontrol_new dmic1_switch[] = {
  1680. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1681. };
  1682. static const struct snd_kcontrol_new dmic2_switch[] = {
  1683. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1684. };
  1685. static const struct snd_kcontrol_new dmic3_switch[] = {
  1686. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1687. };
  1688. static const struct snd_kcontrol_new dmic4_switch[] = {
  1689. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1690. };
  1691. static const struct snd_kcontrol_new dmic5_switch[] = {
  1692. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1693. };
  1694. static const struct snd_kcontrol_new dmic6_switch[] = {
  1695. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1696. };
  1697. static const struct snd_kcontrol_new dmic7_switch[] = {
  1698. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1699. };
  1700. static const struct snd_kcontrol_new dmic8_switch[] = {
  1701. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1702. };
  1703. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1704. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1705. };
  1706. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1707. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1708. };
  1709. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1710. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1711. };
  1712. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1713. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1714. };
  1715. static const char * const adc2_mux_text[] = {
  1716. "INP2", "INP3"
  1717. };
  1718. static const struct soc_enum adc2_enum =
  1719. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  1720. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1721. static const struct snd_kcontrol_new tx_adc2_mux =
  1722. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1723. static const char * const adc3_mux_text[] = {
  1724. "INP4", "INP6"
  1725. };
  1726. static const struct soc_enum adc3_enum =
  1727. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  1728. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  1729. static const struct snd_kcontrol_new tx_adc3_mux =
  1730. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  1731. static const char * const adc4_mux_text[] = {
  1732. "INP5", "INP7"
  1733. };
  1734. static const struct soc_enum adc4_enum =
  1735. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  1736. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  1737. static const struct snd_kcontrol_new tx_adc4_mux =
  1738. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  1739. static const char * const rdac3_mux_text[] = {
  1740. "RX1", "RX3"
  1741. };
  1742. static const char * const hdr12_mux_text[] = {
  1743. "NO_HDR12", "HDR12"
  1744. };
  1745. static const struct soc_enum hdr12_enum =
  1746. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  1747. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  1748. static const struct snd_kcontrol_new tx_hdr12_mux =
  1749. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  1750. static const char * const hdr34_mux_text[] = {
  1751. "NO_HDR34", "HDR34"
  1752. };
  1753. static const struct soc_enum hdr34_enum =
  1754. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  1755. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  1756. static const struct snd_kcontrol_new tx_hdr34_mux =
  1757. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  1758. static const struct soc_enum rdac3_enum =
  1759. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1760. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1761. static const struct snd_kcontrol_new rx_rdac3_mux =
  1762. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1763. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  1764. /*input widgets*/
  1765. SND_SOC_DAPM_INPUT("AMIC1"),
  1766. SND_SOC_DAPM_INPUT("AMIC2"),
  1767. SND_SOC_DAPM_INPUT("AMIC3"),
  1768. SND_SOC_DAPM_INPUT("AMIC4"),
  1769. SND_SOC_DAPM_INPUT("AMIC5"),
  1770. SND_SOC_DAPM_INPUT("AMIC6"),
  1771. SND_SOC_DAPM_INPUT("AMIC7"),
  1772. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1773. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1774. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1775. /*tx widgets*/
  1776. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1777. wcd938x_codec_enable_adc,
  1778. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1779. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1780. wcd938x_codec_enable_adc,
  1781. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1782. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  1783. wcd938x_codec_enable_adc,
  1784. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1785. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  1786. wcd938x_codec_enable_adc,
  1787. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1788. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  1789. wcd938x_codec_enable_dmic,
  1790. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1791. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  1792. wcd938x_codec_enable_dmic,
  1793. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1794. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  1795. wcd938x_codec_enable_dmic,
  1796. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1797. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  1798. wcd938x_codec_enable_dmic,
  1799. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1800. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  1801. wcd938x_codec_enable_dmic,
  1802. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1803. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  1804. wcd938x_codec_enable_dmic,
  1805. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1806. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  1807. wcd938x_codec_enable_dmic,
  1808. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1809. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  1810. wcd938x_codec_enable_dmic,
  1811. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1812. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1813. NULL, 0, wcd938x_enable_req,
  1814. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1815. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  1816. NULL, 0, wcd938x_enable_req,
  1817. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1818. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  1819. NULL, 0, wcd938x_enable_req,
  1820. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1821. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  1822. NULL, 0, wcd938x_enable_req,
  1823. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1824. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1825. &tx_adc2_mux),
  1826. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  1827. &tx_adc3_mux),
  1828. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  1829. &tx_adc4_mux),
  1830. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  1831. &tx_hdr12_mux),
  1832. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  1833. &tx_hdr34_mux),
  1834. /*tx mixers*/
  1835. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1836. adc1_switch, ARRAY_SIZE(adc1_switch),
  1837. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1838. SND_SOC_DAPM_POST_PMD),
  1839. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1840. adc2_switch, ARRAY_SIZE(adc2_switch),
  1841. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1842. SND_SOC_DAPM_POST_PMD),
  1843. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  1844. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  1845. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1846. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  1847. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  1848. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1849. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  1850. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  1851. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1852. SND_SOC_DAPM_POST_PMD),
  1853. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  1854. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  1855. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1856. SND_SOC_DAPM_POST_PMD),
  1857. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  1858. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  1859. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1860. SND_SOC_DAPM_POST_PMD),
  1861. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  1862. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  1863. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1864. SND_SOC_DAPM_POST_PMD),
  1865. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  1866. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  1867. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1868. SND_SOC_DAPM_POST_PMD),
  1869. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  1870. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  1871. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1872. SND_SOC_DAPM_POST_PMD),
  1873. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  1874. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  1875. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1876. SND_SOC_DAPM_POST_PMD),
  1877. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  1878. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  1879. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1880. SND_SOC_DAPM_POST_PMD),
  1881. /* micbias widgets*/
  1882. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1883. wcd938x_codec_enable_micbias,
  1884. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1885. SND_SOC_DAPM_POST_PMD),
  1886. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1887. wcd938x_codec_enable_micbias,
  1888. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1889. SND_SOC_DAPM_POST_PMD),
  1890. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1891. wcd938x_codec_enable_micbias,
  1892. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1893. SND_SOC_DAPM_POST_PMD),
  1894. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  1895. wcd938x_codec_enable_micbias,
  1896. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1897. SND_SOC_DAPM_POST_PMD),
  1898. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  1899. wcd938x_enable_clsh,
  1900. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1901. /*rx widgets*/
  1902. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  1903. wcd938x_codec_enable_ear_pa,
  1904. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1905. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1906. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  1907. wcd938x_codec_enable_aux_pa,
  1908. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1909. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1910. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  1911. wcd938x_codec_enable_hphl_pa,
  1912. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1913. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1914. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  1915. wcd938x_codec_enable_hphr_pa,
  1916. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1917. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1918. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  1919. wcd938x_codec_hphl_dac_event,
  1920. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1921. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1922. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  1923. wcd938x_codec_hphr_dac_event,
  1924. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1925. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1926. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  1927. wcd938x_codec_ear_dac_event,
  1928. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1929. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1930. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  1931. wcd938x_codec_aux_dac_event,
  1932. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1933. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1934. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  1935. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  1936. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  1937. SND_SOC_DAPM_POST_PMD),
  1938. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  1939. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  1940. SND_SOC_DAPM_POST_PMD),
  1941. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  1942. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  1943. SND_SOC_DAPM_POST_PMD),
  1944. /* rx mixer widgets*/
  1945. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  1946. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  1947. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  1948. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  1949. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  1950. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  1951. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  1952. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  1953. /*output widgets tx*/
  1954. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  1955. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  1956. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  1957. SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
  1958. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  1959. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  1960. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  1961. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  1962. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  1963. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  1964. SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
  1965. SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
  1966. /*output widgets rx*/
  1967. SND_SOC_DAPM_OUTPUT("EAR"),
  1968. SND_SOC_DAPM_OUTPUT("AUX"),
  1969. SND_SOC_DAPM_OUTPUT("HPHL"),
  1970. SND_SOC_DAPM_OUTPUT("HPHR"),
  1971. };
  1972. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  1973. {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
  1974. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  1975. {"ADC1 REQ", NULL, "ADC1"},
  1976. {"ADC1", NULL, "AMIC1"},
  1977. {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
  1978. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  1979. {"ADC2 REQ", NULL, "ADC2"},
  1980. {"ADC2", NULL, "HDR12 MUX"},
  1981. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  1982. {"HDR12 MUX", "HDR12", "AMIC1"},
  1983. {"ADC2 MUX", "INP3", "AMIC3"},
  1984. {"ADC2 MUX", "INP2", "AMIC2"},
  1985. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  1986. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  1987. {"ADC3 REQ", NULL, "ADC3"},
  1988. {"ADC3", NULL, "HDR34 MUX"},
  1989. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  1990. {"HDR34 MUX", "HDR34", "AMIC5"},
  1991. {"ADC3 MUX", "INP4", "AMIC4"},
  1992. {"ADC3 MUX", "INP6", "AMIC6"},
  1993. {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
  1994. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  1995. {"ADC4 REQ", NULL, "ADC4"},
  1996. {"ADC4", NULL, "ADC4 MUX"},
  1997. {"ADC4 MUX", "INP5", "AMIC5"},
  1998. {"ADC4 MUX", "INP7", "AMIC7"},
  1999. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2000. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2001. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2002. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2003. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2004. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2005. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2006. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2007. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2008. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2009. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2010. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2011. {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
  2012. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2013. {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
  2014. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2015. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2016. {"RX1", NULL, "IN1_HPHL"},
  2017. {"RDAC1", NULL, "RX1"},
  2018. {"HPHL_RDAC", "Switch", "RDAC1"},
  2019. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2020. {"HPHL", NULL, "HPHL PGA"},
  2021. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2022. {"RX2", NULL, "IN2_HPHR"},
  2023. {"RDAC2", NULL, "RX2"},
  2024. {"HPHR_RDAC", "Switch", "RDAC2"},
  2025. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2026. {"HPHR", NULL, "HPHR PGA"},
  2027. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2028. {"RX3", NULL, "IN3_AUX"},
  2029. {"RDAC4", NULL, "RX3"},
  2030. {"AUX_RDAC", "Switch", "RDAC4"},
  2031. {"AUX PGA", NULL, "AUX_RDAC"},
  2032. {"AUX", NULL, "AUX PGA"},
  2033. {"RDAC3_MUX", "RX3", "RX3"},
  2034. {"RDAC3_MUX", "RX1", "RX1"},
  2035. {"RDAC3", NULL, "RDAC3_MUX"},
  2036. {"EAR_RDAC", "Switch", "RDAC3"},
  2037. {"EAR PGA", NULL, "EAR_RDAC"},
  2038. {"EAR", NULL, "EAR PGA"},
  2039. };
  2040. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2041. void *file_private_data,
  2042. struct file *file,
  2043. char __user *buf, size_t count,
  2044. loff_t pos)
  2045. {
  2046. struct wcd938x_priv *priv;
  2047. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2048. int len = 0;
  2049. priv = (struct wcd938x_priv *) entry->private_data;
  2050. if (!priv) {
  2051. pr_err("%s: wcd938x priv is null\n", __func__);
  2052. return -EINVAL;
  2053. }
  2054. switch (priv->version) {
  2055. case WCD938X_VERSION_1_0:
  2056. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2057. break;
  2058. default:
  2059. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2060. }
  2061. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2062. }
  2063. static struct snd_info_entry_ops wcd938x_info_ops = {
  2064. .read = wcd938x_version_read,
  2065. };
  2066. /*
  2067. * wcd938x_info_create_codec_entry - creates wcd938x module
  2068. * @codec_root: The parent directory
  2069. * @component: component instance
  2070. *
  2071. * Creates wcd938x module and version entry under the given
  2072. * parent directory.
  2073. *
  2074. * Return: 0 on success or negative error code on failure.
  2075. */
  2076. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2077. struct snd_soc_component *component)
  2078. {
  2079. struct snd_info_entry *version_entry;
  2080. struct wcd938x_priv *priv;
  2081. struct snd_soc_card *card;
  2082. if (!codec_root || !component)
  2083. return -EINVAL;
  2084. priv = snd_soc_component_get_drvdata(component);
  2085. if (priv->entry) {
  2086. dev_dbg(priv->dev,
  2087. "%s:wcd938x module already created\n", __func__);
  2088. return 0;
  2089. }
  2090. card = component->card;
  2091. priv->entry = snd_info_create_subdir(codec_root->module,
  2092. "wcd938x", codec_root);
  2093. if (!priv->entry) {
  2094. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  2095. __func__);
  2096. return -ENOMEM;
  2097. }
  2098. version_entry = snd_info_create_card_entry(card->snd_card,
  2099. "version",
  2100. priv->entry);
  2101. if (!version_entry) {
  2102. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  2103. __func__);
  2104. return -ENOMEM;
  2105. }
  2106. version_entry->private_data = priv;
  2107. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  2108. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2109. version_entry->c.ops = &wcd938x_info_ops;
  2110. if (snd_info_register(version_entry) < 0) {
  2111. snd_info_free_entry(version_entry);
  2112. return -ENOMEM;
  2113. }
  2114. priv->version_entry = version_entry;
  2115. return 0;
  2116. }
  2117. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  2118. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  2119. {
  2120. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2121. struct snd_soc_dapm_context *dapm =
  2122. snd_soc_component_get_dapm(component);
  2123. int variant;
  2124. int ret = -EINVAL;
  2125. dev_info(component->dev, "%s()\n", __func__);
  2126. wcd938x = snd_soc_component_get_drvdata(component);
  2127. if (!wcd938x)
  2128. return -EINVAL;
  2129. wcd938x->component = component;
  2130. snd_soc_component_init_regmap(component, wcd938x->regmap);
  2131. variant = (snd_soc_component_read32(component,
  2132. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2133. wcd938x->variant = variant;
  2134. wcd938x->fw_data = devm_kzalloc(component->dev,
  2135. sizeof(*(wcd938x->fw_data)),
  2136. GFP_KERNEL);
  2137. if (!wcd938x->fw_data) {
  2138. dev_err(component->dev, "Failed to allocate fw_data\n");
  2139. ret = -ENOMEM;
  2140. goto err;
  2141. }
  2142. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  2143. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  2144. WCD9XXX_CODEC_HWDEP_NODE, component);
  2145. if (ret < 0) {
  2146. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2147. goto err_hwdep;
  2148. }
  2149. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  2150. if (ret) {
  2151. pr_err("%s: mbhc initialization failed\n", __func__);
  2152. goto err_hwdep;
  2153. }
  2154. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2155. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2156. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2157. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2158. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  2159. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  2160. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  2161. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2162. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2163. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2164. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2165. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2166. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2167. snd_soc_dapm_ignore_suspend(dapm, "DMIC7_OUTPUT");
  2168. snd_soc_dapm_ignore_suspend(dapm, "DMIC8_OUTPUT");
  2169. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2170. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2171. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2172. snd_soc_dapm_ignore_suspend(dapm, "ADC4_OUTPUT");
  2173. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2174. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2175. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2176. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2177. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2178. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2179. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2180. snd_soc_dapm_sync(dapm);
  2181. wcd_cls_h_init(&wcd938x->clsh_info);
  2182. wcd938x_init_reg(component);
  2183. if (wcd938x->variant == WCD9380) {
  2184. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  2185. ARRAY_SIZE(wcd9380_snd_controls));
  2186. if (ret < 0) {
  2187. dev_err(component->dev,
  2188. "%s: Failed to add snd ctrls for variant: %d\n",
  2189. __func__, wcd938x->variant);
  2190. goto err_hwdep;
  2191. }
  2192. }
  2193. if (wcd938x->variant == WCD9385) {
  2194. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  2195. ARRAY_SIZE(wcd9385_snd_controls));
  2196. if (ret < 0) {
  2197. dev_err(component->dev,
  2198. "%s: Failed to add snd ctrls for variant: %d\n",
  2199. __func__, wcd938x->variant);
  2200. goto err_hwdep;
  2201. }
  2202. }
  2203. wcd938x->version = WCD938X_VERSION_1_0;
  2204. /* Register event notifier */
  2205. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  2206. if (wcd938x->register_notifier) {
  2207. ret = wcd938x->register_notifier(wcd938x->handle,
  2208. &wcd938x->nblock,
  2209. true);
  2210. if (ret) {
  2211. dev_err(component->dev,
  2212. "%s: Failed to register notifier %d\n",
  2213. __func__, ret);
  2214. return ret;
  2215. }
  2216. }
  2217. return ret;
  2218. err_hwdep:
  2219. wcd938x->fw_data = NULL;
  2220. err:
  2221. return ret;
  2222. }
  2223. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  2224. {
  2225. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2226. if (!wcd938x) {
  2227. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  2228. __func__);
  2229. return;
  2230. }
  2231. if (wcd938x->register_notifier)
  2232. wcd938x->register_notifier(wcd938x->handle,
  2233. &wcd938x->nblock,
  2234. false);
  2235. }
  2236. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  2237. .name = WCD938X_DRV_NAME,
  2238. .probe = wcd938x_soc_codec_probe,
  2239. .remove = wcd938x_soc_codec_remove,
  2240. .controls = wcd938x_snd_controls,
  2241. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  2242. .dapm_widgets = wcd938x_dapm_widgets,
  2243. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  2244. .dapm_routes = wcd938x_audio_map,
  2245. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  2246. };
  2247. static int wcd938x_reset(struct device *dev)
  2248. {
  2249. struct wcd938x_priv *wcd938x = NULL;
  2250. int rc = 0;
  2251. int value = 0;
  2252. if (!dev)
  2253. return -ENODEV;
  2254. wcd938x = dev_get_drvdata(dev);
  2255. if (!wcd938x)
  2256. return -EINVAL;
  2257. if (!wcd938x->rst_np) {
  2258. dev_err(dev, "%s: reset gpio device node not specified\n",
  2259. __func__);
  2260. return -EINVAL;
  2261. }
  2262. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  2263. if (value > 0)
  2264. return 0;
  2265. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2266. if (rc) {
  2267. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2268. __func__);
  2269. return rc;
  2270. }
  2271. /* 20us sleep required after pulling the reset gpio to LOW */
  2272. usleep_range(20, 30);
  2273. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  2274. if (rc) {
  2275. dev_err(dev, "%s: wcd active state request fail!\n",
  2276. __func__);
  2277. return rc;
  2278. }
  2279. /* 20us sleep required after pulling the reset gpio to HIGH */
  2280. usleep_range(20, 30);
  2281. return rc;
  2282. }
  2283. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  2284. u32 *val)
  2285. {
  2286. int rc = 0;
  2287. rc = of_property_read_u32(dev->of_node, name, val);
  2288. if (rc)
  2289. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2290. __func__, name, dev->of_node->full_name);
  2291. return rc;
  2292. }
  2293. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  2294. struct wcd938x_micbias_setting *mb)
  2295. {
  2296. u32 prop_val = 0;
  2297. int rc = 0;
  2298. /* MB1 */
  2299. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2300. NULL)) {
  2301. rc = wcd938x_read_of_property_u32(dev,
  2302. "qcom,cdc-micbias1-mv",
  2303. &prop_val);
  2304. if (!rc)
  2305. mb->micb1_mv = prop_val;
  2306. } else {
  2307. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2308. __func__);
  2309. }
  2310. /* MB2 */
  2311. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2312. NULL)) {
  2313. rc = wcd938x_read_of_property_u32(dev,
  2314. "qcom,cdc-micbias2-mv",
  2315. &prop_val);
  2316. if (!rc)
  2317. mb->micb2_mv = prop_val;
  2318. } else {
  2319. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2320. __func__);
  2321. }
  2322. /* MB3 */
  2323. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2324. NULL)) {
  2325. rc = wcd938x_read_of_property_u32(dev,
  2326. "qcom,cdc-micbias3-mv",
  2327. &prop_val);
  2328. if (!rc)
  2329. mb->micb3_mv = prop_val;
  2330. } else {
  2331. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2332. __func__);
  2333. }
  2334. }
  2335. static int wcd938x_reset_low(struct device *dev)
  2336. {
  2337. struct wcd938x_priv *wcd938x = NULL;
  2338. int rc = 0;
  2339. if (!dev)
  2340. return -ENODEV;
  2341. wcd938x = dev_get_drvdata(dev);
  2342. if (!wcd938x)
  2343. return -EINVAL;
  2344. if (!wcd938x->rst_np) {
  2345. dev_err(dev, "%s: reset gpio device node not specified\n",
  2346. __func__);
  2347. return -EINVAL;
  2348. }
  2349. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  2350. if (rc) {
  2351. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2352. __func__);
  2353. return rc;
  2354. }
  2355. /* 20us sleep required after pulling the reset gpio to LOW */
  2356. usleep_range(20, 30);
  2357. return rc;
  2358. }
  2359. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  2360. {
  2361. struct wcd938x_pdata *pdata = NULL;
  2362. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  2363. GFP_KERNEL);
  2364. if (!pdata)
  2365. return NULL;
  2366. pdata->rst_np = of_parse_phandle(dev->of_node,
  2367. "qcom,wcd-rst-gpio-node", 0);
  2368. if (!pdata->rst_np) {
  2369. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2370. __func__, "qcom,wcd-rst-gpio-node",
  2371. dev->of_node->full_name);
  2372. return NULL;
  2373. }
  2374. /* Parse power supplies */
  2375. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2376. &pdata->num_supplies);
  2377. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2378. dev_err(dev, "%s: no power supplies defined for codec\n",
  2379. __func__);
  2380. return NULL;
  2381. }
  2382. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2383. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2384. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  2385. return pdata;
  2386. }
  2387. static int wcd938x_bind(struct device *dev)
  2388. {
  2389. int ret = 0, i = 0;
  2390. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  2391. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2392. /*
  2393. * Add 5msec delay to provide sufficient time for
  2394. * soundwire auto enumeration of slave devices as
  2395. * as per HW requirement.
  2396. */
  2397. usleep_range(5000, 5010);
  2398. ret = component_bind_all(dev, wcd938x);
  2399. if (ret) {
  2400. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2401. __func__, ret);
  2402. return ret;
  2403. }
  2404. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2405. if (!wcd938x->rx_swr_dev) {
  2406. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2407. __func__);
  2408. ret = -ENODEV;
  2409. goto err;
  2410. }
  2411. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2412. if (!wcd938x->tx_swr_dev) {
  2413. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2414. __func__);
  2415. ret = -ENODEV;
  2416. goto err;
  2417. }
  2418. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  2419. &wcd938x_regmap_config);
  2420. if (!wcd938x->regmap) {
  2421. dev_err(dev, "%s: Regmap init failed\n",
  2422. __func__);
  2423. goto err;
  2424. }
  2425. /* Set all interupts as edge triggered */
  2426. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  2427. regmap_write(wcd938x->regmap,
  2428. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2429. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  2430. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  2431. wcd938x->irq_info.codec_name = "WCD938X";
  2432. wcd938x->irq_info.regmap = wcd938x->regmap;
  2433. wcd938x->irq_info.dev = dev;
  2434. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  2435. if (ret) {
  2436. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  2437. __func__, ret);
  2438. goto err;
  2439. }
  2440. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  2441. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  2442. NULL, 0);
  2443. if (ret) {
  2444. dev_err(dev, "%s: Codec registration failed\n",
  2445. __func__);
  2446. goto err_irq;
  2447. }
  2448. return ret;
  2449. err_irq:
  2450. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2451. err:
  2452. component_unbind_all(dev, wcd938x);
  2453. return ret;
  2454. }
  2455. static void wcd938x_unbind(struct device *dev)
  2456. {
  2457. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  2458. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  2459. snd_soc_unregister_component(dev);
  2460. component_unbind_all(dev, wcd938x);
  2461. }
  2462. static const struct of_device_id wcd938x_dt_match[] = {
  2463. { .compatible = "qcom,wcd938x-codec" },
  2464. {}
  2465. };
  2466. static const struct component_master_ops wcd938x_comp_ops = {
  2467. .bind = wcd938x_bind,
  2468. .unbind = wcd938x_unbind,
  2469. };
  2470. static int wcd938x_compare_of(struct device *dev, void *data)
  2471. {
  2472. return dev->of_node == data;
  2473. }
  2474. static void wcd938x_release_of(struct device *dev, void *data)
  2475. {
  2476. of_node_put(data);
  2477. }
  2478. static int wcd938x_add_slave_components(struct device *dev,
  2479. struct component_match **matchptr)
  2480. {
  2481. struct device_node *np, *rx_node, *tx_node;
  2482. np = dev->of_node;
  2483. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2484. if (!rx_node) {
  2485. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2486. return -ENODEV;
  2487. }
  2488. of_node_get(rx_node);
  2489. component_match_add_release(dev, matchptr,
  2490. wcd938x_release_of,
  2491. wcd938x_compare_of,
  2492. rx_node);
  2493. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2494. if (!tx_node) {
  2495. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2496. return -ENODEV;
  2497. }
  2498. of_node_get(tx_node);
  2499. component_match_add_release(dev, matchptr,
  2500. wcd938x_release_of,
  2501. wcd938x_compare_of,
  2502. tx_node);
  2503. return 0;
  2504. }
  2505. static int wcd938x_wakeup(void *handle, bool enable)
  2506. {
  2507. struct wcd938x_priv *priv;
  2508. if (!handle) {
  2509. pr_err("%s: NULL handle\n", __func__);
  2510. return -EINVAL;
  2511. }
  2512. priv = (struct wcd938x_priv *)handle;
  2513. if (!priv->tx_swr_dev) {
  2514. pr_err("%s: tx swr dev is NULL\n", __func__);
  2515. return -EINVAL;
  2516. }
  2517. if (enable)
  2518. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2519. else
  2520. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2521. }
  2522. static int wcd938x_probe(struct platform_device *pdev)
  2523. {
  2524. struct component_match *match = NULL;
  2525. struct wcd938x_priv *wcd938x = NULL;
  2526. struct wcd938x_pdata *pdata = NULL;
  2527. struct wcd_ctrl_platform_data *plat_data = NULL;
  2528. struct device *dev = &pdev->dev;
  2529. int ret;
  2530. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  2531. GFP_KERNEL);
  2532. if (!wcd938x)
  2533. return -ENOMEM;
  2534. dev_set_drvdata(dev, wcd938x);
  2535. pdata = wcd938x_populate_dt_data(dev);
  2536. if (!pdata) {
  2537. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2538. return -EINVAL;
  2539. }
  2540. dev->platform_data = pdata;
  2541. wcd938x->rst_np = pdata->rst_np;
  2542. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  2543. pdata->regulator, pdata->num_supplies);
  2544. if (!wcd938x->supplies) {
  2545. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2546. __func__);
  2547. return ret;
  2548. }
  2549. plat_data = dev_get_platdata(dev->parent);
  2550. if (!plat_data) {
  2551. dev_err(dev, "%s: platform data from parent is NULL\n",
  2552. __func__);
  2553. return -EINVAL;
  2554. }
  2555. wcd938x->handle = (void *)plat_data->handle;
  2556. if (!wcd938x->handle) {
  2557. dev_err(dev, "%s: handle is NULL\n", __func__);
  2558. return -EINVAL;
  2559. }
  2560. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  2561. if (!wcd938x->update_wcd_event) {
  2562. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2563. __func__);
  2564. return -EINVAL;
  2565. }
  2566. wcd938x->register_notifier = plat_data->register_notifier;
  2567. if (!wcd938x->register_notifier) {
  2568. dev_err(dev, "%s: register_notifier api is null!\n",
  2569. __func__);
  2570. return -EINVAL;
  2571. }
  2572. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  2573. pdata->regulator,
  2574. pdata->num_supplies);
  2575. if (ret) {
  2576. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2577. __func__);
  2578. return ret;
  2579. }
  2580. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  2581. CODEC_RX);
  2582. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  2583. CODEC_TX);
  2584. if (ret) {
  2585. dev_err(dev, "Failed to read port mapping\n");
  2586. goto err;
  2587. }
  2588. ret = wcd938x_add_slave_components(dev, &match);
  2589. if (ret)
  2590. goto err;
  2591. wcd938x_reset(dev);
  2592. wcd938x->wakeup = wcd938x_wakeup;
  2593. return component_master_add_with_match(dev,
  2594. &wcd938x_comp_ops, match);
  2595. err:
  2596. return ret;
  2597. }
  2598. static int wcd938x_remove(struct platform_device *pdev)
  2599. {
  2600. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  2601. dev_set_drvdata(&pdev->dev, NULL);
  2602. return 0;
  2603. }
  2604. #ifdef CONFIG_PM_SLEEP
  2605. static int wcd938x_suspend(struct device *dev)
  2606. {
  2607. return 0;
  2608. }
  2609. static int wcd938x_resume(struct device *dev)
  2610. {
  2611. return 0;
  2612. }
  2613. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  2614. SET_SYSTEM_SLEEP_PM_OPS(
  2615. wcd938x_suspend,
  2616. wcd938x_resume
  2617. )
  2618. };
  2619. #endif
  2620. static struct platform_driver wcd938x_codec_driver = {
  2621. .probe = wcd938x_probe,
  2622. .remove = wcd938x_remove,
  2623. .driver = {
  2624. .name = "wcd938x_codec",
  2625. .owner = THIS_MODULE,
  2626. .of_match_table = of_match_ptr(wcd938x_dt_match),
  2627. #ifdef CONFIG_PM_SLEEP
  2628. .pm = &wcd938x_dev_pm_ops,
  2629. #endif
  2630. .suppress_bind_attrs = true,
  2631. },
  2632. };
  2633. module_platform_driver(wcd938x_codec_driver);
  2634. MODULE_DESCRIPTION("WCD938X Codec driver");
  2635. MODULE_LICENSE("GPL v2");