sde_hw_util.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5. */
  6. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  7. #include <drm/sde_drm.h>
  8. #include "msm_drv.h"
  9. #include "sde_kms.h"
  10. #include "sde_hw_mdss.h"
  11. #include "sde_hw_util.h"
  12. /* using a file static variables for debugfs access */
  13. static u32 sde_hw_util_log_mask = SDE_DBG_MASK_NONE;
  14. /* SDE_SCALER_QSEED3 */
  15. #define QSEED3_HW_VERSION 0x00
  16. #define QSEED3_OP_MODE 0x04
  17. #define QSEED3_RGB2Y_COEFF 0x08
  18. #define QSEED3_PHASE_INIT 0x0C
  19. #define QSEED3_PHASE_STEP_Y_H 0x10
  20. #define QSEED3_PHASE_STEP_Y_V 0x14
  21. #define QSEED3_PHASE_STEP_UV_H 0x18
  22. #define QSEED3_PHASE_STEP_UV_V 0x1C
  23. #define QSEED3_PRELOAD 0x20
  24. #define QSEED3_DE_SHARPEN 0x24
  25. #define QSEED3_DE_SHARPEN_CTL 0x28
  26. #define QSEED3_DE_SHAPE_CTL 0x2C
  27. #define QSEED3_DE_THRESHOLD 0x30
  28. #define QSEED3_DE_ADJUST_DATA_0 0x34
  29. #define QSEED3_DE_ADJUST_DATA_1 0x38
  30. #define QSEED3_DE_ADJUST_DATA_2 0x3C
  31. #define QSEED3_DE_LPF_BLEND 0x64
  32. #define QSEED3_SRC_SIZE_Y_RGB_A 0x40
  33. #define QSEED3_SRC_SIZE_UV 0x44
  34. #define QSEED3_DST_SIZE 0x48
  35. #define QSEED3_COEF_LUT_CTRL 0x4C
  36. #define QSEED3_COEF_LUT_SWAP_BIT 0
  37. #define QSEED3_BUFFER_CTRL 0x50
  38. #define QSEED3_CLK_CTRL0 0x54
  39. #define QSEED3_CLK_CTRL1 0x58
  40. #define QSEED3_CLK_STATUS 0x5C
  41. #define QSEED3_MISR_CTRL 0x70
  42. #define QSEED3_MISR_SIGNATURE_0 0x74
  43. #define QSEED3_MISR_SIGNATURE_1 0x78
  44. #define QSEED3_PHASE_INIT_Y_H 0x90
  45. #define QSEED3_PHASE_INIT_Y_V 0x94
  46. #define QSEED3_PHASE_INIT_UV_H 0x98
  47. #define QSEED3_PHASE_INIT_UV_V 0x9C
  48. #define QSEED3_ENABLE 2
  49. #define CSC_MATRIX_SHIFT 7
  50. /* SDE_SCALER_QSEED3LITE */
  51. #define QSEED3L_COEF_LUT_Y_SEP_BIT 4
  52. #define QSEED3L_COEF_LUT_UV_SEP_BIT 5
  53. #define QSEED3L_COEF_LUT_CTRL 0x4C
  54. #define QSEED3L_COEF_LUT_SWAP_BIT 0
  55. #define QSEED3L_DIR_FILTER_WEIGHT 0x60
  56. #define QSEED3LITE_SCALER_VERSION 0x2004
  57. #define QSEED4_SCALER_VERSION 0x3000
  58. #define QSEED3_DEFAULT_PRELOAD_V 0x3
  59. #define QSEED3_DEFAULT_PRELOAD_H 0x4
  60. #define QSEED4_DEFAULT_PRELOAD_V 0x2
  61. #define QSEED4_DEFAULT_PRELOAD_H 0x4
  62. #define QSEED5_DEFAULT_DE_LPF_BLEND 0x3FF00000
  63. typedef void (*scaler_lut_type)(struct sde_hw_blk_reg_map *,
  64. struct sde_hw_scaler3_cfg *, u32);
  65. void sde_reg_write(struct sde_hw_blk_reg_map *c,
  66. u32 reg_off,
  67. u32 val,
  68. const char *name)
  69. {
  70. /* don't need to mutex protect this */
  71. if (c->log_mask & sde_hw_util_log_mask)
  72. SDE_DEBUG_DRIVER("[%s:0x%X] <= 0x%X\n",
  73. name, c->blk_off + reg_off, val);
  74. writel_relaxed(val, c->base_off + c->blk_off + reg_off);
  75. SDE_REG_LOG(c->log_mask ? ilog2(c->log_mask)+1 : 0,
  76. val, c->blk_off + reg_off);
  77. }
  78. int sde_reg_read(struct sde_hw_blk_reg_map *c, u32 reg_off)
  79. {
  80. return readl_relaxed(c->base_off + c->blk_off + reg_off);
  81. }
  82. u32 *sde_hw_util_get_log_mask_ptr(void)
  83. {
  84. return &sde_hw_util_log_mask;
  85. }
  86. void sde_init_scaler_blk(struct sde_scaler_blk *blk, u32 version)
  87. {
  88. if (!blk)
  89. return;
  90. blk->version = version;
  91. blk->v_preload = QSEED4_DEFAULT_PRELOAD_V;
  92. blk->h_preload = QSEED4_DEFAULT_PRELOAD_H;
  93. if (version < QSEED4_SCALER_VERSION) {
  94. blk->v_preload = QSEED3_DEFAULT_PRELOAD_V;
  95. blk->h_preload = QSEED3_DEFAULT_PRELOAD_H;
  96. }
  97. }
  98. void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
  99. const struct sde_drm_scaler_v2 *scale_v2)
  100. {
  101. int i;
  102. cfg->enable = scale_v2->enable;
  103. cfg->dir_en = scale_v2->dir_en;
  104. cfg->dir45_en = scale_v2->dir45_en;
  105. cfg->cor_en = scale_v2->cor_en;
  106. for (i = 0; i < SDE_MAX_PLANES; i++) {
  107. cfg->init_phase_x[i] = scale_v2->init_phase_x[i];
  108. cfg->phase_step_x[i] = scale_v2->phase_step_x[i];
  109. cfg->init_phase_y[i] = scale_v2->init_phase_y[i];
  110. cfg->phase_step_y[i] = scale_v2->phase_step_y[i];
  111. cfg->preload_x[i] = scale_v2->preload_x[i];
  112. cfg->preload_y[i] = scale_v2->preload_y[i];
  113. cfg->src_width[i] = scale_v2->src_width[i];
  114. cfg->src_height[i] = scale_v2->src_height[i];
  115. }
  116. cfg->dst_width = scale_v2->dst_width;
  117. cfg->dst_height = scale_v2->dst_height;
  118. cfg->y_rgb_filter_cfg = scale_v2->y_rgb_filter_cfg;
  119. cfg->uv_filter_cfg = scale_v2->uv_filter_cfg;
  120. cfg->alpha_filter_cfg = scale_v2->alpha_filter_cfg;
  121. cfg->blend_cfg = scale_v2->blend_cfg;
  122. cfg->lut_flag = scale_v2->lut_flag;
  123. cfg->dir_lut_idx = scale_v2->dir_lut_idx;
  124. cfg->y_rgb_cir_lut_idx = scale_v2->y_rgb_cir_lut_idx;
  125. cfg->uv_cir_lut_idx = scale_v2->uv_cir_lut_idx;
  126. cfg->y_rgb_sep_lut_idx = scale_v2->y_rgb_sep_lut_idx;
  127. cfg->uv_sep_lut_idx = scale_v2->uv_sep_lut_idx;
  128. cfg->de.prec_shift = scale_v2->de.prec_shift;
  129. cfg->dir_weight = scale_v2->dir_weight;
  130. cfg->dyn_exp_disabled = (scale_v2->flags & SDE_DYN_EXP_DISABLE) ? 1 : 0;
  131. cfg->de.enable = scale_v2->de.enable;
  132. cfg->de.sharpen_level1 = scale_v2->de.sharpen_level1;
  133. cfg->de.sharpen_level2 = scale_v2->de.sharpen_level2;
  134. cfg->de.clip = scale_v2->de.clip;
  135. cfg->de.limit = scale_v2->de.limit;
  136. cfg->de.thr_quiet = scale_v2->de.thr_quiet;
  137. cfg->de.thr_dieout = scale_v2->de.thr_dieout;
  138. cfg->de.thr_low = scale_v2->de.thr_low;
  139. cfg->de.thr_high = scale_v2->de.thr_high;
  140. cfg->de.blend = scale_v2->de_blend;
  141. cfg->de_lpf_flags = scale_v2->de_lpf_flags;
  142. cfg->de_lpf_h = scale_v2->de_lpf_h;
  143. cfg->de_lpf_l = scale_v2->de_lpf_l;
  144. cfg->de_lpf_m = scale_v2->de_lpf_m;
  145. for (i = 0; i < SDE_MAX_DE_CURVES; i++) {
  146. cfg->de.adjust_a[i] = scale_v2->de.adjust_a[i];
  147. cfg->de.adjust_b[i] = scale_v2->de.adjust_b[i];
  148. cfg->de.adjust_c[i] = scale_v2->de.adjust_c[i];
  149. }
  150. }
  151. static void _sde_hw_setup_scaler3_lut(struct sde_hw_blk_reg_map *c,
  152. struct sde_hw_scaler3_cfg *scaler3_cfg, u32 offset)
  153. {
  154. int i, j, filter;
  155. int config_lut = 0x0;
  156. unsigned long lut_flags;
  157. u32 lut_addr, lut_offset, lut_len;
  158. u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL};
  159. static const uint32_t off_tbl[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = {
  160. {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} },
  161. {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} },
  162. {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} },
  163. {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} },
  164. {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} },
  165. };
  166. lut_flags = (unsigned long) scaler3_cfg->lut_flag;
  167. if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) &&
  168. (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
  169. lut[0] = scaler3_cfg->dir_lut;
  170. config_lut = 1;
  171. }
  172. if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) &&
  173. (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
  174. (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
  175. lut[1] = scaler3_cfg->cir_lut +
  176. scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
  177. config_lut = 1;
  178. }
  179. if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) &&
  180. (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
  181. (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
  182. lut[2] = scaler3_cfg->cir_lut +
  183. scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
  184. config_lut = 1;
  185. }
  186. if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
  187. (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
  188. (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
  189. lut[3] = scaler3_cfg->sep_lut +
  190. scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
  191. config_lut = 1;
  192. }
  193. if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
  194. (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
  195. (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
  196. lut[4] = scaler3_cfg->sep_lut +
  197. scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
  198. config_lut = 1;
  199. }
  200. if (config_lut) {
  201. for (filter = 0; filter < QSEED3_FILTERS; filter++) {
  202. if (!lut[filter])
  203. continue;
  204. lut_offset = 0;
  205. for (i = 0; i < QSEED3_LUT_REGIONS; i++) {
  206. lut_addr = QSEED3_COEF_LUT_OFF + offset
  207. + off_tbl[filter][i][1];
  208. lut_len = off_tbl[filter][i][0] << 2;
  209. for (j = 0; j < lut_len; j++) {
  210. SDE_REG_WRITE(c,
  211. lut_addr,
  212. (lut[filter])[lut_offset++]);
  213. lut_addr += 4;
  214. }
  215. }
  216. }
  217. }
  218. if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags))
  219. SDE_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0));
  220. }
  221. static void _sde_hw_setup_scaler3lite_lut(struct sde_hw_blk_reg_map *c,
  222. struct sde_hw_scaler3_cfg *scaler3_cfg, u32 offset)
  223. {
  224. int i, filter;
  225. int config_lut = 0x0;
  226. unsigned long lut_flags;
  227. u32 lut_addr, lut_offset;
  228. u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL};
  229. static const uint32_t off_tbl[QSEED3LITE_FILTERS] = {0x000, 0x200};
  230. SDE_REG_WRITE(c, QSEED3L_DIR_FILTER_WEIGHT + offset,
  231. scaler3_cfg->dir_weight & 0xFF);
  232. /* destination scaler case */
  233. if (!scaler3_cfg->sep_lut)
  234. return;
  235. lut_flags = (unsigned long) scaler3_cfg->lut_flag;
  236. if (test_bit(QSEED3L_COEF_LUT_Y_SEP_BIT, &lut_flags) &&
  237. (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3L_SEPARABLE_LUTS) &&
  238. (scaler3_cfg->sep_len == QSEED3L_SEP_LUT_SIZE)) {
  239. lut[0] = scaler3_cfg->sep_lut +
  240. scaler3_cfg->y_rgb_sep_lut_idx * QSEED3L_LUT_SIZE;
  241. config_lut = 1;
  242. }
  243. if (test_bit(QSEED3L_COEF_LUT_UV_SEP_BIT, &lut_flags) &&
  244. (scaler3_cfg->uv_sep_lut_idx < QSEED3L_SEPARABLE_LUTS) &&
  245. (scaler3_cfg->sep_len == QSEED3L_SEP_LUT_SIZE)) {
  246. lut[1] = scaler3_cfg->sep_lut +
  247. scaler3_cfg->uv_sep_lut_idx * QSEED3L_LUT_SIZE;
  248. config_lut = 1;
  249. }
  250. if (config_lut) {
  251. for (filter = 0; filter < QSEED3LITE_FILTERS; filter++) {
  252. if (!lut[filter])
  253. continue;
  254. lut_offset = 0;
  255. lut_addr = QSEED3L_COEF_LUT_OFF + offset +
  256. off_tbl[filter];
  257. for (i = 0; i < QSEED3L_LUT_SIZE; i++) {
  258. SDE_REG_WRITE(c, lut_addr,
  259. (lut[filter])[lut_offset++]);
  260. lut_addr += 4;
  261. }
  262. }
  263. }
  264. if (test_bit(QSEED3L_COEF_LUT_SWAP_BIT, &lut_flags))
  265. SDE_REG_WRITE(c, QSEED3L_COEF_LUT_CTRL + offset, BIT(0));
  266. }
  267. static void _sde_hw_setup_scaler3_de(struct sde_hw_blk_reg_map *c,
  268. struct sde_hw_scaler3_de_cfg *de_cfg, u32 offset)
  269. {
  270. u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr;
  271. u32 adjust_a, adjust_b, adjust_c;
  272. if (!de_cfg->enable)
  273. return;
  274. sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) |
  275. ((de_cfg->sharpen_level2 & 0x1FF) << 16);
  276. sharp_ctl = ((de_cfg->limit & 0xF) << 9) |
  277. ((de_cfg->prec_shift & 0x7) << 13) |
  278. ((de_cfg->clip & 0x7) << 16) |
  279. ((de_cfg->blend & 0xF) << 20);
  280. shape_ctl = (de_cfg->thr_quiet & 0xFF) |
  281. ((de_cfg->thr_dieout & 0x3FF) << 16);
  282. de_thr = (de_cfg->thr_low & 0x3FF) |
  283. ((de_cfg->thr_high & 0x3FF) << 16);
  284. adjust_a = (de_cfg->adjust_a[0] & 0x3FF) |
  285. ((de_cfg->adjust_a[1] & 0x3FF) << 10) |
  286. ((de_cfg->adjust_a[2] & 0x3FF) << 20);
  287. adjust_b = (de_cfg->adjust_b[0] & 0x3FF) |
  288. ((de_cfg->adjust_b[1] & 0x3FF) << 10) |
  289. ((de_cfg->adjust_b[2] & 0x3FF) << 20);
  290. adjust_c = (de_cfg->adjust_c[0] & 0x3FF) |
  291. ((de_cfg->adjust_c[1] & 0x3FF) << 10) |
  292. ((de_cfg->adjust_c[2] & 0x3FF) << 20);
  293. SDE_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl);
  294. SDE_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl);
  295. SDE_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl);
  296. SDE_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr);
  297. SDE_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a);
  298. SDE_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_1 + offset, adjust_b);
  299. SDE_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_2 + offset, adjust_c);
  300. }
  301. static inline scaler_lut_type get_scaler_lut(
  302. struct sde_hw_scaler3_cfg *scaler3_cfg, u32 scaler_version)
  303. {
  304. scaler_lut_type lut_ptr = _sde_hw_setup_scaler3lite_lut;
  305. if (!(scaler3_cfg->lut_flag))
  306. return NULL;
  307. if (scaler_version < QSEED3LITE_SCALER_VERSION)
  308. lut_ptr = _sde_hw_setup_scaler3_lut;
  309. return lut_ptr;
  310. }
  311. void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c,
  312. struct sde_hw_scaler3_cfg *scaler3_cfg, u32 scaler_version,
  313. u32 scaler_offset, const struct sde_format *format, bool de_lpf)
  314. {
  315. u32 op_mode = 0;
  316. u32 phase_init, preload, src_y_rgb, src_uv, dst;
  317. scaler_lut_type setup_lut = NULL;
  318. u32 de_lpf_blend = 0;
  319. if (!scaler3_cfg->enable)
  320. goto end;
  321. op_mode |= BIT(0);
  322. op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
  323. if (format && SDE_FORMAT_IS_YUV(format)) {
  324. op_mode |= BIT(12);
  325. op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
  326. }
  327. op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
  328. op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
  329. op_mode |= (scaler3_cfg->dir_en && scaler3_cfg->cor_en) ? BIT(5) : 0;
  330. op_mode |= (scaler3_cfg->dir_en && scaler3_cfg->dir45_en) ? BIT(6) : 0;
  331. op_mode |= (scaler3_cfg->dyn_exp_disabled) ? BIT(13) : 0;
  332. preload =
  333. ((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
  334. ((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
  335. ((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
  336. ((scaler3_cfg->preload_y[1] & 0x7F) << 24);
  337. src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
  338. ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
  339. src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
  340. ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
  341. dst = (scaler3_cfg->dst_width & 0x1FFFF) |
  342. ((scaler3_cfg->dst_height & 0x1FFFF) << 16);
  343. if (scaler3_cfg->de.enable) {
  344. _sde_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset);
  345. op_mode |= BIT(8);
  346. }
  347. setup_lut = get_scaler_lut(scaler3_cfg, scaler_version);
  348. if (setup_lut)
  349. setup_lut(c, scaler3_cfg, scaler_offset);
  350. if (scaler_version == 0x1002) {
  351. phase_init =
  352. ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
  353. ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
  354. ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
  355. ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
  356. SDE_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init);
  357. } else {
  358. SDE_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset,
  359. scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
  360. SDE_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset,
  361. scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
  362. SDE_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset,
  363. scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
  364. SDE_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset,
  365. scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
  366. }
  367. SDE_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset,
  368. scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
  369. SDE_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset,
  370. scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
  371. SDE_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset,
  372. scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
  373. SDE_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset,
  374. scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
  375. SDE_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload);
  376. SDE_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb);
  377. SDE_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv);
  378. SDE_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
  379. if (de_lpf) {
  380. if (scaler3_cfg->de_lpf_flags & SDE_DE_LPF_BLEND_FLAG_EN) {
  381. de_lpf_blend = (scaler3_cfg->de_lpf_l & 0x3FF) |
  382. ((scaler3_cfg->de_lpf_m & 0x3FF) << 10) |
  383. ((scaler3_cfg->de_lpf_h & 0x3FF) << 20);
  384. SDE_REG_WRITE(c, QSEED3_DE_LPF_BLEND +
  385. scaler_offset, de_lpf_blend);
  386. } else {
  387. SDE_REG_WRITE(c, QSEED3_DE_LPF_BLEND + scaler_offset,
  388. QSEED5_DEFAULT_DE_LPF_BLEND);
  389. }
  390. }
  391. end:
  392. if (format && !SDE_FORMAT_IS_DX(format))
  393. op_mode |= BIT(14);
  394. if (format && format->alpha_enable) {
  395. op_mode |= BIT(10);
  396. if (scaler_version == 0x1002)
  397. op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
  398. else
  399. op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
  400. }
  401. SDE_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);
  402. }
  403. void sde_hw_csc_matrix_coeff_setup(struct sde_hw_blk_reg_map *c,
  404. u32 csc_reg_off, struct sde_csc_cfg *data,
  405. u32 shift_bit)
  406. {
  407. u32 val;
  408. if (!c || !data)
  409. return;
  410. val = ((data->csc_mv[0] >> shift_bit) & 0x1FFF) |
  411. (((data->csc_mv[1] >> shift_bit) & 0x1FFF) << 16);
  412. SDE_REG_WRITE(c, csc_reg_off, val);
  413. val = ((data->csc_mv[2] >> shift_bit) & 0x1FFF) |
  414. (((data->csc_mv[3] >> shift_bit) & 0x1FFF) << 16);
  415. SDE_REG_WRITE(c, csc_reg_off + 0x4, val);
  416. val = ((data->csc_mv[4] >> shift_bit) & 0x1FFF) |
  417. (((data->csc_mv[5] >> shift_bit) & 0x1FFF) << 16);
  418. SDE_REG_WRITE(c, csc_reg_off + 0x8, val);
  419. val = ((data->csc_mv[6] >> shift_bit) & 0x1FFF) |
  420. (((data->csc_mv[7] >> shift_bit) & 0x1FFF) << 16);
  421. SDE_REG_WRITE(c, csc_reg_off + 0xc, val);
  422. val = (data->csc_mv[8] >> shift_bit) & 0x1FFF;
  423. SDE_REG_WRITE(c, csc_reg_off + 0x10, val);
  424. }
  425. void sde_hw_csc_setup(struct sde_hw_blk_reg_map *c,
  426. u32 csc_reg_off,
  427. struct sde_csc_cfg *data, bool csc10)
  428. {
  429. u32 clamp_shift = csc10 ? 16 : 8;
  430. u32 val;
  431. if (!c || !data)
  432. return;
  433. /* matrix coeff - convert S15.16 to S4.9 */
  434. sde_hw_csc_matrix_coeff_setup(c, csc_reg_off, data, CSC_MATRIX_SHIFT);
  435. /* Pre clamp */
  436. val = (data->csc_pre_lv[0] << clamp_shift) | data->csc_pre_lv[1];
  437. SDE_REG_WRITE(c, csc_reg_off + 0x14, val);
  438. val = (data->csc_pre_lv[2] << clamp_shift) | data->csc_pre_lv[3];
  439. SDE_REG_WRITE(c, csc_reg_off + 0x18, val);
  440. val = (data->csc_pre_lv[4] << clamp_shift) | data->csc_pre_lv[5];
  441. SDE_REG_WRITE(c, csc_reg_off + 0x1c, val);
  442. /* Post clamp */
  443. val = (data->csc_post_lv[0] << clamp_shift) | data->csc_post_lv[1];
  444. SDE_REG_WRITE(c, csc_reg_off + 0x20, val);
  445. val = (data->csc_post_lv[2] << clamp_shift) | data->csc_post_lv[3];
  446. SDE_REG_WRITE(c, csc_reg_off + 0x24, val);
  447. val = (data->csc_post_lv[4] << clamp_shift) | data->csc_post_lv[5];
  448. SDE_REG_WRITE(c, csc_reg_off + 0x28, val);
  449. /* Pre-Bias */
  450. SDE_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]);
  451. SDE_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]);
  452. SDE_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]);
  453. /* Post-Bias */
  454. SDE_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]);
  455. SDE_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
  456. SDE_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
  457. }
  458. /**
  459. * _sde_copy_formats - copy formats from src_list to dst_list
  460. * @dst_list: pointer to destination list where to copy formats
  461. * @dst_list_size: size of destination list
  462. * @dst_list_pos: starting position on the list where to copy formats
  463. * @src_list: pointer to source list where to copy formats from
  464. * @src_list_size: size of source list
  465. * Return: number of elements populated
  466. */
  467. uint32_t sde_copy_formats(
  468. struct sde_format_extended *dst_list,
  469. uint32_t dst_list_size,
  470. uint32_t dst_list_pos,
  471. const struct sde_format_extended *src_list,
  472. uint32_t src_list_size)
  473. {
  474. uint32_t cur_pos, i;
  475. if (!dst_list || !src_list || (dst_list_pos >= (dst_list_size - 1)))
  476. return 0;
  477. for (i = 0, cur_pos = dst_list_pos;
  478. (cur_pos < (dst_list_size - 1)) && (i < src_list_size)
  479. && src_list[i].fourcc_format; ++i, ++cur_pos)
  480. dst_list[cur_pos] = src_list[i];
  481. dst_list[cur_pos].fourcc_format = 0;
  482. return i;
  483. }