hal_rh_rx.h 21 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_RH_RX_H_
  20. #define _HAL_RH_RX_H_
  21. #include <hal_rx.h>
  22. #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \
  23. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  24. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \
  25. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \
  26. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB))
  27. #define HAL_RX_BUF_RBM_GET(buff_addr_info) \
  28. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  29. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\
  30. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \
  31. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB))
  32. /*
  33. * macro to set the cookie into the rxdma ring entry
  34. */
  35. #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
  36. ((*(((unsigned int *)buff_addr_info) + \
  37. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  38. ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \
  39. ((*(((unsigned int *)buff_addr_info) + \
  40. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  41. ((cookie) << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
  42. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
  43. /*
  44. * macro to set the manager into the rxdma ring entry
  45. */
  46. #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
  47. ((*(((unsigned int *)buff_addr_info) + \
  48. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
  49. ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \
  50. ((*(((unsigned int *)buff_addr_info) + \
  51. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
  52. ((manager) << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
  53. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)
  54. /*
  55. * NOTE: None of the following _GET macros need a right
  56. * shift by the corresponding _LSB. This is because, they are
  57. * finally taken and "OR'ed" into a single word again.
  58. */
  59. #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \
  60. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  61. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \
  62. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  63. #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  64. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  65. RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \
  66. RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK)
  67. #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  68. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  69. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \
  70. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK)
  71. #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  72. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  73. RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \
  74. RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK)
  75. #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \
  76. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  77. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \
  78. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK)
  79. #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  80. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  81. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \
  82. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK)
  83. /*
  84. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  85. * pre-header.
  86. */
  87. /*
  88. * Every Rx packet starts at an offset from the top of the buffer.
  89. * If the host hasn't subscribed to any specific TLV, there is
  90. * still space reserved for the following TLV's from the start of
  91. * the buffer:
  92. * -- RX ATTENTION
  93. * -- RX MPDU START
  94. * -- RX MSDU START
  95. * -- RX MSDU END
  96. * -- RX MPDU END
  97. * -- RX PACKET HEADER (802.11)
  98. * If the host subscribes to any of the TLV's above, that TLV
  99. * if populated by the HW
  100. */
  101. #define NUM_DWORDS_TAG 1
  102. /* By default the packet header TLV is 128 bytes */
  103. #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128
  104. #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \
  105. (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2)
  106. #define RX_PKT_OFFSET_WORDS \
  107. ( \
  108. NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \
  109. NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \
  110. NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \
  111. NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \
  112. NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \
  113. NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \
  114. )
  115. #define RX_PKT_OFFSET_BYTES \
  116. (RX_PKT_OFFSET_WORDS << 2)
  117. #define RX_PKT_HDR_TLV_LEN 120
  118. /*
  119. * Each RX descriptor TLV is preceded by 1 DWORD "tag"
  120. */
  121. struct rx_attention_tlv {
  122. uint32_t tag;
  123. struct rx_attention rx_attn;
  124. };
  125. struct rx_mpdu_start_tlv {
  126. uint32_t tag;
  127. struct rx_mpdu_start rx_mpdu_start;
  128. };
  129. struct rx_msdu_start_tlv {
  130. uint32_t tag;
  131. struct rx_msdu_start rx_msdu_start;
  132. };
  133. struct rx_msdu_end_tlv {
  134. uint32_t tag;
  135. struct rx_msdu_end rx_msdu_end;
  136. };
  137. struct rx_mpdu_end_tlv {
  138. uint32_t tag;
  139. struct rx_mpdu_end rx_mpdu_end;
  140. };
  141. struct rx_pkt_hdr_tlv {
  142. uint32_t tag; /* 4 B */
  143. uint32_t phy_ppdu_id; /* 4 B */
  144. char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */
  145. };
  146. /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status
  147. * buffers, monitor destination buffers and monitor descriptor buffers.
  148. */
  149. #ifdef RXDMA_OPTIMIZATION
  150. /*
  151. * The RX_PADDING_BYTES is required so that the TLV's don't
  152. * spread across the 128 byte boundary
  153. * RXDMA optimization requires:
  154. * 1) MSDU_END & ATTENTION TLV's follow in that order
  155. * 2) TLV's don't span across 128 byte lines
  156. * 3) Rx Buffer is nicely aligned on the 128 byte boundary
  157. */
  158. #define RX_PADDING0_BYTES 4
  159. #define RX_PADDING1_BYTES 16
  160. struct rx_pkt_tlvs {
  161. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  162. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  163. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  164. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  165. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  166. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  167. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  168. #ifndef NO_RX_PKT_HDR_TLV
  169. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  170. #endif
  171. };
  172. #else /* RXDMA_OPTIMIZATION */
  173. struct rx_pkt_tlvs {
  174. struct rx_attention_tlv attn_tlv;
  175. struct rx_mpdu_start_tlv mpdu_start_tlv;
  176. struct rx_msdu_start_tlv msdu_start_tlv;
  177. struct rx_msdu_end_tlv msdu_end_tlv;
  178. struct rx_mpdu_end_tlv mpdu_end_tlv;
  179. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  180. };
  181. #endif /* RXDMA_OPTIMIZATION */
  182. /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */
  183. #ifdef RXDMA_OPTIMIZATION
  184. struct rx_mon_pkt_tlvs {
  185. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  186. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  187. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  188. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  189. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  190. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  191. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  192. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  193. };
  194. #else /* RXDMA_OPTIMIZATION */
  195. struct rx_mon_pkt_tlvs {
  196. struct rx_attention_tlv attn_tlv;
  197. struct rx_mpdu_start_tlv mpdu_start_tlv;
  198. struct rx_msdu_start_tlv msdu_start_tlv;
  199. struct rx_msdu_end_tlv msdu_end_tlv;
  200. struct rx_mpdu_end_tlv mpdu_end_tlv;
  201. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  202. };
  203. #endif
  204. #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs)
  205. #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs)
  206. #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV
  207. #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field)
  208. #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \
  209. RX_PKT_TLV_OFFSET(mpdu_start_tlv)
  210. #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv)
  211. #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \
  212. RX_PKT_TLV_OFFSET(msdu_start_tlv)
  213. #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv)
  214. #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv)
  215. #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv)
  216. /**
  217. * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf
  218. *
  219. * @rx_buf_start: Pointer to data buffer field
  220. *
  221. * Returns: pointer to rx_pkt_tlvs
  222. */
  223. static inline
  224. struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start)
  225. {
  226. return (struct rx_pkt_tlvs *)rx_buf_start;
  227. }
  228. /**
  229. * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs
  230. *
  231. * @pkt_tlvs: Pointer to pkt_tlvs
  232. * Returns: pointer to rx_mpdu_info structure
  233. */
  234. static inline
  235. struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs)
  236. {
  237. return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  238. }
  239. /**
  240. * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info
  241. * from the reserved bytes of rx_tlv_hdr.
  242. * @buf: start of rx_tlv_hdr
  243. * @buf_info: hal_rx_mon_dest_buf_info structure
  244. *
  245. * Return: void
  246. */
  247. static inline void hal_rx_mon_dest_get_buffer_info_from_tlv(
  248. uint8_t *buf,
  249. struct hal_rx_mon_dest_buf_info *buf_info)
  250. {
  251. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  252. qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0,
  253. sizeof(struct hal_rx_mon_dest_buf_info));
  254. }
  255. /*
  256. * Get msdu_done bit from the RX_ATTENTION TLV
  257. */
  258. #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \
  259. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  260. RX_ATTENTION_2_MSDU_DONE_OFFSET)), \
  261. RX_ATTENTION_2_MSDU_DONE_MASK, \
  262. RX_ATTENTION_2_MSDU_DONE_LSB))
  263. #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \
  264. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  265. RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \
  266. RX_ATTENTION_1_FIRST_MPDU_MASK, \
  267. RX_ATTENTION_1_FIRST_MPDU_LSB))
  268. #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \
  269. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  270. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \
  271. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \
  272. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB))
  273. /*
  274. * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit
  275. * from rx attention
  276. * @buf: pointer to rx_pkt_tlvs
  277. *
  278. * Return: tcp_udp_cksum_fail
  279. */
  280. static inline bool
  281. hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf)
  282. {
  283. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  284. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  285. uint8_t tcp_udp_cksum_fail;
  286. tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn);
  287. return !!tcp_udp_cksum_fail;
  288. }
  289. #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \
  290. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  291. RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \
  292. RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \
  293. RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB))
  294. /*
  295. * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit
  296. * from rx attention
  297. * @buf: pointer to rx_pkt_tlvs
  298. *
  299. * Return: ip_cksum_fail
  300. */
  301. static inline bool
  302. hal_rx_attn_ip_cksum_fail_get(uint8_t *buf)
  303. {
  304. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  305. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  306. uint8_t ip_cksum_fail;
  307. ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn);
  308. return !!ip_cksum_fail;
  309. }
  310. #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \
  311. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  312. RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \
  313. RX_ATTENTION_0_PHY_PPDU_ID_MASK, \
  314. RX_ATTENTION_0_PHY_PPDU_ID_LSB))
  315. #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \
  316. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  317. RX_ATTENTION_1_CCE_MATCH_OFFSET)), \
  318. RX_ATTENTION_1_CCE_MATCH_MASK, \
  319. RX_ATTENTION_1_CCE_MATCH_LSB))
  320. /*
  321. * hal_rx_msdu_cce_match_get_rh(): get CCE match bit
  322. * from rx attention
  323. * @buf: pointer to rx_pkt_tlvs
  324. * Return: CCE match value
  325. */
  326. static inline bool
  327. hal_rx_msdu_cce_match_get_rh(uint8_t *buf)
  328. {
  329. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  330. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  331. uint8_t cce_match_val;
  332. cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn);
  333. return !!cce_match_val;
  334. }
  335. /*
  336. * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
  337. */
  338. #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \
  339. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  340. RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \
  341. RX_MPDU_INFO_8_PEER_META_DATA_MASK, \
  342. RX_MPDU_INFO_8_PEER_META_DATA_LSB))
  343. static inline uint32_t
  344. hal_rx_mpdu_peer_meta_data_get_rh(uint8_t *buf)
  345. {
  346. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  347. struct rx_mpdu_start *mpdu_start =
  348. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  349. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  350. uint32_t peer_meta_data;
  351. peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info);
  352. return peer_meta_data;
  353. }
  354. #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \
  355. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  356. RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \
  357. RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \
  358. RX_MPDU_INFO_12_AMPDU_FLAG_LSB))
  359. /*
  360. * LRO information needed from the TLVs
  361. */
  362. #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \
  363. (_HAL_MS( \
  364. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  365. msdu_end_tlv.rx_msdu_end), \
  366. RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \
  367. RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \
  368. RX_MSDU_END_9_LRO_ELIGIBLE_LSB))
  369. #define HAL_RX_TLV_GET_TCP_ACK(buf) \
  370. (_HAL_MS( \
  371. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  372. msdu_end_tlv.rx_msdu_end), \
  373. RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \
  374. RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \
  375. RX_MSDU_END_8_TCP_ACK_NUMBER_LSB))
  376. #define HAL_RX_TLV_GET_TCP_SEQ(buf) \
  377. (_HAL_MS( \
  378. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  379. msdu_end_tlv.rx_msdu_end), \
  380. RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \
  381. RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \
  382. RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB))
  383. #define HAL_RX_TLV_GET_TCP_WIN(buf) \
  384. (_HAL_MS( \
  385. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  386. msdu_end_tlv.rx_msdu_end), \
  387. RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \
  388. RX_MSDU_END_9_WINDOW_SIZE_MASK, \
  389. RX_MSDU_END_9_WINDOW_SIZE_LSB))
  390. #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \
  391. (_HAL_MS( \
  392. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  393. msdu_start_tlv.rx_msdu_start), \
  394. RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \
  395. RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \
  396. RX_MSDU_START_2_TCP_ONLY_ACK_LSB))
  397. #define HAL_RX_TLV_GET_TCP_PROTO(buf) \
  398. (_HAL_MS( \
  399. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  400. msdu_start_tlv.rx_msdu_start), \
  401. RX_MSDU_START_2_TCP_PROTO_OFFSET)), \
  402. RX_MSDU_START_2_TCP_PROTO_MASK, \
  403. RX_MSDU_START_2_TCP_PROTO_LSB))
  404. #define HAL_RX_TLV_GET_UDP_PROTO(buf) \
  405. (_HAL_MS( \
  406. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  407. msdu_start_tlv.rx_msdu_start), \
  408. RX_MSDU_START_2_UDP_PROTO_OFFSET)), \
  409. RX_MSDU_START_2_UDP_PROTO_MASK, \
  410. RX_MSDU_START_2_UDP_PROTO_LSB))
  411. #define HAL_RX_TLV_GET_IPV6(buf) \
  412. (_HAL_MS( \
  413. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  414. msdu_start_tlv.rx_msdu_start), \
  415. RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \
  416. RX_MSDU_START_2_IPV6_PROTO_MASK, \
  417. RX_MSDU_START_2_IPV6_PROTO_LSB))
  418. #define HAL_RX_TLV_GET_IP_OFFSET(buf) \
  419. (_HAL_MS( \
  420. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  421. msdu_start_tlv.rx_msdu_start), \
  422. RX_MSDU_START_1_L3_OFFSET_OFFSET)), \
  423. RX_MSDU_START_1_L3_OFFSET_MASK, \
  424. RX_MSDU_START_1_L3_OFFSET_LSB))
  425. #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \
  426. (_HAL_MS( \
  427. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  428. msdu_start_tlv.rx_msdu_start), \
  429. RX_MSDU_START_1_L4_OFFSET_OFFSET)), \
  430. RX_MSDU_START_1_L4_OFFSET_MASK, \
  431. RX_MSDU_START_1_L4_OFFSET_LSB))
  432. #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \
  433. (_HAL_MS( \
  434. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  435. msdu_start_tlv.rx_msdu_start), \
  436. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  437. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  438. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  439. #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \
  440. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  441. RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \
  442. RX_MSDU_START_1_MSDU_LENGTH_MASK, \
  443. RX_MSDU_START_1_MSDU_LENGTH_LSB))
  444. #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \
  445. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  446. RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \
  447. RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \
  448. RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB))
  449. #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
  450. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  451. RX_MSDU_START_5_SGI_OFFSET)), \
  452. RX_MSDU_START_5_SGI_MASK, \
  453. RX_MSDU_START_5_SGI_LSB))
  454. #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
  455. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  456. RX_MSDU_START_5_RATE_MCS_OFFSET)), \
  457. RX_MSDU_START_5_RATE_MCS_MASK, \
  458. RX_MSDU_START_5_RATE_MCS_LSB))
  459. #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
  460. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  461. RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \
  462. RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
  463. RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
  464. /*
  465. * Get key index from RX_MSDU_END
  466. */
  467. #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \
  468. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  469. RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \
  470. RX_MSDU_END_2_KEY_ID_OCTET_MASK, \
  471. RX_MSDU_END_2_KEY_ID_OCTET_LSB))
  472. #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \
  473. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  474. RX_MSDU_START_5_USER_RSSI_OFFSET)), \
  475. RX_MSDU_START_5_USER_RSSI_MASK, \
  476. RX_MSDU_START_5_USER_RSSI_LSB))
  477. #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \
  478. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  479. RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \
  480. RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
  481. RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
  482. #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
  483. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  484. RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
  485. RX_MSDU_START_5_PKT_TYPE_MASK, \
  486. RX_MSDU_START_5_PKT_TYPE_LSB))
  487. #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
  488. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  489. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
  490. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
  491. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
  492. #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
  493. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  494. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
  495. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
  496. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
  497. /*******************************************************************************
  498. * RX ERROR APIS
  499. ******************************************************************************/
  500. #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \
  501. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  502. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \
  503. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
  504. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
  505. #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
  506. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  507. RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
  508. RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
  509. RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
  510. #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \
  511. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  512. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \
  513. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \
  514. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB))
  515. /**
  516. * hal_rx_attn_msdu_done_get_rh() - Get msdi done flag from RX TLV
  517. * @buf: RX tlv address
  518. *
  519. * Return: msdu done flag
  520. */
  521. static inline uint32_t hal_rx_attn_msdu_done_get_rh(uint8_t *buf)
  522. {
  523. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  524. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  525. uint32_t msdu_done;
  526. msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn);
  527. return msdu_done;
  528. }
  529. #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \
  530. (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  531. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  532. HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \
  533. HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  534. HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \
  535. HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  536. HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
  537. HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
  538. /**
  539. * hal_rx_msdu_flags_get_rh() - Get msdu flags from ring desc
  540. * @msdu_desc_info_hdl: msdu desc info handle
  541. *
  542. * Return: msdu flags
  543. */
  544. static inline
  545. uint32_t hal_rx_msdu_flags_get_rh(rx_msdu_desc_info_t msdu_desc_info_hdl)
  546. {
  547. struct rx_msdu_desc_info *msdu_desc_info =
  548. (struct rx_msdu_desc_info *)msdu_desc_info_hdl;
  549. return HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  550. }
  551. #define HAL_RX_ATTN_MSDU_LEN_ERR_GET(_rx_attn) \
  552. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  553. RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET)), \
  554. RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK, \
  555. RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB))
  556. /**
  557. * hal_rx_attn_msdu_len_err_get_rh(): Get msdu_len_err value from
  558. * rx attention tlvs
  559. * @buf: pointer to rx pkt tlvs hdr
  560. *
  561. * Return: msdu_len_err value
  562. */
  563. static inline uint32_t
  564. hal_rx_attn_msdu_len_err_get_rh(uint8_t *buf)
  565. {
  566. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  567. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  568. return HAL_RX_ATTN_MSDU_LEN_ERR_GET(rx_attn);
  569. }
  570. #endif /* _HAL_RH_RX_H_ */