hal_be_tx.h 28 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_TX_H_
  20. #define _HAL_BE_TX_H_
  21. #include "hal_be_hw_headers.h"
  22. #include "hal_tx.h"
  23. /* Number of TX banks reserved i.e, will not be used by host driver. */
  24. /* MAX_TCL_BANK reserved for FW use */
  25. #define HAL_TX_NUM_RESERVED_BANKS 1
  26. /*
  27. * Number of Priority to TID mapping
  28. */
  29. #define HAL_BE_TX_MAP0_PRI2TID_MAX 10
  30. #define HAL_BE_TX_MAP1_PRI2TID_MAX 6
  31. enum hal_be_tx_ret_buf_manager {
  32. HAL_BE_WBM_SW0_BM_ID = 5,
  33. HAL_BE_WBM_SW1_BM_ID = 6,
  34. HAL_BE_WBM_SW2_BM_ID = 7,
  35. HAL_BE_WBM_SW3_BM_ID = 8,
  36. HAL_BE_WBM_SW4_BM_ID = 9,
  37. HAL_BE_WBM_SW5_BM_ID = 10,
  38. HAL_BE_WBM_SW6_BM_ID = 11,
  39. };
  40. enum hal_tx_mcast_ctrl {
  41. /* mcast traffic exceptioned to FW
  42. * valid only for AP VAP default for AP
  43. */
  44. HAL_TX_MCAST_CTRL_FW_EXCEPTION = 0,
  45. /* mcast traffic dropped in TCL*/
  46. HAL_TX_MCAST_CTRL_DROP,
  47. /* MEC notification are enabled
  48. * valid only for client VAP
  49. */
  50. HAL_TX_MCAST_CTRL_MEC_NOTIFY,
  51. /* no special routing for mcast
  52. * valid for client vap when index search is enabled
  53. */
  54. HAL_TX_MCAST_CTRL_NO_SPECIAL,
  55. };
  56. /**
  57. * enum hal_tx_notify_frame_type - TX notify frame type
  58. * @NO_TX_NOTIFY: Not a notify frame
  59. * @TX_HARD_NOTIFY: Hard notify TX frame
  60. * @TX_SOFT_NOTIFY_E: Soft Notify Tx frame
  61. * @TX_SEMI_HARD_NOTIFY_E: Semi Hard notify TX frame
  62. */
  63. enum hal_tx_notify_frame_type {
  64. NO_TX_NOTIFY = 0,
  65. TX_HARD_NOTIFY = 1,
  66. TX_SOFT_NOTIFY_E = 2,
  67. TX_SEMI_HARD_NOTIFY_E = 3
  68. };
  69. /*---------------------------------------------------------------------------
  70. * Structures
  71. * ---------------------------------------------------------------------------
  72. */
  73. /**
  74. * union hal_tx_bank_config - SW config bank params
  75. * @epd: EPD indication flag
  76. * @encap_type: encapsulation type
  77. * @encrypt_type: encrypt type
  78. * @src_buffer_swap: big-endia switch for packet buffer
  79. * @link_meta_swap: big-endian switch for link metadata
  80. * @index_lookup_enable: Enable index lookup
  81. * @addrx_en: Address-X search
  82. * @addry_en: Address-Y search
  83. * @mesh_enable:mesh enable flag
  84. * @vdev_id_check_en: vdev id check
  85. * @pmac_id: mac id
  86. * @mcast_pkt_ctrl: mulitcast packet control
  87. * @dscp_tid_map_id: DSCP to TID map id
  88. * @reserved: unused bits
  89. * @val: value representing bank config
  90. */
  91. union hal_tx_bank_config {
  92. struct {
  93. uint32_t epd:1,
  94. encap_type:2,
  95. encrypt_type:4,
  96. src_buffer_swap:1,
  97. link_meta_swap:1,
  98. index_lookup_enable:1,
  99. addrx_en:1,
  100. addry_en:1,
  101. mesh_enable:2,
  102. vdev_id_check_en:1,
  103. pmac_id:2,
  104. mcast_pkt_ctrl:2,
  105. dscp_tid_map_id:6,
  106. reserved:7;
  107. };
  108. uint32_t val;
  109. };
  110. /**
  111. * union hal_tx_cmn_config_ppe - SW config exception related parameters
  112. * @drop_prec_err: Exception drop_prec errors.
  113. * @fake_mac_hdr: Exception fake mac header.
  114. * @cpu_code_inv: Exception cpu code invalid.
  115. * @data_buff_err: Exception buffer length/offset erorors.
  116. * @l3_l4_err: Exception m3_l4 checksum errors
  117. * @data_offset_max: Maximum data offset allowed.
  118. * @data_len_max: Maximum data length allowed.
  119. * @val: aggregate 32-bit value
  120. */
  121. union hal_tx_cmn_config_ppe {
  122. struct {
  123. uint32_t drop_prec_err:1,
  124. fake_mac_hdr:1,
  125. cpu_code_inv:1,
  126. data_buff_err:1,
  127. l3_l4_err:1,
  128. data_offset_max:12,
  129. data_len_max:14;
  130. };
  131. uint32_t val;
  132. };
  133. /**
  134. * union hal_tx_ppe_vp_config - SW config PPE VP table
  135. * @vp_num: Virtual port number
  136. * @pmac_id: Lmac ID
  137. * @bank_id: Bank ID corresponding to this I/F.
  138. * @vdev_id: VDEV ID of the I/F.
  139. * @search_idx_reg_num: Register number of this SI.
  140. * @use_ppe_int_pri: Use the PPE INT_PRI to TID table
  141. * @to_fw: Use FW
  142. * @drop_prec_enable: Enable precedence drop.
  143. * @val: aggregate 32-bit value
  144. */
  145. union hal_tx_ppe_vp_config {
  146. struct {
  147. uint32_t vp_num:8,
  148. pmac_id:2,
  149. bank_id:6,
  150. vdev_id:8,
  151. search_idx_reg_num:3,
  152. use_ppe_int_pri:1,
  153. to_fw:1,
  154. drop_prec_enable:1;
  155. };
  156. uint32_t val;
  157. };
  158. /**
  159. * union hal_tx_ppe_idx_map_config - Use ppe index mapping table
  160. * @search_idx: Search index
  161. * @cache_set: Cache set number
  162. * @val: aggregate 32-bit value
  163. */
  164. union hal_tx_ppe_idx_map_config {
  165. struct {
  166. uint32_t search_idx:20,
  167. cache_set:4;
  168. };
  169. uint32_t val;
  170. };
  171. /**
  172. * union hal_tx_ppe_pri2tid_map0_config - Configure ppe INT_PRI to tid map
  173. * @int_pri0: INT_PRI_0
  174. * @int_pri1: INT_PRI_1
  175. * @int_pri2: INT_PRI_2
  176. * @int_pri3: INT_PRI_3
  177. * @int_pri4: INT_PRI_4
  178. * @int_pri5: INT_PRI_5
  179. * @int_pri6: INT_PRI_6
  180. * @int_pri7: INT_PRI_7
  181. * @int_pri8: INT_PRI_8
  182. * @int_pri9: INT_PRI_9
  183. * @val: aggregate 32-bit value
  184. */
  185. union hal_tx_ppe_pri2tid_map0_config {
  186. struct {
  187. uint32_t int_pri0:3,
  188. int_pri1:3,
  189. int_pri2:3,
  190. int_pri3:3,
  191. int_pri4:3,
  192. int_pri5:3,
  193. int_pri6:3,
  194. int_pri7:3,
  195. int_pri8:3,
  196. int_pri9:3;
  197. };
  198. uint32_t val;
  199. };
  200. /**
  201. * union hal_tx_ppe_pri2tid_map1_config - Configure ppe INT_PRI to tid map
  202. * @int_pri10: INT_PRI_10
  203. * @int_pri11: INT_PRI_11
  204. * @int_pri12: INT_PRI_12
  205. * @int_pri13: INT_PRI_13
  206. * @int_pri14: INT_PRI_14
  207. * @int_pri15: INT_PRI_15
  208. * @val: aggregate 32-bit value
  209. */
  210. union hal_tx_ppe_pri2tid_map1_config {
  211. struct {
  212. uint32_t int_pri10:3,
  213. int_pri11:3,
  214. int_pri12:3,
  215. int_pri13:3,
  216. int_pri14:3,
  217. int_pri15:3;
  218. };
  219. uint32_t val;
  220. };
  221. /*---------------------------------------------------------------------------
  222. * Function declarations and documentation
  223. * ---------------------------------------------------------------------------
  224. */
  225. /*---------------------------------------------------------------------------
  226. * TCL Descriptor accessor APIs
  227. *---------------------------------------------------------------------------
  228. */
  229. /**
  230. * hal_tx_desc_set_tx_notify_frame() - Set TX notify_frame field in Tx desc
  231. * @desc: Handle to Tx Descriptor
  232. * @val: Value to be set
  233. *
  234. * Return: None
  235. */
  236. static inline void hal_tx_desc_set_tx_notify_frame(void *desc,
  237. uint8_t val)
  238. {
  239. HAL_SET_FLD(desc, TCL_DATA_CMD, TX_NOTIFY_FRAME) |=
  240. HAL_TX_SM(TCL_DATA_CMD, TX_NOTIFY_FRAME, val);
  241. }
  242. /**
  243. * hal_tx_desc_set_flow_override_enable() - Set flow_override_enable field
  244. * @desc: Handle to Tx Descriptor
  245. * @val: Value to be set
  246. *
  247. * Return: None
  248. */
  249. static inline void hal_tx_desc_set_flow_override_enable(void *desc,
  250. uint8_t val)
  251. {
  252. HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE) |=
  253. HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE_ENABLE, val);
  254. }
  255. /**
  256. * hal_tx_desc_set_flow_override() - Set flow_override field in TX desc
  257. * @desc: Handle to Tx Descriptor
  258. * @val: Value to be set
  259. *
  260. * Return: None
  261. */
  262. static inline void hal_tx_desc_set_flow_override(void *desc,
  263. uint8_t val)
  264. {
  265. HAL_SET_FLD(desc, TCL_DATA_CMD, FLOW_OVERRIDE) |=
  266. HAL_TX_SM(TCL_DATA_CMD, FLOW_OVERRIDE, val);
  267. }
  268. /**
  269. * hal_tx_desc_set_who_classify_info_sel() - Set who_classify_info_sel field
  270. * @desc: Handle to Tx Descriptor
  271. * @val: Value to be set
  272. *
  273. * Return: None
  274. */
  275. static inline void hal_tx_desc_set_who_classify_info_sel(void *desc,
  276. uint8_t val)
  277. {
  278. HAL_SET_FLD(desc, TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL) |=
  279. HAL_TX_SM(TCL_DATA_CMD, WHO_CLASSIFY_INFO_SEL, val);
  280. }
  281. /**
  282. * hal_tx_desc_set_buf_length() - Set Data length in bytes in Tx Descriptor
  283. * @desc: Handle to Tx Descriptor
  284. * @data_length: MSDU length in case of direct descriptor.
  285. * Length of link extension descriptor in case of Link extension
  286. * descriptor.Includes the length of Metadata
  287. * Return: None
  288. */
  289. static inline void hal_tx_desc_set_buf_length(void *desc,
  290. uint16_t data_length)
  291. {
  292. HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |=
  293. HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length);
  294. }
  295. /**
  296. * hal_tx_desc_set_buf_offset() - Sets Packet Offset field in Tx descriptor
  297. * @desc: Handle to Tx Descriptor
  298. * @offset: Packet offset from Metadata in case of direct buffer descriptor.
  299. *
  300. * Return: void
  301. */
  302. static inline void hal_tx_desc_set_buf_offset(void *desc,
  303. uint8_t offset)
  304. {
  305. HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |=
  306. HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset);
  307. }
  308. /**
  309. * hal_tx_desc_set_l4_checksum_en() - Set TCP/IP checksum enable flags
  310. * Tx Descriptor for MSDU_buffer type
  311. * @desc: Handle to Tx Descriptor
  312. * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
  313. *
  314. * Return: void
  315. */
  316. static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
  317. uint8_t en)
  318. {
  319. HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
  320. (HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) |
  321. HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) |
  322. HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) |
  323. HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en));
  324. }
  325. /**
  326. * hal_tx_desc_set_l3_checksum_en() - Set IPv4 checksum enable flag in
  327. * Tx Descriptor for MSDU_buffer type
  328. * @desc: Handle to Tx Descriptor
  329. * @en: ipv4 checksum enable flags
  330. *
  331. * Return: void
  332. */
  333. static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
  334. uint8_t en)
  335. {
  336. HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
  337. HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en);
  338. }
  339. /**
  340. * hal_tx_desc_set_fw_metadata() - Sets the metadata that is part of TCL descriptor
  341. * @desc: Handle to Tx Descriptor
  342. * @metadata: Metadata to be sent to Firmware
  343. *
  344. * Return: void
  345. */
  346. static inline void hal_tx_desc_set_fw_metadata(void *desc,
  347. uint16_t metadata)
  348. {
  349. HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |=
  350. HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata);
  351. }
  352. /**
  353. * hal_tx_desc_set_to_fw() - Set To_FW bit in Tx Descriptor.
  354. * @desc: Handle to Tx Descriptor
  355. * @to_fw: if set, Forward packet to FW along with classification result
  356. *
  357. * Return: void
  358. */
  359. static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
  360. {
  361. HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |=
  362. HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw);
  363. }
  364. /**
  365. * hal_tx_desc_set_hlos_tid() - Set the TID value (override DSCP/PCP fields in
  366. * frame) to be used for Tx Frame
  367. * @desc: Handle to Tx Descriptor
  368. * @hlos_tid: HLOS TID
  369. *
  370. * Return: void
  371. */
  372. static inline void hal_tx_desc_set_hlos_tid(void *desc,
  373. uint8_t hlos_tid)
  374. {
  375. HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |=
  376. HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid);
  377. HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |=
  378. HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1);
  379. }
  380. /**
  381. * hal_tx_desc_sync() - Commit the descriptor to Hardware
  382. * @hal_tx_desc_cached: Cached descriptor that software maintains
  383. * @hw_desc: Hardware descriptor to be updated
  384. * @num_bytes: descriptor size
  385. */
  386. static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
  387. void *hw_desc, uint8_t num_bytes)
  388. {
  389. qdf_mem_copy(hw_desc, hal_tx_desc_cached, num_bytes);
  390. }
  391. /**
  392. * hal_tx_desc_set_vdev_id() - set vdev id to the descriptor to Hardware
  393. * @desc: Cached descriptor that software maintains
  394. * @vdev_id: vdev id
  395. */
  396. static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id)
  397. {
  398. HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |=
  399. HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id);
  400. }
  401. /**
  402. * hal_tx_desc_set_bank_id() - set bank id to the descriptor to Hardware
  403. * @desc: Cached descriptor that software maintains
  404. * @bank_id: bank id
  405. */
  406. static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id)
  407. {
  408. HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |=
  409. HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id);
  410. }
  411. /**
  412. * hal_tx_desc_set_tcl_cmd_type() - set tcl command type to the descriptor
  413. * to Hardware
  414. * @desc: Cached descriptor that software maintains
  415. * @tcl_cmd_type: tcl command type
  416. */
  417. static inline void
  418. hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
  419. {
  420. HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |=
  421. HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type);
  422. }
  423. /**
  424. * hal_tx_desc_set_lmac_id_be() - set lmac id to the descriptor to Hardware
  425. * @hal_soc_hdl: hal soc handle
  426. * @desc: Cached descriptor that software maintains
  427. * @lmac_id: lmac id
  428. */
  429. static inline void
  430. hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  431. uint8_t lmac_id)
  432. {
  433. HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |=
  434. HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id);
  435. }
  436. /**
  437. * hal_tx_desc_set_search_index_be() - set search index to the
  438. * descriptor to Hardware
  439. * @hal_soc_hdl: hal soc handle
  440. * @desc: Cached descriptor that software maintains
  441. * @search_index: search index
  442. */
  443. static inline void
  444. hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  445. uint32_t search_index)
  446. {
  447. HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |=
  448. HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index);
  449. }
  450. /**
  451. * hal_tx_desc_set_cache_set_num() - set cache set num to the
  452. * descriptor to Hardware
  453. * @hal_soc_hdl: hal soc handle
  454. * @desc: Cached descriptor that software maintains
  455. * @cache_num: cache number
  456. */
  457. static inline void
  458. hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc,
  459. uint8_t cache_num)
  460. {
  461. HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |=
  462. HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num);
  463. }
  464. /**
  465. * hal_tx_desc_set_index_lookup_override() - set lookup override num to the
  466. * descriptor to Hardware
  467. * @hal_soc_hdl: hal soc handle
  468. * @desc: Cached descriptor that software maintains
  469. * @num: set number
  470. */
  471. static inline void
  472. hal_tx_desc_set_index_lookup_override(hal_soc_handle_t hal_soc_hdl,
  473. void *desc, uint8_t num)
  474. {
  475. HAL_SET_FLD(desc, TCL_DATA_CMD, INDEX_LOOKUP_OVERRIDE) |=
  476. HAL_TX_SM(TCL_DATA_CMD, INDEX_LOOKUP_OVERRIDE, num);
  477. }
  478. /*---------------------------------------------------------------------------
  479. * WBM Descriptor accessor APIs for Tx completions
  480. * ---------------------------------------------------------------------------
  481. */
  482. /**
  483. * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring
  484. *
  485. * Return: BM ID for first tx completion ring
  486. */
  487. static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void)
  488. {
  489. return HAL_BE_WBM_SW0_BM_ID;
  490. }
  491. /**
  492. * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
  493. * @hal_desc: completion ring descriptor pointer
  494. *
  495. * This function will tx descriptor id, cookie, within hardware completion
  496. * descriptor. For cases when cookie conversion is disabled, the sw_cookie
  497. * is present in the 2nd DWORD.
  498. *
  499. * Return: cookie
  500. */
  501. static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
  502. {
  503. uint32_t comp_desc =
  504. *(uint32_t *)(((uint8_t *)hal_desc) +
  505. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET);
  506. /* Cookie is placed on 2nd word */
  507. return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >>
  508. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  509. }
  510. /**
  511. * hal_tx_comp_get_paddr() - Get paddr within comp descriptor
  512. * @hal_desc: completion ring descriptor pointer
  513. *
  514. * This function will get buffer physical address within hardware completion
  515. * descriptor
  516. *
  517. * Return: Buffer physical address
  518. */
  519. static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
  520. {
  521. uint32_t paddr_lo;
  522. uint32_t paddr_hi;
  523. paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) +
  524. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET);
  525. paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) +
  526. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET);
  527. paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >>
  528. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB;
  529. return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32));
  530. }
  531. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  532. /* HW set dowrd-2 bit30 to 1 if HW CC is done */
  533. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8
  534. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000
  535. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E
  536. /**
  537. * hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag
  538. * @hal_desc: completion ring descriptor pointer
  539. *
  540. * This function will get the bit value that indicate HW cookie
  541. * conversion done or not
  542. *
  543. * Return: 1 - HW cookie conversion done, 0 - not
  544. */
  545. static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc)
  546. {
  547. return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX,
  548. CC_DONE);
  549. }
  550. #endif
  551. /**
  552. * hal_tx_comp_set_desc_va_63_32() - Set bit 32~63 value for 64 bit VA
  553. * @hal_desc: completion ring descriptor pointer
  554. * @val: value to be set
  555. *
  556. * Return: None
  557. */
  558. static inline void hal_tx_comp_set_desc_va_63_32(void *hal_desc, uint32_t val)
  559. {
  560. HAL_SET_FLD(hal_desc,
  561. WBM2SW_COMPLETION_RING_TX,
  562. BUFFER_VIRT_ADDR_63_32) = val;
  563. }
  564. /**
  565. * hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc
  566. * @hal_desc: completion ring descriptor pointer
  567. *
  568. * This function will get the TX Desc virtual address
  569. *
  570. * Return: TX desc virtual address
  571. */
  572. static inline uint64_t hal_tx_comp_get_desc_va(void *hal_desc)
  573. {
  574. uint64_t va_from_desc;
  575. va_from_desc = qdf_le64_to_cpu(HAL_TX_DESC_GET(hal_desc,
  576. WBM2SW_COMPLETION_RING_TX,
  577. BUFFER_VIRT_ADDR_31_0) |
  578. (((uint64_t)HAL_TX_DESC_GET(
  579. hal_desc,
  580. WBM2SW_COMPLETION_RING_TX,
  581. BUFFER_VIRT_ADDR_63_32)) << 32));
  582. return va_from_desc;
  583. }
  584. /*---------------------------------------------------------------------------
  585. * TX BANK register accessor APIs
  586. * ---------------------------------------------------------------------------
  587. */
  588. /**
  589. * hal_tx_get_num_tcl_banks() - Get number of banks for target
  590. * @hal_soc_hdl: HAL soc handle
  591. *
  592. * Return: None
  593. */
  594. static inline uint8_t
  595. hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl)
  596. {
  597. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  598. int hal_banks = 0;
  599. if (hal_soc->ops->hal_tx_get_num_tcl_banks) {
  600. hal_banks = hal_soc->ops->hal_tx_get_num_tcl_banks();
  601. hal_banks -= HAL_TX_NUM_RESERVED_BANKS;
  602. hal_banks = (hal_banks < 0) ? 0 : hal_banks;
  603. }
  604. return hal_banks;
  605. }
  606. /**
  607. * hal_tx_populate_bank_register() - populate the bank register with
  608. * the software configs.
  609. * @hal_soc_hdl: HAL soc handle
  610. * @config: bank config
  611. * @bank_id: bank id to be configured
  612. *
  613. * Returns: None
  614. */
  615. static inline void
  616. hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
  617. union hal_tx_bank_config *config,
  618. uint8_t bank_id)
  619. {
  620. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  621. hal_soc->ops->hal_tx_populate_bank_register(hal_soc_hdl, config,
  622. bank_id);
  623. }
  624. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  625. #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
  626. #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
  627. #define RBM_PPE2TCL_OFFSET \
  628. (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2)
  629. #define RBM_TCL_CMD_CREDIT_OFFSET \
  630. (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
  631. /**
  632. * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id
  633. * @hal_soc_hdl: HAL SoC context
  634. * @hal_ring_hdl: Source ring pointer
  635. * @rbm_id: return buffer manager ring id
  636. *
  637. * Return: void
  638. */
  639. static inline void
  640. hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl,
  641. hal_ring_handle_t hal_ring_hdl,
  642. uint8_t rbm_id)
  643. {
  644. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  645. hal_soc->ops->hal_tx_config_rbm_mapping_be(hal_soc_hdl, hal_ring_hdl,
  646. rbm_id);
  647. }
  648. #else
  649. static inline void
  650. hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl,
  651. hal_ring_handle_t hal_ring_hdl,
  652. uint8_t rbm_id)
  653. {
  654. }
  655. #endif
  656. /**
  657. * hal_tx_desc_set_buf_addr_be() - Fill Buffer Address information in Tx Desc
  658. * @hal_soc_hdl: HAL SoC context
  659. * @desc: Handle to Tx Descriptor
  660. * @paddr: Physical Address
  661. * @rbm_id: Return Buffer Manager ID
  662. * @desc_id: Descriptor ID
  663. * @type: 0 - Address points to a MSDU buffer
  664. * 1 - Address points to MSDU extension descriptor
  665. *
  666. * Return: void
  667. */
  668. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  669. static inline void
  670. hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  671. dma_addr_t paddr, uint8_t rbm_id,
  672. uint32_t desc_id, uint8_t type)
  673. {
  674. /* Set buffer_addr_info.buffer_addr_31_0 */
  675. HAL_SET_FLD(desc, TCL_DATA_CMD,
  676. BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
  677. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
  678. /* Set buffer_addr_info.buffer_addr_39_32 */
  679. HAL_SET_FLD(desc, TCL_DATA_CMD,
  680. BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
  681. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
  682. (((uint64_t)paddr) >> 32));
  683. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  684. HAL_SET_FLD(desc, TCL_DATA_CMD,
  685. BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
  686. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
  687. desc_id);
  688. /* Set Buffer or Ext Descriptor Type */
  689. HAL_SET_FLD(desc, TCL_DATA_CMD,
  690. BUF_OR_EXT_DESC_TYPE) |=
  691. HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
  692. }
  693. #else
  694. static inline void
  695. hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
  696. dma_addr_t paddr, uint8_t rbm_id,
  697. uint32_t desc_id, uint8_t type)
  698. {
  699. /* Set buffer_addr_info.buffer_addr_31_0 */
  700. HAL_SET_FLD(desc, TCL_DATA_CMD,
  701. BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
  702. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
  703. /* Set buffer_addr_info.buffer_addr_39_32 */
  704. HAL_SET_FLD(desc, TCL_DATA_CMD,
  705. BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
  706. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
  707. (((uint64_t)paddr) >> 32));
  708. /* Set buffer_addr_info.return_buffer_manager = rbm id */
  709. HAL_SET_FLD(desc, TCL_DATA_CMD,
  710. BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |=
  711. HAL_TX_SM(TCL_DATA_CMD,
  712. BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id);
  713. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  714. HAL_SET_FLD(desc, TCL_DATA_CMD,
  715. BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
  716. HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
  717. desc_id);
  718. /* Set Buffer or Ext Descriptor Type */
  719. HAL_SET_FLD(desc, TCL_DATA_CMD,
  720. BUF_OR_EXT_DESC_TYPE) |=
  721. HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
  722. }
  723. #endif
  724. /**
  725. * hal_tx_vdev_mismatch_routing_set() - set vdev mismatch exception routing
  726. * @hal_soc_hdl: HAL SoC context
  727. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  728. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  729. *
  730. * Return: void
  731. */
  732. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  733. static inline void
  734. hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl,
  735. enum hal_tx_vdev_mismatch_notify config)
  736. {
  737. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  738. hal_soc->ops->hal_tx_vdev_mismatch_routing_set(hal_soc_hdl, config);
  739. }
  740. #else
  741. static inline void
  742. hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl,
  743. enum hal_tx_vdev_mismatch_notify config)
  744. {
  745. }
  746. #endif
  747. /**
  748. * hal_tx_mcast_mlo_reinject_routing_set() - set MLO multicast reinject routing
  749. * @hal_soc_hdl: HAL SoC context
  750. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  751. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  752. *
  753. * Return: void
  754. */
  755. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  756. defined(WLAN_MCAST_MLO) && !defined(CONFIG_MLO_SINGLE_DEV)
  757. static inline void
  758. hal_tx_mcast_mlo_reinject_routing_set(
  759. hal_soc_handle_t hal_soc_hdl,
  760. enum hal_tx_mcast_mlo_reinject_notify config)
  761. {
  762. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  763. hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set(hal_soc_hdl,
  764. config);
  765. }
  766. #else
  767. static inline void
  768. hal_tx_mcast_mlo_reinject_routing_set(
  769. hal_soc_handle_t hal_soc_hdl,
  770. enum hal_tx_mcast_mlo_reinject_notify config)
  771. {
  772. }
  773. #endif
  774. /**
  775. * hal_reo_config_reo2ppe_dest_info() - Configure reo2ppe dest info
  776. * @hal_soc_hdl: HAL SoC Context
  777. *
  778. * Return: None.
  779. */
  780. static inline
  781. void hal_reo_config_reo2ppe_dest_info(hal_soc_handle_t hal_soc_hdl)
  782. {
  783. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  784. if (hal_soc->ops->hal_reo_config_reo2ppe_dest_info)
  785. hal_soc->ops->hal_reo_config_reo2ppe_dest_info(hal_soc_hdl);
  786. }
  787. /**
  788. * hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table entries
  789. * @hal_soc_hdl: HAL SoC Context
  790. *
  791. * Return: Total number of entries.
  792. */
  793. static inline
  794. uint32_t hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_handle_t hal_soc_hdl)
  795. {
  796. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  797. return hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_hdl);
  798. }
  799. /**
  800. * hal_tx_get_num_ppe_vp_search_idx_tbl_entries() - Get the total number of
  801. * search idx registers
  802. * @hal_soc_hdl: HAL SoC Context
  803. *
  804. * Return: Total number of entries.
  805. */
  806. static inline
  807. uint32_t hal_tx_get_num_ppe_vp_search_idx_tbl_entries(hal_soc_handle_t hal_soc_hdl)
  808. {
  809. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  810. return hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries(hal_soc_hdl);
  811. }
  812. /**
  813. * hal_tx_set_ppe_cmn_cfg()- Set the PPE common config
  814. * @hal_soc_hdl: HAL SoC context
  815. * @cmn_cfg: HAL PPE VP common config
  816. *
  817. * Return: void
  818. */
  819. static inline void
  820. hal_tx_set_ppe_cmn_cfg(hal_soc_handle_t hal_soc_hdl,
  821. union hal_tx_cmn_config_ppe *cmn_cfg)
  822. {
  823. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  824. hal_soc->ops->hal_tx_set_ppe_cmn_cfg(hal_soc_hdl, cmn_cfg);
  825. }
  826. /**
  827. * hal_tx_populate_ppe_vp_entry() - Populate ppe VP entry
  828. * @hal_soc_hdl: HAL SoC context
  829. * @vp_cfg: HAL PPE VP config
  830. * @ppe_vp_idx: PPE VP index
  831. *
  832. * Return: void
  833. */
  834. static inline void
  835. hal_tx_populate_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl,
  836. union hal_tx_ppe_vp_config *vp_cfg,
  837. int ppe_vp_idx)
  838. {
  839. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  840. hal_soc->ops->hal_tx_set_ppe_vp_entry(hal_soc_hdl, vp_cfg, ppe_vp_idx);
  841. }
  842. /**
  843. * hal_ppeds_cfg_ast_override_map_reg() - Set ppe index mapping table value
  844. * @hal_soc_hdl: HAL SoC context
  845. * @reg_idx: index into the table
  846. * @overide_map: HAL PPE INDEX MAPPING config
  847. *
  848. * Return: void
  849. */
  850. static inline void
  851. hal_ppeds_cfg_ast_override_map_reg(hal_soc_handle_t hal_soc_hdl,
  852. uint8_t reg_idx, union hal_tx_ppe_idx_map_config *overide_map)
  853. {
  854. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  855. if (hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg)
  856. hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg(hal_soc_hdl,
  857. reg_idx,
  858. overide_map);
  859. }
  860. /**
  861. * hal_tx_set_int_pri2tid() - Set the pri2tid table.
  862. * @hal_soc_hdl: HAL SoC context
  863. * @val: value to set
  864. * @map_no: index in SW INT_PRI to TID table
  865. *
  866. * Return: void
  867. */
  868. static inline void
  869. hal_tx_set_int_pri2tid(hal_soc_handle_t hal_soc_hdl,
  870. uint32_t val, uint8_t map_no)
  871. {
  872. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  873. hal_soc->ops->hal_tx_set_ppe_pri2tid(hal_soc_hdl, val, map_no);
  874. }
  875. /**
  876. * hal_tx_update_int_pri2tid() - Populate the pri2tid table.
  877. * @hal_soc_hdl: HAL SoC context
  878. * @pri: INT_PRI value
  879. * @tid: Wi-Fi TID
  880. *
  881. * Return: void
  882. */
  883. static inline void
  884. hal_tx_update_int_pri2tid(hal_soc_handle_t hal_soc_hdl,
  885. uint8_t pri, uint8_t tid)
  886. {
  887. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  888. hal_soc->ops->hal_tx_update_ppe_pri2tid(hal_soc_hdl, pri, tid);
  889. }
  890. /**
  891. * hal_tx_dump_ppe_vp_entry() - Dump the PPE VP entry
  892. * @hal_soc_hdl: HAL SoC context
  893. *
  894. * Return: void
  895. */
  896. static inline void
  897. hal_tx_dump_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl)
  898. {
  899. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  900. hal_soc->ops->hal_tx_dump_ppe_vp_entry(hal_soc_hdl);
  901. }
  902. /**
  903. * hal_tx_enable_pri2tid_map() - Enable the priority to tid mapping
  904. * @hal_soc_hdl: HAL SoC context
  905. * @val: True/False value
  906. * @ppe_vp_idx: map index
  907. *
  908. * Return: void
  909. */
  910. static inline void
  911. hal_tx_enable_pri2tid_map(hal_soc_handle_t hal_soc_hdl, bool val,
  912. uint8_t ppe_vp_idx)
  913. {
  914. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  915. hal_soc->ops->hal_tx_enable_pri2tid_map(hal_soc_hdl, val,
  916. ppe_vp_idx);
  917. }
  918. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  919. static inline void
  920. hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
  921. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  922. {
  923. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  924. hal_soc->ops->hal_tx_vdev_mcast_ctrl_set(hal_soc_hdl, vdev_id,
  925. mcast_ctrl_val);
  926. }
  927. #else
  928. static inline void
  929. hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
  930. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  931. {
  932. }
  933. #endif
  934. #endif /* _HAL_BE_TX_H_ */