cam_mem_mgr.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  13. #include <linux/mem-buf.h>
  14. #include <soc/qcom/secure_buffer.h>
  15. #endif
  16. #include "cam_compat.h"
  17. #include "cam_req_mgr_util.h"
  18. #include "cam_mem_mgr.h"
  19. #include "cam_smmu_api.h"
  20. #include "cam_debug_util.h"
  21. #include "cam_trace.h"
  22. #include "cam_common_util.h"
  23. #define CAM_MEM_SHARED_BUFFER_PAD_4K (4 * 1024)
  24. static struct cam_mem_table tbl;
  25. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  26. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  27. static void cam_mem_mgr_put_dma_heaps(void);
  28. static int cam_mem_mgr_get_dma_heaps(void);
  29. #endif
  30. static void cam_mem_mgr_print_tbl(void)
  31. {
  32. int i;
  33. uint64_t ms, tmp, hrs, min, sec;
  34. struct timespec64 *ts = NULL;
  35. struct timespec64 current_ts;
  36. ktime_get_real_ts64(&(current_ts));
  37. tmp = current_ts.tv_sec;
  38. ms = (current_ts.tv_nsec) / 1000000;
  39. sec = do_div(tmp, 60);
  40. min = do_div(tmp, 60);
  41. hrs = do_div(tmp, 24);
  42. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  43. hrs, min, sec, ms);
  44. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  45. if (tbl.bufq[i].active) {
  46. ts = &tbl.bufq[i].timestamp;
  47. tmp = ts->tv_sec;
  48. ms = (ts->tv_nsec) / 1000000;
  49. sec = do_div(tmp, 60);
  50. min = do_div(tmp, 60);
  51. hrs = do_div(tmp, 24);
  52. CAM_INFO(CAM_MEM,
  53. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  54. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  55. tbl.bufq[i].len);
  56. }
  57. }
  58. }
  59. static int cam_mem_util_get_dma_dir(uint32_t flags)
  60. {
  61. int rc = -EINVAL;
  62. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  63. rc = DMA_TO_DEVICE;
  64. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  65. rc = DMA_FROM_DEVICE;
  66. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  67. rc = DMA_BIDIRECTIONAL;
  68. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  69. rc = DMA_BIDIRECTIONAL;
  70. return rc;
  71. }
  72. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  73. uintptr_t *vaddr,
  74. size_t *len)
  75. {
  76. int rc = 0;
  77. void *addr;
  78. /*
  79. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  80. * need to be called in pair to avoid stability issue.
  81. */
  82. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  83. if (rc) {
  84. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  85. return rc;
  86. }
  87. addr = dma_buf_vmap(dmabuf);
  88. if (!addr) {
  89. CAM_ERR(CAM_MEM, "kernel map fail");
  90. *vaddr = 0;
  91. *len = 0;
  92. rc = -ENOSPC;
  93. goto fail;
  94. }
  95. *vaddr = (uint64_t)addr;
  96. *len = dmabuf->size;
  97. return 0;
  98. fail:
  99. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  100. return rc;
  101. }
  102. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  103. uint64_t vaddr)
  104. {
  105. int rc = 0;
  106. if (!dmabuf || !vaddr) {
  107. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  108. return -EINVAL;
  109. }
  110. dma_buf_vunmap(dmabuf, (void *)vaddr);
  111. /*
  112. * dma_buf_begin_cpu_access() and
  113. * dma_buf_end_cpu_access() need to be called in pair
  114. * to avoid stability issue.
  115. */
  116. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  117. if (rc) {
  118. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  119. dmabuf);
  120. return rc;
  121. }
  122. return rc;
  123. }
  124. static int cam_mem_mgr_create_debug_fs(void)
  125. {
  126. int rc = 0;
  127. struct dentry *dbgfileptr = NULL;
  128. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  129. if (!dbgfileptr) {
  130. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  131. rc = -ENOENT;
  132. goto end;
  133. }
  134. /* Store parent inode for cleanup in caller */
  135. tbl.dentry = dbgfileptr;
  136. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  137. tbl.dentry, &tbl.alloc_profile_enable);
  138. if (IS_ERR(dbgfileptr)) {
  139. if (PTR_ERR(dbgfileptr) == -ENODEV)
  140. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  141. else
  142. rc = PTR_ERR(dbgfileptr);
  143. }
  144. end:
  145. return rc;
  146. }
  147. int cam_mem_mgr_init(void)
  148. {
  149. int i;
  150. int bitmap_size;
  151. int rc = 0;
  152. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  153. if (cam_smmu_need_force_alloc_cached(&tbl.force_cache_allocs)) {
  154. CAM_ERR(CAM_MEM, "Error in getting force cache alloc flag");
  155. return -EINVAL;
  156. }
  157. tbl.need_shared_buffer_padding = cam_smmu_need_shared_buffer_padding();
  158. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  159. rc = cam_mem_mgr_get_dma_heaps();
  160. if (rc) {
  161. CAM_ERR(CAM_MEM, "Failed in getting dma heaps rc=%d", rc);
  162. return rc;
  163. }
  164. #endif
  165. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  166. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  167. if (!tbl.bitmap) {
  168. rc = -ENOMEM;
  169. goto put_heaps;
  170. }
  171. tbl.bits = bitmap_size * BITS_PER_BYTE;
  172. bitmap_zero(tbl.bitmap, tbl.bits);
  173. /* We need to reserve slot 0 because 0 is invalid */
  174. set_bit(0, tbl.bitmap);
  175. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  176. tbl.bufq[i].fd = -1;
  177. tbl.bufq[i].buf_handle = -1;
  178. }
  179. mutex_init(&tbl.m_lock);
  180. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  181. cam_mem_mgr_create_debug_fs();
  182. return 0;
  183. put_heaps:
  184. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  185. cam_mem_mgr_put_dma_heaps();
  186. #endif
  187. return rc;
  188. }
  189. static int32_t cam_mem_get_slot(void)
  190. {
  191. int32_t idx;
  192. mutex_lock(&tbl.m_lock);
  193. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  194. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  195. mutex_unlock(&tbl.m_lock);
  196. return -ENOMEM;
  197. }
  198. set_bit(idx, tbl.bitmap);
  199. tbl.bufq[idx].active = true;
  200. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  201. mutex_init(&tbl.bufq[idx].q_lock);
  202. mutex_unlock(&tbl.m_lock);
  203. return idx;
  204. }
  205. static void cam_mem_put_slot(int32_t idx)
  206. {
  207. mutex_lock(&tbl.m_lock);
  208. mutex_lock(&tbl.bufq[idx].q_lock);
  209. tbl.bufq[idx].active = false;
  210. tbl.bufq[idx].is_internal = false;
  211. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  212. mutex_unlock(&tbl.bufq[idx].q_lock);
  213. mutex_destroy(&tbl.bufq[idx].q_lock);
  214. clear_bit(idx, tbl.bitmap);
  215. mutex_unlock(&tbl.m_lock);
  216. }
  217. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  218. dma_addr_t *iova_ptr, size_t *len_ptr, uint32_t *flags)
  219. {
  220. int rc = 0, idx;
  221. *len_ptr = 0;
  222. if (!atomic_read(&cam_mem_mgr_state)) {
  223. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  224. return -EINVAL;
  225. }
  226. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  227. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  228. return -ENOENT;
  229. if (!tbl.bufq[idx].active) {
  230. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  231. idx);
  232. return -EAGAIN;
  233. }
  234. mutex_lock(&tbl.bufq[idx].q_lock);
  235. if (buf_handle != tbl.bufq[idx].buf_handle) {
  236. rc = -EINVAL;
  237. goto handle_mismatch;
  238. }
  239. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  240. rc = cam_smmu_get_stage2_iova(mmu_handle, tbl.bufq[idx].fd,
  241. iova_ptr, len_ptr);
  242. else
  243. rc = cam_smmu_get_iova(mmu_handle, tbl.bufq[idx].fd,
  244. iova_ptr, len_ptr);
  245. if (rc) {
  246. CAM_ERR(CAM_MEM,
  247. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  248. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  249. goto handle_mismatch;
  250. }
  251. if (flags)
  252. *flags = tbl.bufq[idx].flags;
  253. CAM_DBG(CAM_MEM,
  254. "handle:0x%x fd:%d iova_ptr:0x%llx len_ptr:%llu",
  255. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  256. handle_mismatch:
  257. mutex_unlock(&tbl.bufq[idx].q_lock);
  258. return rc;
  259. }
  260. EXPORT_SYMBOL(cam_mem_get_io_buf);
  261. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  262. {
  263. int idx;
  264. if (!atomic_read(&cam_mem_mgr_state)) {
  265. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  266. return -EINVAL;
  267. }
  268. if (!buf_handle || !vaddr_ptr || !len)
  269. return -EINVAL;
  270. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  271. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  272. return -EINVAL;
  273. if (!tbl.bufq[idx].active) {
  274. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  275. idx);
  276. return -EPERM;
  277. }
  278. if (buf_handle != tbl.bufq[idx].buf_handle)
  279. return -EINVAL;
  280. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  281. return -EINVAL;
  282. if (tbl.bufq[idx].kmdvaddr) {
  283. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  284. *len = tbl.bufq[idx].len;
  285. } else {
  286. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  287. buf_handle);
  288. return -EINVAL;
  289. }
  290. return 0;
  291. }
  292. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  293. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  294. {
  295. int rc = 0, idx;
  296. uint32_t cache_dir;
  297. unsigned long dmabuf_flag = 0;
  298. if (!atomic_read(&cam_mem_mgr_state)) {
  299. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  300. return -EINVAL;
  301. }
  302. if (!cmd)
  303. return -EINVAL;
  304. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  305. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  306. return -EINVAL;
  307. mutex_lock(&tbl.bufq[idx].q_lock);
  308. if (!tbl.bufq[idx].active) {
  309. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  310. idx);
  311. rc = -EINVAL;
  312. goto end;
  313. }
  314. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  315. rc = -EINVAL;
  316. goto end;
  317. }
  318. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  319. if (rc) {
  320. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  321. goto end;
  322. }
  323. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  324. CAM_DBG(CAM_MEM, "Calling dmap buf APIs for cache operations");
  325. cache_dir = DMA_BIDIRECTIONAL;
  326. #else
  327. if (dmabuf_flag & ION_FLAG_CACHED) {
  328. switch (cmd->mem_cache_ops) {
  329. case CAM_MEM_CLEAN_CACHE:
  330. cache_dir = DMA_TO_DEVICE;
  331. break;
  332. case CAM_MEM_INV_CACHE:
  333. cache_dir = DMA_FROM_DEVICE;
  334. break;
  335. case CAM_MEM_CLEAN_INV_CACHE:
  336. cache_dir = DMA_BIDIRECTIONAL;
  337. break;
  338. default:
  339. CAM_ERR(CAM_MEM,
  340. "invalid cache ops :%d", cmd->mem_cache_ops);
  341. rc = -EINVAL;
  342. goto end;
  343. }
  344. } else {
  345. CAM_DBG(CAM_MEM, "BUF is not cached");
  346. goto end;
  347. }
  348. #endif
  349. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  350. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  351. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  352. if (rc) {
  353. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  354. goto end;
  355. }
  356. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  357. cache_dir);
  358. if (rc) {
  359. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  360. goto end;
  361. }
  362. end:
  363. mutex_unlock(&tbl.bufq[idx].q_lock);
  364. return rc;
  365. }
  366. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  367. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  368. #define CAM_MAX_VMIDS 4
  369. static void cam_mem_mgr_put_dma_heaps(void)
  370. {
  371. CAM_DBG(CAM_MEM, "Releasing DMA Buf heaps usage");
  372. }
  373. static int cam_mem_mgr_get_dma_heaps(void)
  374. {
  375. int rc = 0;
  376. tbl.system_heap = NULL;
  377. tbl.system_uncached_heap = NULL;
  378. tbl.camera_heap = NULL;
  379. tbl.camera_uncached_heap = NULL;
  380. tbl.secure_display_heap = NULL;
  381. tbl.system_heap = dma_heap_find("qcom,system");
  382. if (IS_ERR_OR_NULL(tbl.system_heap)) {
  383. rc = PTR_ERR(tbl.system_heap);
  384. CAM_ERR(CAM_MEM, "qcom system heap not found, rc=%d", rc);
  385. tbl.system_heap = NULL;
  386. goto put_heaps;
  387. }
  388. tbl.system_uncached_heap = dma_heap_find("qcom,system-uncached");
  389. if (IS_ERR_OR_NULL(tbl.system_uncached_heap)) {
  390. if (tbl.force_cache_allocs) {
  391. /* optional, we anyway do not use uncached */
  392. CAM_DBG(CAM_MEM,
  393. "qcom system-uncached heap not found, err=%d",
  394. PTR_ERR(tbl.system_uncached_heap));
  395. tbl.system_uncached_heap = NULL;
  396. } else {
  397. /* fatal, must need uncached heaps */
  398. rc = PTR_ERR(tbl.system_uncached_heap);
  399. CAM_ERR(CAM_MEM,
  400. "qcom system-uncached heap not found, rc=%d",
  401. rc);
  402. tbl.system_uncached_heap = NULL;
  403. goto put_heaps;
  404. }
  405. }
  406. tbl.secure_display_heap = dma_heap_find("qcom,display");
  407. if (IS_ERR_OR_NULL(tbl.secure_display_heap)) {
  408. rc = PTR_ERR(tbl.secure_display_heap);
  409. CAM_ERR(CAM_MEM, "qcom,display heap not found, rc=%d",
  410. rc);
  411. tbl.secure_display_heap = NULL;
  412. goto put_heaps;
  413. }
  414. tbl.camera_heap = dma_heap_find("qcom,camera");
  415. if (IS_ERR_OR_NULL(tbl.camera_heap)) {
  416. /* optional heap, not a fatal error */
  417. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  418. PTR_ERR(tbl.camera_heap));
  419. tbl.camera_heap = NULL;
  420. }
  421. tbl.camera_uncached_heap = dma_heap_find("qcom,camera-uncached");
  422. if (IS_ERR_OR_NULL(tbl.camera_uncached_heap)) {
  423. /* optional heap, not a fatal error */
  424. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  425. PTR_ERR(tbl.camera_uncached_heap));
  426. tbl.camera_uncached_heap = NULL;
  427. }
  428. CAM_INFO(CAM_MEM,
  429. "Heaps : system=%pK, system_uncached=%pK, camera=%pK, camera-uncached=%pK, secure_display=%pK",
  430. tbl.system_heap, tbl.system_uncached_heap,
  431. tbl.camera_heap, tbl.camera_uncached_heap,
  432. tbl.secure_display_heap);
  433. return 0;
  434. put_heaps:
  435. cam_mem_mgr_put_dma_heaps();
  436. return rc;
  437. }
  438. static int cam_mem_util_get_dma_buf(size_t len,
  439. unsigned int cam_flags,
  440. struct dma_buf **buf)
  441. {
  442. int rc = 0;
  443. struct dma_heap *heap;
  444. struct dma_heap *try_heap = NULL;
  445. struct timespec64 ts1, ts2;
  446. long microsec = 0;
  447. bool use_cached_heap = false;
  448. struct mem_buf_lend_kernel_arg arg;
  449. int vmids[CAM_MAX_VMIDS];
  450. int perms[CAM_MAX_VMIDS];
  451. int num_vmids = 0;
  452. if (!buf) {
  453. CAM_ERR(CAM_MEM, "Invalid params");
  454. return -EINVAL;
  455. }
  456. if (tbl.alloc_profile_enable)
  457. CAM_GET_TIMESTAMP(ts1);
  458. if ((cam_flags & CAM_MEM_FLAG_CACHE) ||
  459. (tbl.force_cache_allocs &&
  460. (!(cam_flags & CAM_MEM_FLAG_PROTECTED_MODE)))) {
  461. CAM_DBG(CAM_MEM,
  462. "Using CACHED heap, cam_flags=0x%x, force_cache_allocs=%d",
  463. cam_flags, tbl.force_cache_allocs);
  464. use_cached_heap = true;
  465. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  466. use_cached_heap = true;
  467. CAM_DBG(CAM_MEM,
  468. "Using CACHED heap for secure, cam_flags=0x%x, force_cache_allocs=%d",
  469. cam_flags, tbl.force_cache_allocs);
  470. } else {
  471. use_cached_heap = false;
  472. CAM_ERR(CAM_MEM,
  473. "Using UNCACHED heap not supported, cam_flags=0x%x, force_cache_allocs=%d",
  474. cam_flags, tbl.force_cache_allocs);
  475. /*
  476. * Need a better handling based on whether dma-buf-heaps support
  477. * uncached heaps or not. For now, assume not supported.
  478. */
  479. return -EINVAL;
  480. }
  481. if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  482. heap = tbl.secure_display_heap;
  483. vmids[num_vmids] = VMID_CP_CAMERA;
  484. perms[num_vmids] = PERM_READ | PERM_WRITE;
  485. num_vmids++;
  486. if (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT) {
  487. CAM_DBG(CAM_MEM, "Secure mode CDSP flags");
  488. vmids[num_vmids] = VMID_CP_CDSP;
  489. perms[num_vmids] = PERM_READ | PERM_WRITE;
  490. num_vmids++;
  491. }
  492. } else if (cam_flags & CAM_MEM_FLAG_EVA_NOPIXEL) {
  493. heap = tbl.secure_display_heap;
  494. vmids[num_vmids] = VMID_CP_NON_PIXEL;
  495. perms[num_vmids] = PERM_READ | PERM_WRITE;
  496. num_vmids++;
  497. } else if (use_cached_heap) {
  498. try_heap = tbl.camera_heap;
  499. heap = tbl.system_heap;
  500. } else {
  501. try_heap = tbl.camera_uncached_heap;
  502. heap = tbl.system_uncached_heap;
  503. }
  504. CAM_DBG(CAM_MEM, "Using heaps : try=%pK, heap=%pK", try_heap, heap);
  505. *buf = NULL;
  506. if (!try_heap && !heap) {
  507. CAM_ERR(CAM_MEM,
  508. "No heap available for allocation, cant allocate");
  509. return -EINVAL;
  510. }
  511. if (try_heap) {
  512. *buf = dma_heap_buffer_alloc(try_heap, len, O_RDWR, 0);
  513. if (IS_ERR(*buf)) {
  514. CAM_WARN(CAM_MEM,
  515. "Failed in allocating from try heap, heap=%pK, len=%zu, err=%d",
  516. try_heap, len, PTR_ERR(*buf));
  517. *buf = NULL;
  518. }
  519. }
  520. if (*buf == NULL) {
  521. *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0);
  522. if (IS_ERR(*buf)) {
  523. rc = PTR_ERR(*buf);
  524. CAM_ERR(CAM_MEM,
  525. "Failed in allocating from heap, heap=%pK, len=%zu, err=%d",
  526. heap, len, rc);
  527. *buf = NULL;
  528. return rc;
  529. }
  530. }
  531. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) ||
  532. (cam_flags & CAM_MEM_FLAG_EVA_NOPIXEL)) {
  533. if (num_vmids >= CAM_MAX_VMIDS) {
  534. CAM_ERR(CAM_MEM, "Insufficient array size for vmids %d", num_vmids);
  535. rc = -EINVAL;
  536. goto end;
  537. }
  538. arg.nr_acl_entries = num_vmids;
  539. arg.vmids = vmids;
  540. arg.perms = perms;
  541. rc = mem_buf_lend(*buf, &arg);
  542. if (rc) {
  543. CAM_ERR(CAM_MEM,
  544. "Failed in buf lend rc=%d, buf=%pK, vmids [0]=0x%x, [1]=0x%x, [2]=0x%x",
  545. rc, *buf, vmids[0], vmids[1], vmids[2]);
  546. goto end;
  547. }
  548. }
  549. CAM_DBG(CAM_MEM, "Allocate success, len=%zu, *buf=%pK", len, *buf);
  550. if (tbl.alloc_profile_enable) {
  551. CAM_GET_TIMESTAMP(ts2);
  552. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  553. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  554. len, microsec);
  555. }
  556. return rc;
  557. end:
  558. dma_buf_put(*buf);
  559. return rc;
  560. }
  561. #else
  562. static int cam_mem_util_get_dma_buf(size_t len,
  563. unsigned int cam_flags,
  564. struct dma_buf **buf)
  565. {
  566. int rc = 0;
  567. unsigned int heap_id;
  568. int32_t ion_flag = 0;
  569. struct timespec64 ts1, ts2;
  570. long microsec = 0;
  571. if (!buf) {
  572. CAM_ERR(CAM_MEM, "Invalid params");
  573. return -EINVAL;
  574. }
  575. if (tbl.alloc_profile_enable)
  576. CAM_GET_TIMESTAMP(ts1);
  577. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  578. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  579. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  580. ion_flag |=
  581. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  582. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  583. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  584. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  585. } else {
  586. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  587. ION_HEAP(ION_CAMERA_HEAP_ID);
  588. }
  589. if (cam_flags & CAM_MEM_FLAG_CACHE)
  590. ion_flag |= ION_FLAG_CACHED;
  591. else
  592. ion_flag &= ~ION_FLAG_CACHED;
  593. if (tbl.force_cache_allocs && (!(ion_flag & ION_FLAG_SECURE)))
  594. ion_flag |= ION_FLAG_CACHED;
  595. *buf = ion_alloc(len, heap_id, ion_flag);
  596. if (IS_ERR_OR_NULL(*buf))
  597. return -ENOMEM;
  598. if (tbl.alloc_profile_enable) {
  599. CAM_GET_TIMESTAMP(ts2);
  600. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  601. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  602. len, microsec);
  603. }
  604. return rc;
  605. }
  606. #endif
  607. static int cam_mem_util_buffer_alloc(size_t len, uint32_t flags,
  608. struct dma_buf **dmabuf,
  609. int *fd)
  610. {
  611. int rc;
  612. struct dma_buf *temp_dmabuf = NULL;
  613. rc = cam_mem_util_get_dma_buf(len, flags, dmabuf);
  614. if (rc) {
  615. CAM_ERR(CAM_MEM,
  616. "Error allocating dma buf : len=%llu, flags=0x%x",
  617. len, flags);
  618. return rc;
  619. }
  620. *fd = dma_buf_fd(*dmabuf, O_CLOEXEC);
  621. if (*fd < 0) {
  622. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  623. rc = -EINVAL;
  624. goto put_buf;
  625. }
  626. CAM_DBG(CAM_MEM, "Alloc success : len=%zu, *dmabuf=%pK, fd=%d",
  627. len, *dmabuf, *fd);
  628. /*
  629. * increment the ref count so that ref count becomes 2 here
  630. * when we close fd, refcount becomes 1 and when we do
  631. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  632. */
  633. temp_dmabuf = dma_buf_get(*fd);
  634. if (IS_ERR_OR_NULL(temp_dmabuf)) {
  635. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  636. rc = -EINVAL;
  637. goto put_buf;
  638. }
  639. return rc;
  640. put_buf:
  641. dma_buf_put(*dmabuf);
  642. return rc;
  643. }
  644. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  645. {
  646. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  647. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  648. CAM_MEM_MMU_MAX_HANDLE);
  649. return -EINVAL;
  650. }
  651. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  652. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  653. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  654. return -EINVAL;
  655. }
  656. if ((cmd->flags & CAM_MEM_FLAG_EVA_NOPIXEL) &&
  657. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE ||
  658. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS)){
  659. CAM_ERR(CAM_MEM,
  660. "Kernel mapping and secure mode not allowed in no pixel mode");
  661. return -EINVAL;
  662. }
  663. return 0;
  664. }
  665. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  666. {
  667. if (!cmd->flags) {
  668. CAM_ERR(CAM_MEM, "Invalid flags");
  669. return -EINVAL;
  670. }
  671. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  672. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  673. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  674. return -EINVAL;
  675. }
  676. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  677. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  678. CAM_ERR(CAM_MEM,
  679. "Kernel mapping in secure mode not allowed, flags=0x%x",
  680. cmd->flags);
  681. return -EINVAL;
  682. }
  683. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  684. CAM_ERR(CAM_MEM,
  685. "Shared memory buffers are not allowed to be mapped");
  686. return -EINVAL;
  687. }
  688. return 0;
  689. }
  690. static int cam_mem_util_map_hw_va(uint32_t flags,
  691. int32_t *mmu_hdls,
  692. int32_t num_hdls,
  693. int fd,
  694. dma_addr_t *hw_vaddr,
  695. size_t *len,
  696. enum cam_smmu_region_id region,
  697. bool is_internal)
  698. {
  699. int i;
  700. int rc = -1;
  701. int dir = cam_mem_util_get_dma_dir(flags);
  702. bool dis_delayed_unmap = false;
  703. if (dir < 0) {
  704. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  705. return dir;
  706. }
  707. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  708. dis_delayed_unmap = true;
  709. CAM_DBG(CAM_MEM,
  710. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  711. fd, flags, dir, num_hdls);
  712. for (i = 0; i < num_hdls; i++) {
  713. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  714. rc = cam_smmu_map_stage2_iova(mmu_hdls[i], fd, dir, hw_vaddr, len);
  715. else
  716. rc = cam_smmu_map_user_iova(mmu_hdls[i], fd, dis_delayed_unmap, dir,
  717. hw_vaddr, len, region, is_internal);
  718. if (rc) {
  719. CAM_ERR(CAM_MEM,
  720. "Failed %s map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  721. (flags & CAM_MEM_FLAG_PROTECTED_MODE) ? "" : "secured",
  722. i, fd, dir, mmu_hdls[i], rc);
  723. goto multi_map_fail;
  724. }
  725. }
  726. return rc;
  727. multi_map_fail:
  728. for (--i; i>= 0; i--) {
  729. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  730. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  731. else
  732. cam_smmu_unmap_user_iova(mmu_hdls[i], fd, CAM_SMMU_REGION_IO);
  733. }
  734. return rc;
  735. }
  736. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  737. {
  738. int rc;
  739. int32_t idx;
  740. struct dma_buf *dmabuf = NULL;
  741. int fd = -1;
  742. dma_addr_t hw_vaddr = 0;
  743. size_t len;
  744. uintptr_t kvaddr = 0;
  745. size_t klen;
  746. if (!atomic_read(&cam_mem_mgr_state)) {
  747. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  748. return -EINVAL;
  749. }
  750. if (!cmd) {
  751. CAM_ERR(CAM_MEM, " Invalid argument");
  752. return -EINVAL;
  753. }
  754. len = cmd->len;
  755. if (tbl.need_shared_buffer_padding &&
  756. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)) {
  757. len += CAM_MEM_SHARED_BUFFER_PAD_4K;
  758. CAM_DBG(CAM_MEM, "Pad 4k size, actual %llu, allocating %zu",
  759. cmd->len, len);
  760. }
  761. rc = cam_mem_util_check_alloc_flags(cmd);
  762. if (rc) {
  763. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  764. cmd->flags, rc);
  765. return rc;
  766. }
  767. rc = cam_mem_util_buffer_alloc(len, cmd->flags, &dmabuf, &fd);
  768. if (rc) {
  769. CAM_ERR(CAM_MEM,
  770. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  771. len, cmd->align, cmd->flags, cmd->num_hdl);
  772. cam_mem_mgr_print_tbl();
  773. return rc;
  774. }
  775. if (!dmabuf) {
  776. CAM_ERR(CAM_MEM,
  777. "Ion Alloc return NULL dmabuf! fd=%d, len=%d", fd, len);
  778. cam_mem_mgr_print_tbl();
  779. return rc;
  780. }
  781. idx = cam_mem_get_slot();
  782. if (idx < 0) {
  783. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  784. rc = -ENOMEM;
  785. goto slot_fail;
  786. }
  787. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  788. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  789. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  790. enum cam_smmu_region_id region;
  791. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  792. region = CAM_SMMU_REGION_IO;
  793. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  794. (cam_smmu_is_expanded_memory() && cmd->flags & CAM_MEM_FLAG_CMD_BUF_TYPE))
  795. region = CAM_SMMU_REGION_SHARED;
  796. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  797. region = CAM_SMMU_REGION_IO;
  798. rc = cam_mem_util_map_hw_va(cmd->flags,
  799. cmd->mmu_hdls,
  800. cmd->num_hdl,
  801. fd,
  802. &hw_vaddr,
  803. &len,
  804. region,
  805. true);
  806. if (rc) {
  807. CAM_ERR(CAM_MEM,
  808. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  809. len, cmd->flags,
  810. fd, region, cmd->num_hdl, rc);
  811. if (rc == -EALREADY) {
  812. if ((size_t)dmabuf->size != len)
  813. rc = -EBADR;
  814. cam_mem_mgr_print_tbl();
  815. }
  816. goto map_hw_fail;
  817. }
  818. }
  819. mutex_lock(&tbl.bufq[idx].q_lock);
  820. tbl.bufq[idx].fd = fd;
  821. tbl.bufq[idx].dma_buf = NULL;
  822. tbl.bufq[idx].flags = cmd->flags;
  823. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  824. tbl.bufq[idx].is_internal = true;
  825. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  826. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  827. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  828. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  829. if (rc) {
  830. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  831. dmabuf, rc);
  832. goto map_kernel_fail;
  833. }
  834. }
  835. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  836. tbl.dbg_buf_idx = idx;
  837. tbl.bufq[idx].kmdvaddr = kvaddr;
  838. tbl.bufq[idx].vaddr = hw_vaddr;
  839. tbl.bufq[idx].dma_buf = dmabuf;
  840. tbl.bufq[idx].len = len;
  841. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  842. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  843. sizeof(int32_t) * cmd->num_hdl);
  844. tbl.bufq[idx].is_imported = false;
  845. mutex_unlock(&tbl.bufq[idx].q_lock);
  846. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  847. cmd->out.fd = tbl.bufq[idx].fd;
  848. cmd->out.vaddr = 0;
  849. CAM_DBG(CAM_MEM,
  850. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  851. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  852. tbl.bufq[idx].len);
  853. return rc;
  854. map_kernel_fail:
  855. mutex_unlock(&tbl.bufq[idx].q_lock);
  856. map_hw_fail:
  857. cam_mem_put_slot(idx);
  858. slot_fail:
  859. dma_buf_put(dmabuf);
  860. return rc;
  861. }
  862. static bool cam_mem_util_is_map_internal(int32_t fd)
  863. {
  864. uint32_t i;
  865. bool is_internal = false;
  866. mutex_lock(&tbl.m_lock);
  867. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  868. if (tbl.bufq[i].fd == fd) {
  869. is_internal = tbl.bufq[i].is_internal;
  870. break;
  871. }
  872. }
  873. mutex_unlock(&tbl.m_lock);
  874. return is_internal;
  875. }
  876. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  877. {
  878. int32_t idx;
  879. int rc;
  880. struct dma_buf *dmabuf;
  881. dma_addr_t hw_vaddr = 0;
  882. size_t len = 0;
  883. bool is_internal = false;
  884. if (!atomic_read(&cam_mem_mgr_state)) {
  885. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  886. return -EINVAL;
  887. }
  888. if (!cmd || (cmd->fd < 0)) {
  889. CAM_ERR(CAM_MEM, "Invalid argument");
  890. return -EINVAL;
  891. }
  892. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  893. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  894. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  895. return -EINVAL;
  896. }
  897. rc = cam_mem_util_check_map_flags(cmd);
  898. if (rc) {
  899. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  900. return rc;
  901. }
  902. dmabuf = dma_buf_get(cmd->fd);
  903. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  904. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  905. return -EINVAL;
  906. }
  907. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  908. idx = cam_mem_get_slot();
  909. if (idx < 0) {
  910. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  911. idx, cmd->fd);
  912. rc = -ENOMEM;
  913. goto slot_fail;
  914. }
  915. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  916. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  917. rc = cam_mem_util_map_hw_va(cmd->flags,
  918. cmd->mmu_hdls,
  919. cmd->num_hdl,
  920. cmd->fd,
  921. &hw_vaddr,
  922. &len,
  923. CAM_SMMU_REGION_IO,
  924. is_internal);
  925. if (rc) {
  926. CAM_ERR(CAM_MEM,
  927. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  928. cmd->flags, cmd->fd, len,
  929. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  930. if (rc == -EALREADY) {
  931. if ((size_t)dmabuf->size != len) {
  932. rc = -EBADR;
  933. cam_mem_mgr_print_tbl();
  934. }
  935. }
  936. goto map_fail;
  937. }
  938. }
  939. mutex_lock(&tbl.bufq[idx].q_lock);
  940. tbl.bufq[idx].fd = cmd->fd;
  941. tbl.bufq[idx].dma_buf = NULL;
  942. tbl.bufq[idx].flags = cmd->flags;
  943. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  944. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  945. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  946. tbl.bufq[idx].kmdvaddr = 0;
  947. if (cmd->num_hdl > 0)
  948. tbl.bufq[idx].vaddr = hw_vaddr;
  949. else
  950. tbl.bufq[idx].vaddr = 0;
  951. tbl.bufq[idx].dma_buf = dmabuf;
  952. tbl.bufq[idx].len = len;
  953. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  954. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  955. sizeof(int32_t) * cmd->num_hdl);
  956. tbl.bufq[idx].is_imported = true;
  957. tbl.bufq[idx].is_internal = is_internal;
  958. mutex_unlock(&tbl.bufq[idx].q_lock);
  959. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  960. cmd->out.vaddr = 0;
  961. cmd->out.size = (uint32_t)len;
  962. CAM_DBG(CAM_MEM,
  963. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  964. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  965. tbl.bufq[idx].len);
  966. return rc;
  967. map_fail:
  968. cam_mem_put_slot(idx);
  969. slot_fail:
  970. dma_buf_put(dmabuf);
  971. return rc;
  972. }
  973. static int cam_mem_util_unmap_hw_va(int32_t idx,
  974. enum cam_smmu_region_id region,
  975. enum cam_smmu_mapping_client client)
  976. {
  977. int i;
  978. uint32_t flags;
  979. int32_t *mmu_hdls;
  980. int num_hdls;
  981. int fd;
  982. int rc = 0;
  983. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  984. CAM_ERR(CAM_MEM, "Incorrect index");
  985. return -EINVAL;
  986. }
  987. flags = tbl.bufq[idx].flags;
  988. mmu_hdls = tbl.bufq[idx].hdls;
  989. num_hdls = tbl.bufq[idx].num_hdl;
  990. fd = tbl.bufq[idx].fd;
  991. CAM_DBG(CAM_MEM,
  992. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  993. idx, fd, flags, num_hdls, client);
  994. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  995. for (i = 0; i < num_hdls; i++) {
  996. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  997. if (rc < 0) {
  998. CAM_ERR(CAM_MEM,
  999. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  1000. i, fd, mmu_hdls[i], rc);
  1001. goto unmap_end;
  1002. }
  1003. }
  1004. } else {
  1005. for (i = 0; i < num_hdls; i++) {
  1006. if (client == CAM_SMMU_MAPPING_USER) {
  1007. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  1008. fd, region);
  1009. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  1010. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  1011. tbl.bufq[idx].dma_buf, region);
  1012. } else {
  1013. CAM_ERR(CAM_MEM,
  1014. "invalid caller for unmapping : %d",
  1015. client);
  1016. rc = -EINVAL;
  1017. }
  1018. if (rc < 0) {
  1019. CAM_ERR(CAM_MEM,
  1020. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  1021. i, fd, mmu_hdls[i], region, rc);
  1022. goto unmap_end;
  1023. }
  1024. }
  1025. }
  1026. return rc;
  1027. unmap_end:
  1028. CAM_ERR(CAM_MEM, "unmapping failed");
  1029. return rc;
  1030. }
  1031. static void cam_mem_mgr_unmap_active_buf(int idx)
  1032. {
  1033. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1034. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  1035. region = CAM_SMMU_REGION_SHARED;
  1036. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1037. region = CAM_SMMU_REGION_IO;
  1038. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  1039. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  1040. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1041. tbl.bufq[idx].kmdvaddr);
  1042. }
  1043. static int cam_mem_mgr_cleanup_table(void)
  1044. {
  1045. int i;
  1046. mutex_lock(&tbl.m_lock);
  1047. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  1048. if (!tbl.bufq[i].active) {
  1049. CAM_DBG(CAM_MEM,
  1050. "Buffer inactive at idx=%d, continuing", i);
  1051. continue;
  1052. } else {
  1053. CAM_DBG(CAM_MEM,
  1054. "Active buffer at idx=%d, possible leak needs unmapping",
  1055. i);
  1056. cam_mem_mgr_unmap_active_buf(i);
  1057. }
  1058. mutex_lock(&tbl.bufq[i].q_lock);
  1059. if (tbl.bufq[i].dma_buf) {
  1060. dma_buf_put(tbl.bufq[i].dma_buf);
  1061. tbl.bufq[i].dma_buf = NULL;
  1062. }
  1063. tbl.bufq[i].fd = -1;
  1064. tbl.bufq[i].flags = 0;
  1065. tbl.bufq[i].buf_handle = -1;
  1066. tbl.bufq[i].vaddr = 0;
  1067. tbl.bufq[i].len = 0;
  1068. memset(tbl.bufq[i].hdls, 0,
  1069. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  1070. tbl.bufq[i].num_hdl = 0;
  1071. tbl.bufq[i].dma_buf = NULL;
  1072. tbl.bufq[i].active = false;
  1073. tbl.bufq[i].is_internal = false;
  1074. mutex_unlock(&tbl.bufq[i].q_lock);
  1075. mutex_destroy(&tbl.bufq[i].q_lock);
  1076. }
  1077. bitmap_zero(tbl.bitmap, tbl.bits);
  1078. /* We need to reserve slot 0 because 0 is invalid */
  1079. set_bit(0, tbl.bitmap);
  1080. mutex_unlock(&tbl.m_lock);
  1081. return 0;
  1082. }
  1083. void cam_mem_mgr_deinit(void)
  1084. {
  1085. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  1086. cam_mem_mgr_cleanup_table();
  1087. debugfs_remove_recursive(tbl.dentry);
  1088. mutex_lock(&tbl.m_lock);
  1089. bitmap_zero(tbl.bitmap, tbl.bits);
  1090. kfree(tbl.bitmap);
  1091. tbl.bitmap = NULL;
  1092. tbl.dbg_buf_idx = -1;
  1093. mutex_unlock(&tbl.m_lock);
  1094. mutex_destroy(&tbl.m_lock);
  1095. }
  1096. static int cam_mem_util_unmap(int32_t idx,
  1097. enum cam_smmu_mapping_client client)
  1098. {
  1099. int rc = 0;
  1100. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1101. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1102. CAM_ERR(CAM_MEM, "Incorrect index");
  1103. return -EINVAL;
  1104. }
  1105. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  1106. mutex_lock(&tbl.m_lock);
  1107. if ((!tbl.bufq[idx].active) &&
  1108. (tbl.bufq[idx].vaddr) == 0) {
  1109. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  1110. idx);
  1111. mutex_unlock(&tbl.m_lock);
  1112. return 0;
  1113. }
  1114. /* Deactivate the buffer queue to prevent multiple unmap */
  1115. mutex_lock(&tbl.bufq[idx].q_lock);
  1116. tbl.bufq[idx].active = false;
  1117. tbl.bufq[idx].vaddr = 0;
  1118. mutex_unlock(&tbl.bufq[idx].q_lock);
  1119. mutex_unlock(&tbl.m_lock);
  1120. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1121. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  1122. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1123. tbl.bufq[idx].kmdvaddr);
  1124. if (rc)
  1125. CAM_ERR(CAM_MEM,
  1126. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  1127. tbl.bufq[idx].dma_buf,
  1128. (void *) tbl.bufq[idx].kmdvaddr);
  1129. }
  1130. }
  1131. /* SHARED flag gets precedence, all other flags after it */
  1132. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1133. region = CAM_SMMU_REGION_SHARED;
  1134. } else {
  1135. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1136. region = CAM_SMMU_REGION_IO;
  1137. }
  1138. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  1139. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  1140. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  1141. if (cam_mem_util_unmap_hw_va(idx, region, client))
  1142. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  1143. tbl.bufq[idx].dma_buf);
  1144. if (client == CAM_SMMU_MAPPING_KERNEL)
  1145. tbl.bufq[idx].dma_buf = NULL;
  1146. }
  1147. mutex_lock(&tbl.m_lock);
  1148. mutex_lock(&tbl.bufq[idx].q_lock);
  1149. tbl.bufq[idx].flags = 0;
  1150. tbl.bufq[idx].buf_handle = -1;
  1151. memset(tbl.bufq[idx].hdls, 0,
  1152. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  1153. CAM_DBG(CAM_MEM,
  1154. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  1155. idx, tbl.bufq[idx].fd,
  1156. tbl.bufq[idx].is_imported,
  1157. tbl.bufq[idx].dma_buf);
  1158. if (tbl.bufq[idx].dma_buf)
  1159. dma_buf_put(tbl.bufq[idx].dma_buf);
  1160. tbl.bufq[idx].fd = -1;
  1161. tbl.bufq[idx].dma_buf = NULL;
  1162. tbl.bufq[idx].is_imported = false;
  1163. tbl.bufq[idx].is_internal = false;
  1164. tbl.bufq[idx].len = 0;
  1165. tbl.bufq[idx].num_hdl = 0;
  1166. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  1167. mutex_unlock(&tbl.bufq[idx].q_lock);
  1168. mutex_destroy(&tbl.bufq[idx].q_lock);
  1169. clear_bit(idx, tbl.bitmap);
  1170. mutex_unlock(&tbl.m_lock);
  1171. return rc;
  1172. }
  1173. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  1174. {
  1175. int idx;
  1176. int rc;
  1177. if (!atomic_read(&cam_mem_mgr_state)) {
  1178. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1179. return -EINVAL;
  1180. }
  1181. if (!cmd) {
  1182. CAM_ERR(CAM_MEM, "Invalid argument");
  1183. return -EINVAL;
  1184. }
  1185. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  1186. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1187. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  1188. idx);
  1189. return -EINVAL;
  1190. }
  1191. if (!tbl.bufq[idx].active) {
  1192. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1193. return -EINVAL;
  1194. }
  1195. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  1196. CAM_ERR(CAM_MEM,
  1197. "Released buf handle %d not matching within table %d, idx=%d",
  1198. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  1199. return -EINVAL;
  1200. }
  1201. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  1202. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  1203. return rc;
  1204. }
  1205. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  1206. struct cam_mem_mgr_memory_desc *out)
  1207. {
  1208. struct dma_buf *buf = NULL;
  1209. int ion_fd = -1;
  1210. int rc = 0;
  1211. uintptr_t kvaddr;
  1212. dma_addr_t iova = 0;
  1213. size_t request_len = 0;
  1214. uint32_t mem_handle;
  1215. int32_t idx;
  1216. int32_t smmu_hdl = 0;
  1217. int32_t num_hdl = 0;
  1218. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1219. if (!atomic_read(&cam_mem_mgr_state)) {
  1220. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1221. return -EINVAL;
  1222. }
  1223. if (!inp || !out) {
  1224. CAM_ERR(CAM_MEM, "Invalid params");
  1225. return -EINVAL;
  1226. }
  1227. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1228. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1229. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1230. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1231. return -EINVAL;
  1232. }
  1233. rc = cam_mem_util_get_dma_buf(inp->size, inp->flags, &buf);
  1234. if (rc) {
  1235. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1236. goto ion_fail;
  1237. } else if (!buf) {
  1238. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1239. goto ion_fail;
  1240. } else {
  1241. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1242. }
  1243. /*
  1244. * we are mapping kva always here,
  1245. * update flags so that we do unmap properly
  1246. */
  1247. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1248. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1249. if (rc) {
  1250. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1251. goto map_fail;
  1252. }
  1253. if (!inp->smmu_hdl) {
  1254. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1255. rc = -EINVAL;
  1256. goto smmu_fail;
  1257. }
  1258. /* SHARED flag gets precedence, all other flags after it */
  1259. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1260. region = CAM_SMMU_REGION_SHARED;
  1261. } else {
  1262. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1263. region = CAM_SMMU_REGION_IO;
  1264. }
  1265. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1266. buf,
  1267. CAM_SMMU_MAP_RW,
  1268. &iova,
  1269. &request_len,
  1270. region);
  1271. if (rc < 0) {
  1272. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1273. goto smmu_fail;
  1274. }
  1275. smmu_hdl = inp->smmu_hdl;
  1276. num_hdl = 1;
  1277. idx = cam_mem_get_slot();
  1278. if (idx < 0) {
  1279. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1280. rc = -ENOMEM;
  1281. goto slot_fail;
  1282. }
  1283. mutex_lock(&tbl.bufq[idx].q_lock);
  1284. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1285. tbl.bufq[idx].dma_buf = buf;
  1286. tbl.bufq[idx].fd = -1;
  1287. tbl.bufq[idx].flags = inp->flags;
  1288. tbl.bufq[idx].buf_handle = mem_handle;
  1289. tbl.bufq[idx].kmdvaddr = kvaddr;
  1290. tbl.bufq[idx].vaddr = iova;
  1291. tbl.bufq[idx].len = inp->size;
  1292. tbl.bufq[idx].num_hdl = num_hdl;
  1293. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1294. sizeof(int32_t));
  1295. tbl.bufq[idx].is_imported = false;
  1296. mutex_unlock(&tbl.bufq[idx].q_lock);
  1297. out->kva = kvaddr;
  1298. out->iova = (uint32_t)iova;
  1299. out->smmu_hdl = smmu_hdl;
  1300. out->mem_handle = mem_handle;
  1301. out->len = inp->size;
  1302. out->region = region;
  1303. return rc;
  1304. slot_fail:
  1305. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1306. buf, region);
  1307. smmu_fail:
  1308. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1309. map_fail:
  1310. dma_buf_put(buf);
  1311. ion_fail:
  1312. return rc;
  1313. }
  1314. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1315. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1316. {
  1317. int32_t idx;
  1318. int rc;
  1319. if (!atomic_read(&cam_mem_mgr_state)) {
  1320. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1321. return -EINVAL;
  1322. }
  1323. if (!inp) {
  1324. CAM_ERR(CAM_MEM, "Invalid argument");
  1325. return -EINVAL;
  1326. }
  1327. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1328. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1329. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1330. return -EINVAL;
  1331. }
  1332. if (!tbl.bufq[idx].active) {
  1333. if (tbl.bufq[idx].vaddr == 0) {
  1334. CAM_ERR(CAM_MEM, "buffer is released already");
  1335. return 0;
  1336. }
  1337. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1338. return -EINVAL;
  1339. }
  1340. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1341. CAM_ERR(CAM_MEM,
  1342. "Released buf handle not matching within table");
  1343. return -EINVAL;
  1344. }
  1345. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1346. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1347. return rc;
  1348. }
  1349. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1350. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1351. enum cam_smmu_region_id region,
  1352. struct cam_mem_mgr_memory_desc *out)
  1353. {
  1354. struct dma_buf *buf = NULL;
  1355. int rc = 0;
  1356. int ion_fd = -1;
  1357. dma_addr_t iova = 0;
  1358. size_t request_len = 0;
  1359. uint32_t mem_handle;
  1360. int32_t idx;
  1361. int32_t smmu_hdl = 0;
  1362. int32_t num_hdl = 0;
  1363. uintptr_t kvaddr = 0;
  1364. if (!atomic_read(&cam_mem_mgr_state)) {
  1365. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1366. return -EINVAL;
  1367. }
  1368. if (!inp || !out) {
  1369. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1370. return -EINVAL;
  1371. }
  1372. if (!inp->smmu_hdl) {
  1373. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1374. return -EINVAL;
  1375. }
  1376. if ((region != CAM_SMMU_REGION_SECHEAP) &&
  1377. (region != CAM_SMMU_REGION_FWUNCACHED)) {
  1378. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1379. return -EINVAL;
  1380. }
  1381. rc = cam_mem_util_get_dma_buf(inp->size, 0, &buf);
  1382. if (rc) {
  1383. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1384. goto ion_fail;
  1385. } else if (!buf) {
  1386. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1387. goto ion_fail;
  1388. } else {
  1389. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1390. }
  1391. if (inp->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1392. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1393. if (rc) {
  1394. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1395. goto kmap_fail;
  1396. }
  1397. }
  1398. rc = cam_smmu_reserve_buf_region(region,
  1399. inp->smmu_hdl, buf, &iova, &request_len);
  1400. if (rc) {
  1401. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1402. goto smmu_fail;
  1403. }
  1404. smmu_hdl = inp->smmu_hdl;
  1405. num_hdl = 1;
  1406. idx = cam_mem_get_slot();
  1407. if (idx < 0) {
  1408. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1409. rc = -ENOMEM;
  1410. goto slot_fail;
  1411. }
  1412. mutex_lock(&tbl.bufq[idx].q_lock);
  1413. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1414. tbl.bufq[idx].fd = -1;
  1415. tbl.bufq[idx].dma_buf = buf;
  1416. tbl.bufq[idx].flags = inp->flags;
  1417. tbl.bufq[idx].buf_handle = mem_handle;
  1418. tbl.bufq[idx].kmdvaddr = kvaddr;
  1419. tbl.bufq[idx].vaddr = iova;
  1420. tbl.bufq[idx].len = request_len;
  1421. tbl.bufq[idx].num_hdl = num_hdl;
  1422. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1423. sizeof(int32_t));
  1424. tbl.bufq[idx].is_imported = false;
  1425. mutex_unlock(&tbl.bufq[idx].q_lock);
  1426. out->kva = kvaddr;
  1427. out->iova = (uint32_t)iova;
  1428. out->smmu_hdl = smmu_hdl;
  1429. out->mem_handle = mem_handle;
  1430. out->len = request_len;
  1431. out->region = region;
  1432. return rc;
  1433. slot_fail:
  1434. cam_smmu_release_buf_region(region, smmu_hdl);
  1435. smmu_fail:
  1436. if (region == CAM_SMMU_REGION_FWUNCACHED)
  1437. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1438. kmap_fail:
  1439. dma_buf_put(buf);
  1440. ion_fail:
  1441. return rc;
  1442. }
  1443. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1444. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1445. {
  1446. int32_t idx;
  1447. int rc;
  1448. int32_t smmu_hdl;
  1449. if (!atomic_read(&cam_mem_mgr_state)) {
  1450. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1451. return -EINVAL;
  1452. }
  1453. if (!inp) {
  1454. CAM_ERR(CAM_MEM, "Invalid argument");
  1455. return -EINVAL;
  1456. }
  1457. if ((inp->region != CAM_SMMU_REGION_SECHEAP) &&
  1458. (inp->region != CAM_SMMU_REGION_FWUNCACHED)) {
  1459. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1460. return -EINVAL;
  1461. }
  1462. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1463. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1464. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1465. return -EINVAL;
  1466. }
  1467. if (!tbl.bufq[idx].active) {
  1468. if (tbl.bufq[idx].vaddr == 0) {
  1469. CAM_ERR(CAM_MEM, "buffer is released already");
  1470. return 0;
  1471. }
  1472. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1473. return -EINVAL;
  1474. }
  1475. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1476. CAM_ERR(CAM_MEM,
  1477. "Released buf handle not matching within table");
  1478. return -EINVAL;
  1479. }
  1480. if (tbl.bufq[idx].num_hdl != 1) {
  1481. CAM_ERR(CAM_MEM,
  1482. "Sec heap region should have only one smmu hdl");
  1483. return -ENODEV;
  1484. }
  1485. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1486. sizeof(int32_t));
  1487. if (inp->smmu_hdl != smmu_hdl) {
  1488. CAM_ERR(CAM_MEM,
  1489. "Passed SMMU handle doesn't match with internal hdl");
  1490. return -ENODEV;
  1491. }
  1492. rc = cam_smmu_release_buf_region(inp->region, inp->smmu_hdl);
  1493. if (rc) {
  1494. CAM_ERR(CAM_MEM,
  1495. "Sec heap region release failed");
  1496. return -ENODEV;
  1497. }
  1498. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1499. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1500. if (rc)
  1501. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1502. return rc;
  1503. }
  1504. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);
  1505. #ifndef CONFIG_CAM_PRESIL
  1506. struct dma_buf * cam_mem_mgr_get_dma_buf(int fd)
  1507. {
  1508. return NULL;
  1509. }
  1510. int cam_mem_mgr_send_all_buffers_to_presil(int32_t iommu_hdl)
  1511. {
  1512. return 0;
  1513. }
  1514. int cam_mem_mgr_send_buffer_to_presil(int32_t iommu_hdl, int32_t buf_handle)
  1515. {
  1516. return 0;
  1517. }
  1518. int cam_mem_mgr_retrieve_buffer_from_presil(int32_t buf_handle,
  1519. uint32_t buf_size,
  1520. uint32_t offset,
  1521. int32_t iommu_hdl)
  1522. {
  1523. return 0;
  1524. }
  1525. #endif