dp_tx.c 101 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791
  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_tx.h"
  21. #include "dp_tx_desc.h"
  22. #include "dp_peer.h"
  23. #include "dp_types.h"
  24. #include "hal_tx.h"
  25. #include "qdf_mem.h"
  26. #include "qdf_nbuf.h"
  27. #include "qdf_net_types.h"
  28. #include <wlan_cfg.h>
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #define DP_TX_QUEUE_MASK 0x3
  33. /* TODO Add support in TSO */
  34. #define DP_DESC_NUM_FRAG(x) 0
  35. /* disable TQM_BYPASS */
  36. #define TQM_BYPASS_WAR 0
  37. /* invalid peer id for reinject*/
  38. #define DP_INVALID_PEER 0XFFFE
  39. /*mapping between hal encrypt type and cdp_sec_type*/
  40. #define MAX_CDP_SEC_TYPE 12
  41. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  42. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  43. HAL_TX_ENCRYPT_TYPE_WEP_128,
  44. HAL_TX_ENCRYPT_TYPE_WEP_104,
  45. HAL_TX_ENCRYPT_TYPE_WEP_40,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  47. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  48. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  49. HAL_TX_ENCRYPT_TYPE_WAPI,
  50. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  52. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  53. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  54. /**
  55. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  56. * @vdev: DP Virtual device handle
  57. * @nbuf: Buffer pointer
  58. * @queue: queue ids container for nbuf
  59. *
  60. * TX packet queue has 2 instances, software descriptors id and dma ring id
  61. * Based on tx feature and hardware configuration queue id combination could be
  62. * different.
  63. * For example -
  64. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  65. * With no XPS,lock based resource protection, Descriptor pool ids are different
  66. * for each vdev, dma ring id will be same as single pdev id
  67. *
  68. * Return: None
  69. */
  70. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  71. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  72. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  73. {
  74. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  75. queue->desc_pool_id = queue_offset;
  76. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  77. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  78. "%s, pool_id:%d ring_id: %d",
  79. __func__, queue->desc_pool_id, queue->ring_id);
  80. return;
  81. }
  82. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  83. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  84. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  85. {
  86. /* get flow id */
  87. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  88. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  89. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  90. "%s, pool_id:%d ring_id: %d",
  91. __func__, queue->desc_pool_id, queue->ring_id);
  92. return;
  93. }
  94. #endif
  95. #if defined(FEATURE_TSO)
  96. /**
  97. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  98. *
  99. * @soc - core txrx main context
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  106. if (qdf_unlikely(!tx_desc->tso_desc)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO num desc is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. bool is_last_seg;
  118. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  119. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  120. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1)
  121. is_last_seg = false;
  122. else
  123. is_last_seg = true;
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_nbuf_unmap_tso_segment(soc->osdev,
  126. tx_desc->tso_desc, is_last_seg);
  127. }
  128. }
  129. /**
  130. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  131. * back to the freelist
  132. *
  133. * @soc - soc device handle
  134. * @tx_desc - Tx software descriptor
  135. */
  136. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  137. struct dp_tx_desc_s *tx_desc)
  138. {
  139. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  140. if (qdf_unlikely(!tx_desc->tso_desc)) {
  141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  142. "%s %d TSO desc is NULL!",
  143. __func__, __LINE__);
  144. qdf_assert(0);
  145. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  147. "%s %d TSO num desc is NULL!",
  148. __func__, __LINE__);
  149. qdf_assert(0);
  150. } else {
  151. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  152. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  153. /* Add the tso num segment into the free list */
  154. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  155. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  156. tx_desc->tso_num_desc);
  157. tx_desc->tso_num_desc = NULL;
  158. }
  159. /* Add the tso segment into the free list*/
  160. dp_tx_tso_desc_free(soc,
  161. tx_desc->pool_id, tx_desc->tso_desc);
  162. tx_desc->tso_desc = NULL;
  163. }
  164. }
  165. #else
  166. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  167. struct dp_tx_desc_s *tx_desc)
  168. {
  169. }
  170. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  171. struct dp_tx_desc_s *tx_desc)
  172. {
  173. }
  174. #endif
  175. /**
  176. * dp_tx_desc_release() - Release Tx Descriptor
  177. * @tx_desc : Tx Descriptor
  178. * @desc_pool_id: Descriptor Pool ID
  179. *
  180. * Deallocate all resources attached to Tx descriptor and free the Tx
  181. * descriptor.
  182. *
  183. * Return:
  184. */
  185. static void
  186. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  187. {
  188. struct dp_pdev *pdev = tx_desc->pdev;
  189. struct dp_soc *soc;
  190. uint8_t comp_status = 0;
  191. qdf_assert(pdev);
  192. soc = pdev->soc;
  193. if (tx_desc->frm_type == dp_tx_frm_tso)
  194. dp_tx_tso_desc_release(soc, tx_desc);
  195. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  196. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  197. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  198. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  199. qdf_atomic_dec(&pdev->num_tx_outstanding);
  200. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  201. qdf_atomic_dec(&pdev->num_tx_exception);
  202. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  203. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  204. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  205. soc->hal_soc);
  206. else
  207. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  208. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  209. "Tx Completion Release desc %d status %d outstanding %d",
  210. tx_desc->id, comp_status,
  211. qdf_atomic_read(&pdev->num_tx_outstanding));
  212. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  213. return;
  214. }
  215. /**
  216. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  217. * @vdev: DP vdev Handle
  218. * @nbuf: skb
  219. *
  220. * Prepares and fills HTT metadata in the frame pre-header for special frames
  221. * that should be transmitted using varying transmit parameters.
  222. * There are 2 VDEV modes that currently needs this special metadata -
  223. * 1) Mesh Mode
  224. * 2) DSRC Mode
  225. *
  226. * Return: HTT metadata size
  227. *
  228. */
  229. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  230. uint32_t *meta_data)
  231. {
  232. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  233. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  234. uint8_t htt_desc_size;
  235. /* Size rounded of multiple of 8 bytes */
  236. uint8_t htt_desc_size_aligned;
  237. uint8_t *hdr = NULL;
  238. /*
  239. * Metadata - HTT MSDU Extension header
  240. */
  241. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  242. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  243. if (vdev->mesh_vdev) {
  244. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  245. htt_desc_size_aligned)) {
  246. DP_STATS_INC(vdev,
  247. tx_i.dropped.headroom_insufficient, 1);
  248. return 0;
  249. }
  250. /* Fill and add HTT metaheader */
  251. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  252. if (hdr == NULL) {
  253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  254. "Error in filling HTT metadata");
  255. return 0;
  256. }
  257. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  258. } else if (vdev->opmode == wlan_op_mode_ocb) {
  259. /* Todo - Add support for DSRC */
  260. }
  261. return htt_desc_size_aligned;
  262. }
  263. /**
  264. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  265. * @tso_seg: TSO segment to process
  266. * @ext_desc: Pointer to MSDU extension descriptor
  267. *
  268. * Return: void
  269. */
  270. #if defined(FEATURE_TSO)
  271. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  272. void *ext_desc)
  273. {
  274. uint8_t num_frag;
  275. uint32_t tso_flags;
  276. /*
  277. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  278. * tcp_flag_mask
  279. *
  280. * Checksum enable flags are set in TCL descriptor and not in Extension
  281. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  282. */
  283. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  284. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  285. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  286. tso_seg->tso_flags.ip_len);
  287. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  288. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  289. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  290. uint32_t lo = 0;
  291. uint32_t hi = 0;
  292. qdf_dmaaddr_to_32s(
  293. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  294. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  295. tso_seg->tso_frags[num_frag].length);
  296. }
  297. return;
  298. }
  299. #else
  300. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  301. void *ext_desc)
  302. {
  303. return;
  304. }
  305. #endif
  306. #if defined(FEATURE_TSO)
  307. /**
  308. * dp_tx_free_tso_seg() - Loop through the tso segments
  309. * allocated and free them
  310. *
  311. * @soc: soc handle
  312. * @free_seg: list of tso segments
  313. * @msdu_info: msdu descriptor
  314. *
  315. * Return - void
  316. */
  317. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  318. struct qdf_tso_seg_elem_t *free_seg,
  319. struct dp_tx_msdu_info_s *msdu_info)
  320. {
  321. struct qdf_tso_seg_elem_t *next_seg;
  322. while (free_seg) {
  323. next_seg = free_seg->next;
  324. dp_tx_tso_desc_free(soc,
  325. msdu_info->tx_queue.desc_pool_id,
  326. free_seg);
  327. free_seg = next_seg;
  328. }
  329. }
  330. /**
  331. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  332. * allocated and free them
  333. *
  334. * @soc: soc handle
  335. * @free_seg: list of tso segments
  336. * @msdu_info: msdu descriptor
  337. * Return - void
  338. */
  339. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  340. struct qdf_tso_num_seg_elem_t *free_seg,
  341. struct dp_tx_msdu_info_s *msdu_info)
  342. {
  343. struct qdf_tso_num_seg_elem_t *next_seg;
  344. while (free_seg) {
  345. next_seg = free_seg->next;
  346. dp_tso_num_seg_free(soc,
  347. msdu_info->tx_queue.desc_pool_id,
  348. free_seg);
  349. free_seg = next_seg;
  350. }
  351. }
  352. /**
  353. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  354. * @vdev: virtual device handle
  355. * @msdu: network buffer
  356. * @msdu_info: meta data associated with the msdu
  357. *
  358. * Return: QDF_STATUS_SUCCESS success
  359. */
  360. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  361. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  362. {
  363. struct qdf_tso_seg_elem_t *tso_seg;
  364. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  365. struct dp_soc *soc = vdev->pdev->soc;
  366. struct qdf_tso_info_t *tso_info;
  367. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  368. tso_info = &msdu_info->u.tso_info;
  369. tso_info->curr_seg = NULL;
  370. tso_info->tso_seg_list = NULL;
  371. tso_info->num_segs = num_seg;
  372. msdu_info->frm_type = dp_tx_frm_tso;
  373. tso_info->tso_num_seg_list = NULL;
  374. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  375. while (num_seg) {
  376. tso_seg = dp_tx_tso_desc_alloc(
  377. soc, msdu_info->tx_queue.desc_pool_id);
  378. if (tso_seg) {
  379. tso_seg->next = tso_info->tso_seg_list;
  380. tso_info->tso_seg_list = tso_seg;
  381. num_seg--;
  382. } else {
  383. struct qdf_tso_seg_elem_t *free_seg =
  384. tso_info->tso_seg_list;
  385. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  386. return QDF_STATUS_E_NOMEM;
  387. }
  388. }
  389. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  390. tso_num_seg = dp_tso_num_seg_alloc(soc,
  391. msdu_info->tx_queue.desc_pool_id);
  392. if (tso_num_seg) {
  393. tso_num_seg->next = tso_info->tso_num_seg_list;
  394. tso_info->tso_num_seg_list = tso_num_seg;
  395. } else {
  396. /* Bug: free tso_num_seg and tso_seg */
  397. /* Free the already allocated num of segments */
  398. struct qdf_tso_seg_elem_t *free_seg =
  399. tso_info->tso_seg_list;
  400. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  401. __func__);
  402. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  403. return QDF_STATUS_E_NOMEM;
  404. }
  405. msdu_info->num_seg =
  406. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  407. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  408. msdu_info->num_seg);
  409. if (!(msdu_info->num_seg)) {
  410. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  411. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  412. msdu_info);
  413. return QDF_STATUS_E_INVAL;
  414. }
  415. tso_info->curr_seg = tso_info->tso_seg_list;
  416. return QDF_STATUS_SUCCESS;
  417. }
  418. #else
  419. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  420. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  421. {
  422. return QDF_STATUS_E_NOMEM;
  423. }
  424. #endif
  425. /**
  426. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  427. * @vdev: DP Vdev handle
  428. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  429. * @desc_pool_id: Descriptor Pool ID
  430. *
  431. * Return:
  432. */
  433. static
  434. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  435. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  436. {
  437. uint8_t i;
  438. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  439. struct dp_tx_seg_info_s *seg_info;
  440. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  441. struct dp_soc *soc = vdev->pdev->soc;
  442. /* Allocate an extension descriptor */
  443. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  444. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  445. if (!msdu_ext_desc) {
  446. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  447. return NULL;
  448. }
  449. if (msdu_info->exception_fw &&
  450. qdf_unlikely(vdev->mesh_vdev)) {
  451. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  452. &msdu_info->meta_data[0],
  453. sizeof(struct htt_tx_msdu_desc_ext2_t));
  454. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  455. }
  456. switch (msdu_info->frm_type) {
  457. case dp_tx_frm_sg:
  458. case dp_tx_frm_me:
  459. case dp_tx_frm_raw:
  460. seg_info = msdu_info->u.sg_info.curr_seg;
  461. /* Update the buffer pointers in MSDU Extension Descriptor */
  462. for (i = 0; i < seg_info->frag_cnt; i++) {
  463. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  464. seg_info->frags[i].paddr_lo,
  465. seg_info->frags[i].paddr_hi,
  466. seg_info->frags[i].len);
  467. }
  468. break;
  469. case dp_tx_frm_tso:
  470. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  471. &cached_ext_desc[0]);
  472. break;
  473. default:
  474. break;
  475. }
  476. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  477. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  478. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  479. msdu_ext_desc->vaddr);
  480. return msdu_ext_desc;
  481. }
  482. /**
  483. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  484. *
  485. * @skb: skb to be traced
  486. * @msdu_id: msdu_id of the packet
  487. * @vdev_id: vdev_id of the packet
  488. *
  489. * Return: None
  490. */
  491. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  492. uint8_t vdev_id)
  493. {
  494. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  495. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  496. DPTRACE(qdf_dp_trace_ptr(skb,
  497. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  498. QDF_TRACE_DEFAULT_PDEV_ID,
  499. qdf_nbuf_data_addr(skb),
  500. sizeof(qdf_nbuf_data(skb)),
  501. msdu_id, vdev_id));
  502. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  503. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  504. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  505. msdu_id, QDF_TX));
  506. }
  507. /**
  508. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  509. * @vdev: DP vdev handle
  510. * @nbuf: skb
  511. * @desc_pool_id: Descriptor pool ID
  512. * @meta_data: Metadata to the fw
  513. * @tx_exc_metadata: Handle that holds exception path metadata
  514. * Allocate and prepare Tx descriptor with msdu information.
  515. *
  516. * Return: Pointer to Tx Descriptor on success,
  517. * NULL on failure
  518. */
  519. static
  520. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  521. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  522. struct dp_tx_msdu_info_s *msdu_info,
  523. struct cdp_tx_exception_metadata *tx_exc_metadata)
  524. {
  525. uint8_t align_pad;
  526. uint8_t is_exception = 0;
  527. uint8_t htt_hdr_size;
  528. struct ether_header *eh;
  529. struct dp_tx_desc_s *tx_desc;
  530. struct dp_pdev *pdev = vdev->pdev;
  531. struct dp_soc *soc = pdev->soc;
  532. /* Allocate software Tx descriptor */
  533. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  534. if (qdf_unlikely(!tx_desc)) {
  535. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  536. return NULL;
  537. }
  538. /* Flow control/Congestion Control counters */
  539. qdf_atomic_inc(&pdev->num_tx_outstanding);
  540. /* Initialize the SW tx descriptor */
  541. tx_desc->nbuf = nbuf;
  542. tx_desc->frm_type = dp_tx_frm_std;
  543. tx_desc->tx_encap_type = (tx_exc_metadata ?
  544. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  545. tx_desc->vdev = vdev;
  546. tx_desc->pdev = pdev;
  547. tx_desc->msdu_ext_desc = NULL;
  548. tx_desc->pkt_offset = 0;
  549. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  550. /* Reset the control block */
  551. qdf_nbuf_reset_ctxt(nbuf);
  552. /*
  553. * For special modes (vdev_type == ocb or mesh), data frames should be
  554. * transmitted using varying transmit parameters (tx spec) which include
  555. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  556. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  557. * These frames are sent as exception packets to firmware.
  558. *
  559. * HW requirement is that metadata should always point to a
  560. * 8-byte aligned address. So we add alignment pad to start of buffer.
  561. * HTT Metadata should be ensured to be multiple of 8-bytes,
  562. * to get 8-byte aligned start address along with align_pad added
  563. *
  564. * |-----------------------------|
  565. * | |
  566. * |-----------------------------| <-----Buffer Pointer Address given
  567. * | | ^ in HW descriptor (aligned)
  568. * | HTT Metadata | |
  569. * | | |
  570. * | | | Packet Offset given in descriptor
  571. * | | |
  572. * |-----------------------------| |
  573. * | Alignment Pad | v
  574. * |-----------------------------| <----- Actual buffer start address
  575. * | SKB Data | (Unaligned)
  576. * | |
  577. * | |
  578. * | |
  579. * | |
  580. * | |
  581. * |-----------------------------|
  582. */
  583. if (qdf_unlikely((msdu_info->exception_fw)) ||
  584. (vdev->opmode == wlan_op_mode_ocb)) {
  585. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  586. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  587. DP_STATS_INC(vdev,
  588. tx_i.dropped.headroom_insufficient, 1);
  589. goto failure;
  590. }
  591. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  593. "qdf_nbuf_push_head failed");
  594. goto failure;
  595. }
  596. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  597. msdu_info->meta_data);
  598. if (htt_hdr_size == 0)
  599. goto failure;
  600. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  601. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  602. is_exception = 1;
  603. }
  604. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  605. qdf_nbuf_map(soc->osdev, nbuf,
  606. QDF_DMA_TO_DEVICE))) {
  607. /* Handle failure */
  608. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  609. "qdf_nbuf_map failed");
  610. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  611. goto failure;
  612. }
  613. if (qdf_unlikely(vdev->nawds_enabled)) {
  614. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  615. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  616. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  617. is_exception = 1;
  618. }
  619. }
  620. #if !TQM_BYPASS_WAR
  621. if (is_exception || tx_exc_metadata)
  622. #endif
  623. {
  624. /* Temporary WAR due to TQM VP issues */
  625. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  626. qdf_atomic_inc(&pdev->num_tx_exception);
  627. }
  628. return tx_desc;
  629. failure:
  630. dp_tx_desc_release(tx_desc, desc_pool_id);
  631. return NULL;
  632. }
  633. /**
  634. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  635. * @vdev: DP vdev handle
  636. * @nbuf: skb
  637. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  638. * @desc_pool_id : Descriptor Pool ID
  639. *
  640. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  641. * information. For frames wth fragments, allocate and prepare
  642. * an MSDU extension descriptor
  643. *
  644. * Return: Pointer to Tx Descriptor on success,
  645. * NULL on failure
  646. */
  647. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  648. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  649. uint8_t desc_pool_id)
  650. {
  651. struct dp_tx_desc_s *tx_desc;
  652. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  653. struct dp_pdev *pdev = vdev->pdev;
  654. struct dp_soc *soc = pdev->soc;
  655. /* Allocate software Tx descriptor */
  656. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  657. if (!tx_desc) {
  658. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  659. return NULL;
  660. }
  661. /* Flow control/Congestion Control counters */
  662. qdf_atomic_inc(&pdev->num_tx_outstanding);
  663. /* Initialize the SW tx descriptor */
  664. tx_desc->nbuf = nbuf;
  665. tx_desc->frm_type = msdu_info->frm_type;
  666. tx_desc->tx_encap_type = vdev->tx_encap_type;
  667. tx_desc->vdev = vdev;
  668. tx_desc->pdev = pdev;
  669. tx_desc->pkt_offset = 0;
  670. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  671. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  672. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  673. /* Reset the control block */
  674. qdf_nbuf_reset_ctxt(nbuf);
  675. /* Handle scattered frames - TSO/SG/ME */
  676. /* Allocate and prepare an extension descriptor for scattered frames */
  677. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  678. if (!msdu_ext_desc) {
  679. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  680. "%s Tx Extension Descriptor Alloc Fail",
  681. __func__);
  682. goto failure;
  683. }
  684. #if TQM_BYPASS_WAR
  685. /* Temporary WAR due to TQM VP issues */
  686. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  687. qdf_atomic_inc(&pdev->num_tx_exception);
  688. #endif
  689. if (qdf_unlikely(msdu_info->exception_fw))
  690. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  691. tx_desc->msdu_ext_desc = msdu_ext_desc;
  692. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  693. return tx_desc;
  694. failure:
  695. dp_tx_desc_release(tx_desc, desc_pool_id);
  696. return NULL;
  697. }
  698. /**
  699. * dp_tx_prepare_raw() - Prepare RAW packet TX
  700. * @vdev: DP vdev handle
  701. * @nbuf: buffer pointer
  702. * @seg_info: Pointer to Segment info Descriptor to be prepared
  703. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  704. * descriptor
  705. *
  706. * Return:
  707. */
  708. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  709. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  710. {
  711. qdf_nbuf_t curr_nbuf = NULL;
  712. uint16_t total_len = 0;
  713. qdf_dma_addr_t paddr;
  714. int32_t i;
  715. int32_t mapped_buf_num = 0;
  716. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  717. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  718. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  719. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  720. if (vdev->raw_mode_war &&
  721. (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS))
  722. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  723. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  724. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  725. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  726. QDF_DMA_TO_DEVICE)) {
  727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  728. "%s dma map error ", __func__);
  729. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  730. mapped_buf_num = i;
  731. goto error;
  732. }
  733. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  734. seg_info->frags[i].paddr_lo = paddr;
  735. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  736. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  737. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  738. total_len += qdf_nbuf_len(curr_nbuf);
  739. }
  740. seg_info->frag_cnt = i;
  741. seg_info->total_len = total_len;
  742. seg_info->next = NULL;
  743. sg_info->curr_seg = seg_info;
  744. msdu_info->frm_type = dp_tx_frm_raw;
  745. msdu_info->num_seg = 1;
  746. return nbuf;
  747. error:
  748. i = 0;
  749. while (nbuf) {
  750. curr_nbuf = nbuf;
  751. if (i < mapped_buf_num) {
  752. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  753. i++;
  754. }
  755. nbuf = qdf_nbuf_next(nbuf);
  756. qdf_nbuf_free(curr_nbuf);
  757. }
  758. return NULL;
  759. }
  760. /**
  761. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  762. * @soc: DP Soc Handle
  763. * @vdev: DP vdev handle
  764. * @tx_desc: Tx Descriptor Handle
  765. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  766. * @fw_metadata: Metadata to send to Target Firmware along with frame
  767. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  768. * @tx_exc_metadata: Handle that holds exception path meta data
  769. *
  770. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  771. * from software Tx descriptor
  772. *
  773. * Return:
  774. */
  775. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  776. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  777. uint16_t fw_metadata, uint8_t ring_id,
  778. struct cdp_tx_exception_metadata
  779. *tx_exc_metadata)
  780. {
  781. uint8_t type;
  782. uint16_t length;
  783. void *hal_tx_desc, *hal_tx_desc_cached;
  784. qdf_dma_addr_t dma_addr;
  785. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  786. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  787. tx_exc_metadata->sec_type : vdev->sec_type);
  788. /* Return Buffer Manager ID */
  789. uint8_t bm_id = ring_id;
  790. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  791. hal_tx_desc_cached = (void *) cached_desc;
  792. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  793. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  794. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  795. type = HAL_TX_BUF_TYPE_EXT_DESC;
  796. dma_addr = tx_desc->msdu_ext_desc->paddr;
  797. } else {
  798. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  799. type = HAL_TX_BUF_TYPE_BUFFER;
  800. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  801. }
  802. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  803. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  804. dma_addr, bm_id, tx_desc->id,
  805. type, soc->hal_soc);
  806. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  807. return QDF_STATUS_E_RESOURCES;
  808. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  809. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  810. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  811. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  812. vdev->pdev->lmac_id);
  813. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  814. vdev->search_type);
  815. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  816. vdev->bss_ast_hash);
  817. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  818. vdev->dscp_tid_map_id);
  819. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  820. sec_type_map[sec_type]);
  821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  822. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  823. __func__, length, type, (uint64_t)dma_addr,
  824. tx_desc->pkt_offset, tx_desc->id);
  825. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  826. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  827. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  828. vdev->hal_desc_addr_search_flags);
  829. /* verify checksum offload configuration*/
  830. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  831. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  832. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  833. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  834. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  835. }
  836. if (tid != HTT_TX_EXT_TID_INVALID)
  837. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  838. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  839. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  840. /* Sync cached descriptor with HW */
  841. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  842. if (!hal_tx_desc) {
  843. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  844. "%s TCL ring full ring_id:%d", __func__, ring_id);
  845. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  846. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  847. return QDF_STATUS_E_RESOURCES;
  848. }
  849. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  850. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  851. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  852. return QDF_STATUS_SUCCESS;
  853. }
  854. /**
  855. * dp_cce_classify() - Classify the frame based on CCE rules
  856. * @vdev: DP vdev handle
  857. * @nbuf: skb
  858. *
  859. * Classify frames based on CCE rules
  860. * Return: bool( true if classified,
  861. * else false)
  862. */
  863. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  864. {
  865. struct ether_header *eh = NULL;
  866. uint16_t ether_type;
  867. qdf_llc_t *llcHdr;
  868. qdf_nbuf_t nbuf_clone = NULL;
  869. qdf_dot3_qosframe_t *qos_wh = NULL;
  870. /* for mesh packets don't do any classification */
  871. if (qdf_unlikely(vdev->mesh_vdev))
  872. return false;
  873. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  874. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  875. ether_type = eh->ether_type;
  876. llcHdr = (qdf_llc_t *)(nbuf->data +
  877. sizeof(struct ether_header));
  878. } else {
  879. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  880. /* For encrypted packets don't do any classification */
  881. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  882. return false;
  883. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  884. if (qdf_unlikely(
  885. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  886. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  887. ether_type = *(uint16_t *)(nbuf->data
  888. + QDF_IEEE80211_4ADDR_HDR_LEN
  889. + sizeof(qdf_llc_t)
  890. - sizeof(ether_type));
  891. llcHdr = (qdf_llc_t *)(nbuf->data +
  892. QDF_IEEE80211_4ADDR_HDR_LEN);
  893. } else {
  894. ether_type = *(uint16_t *)(nbuf->data
  895. + QDF_IEEE80211_3ADDR_HDR_LEN
  896. + sizeof(qdf_llc_t)
  897. - sizeof(ether_type));
  898. llcHdr = (qdf_llc_t *)(nbuf->data +
  899. QDF_IEEE80211_3ADDR_HDR_LEN);
  900. }
  901. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  902. && (ether_type ==
  903. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  904. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  905. return true;
  906. }
  907. }
  908. return false;
  909. }
  910. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  911. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  912. sizeof(*llcHdr));
  913. nbuf_clone = qdf_nbuf_clone(nbuf);
  914. if (qdf_unlikely(nbuf_clone)) {
  915. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  916. if (ether_type == htons(ETHERTYPE_8021Q)) {
  917. qdf_nbuf_pull_head(nbuf_clone,
  918. sizeof(qdf_net_vlanhdr_t));
  919. }
  920. }
  921. } else {
  922. if (ether_type == htons(ETHERTYPE_8021Q)) {
  923. nbuf_clone = qdf_nbuf_clone(nbuf);
  924. if (qdf_unlikely(nbuf_clone)) {
  925. qdf_nbuf_pull_head(nbuf_clone,
  926. sizeof(qdf_net_vlanhdr_t));
  927. }
  928. }
  929. }
  930. if (qdf_unlikely(nbuf_clone))
  931. nbuf = nbuf_clone;
  932. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  933. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  934. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  935. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  936. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  937. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  938. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  939. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  940. if (qdf_unlikely(nbuf_clone != NULL))
  941. qdf_nbuf_free(nbuf_clone);
  942. return true;
  943. }
  944. if (qdf_unlikely(nbuf_clone != NULL))
  945. qdf_nbuf_free(nbuf_clone);
  946. return false;
  947. }
  948. /**
  949. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  950. * @vdev: DP vdev handle
  951. * @nbuf: skb
  952. *
  953. * Extract the DSCP or PCP information from frame and map into TID value.
  954. * Software based TID classification is required when more than 2 DSCP-TID
  955. * mapping tables are needed.
  956. * Hardware supports 2 DSCP-TID mapping tables
  957. *
  958. * Return: void
  959. */
  960. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  961. struct dp_tx_msdu_info_s *msdu_info)
  962. {
  963. uint8_t tos = 0, dscp_tid_override = 0;
  964. uint8_t *hdr_ptr, *L3datap;
  965. uint8_t is_mcast = 0;
  966. struct ether_header *eh = NULL;
  967. qdf_ethervlan_header_t *evh = NULL;
  968. uint16_t ether_type;
  969. qdf_llc_t *llcHdr;
  970. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  971. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  972. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  973. return;
  974. /* for mesh packets don't do any classification */
  975. if (qdf_unlikely(vdev->mesh_vdev))
  976. return;
  977. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  978. eh = (struct ether_header *) nbuf->data;
  979. hdr_ptr = eh->ether_dhost;
  980. L3datap = hdr_ptr + sizeof(struct ether_header);
  981. } else {
  982. qdf_dot3_qosframe_t *qos_wh =
  983. (qdf_dot3_qosframe_t *) nbuf->data;
  984. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  985. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  986. return;
  987. }
  988. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  989. ether_type = eh->ether_type;
  990. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  991. /*
  992. * Check if packet is dot3 or eth2 type.
  993. */
  994. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  995. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  996. sizeof(*llcHdr));
  997. if (ether_type == htons(ETHERTYPE_8021Q)) {
  998. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  999. sizeof(*llcHdr);
  1000. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  1001. + sizeof(*llcHdr) +
  1002. sizeof(qdf_net_vlanhdr_t));
  1003. } else {
  1004. L3datap = hdr_ptr + sizeof(struct ether_header) +
  1005. sizeof(*llcHdr);
  1006. }
  1007. } else {
  1008. if (ether_type == htons(ETHERTYPE_8021Q)) {
  1009. evh = (qdf_ethervlan_header_t *) eh;
  1010. ether_type = evh->ether_type;
  1011. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1012. }
  1013. }
  1014. /*
  1015. * Find priority from IP TOS DSCP field
  1016. */
  1017. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1018. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1019. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1020. /* Only for unicast frames */
  1021. if (!is_mcast) {
  1022. /* send it on VO queue */
  1023. msdu_info->tid = DP_VO_TID;
  1024. }
  1025. } else {
  1026. /*
  1027. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1028. * from TOS byte.
  1029. */
  1030. tos = ip->ip_tos;
  1031. dscp_tid_override = 1;
  1032. }
  1033. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1034. /* TODO
  1035. * use flowlabel
  1036. *igmpmld cases to be handled in phase 2
  1037. */
  1038. unsigned long ver_pri_flowlabel;
  1039. unsigned long pri;
  1040. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1041. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1042. DP_IPV6_PRIORITY_SHIFT;
  1043. tos = pri;
  1044. dscp_tid_override = 1;
  1045. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1046. msdu_info->tid = DP_VO_TID;
  1047. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1048. /* Only for unicast frames */
  1049. if (!is_mcast) {
  1050. /* send ucast arp on VO queue */
  1051. msdu_info->tid = DP_VO_TID;
  1052. }
  1053. }
  1054. /*
  1055. * Assign all MCAST packets to BE
  1056. */
  1057. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1058. if (is_mcast) {
  1059. tos = 0;
  1060. dscp_tid_override = 1;
  1061. }
  1062. }
  1063. if (dscp_tid_override == 1) {
  1064. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1065. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1066. }
  1067. return;
  1068. }
  1069. #ifdef CONVERGED_TDLS_ENABLE
  1070. /**
  1071. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1072. * @tx_desc: TX descriptor
  1073. *
  1074. * Return: None
  1075. */
  1076. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1077. {
  1078. if (tx_desc->vdev) {
  1079. if (tx_desc->vdev->is_tdls_frame)
  1080. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1081. tx_desc->vdev->is_tdls_frame = false;
  1082. }
  1083. }
  1084. /**
  1085. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1086. * @tx_desc: TX descriptor
  1087. * @vdev: datapath vdev handle
  1088. *
  1089. * Return: None
  1090. */
  1091. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1092. struct dp_vdev *vdev)
  1093. {
  1094. struct hal_tx_completion_status ts = {0};
  1095. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1096. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1097. if (vdev->tx_non_std_data_callback.func) {
  1098. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1099. vdev->tx_non_std_data_callback.func(
  1100. vdev->tx_non_std_data_callback.ctxt,
  1101. nbuf, ts.status);
  1102. return;
  1103. }
  1104. }
  1105. #endif
  1106. /**
  1107. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1108. * @vdev: DP vdev handle
  1109. * @nbuf: skb
  1110. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1111. * @meta_data: Metadata to the fw
  1112. * @tx_q: Tx queue to be used for this Tx frame
  1113. * @peer_id: peer_id of the peer in case of NAWDS frames
  1114. * @tx_exc_metadata: Handle that holds exception path metadata
  1115. *
  1116. * Return: NULL on success,
  1117. * nbuf when it fails to send
  1118. */
  1119. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1120. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1121. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1122. {
  1123. struct dp_pdev *pdev = vdev->pdev;
  1124. struct dp_soc *soc = pdev->soc;
  1125. struct dp_tx_desc_s *tx_desc;
  1126. QDF_STATUS status;
  1127. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1128. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1129. uint16_t htt_tcl_metadata = 0;
  1130. uint8_t tid = msdu_info->tid;
  1131. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1132. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1133. msdu_info, tx_exc_metadata);
  1134. if (!tx_desc) {
  1135. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1136. "%s Tx_desc prepare Fail vdev %pK queue %d",
  1137. __func__, vdev, tx_q->desc_pool_id);
  1138. return nbuf;
  1139. }
  1140. if (qdf_unlikely(soc->cce_disable)) {
  1141. if (dp_cce_classify(vdev, nbuf) == true) {
  1142. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1143. tid = DP_VO_TID;
  1144. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1145. }
  1146. }
  1147. dp_tx_update_tdls_flags(tx_desc);
  1148. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1149. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1150. "%s %d : HAL RING Access Failed -- %pK",
  1151. __func__, __LINE__, hal_srng);
  1152. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1153. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1154. goto fail_return;
  1155. }
  1156. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1157. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1158. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1159. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1160. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1161. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1162. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1163. peer_id);
  1164. } else
  1165. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1166. if (msdu_info->exception_fw) {
  1167. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1168. }
  1169. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1170. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1171. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1172. if (status != QDF_STATUS_SUCCESS) {
  1173. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1174. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1175. __func__, tx_desc, tx_q->ring_id);
  1176. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1177. goto fail_return;
  1178. }
  1179. nbuf = NULL;
  1180. fail_return:
  1181. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1182. hal_srng_access_end(soc->hal_soc, hal_srng);
  1183. hif_pm_runtime_put(soc->hif_handle);
  1184. } else {
  1185. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1186. }
  1187. return nbuf;
  1188. }
  1189. /**
  1190. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1191. * @vdev: DP vdev handle
  1192. * @nbuf: skb
  1193. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1194. *
  1195. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1196. *
  1197. * Return: NULL on success,
  1198. * nbuf when it fails to send
  1199. */
  1200. #if QDF_LOCK_STATS
  1201. static noinline
  1202. #else
  1203. static
  1204. #endif
  1205. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1206. struct dp_tx_msdu_info_s *msdu_info)
  1207. {
  1208. uint8_t i;
  1209. struct dp_pdev *pdev = vdev->pdev;
  1210. struct dp_soc *soc = pdev->soc;
  1211. struct dp_tx_desc_s *tx_desc;
  1212. bool is_cce_classified = false;
  1213. QDF_STATUS status;
  1214. uint16_t htt_tcl_metadata = 0;
  1215. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1216. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1217. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1218. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1219. "%s %d : HAL RING Access Failed -- %pK",
  1220. __func__, __LINE__, hal_srng);
  1221. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1222. return nbuf;
  1223. }
  1224. if (qdf_unlikely(soc->cce_disable)) {
  1225. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1226. if (is_cce_classified) {
  1227. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1228. msdu_info->tid = DP_VO_TID;
  1229. }
  1230. }
  1231. if (msdu_info->frm_type == dp_tx_frm_me)
  1232. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1233. i = 0;
  1234. /* Print statement to track i and num_seg */
  1235. /*
  1236. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1237. * descriptors using information in msdu_info
  1238. */
  1239. while (i < msdu_info->num_seg) {
  1240. /*
  1241. * Setup Tx descriptor for an MSDU, and MSDU extension
  1242. * descriptor
  1243. */
  1244. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1245. tx_q->desc_pool_id);
  1246. if (!tx_desc) {
  1247. if (msdu_info->frm_type == dp_tx_frm_me) {
  1248. dp_tx_me_free_buf(pdev,
  1249. (void *)(msdu_info->u.sg_info
  1250. .curr_seg->frags[0].vaddr));
  1251. }
  1252. goto done;
  1253. }
  1254. if (msdu_info->frm_type == dp_tx_frm_me) {
  1255. tx_desc->me_buffer =
  1256. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1257. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1258. }
  1259. if (is_cce_classified)
  1260. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1261. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1262. if (msdu_info->exception_fw) {
  1263. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1264. }
  1265. /*
  1266. * Enqueue the Tx MSDU descriptor to HW for transmit
  1267. */
  1268. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1269. htt_tcl_metadata, tx_q->ring_id, NULL);
  1270. if (status != QDF_STATUS_SUCCESS) {
  1271. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1272. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1273. __func__, tx_desc, tx_q->ring_id);
  1274. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1275. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1276. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1277. goto done;
  1278. }
  1279. /*
  1280. * TODO
  1281. * if tso_info structure can be modified to have curr_seg
  1282. * as first element, following 2 blocks of code (for TSO and SG)
  1283. * can be combined into 1
  1284. */
  1285. /*
  1286. * For frames with multiple segments (TSO, ME), jump to next
  1287. * segment.
  1288. */
  1289. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1290. if (msdu_info->u.tso_info.curr_seg->next) {
  1291. msdu_info->u.tso_info.curr_seg =
  1292. msdu_info->u.tso_info.curr_seg->next;
  1293. /*
  1294. * If this is a jumbo nbuf, then increment the number of
  1295. * nbuf users for each additional segment of the msdu.
  1296. * This will ensure that the skb is freed only after
  1297. * receiving tx completion for all segments of an nbuf
  1298. */
  1299. qdf_nbuf_inc_users(nbuf);
  1300. /* Check with MCL if this is needed */
  1301. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1302. }
  1303. }
  1304. /*
  1305. * For Multicast-Unicast converted packets,
  1306. * each converted frame (for a client) is represented as
  1307. * 1 segment
  1308. */
  1309. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1310. (msdu_info->frm_type == dp_tx_frm_me)) {
  1311. if (msdu_info->u.sg_info.curr_seg->next) {
  1312. msdu_info->u.sg_info.curr_seg =
  1313. msdu_info->u.sg_info.curr_seg->next;
  1314. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1315. }
  1316. }
  1317. i++;
  1318. }
  1319. nbuf = NULL;
  1320. done:
  1321. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1322. hal_srng_access_end(soc->hal_soc, hal_srng);
  1323. hif_pm_runtime_put(soc->hif_handle);
  1324. } else {
  1325. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1326. }
  1327. return nbuf;
  1328. }
  1329. /**
  1330. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1331. * for SG frames
  1332. * @vdev: DP vdev handle
  1333. * @nbuf: skb
  1334. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1335. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1336. *
  1337. * Return: NULL on success,
  1338. * nbuf when it fails to send
  1339. */
  1340. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1341. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1342. {
  1343. uint32_t cur_frag, nr_frags;
  1344. qdf_dma_addr_t paddr;
  1345. struct dp_tx_sg_info_s *sg_info;
  1346. sg_info = &msdu_info->u.sg_info;
  1347. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1348. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1349. QDF_DMA_TO_DEVICE)) {
  1350. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1351. "dma map error");
  1352. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1353. qdf_nbuf_free(nbuf);
  1354. return NULL;
  1355. }
  1356. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1357. seg_info->frags[0].paddr_lo = paddr;
  1358. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1359. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1360. seg_info->frags[0].vaddr = (void *) nbuf;
  1361. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1362. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1363. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1364. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1365. "frag dma map error");
  1366. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1367. qdf_nbuf_free(nbuf);
  1368. return NULL;
  1369. }
  1370. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1371. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1372. seg_info->frags[cur_frag + 1].paddr_hi =
  1373. ((uint64_t) paddr) >> 32;
  1374. seg_info->frags[cur_frag + 1].len =
  1375. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1376. }
  1377. seg_info->frag_cnt = (cur_frag + 1);
  1378. seg_info->total_len = qdf_nbuf_len(nbuf);
  1379. seg_info->next = NULL;
  1380. sg_info->curr_seg = seg_info;
  1381. msdu_info->frm_type = dp_tx_frm_sg;
  1382. msdu_info->num_seg = 1;
  1383. return nbuf;
  1384. }
  1385. #ifdef MESH_MODE_SUPPORT
  1386. /**
  1387. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1388. and prepare msdu_info for mesh frames.
  1389. * @vdev: DP vdev handle
  1390. * @nbuf: skb
  1391. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1392. *
  1393. * Return: NULL on failure,
  1394. * nbuf when extracted successfully
  1395. */
  1396. static
  1397. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1398. struct dp_tx_msdu_info_s *msdu_info)
  1399. {
  1400. struct meta_hdr_s *mhdr;
  1401. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1402. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1403. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1404. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1405. msdu_info->exception_fw = 0;
  1406. goto remove_meta_hdr;
  1407. }
  1408. msdu_info->exception_fw = 1;
  1409. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1410. meta_data->host_tx_desc_pool = 1;
  1411. meta_data->update_peer_cache = 1;
  1412. meta_data->learning_frame = 1;
  1413. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1414. meta_data->power = mhdr->power;
  1415. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1416. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1417. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1418. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1419. meta_data->dyn_bw = 1;
  1420. meta_data->valid_pwr = 1;
  1421. meta_data->valid_mcs_mask = 1;
  1422. meta_data->valid_nss_mask = 1;
  1423. meta_data->valid_preamble_type = 1;
  1424. meta_data->valid_retries = 1;
  1425. meta_data->valid_bw_info = 1;
  1426. }
  1427. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1428. meta_data->encrypt_type = 0;
  1429. meta_data->valid_encrypt_type = 1;
  1430. meta_data->learning_frame = 0;
  1431. }
  1432. meta_data->valid_key_flags = 1;
  1433. meta_data->key_flags = (mhdr->keyix & 0x3);
  1434. remove_meta_hdr:
  1435. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1436. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1437. "qdf_nbuf_pull_head failed");
  1438. qdf_nbuf_free(nbuf);
  1439. return NULL;
  1440. }
  1441. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1442. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1443. else
  1444. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1445. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1446. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1447. " tid %d to_fw %d",
  1448. __func__, msdu_info->meta_data[0],
  1449. msdu_info->meta_data[1],
  1450. msdu_info->meta_data[2],
  1451. msdu_info->meta_data[3],
  1452. msdu_info->meta_data[4],
  1453. msdu_info->meta_data[5],
  1454. msdu_info->tid, msdu_info->exception_fw);
  1455. return nbuf;
  1456. }
  1457. #else
  1458. static
  1459. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1460. struct dp_tx_msdu_info_s *msdu_info)
  1461. {
  1462. return nbuf;
  1463. }
  1464. #endif
  1465. #ifdef DP_FEATURE_NAWDS_TX
  1466. /**
  1467. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1468. * @vdev: dp_vdev handle
  1469. * @nbuf: skb
  1470. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1471. * @tx_q: Tx queue to be used for this Tx frame
  1472. * @meta_data: Meta date for mesh
  1473. * @peer_id: peer_id of the peer in case of NAWDS frames
  1474. *
  1475. * return: NULL on success nbuf on failure
  1476. */
  1477. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1478. struct dp_tx_msdu_info_s *msdu_info)
  1479. {
  1480. struct dp_peer *peer = NULL;
  1481. struct dp_soc *soc = vdev->pdev->soc;
  1482. struct dp_ast_entry *ast_entry = NULL;
  1483. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1484. uint16_t peer_id = HTT_INVALID_PEER;
  1485. struct dp_peer *sa_peer = NULL;
  1486. qdf_nbuf_t nbuf_copy;
  1487. qdf_spin_lock_bh(&(soc->ast_lock));
  1488. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1489. if (ast_entry)
  1490. sa_peer = ast_entry->peer;
  1491. qdf_spin_unlock_bh(&(soc->ast_lock));
  1492. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1493. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1494. (peer->nawds_enabled)) {
  1495. if (sa_peer == peer) {
  1496. QDF_TRACE(QDF_MODULE_ID_DP,
  1497. QDF_TRACE_LEVEL_DEBUG,
  1498. " %s: broadcast multicast packet",
  1499. __func__);
  1500. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1501. continue;
  1502. }
  1503. nbuf_copy = qdf_nbuf_copy(nbuf);
  1504. if (!nbuf_copy) {
  1505. QDF_TRACE(QDF_MODULE_ID_DP,
  1506. QDF_TRACE_LEVEL_ERROR,
  1507. "nbuf copy failed");
  1508. }
  1509. peer_id = peer->peer_ids[0];
  1510. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1511. msdu_info, peer_id, NULL);
  1512. if (nbuf_copy != NULL) {
  1513. qdf_nbuf_free(nbuf_copy);
  1514. continue;
  1515. }
  1516. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1517. 1, qdf_nbuf_len(nbuf));
  1518. }
  1519. }
  1520. if (peer_id == HTT_INVALID_PEER)
  1521. return nbuf;
  1522. return NULL;
  1523. }
  1524. #endif
  1525. /**
  1526. * dp_check_exc_metadata() - Checks if parameters are valid
  1527. * @tx_exc - holds all exception path parameters
  1528. *
  1529. * Returns true when all the parameters are valid else false
  1530. *
  1531. */
  1532. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1533. {
  1534. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1535. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1536. tx_exc->sec_type > cdp_num_sec_types) {
  1537. return false;
  1538. }
  1539. return true;
  1540. }
  1541. /**
  1542. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1543. * @vap_dev: DP vdev handle
  1544. * @nbuf: skb
  1545. * @tx_exc_metadata: Handle that holds exception path meta data
  1546. *
  1547. * Entry point for Core Tx layer (DP_TX) invoked from
  1548. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1549. *
  1550. * Return: NULL on success,
  1551. * nbuf when it fails to send
  1552. */
  1553. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1554. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1555. {
  1556. struct ether_header *eh = NULL;
  1557. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1558. struct dp_tx_msdu_info_s msdu_info;
  1559. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1560. msdu_info.tid = tx_exc_metadata->tid;
  1561. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1562. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1563. "%s , skb %pM",
  1564. __func__, nbuf->data);
  1565. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1566. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1567. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1568. "Invalid parameters in exception path");
  1569. goto fail;
  1570. }
  1571. /* Basic sanity checks for unsupported packets */
  1572. /* MESH mode */
  1573. if (qdf_unlikely(vdev->mesh_vdev)) {
  1574. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1575. "Mesh mode is not supported in exception path");
  1576. goto fail;
  1577. }
  1578. /* TSO or SG */
  1579. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1580. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1581. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1582. "TSO and SG are not supported in exception path");
  1583. goto fail;
  1584. }
  1585. /* RAW */
  1586. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1587. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1588. "Raw frame is not supported in exception path");
  1589. goto fail;
  1590. }
  1591. /* Mcast enhancement*/
  1592. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1593. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1594. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1595. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1596. }
  1597. }
  1598. /*
  1599. * Get HW Queue to use for this frame.
  1600. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1601. * dedicated for data and 1 for command.
  1602. * "queue_id" maps to one hardware ring.
  1603. * With each ring, we also associate a unique Tx descriptor pool
  1604. * to minimize lock contention for these resources.
  1605. */
  1606. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1607. /* Single linear frame */
  1608. /*
  1609. * If nbuf is a simple linear frame, use send_single function to
  1610. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1611. * SRNG. There is no need to setup a MSDU extension descriptor.
  1612. */
  1613. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1614. tx_exc_metadata->peer_id, tx_exc_metadata);
  1615. return nbuf;
  1616. fail:
  1617. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1618. "pkt send failed");
  1619. return nbuf;
  1620. }
  1621. /**
  1622. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1623. * @vap_dev: DP vdev handle
  1624. * @nbuf: skb
  1625. *
  1626. * Entry point for Core Tx layer (DP_TX) invoked from
  1627. * hard_start_xmit in OSIF/HDD
  1628. *
  1629. * Return: NULL on success,
  1630. * nbuf when it fails to send
  1631. */
  1632. #ifdef MESH_MODE_SUPPORT
  1633. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1634. {
  1635. struct meta_hdr_s *mhdr;
  1636. qdf_nbuf_t nbuf_mesh = NULL;
  1637. qdf_nbuf_t nbuf_clone = NULL;
  1638. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1639. uint8_t no_enc_frame = 0;
  1640. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1641. if (nbuf_mesh == NULL) {
  1642. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1643. "qdf_nbuf_unshare failed");
  1644. return nbuf;
  1645. }
  1646. nbuf = nbuf_mesh;
  1647. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1648. if ((vdev->sec_type != cdp_sec_type_none) &&
  1649. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1650. no_enc_frame = 1;
  1651. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1652. !no_enc_frame) {
  1653. nbuf_clone = qdf_nbuf_clone(nbuf);
  1654. if (nbuf_clone == NULL) {
  1655. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1656. "qdf_nbuf_clone failed");
  1657. return nbuf;
  1658. }
  1659. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1660. }
  1661. if (nbuf_clone) {
  1662. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1663. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1664. } else {
  1665. qdf_nbuf_free(nbuf_clone);
  1666. }
  1667. }
  1668. if (no_enc_frame)
  1669. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1670. else
  1671. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1672. nbuf = dp_tx_send(vap_dev, nbuf);
  1673. if ((nbuf == NULL) && no_enc_frame) {
  1674. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1675. }
  1676. return nbuf;
  1677. }
  1678. #else
  1679. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1680. {
  1681. return dp_tx_send(vap_dev, nbuf);
  1682. }
  1683. #endif
  1684. /**
  1685. * dp_tx_send() - Transmit a frame on a given VAP
  1686. * @vap_dev: DP vdev handle
  1687. * @nbuf: skb
  1688. *
  1689. * Entry point for Core Tx layer (DP_TX) invoked from
  1690. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1691. * cases
  1692. *
  1693. * Return: NULL on success,
  1694. * nbuf when it fails to send
  1695. */
  1696. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1697. {
  1698. struct ether_header *eh = NULL;
  1699. struct dp_tx_msdu_info_s msdu_info;
  1700. struct dp_tx_seg_info_s seg_info;
  1701. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1702. uint16_t peer_id = HTT_INVALID_PEER;
  1703. qdf_nbuf_t nbuf_mesh = NULL;
  1704. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1705. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1706. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1707. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1708. "%s , skb %pM",
  1709. __func__, nbuf->data);
  1710. /*
  1711. * Set Default Host TID value to invalid TID
  1712. * (TID override disabled)
  1713. */
  1714. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1715. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1716. if (qdf_unlikely(vdev->mesh_vdev)) {
  1717. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1718. &msdu_info);
  1719. if (nbuf_mesh == NULL) {
  1720. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1721. "Extracting mesh metadata failed");
  1722. return nbuf;
  1723. }
  1724. nbuf = nbuf_mesh;
  1725. }
  1726. /*
  1727. * Get HW Queue to use for this frame.
  1728. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1729. * dedicated for data and 1 for command.
  1730. * "queue_id" maps to one hardware ring.
  1731. * With each ring, we also associate a unique Tx descriptor pool
  1732. * to minimize lock contention for these resources.
  1733. */
  1734. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1735. /*
  1736. * TCL H/W supports 2 DSCP-TID mapping tables.
  1737. * Table 1 - Default DSCP-TID mapping table
  1738. * Table 2 - 1 DSCP-TID override table
  1739. *
  1740. * If we need a different DSCP-TID mapping for this vap,
  1741. * call tid_classify to extract DSCP/ToS from frame and
  1742. * map to a TID and store in msdu_info. This is later used
  1743. * to fill in TCL Input descriptor (per-packet TID override).
  1744. */
  1745. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1746. /*
  1747. * Classify the frame and call corresponding
  1748. * "prepare" function which extracts the segment (TSO)
  1749. * and fragmentation information (for TSO , SG, ME, or Raw)
  1750. * into MSDU_INFO structure which is later used to fill
  1751. * SW and HW descriptors.
  1752. */
  1753. if (qdf_nbuf_is_tso(nbuf)) {
  1754. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1755. "%s TSO frame %pK", __func__, vdev);
  1756. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1757. qdf_nbuf_len(nbuf));
  1758. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1759. DP_STATS_INC_PKT(vdev, tx_i.tso.dropped_host, 1,
  1760. qdf_nbuf_len(nbuf));
  1761. return nbuf;
  1762. }
  1763. goto send_multiple;
  1764. }
  1765. /* SG */
  1766. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1767. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1768. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1769. "%s non-TSO SG frame %pK", __func__, vdev);
  1770. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1771. qdf_nbuf_len(nbuf));
  1772. goto send_multiple;
  1773. }
  1774. #ifdef ATH_SUPPORT_IQUE
  1775. /* Mcast to Ucast Conversion*/
  1776. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1777. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1778. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1779. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1780. "%s Mcast frm for ME %pK", __func__, vdev);
  1781. DP_STATS_INC_PKT(vdev,
  1782. tx_i.mcast_en.mcast_pkt, 1,
  1783. qdf_nbuf_len(nbuf));
  1784. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1785. QDF_STATUS_SUCCESS) {
  1786. return NULL;
  1787. }
  1788. }
  1789. }
  1790. #endif
  1791. /* RAW */
  1792. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1793. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1794. if (nbuf == NULL)
  1795. return NULL;
  1796. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1797. "%s Raw frame %pK", __func__, vdev);
  1798. goto send_multiple;
  1799. }
  1800. /* Single linear frame */
  1801. /*
  1802. * If nbuf is a simple linear frame, use send_single function to
  1803. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1804. * SRNG. There is no need to setup a MSDU extension descriptor.
  1805. */
  1806. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1807. return nbuf;
  1808. send_multiple:
  1809. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1810. return nbuf;
  1811. }
  1812. /**
  1813. * dp_tx_reinject_handler() - Tx Reinject Handler
  1814. * @tx_desc: software descriptor head pointer
  1815. * @status : Tx completion status from HTT descriptor
  1816. *
  1817. * This function reinjects frames back to Target.
  1818. * Todo - Host queue needs to be added
  1819. *
  1820. * Return: none
  1821. */
  1822. static
  1823. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1824. {
  1825. struct dp_vdev *vdev;
  1826. struct dp_peer *peer = NULL;
  1827. uint32_t peer_id = HTT_INVALID_PEER;
  1828. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1829. qdf_nbuf_t nbuf_copy = NULL;
  1830. struct dp_tx_msdu_info_s msdu_info;
  1831. struct dp_peer *sa_peer = NULL;
  1832. struct dp_ast_entry *ast_entry = NULL;
  1833. struct dp_soc *soc = NULL;
  1834. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1835. #ifdef WDS_VENDOR_EXTENSION
  1836. int is_mcast = 0, is_ucast = 0;
  1837. int num_peers_3addr = 0;
  1838. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1839. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1840. #endif
  1841. vdev = tx_desc->vdev;
  1842. soc = vdev->pdev->soc;
  1843. qdf_assert(vdev);
  1844. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1845. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1846. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1847. "%s Tx reinject path", __func__);
  1848. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1849. qdf_nbuf_len(tx_desc->nbuf));
  1850. qdf_spin_lock_bh(&(soc->ast_lock));
  1851. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1852. if (ast_entry)
  1853. sa_peer = ast_entry->peer;
  1854. qdf_spin_unlock_bh(&(soc->ast_lock));
  1855. #ifdef WDS_VENDOR_EXTENSION
  1856. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1857. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1858. } else {
  1859. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1860. }
  1861. is_ucast = !is_mcast;
  1862. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1863. if (peer->bss_peer)
  1864. continue;
  1865. /* Detect wds peers that use 3-addr framing for mcast.
  1866. * if there are any, the bss_peer is used to send the
  1867. * the mcast frame using 3-addr format. all wds enabled
  1868. * peers that use 4-addr framing for mcast frames will
  1869. * be duplicated and sent as 4-addr frames below.
  1870. */
  1871. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1872. num_peers_3addr = 1;
  1873. break;
  1874. }
  1875. }
  1876. #endif
  1877. if (qdf_unlikely(vdev->mesh_vdev)) {
  1878. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1879. } else {
  1880. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1881. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1882. #ifdef WDS_VENDOR_EXTENSION
  1883. /*
  1884. * . if 3-addr STA, then send on BSS Peer
  1885. * . if Peer WDS enabled and accept 4-addr mcast,
  1886. * send mcast on that peer only
  1887. * . if Peer WDS enabled and accept 4-addr ucast,
  1888. * send ucast on that peer only
  1889. */
  1890. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1891. (peer->wds_enabled &&
  1892. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1893. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1894. #else
  1895. ((peer->bss_peer &&
  1896. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1897. peer->nawds_enabled)) {
  1898. #endif
  1899. peer_id = DP_INVALID_PEER;
  1900. if (peer->nawds_enabled) {
  1901. peer_id = peer->peer_ids[0];
  1902. if (sa_peer == peer) {
  1903. QDF_TRACE(
  1904. QDF_MODULE_ID_DP,
  1905. QDF_TRACE_LEVEL_DEBUG,
  1906. " %s: multicast packet",
  1907. __func__);
  1908. DP_STATS_INC(peer,
  1909. tx.nawds_mcast_drop, 1);
  1910. continue;
  1911. }
  1912. }
  1913. nbuf_copy = qdf_nbuf_copy(nbuf);
  1914. if (!nbuf_copy) {
  1915. QDF_TRACE(QDF_MODULE_ID_DP,
  1916. QDF_TRACE_LEVEL_DEBUG,
  1917. FL("nbuf copy failed"));
  1918. break;
  1919. }
  1920. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1921. nbuf_copy,
  1922. &msdu_info,
  1923. peer_id,
  1924. NULL);
  1925. if (nbuf_copy) {
  1926. QDF_TRACE(QDF_MODULE_ID_DP,
  1927. QDF_TRACE_LEVEL_DEBUG,
  1928. FL("pkt send failed"));
  1929. qdf_nbuf_free(nbuf_copy);
  1930. } else {
  1931. if (peer_id != DP_INVALID_PEER)
  1932. DP_STATS_INC_PKT(peer,
  1933. tx.nawds_mcast,
  1934. 1, qdf_nbuf_len(nbuf));
  1935. }
  1936. }
  1937. }
  1938. }
  1939. if (vdev->nawds_enabled) {
  1940. peer_id = DP_INVALID_PEER;
  1941. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1942. 1, qdf_nbuf_len(nbuf));
  1943. nbuf = dp_tx_send_msdu_single(vdev,
  1944. nbuf,
  1945. &msdu_info,
  1946. peer_id, NULL);
  1947. if (nbuf) {
  1948. QDF_TRACE(QDF_MODULE_ID_DP,
  1949. QDF_TRACE_LEVEL_DEBUG,
  1950. FL("pkt send failed"));
  1951. qdf_nbuf_free(nbuf);
  1952. }
  1953. } else
  1954. qdf_nbuf_free(nbuf);
  1955. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1956. }
  1957. /**
  1958. * dp_tx_inspect_handler() - Tx Inspect Handler
  1959. * @tx_desc: software descriptor head pointer
  1960. * @status : Tx completion status from HTT descriptor
  1961. *
  1962. * Handles Tx frames sent back to Host for inspection
  1963. * (ProxyARP)
  1964. *
  1965. * Return: none
  1966. */
  1967. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1968. {
  1969. struct dp_soc *soc;
  1970. struct dp_pdev *pdev = tx_desc->pdev;
  1971. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1972. "%s Tx inspect path",
  1973. __func__);
  1974. qdf_assert(pdev);
  1975. soc = pdev->soc;
  1976. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1977. qdf_nbuf_len(tx_desc->nbuf));
  1978. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1979. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1980. }
  1981. #ifdef FEATURE_PERPKT_INFO
  1982. /**
  1983. * dp_get_completion_indication_for_stack() - send completion to stack
  1984. * @soc : dp_soc handle
  1985. * @pdev: dp_pdev handle
  1986. * @peer: dp peer handle
  1987. * @peer_id: peer_id of the peer for which completion came
  1988. * @ppdu_id: ppdu_id
  1989. * @first_msdu: first msdu
  1990. * @last_msdu: last msdu
  1991. * @netbuf: Buffer pointer for free
  1992. *
  1993. * This function is used for indication whether buffer needs to be
  1994. * send to stack for free or not
  1995. */
  1996. QDF_STATUS
  1997. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  1998. struct dp_pdev *pdev,
  1999. struct dp_peer *peer, uint16_t peer_id,
  2000. uint32_t ppdu_id, uint8_t first_msdu,
  2001. uint8_t last_msdu, qdf_nbuf_t netbuf)
  2002. {
  2003. struct tx_capture_hdr *ppdu_hdr;
  2004. struct ether_header *eh;
  2005. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  2006. return QDF_STATUS_E_NOSUPPORT;
  2007. if (!peer) {
  2008. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2009. FL("Peer Invalid"));
  2010. return QDF_STATUS_E_INVAL;
  2011. }
  2012. if (pdev->mcopy_mode) {
  2013. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2014. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2015. return QDF_STATUS_E_INVAL;
  2016. }
  2017. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2018. pdev->m_copy_id.tx_peer_id = peer_id;
  2019. }
  2020. eh = (struct ether_header *)qdf_nbuf_data(netbuf);
  2021. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2022. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2023. FL("No headroom"));
  2024. return QDF_STATUS_E_NOMEM;
  2025. }
  2026. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2027. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2028. IEEE80211_ADDR_LEN);
  2029. if (peer->bss_peer) {
  2030. qdf_mem_copy(ppdu_hdr->ra, eh->ether_dhost, IEEE80211_ADDR_LEN);
  2031. } else {
  2032. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2033. IEEE80211_ADDR_LEN);
  2034. }
  2035. ppdu_hdr->ppdu_id = ppdu_id;
  2036. ppdu_hdr->peer_id = peer_id;
  2037. ppdu_hdr->first_msdu = first_msdu;
  2038. ppdu_hdr->last_msdu = last_msdu;
  2039. return QDF_STATUS_SUCCESS;
  2040. }
  2041. /**
  2042. * dp_send_completion_to_stack() - send completion to stack
  2043. * @soc : dp_soc handle
  2044. * @pdev: dp_pdev handle
  2045. * @peer_id: peer_id of the peer for which completion came
  2046. * @ppdu_id: ppdu_id
  2047. * @netbuf: Buffer pointer for free
  2048. *
  2049. * This function is used to send completion to stack
  2050. * to free buffer
  2051. */
  2052. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2053. uint16_t peer_id, uint32_t ppdu_id,
  2054. qdf_nbuf_t netbuf)
  2055. {
  2056. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2057. netbuf, peer_id,
  2058. WDI_NO_VAL, pdev->pdev_id);
  2059. }
  2060. #else
  2061. static QDF_STATUS
  2062. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2063. struct dp_pdev *pdev,
  2064. struct dp_peer *peer, uint16_t peer_id,
  2065. uint32_t ppdu_id, uint8_t first_msdu,
  2066. uint8_t last_msdu, qdf_nbuf_t netbuf)
  2067. {
  2068. return QDF_STATUS_E_NOSUPPORT;
  2069. }
  2070. static void
  2071. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2072. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2073. {
  2074. }
  2075. #endif
  2076. /**
  2077. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2078. * @soc: Soc handle
  2079. * @desc: software Tx descriptor to be processed
  2080. *
  2081. * Return: none
  2082. */
  2083. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2084. struct dp_tx_desc_s *desc)
  2085. {
  2086. struct dp_vdev *vdev = desc->vdev;
  2087. qdf_nbuf_t nbuf = desc->nbuf;
  2088. /* If it is TDLS mgmt, don't unmap or free the frame */
  2089. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2090. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2091. /* 0 : MSDU buffer, 1 : MLE */
  2092. if (desc->msdu_ext_desc) {
  2093. /* TSO free */
  2094. if (hal_tx_ext_desc_get_tso_enable(
  2095. desc->msdu_ext_desc->vaddr)) {
  2096. /* unmap eash TSO seg before free the nbuf */
  2097. dp_tx_tso_unmap_segment(soc, desc);
  2098. qdf_nbuf_free(nbuf);
  2099. return;
  2100. }
  2101. }
  2102. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2103. if (qdf_likely(!vdev->mesh_vdev))
  2104. qdf_nbuf_free(nbuf);
  2105. else {
  2106. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2107. qdf_nbuf_free(nbuf);
  2108. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2109. } else
  2110. vdev->osif_tx_free_ext((nbuf));
  2111. }
  2112. }
  2113. /**
  2114. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2115. * @vdev: pointer to dp dev handler
  2116. * @status : Tx completion status from HTT descriptor
  2117. *
  2118. * Handles MEC notify event sent from fw to Host
  2119. *
  2120. * Return: none
  2121. */
  2122. #ifdef FEATURE_WDS
  2123. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2124. {
  2125. struct dp_soc *soc;
  2126. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2127. struct dp_peer *peer;
  2128. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2129. if (!vdev->wds_enabled)
  2130. return;
  2131. /* MEC required only in STA mode */
  2132. if (vdev->opmode != wlan_op_mode_sta)
  2133. return;
  2134. soc = vdev->pdev->soc;
  2135. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2136. peer = TAILQ_FIRST(&vdev->peer_list);
  2137. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2138. if (!peer) {
  2139. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2140. FL("peer is NULL"));
  2141. return;
  2142. }
  2143. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2144. "%s Tx MEC Handler",
  2145. __func__);
  2146. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2147. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2148. status[(DP_MAC_ADDR_LEN - 2) + i];
  2149. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2150. dp_peer_add_ast(soc,
  2151. peer,
  2152. mac_addr,
  2153. CDP_TXRX_AST_TYPE_MEC,
  2154. flags);
  2155. }
  2156. #endif
  2157. /**
  2158. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2159. * @tx_desc: software descriptor head pointer
  2160. * @status : Tx completion status from HTT descriptor
  2161. *
  2162. * This function will process HTT Tx indication messages from Target
  2163. *
  2164. * Return: none
  2165. */
  2166. static
  2167. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2168. {
  2169. uint8_t tx_status;
  2170. struct dp_pdev *pdev;
  2171. struct dp_vdev *vdev;
  2172. struct dp_soc *soc;
  2173. uint32_t *htt_status_word = (uint32_t *) status;
  2174. qdf_assert(tx_desc->pdev);
  2175. pdev = tx_desc->pdev;
  2176. vdev = tx_desc->vdev;
  2177. soc = pdev->soc;
  2178. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2179. switch (tx_status) {
  2180. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2181. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2182. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2183. {
  2184. dp_tx_comp_free_buf(soc, tx_desc);
  2185. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2186. break;
  2187. }
  2188. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2189. {
  2190. dp_tx_reinject_handler(tx_desc, status);
  2191. break;
  2192. }
  2193. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2194. {
  2195. dp_tx_inspect_handler(tx_desc, status);
  2196. break;
  2197. }
  2198. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2199. {
  2200. dp_tx_mec_handler(vdev, status);
  2201. break;
  2202. }
  2203. default:
  2204. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2205. "%s Invalid HTT tx_status %d",
  2206. __func__, tx_status);
  2207. break;
  2208. }
  2209. }
  2210. #ifdef MESH_MODE_SUPPORT
  2211. /**
  2212. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2213. * in mesh meta header
  2214. * @tx_desc: software descriptor head pointer
  2215. * @ts: pointer to tx completion stats
  2216. * Return: none
  2217. */
  2218. static
  2219. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2220. struct hal_tx_completion_status *ts)
  2221. {
  2222. struct meta_hdr_s *mhdr;
  2223. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2224. if (!tx_desc->msdu_ext_desc) {
  2225. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2227. "netbuf %pK offset %d",
  2228. netbuf, tx_desc->pkt_offset);
  2229. return;
  2230. }
  2231. }
  2232. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2233. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2234. "netbuf %pK offset %d", netbuf,
  2235. sizeof(struct meta_hdr_s));
  2236. return;
  2237. }
  2238. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2239. mhdr->rssi = ts->ack_frame_rssi;
  2240. mhdr->channel = tx_desc->pdev->operating_channel;
  2241. }
  2242. #else
  2243. static
  2244. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2245. struct hal_tx_completion_status *ts)
  2246. {
  2247. }
  2248. #endif
  2249. /**
  2250. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2251. * @peer: Handle to DP peer
  2252. * @ts: pointer to HAL Tx completion stats
  2253. * @length: MSDU length
  2254. *
  2255. * Return: None
  2256. */
  2257. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2258. struct hal_tx_completion_status *ts, uint32_t length)
  2259. {
  2260. struct dp_pdev *pdev = peer->vdev->pdev;
  2261. struct dp_soc *soc = pdev->soc;
  2262. uint8_t mcs, pkt_type;
  2263. mcs = ts->mcs;
  2264. pkt_type = ts->pkt_type;
  2265. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2266. return;
  2267. if (peer->bss_peer) {
  2268. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2269. } else {
  2270. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2271. }
  2272. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2273. DP_STATS_INCC_PKT(peer, tx.tx_success, 1, length,
  2274. (ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  2275. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2276. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2277. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2278. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2279. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2280. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2281. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2282. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2283. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2284. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2285. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2286. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2287. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2288. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2289. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2290. return;
  2291. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2292. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2293. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2294. if (!(soc->process_tx_status))
  2295. return;
  2296. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2297. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2298. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2299. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2300. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2301. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2302. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2303. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2304. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2305. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2306. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2307. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2308. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2309. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2310. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2311. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2312. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2313. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2314. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2315. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2316. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2317. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2318. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2319. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2320. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2321. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2322. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2323. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2324. soc->cdp_soc.ol_ops->update_dp_stats(pdev->ctrl_pdev,
  2325. &peer->stats, ts->peer_id,
  2326. UPDATE_PEER_STATS);
  2327. }
  2328. }
  2329. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2330. /**
  2331. * dp_tx_flow_pool_lock() - take flow pool lock
  2332. * @soc: core txrx main context
  2333. * @tx_desc: tx desc
  2334. *
  2335. * Return: None
  2336. */
  2337. static inline
  2338. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2339. struct dp_tx_desc_s *tx_desc)
  2340. {
  2341. struct dp_tx_desc_pool_s *pool;
  2342. uint8_t desc_pool_id;
  2343. desc_pool_id = tx_desc->pool_id;
  2344. pool = &soc->tx_desc[desc_pool_id];
  2345. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2346. }
  2347. /**
  2348. * dp_tx_flow_pool_unlock() - release flow pool lock
  2349. * @soc: core txrx main context
  2350. * @tx_desc: tx desc
  2351. *
  2352. * Return: None
  2353. */
  2354. static inline
  2355. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2356. struct dp_tx_desc_s *tx_desc)
  2357. {
  2358. struct dp_tx_desc_pool_s *pool;
  2359. uint8_t desc_pool_id;
  2360. desc_pool_id = tx_desc->pool_id;
  2361. pool = &soc->tx_desc[desc_pool_id];
  2362. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2363. }
  2364. #else
  2365. static inline
  2366. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2367. {
  2368. }
  2369. static inline
  2370. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2371. {
  2372. }
  2373. #endif
  2374. /**
  2375. * dp_tx_notify_completion() - Notify tx completion for this desc
  2376. * @soc: core txrx main context
  2377. * @tx_desc: tx desc
  2378. * @netbuf: buffer
  2379. *
  2380. * Return: none
  2381. */
  2382. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2383. struct dp_tx_desc_s *tx_desc,
  2384. qdf_nbuf_t netbuf)
  2385. {
  2386. void *osif_dev;
  2387. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2388. qdf_assert(tx_desc);
  2389. dp_tx_flow_pool_lock(soc, tx_desc);
  2390. if (!tx_desc->vdev ||
  2391. !tx_desc->vdev->osif_vdev) {
  2392. dp_tx_flow_pool_unlock(soc, tx_desc);
  2393. return;
  2394. }
  2395. osif_dev = tx_desc->vdev->osif_vdev;
  2396. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2397. dp_tx_flow_pool_unlock(soc, tx_desc);
  2398. if (tx_compl_cbk)
  2399. tx_compl_cbk(netbuf, osif_dev);
  2400. }
  2401. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2402. * @pdev: pdev handle
  2403. * @tid: tid value
  2404. * @txdesc_ts: timestamp from txdesc
  2405. * @ppdu_id: ppdu id
  2406. *
  2407. * Return: none
  2408. */
  2409. #ifdef FEATURE_PERPKT_INFO
  2410. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2411. uint8_t tid,
  2412. uint64_t txdesc_ts,
  2413. uint32_t ppdu_id)
  2414. {
  2415. uint64_t delta_ms;
  2416. struct cdp_tx_sojourn_stats *sojourn_stats;
  2417. if (pdev->enhanced_stats_en == 0)
  2418. return;
  2419. if (pdev->sojourn_stats.ppdu_seq_id == 0)
  2420. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2421. if (ppdu_id != pdev->sojourn_stats.ppdu_seq_id) {
  2422. if (!pdev->sojourn_buf)
  2423. return;
  2424. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2425. qdf_nbuf_data(pdev->sojourn_buf);
  2426. qdf_mem_copy(sojourn_stats, &pdev->sojourn_stats,
  2427. sizeof(struct cdp_tx_sojourn_stats));
  2428. qdf_mem_zero(&pdev->sojourn_stats,
  2429. sizeof(struct cdp_tx_sojourn_stats));
  2430. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2431. pdev->sojourn_buf, HTT_INVALID_PEER,
  2432. WDI_NO_VAL, pdev->pdev_id);
  2433. pdev->sojourn_stats.ppdu_seq_id = ppdu_id;
  2434. }
  2435. if (tid == HTT_INVALID_TID)
  2436. return;
  2437. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2438. txdesc_ts;
  2439. qdf_ewma_tx_lag_add(&pdev->sojourn_stats.avg_sojourn_msdu[tid],
  2440. delta_ms);
  2441. pdev->sojourn_stats.sum_sojourn_msdu[tid] += delta_ms;
  2442. pdev->sojourn_stats.num_msdus[tid]++;
  2443. }
  2444. #else
  2445. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2446. uint8_t tid,
  2447. uint64_t txdesc_ts,
  2448. uint32_t ppdu_id)
  2449. {
  2450. }
  2451. #endif
  2452. /**
  2453. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2454. * @tx_desc: software descriptor head pointer
  2455. * @length: packet length
  2456. * @peer: peer handle
  2457. *
  2458. * Return: none
  2459. */
  2460. static inline
  2461. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2462. uint32_t length, struct dp_peer *peer)
  2463. {
  2464. struct hal_tx_completion_status ts = {0};
  2465. struct dp_soc *soc = NULL;
  2466. struct dp_vdev *vdev = tx_desc->vdev;
  2467. struct ether_header *eh =
  2468. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2469. if (!vdev) {
  2470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2471. "invalid vdev");
  2472. goto out;
  2473. }
  2474. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  2475. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2476. "-------------------- \n"
  2477. "Tx Completion Stats: \n"
  2478. "-------------------- \n"
  2479. "ack_frame_rssi = %d \n"
  2480. "first_msdu = %d \n"
  2481. "last_msdu = %d \n"
  2482. "msdu_part_of_amsdu = %d \n"
  2483. "rate_stats valid = %d \n"
  2484. "bw = %d \n"
  2485. "pkt_type = %d \n"
  2486. "stbc = %d \n"
  2487. "ldpc = %d \n"
  2488. "sgi = %d \n"
  2489. "mcs = %d \n"
  2490. "ofdma = %d \n"
  2491. "tones_in_ru = %d \n"
  2492. "tsf = %d \n"
  2493. "ppdu_id = %d \n"
  2494. "transmit_cnt = %d \n"
  2495. "tid = %d \n"
  2496. "peer_id = %d ",
  2497. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2498. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2499. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2500. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2501. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2502. ts.peer_id);
  2503. soc = vdev->pdev->soc;
  2504. /* Update SoC level stats */
  2505. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2506. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2507. /* Update per-packet stats */
  2508. if (qdf_unlikely(vdev->mesh_vdev) &&
  2509. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2510. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2511. /* Update peer level stats */
  2512. if (!peer) {
  2513. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2514. "invalid peer");
  2515. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2516. goto out;
  2517. }
  2518. if (qdf_likely(peer->vdev->tx_encap_type ==
  2519. htt_cmn_pkt_type_ethernet)) {
  2520. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2521. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2522. }
  2523. dp_tx_sojourn_stats_process(vdev->pdev, ts.tid,
  2524. tx_desc->timestamp,
  2525. ts.ppdu_id);
  2526. dp_tx_update_peer_stats(peer, &ts, length);
  2527. out:
  2528. return;
  2529. }
  2530. /**
  2531. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2532. * @soc: core txrx main context
  2533. * @comp_head: software descriptor head pointer
  2534. *
  2535. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2536. * and release the software descriptors after processing is complete
  2537. *
  2538. * Return: none
  2539. */
  2540. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2541. struct dp_tx_desc_s *comp_head)
  2542. {
  2543. struct dp_tx_desc_s *desc;
  2544. struct dp_tx_desc_s *next;
  2545. struct hal_tx_completion_status ts = {0};
  2546. uint32_t length;
  2547. struct dp_peer *peer;
  2548. DP_HIST_INIT();
  2549. desc = comp_head;
  2550. while (desc) {
  2551. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2552. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2553. length = qdf_nbuf_len(desc->nbuf);
  2554. /* check tx completion notification */
  2555. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(desc->nbuf))
  2556. dp_tx_notify_completion(soc, desc, desc->nbuf);
  2557. dp_tx_comp_process_tx_status(desc, length, peer);
  2558. DPTRACE(qdf_dp_trace_ptr
  2559. (desc->nbuf,
  2560. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2561. QDF_TRACE_DEFAULT_PDEV_ID,
  2562. qdf_nbuf_data_addr(desc->nbuf),
  2563. sizeof(qdf_nbuf_data(desc->nbuf)),
  2564. desc->id, ts.status)
  2565. );
  2566. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2567. if (!(desc->msdu_ext_desc) &&
  2568. (dp_get_completion_indication_for_stack(soc, desc->pdev,
  2569. peer, ts.peer_id, ts.ppdu_id,
  2570. ts.first_msdu, ts.last_msdu,
  2571. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2572. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2573. QDF_DMA_TO_DEVICE);
  2574. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2575. ts.ppdu_id, desc->nbuf);
  2576. } else {
  2577. dp_tx_comp_free_buf(soc, desc);
  2578. }
  2579. if (peer)
  2580. dp_peer_unref_del_find_by_id(peer);
  2581. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2582. next = desc->next;
  2583. dp_tx_desc_release(desc, desc->pool_id);
  2584. desc = next;
  2585. }
  2586. DP_TX_HIST_STATS_PER_PDEV();
  2587. }
  2588. /**
  2589. * dp_tx_comp_handler() - Tx completion handler
  2590. * @soc: core txrx main context
  2591. * @ring_id: completion ring id
  2592. * @quota: No. of packets/descriptors that can be serviced in one loop
  2593. *
  2594. * This function will collect hardware release ring element contents and
  2595. * handle descriptor contents. Based on contents, free packet or handle error
  2596. * conditions
  2597. *
  2598. * Return: none
  2599. */
  2600. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2601. {
  2602. void *tx_comp_hal_desc;
  2603. uint8_t buffer_src;
  2604. uint8_t pool_id;
  2605. uint32_t tx_desc_id;
  2606. struct dp_tx_desc_s *tx_desc = NULL;
  2607. struct dp_tx_desc_s *head_desc = NULL;
  2608. struct dp_tx_desc_s *tail_desc = NULL;
  2609. uint32_t num_processed;
  2610. uint32_t count;
  2611. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2612. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2613. "%s %d : HAL RING Access Failed -- %pK",
  2614. __func__, __LINE__, hal_srng);
  2615. return 0;
  2616. }
  2617. num_processed = 0;
  2618. count = 0;
  2619. /* Find head descriptor from completion ring */
  2620. while (qdf_likely(tx_comp_hal_desc =
  2621. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2622. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2623. /* If this buffer was not released by TQM or FW, then it is not
  2624. * Tx completion indication, assert */
  2625. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2626. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2627. QDF_TRACE(QDF_MODULE_ID_DP,
  2628. QDF_TRACE_LEVEL_FATAL,
  2629. "Tx comp release_src != TQM | FW");
  2630. qdf_assert_always(0);
  2631. }
  2632. /* Get descriptor id */
  2633. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2634. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2635. DP_TX_DESC_ID_POOL_OS;
  2636. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2637. continue;
  2638. /* Find Tx descriptor */
  2639. tx_desc = dp_tx_desc_find(soc, pool_id,
  2640. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2641. DP_TX_DESC_ID_PAGE_OS,
  2642. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2643. DP_TX_DESC_ID_OFFSET_OS);
  2644. /*
  2645. * If the release source is FW, process the HTT status
  2646. */
  2647. if (qdf_unlikely(buffer_src ==
  2648. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2649. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2650. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2651. htt_tx_status);
  2652. dp_tx_process_htt_completion(tx_desc,
  2653. htt_tx_status);
  2654. } else {
  2655. /* Pool id is not matching. Error */
  2656. if (tx_desc->pool_id != pool_id) {
  2657. QDF_TRACE(QDF_MODULE_ID_DP,
  2658. QDF_TRACE_LEVEL_FATAL,
  2659. "Tx Comp pool id %d not matched %d",
  2660. pool_id, tx_desc->pool_id);
  2661. qdf_assert_always(0);
  2662. }
  2663. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2664. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2665. QDF_TRACE(QDF_MODULE_ID_DP,
  2666. QDF_TRACE_LEVEL_FATAL,
  2667. "Txdesc invalid, flgs = %x,id = %d",
  2668. tx_desc->flags, tx_desc_id);
  2669. qdf_assert_always(0);
  2670. }
  2671. /* First ring descriptor on the cycle */
  2672. if (!head_desc) {
  2673. head_desc = tx_desc;
  2674. tail_desc = tx_desc;
  2675. }
  2676. tail_desc->next = tx_desc;
  2677. tx_desc->next = NULL;
  2678. tail_desc = tx_desc;
  2679. /* Collect hw completion contents */
  2680. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2681. &tx_desc->comp, 1);
  2682. }
  2683. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2684. /*
  2685. * Processed packet count is more than given quota
  2686. * stop to processing
  2687. */
  2688. if ((num_processed >= quota))
  2689. break;
  2690. count++;
  2691. }
  2692. hal_srng_access_end(soc->hal_soc, hal_srng);
  2693. /* Process the reaped descriptors */
  2694. if (head_desc)
  2695. dp_tx_comp_process_desc(soc, head_desc);
  2696. return num_processed;
  2697. }
  2698. #ifdef CONVERGED_TDLS_ENABLE
  2699. /**
  2700. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2701. *
  2702. * @data_vdev - which vdev should transmit the tx data frames
  2703. * @tx_spec - what non-standard handling to apply to the tx data frames
  2704. * @msdu_list - NULL-terminated list of tx MSDUs
  2705. *
  2706. * Return: NULL on success,
  2707. * nbuf when it fails to send
  2708. */
  2709. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2710. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2711. {
  2712. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2713. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2714. vdev->is_tdls_frame = true;
  2715. return dp_tx_send(vdev_handle, msdu_list);
  2716. }
  2717. #endif
  2718. /**
  2719. * dp_tx_vdev_attach() - attach vdev to dp tx
  2720. * @vdev: virtual device instance
  2721. *
  2722. * Return: QDF_STATUS_SUCCESS: success
  2723. * QDF_STATUS_E_RESOURCES: Error return
  2724. */
  2725. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2726. {
  2727. /*
  2728. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2729. */
  2730. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2731. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2732. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2733. vdev->vdev_id);
  2734. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2735. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2736. /*
  2737. * Set HTT Extension Valid bit to 0 by default
  2738. */
  2739. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2740. dp_tx_vdev_update_search_flags(vdev);
  2741. return QDF_STATUS_SUCCESS;
  2742. }
  2743. /**
  2744. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2745. * @vdev: virtual device instance
  2746. *
  2747. * Return: void
  2748. *
  2749. */
  2750. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2751. {
  2752. struct dp_soc *soc = vdev->pdev->soc;
  2753. /*
  2754. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2755. * for TDLS link
  2756. *
  2757. * Enable AddrY (SA based search) only for non-WDS STA and
  2758. * ProxySTA VAP modes.
  2759. *
  2760. * In all other VAP modes, only DA based search should be
  2761. * enabled
  2762. */
  2763. if (vdev->opmode == wlan_op_mode_sta &&
  2764. vdev->tdls_link_connected)
  2765. vdev->hal_desc_addr_search_flags =
  2766. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2767. else if ((vdev->opmode == wlan_op_mode_sta &&
  2768. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2769. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2770. else
  2771. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2772. /* Set search type only when peer map v2 messaging is enabled
  2773. * as we will have the search index (AST hash) only when v2 is
  2774. * enabled
  2775. */
  2776. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  2777. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  2778. else
  2779. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  2780. }
  2781. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2782. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2783. {
  2784. }
  2785. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2786. /* dp_tx_desc_flush() - release resources associated
  2787. * to tx_desc
  2788. * @vdev: virtual device instance
  2789. *
  2790. * This function will free all outstanding Tx buffers,
  2791. * including ME buffer for which either free during
  2792. * completion didn't happened or completion is not
  2793. * received.
  2794. */
  2795. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2796. {
  2797. uint8_t i, num_pool;
  2798. uint32_t j;
  2799. uint32_t num_desc;
  2800. struct dp_soc *soc = vdev->pdev->soc;
  2801. struct dp_tx_desc_s *tx_desc = NULL;
  2802. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2803. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2804. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2805. for (i = 0; i < num_pool; i++) {
  2806. for (j = 0; j < num_desc; j++) {
  2807. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2808. if (tx_desc_pool &&
  2809. tx_desc_pool->desc_pages.cacheable_pages) {
  2810. tx_desc = dp_tx_desc_find(soc, i,
  2811. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2812. DP_TX_DESC_ID_PAGE_OS,
  2813. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2814. DP_TX_DESC_ID_OFFSET_OS);
  2815. if (tx_desc && (tx_desc->vdev == vdev) &&
  2816. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2817. dp_tx_comp_free_buf(soc, tx_desc);
  2818. dp_tx_desc_release(tx_desc, i);
  2819. }
  2820. }
  2821. }
  2822. }
  2823. }
  2824. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2825. /**
  2826. * dp_tx_vdev_detach() - detach vdev from dp tx
  2827. * @vdev: virtual device instance
  2828. *
  2829. * Return: QDF_STATUS_SUCCESS: success
  2830. * QDF_STATUS_E_RESOURCES: Error return
  2831. */
  2832. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2833. {
  2834. dp_tx_desc_flush(vdev);
  2835. return QDF_STATUS_SUCCESS;
  2836. }
  2837. /**
  2838. * dp_tx_pdev_attach() - attach pdev to dp tx
  2839. * @pdev: physical device instance
  2840. *
  2841. * Return: QDF_STATUS_SUCCESS: success
  2842. * QDF_STATUS_E_RESOURCES: Error return
  2843. */
  2844. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2845. {
  2846. struct dp_soc *soc = pdev->soc;
  2847. /* Initialize Flow control counters */
  2848. qdf_atomic_init(&pdev->num_tx_exception);
  2849. qdf_atomic_init(&pdev->num_tx_outstanding);
  2850. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2851. /* Initialize descriptors in TCL Ring */
  2852. hal_tx_init_data_ring(soc->hal_soc,
  2853. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2854. }
  2855. return QDF_STATUS_SUCCESS;
  2856. }
  2857. /**
  2858. * dp_tx_pdev_detach() - detach pdev from dp tx
  2859. * @pdev: physical device instance
  2860. *
  2861. * Return: QDF_STATUS_SUCCESS: success
  2862. * QDF_STATUS_E_RESOURCES: Error return
  2863. */
  2864. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2865. {
  2866. dp_tx_me_exit(pdev);
  2867. return QDF_STATUS_SUCCESS;
  2868. }
  2869. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2870. /* Pools will be allocated dynamically */
  2871. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2872. int num_desc)
  2873. {
  2874. uint8_t i;
  2875. for (i = 0; i < num_pool; i++) {
  2876. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2877. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2878. }
  2879. return 0;
  2880. }
  2881. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2882. {
  2883. uint8_t i;
  2884. for (i = 0; i < num_pool; i++)
  2885. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2886. }
  2887. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2888. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2889. int num_desc)
  2890. {
  2891. uint8_t i;
  2892. /* Allocate software Tx descriptor pools */
  2893. for (i = 0; i < num_pool; i++) {
  2894. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2896. "%s Tx Desc Pool alloc %d failed %pK",
  2897. __func__, i, soc);
  2898. return ENOMEM;
  2899. }
  2900. }
  2901. return 0;
  2902. }
  2903. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2904. {
  2905. uint8_t i;
  2906. for (i = 0; i < num_pool; i++) {
  2907. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2908. if (dp_tx_desc_pool_free(soc, i)) {
  2909. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2910. "%s Tx Desc Pool Free failed", __func__);
  2911. }
  2912. }
  2913. }
  2914. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2915. /**
  2916. * dp_tx_soc_detach() - detach soc from dp tx
  2917. * @soc: core txrx main context
  2918. *
  2919. * This function will detach dp tx into main device context
  2920. * will free dp tx resource and initialize resources
  2921. *
  2922. * Return: QDF_STATUS_SUCCESS: success
  2923. * QDF_STATUS_E_RESOURCES: Error return
  2924. */
  2925. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2926. {
  2927. uint8_t num_pool;
  2928. uint16_t num_desc;
  2929. uint16_t num_ext_desc;
  2930. uint8_t i;
  2931. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2932. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2933. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2934. dp_tx_flow_control_deinit(soc);
  2935. dp_tx_delete_static_pools(soc, num_pool);
  2936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2937. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  2938. __func__, num_pool, num_desc);
  2939. for (i = 0; i < num_pool; i++) {
  2940. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2941. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2942. "%s Tx Ext Desc Pool Free failed",
  2943. __func__);
  2944. return QDF_STATUS_E_RESOURCES;
  2945. }
  2946. }
  2947. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2948. "%s MSDU Ext Desc Pool %d Free descs = %d",
  2949. __func__, num_pool, num_ext_desc);
  2950. for (i = 0; i < num_pool; i++) {
  2951. dp_tx_tso_desc_pool_free(soc, i);
  2952. }
  2953. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2954. "%s TSO Desc Pool %d Free descs = %d",
  2955. __func__, num_pool, num_desc);
  2956. for (i = 0; i < num_pool; i++)
  2957. dp_tx_tso_num_seg_pool_free(soc, i);
  2958. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2959. "%s TSO Num of seg Desc Pool %d Free descs = %d",
  2960. __func__, num_pool, num_desc);
  2961. return QDF_STATUS_SUCCESS;
  2962. }
  2963. /**
  2964. * dp_tx_soc_attach() - attach soc to dp tx
  2965. * @soc: core txrx main context
  2966. *
  2967. * This function will attach dp tx into main device context
  2968. * will allocate dp tx resource and initialize resources
  2969. *
  2970. * Return: QDF_STATUS_SUCCESS: success
  2971. * QDF_STATUS_E_RESOURCES: Error return
  2972. */
  2973. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2974. {
  2975. uint8_t i;
  2976. uint8_t num_pool;
  2977. uint32_t num_desc;
  2978. uint32_t num_ext_desc;
  2979. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2980. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2981. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2982. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2983. goto fail;
  2984. dp_tx_flow_control_init(soc);
  2985. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2986. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  2987. __func__, num_pool, num_desc);
  2988. /* Allocate extension tx descriptor pools */
  2989. for (i = 0; i < num_pool; i++) {
  2990. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2991. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2992. "MSDU Ext Desc Pool alloc %d failed %pK",
  2993. i, soc);
  2994. goto fail;
  2995. }
  2996. }
  2997. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2998. "%s MSDU Ext Desc Alloc %d, descs = %d",
  2999. __func__, num_pool, num_ext_desc);
  3000. for (i = 0; i < num_pool; i++) {
  3001. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3002. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3003. "TSO Desc Pool alloc %d failed %pK",
  3004. i, soc);
  3005. goto fail;
  3006. }
  3007. }
  3008. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3009. "%s TSO Desc Alloc %d, descs = %d",
  3010. __func__, num_pool, num_desc);
  3011. for (i = 0; i < num_pool; i++) {
  3012. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3013. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3014. "TSO Num of seg Pool alloc %d failed %pK",
  3015. i, soc);
  3016. goto fail;
  3017. }
  3018. }
  3019. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3020. "%s TSO Num of seg pool Alloc %d, descs = %d",
  3021. __func__, num_pool, num_desc);
  3022. /* Initialize descriptors in TCL Rings */
  3023. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3024. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3025. hal_tx_init_data_ring(soc->hal_soc,
  3026. soc->tcl_data_ring[i].hal_srng);
  3027. }
  3028. }
  3029. /*
  3030. * todo - Add a runtime config option to enable this.
  3031. */
  3032. /*
  3033. * Due to multiple issues on NPR EMU, enable it selectively
  3034. * only for NPR EMU, should be removed, once NPR platforms
  3035. * are stable.
  3036. */
  3037. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3038. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3039. "%s HAL Tx init Success", __func__);
  3040. return QDF_STATUS_SUCCESS;
  3041. fail:
  3042. /* Detach will take care of freeing only allocated resources */
  3043. dp_tx_soc_detach(soc);
  3044. return QDF_STATUS_E_RESOURCES;
  3045. }
  3046. /*
  3047. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  3048. * pdev: pointer to DP PDEV structure
  3049. * seg_info_head: Pointer to the head of list
  3050. *
  3051. * return: void
  3052. */
  3053. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  3054. struct dp_tx_seg_info_s *seg_info_head)
  3055. {
  3056. struct dp_tx_me_buf_t *mc_uc_buf;
  3057. struct dp_tx_seg_info_s *seg_info_new = NULL;
  3058. qdf_nbuf_t nbuf = NULL;
  3059. uint64_t phy_addr;
  3060. while (seg_info_head) {
  3061. nbuf = seg_info_head->nbuf;
  3062. mc_uc_buf = (struct dp_tx_me_buf_t *)
  3063. seg_info_head->frags[0].vaddr;
  3064. phy_addr = seg_info_head->frags[0].paddr_hi;
  3065. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  3066. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  3067. phy_addr,
  3068. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  3069. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3070. qdf_nbuf_free(nbuf);
  3071. seg_info_new = seg_info_head;
  3072. seg_info_head = seg_info_head->next;
  3073. qdf_mem_free(seg_info_new);
  3074. }
  3075. }
  3076. /**
  3077. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  3078. * @vdev: DP VDEV handle
  3079. * @nbuf: Multicast nbuf
  3080. * @newmac: Table of the clients to which packets have to be sent
  3081. * @new_mac_cnt: No of clients
  3082. *
  3083. * return: no of converted packets
  3084. */
  3085. uint16_t
  3086. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  3087. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3088. {
  3089. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3090. struct dp_pdev *pdev = vdev->pdev;
  3091. struct ether_header *eh;
  3092. uint8_t *data;
  3093. uint16_t len;
  3094. /* reference to frame dst addr */
  3095. uint8_t *dstmac;
  3096. /* copy of original frame src addr */
  3097. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3098. /* local index into newmac */
  3099. uint8_t new_mac_idx = 0;
  3100. struct dp_tx_me_buf_t *mc_uc_buf;
  3101. qdf_nbuf_t nbuf_clone;
  3102. struct dp_tx_msdu_info_s msdu_info;
  3103. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3104. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3105. struct dp_tx_seg_info_s *seg_info_new;
  3106. struct dp_tx_frag_info_s data_frag;
  3107. qdf_dma_addr_t paddr_data;
  3108. qdf_dma_addr_t paddr_mcbuf = 0;
  3109. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3110. QDF_STATUS status;
  3111. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3112. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3113. eh = (struct ether_header *) nbuf;
  3114. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3115. len = qdf_nbuf_len(nbuf);
  3116. data = qdf_nbuf_data(nbuf);
  3117. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3118. QDF_DMA_TO_DEVICE);
  3119. if (status) {
  3120. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3121. "Mapping failure Error:%d", status);
  3122. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3123. qdf_nbuf_free(nbuf);
  3124. return 1;
  3125. }
  3126. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3127. /*preparing data fragment*/
  3128. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3129. data_frag.paddr_lo = (uint32_t)paddr_data;
  3130. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3131. data_frag.len = len - DP_MAC_ADDR_LEN;
  3132. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3133. dstmac = newmac[new_mac_idx];
  3134. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3135. "added mac addr (%pM)", dstmac);
  3136. /* Check for NULL Mac Address */
  3137. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3138. continue;
  3139. /* frame to self mac. skip */
  3140. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3141. continue;
  3142. /*
  3143. * TODO: optimize to avoid malloc in per-packet path
  3144. * For eg. seg_pool can be made part of vdev structure
  3145. */
  3146. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3147. if (!seg_info_new) {
  3148. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3149. "alloc failed");
  3150. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3151. goto fail_seg_alloc;
  3152. }
  3153. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3154. if (mc_uc_buf == NULL)
  3155. goto fail_buf_alloc;
  3156. /*
  3157. * TODO: Check if we need to clone the nbuf
  3158. * Or can we just use the reference for all cases
  3159. */
  3160. if (new_mac_idx < (new_mac_cnt - 1)) {
  3161. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3162. if (nbuf_clone == NULL) {
  3163. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3164. goto fail_clone;
  3165. }
  3166. } else {
  3167. /*
  3168. * Update the ref
  3169. * to account for frame sent without cloning
  3170. */
  3171. qdf_nbuf_ref(nbuf);
  3172. nbuf_clone = nbuf;
  3173. }
  3174. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3175. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3176. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3177. &paddr_mcbuf);
  3178. if (status) {
  3179. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3180. "Mapping failure Error:%d", status);
  3181. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3182. goto fail_map;
  3183. }
  3184. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3185. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3186. seg_info_new->frags[0].paddr_hi =
  3187. ((uint64_t) paddr_mcbuf >> 32);
  3188. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3189. seg_info_new->frags[1] = data_frag;
  3190. seg_info_new->nbuf = nbuf_clone;
  3191. seg_info_new->frag_cnt = 2;
  3192. seg_info_new->total_len = len;
  3193. seg_info_new->next = NULL;
  3194. if (seg_info_head == NULL)
  3195. seg_info_head = seg_info_new;
  3196. else
  3197. seg_info_tail->next = seg_info_new;
  3198. seg_info_tail = seg_info_new;
  3199. }
  3200. if (!seg_info_head) {
  3201. goto free_return;
  3202. }
  3203. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3204. msdu_info.num_seg = new_mac_cnt;
  3205. msdu_info.frm_type = dp_tx_frm_me;
  3206. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3207. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3208. while (seg_info_head->next) {
  3209. seg_info_new = seg_info_head;
  3210. seg_info_head = seg_info_head->next;
  3211. qdf_mem_free(seg_info_new);
  3212. }
  3213. qdf_mem_free(seg_info_head);
  3214. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3215. qdf_nbuf_free(nbuf);
  3216. return new_mac_cnt;
  3217. fail_map:
  3218. qdf_nbuf_free(nbuf_clone);
  3219. fail_clone:
  3220. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3221. fail_buf_alloc:
  3222. qdf_mem_free(seg_info_new);
  3223. fail_seg_alloc:
  3224. dp_tx_me_mem_free(pdev, seg_info_head);
  3225. free_return:
  3226. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3227. qdf_nbuf_free(nbuf);
  3228. return 1;
  3229. }