wcd937x.c 99 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <linux/regmap.h>
  14. #include <linux/pm_runtime.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include <soc/soundwire.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <asoc/wcdcal-hwdep.h>
  21. #include <asoc/msm-cdc-pinctrl.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <asoc/msm-cdc-supply.h>
  24. #include "wcd937x-registers.h"
  25. #include "wcd937x.h"
  26. #include "internal.h"
  27. #include "asoc/bolero-slave-internal.h"
  28. #define WCD9370_VARIANT 0
  29. #define WCD9375_VARIANT 5
  30. #define WCD937X_VARIANT_ENTRY_SIZE 32
  31. #define NUM_SWRS_DT_PARAMS 5
  32. #define WCD937X_VERSION_1_0 1
  33. #define WCD937X_VERSION_ENTRY_SIZE 32
  34. #define EAR_RX_PATH_AUX 1
  35. #define NUM_ATTEMPTS 5
  36. #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  37. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  38. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  39. SNDRV_PCM_RATE_384000)
  40. /* Fractional Rates */
  41. #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  42. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  43. #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  44. SNDRV_PCM_FMTBIT_S24_LE |\
  45. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  46. enum {
  47. CODEC_TX = 0,
  48. CODEC_RX,
  49. };
  50. enum {
  51. ALLOW_BUCK_DISABLE,
  52. HPH_COMP_DELAY,
  53. HPH_PA_DELAY,
  54. AMIC2_BCS_ENABLE,
  55. };
  56. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  57. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  58. static int wcd937x_handle_post_irq(void *data);
  59. static int wcd937x_reset(struct device *dev);
  60. static int wcd937x_reset_low(struct device *dev);
  61. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  62. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  71. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  72. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  73. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  74. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  75. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  76. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  77. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  78. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  79. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  80. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  81. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  82. };
  83. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  84. .name = "wcd937x",
  85. .irqs = wcd937x_irqs,
  86. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  87. .num_regs = 3,
  88. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  89. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  90. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  91. .use_ack = 1,
  92. //#if IS_ENABLED(CONFIG_AUDIO_QGKI)
  93. .clear_ack = 1,
  94. //#endif
  95. .mask_writeonly = 1,
  96. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  97. .runtime_pm = false,
  98. .handle_post_irq = wcd937x_handle_post_irq,
  99. .irq_drv_data = NULL,
  100. };
  101. static struct snd_soc_dai_driver wcd937x_dai[] = {
  102. {
  103. .name = "wcd937x_cdc",
  104. .playback = {
  105. .stream_name = "WCD937X_AIF Playback",
  106. .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
  107. .formats = WCD937X_FORMATS,
  108. .rate_max = 384000,
  109. .rate_min = 8000,
  110. .channels_min = 1,
  111. .channels_max = 4,
  112. },
  113. .capture = {
  114. .stream_name = "WCD937X_AIF Capture",
  115. .rates = WCD937X_RATES,
  116. .formats = WCD937X_FORMATS,
  117. .rate_max = 192000,
  118. .rate_min = 8000,
  119. .channels_min = 1,
  120. .channels_max = 4,
  121. },
  122. },
  123. };
  124. static int wcd937x_handle_post_irq(void *data)
  125. {
  126. struct wcd937x_priv *wcd937x = data;
  127. u32 status1 = 0, status2 = 0, status3 = 0;
  128. /* Clear the ACK registers. Temporary workaround.*/
  129. regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0x0);
  130. regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0x0);
  131. regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0x0);
  132. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  133. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  134. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  135. wcd937x->tx_swr_dev->slave_irq_pending =
  136. ((status1 || status2 || status3) ? true : false);
  137. return IRQ_HANDLED;
  138. }
  139. static int wcd937x_init_reg(struct snd_soc_component *component)
  140. {
  141. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  142. 0x0E, 0x0E);
  143. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  144. 0x80, 0x80);
  145. usleep_range(1000, 1010);
  146. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  147. 0x40, 0x40);
  148. usleep_range(1000, 1010);
  149. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  150. 0x10, 0x00);
  151. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  152. 0xF0, 0x80);
  153. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  154. 0x80, 0x80);
  155. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  156. 0x40, 0x40);
  157. usleep_range(10000, 10010);
  158. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  159. 0x40, 0x00);
  160. snd_soc_component_update_bits(component,
  161. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  162. 0xFF, 0xD9);
  163. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  164. 0xFF, 0xFA);
  165. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  166. 0xFF, 0xFA);
  167. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  168. 0xFF, 0xFA);
  169. return 0;
  170. }
  171. static int wcd937x_set_port_params(struct snd_soc_component *component,
  172. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  173. u8 *ch_mask, u32 *ch_rate,
  174. u8 *port_type, u8 path)
  175. {
  176. int i, j;
  177. u8 num_ports = 0;
  178. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  179. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  180. switch (path) {
  181. case CODEC_RX:
  182. map = &wcd937x->rx_port_mapping;
  183. num_ports = wcd937x->num_rx_ports;
  184. break;
  185. case CODEC_TX:
  186. map = &wcd937x->tx_port_mapping;
  187. num_ports = wcd937x->num_tx_ports;
  188. break;
  189. default:
  190. dev_err(component->dev, "%s Invalid path selected %u\n",
  191. __func__, path);
  192. return -EINVAL;
  193. }
  194. for (i = 0; i <= num_ports; i++) {
  195. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  196. if ((*map)[i][j].slave_port_type == slv_prt_type)
  197. goto found;
  198. }
  199. }
  200. found:
  201. if (i > num_ports || j == MAX_CH_PER_PORT) {
  202. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  203. __func__, slv_prt_type);
  204. return -EINVAL;
  205. }
  206. *port_id = i;
  207. *num_ch = (*map)[i][j].num_ch;
  208. *ch_mask = (*map)[i][j].ch_mask;
  209. *ch_rate = (*map)[i][j].ch_rate;
  210. *port_type = (*map)[i][j].master_port_type;
  211. return 0;
  212. }
  213. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  214. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  215. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  216. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  217. static int wcd937x_parse_port_params(struct device *dev,
  218. char *prop, u8 path)
  219. {
  220. u32 *dt_array, map_size, max_uc;
  221. int ret = 0;
  222. u32 cnt = 0;
  223. u32 i, j;
  224. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  225. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  226. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  227. switch (path) {
  228. case CODEC_TX:
  229. map = &wcd937x->tx_port_params;
  230. map_uc = &wcd937x->swr_tx_port_params;
  231. break;
  232. default:
  233. ret = -EINVAL;
  234. goto err_port_map;
  235. }
  236. if (!of_find_property(dev->of_node, prop,
  237. &map_size)) {
  238. dev_err(dev, "missing port mapping prop %s\n", prop);
  239. ret = -EINVAL;
  240. goto err_port_map;
  241. }
  242. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  243. if (max_uc != SWR_UC_MAX) {
  244. dev_err(dev, "%s: port params not provided for all usecases\n",
  245. __func__);
  246. ret = -EINVAL;
  247. goto err_port_map;
  248. }
  249. dt_array = kzalloc(map_size, GFP_KERNEL);
  250. if (!dt_array) {
  251. ret = -ENOMEM;
  252. goto err_alloc;
  253. }
  254. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  255. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  256. if (ret) {
  257. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  258. __func__, prop);
  259. goto err_pdata_fail;
  260. }
  261. for (i = 0; i < max_uc; i++) {
  262. for (j = 0; j < SWR_NUM_PORTS; j++) {
  263. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  264. (*map)[i][j].offset1 = dt_array[cnt];
  265. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  266. }
  267. (*map_uc)[i].pp = &(*map)[i][0];
  268. }
  269. kfree(dt_array);
  270. return 0;
  271. err_pdata_fail:
  272. kfree(dt_array);
  273. err_alloc:
  274. err_port_map:
  275. return ret;
  276. }
  277. static int wcd937x_parse_port_mapping(struct device *dev,
  278. char *prop, u8 path)
  279. {
  280. u32 *dt_array, map_size, map_length;
  281. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  282. u32 slave_port_type, master_port_type;
  283. u32 i, ch_iter = 0;
  284. int ret = 0;
  285. u8 *num_ports = NULL;
  286. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  287. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  288. switch (path) {
  289. case CODEC_RX:
  290. map = &wcd937x->rx_port_mapping;
  291. num_ports = &wcd937x->num_rx_ports;
  292. break;
  293. case CODEC_TX:
  294. map = &wcd937x->tx_port_mapping;
  295. num_ports = &wcd937x->num_tx_ports;
  296. break;
  297. default:
  298. dev_err(dev, "%s Invalid path selected %u\n",
  299. __func__, path);
  300. return -EINVAL;
  301. }
  302. if (!of_find_property(dev->of_node, prop,
  303. &map_size)) {
  304. dev_err(dev, "missing port mapping prop %s\n", prop);
  305. ret = -EINVAL;
  306. goto err;
  307. }
  308. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  309. dt_array = kzalloc(map_size, GFP_KERNEL);
  310. if (!dt_array) {
  311. ret = -ENOMEM;
  312. goto err;
  313. }
  314. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  315. NUM_SWRS_DT_PARAMS * map_length);
  316. if (ret) {
  317. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  318. __func__, prop);
  319. ret = -EINVAL;
  320. goto err_pdata_fail;
  321. }
  322. for (i = 0; i < map_length; i++) {
  323. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  324. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  325. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  326. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  327. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  328. if (port_num != old_port_num)
  329. ch_iter = 0;
  330. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  331. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  332. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  333. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  334. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  335. old_port_num = port_num;
  336. }
  337. *num_ports = port_num;
  338. kfree(dt_array);
  339. return 0;
  340. err_pdata_fail:
  341. kfree(dt_array);
  342. err:
  343. return ret;
  344. }
  345. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  346. u8 slv_port_type, u8 enable)
  347. {
  348. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  349. u8 port_id;
  350. u8 num_ch;
  351. u8 ch_mask;
  352. u32 ch_rate;
  353. u8 ch_type = 0;
  354. int slave_ch_idx;
  355. u8 num_port = 1;
  356. int ret = 0;
  357. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  358. &num_ch, &ch_mask, &ch_rate,
  359. &ch_type, CODEC_TX);
  360. if (ret)
  361. return ret;
  362. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  363. if (slave_ch_idx != -EINVAL)
  364. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  365. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  366. __func__, slave_ch_idx, ch_type);
  367. if (enable)
  368. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  369. num_port, &ch_mask, &ch_rate,
  370. &num_ch, &ch_type);
  371. else
  372. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  373. num_port, &ch_mask, &ch_type);
  374. return ret;
  375. }
  376. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  377. u8 slv_port_type, u8 enable)
  378. {
  379. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  380. u8 port_id;
  381. u8 num_ch;
  382. u8 ch_mask;
  383. u32 ch_rate;
  384. u8 port_type;
  385. u8 num_port = 1;
  386. int ret = 0;
  387. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  388. &num_ch, &ch_mask, &ch_rate,
  389. &port_type, CODEC_RX);
  390. if (ret)
  391. return ret;
  392. if (enable)
  393. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  394. num_port, &ch_mask, &ch_rate,
  395. &num_ch, &port_type);
  396. else
  397. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  398. num_port, &ch_mask, &port_type);
  399. return ret;
  400. }
  401. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  402. {
  403. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  404. if (wcd937x->rx_clk_cnt == 0) {
  405. snd_soc_component_update_bits(component,
  406. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  407. snd_soc_component_update_bits(component,
  408. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  409. snd_soc_component_update_bits(component,
  410. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  411. snd_soc_component_update_bits(component,
  412. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  413. snd_soc_component_update_bits(component,
  414. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  415. snd_soc_component_update_bits(component,
  416. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  417. snd_soc_component_update_bits(component,
  418. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  419. }
  420. wcd937x->rx_clk_cnt++;
  421. return 0;
  422. }
  423. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  424. {
  425. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  426. if (wcd937x->rx_clk_cnt == 0) {
  427. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  428. return 0;
  429. }
  430. wcd937x->rx_clk_cnt--;
  431. if (wcd937x->rx_clk_cnt == 0) {
  432. snd_soc_component_update_bits(component,
  433. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  434. snd_soc_component_update_bits(component,
  435. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  436. 0x02, 0x00);
  437. snd_soc_component_update_bits(component,
  438. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  439. 0x01, 0x00);
  440. }
  441. return 0;
  442. }
  443. /*
  444. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  445. * @component: handle to snd_soc_component *
  446. *
  447. * return wcd937x_mbhc handle or error code in case of failure
  448. */
  449. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  450. {
  451. struct wcd937x_priv *wcd937x;
  452. if (!component) {
  453. pr_err("%s: Invalid params, NULL component\n", __func__);
  454. return NULL;
  455. }
  456. wcd937x = snd_soc_component_get_drvdata(component);
  457. if (!wcd937x) {
  458. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  459. return NULL;
  460. }
  461. return wcd937x->mbhc;
  462. }
  463. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  464. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  465. struct snd_kcontrol *kcontrol,
  466. int event)
  467. {
  468. struct snd_soc_component *component =
  469. snd_soc_dapm_to_component(w->dapm);
  470. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  471. int hph_mode = wcd937x->hph_mode;
  472. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  473. w->name, event);
  474. switch (event) {
  475. case SND_SOC_DAPM_PRE_PMU:
  476. wcd937x_rx_clk_enable(component);
  477. snd_soc_component_update_bits(component,
  478. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  479. 0x01, 0x01);
  480. snd_soc_component_update_bits(component,
  481. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  482. 0x04, 0x04);
  483. snd_soc_component_update_bits(component,
  484. WCD937X_HPH_RDAC_CLK_CTL1,
  485. 0x80, 0x00);
  486. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  487. break;
  488. case SND_SOC_DAPM_POST_PMU:
  489. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  490. snd_soc_component_update_bits(component,
  491. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  492. 0x0F, 0x02);
  493. else if (hph_mode == CLS_H_LOHIFI)
  494. snd_soc_component_update_bits(component,
  495. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  496. 0x0F, 0x06);
  497. if (wcd937x->comp1_enable) {
  498. snd_soc_component_update_bits(component,
  499. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  500. 0x02, 0x02);
  501. snd_soc_component_update_bits(component,
  502. WCD937X_HPH_L_EN, 0x20, 0x00);
  503. if (wcd937x->comp2_enable) {
  504. snd_soc_component_update_bits(component,
  505. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  506. 0x01, 0x01);
  507. snd_soc_component_update_bits(component,
  508. WCD937X_HPH_R_EN, 0x20, 0x00);
  509. }
  510. /*
  511. * 5ms sleep is required after COMP is enabled as per
  512. * HW requirement
  513. */
  514. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  515. usleep_range(5000, 5100);
  516. clear_bit(HPH_COMP_DELAY,
  517. &wcd937x->status_mask);
  518. }
  519. } else {
  520. snd_soc_component_update_bits(component,
  521. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  522. 0x02, 0x00);
  523. snd_soc_component_update_bits(component,
  524. WCD937X_HPH_L_EN, 0x20, 0x20);
  525. }
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  528. break;
  529. case SND_SOC_DAPM_POST_PMD:
  530. snd_soc_component_update_bits(component,
  531. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  532. 0x0F, 0x01);
  533. break;
  534. }
  535. return 0;
  536. }
  537. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  538. struct snd_kcontrol *kcontrol,
  539. int event)
  540. {
  541. struct snd_soc_component *component =
  542. snd_soc_dapm_to_component(w->dapm);
  543. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  544. int hph_mode = wcd937x->hph_mode;
  545. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  546. w->name, event);
  547. switch (event) {
  548. case SND_SOC_DAPM_PRE_PMU:
  549. wcd937x_rx_clk_enable(component);
  550. snd_soc_component_update_bits(component,
  551. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  552. snd_soc_component_update_bits(component,
  553. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  554. snd_soc_component_update_bits(component,
  555. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  556. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  557. break;
  558. case SND_SOC_DAPM_POST_PMU:
  559. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  560. snd_soc_component_update_bits(component,
  561. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  562. 0x0F, 0x02);
  563. else if (hph_mode == CLS_H_LOHIFI)
  564. snd_soc_component_update_bits(component,
  565. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  566. 0x0F, 0x06);
  567. if (wcd937x->comp2_enable) {
  568. snd_soc_component_update_bits(component,
  569. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  570. 0x01, 0x01);
  571. snd_soc_component_update_bits(component,
  572. WCD937X_HPH_R_EN, 0x20, 0x00);
  573. if (wcd937x->comp1_enable) {
  574. snd_soc_component_update_bits(component,
  575. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  576. 0x02, 0x02);
  577. snd_soc_component_update_bits(component,
  578. WCD937X_HPH_L_EN, 0x20, 0x00);
  579. }
  580. /*
  581. * 5ms sleep is required after COMP is enabled as per
  582. * HW requirement
  583. */
  584. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  585. usleep_range(5000, 5100);
  586. clear_bit(HPH_COMP_DELAY,
  587. &wcd937x->status_mask);
  588. }
  589. } else {
  590. snd_soc_component_update_bits(component,
  591. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  592. 0x01, 0x00);
  593. snd_soc_component_update_bits(component,
  594. WCD937X_HPH_R_EN, 0x20, 0x20);
  595. }
  596. snd_soc_component_update_bits(component,
  597. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  598. break;
  599. case SND_SOC_DAPM_POST_PMD:
  600. snd_soc_component_update_bits(component,
  601. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  602. 0x0F, 0x01);
  603. break;
  604. }
  605. return 0;
  606. }
  607. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  608. struct snd_kcontrol *kcontrol,
  609. int event)
  610. {
  611. struct snd_soc_component *component =
  612. snd_soc_dapm_to_component(w->dapm);
  613. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  614. int hph_mode = wcd937x->hph_mode;
  615. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  616. w->name, event);
  617. switch (event) {
  618. case SND_SOC_DAPM_PRE_PMU:
  619. wcd937x_rx_clk_enable(component);
  620. snd_soc_component_update_bits(component,
  621. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  622. 0x04, 0x04);
  623. snd_soc_component_update_bits(component,
  624. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  625. 0x01, 0x01);
  626. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  627. snd_soc_component_update_bits(component,
  628. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  629. 0x0F, 0x02);
  630. else if (hph_mode == CLS_H_LOHIFI)
  631. snd_soc_component_update_bits(component,
  632. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  633. 0x0F, 0x06);
  634. if (wcd937x->comp1_enable)
  635. snd_soc_component_update_bits(component,
  636. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  637. 0x02, 0x02);
  638. usleep_range(5000, 5010);
  639. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  640. 0x04, 0x00);
  641. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  642. WCD_CLSH_EVENT_PRE_DAC,
  643. WCD_CLSH_STATE_EAR,
  644. hph_mode);
  645. break;
  646. case SND_SOC_DAPM_POST_PMD:
  647. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  648. hph_mode == CLS_H_HIFI)
  649. snd_soc_component_update_bits(component,
  650. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  651. 0x0F, 0x01);
  652. if (wcd937x->comp1_enable)
  653. snd_soc_component_update_bits(component,
  654. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  655. 0x02, 0x00);
  656. break;
  657. };
  658. return 0;
  659. }
  660. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  661. struct snd_kcontrol *kcontrol,
  662. int event)
  663. {
  664. struct snd_soc_component *component =
  665. snd_soc_dapm_to_component(w->dapm);
  666. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  667. int hph_mode = wcd937x->hph_mode;
  668. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  669. w->name, event);
  670. switch (event) {
  671. case SND_SOC_DAPM_PRE_PMU:
  672. wcd937x_rx_clk_enable(component);
  673. snd_soc_component_update_bits(component,
  674. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  675. 0x04, 0x04);
  676. snd_soc_component_update_bits(component,
  677. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  678. 0x04, 0x04);
  679. snd_soc_component_update_bits(component,
  680. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  681. 0x01, 0x01);
  682. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  683. WCD_CLSH_EVENT_PRE_DAC,
  684. WCD_CLSH_STATE_AUX,
  685. hph_mode);
  686. break;
  687. case SND_SOC_DAPM_POST_PMD:
  688. snd_soc_component_update_bits(component,
  689. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  690. 0x04, 0x00);
  691. break;
  692. };
  693. return 0;
  694. }
  695. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  696. struct snd_kcontrol *kcontrol,
  697. int event)
  698. {
  699. struct snd_soc_component *component =
  700. snd_soc_dapm_to_component(w->dapm);
  701. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  702. int ret = 0;
  703. int hph_mode = wcd937x->hph_mode;
  704. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  705. w->name, event);
  706. switch (event) {
  707. case SND_SOC_DAPM_PRE_PMU:
  708. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  709. wcd937x->rx_swr_dev->dev_num,
  710. true);
  711. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  712. WCD_CLSH_EVENT_PRE_DAC,
  713. WCD_CLSH_STATE_HPHR,
  714. hph_mode);
  715. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  716. 0x10, 0x10);
  717. usleep_range(100, 110);
  718. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  719. snd_soc_component_update_bits(component,
  720. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  721. break;
  722. case SND_SOC_DAPM_POST_PMU:
  723. /*
  724. * 7ms sleep is required after PA is enabled as per
  725. * HW requirement. If compander is disabled, then
  726. * 20ms delay is required.
  727. */
  728. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  729. if (!wcd937x->comp2_enable)
  730. usleep_range(20000, 20100);
  731. else
  732. usleep_range(7000, 7100);
  733. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  734. }
  735. snd_soc_component_update_bits(component,
  736. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  737. 0x02, 0x02);
  738. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  739. snd_soc_component_update_bits(component,
  740. WCD937X_ANA_RX_SUPPLIES,
  741. 0x02, 0x02);
  742. if (wcd937x->update_wcd_event)
  743. wcd937x->update_wcd_event(wcd937x->handle,
  744. SLV_BOLERO_EVT_RX_MUTE,
  745. (WCD_RX2 << 0x10));
  746. wcd_enable_irq(&wcd937x->irq_info,
  747. WCD937X_IRQ_HPHR_PDM_WD_INT);
  748. break;
  749. case SND_SOC_DAPM_PRE_PMD:
  750. wcd_disable_irq(&wcd937x->irq_info,
  751. WCD937X_IRQ_HPHR_PDM_WD_INT);
  752. if (wcd937x->update_wcd_event)
  753. wcd937x->update_wcd_event(wcd937x->handle,
  754. SLV_BOLERO_EVT_RX_MUTE,
  755. (WCD_RX2 << 0x10 | 0x1));
  756. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  757. WCD_EVENT_PRE_HPHR_PA_OFF,
  758. &wcd937x->mbhc->wcd_mbhc);
  759. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  760. break;
  761. case SND_SOC_DAPM_POST_PMD:
  762. /*
  763. * 7ms sleep is required after PA is disabled as per
  764. * HW requirement. If compander is disabled, then
  765. * 20ms delay is required.
  766. */
  767. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  768. if (!wcd937x->comp2_enable)
  769. usleep_range(20000, 20100);
  770. else
  771. usleep_range(7000, 7100);
  772. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  773. }
  774. snd_soc_component_update_bits(component,
  775. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  776. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  777. WCD_EVENT_POST_HPHR_PA_OFF,
  778. &wcd937x->mbhc->wcd_mbhc);
  779. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  780. 0x10, 0x00);
  781. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  782. WCD_CLSH_EVENT_POST_PA,
  783. WCD_CLSH_STATE_HPHR,
  784. hph_mode);
  785. break;
  786. };
  787. return ret;
  788. }
  789. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  790. struct snd_kcontrol *kcontrol,
  791. int event)
  792. {
  793. struct snd_soc_component *component =
  794. snd_soc_dapm_to_component(w->dapm);
  795. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  796. int ret = 0;
  797. int hph_mode = wcd937x->hph_mode;
  798. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  799. w->name, event);
  800. switch (event) {
  801. case SND_SOC_DAPM_PRE_PMU:
  802. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  803. wcd937x->rx_swr_dev->dev_num,
  804. true);
  805. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  806. WCD_CLSH_EVENT_PRE_DAC,
  807. WCD_CLSH_STATE_HPHL,
  808. hph_mode);
  809. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  810. 0x20, 0x20);
  811. usleep_range(100, 110);
  812. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  813. snd_soc_component_update_bits(component,
  814. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  815. break;
  816. case SND_SOC_DAPM_POST_PMU:
  817. /*
  818. * 7ms sleep is required after PA is enabled as per
  819. * HW requirement. If compander is disabled, then
  820. * 20ms delay is required.
  821. */
  822. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  823. if (!wcd937x->comp1_enable)
  824. usleep_range(20000, 20100);
  825. else
  826. usleep_range(7000, 7100);
  827. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  828. }
  829. snd_soc_component_update_bits(component,
  830. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  831. 0x02, 0x02);
  832. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  833. snd_soc_component_update_bits(component,
  834. WCD937X_ANA_RX_SUPPLIES,
  835. 0x02, 0x02);
  836. if (wcd937x->update_wcd_event)
  837. wcd937x->update_wcd_event(wcd937x->handle,
  838. SLV_BOLERO_EVT_RX_MUTE,
  839. (WCD_RX1 << 0x10));
  840. wcd_enable_irq(&wcd937x->irq_info,
  841. WCD937X_IRQ_HPHL_PDM_WD_INT);
  842. break;
  843. case SND_SOC_DAPM_PRE_PMD:
  844. wcd_disable_irq(&wcd937x->irq_info,
  845. WCD937X_IRQ_HPHL_PDM_WD_INT);
  846. if (wcd937x->update_wcd_event)
  847. wcd937x->update_wcd_event(wcd937x->handle,
  848. SLV_BOLERO_EVT_RX_MUTE,
  849. (WCD_RX1 << 0x10 | 0x1));
  850. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  851. WCD_EVENT_PRE_HPHL_PA_OFF,
  852. &wcd937x->mbhc->wcd_mbhc);
  853. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  854. break;
  855. case SND_SOC_DAPM_POST_PMD:
  856. /*
  857. * 7ms sleep is required after PA is disabled as per
  858. * HW requirement. If compander is disabled, then
  859. * 20ms delay is required.
  860. */
  861. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  862. if (!wcd937x->comp1_enable)
  863. usleep_range(20000, 20100);
  864. else
  865. usleep_range(7000, 7100);
  866. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  867. }
  868. snd_soc_component_update_bits(component,
  869. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  870. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  871. WCD_EVENT_POST_HPHL_PA_OFF,
  872. &wcd937x->mbhc->wcd_mbhc);
  873. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  874. 0x20, 0x00);
  875. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  876. WCD_CLSH_EVENT_POST_PA,
  877. WCD_CLSH_STATE_HPHL,
  878. hph_mode);
  879. break;
  880. };
  881. return ret;
  882. }
  883. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  884. struct snd_kcontrol *kcontrol,
  885. int event)
  886. {
  887. struct snd_soc_component *component =
  888. snd_soc_dapm_to_component(w->dapm);
  889. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  890. int hph_mode = wcd937x->hph_mode;
  891. int ret = 0;
  892. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  893. w->name, event);
  894. switch (event) {
  895. case SND_SOC_DAPM_PRE_PMU:
  896. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  897. wcd937x->rx_swr_dev->dev_num,
  898. true);
  899. snd_soc_component_update_bits(component,
  900. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  901. break;
  902. case SND_SOC_DAPM_POST_PMU:
  903. usleep_range(1000, 1010);
  904. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  905. snd_soc_component_update_bits(component,
  906. WCD937X_ANA_RX_SUPPLIES,
  907. 0x02, 0x02);
  908. if (wcd937x->update_wcd_event)
  909. wcd937x->update_wcd_event(wcd937x->handle,
  910. SLV_BOLERO_EVT_RX_MUTE,
  911. (WCD_RX3 << 0x10));
  912. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  913. break;
  914. case SND_SOC_DAPM_PRE_PMD:
  915. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  916. if (wcd937x->update_wcd_event)
  917. wcd937x->update_wcd_event(wcd937x->handle,
  918. SLV_BOLERO_EVT_RX_MUTE,
  919. (WCD_RX3 << 0x10 | 0x1));
  920. break;
  921. case SND_SOC_DAPM_POST_PMD:
  922. /* Add delay as per hw requirement */
  923. usleep_range(2000, 2010);
  924. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  925. WCD_CLSH_EVENT_POST_PA,
  926. WCD_CLSH_STATE_AUX,
  927. hph_mode);
  928. snd_soc_component_update_bits(component,
  929. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  930. break;
  931. };
  932. return ret;
  933. }
  934. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  935. struct snd_kcontrol *kcontrol,
  936. int event)
  937. {
  938. struct snd_soc_component *component =
  939. snd_soc_dapm_to_component(w->dapm);
  940. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  941. int hph_mode = wcd937x->hph_mode;
  942. int ret = 0;
  943. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  944. w->name, event);
  945. switch (event) {
  946. case SND_SOC_DAPM_PRE_PMU:
  947. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  948. wcd937x->rx_swr_dev->dev_num,
  949. true);
  950. /*
  951. * Enable watchdog interrupt for HPHL or AUX
  952. * depending on mux value
  953. */
  954. wcd937x->ear_rx_path =
  955. snd_soc_component_read(
  956. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  957. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  958. snd_soc_component_update_bits(component,
  959. WCD937X_DIGITAL_PDM_WD_CTL2,
  960. 0x05, 0x05);
  961. else
  962. snd_soc_component_update_bits(component,
  963. WCD937X_DIGITAL_PDM_WD_CTL0,
  964. 0x17, 0x13);
  965. if (!wcd937x->comp1_enable)
  966. snd_soc_component_update_bits(component,
  967. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  968. break;
  969. case SND_SOC_DAPM_POST_PMU:
  970. usleep_range(6000, 6010);
  971. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  972. snd_soc_component_update_bits(component,
  973. WCD937X_ANA_RX_SUPPLIES,
  974. 0x02, 0x02);
  975. if (wcd937x->update_wcd_event)
  976. wcd937x->update_wcd_event(wcd937x->handle,
  977. SLV_BOLERO_EVT_RX_MUTE,
  978. (WCD_RX1 << 0x10));
  979. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  980. wcd_enable_irq(&wcd937x->irq_info,
  981. WCD937X_IRQ_AUX_PDM_WD_INT);
  982. else
  983. wcd_enable_irq(&wcd937x->irq_info,
  984. WCD937X_IRQ_HPHL_PDM_WD_INT);
  985. break;
  986. case SND_SOC_DAPM_PRE_PMD:
  987. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  988. wcd_disable_irq(&wcd937x->irq_info,
  989. WCD937X_IRQ_AUX_PDM_WD_INT);
  990. else
  991. wcd_disable_irq(&wcd937x->irq_info,
  992. WCD937X_IRQ_HPHL_PDM_WD_INT);
  993. if (wcd937x->update_wcd_event)
  994. wcd937x->update_wcd_event(wcd937x->handle,
  995. SLV_BOLERO_EVT_RX_MUTE,
  996. (WCD_RX1 << 0x10 | 0x1));
  997. break;
  998. case SND_SOC_DAPM_POST_PMD:
  999. if (!wcd937x->comp1_enable)
  1000. snd_soc_component_update_bits(component,
  1001. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1002. usleep_range(7000, 7010);
  1003. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  1004. WCD_CLSH_EVENT_POST_PA,
  1005. WCD_CLSH_STATE_EAR,
  1006. hph_mode);
  1007. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  1008. 0x04, 0x04);
  1009. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  1010. snd_soc_component_update_bits(component,
  1011. WCD937X_DIGITAL_PDM_WD_CTL2,
  1012. 0x05, 0x00);
  1013. else
  1014. snd_soc_component_update_bits(component,
  1015. WCD937X_DIGITAL_PDM_WD_CTL0,
  1016. 0x17, 0x00);
  1017. break;
  1018. };
  1019. return ret;
  1020. }
  1021. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  1022. struct snd_kcontrol *kcontrol,
  1023. int event)
  1024. {
  1025. struct snd_soc_component *component =
  1026. snd_soc_dapm_to_component(w->dapm);
  1027. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1028. int mode = wcd937x->hph_mode;
  1029. int ret = 0;
  1030. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1031. w->name, event);
  1032. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1033. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1034. wcd937x_rx_connect_port(component, CLSH,
  1035. SND_SOC_DAPM_EVENT_ON(event));
  1036. }
  1037. if (SND_SOC_DAPM_EVENT_OFF(event))
  1038. ret = swr_slvdev_datapath_control(
  1039. wcd937x->rx_swr_dev,
  1040. wcd937x->rx_swr_dev->dev_num,
  1041. false);
  1042. return ret;
  1043. }
  1044. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  1045. struct snd_kcontrol *kcontrol,
  1046. int event)
  1047. {
  1048. struct snd_soc_component *component =
  1049. snd_soc_dapm_to_component(w->dapm);
  1050. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1051. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1052. w->name, event);
  1053. switch (event) {
  1054. case SND_SOC_DAPM_PRE_PMU:
  1055. wcd937x_rx_connect_port(component, HPH_L, true);
  1056. if (wcd937x->comp1_enable)
  1057. wcd937x_rx_connect_port(component, COMP_L, true);
  1058. break;
  1059. case SND_SOC_DAPM_POST_PMD:
  1060. wcd937x_rx_connect_port(component, HPH_L, false);
  1061. if (wcd937x->comp1_enable)
  1062. wcd937x_rx_connect_port(component, COMP_L, false);
  1063. wcd937x_rx_clk_disable(component);
  1064. snd_soc_component_update_bits(component,
  1065. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1066. 0x01, 0x00);
  1067. break;
  1068. };
  1069. return 0;
  1070. }
  1071. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  1072. struct snd_kcontrol *kcontrol, int event)
  1073. {
  1074. struct snd_soc_component *component =
  1075. snd_soc_dapm_to_component(w->dapm);
  1076. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1077. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1078. w->name, event);
  1079. switch (event) {
  1080. case SND_SOC_DAPM_PRE_PMU:
  1081. wcd937x_rx_connect_port(component, HPH_R, true);
  1082. if (wcd937x->comp2_enable)
  1083. wcd937x_rx_connect_port(component, COMP_R, true);
  1084. break;
  1085. case SND_SOC_DAPM_POST_PMD:
  1086. wcd937x_rx_connect_port(component, HPH_R, false);
  1087. if (wcd937x->comp2_enable)
  1088. wcd937x_rx_connect_port(component, COMP_R, false);
  1089. wcd937x_rx_clk_disable(component);
  1090. snd_soc_component_update_bits(component,
  1091. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  1092. 0x02, 0x00);
  1093. break;
  1094. };
  1095. return 0;
  1096. }
  1097. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  1098. struct snd_kcontrol *kcontrol,
  1099. int event)
  1100. {
  1101. struct snd_soc_component *component =
  1102. snd_soc_dapm_to_component(w->dapm);
  1103. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1104. w->name, event);
  1105. switch (event) {
  1106. case SND_SOC_DAPM_PRE_PMU:
  1107. wcd937x_rx_connect_port(component, LO, true);
  1108. break;
  1109. case SND_SOC_DAPM_POST_PMD:
  1110. wcd937x_rx_connect_port(component, LO, false);
  1111. usleep_range(6000, 6010);
  1112. wcd937x_rx_clk_disable(component);
  1113. snd_soc_component_update_bits(component,
  1114. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1115. break;
  1116. }
  1117. return 0;
  1118. }
  1119. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1120. struct snd_kcontrol *kcontrol,
  1121. int event)
  1122. {
  1123. struct snd_soc_component *component =
  1124. snd_soc_dapm_to_component(w->dapm);
  1125. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1126. u16 dmic_clk_reg;
  1127. s32 *dmic_clk_cnt;
  1128. unsigned int dmic;
  1129. char *wname;
  1130. int ret = 0;
  1131. wname = strpbrk(w->name, "012345");
  1132. if (!wname) {
  1133. dev_err(component->dev, "%s: widget not found\n", __func__);
  1134. return -EINVAL;
  1135. }
  1136. ret = kstrtouint(wname, 10, &dmic);
  1137. if (ret < 0) {
  1138. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1139. __func__);
  1140. return -EINVAL;
  1141. }
  1142. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1143. w->name, event);
  1144. switch (dmic) {
  1145. case 0:
  1146. case 1:
  1147. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1148. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1149. break;
  1150. case 2:
  1151. case 3:
  1152. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1153. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1154. break;
  1155. case 4:
  1156. case 5:
  1157. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1158. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1159. break;
  1160. default:
  1161. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1162. __func__);
  1163. return -EINVAL;
  1164. };
  1165. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1166. __func__, event, dmic, *dmic_clk_cnt);
  1167. switch (event) {
  1168. case SND_SOC_DAPM_PRE_PMU:
  1169. snd_soc_component_update_bits(component,
  1170. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1171. snd_soc_component_update_bits(component,
  1172. dmic_clk_reg, 0x07, 0x02);
  1173. snd_soc_component_update_bits(component,
  1174. dmic_clk_reg, 0x08, 0x08);
  1175. snd_soc_component_update_bits(component,
  1176. dmic_clk_reg, 0x70, 0x20);
  1177. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1178. wcd937x->tx_swr_dev->dev_num,
  1179. true);
  1180. break;
  1181. case SND_SOC_DAPM_POST_PMD:
  1182. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1183. break;
  1184. };
  1185. return 0;
  1186. }
  1187. /*
  1188. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1189. * @micb_mv: micbias in mv
  1190. *
  1191. * return register value converted
  1192. */
  1193. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1194. {
  1195. /* min micbias voltage is 1V and maximum is 2.85V */
  1196. if (micb_mv < 1000 || micb_mv > 2850) {
  1197. pr_err("%s: unsupported micbias voltage\n", __func__);
  1198. return -EINVAL;
  1199. }
  1200. return (micb_mv - 1000) / 50;
  1201. }
  1202. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1203. /*
  1204. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1205. * @component: handle to snd_soc_component *
  1206. * @req_volt: micbias voltage to be set
  1207. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1208. *
  1209. * return 0 if adjustment is success or error code in case of failure
  1210. */
  1211. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1212. int req_volt, int micb_num)
  1213. {
  1214. struct wcd937x_priv *wcd937x =
  1215. snd_soc_component_get_drvdata(component);
  1216. int cur_vout_ctl, req_vout_ctl;
  1217. int micb_reg, micb_val, micb_en;
  1218. int ret = 0;
  1219. switch (micb_num) {
  1220. case MIC_BIAS_1:
  1221. micb_reg = WCD937X_ANA_MICB1;
  1222. break;
  1223. case MIC_BIAS_2:
  1224. micb_reg = WCD937X_ANA_MICB2;
  1225. break;
  1226. case MIC_BIAS_3:
  1227. micb_reg = WCD937X_ANA_MICB3;
  1228. break;
  1229. default:
  1230. return -EINVAL;
  1231. }
  1232. mutex_lock(&wcd937x->micb_lock);
  1233. /*
  1234. * If requested micbias voltage is same as current micbias
  1235. * voltage, then just return. Otherwise, adjust voltage as
  1236. * per requested value. If micbias is already enabled, then
  1237. * to avoid slow micbias ramp-up or down enable pull-up
  1238. * momentarily, change the micbias value and then re-enable
  1239. * micbias.
  1240. */
  1241. micb_val = snd_soc_component_read(component, micb_reg);
  1242. micb_en = (micb_val & 0xC0) >> 6;
  1243. cur_vout_ctl = micb_val & 0x3F;
  1244. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1245. if (req_vout_ctl < 0) {
  1246. ret = -EINVAL;
  1247. goto exit;
  1248. }
  1249. if (cur_vout_ctl == req_vout_ctl) {
  1250. ret = 0;
  1251. goto exit;
  1252. }
  1253. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1254. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1255. req_volt, micb_en);
  1256. if (micb_en == 0x1)
  1257. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1258. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1259. if (micb_en == 0x1) {
  1260. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1261. /*
  1262. * Add 2ms delay as per HW requirement after enabling
  1263. * micbias
  1264. */
  1265. usleep_range(2000, 2100);
  1266. }
  1267. exit:
  1268. mutex_unlock(&wcd937x->micb_lock);
  1269. return ret;
  1270. }
  1271. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1272. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1273. struct snd_kcontrol *kcontrol,
  1274. int event)
  1275. {
  1276. struct snd_soc_component *component =
  1277. snd_soc_dapm_to_component(w->dapm);
  1278. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1279. int ret = 0;
  1280. switch (event) {
  1281. case SND_SOC_DAPM_PRE_PMU:
  1282. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1283. /* Enable BCS for Headset mic */
  1284. if (w->shift == 1 && !(snd_soc_component_read(component,
  1285. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1286. wcd937x_tx_connect_port(component, MBHC, true);
  1287. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1288. }
  1289. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1290. } else {
  1291. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1292. }
  1293. break;
  1294. case SND_SOC_DAPM_POST_PMD:
  1295. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1296. wcd937x->tx_swr_dev->dev_num,
  1297. false);
  1298. break;
  1299. };
  1300. return ret;
  1301. }
  1302. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1303. struct snd_kcontrol *kcontrol,
  1304. int event){
  1305. struct snd_soc_component *component =
  1306. snd_soc_dapm_to_component(w->dapm);
  1307. struct wcd937x_priv *wcd937x =
  1308. snd_soc_component_get_drvdata(component);
  1309. int ret = 0;
  1310. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1311. w->name, event);
  1312. switch (event) {
  1313. case SND_SOC_DAPM_PRE_PMU:
  1314. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1315. wcd937x->ana_clk_count++;
  1316. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1317. snd_soc_component_update_bits(component,
  1318. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1319. snd_soc_component_update_bits(component,
  1320. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1321. snd_soc_component_update_bits(component,
  1322. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1323. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1324. wcd937x->tx_swr_dev->dev_num,
  1325. true);
  1326. break;
  1327. case SND_SOC_DAPM_POST_PMD:
  1328. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1329. if (w->shift == 1 &&
  1330. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1331. wcd937x_tx_connect_port(component, MBHC, false);
  1332. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1333. }
  1334. snd_soc_component_update_bits(component,
  1335. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1336. break;
  1337. };
  1338. return ret;
  1339. }
  1340. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1341. struct snd_kcontrol *kcontrol, int event)
  1342. {
  1343. struct snd_soc_component *component =
  1344. snd_soc_dapm_to_component(w->dapm);
  1345. struct wcd937x_priv *wcd937x =
  1346. snd_soc_component_get_drvdata(component);
  1347. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1348. w->name, event);
  1349. switch (event) {
  1350. case SND_SOC_DAPM_PRE_PMU:
  1351. snd_soc_component_update_bits(component,
  1352. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1353. snd_soc_component_update_bits(component,
  1354. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1355. snd_soc_component_update_bits(component,
  1356. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1357. snd_soc_component_update_bits(component,
  1358. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1359. snd_soc_component_update_bits(component,
  1360. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1361. snd_soc_component_update_bits(component,
  1362. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1363. snd_soc_component_update_bits(component,
  1364. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1365. snd_soc_component_update_bits(component,
  1366. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1367. snd_soc_component_update_bits(component,
  1368. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1369. break;
  1370. case SND_SOC_DAPM_POST_PMD:
  1371. snd_soc_component_update_bits(component,
  1372. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1373. snd_soc_component_update_bits(component,
  1374. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1375. snd_soc_component_update_bits(component,
  1376. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1377. snd_soc_component_update_bits(component,
  1378. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1379. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1380. wcd937x->ana_clk_count--;
  1381. if (wcd937x->ana_clk_count <= 0) {
  1382. snd_soc_component_update_bits(component,
  1383. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1384. wcd937x->ana_clk_count = 0;
  1385. }
  1386. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1387. snd_soc_component_update_bits(component,
  1388. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1389. break;
  1390. };
  1391. return 0;
  1392. }
  1393. int wcd937x_micbias_control(struct snd_soc_component *component,
  1394. int micb_num, int req, bool is_dapm)
  1395. {
  1396. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1397. int micb_index = micb_num - 1;
  1398. u16 micb_reg;
  1399. int pre_off_event = 0, post_off_event = 0;
  1400. int post_on_event = 0, post_dapm_off = 0;
  1401. int post_dapm_on = 0;
  1402. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1403. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1404. __func__, micb_index);
  1405. return -EINVAL;
  1406. }
  1407. switch (micb_num) {
  1408. case MIC_BIAS_1:
  1409. micb_reg = WCD937X_ANA_MICB1;
  1410. break;
  1411. case MIC_BIAS_2:
  1412. micb_reg = WCD937X_ANA_MICB2;
  1413. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1414. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1415. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1416. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1417. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1418. break;
  1419. case MIC_BIAS_3:
  1420. micb_reg = WCD937X_ANA_MICB3;
  1421. break;
  1422. default:
  1423. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1424. __func__, micb_num);
  1425. return -EINVAL;
  1426. };
  1427. mutex_lock(&wcd937x->micb_lock);
  1428. switch (req) {
  1429. case MICB_PULLUP_ENABLE:
  1430. wcd937x->pullup_ref[micb_index]++;
  1431. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1432. (wcd937x->micb_ref[micb_index] == 0))
  1433. snd_soc_component_update_bits(component, micb_reg,
  1434. 0xC0, 0x80);
  1435. break;
  1436. case MICB_PULLUP_DISABLE:
  1437. if (wcd937x->pullup_ref[micb_index] > 0)
  1438. wcd937x->pullup_ref[micb_index]--;
  1439. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1440. (wcd937x->micb_ref[micb_index] == 0))
  1441. snd_soc_component_update_bits(component, micb_reg,
  1442. 0xC0, 0x00);
  1443. break;
  1444. case MICB_ENABLE:
  1445. wcd937x->micb_ref[micb_index]++;
  1446. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1447. wcd937x->ana_clk_count++;
  1448. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1449. if (wcd937x->micb_ref[micb_index] == 1) {
  1450. snd_soc_component_update_bits(component,
  1451. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1452. snd_soc_component_update_bits(component,
  1453. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1454. snd_soc_component_update_bits(component,
  1455. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1456. snd_soc_component_update_bits(component,
  1457. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1458. snd_soc_component_update_bits(component,
  1459. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1460. snd_soc_component_update_bits(component,
  1461. micb_reg, 0xC0, 0x40);
  1462. if (post_on_event)
  1463. blocking_notifier_call_chain(
  1464. &wcd937x->mbhc->notifier, post_on_event,
  1465. &wcd937x->mbhc->wcd_mbhc);
  1466. }
  1467. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1468. blocking_notifier_call_chain(
  1469. &wcd937x->mbhc->notifier, post_dapm_on,
  1470. &wcd937x->mbhc->wcd_mbhc);
  1471. break;
  1472. case MICB_DISABLE:
  1473. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1474. wcd937x->ana_clk_count--;
  1475. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1476. if (wcd937x->micb_ref[micb_index] > 0)
  1477. wcd937x->micb_ref[micb_index]--;
  1478. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1479. (wcd937x->pullup_ref[micb_index] > 0))
  1480. snd_soc_component_update_bits(component, micb_reg,
  1481. 0xC0, 0x80);
  1482. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1483. (wcd937x->pullup_ref[micb_index] == 0)) {
  1484. if (pre_off_event && wcd937x->mbhc)
  1485. blocking_notifier_call_chain(
  1486. &wcd937x->mbhc->notifier, pre_off_event,
  1487. &wcd937x->mbhc->wcd_mbhc);
  1488. snd_soc_component_update_bits(component, micb_reg,
  1489. 0xC0, 0x00);
  1490. if (post_off_event && wcd937x->mbhc)
  1491. blocking_notifier_call_chain(
  1492. &wcd937x->mbhc->notifier,
  1493. post_off_event,
  1494. &wcd937x->mbhc->wcd_mbhc);
  1495. }
  1496. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1497. if (wcd937x->ana_clk_count <= 0) {
  1498. snd_soc_component_update_bits(component,
  1499. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1500. 0x10, 0x00);
  1501. wcd937x->ana_clk_count = 0;
  1502. }
  1503. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1504. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1505. blocking_notifier_call_chain(
  1506. &wcd937x->mbhc->notifier, post_dapm_off,
  1507. &wcd937x->mbhc->wcd_mbhc);
  1508. break;
  1509. };
  1510. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1511. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1512. wcd937x->pullup_ref[micb_index]);
  1513. mutex_unlock(&wcd937x->micb_lock);
  1514. return 0;
  1515. }
  1516. EXPORT_SYMBOL(wcd937x_micbias_control);
  1517. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1518. bool bcs_disable)
  1519. {
  1520. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1521. if (wcd937x->update_wcd_event) {
  1522. if (bcs_disable)
  1523. wcd937x->update_wcd_event(wcd937x->handle,
  1524. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1525. else
  1526. wcd937x->update_wcd_event(wcd937x->handle,
  1527. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1528. }
  1529. }
  1530. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1531. {
  1532. int ret = 0;
  1533. uint8_t devnum = 0;
  1534. int num_retry = NUM_ATTEMPTS;
  1535. do {
  1536. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1537. if (ret) {
  1538. dev_err(&swr_dev->dev,
  1539. "%s get devnum %d for dev addr %lx failed\n",
  1540. __func__, devnum, swr_dev->addr);
  1541. /* retry after 1ms */
  1542. usleep_range(1000, 1010);
  1543. }
  1544. } while (ret && --num_retry);
  1545. swr_dev->dev_num = devnum;
  1546. return 0;
  1547. }
  1548. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1549. struct wcd_mbhc_config *mbhc_cfg)
  1550. {
  1551. if (mbhc_cfg->enable_usbc_analog) {
  1552. if (!(snd_soc_component_read(component, WCD937X_ANA_MBHC_MECH)
  1553. & 0x20))
  1554. return true;
  1555. }
  1556. return false;
  1557. }
  1558. static int wcd937x_event_notify(struct notifier_block *block,
  1559. unsigned long val,
  1560. void *data)
  1561. {
  1562. u16 event = (val & 0xffff);
  1563. u16 amic = (val >> 0x10);
  1564. u16 mask = 0x40, reg = 0x0;
  1565. int ret = 0;
  1566. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1567. struct snd_soc_component *component = wcd937x->component;
  1568. struct wcd_mbhc *mbhc;
  1569. switch (event) {
  1570. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1571. if (amic == 0x1 || amic == 0x2)
  1572. reg = WCD937X_ANA_TX_CH2;
  1573. else if (amic == 0x3)
  1574. reg = WCD937X_ANA_TX_CH3_HPF;
  1575. else
  1576. return 0;
  1577. if (amic == 0x2)
  1578. mask = 0x20;
  1579. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1580. break;
  1581. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1582. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1583. 0xC0, 0x00);
  1584. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1585. 0x80, 0x00);
  1586. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1587. 0x80, 0x00);
  1588. break;
  1589. case BOLERO_SLV_EVT_SSR_DOWN:
  1590. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1591. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1592. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1593. mbhc->mbhc_cfg);
  1594. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1595. wcd937x_reset_low(wcd937x->dev);
  1596. break;
  1597. case BOLERO_SLV_EVT_SSR_UP:
  1598. wcd937x_reset(wcd937x->dev);
  1599. /* allow reset to take effect */
  1600. usleep_range(10000, 10010);
  1601. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1602. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1603. wcd937x_init_reg(component);
  1604. regcache_mark_dirty(wcd937x->regmap);
  1605. regcache_sync(wcd937x->regmap);
  1606. /* Initialize MBHC module */
  1607. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1608. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1609. if (ret) {
  1610. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1611. __func__);
  1612. } else {
  1613. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1614. if (wcd937x->usbc_hs_status)
  1615. mdelay(500);
  1616. }
  1617. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1618. break;
  1619. default:
  1620. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1621. event);
  1622. break;
  1623. }
  1624. return 0;
  1625. }
  1626. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1627. int event)
  1628. {
  1629. struct snd_soc_component *component =
  1630. snd_soc_dapm_to_component(w->dapm);
  1631. int micb_num;
  1632. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1633. __func__, w->name, event);
  1634. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1635. micb_num = MIC_BIAS_1;
  1636. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1637. micb_num = MIC_BIAS_2;
  1638. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1639. micb_num = MIC_BIAS_3;
  1640. else
  1641. return -EINVAL;
  1642. switch (event) {
  1643. case SND_SOC_DAPM_PRE_PMU:
  1644. wcd937x_micbias_control(component, micb_num,
  1645. MICB_ENABLE, true);
  1646. break;
  1647. case SND_SOC_DAPM_POST_PMU:
  1648. usleep_range(1000, 1100);
  1649. break;
  1650. case SND_SOC_DAPM_POST_PMD:
  1651. wcd937x_micbias_control(component, micb_num,
  1652. MICB_DISABLE, true);
  1653. break;
  1654. };
  1655. return 0;
  1656. }
  1657. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1658. struct snd_kcontrol *kcontrol,
  1659. int event)
  1660. {
  1661. return __wcd937x_codec_enable_micbias(w, event);
  1662. }
  1663. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1664. int event)
  1665. {
  1666. struct snd_soc_component *component =
  1667. snd_soc_dapm_to_component(w->dapm);
  1668. int micb_num;
  1669. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1670. __func__, w->name, event);
  1671. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1672. micb_num = MIC_BIAS_1;
  1673. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1674. micb_num = MIC_BIAS_2;
  1675. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1676. micb_num = MIC_BIAS_3;
  1677. else
  1678. return -EINVAL;
  1679. switch (event) {
  1680. case SND_SOC_DAPM_PRE_PMU:
  1681. wcd937x_micbias_control(component, micb_num,
  1682. MICB_PULLUP_ENABLE, true);
  1683. break;
  1684. case SND_SOC_DAPM_POST_PMU:
  1685. /* 1 msec delay as per HW requirement */
  1686. usleep_range(1000, 1100);
  1687. break;
  1688. case SND_SOC_DAPM_POST_PMD:
  1689. wcd937x_micbias_control(component, micb_num,
  1690. MICB_PULLUP_DISABLE, true);
  1691. break;
  1692. };
  1693. return 0;
  1694. }
  1695. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1696. struct snd_kcontrol *kcontrol,
  1697. int event)
  1698. {
  1699. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1700. }
  1701. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1702. struct snd_ctl_elem_value *ucontrol)
  1703. {
  1704. struct snd_soc_component *component =
  1705. snd_soc_kcontrol_component(kcontrol);
  1706. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1707. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1708. return 0;
  1709. }
  1710. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1711. struct snd_ctl_elem_value *ucontrol)
  1712. {
  1713. struct snd_soc_component *component =
  1714. snd_soc_kcontrol_component(kcontrol);
  1715. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1716. u32 mode_val;
  1717. mode_val = ucontrol->value.enumerated.item[0];
  1718. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1719. if (mode_val == 0) {
  1720. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1721. __func__);
  1722. mode_val = 3; /* enum will be updated later */
  1723. }
  1724. wcd937x->hph_mode = mode_val;
  1725. return 0;
  1726. }
  1727. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1728. struct snd_ctl_elem_value *ucontrol)
  1729. {
  1730. struct snd_soc_component *component =
  1731. snd_soc_kcontrol_component(kcontrol);
  1732. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1733. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1734. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1735. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1736. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1737. return 0;
  1738. }
  1739. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1740. struct snd_ctl_elem_value *ucontrol)
  1741. {
  1742. struct snd_soc_component *component =
  1743. snd_soc_kcontrol_component(kcontrol);
  1744. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1745. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1746. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1747. __func__, pwr_level);
  1748. if (strnstr(kcontrol->id.name, "CH1",
  1749. sizeof(kcontrol->id.name))) {
  1750. snd_soc_component_update_bits(component,
  1751. WCD937X_ANA_TX_CH1, 0x60,
  1752. pwr_level << 0x5);
  1753. wcd937x->tx_ch_pwr[0] = pwr_level;
  1754. } else if (strnstr(kcontrol->id.name, "CH3",
  1755. sizeof(kcontrol->id.name))) {
  1756. snd_soc_component_update_bits(component,
  1757. WCD937X_ANA_TX_CH3, 0x60,
  1758. pwr_level << 0x5);
  1759. wcd937x->tx_ch_pwr[1] = pwr_level;
  1760. }
  1761. return 0;
  1762. }
  1763. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1764. struct snd_ctl_elem_value *ucontrol)
  1765. {
  1766. u8 ear_pa_gain = 0;
  1767. struct snd_soc_component *component =
  1768. snd_soc_kcontrol_component(kcontrol);
  1769. ear_pa_gain = snd_soc_component_read(component,
  1770. WCD937X_ANA_EAR_COMPANDER_CTL);
  1771. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1772. ucontrol->value.integer.value[0] = ear_pa_gain;
  1773. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1774. ear_pa_gain);
  1775. return 0;
  1776. }
  1777. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1778. struct snd_ctl_elem_value *ucontrol)
  1779. {
  1780. u8 ear_pa_gain = 0;
  1781. struct snd_soc_component *component =
  1782. snd_soc_kcontrol_component(kcontrol);
  1783. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1784. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1785. __func__, ucontrol->value.integer.value[0]);
  1786. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1787. if (!wcd937x->comp1_enable) {
  1788. snd_soc_component_update_bits(component,
  1789. WCD937X_ANA_EAR_COMPANDER_CTL,
  1790. 0x7C, ear_pa_gain);
  1791. }
  1792. return 0;
  1793. }
  1794. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1795. struct snd_ctl_elem_value *ucontrol)
  1796. {
  1797. struct snd_soc_component *component =
  1798. snd_soc_kcontrol_component(kcontrol);
  1799. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1800. bool hphr;
  1801. struct soc_multi_mixer_control *mc;
  1802. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1803. hphr = mc->shift;
  1804. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1805. wcd937x->comp1_enable;
  1806. return 0;
  1807. }
  1808. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1809. struct snd_ctl_elem_value *ucontrol)
  1810. {
  1811. struct snd_soc_component *component =
  1812. snd_soc_kcontrol_component(kcontrol);
  1813. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1814. int value = ucontrol->value.integer.value[0];
  1815. bool hphr;
  1816. struct soc_multi_mixer_control *mc;
  1817. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1818. hphr = mc->shift;
  1819. if (hphr)
  1820. wcd937x->comp2_enable = value;
  1821. else
  1822. wcd937x->comp1_enable = value;
  1823. return 0;
  1824. }
  1825. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1826. struct snd_kcontrol *kcontrol,
  1827. int event)
  1828. {
  1829. struct snd_soc_component *component =
  1830. snd_soc_dapm_to_component(w->dapm);
  1831. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1832. struct wcd937x_pdata *pdata = NULL;
  1833. int ret = 0;
  1834. pdata = dev_get_platdata(wcd937x->dev);
  1835. if (!pdata) {
  1836. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1837. return -EINVAL;
  1838. }
  1839. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1840. w->name, event);
  1841. switch (event) {
  1842. case SND_SOC_DAPM_PRE_PMU:
  1843. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1844. dev_dbg(component->dev,
  1845. "%s: buck already in enabled state\n",
  1846. __func__);
  1847. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1848. return 0;
  1849. }
  1850. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1851. wcd937x->supplies,
  1852. pdata->regulator,
  1853. pdata->num_supplies,
  1854. "cdc-vdd-buck");
  1855. if (ret == -EINVAL) {
  1856. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1857. __func__);
  1858. return ret;
  1859. }
  1860. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1861. /*
  1862. * 200us sleep is required after LDO15 is enabled as per
  1863. * HW requirement
  1864. */
  1865. usleep_range(200, 250);
  1866. break;
  1867. case SND_SOC_DAPM_POST_PMD:
  1868. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1869. break;
  1870. }
  1871. return 0;
  1872. }
  1873. static const char * const rx_hph_mode_mux_text[] = {
  1874. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1875. "CLS_H_ULP", "CLS_AB_HIFI",
  1876. };
  1877. const char * const tx_master_ch_text[] = {
  1878. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1879. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1880. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1881. "SWRM_PCM_IN",
  1882. };
  1883. const struct soc_enum tx_master_ch_enum =
  1884. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1885. tx_master_ch_text);
  1886. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1887. {
  1888. u8 ch_type = 0;
  1889. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1890. ch_type = ADC1;
  1891. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1892. ch_type = ADC2;
  1893. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1894. ch_type = ADC3;
  1895. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1896. ch_type = DMIC0;
  1897. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1898. ch_type = DMIC1;
  1899. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1900. ch_type = MBHC;
  1901. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1902. ch_type = DMIC2;
  1903. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1904. ch_type = DMIC3;
  1905. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1906. ch_type = DMIC4;
  1907. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1908. ch_type = DMIC5;
  1909. else
  1910. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1911. if (ch_type)
  1912. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1913. else
  1914. *ch_idx = -EINVAL;
  1915. }
  1916. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1917. struct snd_ctl_elem_value *ucontrol)
  1918. {
  1919. struct snd_soc_component *component =
  1920. snd_soc_kcontrol_component(kcontrol);
  1921. struct wcd937x_priv *wcd937x = NULL;
  1922. int slave_ch_idx = -EINVAL;
  1923. if (component == NULL)
  1924. return -EINVAL;
  1925. wcd937x = snd_soc_component_get_drvdata(component);
  1926. if (wcd937x == NULL)
  1927. return -EINVAL;
  1928. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1929. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  1930. return -EINVAL;
  1931. ucontrol->value.integer.value[0] =
  1932. wcd937x_slave_get_master_ch_val(
  1933. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1934. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1935. __func__, ucontrol->value.integer.value[0]);
  1936. return 0;
  1937. }
  1938. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1939. struct snd_ctl_elem_value *ucontrol)
  1940. {
  1941. struct snd_soc_component *component =
  1942. snd_soc_kcontrol_component(kcontrol);
  1943. struct wcd937x_priv *wcd937x;
  1944. int slave_ch_idx = -EINVAL, idx = 0;
  1945. if (component == NULL)
  1946. return -EINVAL;
  1947. wcd937x = snd_soc_component_get_drvdata(component);
  1948. if (wcd937x == NULL)
  1949. return -EINVAL;
  1950. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1951. if (slave_ch_idx < 0 || slave_ch_idx >= WCD937X_MAX_SLAVE_CH_TYPES)
  1952. return -EINVAL;
  1953. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1954. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1955. __func__, ucontrol->value.enumerated.item[0]);
  1956. idx = ucontrol->value.enumerated.item[0];
  1957. if (idx < 0 || idx >= ARRAY_SIZE(wcd937x_swr_master_ch_map))
  1958. return -EINVAL;
  1959. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1960. wcd937x_slave_get_master_ch(idx);
  1961. return 0;
  1962. }
  1963. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1964. "L0", "L1", "L2", "L3",
  1965. };
  1966. static const char * const wcd937x_ear_pa_gain_text[] = {
  1967. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1968. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1969. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1970. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1971. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1972. };
  1973. static const struct soc_enum rx_hph_mode_mux_enum =
  1974. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1975. rx_hph_mode_mux_text);
  1976. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1977. wcd937x_ear_pa_gain_text);
  1978. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1979. wcd937x_tx_ch_pwr_level_text);
  1980. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1981. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1982. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1983. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1984. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1985. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1986. wcd937x_get_compander, wcd937x_set_compander),
  1987. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1988. wcd937x_get_compander, wcd937x_set_compander),
  1989. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1990. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1991. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1992. analog_gain),
  1993. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1994. analog_gain),
  1995. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1996. analog_gain),
  1997. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1998. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1999. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2000. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2001. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2002. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2003. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2004. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2005. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2006. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2007. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2008. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2009. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2010. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2011. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2012. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2013. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2014. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2015. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2016. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  2017. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  2018. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2019. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  2020. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  2021. };
  2022. static const struct snd_kcontrol_new adc1_switch[] = {
  2023. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2024. };
  2025. static const struct snd_kcontrol_new adc2_switch[] = {
  2026. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2027. };
  2028. static const struct snd_kcontrol_new adc3_switch[] = {
  2029. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2030. };
  2031. static const struct snd_kcontrol_new dmic1_switch[] = {
  2032. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2033. };
  2034. static const struct snd_kcontrol_new dmic2_switch[] = {
  2035. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2036. };
  2037. static const struct snd_kcontrol_new dmic3_switch[] = {
  2038. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2039. };
  2040. static const struct snd_kcontrol_new dmic4_switch[] = {
  2041. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2042. };
  2043. static const struct snd_kcontrol_new dmic5_switch[] = {
  2044. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2045. };
  2046. static const struct snd_kcontrol_new dmic6_switch[] = {
  2047. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2048. };
  2049. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2050. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2051. };
  2052. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2053. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2054. };
  2055. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2056. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2057. };
  2058. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2059. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2060. };
  2061. static const char * const adc2_mux_text[] = {
  2062. "INP2", "INP3"
  2063. };
  2064. static const char * const rdac3_mux_text[] = {
  2065. "RX1", "RX3"
  2066. };
  2067. static const struct soc_enum adc2_enum =
  2068. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  2069. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2070. static const struct soc_enum rdac3_enum =
  2071. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2072. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2073. static const struct snd_kcontrol_new tx_adc2_mux =
  2074. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2075. static const struct snd_kcontrol_new rx_rdac3_mux =
  2076. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2077. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  2078. /*input widgets*/
  2079. SND_SOC_DAPM_INPUT("AMIC1"),
  2080. SND_SOC_DAPM_INPUT("AMIC2"),
  2081. SND_SOC_DAPM_INPUT("AMIC3"),
  2082. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2083. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2084. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2085. /*
  2086. * These dummy widgets are null connected to WCD937x dapm input and
  2087. * output widgets which are not actual path endpoints. This ensures
  2088. * dapm doesnt set these dapm input and output widgets as endpoints.
  2089. */
  2090. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2091. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2092. /*tx widgets*/
  2093. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2094. wcd937x_codec_enable_adc,
  2095. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2096. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2097. wcd937x_codec_enable_adc,
  2098. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2099. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2100. NULL, 0, wcd937x_enable_req,
  2101. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2102. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  2103. NULL, 0, wcd937x_enable_req,
  2104. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2105. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2106. &tx_adc2_mux),
  2107. /*tx mixers*/
  2108. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2109. adc1_switch, ARRAY_SIZE(adc1_switch),
  2110. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2111. SND_SOC_DAPM_POST_PMD),
  2112. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
  2113. adc2_switch, ARRAY_SIZE(adc2_switch),
  2114. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2115. SND_SOC_DAPM_POST_PMD),
  2116. /* micbias widgets*/
  2117. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2118. wcd937x_codec_enable_micbias,
  2119. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2120. SND_SOC_DAPM_POST_PMD),
  2121. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2122. wcd937x_codec_enable_micbias,
  2123. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2124. SND_SOC_DAPM_POST_PMD),
  2125. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2126. wcd937x_codec_enable_micbias,
  2127. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2128. SND_SOC_DAPM_POST_PMD),
  2129. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2130. wcd937x_codec_enable_vdd_buck,
  2131. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2132. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2133. wcd937x_enable_clsh,
  2134. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2135. /*rx widgets*/
  2136. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2137. wcd937x_codec_enable_ear_pa,
  2138. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2139. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2140. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2141. wcd937x_codec_enable_aux_pa,
  2142. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2143. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2144. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2145. wcd937x_codec_enable_hphl_pa,
  2146. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2147. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2148. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2149. wcd937x_codec_enable_hphr_pa,
  2150. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2151. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2152. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2153. wcd937x_codec_hphl_dac_event,
  2154. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2155. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2156. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2157. wcd937x_codec_hphr_dac_event,
  2158. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2159. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2160. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2161. wcd937x_codec_ear_dac_event,
  2162. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2163. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2164. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2165. wcd937x_codec_aux_dac_event,
  2166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2167. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2168. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2169. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2170. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2171. SND_SOC_DAPM_POST_PMD),
  2172. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2173. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2174. SND_SOC_DAPM_POST_PMD),
  2175. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2176. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2177. SND_SOC_DAPM_POST_PMD),
  2178. /* rx mixer widgets*/
  2179. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2180. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2181. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2182. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2183. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2184. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2185. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2186. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2187. /*output widgets tx*/
  2188. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2189. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2190. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2191. /*output widgets rx*/
  2192. SND_SOC_DAPM_OUTPUT("EAR"),
  2193. SND_SOC_DAPM_OUTPUT("AUX"),
  2194. SND_SOC_DAPM_OUTPUT("HPHL"),
  2195. SND_SOC_DAPM_OUTPUT("HPHR"),
  2196. /* micbias pull up widgets*/
  2197. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2198. wcd937x_codec_enable_micbias_pullup,
  2199. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2200. SND_SOC_DAPM_POST_PMD),
  2201. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2202. wcd937x_codec_enable_micbias_pullup,
  2203. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2204. SND_SOC_DAPM_POST_PMD),
  2205. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2206. wcd937x_codec_enable_micbias_pullup,
  2207. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2208. SND_SOC_DAPM_POST_PMD),
  2209. };
  2210. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2211. /*input widgets*/
  2212. SND_SOC_DAPM_INPUT("AMIC4"),
  2213. /*tx widgets*/
  2214. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2215. wcd937x_codec_enable_adc,
  2216. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2217. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2218. NULL, 0, wcd937x_enable_req,
  2219. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2220. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2221. wcd937x_codec_enable_dmic,
  2222. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2223. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2224. wcd937x_codec_enable_dmic,
  2225. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2226. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2227. wcd937x_codec_enable_dmic,
  2228. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2229. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2230. wcd937x_codec_enable_dmic,
  2231. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2232. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2233. wcd937x_codec_enable_dmic,
  2234. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2235. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2236. wcd937x_codec_enable_dmic,
  2237. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2238. /*tx mixer widgets*/
  2239. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2240. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2241. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2242. SND_SOC_DAPM_POST_PMD),
  2243. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
  2244. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2245. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2246. SND_SOC_DAPM_POST_PMD),
  2247. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
  2248. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2249. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2250. SND_SOC_DAPM_POST_PMD),
  2251. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
  2252. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2253. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2254. SND_SOC_DAPM_POST_PMD),
  2255. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
  2256. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2257. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2258. SND_SOC_DAPM_POST_PMD),
  2259. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
  2260. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2261. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2262. SND_SOC_DAPM_POST_PMD),
  2263. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
  2264. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2265. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2266. /*output widgets*/
  2267. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2268. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2269. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2270. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2271. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2272. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2273. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2274. };
  2275. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2276. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2277. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2278. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2279. {"ADC1 REQ", NULL, "ADC1"},
  2280. {"ADC1", NULL, "AMIC1"},
  2281. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2282. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2283. {"ADC2 REQ", NULL, "ADC2"},
  2284. {"ADC2", NULL, "ADC2 MUX"},
  2285. {"ADC2 MUX", "INP3", "AMIC3"},
  2286. {"ADC2 MUX", "INP2", "AMIC2"},
  2287. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  2288. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2289. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2290. {"RX1", NULL, "IN1_HPHL"},
  2291. {"RDAC1", NULL, "RX1"},
  2292. {"HPHL_RDAC", "Switch", "RDAC1"},
  2293. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2294. {"HPHL", NULL, "HPHL PGA"},
  2295. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  2296. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2297. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2298. {"RX2", NULL, "IN2_HPHR"},
  2299. {"RDAC2", NULL, "RX2"},
  2300. {"HPHR_RDAC", "Switch", "RDAC2"},
  2301. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2302. {"HPHR", NULL, "HPHR PGA"},
  2303. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  2304. {"IN3_AUX", NULL, "VDD_BUCK"},
  2305. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2306. {"RX3", NULL, "IN3_AUX"},
  2307. {"RDAC4", NULL, "RX3"},
  2308. {"AUX_RDAC", "Switch", "RDAC4"},
  2309. {"AUX PGA", NULL, "AUX_RDAC"},
  2310. {"AUX", NULL, "AUX PGA"},
  2311. {"RDAC3_MUX", "RX3", "RX3"},
  2312. {"RDAC3_MUX", "RX1", "RX1"},
  2313. {"RDAC3", NULL, "RDAC3_MUX"},
  2314. {"EAR_RDAC", "Switch", "RDAC3"},
  2315. {"EAR PGA", NULL, "EAR_RDAC"},
  2316. {"EAR", NULL, "EAR PGA"},
  2317. };
  2318. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2319. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  2320. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2321. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2322. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2323. {"ADC3 REQ", NULL, "ADC3"},
  2324. {"ADC3", NULL, "AMIC4"},
  2325. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2326. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2327. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2328. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2329. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2330. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2331. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2332. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2333. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2334. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2335. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2336. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2337. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2338. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2339. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2340. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2341. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2342. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2343. };
  2344. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2345. void *file_private_data,
  2346. struct file *file,
  2347. char __user *buf, size_t count,
  2348. loff_t pos)
  2349. {
  2350. struct wcd937x_priv *priv;
  2351. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2352. int len = 0;
  2353. priv = (struct wcd937x_priv *) entry->private_data;
  2354. if (!priv) {
  2355. pr_err("%s: wcd937x priv is null\n", __func__);
  2356. return -EINVAL;
  2357. }
  2358. switch (priv->version) {
  2359. case WCD937X_VERSION_1_0:
  2360. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2361. break;
  2362. default:
  2363. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2364. }
  2365. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2366. }
  2367. static struct snd_info_entry_ops wcd937x_info_ops = {
  2368. .read = wcd937x_version_read,
  2369. };
  2370. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2371. void *file_private_data,
  2372. struct file *file,
  2373. char __user *buf, size_t count,
  2374. loff_t pos)
  2375. {
  2376. struct wcd937x_priv *priv;
  2377. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2378. int len = 0;
  2379. priv = (struct wcd937x_priv *) entry->private_data;
  2380. if (!priv) {
  2381. pr_err("%s: wcd937x priv is null\n", __func__);
  2382. return -EINVAL;
  2383. }
  2384. switch (priv->variant) {
  2385. case WCD9370_VARIANT:
  2386. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2387. break;
  2388. case WCD9375_VARIANT:
  2389. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2390. break;
  2391. default:
  2392. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2393. }
  2394. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2395. }
  2396. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2397. .read = wcd937x_variant_read,
  2398. };
  2399. /*
  2400. * wcd937x_info_create_codec_entry - creates wcd937x module
  2401. * @codec_root: The parent directory
  2402. * @component: component instance
  2403. *
  2404. * Creates wcd937x module, variant and version entry under the given
  2405. * parent directory.
  2406. *
  2407. * Return: 0 on success or negative error code on failure.
  2408. */
  2409. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2410. struct snd_soc_component *component)
  2411. {
  2412. struct snd_info_entry *version_entry;
  2413. struct snd_info_entry *variant_entry;
  2414. struct wcd937x_priv *priv;
  2415. struct snd_soc_card *card;
  2416. if (!codec_root || !component)
  2417. return -EINVAL;
  2418. priv = snd_soc_component_get_drvdata(component);
  2419. if (priv->entry) {
  2420. dev_dbg(priv->dev,
  2421. "%s:wcd937x module already created\n", __func__);
  2422. return 0;
  2423. }
  2424. card = component->card;
  2425. priv->entry = snd_info_create_module_entry(codec_root->module,
  2426. "wcd937x", codec_root);
  2427. if (!priv->entry) {
  2428. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2429. __func__);
  2430. return -ENOMEM;
  2431. }
  2432. priv->entry->mode = S_IFDIR | 0555;
  2433. if (snd_info_register(priv->entry) < 0) {
  2434. snd_info_free_entry(priv->entry);
  2435. return -ENOMEM;
  2436. }
  2437. version_entry = snd_info_create_card_entry(card->snd_card,
  2438. "version",
  2439. priv->entry);
  2440. if (!version_entry) {
  2441. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2442. __func__);
  2443. snd_info_free_entry(priv->entry);
  2444. return -ENOMEM;
  2445. }
  2446. version_entry->private_data = priv;
  2447. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2448. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2449. version_entry->c.ops = &wcd937x_info_ops;
  2450. if (snd_info_register(version_entry) < 0) {
  2451. snd_info_free_entry(version_entry);
  2452. snd_info_free_entry(priv->entry);
  2453. return -ENOMEM;
  2454. }
  2455. priv->version_entry = version_entry;
  2456. variant_entry = snd_info_create_card_entry(card->snd_card,
  2457. "variant",
  2458. priv->entry);
  2459. if (!variant_entry) {
  2460. dev_dbg(component->dev,
  2461. "%s: failed to create wcd937x variant entry\n",
  2462. __func__);
  2463. snd_info_free_entry(version_entry);
  2464. snd_info_free_entry(priv->entry);
  2465. return -ENOMEM;
  2466. }
  2467. variant_entry->private_data = priv;
  2468. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2469. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2470. variant_entry->c.ops = &wcd937x_variant_ops;
  2471. if (snd_info_register(variant_entry) < 0) {
  2472. snd_info_free_entry(variant_entry);
  2473. snd_info_free_entry(version_entry);
  2474. snd_info_free_entry(priv->entry);
  2475. return -ENOMEM;
  2476. }
  2477. priv->variant_entry = variant_entry;
  2478. return 0;
  2479. }
  2480. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2481. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2482. struct wcd937x_pdata *pdata)
  2483. {
  2484. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2485. int rc = 0;
  2486. if (!pdata) {
  2487. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2488. return -ENODEV;
  2489. }
  2490. /* set micbias voltage */
  2491. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2492. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2493. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2494. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2495. rc = -EINVAL;
  2496. goto done;
  2497. }
  2498. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2499. vout_ctl_1);
  2500. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2501. vout_ctl_2);
  2502. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2503. vout_ctl_3);
  2504. done:
  2505. return rc;
  2506. }
  2507. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2508. {
  2509. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2510. struct snd_soc_dapm_context *dapm =
  2511. snd_soc_component_get_dapm(component);
  2512. int variant;
  2513. int ret = -EINVAL;
  2514. dev_info(component->dev, "%s()\n", __func__);
  2515. wcd937x = snd_soc_component_get_drvdata(component);
  2516. if (!wcd937x)
  2517. return -EINVAL;
  2518. wcd937x->component = component;
  2519. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2520. variant = (snd_soc_component_read(
  2521. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2522. wcd937x->variant = variant;
  2523. wcd937x->fw_data = devm_kzalloc(component->dev,
  2524. sizeof(*(wcd937x->fw_data)),
  2525. GFP_KERNEL);
  2526. if (!wcd937x->fw_data) {
  2527. dev_err(component->dev, "Failed to allocate fw_data\n");
  2528. ret = -ENOMEM;
  2529. goto err;
  2530. }
  2531. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2532. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2533. WCD9XXX_CODEC_HWDEP_NODE, component);
  2534. if (ret < 0) {
  2535. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2536. goto err_hwdep;
  2537. }
  2538. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2539. if (ret) {
  2540. pr_err("%s: mbhc initialization failed\n", __func__);
  2541. goto err_hwdep;
  2542. }
  2543. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2544. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2545. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2546. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2547. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2548. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2549. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2550. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2551. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2552. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2553. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2554. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2555. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2556. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  2557. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  2558. snd_soc_dapm_sync(dapm);
  2559. wcd_cls_h_init(&wcd937x->clsh_info);
  2560. wcd937x_init_reg(component);
  2561. if (wcd937x->variant == WCD9375_VARIANT) {
  2562. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2563. ARRAY_SIZE(wcd9375_dapm_widgets));
  2564. if (ret < 0) {
  2565. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2566. __func__);
  2567. goto err_hwdep;
  2568. }
  2569. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2570. ARRAY_SIZE(wcd9375_audio_map));
  2571. if (ret < 0) {
  2572. dev_err(component->dev, "%s: Failed to add routes\n",
  2573. __func__);
  2574. goto err_hwdep;
  2575. }
  2576. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2577. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2578. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2579. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2580. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2581. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2582. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2583. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2584. snd_soc_dapm_sync(dapm);
  2585. }
  2586. wcd937x->version = WCD937X_VERSION_1_0;
  2587. /* Register event notifier */
  2588. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2589. if (wcd937x->register_notifier) {
  2590. ret = wcd937x->register_notifier(wcd937x->handle,
  2591. &wcd937x->nblock,
  2592. true);
  2593. if (ret) {
  2594. dev_err(component->dev,
  2595. "%s: Failed to register notifier %d\n",
  2596. __func__, ret);
  2597. return ret;
  2598. }
  2599. }
  2600. return ret;
  2601. err_hwdep:
  2602. wcd937x->fw_data = NULL;
  2603. err:
  2604. return ret;
  2605. }
  2606. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2607. {
  2608. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2609. if (!wcd937x)
  2610. return;
  2611. if (wcd937x->register_notifier)
  2612. wcd937x->register_notifier(wcd937x->handle,
  2613. &wcd937x->nblock,
  2614. false);
  2615. return;
  2616. }
  2617. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2618. .name = WCD937X_DRV_NAME,
  2619. .probe = wcd937x_soc_codec_probe,
  2620. .remove = wcd937x_soc_codec_remove,
  2621. .controls = wcd937x_snd_controls,
  2622. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2623. .dapm_widgets = wcd937x_dapm_widgets,
  2624. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2625. .dapm_routes = wcd937x_audio_map,
  2626. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2627. };
  2628. #ifdef CONFIG_PM_SLEEP
  2629. static int wcd937x_suspend(struct device *dev)
  2630. {
  2631. struct wcd937x_priv *wcd937x = NULL;
  2632. int ret = 0;
  2633. struct wcd937x_pdata *pdata = NULL;
  2634. if (!dev)
  2635. return -ENODEV;
  2636. wcd937x = dev_get_drvdata(dev);
  2637. if (!wcd937x)
  2638. return -EINVAL;
  2639. pdata = dev_get_platdata(wcd937x->dev);
  2640. if (!pdata) {
  2641. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2642. return -EINVAL;
  2643. }
  2644. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2645. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2646. wcd937x->supplies,
  2647. pdata->regulator,
  2648. pdata->num_supplies,
  2649. "cdc-vdd-buck");
  2650. if (ret == -EINVAL) {
  2651. dev_err(dev, "%s: vdd buck is not disabled\n",
  2652. __func__);
  2653. return 0;
  2654. }
  2655. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2656. }
  2657. return 0;
  2658. }
  2659. static int wcd937x_resume(struct device *dev)
  2660. {
  2661. return 0;
  2662. }
  2663. #endif
  2664. static int wcd937x_reset(struct device *dev)
  2665. {
  2666. struct wcd937x_priv *wcd937x = NULL;
  2667. int rc = 0;
  2668. int value = 0;
  2669. if (!dev)
  2670. return -ENODEV;
  2671. wcd937x = dev_get_drvdata(dev);
  2672. if (!wcd937x)
  2673. return -EINVAL;
  2674. if (!wcd937x->rst_np) {
  2675. dev_err(dev, "%s: reset gpio device node not specified\n",
  2676. __func__);
  2677. return -EINVAL;
  2678. }
  2679. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2680. if (value > 0)
  2681. return 0;
  2682. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2683. if (rc) {
  2684. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2685. __func__);
  2686. return rc;
  2687. }
  2688. /* 20ms sleep required after pulling the reset gpio to LOW */
  2689. usleep_range(20, 30);
  2690. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2691. if (rc) {
  2692. dev_err(dev, "%s: wcd active state request fail!\n",
  2693. __func__);
  2694. return rc;
  2695. }
  2696. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2697. usleep_range(20, 30);
  2698. return rc;
  2699. }
  2700. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2701. u32 *val)
  2702. {
  2703. int rc = 0;
  2704. rc = of_property_read_u32(dev->of_node, name, val);
  2705. if (rc)
  2706. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2707. __func__, name, dev->of_node->full_name);
  2708. return rc;
  2709. }
  2710. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2711. struct wcd937x_micbias_setting *mb)
  2712. {
  2713. u32 prop_val = 0;
  2714. int rc = 0;
  2715. /* MB1 */
  2716. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2717. NULL)) {
  2718. rc = wcd937x_read_of_property_u32(dev,
  2719. "qcom,cdc-micbias1-mv",
  2720. &prop_val);
  2721. if (!rc)
  2722. mb->micb1_mv = prop_val;
  2723. } else {
  2724. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2725. __func__);
  2726. }
  2727. /* MB2 */
  2728. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2729. NULL)) {
  2730. rc = wcd937x_read_of_property_u32(dev,
  2731. "qcom,cdc-micbias2-mv",
  2732. &prop_val);
  2733. if (!rc)
  2734. mb->micb2_mv = prop_val;
  2735. } else {
  2736. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2737. __func__);
  2738. }
  2739. /* MB3 */
  2740. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2741. NULL)) {
  2742. rc = wcd937x_read_of_property_u32(dev,
  2743. "qcom,cdc-micbias3-mv",
  2744. &prop_val);
  2745. if (!rc)
  2746. mb->micb3_mv = prop_val;
  2747. } else {
  2748. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2749. __func__);
  2750. }
  2751. }
  2752. static int wcd937x_reset_low(struct device *dev)
  2753. {
  2754. struct wcd937x_priv *wcd937x = NULL;
  2755. int rc = 0;
  2756. if (!dev)
  2757. return -ENODEV;
  2758. wcd937x = dev_get_drvdata(dev);
  2759. if (!wcd937x)
  2760. return -EINVAL;
  2761. if (!wcd937x->rst_np) {
  2762. dev_err(dev, "%s: reset gpio device node not specified\n",
  2763. __func__);
  2764. return -EINVAL;
  2765. }
  2766. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2767. if (rc) {
  2768. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2769. __func__);
  2770. return rc;
  2771. }
  2772. /* 20ms sleep required after pulling the reset gpio to LOW */
  2773. usleep_range(20, 30);
  2774. return rc;
  2775. }
  2776. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2777. {
  2778. struct wcd937x_pdata *pdata = NULL;
  2779. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2780. GFP_KERNEL);
  2781. if (!pdata)
  2782. return NULL;
  2783. pdata->rst_np = of_parse_phandle(dev->of_node,
  2784. "qcom,wcd-rst-gpio-node", 0);
  2785. if (!pdata->rst_np) {
  2786. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2787. __func__, "qcom,wcd-rst-gpio-node",
  2788. dev->of_node->full_name);
  2789. return NULL;
  2790. }
  2791. /* Parse power supplies */
  2792. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2793. &pdata->num_supplies);
  2794. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2795. dev_err(dev, "%s: no power supplies defined for codec\n",
  2796. __func__);
  2797. return NULL;
  2798. }
  2799. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2800. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2801. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2802. return pdata;
  2803. }
  2804. static int wcd937x_wakeup(void *handle, bool enable)
  2805. {
  2806. struct wcd937x_priv *priv;
  2807. if (!handle) {
  2808. pr_err("%s: NULL handle\n", __func__);
  2809. return -EINVAL;
  2810. }
  2811. priv = (struct wcd937x_priv *)handle;
  2812. if (!priv->tx_swr_dev) {
  2813. pr_err("%s: tx swr dev is NULL\n", __func__);
  2814. return -EINVAL;
  2815. }
  2816. if (enable)
  2817. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2818. else
  2819. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2820. }
  2821. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2822. {
  2823. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2824. __func__, irq);
  2825. return IRQ_HANDLED;
  2826. }
  2827. static int wcd937x_bind(struct device *dev)
  2828. {
  2829. int ret = 0, i = 0;
  2830. struct wcd937x_priv *wcd937x = NULL;
  2831. struct wcd937x_pdata *pdata = NULL;
  2832. struct wcd_ctrl_platform_data *plat_data = NULL;
  2833. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2834. if (!wcd937x)
  2835. return -ENOMEM;
  2836. dev_set_drvdata(dev, wcd937x);
  2837. pdata = wcd937x_populate_dt_data(dev);
  2838. if (!pdata) {
  2839. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2840. return -EINVAL;
  2841. }
  2842. wcd937x->dev = dev;
  2843. wcd937x->dev->platform_data = pdata;
  2844. wcd937x->rst_np = pdata->rst_np;
  2845. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2846. pdata->regulator, pdata->num_supplies);
  2847. if (!wcd937x->supplies) {
  2848. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2849. __func__);
  2850. goto err_bind_all;
  2851. }
  2852. plat_data = dev_get_platdata(dev->parent);
  2853. if (!plat_data) {
  2854. dev_err(dev, "%s: platform data from parent is NULL\n",
  2855. __func__);
  2856. ret = -EINVAL;
  2857. goto err_bind_all;
  2858. }
  2859. wcd937x->handle = (void *)plat_data->handle;
  2860. if (!wcd937x->handle) {
  2861. dev_err(dev, "%s: handle is NULL\n", __func__);
  2862. ret = -EINVAL;
  2863. goto err_bind_all;
  2864. }
  2865. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2866. if (!wcd937x->update_wcd_event) {
  2867. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2868. __func__);
  2869. ret = -EINVAL;
  2870. goto err_bind_all;
  2871. }
  2872. wcd937x->register_notifier = plat_data->register_notifier;
  2873. if (!wcd937x->register_notifier) {
  2874. dev_err(dev, "%s: register_notifier api is null!\n",
  2875. __func__);
  2876. ret = -EINVAL;
  2877. goto err_bind_all;
  2878. }
  2879. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2880. pdata->regulator,
  2881. pdata->num_supplies);
  2882. if (ret) {
  2883. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2884. __func__);
  2885. goto err_bind_all;
  2886. }
  2887. wcd937x_reset(dev);
  2888. /*
  2889. * Add 5msec delay to provide sufficient time for
  2890. * soundwire auto enumeration of slave devices as
  2891. * as per HW requirement.
  2892. */
  2893. usleep_range(5000, 5010);
  2894. wcd937x->wakeup = wcd937x_wakeup;
  2895. ret = component_bind_all(dev, wcd937x);
  2896. if (ret) {
  2897. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2898. __func__, ret);
  2899. goto err_bind_all;
  2900. }
  2901. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2902. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2903. if (ret) {
  2904. dev_err(dev, "Failed to read port mapping\n");
  2905. goto err;
  2906. }
  2907. ret = wcd937x_parse_port_params(dev, "qcom,swr-tx-port-params",
  2908. CODEC_TX);
  2909. if (ret) {
  2910. dev_err(dev, "Failed to read port params\n");
  2911. goto err;
  2912. }
  2913. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2914. if (!wcd937x->rx_swr_dev) {
  2915. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2916. __func__);
  2917. ret = -ENODEV;
  2918. goto err;
  2919. }
  2920. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2921. if (!wcd937x->tx_swr_dev) {
  2922. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2923. __func__);
  2924. ret = -ENODEV;
  2925. goto err;
  2926. }
  2927. swr_init_port_params(wcd937x->tx_swr_dev, SWR_NUM_PORTS,
  2928. wcd937x->swr_tx_port_params);
  2929. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2930. &wcd937x_regmap_config);
  2931. if (!wcd937x->regmap) {
  2932. dev_err(dev, "%s: Regmap init failed\n",
  2933. __func__);
  2934. goto err;
  2935. }
  2936. /* Set all interupts as edge triggered */
  2937. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2938. regmap_write(wcd937x->regmap,
  2939. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2940. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2941. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2942. wcd937x->irq_info.codec_name = "WCD937X";
  2943. wcd937x->irq_info.regmap = wcd937x->regmap;
  2944. wcd937x->irq_info.dev = dev;
  2945. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2946. if (ret) {
  2947. dev_err(dev, "%s: IRQ init failed: %d\n",
  2948. __func__, ret);
  2949. goto err;
  2950. }
  2951. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2952. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2953. if (ret < 0) {
  2954. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2955. goto err_irq;
  2956. }
  2957. /* default L1 power setting */
  2958. wcd937x->tx_ch_pwr[0] = 1;
  2959. wcd937x->tx_ch_pwr[1] = 1;
  2960. mutex_init(&wcd937x->micb_lock);
  2961. mutex_init(&wcd937x->ana_tx_clk_lock);
  2962. /* Request for watchdog interrupt */
  2963. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2964. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2965. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2966. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2967. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2968. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2969. /* Disable watchdog interrupt for HPH and AUX */
  2970. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2971. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2972. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2973. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2974. wcd937x_dai, ARRAY_SIZE(wcd937x_dai));
  2975. if (ret) {
  2976. dev_err(dev, "%s: Codec registration failed\n",
  2977. __func__);
  2978. goto err_irq;
  2979. }
  2980. return ret;
  2981. err_irq:
  2982. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2983. err:
  2984. component_unbind_all(dev, wcd937x);
  2985. err_bind_all:
  2986. dev_set_drvdata(dev, NULL);
  2987. kfree(pdata);
  2988. kfree(wcd937x);
  2989. return ret;
  2990. }
  2991. static void wcd937x_unbind(struct device *dev)
  2992. {
  2993. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2994. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2995. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2996. snd_soc_unregister_component(dev);
  2997. component_unbind_all(dev, wcd937x);
  2998. mutex_destroy(&wcd937x->micb_lock);
  2999. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  3000. dev_set_drvdata(dev, NULL);
  3001. kfree(pdata);
  3002. kfree(wcd937x);
  3003. }
  3004. static const struct of_device_id wcd937x_dt_match[] = {
  3005. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  3006. {}
  3007. };
  3008. static const struct component_master_ops wcd937x_comp_ops = {
  3009. .bind = wcd937x_bind,
  3010. .unbind = wcd937x_unbind,
  3011. };
  3012. static int wcd937x_compare_of(struct device *dev, void *data)
  3013. {
  3014. return dev->of_node == data;
  3015. }
  3016. static void wcd937x_release_of(struct device *dev, void *data)
  3017. {
  3018. of_node_put(data);
  3019. }
  3020. static int wcd937x_add_slave_components(struct device *dev,
  3021. struct component_match **matchptr)
  3022. {
  3023. struct device_node *np, *rx_node, *tx_node;
  3024. np = dev->of_node;
  3025. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3026. if (!rx_node) {
  3027. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3028. return -ENODEV;
  3029. }
  3030. of_node_get(rx_node);
  3031. component_match_add_release(dev, matchptr,
  3032. wcd937x_release_of,
  3033. wcd937x_compare_of,
  3034. rx_node);
  3035. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3036. if (!tx_node) {
  3037. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3038. return -ENODEV;
  3039. }
  3040. of_node_get(tx_node);
  3041. component_match_add_release(dev, matchptr,
  3042. wcd937x_release_of,
  3043. wcd937x_compare_of,
  3044. tx_node);
  3045. return 0;
  3046. }
  3047. static int wcd937x_probe(struct platform_device *pdev)
  3048. {
  3049. struct component_match *match = NULL;
  3050. int ret;
  3051. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  3052. if (ret)
  3053. return ret;
  3054. return component_master_add_with_match(&pdev->dev,
  3055. &wcd937x_comp_ops, match);
  3056. }
  3057. static int wcd937x_remove(struct platform_device *pdev)
  3058. {
  3059. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  3060. dev_set_drvdata(&pdev->dev, NULL);
  3061. return 0;
  3062. }
  3063. #ifdef CONFIG_PM_SLEEP
  3064. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  3065. SET_SYSTEM_SLEEP_PM_OPS(
  3066. wcd937x_suspend,
  3067. wcd937x_resume
  3068. )
  3069. };
  3070. #endif
  3071. static struct platform_driver wcd937x_codec_driver = {
  3072. .probe = wcd937x_probe,
  3073. .remove = wcd937x_remove,
  3074. .driver = {
  3075. .name = "wcd937x_codec",
  3076. .owner = THIS_MODULE,
  3077. .of_match_table = of_match_ptr(wcd937x_dt_match),
  3078. #ifdef CONFIG_PM_SLEEP
  3079. .pm = &wcd937x_dev_pm_ops,
  3080. #endif
  3081. .suppress_bind_attrs = true,
  3082. },
  3083. };
  3084. module_platform_driver(wcd937x_codec_driver);
  3085. MODULE_DESCRIPTION("WCD937X Codec driver");
  3086. MODULE_LICENSE("GPL v2");