e60a0a35f8
Update the voltage swing and pre-emphasis settings based on the latest hardware programming guide. Change-Id: If90db2833aba2bd0613276eff22f850bf34859e5 Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
362 sor
9.5 KiB
C
362 sor
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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*/
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#include "dp_catalog.h"
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#include "dp_reg.h"
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#include "dp_debug.h"
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#define dp_catalog_get_priv_v420(x) ({ \
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struct dp_catalog *catalog; \
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catalog = container_of(x, struct dp_catalog, x); \
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container_of(catalog->sub, \
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struct dp_catalog_private_v420, sub); \
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})
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#define dp_read(x) ({ \
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catalog->sub.read(catalog->dpc, io_data, x); \
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})
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#define dp_write(x, y) ({ \
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catalog->sub.write(catalog->dpc, io_data, x, y); \
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})
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#define MAX_VOLTAGE_LEVELS 4
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#define MAX_PRE_EMP_LEVELS 4
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static u8 const vm_pre_emphasis[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {
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{0x00, 0x0E, 0x16, 0xFF}, /* pe0, 0 db */
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{0x00, 0x0E, 0x16, 0xFF}, /* pe1, 3.5 db */
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{0x00, 0x0E, 0xFF, 0xFF}, /* pe2, 6.0 db */
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{0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
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};
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/* voltage swing, 0.2v and 1.0v are not support */
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static u8 const vm_voltage_swing[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {
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{0x07, 0x0F, 0x16, 0xFF}, /* sw0, 0.4v */
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{0x11, 0x1E, 0x1F, 0xFF}, /* sw1, 0.6 v */
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{0x1A, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
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{0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
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};
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static u8 const dp_pre_emp_hbr2_hbr3[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {
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{0x00, 0x0C, 0x15, 0x1B}, /* pe0, 0 db */
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{0x02, 0x0E, 0x16, 0xFF}, /* pe1, 3.5 db */
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{0x02, 0x11, 0xFF, 0xFF}, /* pe2, 6.0 db */
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{0x04, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
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};
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static u8 const dp_swing_hbr2_hbr3[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {
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{0x02, 0x12, 0x16, 0x1A}, /* sw0, 0.4v */
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{0x09, 0x19, 0x1F, 0xFF}, /* sw1, 0.6v */
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{0x10, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8v */
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{0x1F, 0xFF, 0xFF, 0xFF} /* sw1, 1.2v */
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};
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static u8 const dp_pre_emp_hbr_rbr[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {
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{0x00, 0x0E, 0x15, 0x1B}, /* pe0, 0 db */
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{0x00, 0x0E, 0x15, 0xFF}, /* pe1, 3.5 db */
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{0x00, 0x0E, 0xFF, 0xFF}, /* pe2, 6.0 db */
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{0x04, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
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};
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static u8 const dp_swing_hbr_rbr[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {
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{0x08, 0x0F, 0x16, 0x1F}, /* sw0, 0.4v */
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{0x11, 0x1E, 0x1F, 0xFF}, /* sw1, 0.6v */
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{0x16, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8v */
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{0x1F, 0xFF, 0xFF, 0xFF} /* sw1, 1.2v */
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};
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struct dp_catalog_private_v420 {
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struct device *dev;
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struct dp_catalog_sub sub;
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struct dp_catalog_io *io;
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struct dp_catalog *dpc;
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};
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static void dp_catalog_aux_setup_v420(struct dp_catalog_aux *aux,
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struct dp_aux_cfg *cfg)
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{
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struct dp_catalog_private_v420 *catalog;
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struct dp_io_data *io_data;
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int i = 0;
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if (!aux || !cfg) {
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DP_ERR("invalid input\n");
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return;
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}
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catalog = dp_catalog_get_priv_v420(aux);
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io_data = catalog->io->dp_phy;
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dp_write(DP_PHY_PD_CTL, 0x67);
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wmb(); /* make sure PD programming happened */
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/* Turn on BIAS current for PHY/PLL */
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io_data = catalog->io->dp_pll;
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dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17);
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wmb(); /* make sure BIAS programming happened */
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io_data = catalog->io->dp_phy;
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/* DP AUX CFG register programming */
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for (i = 0; i < PHY_AUX_CFG_MAX; i++) {
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DP_DEBUG("%s: offset=0x%08x, value=0x%08x\n",
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dp_phy_aux_config_type_to_string(i),
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cfg[i].offset, cfg[i].lut[cfg[i].current_index]);
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dp_write(cfg[i].offset, cfg[i].lut[cfg[i].current_index]);
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}
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wmb(); /* make sure DP AUX CFG programming happened */
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dp_write(DP_PHY_AUX_INTERRUPT_MASK_V420, 0x1F);
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}
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static void dp_catalog_aux_clear_hw_int_v420(struct dp_catalog_aux *aux)
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{
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struct dp_catalog_private_v420 *catalog;
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struct dp_io_data *io_data;
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u32 data = 0;
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if (!aux) {
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DP_ERR("invalid input\n");
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return;
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}
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catalog = dp_catalog_get_priv_v420(aux);
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io_data = catalog->io->dp_phy;
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data = dp_read(DP_PHY_AUX_INTERRUPT_STATUS_V420);
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dp_write(DP_PHY_AUX_INTERRUPT_CLEAR_V420, 0x1f);
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wmb(); /* make sure 0x1f is written before next write */
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dp_write(DP_PHY_AUX_INTERRUPT_CLEAR_V420, 0x9f);
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wmb(); /* make sure 0x9f is written before next write */
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dp_write(DP_PHY_AUX_INTERRUPT_CLEAR_V420, 0);
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wmb(); /* make sure register is cleared */
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}
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static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
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u32 rate, u32 stream_rate_khz)
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{
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u32 pixel_m, pixel_n;
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u32 mvid, nvid, reg_off = 0, mvid_off = 0, nvid_off = 0;
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u32 const nvid_fixed = 0x8000;
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u32 const link_rate_hbr2 = 540000;
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u32 const link_rate_hbr3 = 810000;
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struct dp_catalog_private_v420 *catalog;
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struct dp_io_data *io_data;
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if (!panel || !rate) {
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DP_ERR("invalid input\n");
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return;
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}
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if (panel->stream_id >= DP_STREAM_MAX) {
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DP_ERR("invalid stream id:%d\n", panel->stream_id);
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return;
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}
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catalog = dp_catalog_get_priv_v420(panel);
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io_data = catalog->io->dp_mmss_cc;
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if (panel->stream_id == DP_STREAM_1)
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reg_off = MMSS_DP_PIXEL1_M_V420 - MMSS_DP_PIXEL_M_V420;
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pixel_m = dp_read(MMSS_DP_PIXEL_M_V420 + reg_off);
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pixel_n = dp_read(MMSS_DP_PIXEL_N_V420 + reg_off);
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DP_DEBUG("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
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mvid = (pixel_m & 0xFFFF) * 5;
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nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
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if (nvid < nvid_fixed) {
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u32 temp;
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temp = (nvid_fixed / nvid) * nvid;
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mvid = (nvid_fixed / nvid) * mvid;
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nvid = temp;
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}
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DP_DEBUG("rate = %d\n", rate);
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if (panel->widebus_en)
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mvid <<= 1;
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if (link_rate_hbr2 == rate)
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nvid *= 2;
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if (link_rate_hbr3 == rate)
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nvid *= 3;
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io_data = catalog->io->dp_link;
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if (panel->stream_id == DP_STREAM_1) {
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mvid_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID;
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nvid_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID;
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}
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DP_DEBUG("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
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dp_write(DP_SOFTWARE_MVID + mvid_off, mvid);
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dp_write(DP_SOFTWARE_NVID + nvid_off, nvid);
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}
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static void dp_catalog_ctrl_phy_lane_cfg_v420(struct dp_catalog_ctrl *ctrl,
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bool flipped, u8 ln_cnt)
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{
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u32 info = 0x0;
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struct dp_catalog_private_v420 *catalog;
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struct dp_io_data *io_data;
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u8 orientation = BIT(!!flipped);
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if (!ctrl) {
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DP_ERR("invalid input\n");
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return;
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}
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catalog = dp_catalog_get_priv_v420(ctrl);
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io_data = catalog->io->dp_phy;
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info |= (ln_cnt & 0x0F);
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info |= ((orientation & 0x0F) << 4);
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DP_DEBUG("Shared Info = 0x%x\n", info);
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dp_write(DP_PHY_SPARE0_V420, info);
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}
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static void dp_catalog_ctrl_update_vx_px_v420(struct dp_catalog_ctrl *ctrl,
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u8 v_level, u8 p_level, bool high)
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{
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struct dp_catalog_private_v420 *catalog;
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struct dp_io_data *io_data;
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u8 value0, value1;
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u32 version;
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if (!ctrl || !((v_level < MAX_VOLTAGE_LEVELS)
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&& (p_level < MAX_PRE_EMP_LEVELS))) {
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DP_ERR("invalid input\n");
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return;
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}
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DP_DEBUG("hw: v=%d p=%d, high=%d\n", v_level, p_level, high);
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catalog = dp_catalog_get_priv_v420(ctrl);
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io_data = catalog->io->dp_ahb;
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version = dp_read(DP_HW_VERSION);
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/*
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* For DP controller versions 1.2.3 and 1.2.4
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*/
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if ((version == 0x10020003) || (version == 0x10020004)) {
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if (high) {
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value0 = dp_swing_hbr2_hbr3[v_level][p_level];
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value1 = dp_pre_emp_hbr2_hbr3[v_level][p_level];
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} else {
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value0 = dp_swing_hbr_rbr[v_level][p_level];
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value1 = dp_pre_emp_hbr_rbr[v_level][p_level];
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}
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} else {
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value0 = vm_voltage_swing[v_level][p_level];
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value1 = vm_pre_emphasis[v_level][p_level];
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}
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/* program default setting first */
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io_data = catalog->io->dp_ln_tx0;
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dp_write(TXn_TX_DRV_LVL_V420, 0x2A);
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dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
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io_data = catalog->io->dp_ln_tx1;
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dp_write(TXn_TX_DRV_LVL_V420, 0x2A);
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dp_write(TXn_TX_EMP_POST1_LVL, 0x20);
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/* Enable MUX to use Cursor values from these registers */
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value0 |= BIT(5);
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value1 |= BIT(5);
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/* Configure host and panel only if both values are allowed */
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if (value0 != 0xFF && value1 != 0xFF) {
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io_data = catalog->io->dp_ln_tx0;
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dp_write(TXn_TX_DRV_LVL_V420, value0);
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dp_write(TXn_TX_EMP_POST1_LVL, value1);
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io_data = catalog->io->dp_ln_tx1;
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dp_write(TXn_TX_DRV_LVL_V420, value0);
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dp_write(TXn_TX_EMP_POST1_LVL, value1);
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DP_DEBUG("hw: vx_value=0x%x px_value=0x%x\n",
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value0, value1);
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} else {
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DP_ERR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
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v_level, value0, p_level, value1);
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}
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}
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static void dp_catalog_ctrl_lane_pnswap_v420(struct dp_catalog_ctrl *ctrl,
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u8 ln_pnswap)
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{
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struct dp_catalog_private_v420 *catalog;
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struct dp_io_data *io_data;
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u32 cfg0, cfg1;
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catalog = dp_catalog_get_priv_v420(ctrl);
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cfg0 = 0x0a;
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cfg1 = 0x0a;
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cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;
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cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;
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cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;
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cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;
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io_data = catalog->io->dp_ln_tx0;
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dp_write(TXn_TX_POL_INV_V420, cfg0);
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io_data = catalog->io->dp_ln_tx1;
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dp_write(TXn_TX_POL_INV_V420, cfg1);
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}
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static void dp_catalog_put_v420(struct dp_catalog *catalog)
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{
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struct dp_catalog_private_v420 *catalog_priv;
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if (!catalog)
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return;
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catalog_priv = container_of(catalog->sub,
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struct dp_catalog_private_v420, sub);
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devm_kfree(catalog_priv->dev, catalog_priv);
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}
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struct dp_catalog_sub *dp_catalog_get_v420(struct device *dev,
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struct dp_catalog *catalog, struct dp_catalog_io *io)
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{
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struct dp_catalog_private_v420 *catalog_priv;
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if (!dev || !catalog) {
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DP_ERR("invalid input\n");
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return ERR_PTR(-EINVAL);
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}
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catalog_priv = devm_kzalloc(dev, sizeof(*catalog_priv), GFP_KERNEL);
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if (!catalog_priv)
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return ERR_PTR(-ENOMEM);
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catalog_priv->dev = dev;
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catalog_priv->io = io;
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catalog_priv->dpc = catalog;
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catalog_priv->sub.put = dp_catalog_put_v420;
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catalog->aux.setup = dp_catalog_aux_setup_v420;
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catalog->aux.clear_hw_interrupts = dp_catalog_aux_clear_hw_int_v420;
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catalog->panel.config_msa = dp_catalog_panel_config_msa_v420;
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catalog->ctrl.phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg_v420;
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catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v420;
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catalog->ctrl.lane_pnswap = dp_catalog_ctrl_lane_pnswap_v420;
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return &catalog_priv->sub;
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}
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