msm_cvp_platform.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/debugfs.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/init.h>
  8. #include <linux/ioctl.h>
  9. #include <linux/list.h>
  10. #include <linux/module.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/types.h>
  15. #include <linux/version.h>
  16. #include <linux/io.h>
  17. #include <linux/of_fdt.h>
  18. #include "msm_cvp_internal.h"
  19. #include "msm_cvp_debug.h"
  20. #include "cvp_hfi_api.h"
  21. #include "cvp_hfi.h"
  22. #define UBWC_CONFIG(mco, mlo, hbo, bslo, bso, rs, mc, ml, hbb, bsl, bsp) \
  23. { \
  24. .override_bit_info.max_channel_override = mco, \
  25. .override_bit_info.mal_length_override = mlo, \
  26. .override_bit_info.hb_override = hbo, \
  27. .override_bit_info.bank_swzl_level_override = bslo, \
  28. .override_bit_info.bank_spreading_override = bso, \
  29. .override_bit_info.reserved = rs, \
  30. .max_channels = mc, \
  31. .mal_length = ml, \
  32. .highest_bank_bit = hbb, \
  33. .bank_swzl_level = bsl, \
  34. .bank_spreading = bsp, \
  35. }
  36. static struct msm_cvp_common_data default_common_data[] = {
  37. {
  38. .key = "qcom,never-unload-fw",
  39. .value = 1,
  40. },
  41. };
  42. static struct msm_cvp_common_data sm8450_common_data[] = {
  43. {
  44. .key = "qcom,auto-pil",
  45. .value = 1,
  46. },
  47. {
  48. .key = "qcom,never-unload-fw",
  49. .value = 1,
  50. },
  51. {
  52. .key = "qcom,sw-power-collapse",
  53. .value = 1,
  54. },
  55. {
  56. .key = "qcom,domain-attr-non-fatal-faults",
  57. .value = 0,
  58. },
  59. {
  60. .key = "qcom,max-secure-instances",
  61. .value = 2, /*
  62. * As per design driver allows 3rd
  63. * instance as well since the secure
  64. * flags were updated later for the
  65. * current instance. Hence total
  66. * secure sessions would be
  67. * max-secure-instances + 1.
  68. */
  69. },
  70. {
  71. .key = "qcom,max-ssr-allowed",
  72. .value = 1, /*
  73. * Maxinum number of SSR before BUG_ON
  74. */
  75. },
  76. {
  77. .key = "qcom,power-collapse-delay",
  78. .value = 3000,
  79. },
  80. {
  81. .key = "qcom,hw-resp-timeout",
  82. .value = 2000,
  83. },
  84. {
  85. .key = "qcom,dsp-resp-timeout",
  86. .value = 1000,
  87. },
  88. {
  89. .key = "qcom,debug-timeout",
  90. .value = 0,
  91. },
  92. {
  93. .key = "qcom,dsp-enabled",
  94. .value = 1,
  95. }
  96. };
  97. /* Default UBWC config for LPDDR5 */
  98. static struct msm_cvp_ubwc_config_data kona_ubwc_data[] = {
  99. UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0),
  100. };
  101. static struct msm_cvp_platform_data default_data = {
  102. .common_data = default_common_data,
  103. .common_data_length = ARRAY_SIZE(default_common_data),
  104. .sku_version = 0,
  105. .vpu_ver = VPU_VERSION_5,
  106. .ubwc_config = 0x0,
  107. };
  108. static struct msm_cvp_platform_data sm8450_data = {
  109. .common_data = sm8450_common_data,
  110. .common_data_length = ARRAY_SIZE(sm8450_common_data),
  111. .sku_version = 0,
  112. .vpu_ver = VPU_VERSION_5,
  113. .ubwc_config = kona_ubwc_data,
  114. };
  115. static const struct of_device_id msm_cvp_dt_match[] = {
  116. {
  117. .compatible = "qcom,waipio-cvp",
  118. .data = &sm8450_data,
  119. },
  120. {},
  121. };
  122. const struct msm_cvp_hfi_defs cvp_hfi_defs[] = {
  123. {
  124. .size = HFI_DFS_CONFIG_CMD_SIZE,
  125. .type = HFI_CMD_SESSION_CVP_DFS_CONFIG,
  126. .is_config_pkt = true,
  127. .resp = HAL_NO_RESP,
  128. },
  129. {
  130. .size = HFI_DFS_FRAME_CMD_SIZE,
  131. .type = HFI_CMD_SESSION_CVP_DFS_FRAME,
  132. .is_config_pkt = false,
  133. .resp = HAL_NO_RESP,
  134. },
  135. {
  136. .size = 0xFFFFFFFF,
  137. .type = HFI_CMD_SESSION_CVP_SGM_OF_CONFIG,
  138. .is_config_pkt = true,
  139. .resp = HAL_NO_RESP,
  140. },
  141. {
  142. .size = 0xFFFFFFFF,
  143. .type = HFI_CMD_SESSION_CVP_SGM_OF_FRAME,
  144. .is_config_pkt = false,
  145. .resp = HAL_NO_RESP,
  146. },
  147. {
  148. .size = 0xFFFFFFFF,
  149. .type = HFI_CMD_SESSION_CVP_WARP_NCC_CONFIG,
  150. .is_config_pkt = true,
  151. .resp = HAL_NO_RESP,
  152. },
  153. {
  154. .size = 0xFFFFFFFF,
  155. .type = HFI_CMD_SESSION_CVP_WARP_NCC_FRAME,
  156. .is_config_pkt = false,
  157. .resp = HAL_NO_RESP,
  158. },
  159. {
  160. .size = 0xFFFFFFFF,
  161. .type = HFI_CMD_SESSION_CVP_WARP_CONFIG,
  162. .is_config_pkt = true,
  163. .resp = HAL_NO_RESP,
  164. },
  165. {
  166. .size = 0xFFFFFFFF,
  167. .type = HFI_CMD_SESSION_CVP_WARP_DS_PARAMS,
  168. .is_config_pkt = true,
  169. .resp = HAL_NO_RESP,
  170. },
  171. {
  172. .size = 0xFFFFFFFF,
  173. .type = HFI_CMD_SESSION_CVP_WARP_FRAME,
  174. .is_config_pkt = false,
  175. .resp = HAL_NO_RESP,
  176. },
  177. {
  178. .size = HFI_DMM_CONFIG_CMD_SIZE,
  179. .type = HFI_CMD_SESSION_CVP_DMM_CONFIG,
  180. .is_config_pkt = true,
  181. .resp = HAL_NO_RESP,
  182. },
  183. {
  184. .size = 0xFFFFFFFF,
  185. .type = HFI_CMD_SESSION_CVP_DMM_PARAMS,
  186. .is_config_pkt = true,
  187. .resp = HAL_NO_RESP,
  188. },
  189. {
  190. .size = HFI_DMM_FRAME_CMD_SIZE,
  191. .type = HFI_CMD_SESSION_CVP_DMM_FRAME,
  192. .is_config_pkt = false,
  193. .resp = HAL_NO_RESP,
  194. },
  195. {
  196. .size = HFI_PERSIST_CMD_SIZE,
  197. .type = HFI_CMD_SESSION_CVP_SET_PERSIST_BUFFERS,
  198. .is_config_pkt = true,
  199. .resp = HAL_NO_RESP,
  200. },
  201. {
  202. .size = 0xffffffff,
  203. .type = HFI_CMD_SESSION_CVP_RELEASE_PERSIST_BUFFERS,
  204. .is_config_pkt = true,
  205. .resp = HAL_NO_RESP,
  206. },
  207. {
  208. .size = HFI_DS_CMD_SIZE,
  209. .type = HFI_CMD_SESSION_CVP_DS,
  210. .is_config_pkt = false,
  211. .resp = HAL_NO_RESP,
  212. },
  213. {
  214. .size = HFI_OF_CONFIG_CMD_SIZE,
  215. .type = HFI_CMD_SESSION_CVP_CV_TME_CONFIG,
  216. .is_config_pkt = true,
  217. .resp = HAL_NO_RESP,
  218. },
  219. {
  220. .size = HFI_OF_FRAME_CMD_SIZE,
  221. .type = HFI_CMD_SESSION_CVP_CV_TME_FRAME,
  222. .is_config_pkt = false,
  223. .resp = HAL_NO_RESP,
  224. },
  225. {
  226. .size = HFI_ODT_CONFIG_CMD_SIZE,
  227. .type = HFI_CMD_SESSION_CVP_CV_ODT_CONFIG,
  228. .is_config_pkt = true,
  229. .resp = HAL_NO_RESP,
  230. },
  231. {
  232. .size = HFI_ODT_FRAME_CMD_SIZE,
  233. .type = HFI_CMD_SESSION_CVP_CV_ODT_FRAME,
  234. .is_config_pkt = false,
  235. .resp = HAL_NO_RESP,
  236. },
  237. {
  238. .size = HFI_OD_CONFIG_CMD_SIZE,
  239. .type = HFI_CMD_SESSION_CVP_CV_OD_CONFIG,
  240. .is_config_pkt = true,
  241. .resp = HAL_NO_RESP,
  242. },
  243. {
  244. .size = HFI_OD_FRAME_CMD_SIZE,
  245. .type = HFI_CMD_SESSION_CVP_CV_OD_FRAME,
  246. .is_config_pkt = false,
  247. .resp = HAL_NO_RESP,
  248. },
  249. {
  250. .size = HFI_NCC_CONFIG_CMD_SIZE,
  251. .type = HFI_CMD_SESSION_CVP_NCC_CONFIG,
  252. .is_config_pkt = true,
  253. .resp = HAL_NO_RESP,
  254. },
  255. {
  256. .size = HFI_NCC_FRAME_CMD_SIZE,
  257. .type = HFI_CMD_SESSION_CVP_NCC_FRAME,
  258. .is_config_pkt = false,
  259. .resp = HAL_NO_RESP,
  260. },
  261. {
  262. .size = HFI_ICA_CONFIG_CMD_SIZE,
  263. .type = HFI_CMD_SESSION_CVP_ICA_CONFIG,
  264. .is_config_pkt = true,
  265. .resp = HAL_NO_RESP,
  266. },
  267. {
  268. .size = HFI_ICA_FRAME_CMD_SIZE,
  269. .type = HFI_CMD_SESSION_CVP_ICA_FRAME,
  270. .is_config_pkt = false,
  271. .resp = HAL_NO_RESP,
  272. },
  273. {
  274. .size = HFI_HCD_CONFIG_CMD_SIZE,
  275. .type = HFI_CMD_SESSION_CVP_HCD_CONFIG,
  276. .is_config_pkt = true,
  277. .resp = HAL_NO_RESP,
  278. },
  279. {
  280. .size = HFI_HCD_FRAME_CMD_SIZE,
  281. .type = HFI_CMD_SESSION_CVP_HCD_FRAME,
  282. .is_config_pkt = false,
  283. .resp = HAL_NO_RESP,
  284. },
  285. {
  286. .size = HFI_DCM_CONFIG_CMD_SIZE,
  287. .type = HFI_CMD_SESSION_CVP_DC_CONFIG,
  288. .is_config_pkt = true,
  289. .resp = HAL_NO_RESP,
  290. },
  291. {
  292. .size = HFI_DCM_FRAME_CMD_SIZE,
  293. .type = HFI_CMD_SESSION_CVP_DC_FRAME,
  294. .is_config_pkt = false,
  295. .resp = HAL_NO_RESP,
  296. },
  297. {
  298. .size = HFI_DCM_CONFIG_CMD_SIZE,
  299. .type = HFI_CMD_SESSION_CVP_DCM_CONFIG,
  300. .is_config_pkt = true,
  301. .resp = HAL_NO_RESP,
  302. },
  303. {
  304. .size = HFI_DCM_FRAME_CMD_SIZE,
  305. .type = HFI_CMD_SESSION_CVP_DCM_FRAME,
  306. .is_config_pkt = false,
  307. .resp = HAL_NO_RESP,
  308. },
  309. {
  310. .size = HFI_PYS_HCD_CONFIG_CMD_SIZE,
  311. .type = HFI_CMD_SESSION_CVP_PYS_HCD_CONFIG,
  312. .is_config_pkt = true,
  313. .resp = HAL_NO_RESP,
  314. },
  315. {
  316. .size = HFI_PYS_HCD_FRAME_CMD_SIZE,
  317. .type = HFI_CMD_SESSION_CVP_PYS_HCD_FRAME,
  318. .is_config_pkt = false,
  319. .resp = HAL_NO_RESP,
  320. },
  321. {
  322. .size = 0xFFFFFFFF,
  323. .type = HFI_CMD_SESSION_CVP_SET_MODEL_BUFFERS,
  324. .is_config_pkt = true,
  325. .resp = HAL_NO_RESP,
  326. },
  327. {
  328. .size = 0xFFFFFFFF,
  329. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_BUFFERS,
  330. .is_config_pkt = true,
  331. .resp = HAL_NO_RESP,
  332. },
  333. {
  334. .size = 0xFFFFFFFF,
  335. .type = HFI_CMD_SESSION_CVP_RELEASE_SNAPSHOT_BUFFERS,
  336. .is_config_pkt = true,
  337. .resp = HAL_NO_RESP,
  338. },
  339. {
  340. .size = 0xFFFFFFFF,
  341. .type = HFI_CMD_SESSION_CVP_SET_SNAPSHOT_MODE,
  342. .is_config_pkt = true,
  343. .resp = HAL_NO_RESP,
  344. },
  345. {
  346. .size = 0xFFFFFFFF,
  347. .type = HFI_CMD_SESSION_CVP_SNAPSHOT_WRITE_DONE,
  348. .is_config_pkt = true,
  349. .resp = HAL_NO_RESP,
  350. },
  351. {
  352. .size = 0xFFFFFFFF,
  353. .type = HFI_CMD_SESSION_CVP_FD_CONFIG,
  354. .is_config_pkt = true,
  355. .resp = HAL_NO_RESP,
  356. },
  357. {
  358. .size = 0xFFFFFFFF,
  359. .type = HFI_CMD_SESSION_CVP_FD_FRAME,
  360. .is_config_pkt = false,
  361. .resp = HAL_NO_RESP,
  362. },
  363. };
  364. int get_pkt_array_size(void)
  365. {
  366. return ARRAY_SIZE(cvp_hfi_defs);
  367. }
  368. int get_pkt_index(struct cvp_hal_session_cmd_pkt *hdr)
  369. {
  370. int i;
  371. for (i = 0; i < get_pkt_array_size(); i++)
  372. if (cvp_hfi_defs[i].type == hdr->packet_type)
  373. return i;
  374. return -EINVAL;
  375. }
  376. MODULE_DEVICE_TABLE(of, msm_cvp_dt_match);
  377. void *cvp_get_drv_data(struct device *dev)
  378. {
  379. struct msm_cvp_platform_data *driver_data;
  380. const struct of_device_id *match;
  381. uint32_t ddr_type = DDR_TYPE_LPDDR5;
  382. driver_data = &default_data;
  383. if (!IS_ENABLED(CONFIG_OF) || !dev->of_node)
  384. goto exit;
  385. match = of_match_node(msm_cvp_dt_match, dev->of_node);
  386. if (!match)
  387. return NULL;
  388. driver_data = (struct msm_cvp_platform_data *)match->data;
  389. if (!strcmp(match->compatible, "qcom,waipio-cvp")) {
  390. ddr_type = of_fdt_get_ddrtype();
  391. if (ddr_type == -ENOENT) {
  392. dprintk(CVP_ERR,
  393. "Failed to get ddr type, use LPDDR5\n");
  394. }
  395. if (driver_data->ubwc_config &&
  396. (ddr_type == DDR_TYPE_LPDDR4 ||
  397. ddr_type == DDR_TYPE_LPDDR4X))
  398. driver_data->ubwc_config->highest_bank_bit = 15;
  399. dprintk(CVP_CORE, "DDR Type 0x%x hbb 0x%x\n",
  400. ddr_type, driver_data->ubwc_config ?
  401. driver_data->ubwc_config->highest_bank_bit : -1);
  402. }
  403. exit:
  404. return driver_data;
  405. }