msm_cvp_internal.h 8.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _MSM_CVP_INTERNAL_H_
  6. #define _MSM_CVP_INTERNAL_H_
  7. #include <linux/atomic.h>
  8. #include <linux/list.h>
  9. #include <linux/time.h>
  10. #include <linux/types.h>
  11. #include <linux/completion.h>
  12. #include <linux/wait.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interconnect.h>
  15. #include <linux/kref.h>
  16. #include <linux/cdev.h>
  17. #include <linux/slab.h>
  18. #include <linux/kthread.h>
  19. #include <linux/dma-mapping.h>
  20. #include "msm_cvp_core.h"
  21. #include <media/msm_media_info.h>
  22. #include <media/msm_eva_private.h>
  23. #include "cvp_hfi_api.h"
  24. #include "cvp_hfi_helper.h"
  25. #include <synx_api.h>
  26. #define MAX_SUPPORTED_INSTANCES 16
  27. #define MAX_NAME_LENGTH 64
  28. #define MAX_DEBUGFS_NAME 50
  29. #define MAX_DSP_INIT_ATTEMPTS 16
  30. #define FENCE_WAIT_SIGNAL_TIMEOUT 100
  31. #define FENCE_WAIT_SIGNAL_RETRY_TIMES 20
  32. #define FENCE_BIT (1ULL << 63)
  33. #define FENCE_DMM_ICA_ENABLED_IDX 0
  34. #define FENCE_DMM_DS_IDX 1
  35. #define FENCE_DMM_OUTPUT_IDX 7
  36. #define SYS_MSG_START HAL_SYS_INIT_DONE
  37. #define SYS_MSG_END HAL_SYS_ERROR
  38. #define SESSION_MSG_START HAL_SESSION_EVENT_CHANGE
  39. #define SESSION_MSG_END HAL_SESSION_ERROR
  40. #define SYS_MSG_INDEX(__msg) (__msg - SYS_MSG_START)
  41. #define SESSION_MSG_INDEX(__msg) (__msg - SESSION_MSG_START)
  42. #define ARP_BUF_SIZE 0x300000
  43. #define CVP_RT_PRIO_THRESHOLD 1
  44. struct msm_cvp_inst;
  45. enum cvp_core_state {
  46. CVP_CORE_UNINIT = 0,
  47. CVP_CORE_INIT,
  48. CVP_CORE_INIT_DONE,
  49. };
  50. /*
  51. * Do not change the enum values unless
  52. * you know what you are doing
  53. */
  54. enum hw_block {
  55. CVP_FDU = 0x0001,
  56. CVP_ICA,
  57. CVP_MPU,
  58. CVP_OD
  59. };
  60. enum instance_state {
  61. MSM_CVP_CORE_UNINIT_DONE = 0x0001,
  62. MSM_CVP_CORE_INIT,
  63. MSM_CVP_CORE_INIT_DONE,
  64. MSM_CVP_OPEN,
  65. MSM_CVP_OPEN_DONE,
  66. MSM_CVP_CLOSE,
  67. MSM_CVP_CLOSE_DONE,
  68. MSM_CVP_CORE_UNINIT,
  69. MSM_CVP_CORE_INVALID
  70. };
  71. enum dsp_state {
  72. DSP_INVALID,
  73. DSP_UNINIT,
  74. DSP_PROBED,
  75. DSP_READY,
  76. DSP_SUSPEND,
  77. DSP_INACTIVE,
  78. };
  79. struct msm_cvp_common_data {
  80. char key[128];
  81. int value;
  82. };
  83. enum sku_version {
  84. SKU_VERSION_0 = 0,
  85. SKU_VERSION_1,
  86. SKU_VERSION_2,
  87. };
  88. enum vpu_version {
  89. VPU_VERSION_4 = 1,
  90. VPU_VERSION_5,
  91. };
  92. struct msm_cvp_ubwc_config_data {
  93. struct {
  94. u32 max_channel_override : 1;
  95. u32 mal_length_override : 1;
  96. u32 hb_override : 1;
  97. u32 bank_swzl_level_override : 1;
  98. u32 bank_spreading_override : 1;
  99. u32 reserved : 27;
  100. } override_bit_info;
  101. u32 max_channels;
  102. u32 mal_length;
  103. u32 highest_bank_bit;
  104. u32 bank_swzl_level;
  105. u32 bank_spreading;
  106. };
  107. struct msm_cvp_platform_data {
  108. struct msm_cvp_common_data *common_data;
  109. unsigned int common_data_length;
  110. unsigned int sku_version;
  111. uint32_t vpu_ver;
  112. struct msm_cvp_ubwc_config_data *ubwc_config;
  113. };
  114. struct msm_cvp_drv {
  115. struct mutex lock;
  116. struct list_head cores;
  117. int num_cores;
  118. struct dentry *debugfs_root;
  119. int thermal_level;
  120. u32 sku_version;
  121. struct kmem_cache *msg_cache;
  122. struct kmem_cache *frame_cache;
  123. struct kmem_cache *buf_cache;
  124. struct kmem_cache *smem_cache;
  125. char fw_version[CVP_VERSION_LENGTH];
  126. };
  127. enum profiling_points {
  128. SYS_INIT = 0,
  129. SESSION_INIT,
  130. LOAD_RESOURCES,
  131. FRAME_PROCESSING,
  132. FW_IDLE,
  133. MAX_PROFILING_POINTS,
  134. };
  135. struct cvp_clock_data {
  136. int buffer_counter;
  137. int load;
  138. int load_low;
  139. int load_norm;
  140. int load_high;
  141. int min_threshold;
  142. int max_threshold;
  143. unsigned long bitrate;
  144. unsigned long min_freq;
  145. unsigned long curr_freq;
  146. u32 ddr_bw;
  147. u32 sys_cache_bw;
  148. u32 operating_rate;
  149. u32 core_id;
  150. bool low_latency_mode;
  151. bool turbo_mode;
  152. };
  153. struct cvp_profile_data {
  154. int start;
  155. int stop;
  156. int cumulative;
  157. char name[64];
  158. int sampling;
  159. int average;
  160. };
  161. struct msm_cvp_debug {
  162. struct cvp_profile_data pdata[MAX_PROFILING_POINTS];
  163. int profile;
  164. int samples;
  165. };
  166. enum msm_cvp_modes {
  167. CVP_SECURE = BIT(0),
  168. CVP_TURBO = BIT(1),
  169. CVP_THUMBNAIL = BIT(2),
  170. CVP_LOW_POWER = BIT(3),
  171. CVP_REALTIME = BIT(4),
  172. };
  173. #define MAX_NUM_MSGS_PER_SESSION 128
  174. #define CVP_MAX_WAIT_TIME 2000
  175. struct cvp_session_msg {
  176. struct list_head node;
  177. struct cvp_hfi_msg_session_hdr_ext pkt;
  178. };
  179. struct cvp_session_queue {
  180. spinlock_t lock;
  181. enum queue_state state;
  182. unsigned int msg_count;
  183. struct list_head msgs;
  184. wait_queue_head_t wq;
  185. };
  186. #define CVP_CYCLE_STAT_SIZE 8
  187. struct cvp_cycle_stat {
  188. u32 busy[CVP_CYCLE_STAT_SIZE];
  189. u32 total;
  190. u32 idx;
  191. u32 size;
  192. };
  193. struct cvp_cycle_info {
  194. u32 sum_fps[HFI_MAX_HW_THREADS];
  195. u32 hi_ctrl_lim[HFI_MAX_HW_THREADS];
  196. u32 lo_ctrl_lim[HFI_MAX_HW_THREADS];
  197. struct cvp_cycle_stat cycle[HFI_MAX_HW_THREADS];
  198. unsigned long conf_freq;
  199. };
  200. struct cvp_session_prop {
  201. u32 type;
  202. u32 kernel_mask;
  203. u32 priority;
  204. u32 is_secure;
  205. u32 dsp_mask;
  206. u32 fthread_nr;
  207. u32 fdu_cycles;
  208. u32 od_cycles;
  209. u32 mpu_cycles;
  210. u32 ica_cycles;
  211. u32 fw_cycles;
  212. u32 fdu_op_cycles;
  213. u32 od_op_cycles;
  214. u32 mpu_op_cycles;
  215. u32 ica_op_cycles;
  216. u32 fw_op_cycles;
  217. u32 ddr_bw;
  218. u32 ddr_op_bw;
  219. u32 ddr_cache;
  220. u32 ddr_op_cache;
  221. u32 fps[HFI_MAX_HW_THREADS];
  222. u32 dump_offset;
  223. u32 dump_size;
  224. };
  225. enum cvp_event_t {
  226. CVP_NO_EVENT,
  227. CVP_SSR_EVENT = 1,
  228. CVP_SYS_ERROR_EVENT,
  229. CVP_MAX_CLIENTS_EVENT,
  230. CVP_HW_UNSUPPORTED_EVENT,
  231. CVP_INVALID_EVENT,
  232. CVP_DUMP_EVENT,
  233. };
  234. struct cvp_session_event {
  235. spinlock_t lock;
  236. enum cvp_event_t event;
  237. wait_queue_head_t wq;
  238. };
  239. #define MAX_ENTRIES 64
  240. struct smem_data {
  241. u32 size;
  242. u32 flags;
  243. u32 device_addr;
  244. u32 bitmap_index;
  245. u32 refcount;
  246. };
  247. struct cvp_buf_data {
  248. u32 device_addr;
  249. u32 size;
  250. };
  251. struct inst_snapshot {
  252. void *session;
  253. u32 smem_index;
  254. u32 dsp_index;
  255. u32 persist_index;
  256. struct smem_data smem_log[MAX_ENTRIES];
  257. struct cvp_buf_data dsp_buf_log[MAX_ENTRIES];
  258. struct cvp_buf_data persist_buf_log[MAX_ENTRIES];
  259. };
  260. struct cvp_noc_log {
  261. u32 err_ctrl_swid_low;
  262. u32 err_ctrl_swid_high;
  263. u32 err_ctrl_mainctl_low;
  264. u32 err_ctrl_errvld_low;
  265. u32 err_ctrl_errclr_low;
  266. u32 err_ctrl_errlog0_low;
  267. u32 err_ctrl_errlog0_high;
  268. u32 err_ctrl_errlog1_low;
  269. u32 err_ctrl_errlog1_high;
  270. u32 err_ctrl_errlog2_low;
  271. u32 err_ctrl_errlog2_high;
  272. u32 err_ctrl_errlog3_low;
  273. u32 err_ctrl_errlog3_high;
  274. u32 err_core_swid_low;
  275. u32 err_core_swid_high;
  276. u32 err_core_mainctl_low;
  277. u32 err_core_errvld_low;
  278. u32 err_core_errclr_low;
  279. u32 err_core_errlog0_low;
  280. u32 err_core_errlog0_high;
  281. u32 err_core_errlog1_low;
  282. u32 err_core_errlog1_high;
  283. u32 err_core_errlog2_low;
  284. u32 err_core_errlog2_high;
  285. u32 err_core_errlog3_low;
  286. u32 err_core_errlog3_high;
  287. u32 arp_test_bus[16];
  288. u32 dma_test_bus[512];
  289. };
  290. struct cvp_debug_log {
  291. struct cvp_noc_log noc_log;
  292. u32 snapshot_index;
  293. struct inst_snapshot snapshot[16];
  294. };
  295. struct msm_cvp_core {
  296. struct list_head list;
  297. struct mutex lock;
  298. struct mutex clk_lock;
  299. int id;
  300. dev_t dev_num;
  301. struct cdev cdev;
  302. struct class *class;
  303. struct device *dev;
  304. struct cvp_hfi_device *device;
  305. struct msm_cvp_platform_data *platform_data;
  306. struct list_head instances;
  307. struct dentry *debugfs_root;
  308. enum cvp_core_state state;
  309. struct completion completions[SYS_MSG_END - SYS_MSG_START + 1];
  310. enum msm_cvp_hfi_type hfi_type;
  311. struct msm_cvp_platform_resources resources;
  312. struct msm_cvp_capability *capabilities;
  313. struct delayed_work fw_unload_work;
  314. struct work_struct ssr_work;
  315. enum hal_ssr_trigger_type ssr_type;
  316. u32 smmu_fault_count;
  317. u32 last_fault_addr;
  318. u32 ssr_count;
  319. bool trigger_ssr;
  320. unsigned long curr_freq;
  321. struct cvp_cycle_info dyn_clk;
  322. atomic64_t kernel_trans_id;
  323. struct cvp_debug_log log;
  324. };
  325. struct msm_cvp_inst {
  326. struct list_head list;
  327. struct list_head dsp_list;
  328. struct mutex sync_lock, lock;
  329. struct msm_cvp_core *core;
  330. enum session_type session_type;
  331. u32 process_id;
  332. struct task_struct *task;
  333. struct cvp_session_queue session_queue;
  334. struct cvp_session_queue session_queue_fence;
  335. struct cvp_session_event event_handler;
  336. void *session;
  337. enum instance_state state;
  338. struct msm_cvp_list freqs;
  339. struct msm_cvp_list persistbufs;
  340. struct cvp_dmamap_cache dma_cache;
  341. struct msm_cvp_list cvpdspbufs;
  342. struct msm_cvp_list frames;
  343. struct completion completions[SESSION_MSG_END - SESSION_MSG_START + 1];
  344. struct dentry *debugfs_root;
  345. struct msm_cvp_debug debug;
  346. struct cvp_clock_data clk_data;
  347. enum msm_cvp_modes flags;
  348. struct msm_cvp_capability capability;
  349. struct kref kref;
  350. struct cvp_session_prop prop;
  351. u32 cur_cmd_type;
  352. struct synx_session synx_session_id;
  353. struct cvp_fence_queue fence_cmd_queue;
  354. };
  355. extern struct msm_cvp_drv *cvp_driver;
  356. void cvp_handle_cmd_response(enum hal_command_response cmd, void *data);
  357. int msm_cvp_trigger_ssr(struct msm_cvp_core *core,
  358. enum hal_ssr_trigger_type type);
  359. int msm_cvp_noc_error_info(struct msm_cvp_core *core);
  360. void msm_cvp_comm_handle_thermal_event(void);
  361. void msm_cvp_fw_unload_handler(struct work_struct *work);
  362. void msm_cvp_ssr_handler(struct work_struct *work);
  363. /*
  364. * XXX: normally should be in msm_cvp_core.h, but that's meant for public APIs,
  365. * whereas this is private
  366. */
  367. int msm_cvp_destroy(struct msm_cvp_inst *inst);
  368. void *cvp_get_drv_data(struct device *dev);
  369. #endif