wcd937x.c 94 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <linux/regmap.h>
  13. #include <linux/pm_runtime.h>
  14. #include <sound/soc.h>
  15. #include <sound/tlv.h>
  16. #include <soc/soundwire.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include <asoc/msm-cdc-supply.h>
  23. #include "wcd937x-registers.h"
  24. #include "wcd937x.h"
  25. #include "internal.h"
  26. #define DRV_NAME "wcd937x_codec"
  27. #define WCD9370_VARIANT 0
  28. #define WCD9375_VARIANT 5
  29. #define WCD937X_VARIANT_ENTRY_SIZE 32
  30. #define NUM_SWRS_DT_PARAMS 5
  31. #define WCD937X_VERSION_1_0 1
  32. #define WCD937X_VERSION_ENTRY_SIZE 32
  33. #define EAR_RX_PATH_AUX 1
  34. #define NUM_ATTEMPTS 5
  35. enum {
  36. CODEC_TX = 0,
  37. CODEC_RX,
  38. };
  39. enum {
  40. ALLOW_BUCK_DISABLE,
  41. HPH_COMP_DELAY,
  42. HPH_PA_DELAY,
  43. AMIC2_BCS_ENABLE,
  44. };
  45. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  46. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  47. static int wcd937x_handle_post_irq(void *data);
  48. static int wcd937x_reset(struct device *dev);
  49. static int wcd937x_reset_low(struct device *dev);
  50. static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
  51. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  52. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  53. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  54. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  55. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, 0x10),
  56. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, 0x20),
  57. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, 0x40),
  58. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, 0x80),
  59. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, 0x01),
  60. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, 0x02),
  61. REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, 0x04),
  62. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, 0x08),
  63. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, 0x10),
  64. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  65. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  66. REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  67. REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, 0x01),
  68. REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  69. REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  70. REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  71. };
  72. static struct regmap_irq_chip wcd937x_regmap_irq_chip = {
  73. .name = "wcd937x",
  74. .irqs = wcd937x_irqs,
  75. .num_irqs = ARRAY_SIZE(wcd937x_irqs),
  76. .num_regs = 3,
  77. .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
  78. .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
  79. .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
  80. .use_ack = 1,
  81. .clear_ack = 1,
  82. .type_base = WCD937X_DIGITAL_INTR_LEVEL_0,
  83. .runtime_pm = false,
  84. .handle_post_irq = wcd937x_handle_post_irq,
  85. .irq_drv_data = NULL,
  86. };
  87. static int wcd937x_handle_post_irq(void *data)
  88. {
  89. struct wcd937x_priv *wcd937x = data;
  90. u32 status1 = 0, status2 = 0, status3 = 0;
  91. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_0, &status1);
  92. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_1, &status2);
  93. regmap_read(wcd937x->regmap, WCD937X_DIGITAL_INTR_STATUS_2, &status3);
  94. wcd937x->tx_swr_dev->slave_irq_pending =
  95. ((status1 || status2 || status3) ? true : false);
  96. return IRQ_HANDLED;
  97. }
  98. static int wcd937x_init_reg(struct snd_soc_component *component)
  99. {
  100. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  101. 0x0E, 0x0E);
  102. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  103. 0x80, 0x80);
  104. usleep_range(1000, 1010);
  105. snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,
  106. 0x40, 0x40);
  107. usleep_range(1000, 1010);
  108. snd_soc_component_update_bits(component, WCD937X_LDORXTX_CONFIG,
  109. 0x10, 0x00);
  110. snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ,
  111. 0xF0, 0x80);
  112. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  113. 0x80, 0x80);
  114. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  115. 0x40, 0x40);
  116. usleep_range(10000, 10010);
  117. snd_soc_component_update_bits(component, WCD937X_ANA_BIAS,
  118. 0x40, 0x00);
  119. snd_soc_component_update_bits(component,
  120. WCD937X_HPH_SURGE_HPHLR_SURGE_EN,
  121. 0xFF, 0xD9);
  122. snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_1,
  123. 0xFF, 0xFA);
  124. snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_1,
  125. 0xFF, 0xFA);
  126. snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1,
  127. 0xFF, 0xFA);
  128. return 0;
  129. }
  130. static int wcd937x_set_port_params(struct snd_soc_component *component,
  131. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  132. u8 *ch_mask, u32 *ch_rate,
  133. u8 *port_type, u8 path)
  134. {
  135. int i, j;
  136. u8 num_ports = 0;
  137. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  138. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  139. switch (path) {
  140. case CODEC_RX:
  141. map = &wcd937x->rx_port_mapping;
  142. num_ports = wcd937x->num_rx_ports;
  143. break;
  144. case CODEC_TX:
  145. map = &wcd937x->tx_port_mapping;
  146. num_ports = wcd937x->num_tx_ports;
  147. break;
  148. default:
  149. dev_err(component->dev, "%s Invalid path selected %u\n",
  150. __func__, path);
  151. return -EINVAL;
  152. }
  153. for (i = 0; i <= num_ports; i++) {
  154. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  155. if ((*map)[i][j].slave_port_type == slv_prt_type)
  156. goto found;
  157. }
  158. }
  159. found:
  160. if (i > num_ports || j == MAX_CH_PER_PORT) {
  161. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  162. __func__, slv_prt_type);
  163. return -EINVAL;
  164. }
  165. *port_id = i;
  166. *num_ch = (*map)[i][j].num_ch;
  167. *ch_mask = (*map)[i][j].ch_mask;
  168. *ch_rate = (*map)[i][j].ch_rate;
  169. *port_type = (*map)[i][j].master_port_type;
  170. return 0;
  171. }
  172. static int wcd937x_parse_port_mapping(struct device *dev,
  173. char *prop, u8 path)
  174. {
  175. u32 *dt_array, map_size, map_length;
  176. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  177. u32 slave_port_type, master_port_type;
  178. u32 i, ch_iter = 0;
  179. int ret = 0;
  180. u8 *num_ports = NULL;
  181. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT] = NULL;
  182. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  183. switch (path) {
  184. case CODEC_RX:
  185. map = &wcd937x->rx_port_mapping;
  186. num_ports = &wcd937x->num_rx_ports;
  187. break;
  188. case CODEC_TX:
  189. map = &wcd937x->tx_port_mapping;
  190. num_ports = &wcd937x->num_tx_ports;
  191. break;
  192. default:
  193. dev_err(dev, "%s Invalid path selected %u\n",
  194. __func__, path);
  195. return -EINVAL;
  196. }
  197. if (!of_find_property(dev->of_node, prop,
  198. &map_size)) {
  199. dev_err(dev, "missing port mapping prop %s\n", prop);
  200. ret = -EINVAL;
  201. goto err;
  202. }
  203. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  204. dt_array = kzalloc(map_size, GFP_KERNEL);
  205. if (!dt_array) {
  206. ret = -ENOMEM;
  207. goto err;
  208. }
  209. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  210. NUM_SWRS_DT_PARAMS * map_length);
  211. if (ret) {
  212. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  213. __func__, prop);
  214. ret = -EINVAL;
  215. goto err_pdata_fail;
  216. }
  217. for (i = 0; i < map_length; i++) {
  218. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  219. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  220. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  221. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  222. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  223. if (port_num != old_port_num)
  224. ch_iter = 0;
  225. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  226. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  227. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  228. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  229. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  230. old_port_num = port_num;
  231. }
  232. *num_ports = port_num;
  233. kfree(dt_array);
  234. return 0;
  235. err_pdata_fail:
  236. kfree(dt_array);
  237. err:
  238. return ret;
  239. }
  240. static int wcd937x_tx_connect_port(struct snd_soc_component *component,
  241. u8 slv_port_type, u8 enable)
  242. {
  243. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  244. u8 port_id;
  245. u8 num_ch;
  246. u8 ch_mask;
  247. u32 ch_rate;
  248. u8 ch_type = 0;
  249. int slave_port_idx;
  250. u8 num_port = 1;
  251. int ret = 0;
  252. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  253. &num_ch, &ch_mask, &ch_rate,
  254. &ch_type, CODEC_TX);
  255. if (ret)
  256. return ret;
  257. slave_ch_idx = wcd937x_slave_get_slave_ch_val(slv_port_type);
  258. if (slave_ch_idx != -EINVAL)
  259. ch_type = wcd937x->tx_master_ch_map[slave_ch_idx];
  260. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  261. __func__, slave_ch_idx, ch_type);
  262. if (enable)
  263. ret = swr_connect_port(wcd937x->tx_swr_dev, &port_id,
  264. num_port, &ch_mask, &ch_rate,
  265. &num_ch, &ch_type);
  266. else
  267. ret = swr_disconnect_port(wcd937x->tx_swr_dev, &port_id,
  268. num_port, &ch_mask, &ch_type);
  269. return ret;
  270. }
  271. static int wcd937x_rx_connect_port(struct snd_soc_component *component,
  272. u8 slv_port_type, u8 enable)
  273. {
  274. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  275. u8 port_id;
  276. u8 num_ch;
  277. u8 ch_mask;
  278. u32 ch_rate;
  279. u8 port_type;
  280. u8 num_port = 1;
  281. int ret = 0;
  282. ret = wcd937x_set_port_params(component, slv_port_type, &port_id,
  283. &num_ch, &ch_mask, &ch_rate,
  284. &port_type, CODEC_RX);
  285. if (ret)
  286. return ret;
  287. if (enable)
  288. ret = swr_connect_port(wcd937x->rx_swr_dev, &port_id,
  289. num_port, &ch_mask, &ch_rate,
  290. &num_ch, &port_type);
  291. else
  292. ret = swr_disconnect_port(wcd937x->rx_swr_dev, &port_id,
  293. num_port, &ch_mask, &port_type);
  294. return ret;
  295. }
  296. static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
  297. {
  298. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  299. if (wcd937x->rx_clk_cnt == 0) {
  300. snd_soc_component_update_bits(component,
  301. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x08, 0x08);
  302. snd_soc_component_update_bits(component,
  303. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  304. snd_soc_component_update_bits(component,
  305. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x01);
  306. snd_soc_component_update_bits(component,
  307. WCD937X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  308. snd_soc_component_update_bits(component,
  309. WCD937X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  310. snd_soc_component_update_bits(component,
  311. WCD937X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  312. snd_soc_component_update_bits(component,
  313. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  314. }
  315. wcd937x->rx_clk_cnt++;
  316. return 0;
  317. }
  318. static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
  319. {
  320. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  321. if (wcd937x->rx_clk_cnt == 0) {
  322. dev_dbg(wcd937x->dev, "%s:clk already disabled\n", __func__);
  323. return 0;
  324. }
  325. wcd937x->rx_clk_cnt--;
  326. if (wcd937x->rx_clk_cnt == 0) {
  327. snd_soc_component_update_bits(component,
  328. WCD937X_ANA_RX_SUPPLIES, 0x01, 0x00);
  329. snd_soc_component_update_bits(component,
  330. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  331. 0x02, 0x00);
  332. snd_soc_component_update_bits(component,
  333. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  334. 0x01, 0x00);
  335. }
  336. return 0;
  337. }
  338. /*
  339. * wcd937x_soc_get_mbhc: get wcd937x_mbhc handle of corresponding component
  340. * @component: handle to snd_soc_component *
  341. *
  342. * return wcd937x_mbhc handle or error code in case of failure
  343. */
  344. struct wcd937x_mbhc *wcd937x_soc_get_mbhc(struct snd_soc_component *component)
  345. {
  346. struct wcd937x_priv *wcd937x;
  347. if (!component) {
  348. pr_err("%s: Invalid params, NULL component\n", __func__);
  349. return NULL;
  350. }
  351. wcd937x = snd_soc_component_get_drvdata(component);
  352. if (!wcd937x) {
  353. pr_err("%s: Invalid params, NULL tavil\n", __func__);
  354. return NULL;
  355. }
  356. return wcd937x->mbhc;
  357. }
  358. EXPORT_SYMBOL(wcd937x_soc_get_mbhc);
  359. static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  360. struct snd_kcontrol *kcontrol,
  361. int event)
  362. {
  363. struct snd_soc_component *component =
  364. snd_soc_dapm_to_component(w->dapm);
  365. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  366. int hph_mode = wcd937x->hph_mode;
  367. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  368. w->name, event);
  369. switch (event) {
  370. case SND_SOC_DAPM_PRE_PMU:
  371. wcd937x_rx_clk_enable(component);
  372. snd_soc_component_update_bits(component,
  373. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  374. 0x01, 0x01);
  375. snd_soc_component_update_bits(component,
  376. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  377. 0x04, 0x04);
  378. snd_soc_component_update_bits(component,
  379. WCD937X_HPH_RDAC_CLK_CTL1,
  380. 0x80, 0x00);
  381. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  382. break;
  383. case SND_SOC_DAPM_POST_PMU:
  384. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  385. snd_soc_component_update_bits(component,
  386. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  387. 0x0F, 0x02);
  388. else if (hph_mode == CLS_H_LOHIFI)
  389. snd_soc_component_update_bits(component,
  390. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  391. 0x0F, 0x06);
  392. if (wcd937x->comp1_enable) {
  393. snd_soc_component_update_bits(component,
  394. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  395. 0x02, 0x02);
  396. snd_soc_component_update_bits(component,
  397. WCD937X_HPH_L_EN, 0x20, 0x00);
  398. if (wcd937x->comp2_enable) {
  399. snd_soc_component_update_bits(component,
  400. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  401. 0x01, 0x01);
  402. snd_soc_component_update_bits(component,
  403. WCD937X_HPH_R_EN, 0x20, 0x00);
  404. }
  405. /*
  406. * 5ms sleep is required after COMP is enabled as per
  407. * HW requirement
  408. */
  409. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  410. usleep_range(5000, 5100);
  411. clear_bit(HPH_COMP_DELAY,
  412. &wcd937x->status_mask);
  413. }
  414. } else {
  415. snd_soc_component_update_bits(component,
  416. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  417. 0x02, 0x00);
  418. snd_soc_component_update_bits(component,
  419. WCD937X_HPH_L_EN, 0x20, 0x20);
  420. }
  421. snd_soc_component_update_bits(component,
  422. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  423. break;
  424. case SND_SOC_DAPM_POST_PMD:
  425. snd_soc_component_update_bits(component,
  426. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  427. 0x0F, 0x01);
  428. break;
  429. }
  430. return 0;
  431. }
  432. static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  433. struct snd_kcontrol *kcontrol,
  434. int event)
  435. {
  436. struct snd_soc_component *component =
  437. snd_soc_dapm_to_component(w->dapm);
  438. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  439. int hph_mode = wcd937x->hph_mode;
  440. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  441. w->name, event);
  442. switch (event) {
  443. case SND_SOC_DAPM_PRE_PMU:
  444. wcd937x_rx_clk_enable(component);
  445. snd_soc_component_update_bits(component,
  446. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  447. snd_soc_component_update_bits(component,
  448. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  449. snd_soc_component_update_bits(component,
  450. WCD937X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  451. set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
  452. break;
  453. case SND_SOC_DAPM_POST_PMU:
  454. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  455. snd_soc_component_update_bits(component,
  456. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  457. 0x0F, 0x02);
  458. else if (hph_mode == CLS_H_LOHIFI)
  459. snd_soc_component_update_bits(component,
  460. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  461. 0x0F, 0x06);
  462. if (wcd937x->comp2_enable) {
  463. snd_soc_component_update_bits(component,
  464. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  465. 0x01, 0x01);
  466. snd_soc_component_update_bits(component,
  467. WCD937X_HPH_R_EN, 0x20, 0x00);
  468. if (wcd937x->comp1_enable) {
  469. snd_soc_component_update_bits(component,
  470. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  471. 0x02, 0x02);
  472. snd_soc_component_update_bits(component,
  473. WCD937X_HPH_L_EN, 0x20, 0x00);
  474. }
  475. /*
  476. * 5ms sleep is required after COMP is enabled as per
  477. * HW requirement
  478. */
  479. if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
  480. usleep_range(5000, 5100);
  481. clear_bit(HPH_COMP_DELAY,
  482. &wcd937x->status_mask);
  483. }
  484. } else {
  485. snd_soc_component_update_bits(component,
  486. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  487. 0x01, 0x00);
  488. snd_soc_component_update_bits(component,
  489. WCD937X_HPH_R_EN, 0x20, 0x20);
  490. }
  491. snd_soc_component_update_bits(component,
  492. WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  493. break;
  494. case SND_SOC_DAPM_POST_PMD:
  495. snd_soc_component_update_bits(component,
  496. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  497. 0x0F, 0x01);
  498. break;
  499. }
  500. return 0;
  501. }
  502. static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  503. struct snd_kcontrol *kcontrol,
  504. int event)
  505. {
  506. struct snd_soc_component *component =
  507. snd_soc_dapm_to_component(w->dapm);
  508. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  509. int hph_mode = wcd937x->hph_mode;
  510. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  511. w->name, event);
  512. switch (event) {
  513. case SND_SOC_DAPM_PRE_PMU:
  514. wcd937x_rx_clk_enable(component);
  515. snd_soc_component_update_bits(component,
  516. WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
  517. 0x04, 0x04);
  518. snd_soc_component_update_bits(component,
  519. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  520. 0x01, 0x01);
  521. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
  522. snd_soc_component_update_bits(component,
  523. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  524. 0x0F, 0x02);
  525. else if (hph_mode == CLS_H_LOHIFI)
  526. snd_soc_component_update_bits(component,
  527. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  528. 0x0F, 0x06);
  529. if (wcd937x->comp1_enable)
  530. snd_soc_component_update_bits(component,
  531. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  532. 0x02, 0x02);
  533. usleep_range(5000, 5010);
  534. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  535. 0x04, 0x00);
  536. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  537. WCD_CLSH_EVENT_PRE_DAC,
  538. WCD_CLSH_STATE_EAR,
  539. hph_mode);
  540. break;
  541. case SND_SOC_DAPM_POST_PMD:
  542. if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
  543. hph_mode == CLS_H_HIFI)
  544. snd_soc_component_update_bits(component,
  545. WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
  546. 0x0F, 0x01);
  547. if (wcd937x->comp1_enable)
  548. snd_soc_component_update_bits(component,
  549. WCD937X_DIGITAL_CDC_COMP_CTL_0,
  550. 0x02, 0x00);
  551. break;
  552. };
  553. return 0;
  554. }
  555. static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  556. struct snd_kcontrol *kcontrol,
  557. int event)
  558. {
  559. struct snd_soc_component *component =
  560. snd_soc_dapm_to_component(w->dapm);
  561. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  562. int hph_mode = wcd937x->hph_mode;
  563. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  564. w->name, event);
  565. switch (event) {
  566. case SND_SOC_DAPM_PRE_PMU:
  567. wcd937x_rx_clk_enable(component);
  568. snd_soc_component_update_bits(component,
  569. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  570. 0x04, 0x04);
  571. snd_soc_component_update_bits(component,
  572. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  573. 0x04, 0x04);
  574. snd_soc_component_update_bits(component,
  575. WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
  576. 0x01, 0x01);
  577. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  578. WCD_CLSH_EVENT_PRE_DAC,
  579. WCD_CLSH_STATE_AUX,
  580. hph_mode);
  581. break;
  582. case SND_SOC_DAPM_POST_PMD:
  583. snd_soc_component_update_bits(component,
  584. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  585. 0x04, 0x00);
  586. break;
  587. };
  588. return 0;
  589. }
  590. static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  591. struct snd_kcontrol *kcontrol,
  592. int event)
  593. {
  594. struct snd_soc_component *component =
  595. snd_soc_dapm_to_component(w->dapm);
  596. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  597. int ret = 0;
  598. int hph_mode = wcd937x->hph_mode;
  599. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  600. w->name, event);
  601. switch (event) {
  602. case SND_SOC_DAPM_PRE_PMU:
  603. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  604. wcd937x->rx_swr_dev->dev_num,
  605. true);
  606. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  607. WCD_CLSH_EVENT_PRE_DAC,
  608. WCD_CLSH_STATE_HPHR,
  609. hph_mode);
  610. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  611. 0x10, 0x10);
  612. usleep_range(100, 110);
  613. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  614. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  615. wcd937x->rx_swr_dev->dev_num,
  616. true);
  617. snd_soc_component_update_bits(component,
  618. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  619. break;
  620. case SND_SOC_DAPM_POST_PMU:
  621. /*
  622. * 7ms sleep is required after PA is enabled as per
  623. * HW requirement. If compander is disabled, then
  624. * 20ms delay is required.
  625. */
  626. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  627. if (!wcd937x->comp2_enable)
  628. usleep_range(20000, 20100);
  629. else
  630. usleep_range(7000, 7100);
  631. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  632. }
  633. snd_soc_component_update_bits(component,
  634. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  635. 0x02, 0x02);
  636. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  637. snd_soc_component_update_bits(component,
  638. WCD937X_ANA_RX_SUPPLIES,
  639. 0x02, 0x02);
  640. if (wcd937x->update_wcd_event)
  641. wcd937x->update_wcd_event(wcd937x->handle,
  642. WCD_BOLERO_EVT_RX_MUTE,
  643. (WCD_RX2 << 0x10));
  644. wcd_enable_irq(&wcd937x->irq_info,
  645. WCD937X_IRQ_HPHR_PDM_WD_INT);
  646. break;
  647. case SND_SOC_DAPM_PRE_PMD:
  648. wcd_disable_irq(&wcd937x->irq_info,
  649. WCD937X_IRQ_HPHR_PDM_WD_INT);
  650. if (wcd937x->update_wcd_event)
  651. wcd937x->update_wcd_event(wcd937x->handle,
  652. WCD_BOLERO_EVT_RX_MUTE,
  653. (WCD_RX2 << 0x10 | 0x1));
  654. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  655. WCD_EVENT_PRE_HPHR_PA_OFF,
  656. &wcd937x->mbhc->wcd_mbhc);
  657. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  658. break;
  659. case SND_SOC_DAPM_POST_PMD:
  660. /*
  661. * 7ms sleep is required after PA is disabled as per
  662. * HW requirement. If compander is disabled, then
  663. * 20ms delay is required.
  664. */
  665. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  666. if (!wcd937x->comp2_enable)
  667. usleep_range(20000, 20100);
  668. else
  669. usleep_range(7000, 7100);
  670. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  671. }
  672. snd_soc_component_update_bits(component,
  673. WCD937X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  674. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  675. WCD_EVENT_POST_HPHR_PA_OFF,
  676. &wcd937x->mbhc->wcd_mbhc);
  677. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  678. 0x10, 0x00);
  679. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  680. WCD_CLSH_EVENT_POST_PA,
  681. WCD_CLSH_STATE_HPHR,
  682. hph_mode);
  683. break;
  684. };
  685. return ret;
  686. }
  687. static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  688. struct snd_kcontrol *kcontrol,
  689. int event)
  690. {
  691. struct snd_soc_component *component =
  692. snd_soc_dapm_to_component(w->dapm);
  693. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  694. int ret = 0;
  695. int hph_mode = wcd937x->hph_mode;
  696. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  697. w->name, event);
  698. switch (event) {
  699. case SND_SOC_DAPM_PRE_PMU:
  700. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  701. wcd937x->rx_swr_dev->dev_num,
  702. true);
  703. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  704. WCD_CLSH_EVENT_PRE_DAC,
  705. WCD_CLSH_STATE_HPHL,
  706. hph_mode);
  707. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  708. 0x20, 0x20);
  709. usleep_range(100, 110);
  710. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  711. snd_soc_component_update_bits(component,
  712. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  713. break;
  714. case SND_SOC_DAPM_POST_PMU:
  715. /*
  716. * 7ms sleep is required after PA is enabled as per
  717. * HW requirement. If compander is disabled, then
  718. * 20ms delay is required.
  719. */
  720. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  721. if (!wcd937x->comp1_enable)
  722. usleep_range(20000, 20100);
  723. else
  724. usleep_range(7000, 7100);
  725. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  726. }
  727. snd_soc_component_update_bits(component,
  728. WCD937X_HPH_NEW_INT_HPH_TIMER1,
  729. 0x02, 0x02);
  730. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  731. snd_soc_component_update_bits(component,
  732. WCD937X_ANA_RX_SUPPLIES,
  733. 0x02, 0x02);
  734. if (wcd937x->update_wcd_event)
  735. wcd937x->update_wcd_event(wcd937x->handle,
  736. WCD_BOLERO_EVT_RX_MUTE,
  737. (WCD_RX1 << 0x10));
  738. wcd_enable_irq(&wcd937x->irq_info,
  739. WCD937X_IRQ_HPHL_PDM_WD_INT);
  740. break;
  741. case SND_SOC_DAPM_PRE_PMD:
  742. wcd_disable_irq(&wcd937x->irq_info,
  743. WCD937X_IRQ_HPHL_PDM_WD_INT);
  744. if (wcd937x->update_wcd_event)
  745. wcd937x->update_wcd_event(wcd937x->handle,
  746. WCD_BOLERO_EVT_RX_MUTE,
  747. (WCD_RX1 << 0x10 | 0x1));
  748. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  749. WCD_EVENT_PRE_HPHL_PA_OFF,
  750. &wcd937x->mbhc->wcd_mbhc);
  751. set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  752. break;
  753. case SND_SOC_DAPM_POST_PMD:
  754. /*
  755. * 7ms sleep is required after PA is disabled as per
  756. * HW requirement. If compander is disabled, then
  757. * 20ms delay is required.
  758. */
  759. if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
  760. if (!wcd937x->comp1_enable)
  761. usleep_range(20000, 20100);
  762. else
  763. usleep_range(7000, 7100);
  764. clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
  765. }
  766. snd_soc_component_update_bits(component,
  767. WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  768. blocking_notifier_call_chain(&wcd937x->mbhc->notifier,
  769. WCD_EVENT_POST_HPHL_PA_OFF,
  770. &wcd937x->mbhc->wcd_mbhc);
  771. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  772. 0x20, 0x00);
  773. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  774. WCD_CLSH_EVENT_POST_PA,
  775. WCD_CLSH_STATE_HPHL,
  776. hph_mode);
  777. break;
  778. };
  779. return ret;
  780. }
  781. static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  782. struct snd_kcontrol *kcontrol,
  783. int event)
  784. {
  785. struct snd_soc_component *component =
  786. snd_soc_dapm_to_component(w->dapm);
  787. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  788. int hph_mode = wcd937x->hph_mode;
  789. int ret = 0;
  790. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  791. w->name, event);
  792. switch (event) {
  793. case SND_SOC_DAPM_PRE_PMU:
  794. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  795. wcd937x->rx_swr_dev->dev_num,
  796. true);
  797. snd_soc_component_update_bits(component,
  798. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  799. break;
  800. case SND_SOC_DAPM_POST_PMU:
  801. usleep_range(1000, 1010);
  802. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  803. snd_soc_component_update_bits(component,
  804. WCD937X_ANA_RX_SUPPLIES,
  805. 0x02, 0x02);
  806. if (wcd937x->update_wcd_event)
  807. wcd937x->update_wcd_event(wcd937x->handle,
  808. WCD_BOLERO_EVT_RX_MUTE,
  809. (WCD_RX3 << 0x10));
  810. wcd_enable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  811. break;
  812. case SND_SOC_DAPM_PRE_PMD:
  813. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  814. if (wcd937x->update_wcd_event)
  815. wcd937x->update_wcd_event(wcd937x->handle,
  816. WCD_BOLERO_EVT_RX_MUTE,
  817. (WCD_RX3 << 0x10 | 0x1));
  818. break;
  819. case SND_SOC_DAPM_POST_PMD:
  820. /* Add delay as per hw requirement */
  821. usleep_range(2000, 2010);
  822. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  823. WCD_CLSH_EVENT_POST_PA,
  824. WCD_CLSH_STATE_AUX,
  825. hph_mode);
  826. snd_soc_component_update_bits(component,
  827. WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  828. break;
  829. };
  830. return ret;
  831. }
  832. static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  833. struct snd_kcontrol *kcontrol,
  834. int event)
  835. {
  836. struct snd_soc_component *component =
  837. snd_soc_dapm_to_component(w->dapm);
  838. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  839. int hph_mode = wcd937x->hph_mode;
  840. int ret = 0;
  841. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  842. w->name, event);
  843. switch (event) {
  844. case SND_SOC_DAPM_PRE_PMU:
  845. ret = swr_slvdev_datapath_control(wcd937x->rx_swr_dev,
  846. wcd937x->rx_swr_dev->dev_num,
  847. true);
  848. /*
  849. * Enable watchdog interrupt for HPHL or AUX
  850. * depending on mux value
  851. */
  852. wcd937x->ear_rx_path =
  853. snd_soc_component_read32(
  854. component, WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
  855. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  856. snd_soc_component_update_bits(component,
  857. WCD937X_DIGITAL_PDM_WD_CTL2,
  858. 0x05, 0x05);
  859. else
  860. snd_soc_component_update_bits(component,
  861. WCD937X_DIGITAL_PDM_WD_CTL0,
  862. 0x17, 0x13);
  863. if (!wcd937x->comp1_enable)
  864. snd_soc_component_update_bits(component,
  865. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  866. break;
  867. case SND_SOC_DAPM_POST_PMU:
  868. usleep_range(6000, 6010);
  869. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
  870. snd_soc_component_update_bits(component,
  871. WCD937X_ANA_RX_SUPPLIES,
  872. 0x02, 0x02);
  873. if (wcd937x->update_wcd_event)
  874. wcd937x->update_wcd_event(wcd937x->handle,
  875. WCD_BOLERO_EVT_RX_MUTE,
  876. (WCD_RX1 << 0x10));
  877. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  878. wcd_enable_irq(&wcd937x->irq_info,
  879. WCD937X_IRQ_AUX_PDM_WD_INT);
  880. else
  881. wcd_enable_irq(&wcd937x->irq_info,
  882. WCD937X_IRQ_HPHL_PDM_WD_INT);
  883. break;
  884. case SND_SOC_DAPM_PRE_PMD:
  885. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  886. wcd_disable_irq(&wcd937x->irq_info,
  887. WCD937X_IRQ_AUX_PDM_WD_INT);
  888. else
  889. wcd_disable_irq(&wcd937x->irq_info,
  890. WCD937X_IRQ_HPHL_PDM_WD_INT);
  891. if (wcd937x->update_wcd_event)
  892. wcd937x->update_wcd_event(wcd937x->handle,
  893. WCD_BOLERO_EVT_RX_MUTE,
  894. (WCD_RX1 << 0x10 | 0x1));
  895. break;
  896. case SND_SOC_DAPM_POST_PMD:
  897. if (!wcd937x->comp1_enable)
  898. snd_soc_component_update_bits(component,
  899. WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  900. usleep_range(7000, 7010);
  901. wcd_cls_h_fsm(component, &wcd937x->clsh_info,
  902. WCD_CLSH_EVENT_POST_PA,
  903. WCD_CLSH_STATE_EAR,
  904. hph_mode);
  905. snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
  906. 0x04, 0x04);
  907. if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
  908. snd_soc_component_update_bits(component,
  909. WCD937X_DIGITAL_PDM_WD_CTL2,
  910. 0x05, 0x00);
  911. else
  912. snd_soc_component_update_bits(component,
  913. WCD937X_DIGITAL_PDM_WD_CTL0,
  914. 0x17, 0x00);
  915. break;
  916. };
  917. return ret;
  918. }
  919. static int wcd937x_enable_clsh(struct snd_soc_dapm_widget *w,
  920. struct snd_kcontrol *kcontrol,
  921. int event)
  922. {
  923. struct snd_soc_component *component =
  924. snd_soc_dapm_to_component(w->dapm);
  925. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  926. int mode = wcd937x->hph_mode;
  927. int ret = 0;
  928. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  929. w->name, event);
  930. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  931. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  932. wcd937x_rx_connect_port(component, CLSH,
  933. SND_SOC_DAPM_EVENT_ON(event));
  934. }
  935. if (SND_SOC_DAPM_EVENT_OFF(event))
  936. ret = swr_slvdev_datapath_control(
  937. wcd937x->rx_swr_dev,
  938. wcd937x->rx_swr_dev->dev_num,
  939. false);
  940. return ret;
  941. }
  942. static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
  943. struct snd_kcontrol *kcontrol,
  944. int event)
  945. {
  946. struct snd_soc_component *component =
  947. snd_soc_dapm_to_component(w->dapm);
  948. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  949. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  950. w->name, event);
  951. switch (event) {
  952. case SND_SOC_DAPM_PRE_PMU:
  953. wcd937x_rx_connect_port(component, HPH_L, true);
  954. if (wcd937x->comp1_enable)
  955. wcd937x_rx_connect_port(component, COMP_L, true);
  956. break;
  957. case SND_SOC_DAPM_POST_PMD:
  958. wcd937x_rx_connect_port(component, HPH_L, false);
  959. if (wcd937x->comp1_enable)
  960. wcd937x_rx_connect_port(component, COMP_L, false);
  961. wcd937x_rx_clk_disable(component);
  962. snd_soc_component_update_bits(component,
  963. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  964. 0x01, 0x00);
  965. break;
  966. };
  967. return 0;
  968. }
  969. static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
  970. struct snd_kcontrol *kcontrol, int event)
  971. {
  972. struct snd_soc_component *component =
  973. snd_soc_dapm_to_component(w->dapm);
  974. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  975. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  976. w->name, event);
  977. switch (event) {
  978. case SND_SOC_DAPM_PRE_PMU:
  979. wcd937x_rx_connect_port(component, HPH_R, true);
  980. if (wcd937x->comp2_enable)
  981. wcd937x_rx_connect_port(component, COMP_R, true);
  982. break;
  983. case SND_SOC_DAPM_POST_PMD:
  984. wcd937x_rx_connect_port(component, HPH_R, false);
  985. if (wcd937x->comp2_enable)
  986. wcd937x_rx_connect_port(component, COMP_R, false);
  987. wcd937x_rx_clk_disable(component);
  988. snd_soc_component_update_bits(component,
  989. WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
  990. 0x02, 0x00);
  991. break;
  992. };
  993. return 0;
  994. }
  995. static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
  996. struct snd_kcontrol *kcontrol,
  997. int event)
  998. {
  999. struct snd_soc_component *component =
  1000. snd_soc_dapm_to_component(w->dapm);
  1001. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1002. w->name, event);
  1003. switch (event) {
  1004. case SND_SOC_DAPM_PRE_PMU:
  1005. wcd937x_rx_connect_port(component, LO, true);
  1006. break;
  1007. case SND_SOC_DAPM_POST_PMD:
  1008. wcd937x_rx_connect_port(component, LO, false);
  1009. usleep_range(6000, 6010);
  1010. wcd937x_rx_clk_disable(component);
  1011. snd_soc_component_update_bits(component,
  1012. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1013. break;
  1014. }
  1015. return 0;
  1016. }
  1017. static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1018. struct snd_kcontrol *kcontrol,
  1019. int event)
  1020. {
  1021. struct snd_soc_component *component =
  1022. snd_soc_dapm_to_component(w->dapm);
  1023. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1024. u16 dmic_clk_reg;
  1025. s32 *dmic_clk_cnt;
  1026. unsigned int dmic;
  1027. char *wname;
  1028. int ret = 0;
  1029. wname = strpbrk(w->name, "012345");
  1030. if (!wname) {
  1031. dev_err(component->dev, "%s: widget not found\n", __func__);
  1032. return -EINVAL;
  1033. }
  1034. ret = kstrtouint(wname, 10, &dmic);
  1035. if (ret < 0) {
  1036. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  1037. __func__);
  1038. return -EINVAL;
  1039. }
  1040. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1041. w->name, event);
  1042. switch (dmic) {
  1043. case 0:
  1044. case 1:
  1045. dmic_clk_cnt = &(wcd937x->dmic_0_1_clk_cnt);
  1046. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
  1047. break;
  1048. case 2:
  1049. case 3:
  1050. dmic_clk_cnt = &(wcd937x->dmic_2_3_clk_cnt);
  1051. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
  1052. break;
  1053. case 4:
  1054. case 5:
  1055. dmic_clk_cnt = &(wcd937x->dmic_4_5_clk_cnt);
  1056. dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
  1057. break;
  1058. default:
  1059. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1060. __func__);
  1061. return -EINVAL;
  1062. };
  1063. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1064. __func__, event, dmic, *dmic_clk_cnt);
  1065. switch (event) {
  1066. case SND_SOC_DAPM_PRE_PMU:
  1067. snd_soc_component_update_bits(component,
  1068. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1069. snd_soc_component_update_bits(component,
  1070. dmic_clk_reg, 0x07, 0x02);
  1071. snd_soc_component_update_bits(component,
  1072. dmic_clk_reg, 0x08, 0x08);
  1073. snd_soc_component_update_bits(component,
  1074. dmic_clk_reg, 0x70, 0x20);
  1075. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), true);
  1076. break;
  1077. case SND_SOC_DAPM_POST_PMD:
  1078. wcd937x_tx_connect_port(component, DMIC0 + (w->shift), false);
  1079. break;
  1080. };
  1081. return 0;
  1082. }
  1083. /*
  1084. * wcd937x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1085. * @micb_mv: micbias in mv
  1086. *
  1087. * return register value converted
  1088. */
  1089. int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
  1090. {
  1091. /* min micbias voltage is 1V and maximum is 2.85V */
  1092. if (micb_mv < 1000 || micb_mv > 2850) {
  1093. pr_err("%s: unsupported micbias voltage\n", __func__);
  1094. return -EINVAL;
  1095. }
  1096. return (micb_mv - 1000) / 50;
  1097. }
  1098. EXPORT_SYMBOL(wcd937x_get_micb_vout_ctl_val);
  1099. /*
  1100. * wcd937x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1101. * @component: handle to snd_soc_component *
  1102. * @req_volt: micbias voltage to be set
  1103. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1104. *
  1105. * return 0 if adjustment is success or error code in case of failure
  1106. */
  1107. int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1108. int req_volt, int micb_num)
  1109. {
  1110. struct wcd937x_priv *wcd937x =
  1111. snd_soc_component_get_drvdata(component);
  1112. int cur_vout_ctl, req_vout_ctl;
  1113. int micb_reg, micb_val, micb_en;
  1114. int ret = 0;
  1115. switch (micb_num) {
  1116. case MIC_BIAS_1:
  1117. micb_reg = WCD937X_ANA_MICB1;
  1118. break;
  1119. case MIC_BIAS_2:
  1120. micb_reg = WCD937X_ANA_MICB2;
  1121. break;
  1122. case MIC_BIAS_3:
  1123. micb_reg = WCD937X_ANA_MICB3;
  1124. break;
  1125. default:
  1126. return -EINVAL;
  1127. }
  1128. mutex_lock(&wcd937x->micb_lock);
  1129. /*
  1130. * If requested micbias voltage is same as current micbias
  1131. * voltage, then just return. Otherwise, adjust voltage as
  1132. * per requested value. If micbias is already enabled, then
  1133. * to avoid slow micbias ramp-up or down enable pull-up
  1134. * momentarily, change the micbias value and then re-enable
  1135. * micbias.
  1136. */
  1137. micb_val = snd_soc_component_read32(component, micb_reg);
  1138. micb_en = (micb_val & 0xC0) >> 6;
  1139. cur_vout_ctl = micb_val & 0x3F;
  1140. req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
  1141. if (req_vout_ctl < 0) {
  1142. ret = -EINVAL;
  1143. goto exit;
  1144. }
  1145. if (cur_vout_ctl == req_vout_ctl) {
  1146. ret = 0;
  1147. goto exit;
  1148. }
  1149. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1150. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1151. req_volt, micb_en);
  1152. if (micb_en == 0x1)
  1153. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1154. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1155. if (micb_en == 0x1) {
  1156. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1157. /*
  1158. * Add 2ms delay as per HW requirement after enabling
  1159. * micbias
  1160. */
  1161. usleep_range(2000, 2100);
  1162. }
  1163. exit:
  1164. mutex_unlock(&wcd937x->micb_lock);
  1165. return ret;
  1166. }
  1167. EXPORT_SYMBOL(wcd937x_mbhc_micb_adjust_voltage);
  1168. static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1169. struct snd_kcontrol *kcontrol,
  1170. int event)
  1171. {
  1172. struct snd_soc_component *component =
  1173. snd_soc_dapm_to_component(w->dapm);
  1174. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1175. int ret = 0;
  1176. switch (event) {
  1177. case SND_SOC_DAPM_PRE_PMU:
  1178. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1179. wcd937x->tx_swr_dev->dev_num,
  1180. true);
  1181. break;
  1182. case SND_SOC_DAPM_POST_PMD:
  1183. ret = swr_slvdev_datapath_control(wcd937x->tx_swr_dev,
  1184. wcd937x->tx_swr_dev->dev_num,
  1185. false);
  1186. break;
  1187. };
  1188. return ret;
  1189. }
  1190. static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1191. struct snd_kcontrol *kcontrol,
  1192. int event){
  1193. struct snd_soc_component *component =
  1194. snd_soc_dapm_to_component(w->dapm);
  1195. struct wcd937x_priv *wcd937x =
  1196. snd_soc_component_get_drvdata(component);
  1197. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1198. w->name, event);
  1199. switch (event) {
  1200. case SND_SOC_DAPM_PRE_PMU:
  1201. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1202. wcd937x->ana_clk_count++;
  1203. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1204. snd_soc_component_update_bits(component,
  1205. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1206. snd_soc_component_update_bits(component,
  1207. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1208. snd_soc_component_update_bits(component,
  1209. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1210. /* Enable BCS for Headset mic */
  1211. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1212. WCD937X_TX_NEW_TX_CH2_SEL) & 0x80)) {
  1213. wcd937x_tx_connect_port(component, MBHC, true);
  1214. set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1215. }
  1216. wcd937x_tx_connect_port(component, ADC1 + (w->shift), true);
  1217. break;
  1218. case SND_SOC_DAPM_POST_PMD:
  1219. wcd937x_tx_connect_port(component, ADC1 + (w->shift), false);
  1220. if (w->shift == 1 &&
  1221. test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask)) {
  1222. wcd937x_tx_connect_port(component, MBHC, false);
  1223. clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
  1224. }
  1225. snd_soc_component_update_bits(component,
  1226. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1227. break;
  1228. };
  1229. return 0;
  1230. }
  1231. static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
  1232. struct snd_kcontrol *kcontrol, int event)
  1233. {
  1234. struct snd_soc_component *component =
  1235. snd_soc_dapm_to_component(w->dapm);
  1236. struct wcd937x_priv *wcd937x =
  1237. snd_soc_component_get_drvdata(component);
  1238. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1239. w->name, event);
  1240. switch (event) {
  1241. case SND_SOC_DAPM_PRE_PMU:
  1242. snd_soc_component_update_bits(component,
  1243. WCD937X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1244. snd_soc_component_update_bits(component,
  1245. WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1246. snd_soc_component_update_bits(component,
  1247. WCD937X_ANA_TX_CH2, 0x40, 0x40);
  1248. snd_soc_component_update_bits(component,
  1249. WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40);
  1250. snd_soc_component_update_bits(component,
  1251. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
  1252. snd_soc_component_update_bits(component,
  1253. WCD937X_ANA_TX_CH1, 0x80, 0x80);
  1254. snd_soc_component_update_bits(component,
  1255. WCD937X_ANA_TX_CH2, 0x40, 0x00);
  1256. snd_soc_component_update_bits(component,
  1257. WCD937X_ANA_TX_CH2, 0x80, 0x80);
  1258. snd_soc_component_update_bits(component,
  1259. WCD937X_ANA_TX_CH3, 0x80, 0x80);
  1260. break;
  1261. case SND_SOC_DAPM_POST_PMD:
  1262. snd_soc_component_update_bits(component,
  1263. WCD937X_ANA_TX_CH1, 0x80, 0x00);
  1264. snd_soc_component_update_bits(component,
  1265. WCD937X_ANA_TX_CH2, 0x80, 0x00);
  1266. snd_soc_component_update_bits(component,
  1267. WCD937X_ANA_TX_CH3, 0x80, 0x00);
  1268. snd_soc_component_update_bits(component,
  1269. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1270. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1271. wcd937x->ana_clk_count--;
  1272. if (wcd937x->ana_clk_count <= 0) {
  1273. snd_soc_component_update_bits(component,
  1274. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1275. wcd937x->ana_clk_count = 0;
  1276. }
  1277. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1278. snd_soc_component_update_bits(component,
  1279. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1280. break;
  1281. };
  1282. return 0;
  1283. }
  1284. int wcd937x_micbias_control(struct snd_soc_component *component,
  1285. int micb_num, int req, bool is_dapm)
  1286. {
  1287. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1288. int micb_index = micb_num - 1;
  1289. u16 micb_reg;
  1290. int pre_off_event = 0, post_off_event = 0;
  1291. int post_on_event = 0, post_dapm_off = 0;
  1292. int post_dapm_on = 0;
  1293. if ((micb_index < 0) || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
  1294. dev_err(component->dev, "%s: Invalid micbias index, micb_ind:%d\n",
  1295. __func__, micb_index);
  1296. return -EINVAL;
  1297. }
  1298. switch (micb_num) {
  1299. case MIC_BIAS_1:
  1300. micb_reg = WCD937X_ANA_MICB1;
  1301. break;
  1302. case MIC_BIAS_2:
  1303. micb_reg = WCD937X_ANA_MICB2;
  1304. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1305. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1306. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1307. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1308. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1309. break;
  1310. case MIC_BIAS_3:
  1311. micb_reg = WCD937X_ANA_MICB3;
  1312. break;
  1313. default:
  1314. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1315. __func__, micb_num);
  1316. return -EINVAL;
  1317. };
  1318. mutex_lock(&wcd937x->micb_lock);
  1319. switch (req) {
  1320. case MICB_PULLUP_ENABLE:
  1321. wcd937x->pullup_ref[micb_index]++;
  1322. if ((wcd937x->pullup_ref[micb_index] == 1) &&
  1323. (wcd937x->micb_ref[micb_index] == 0))
  1324. snd_soc_component_update_bits(component, micb_reg,
  1325. 0xC0, 0x80);
  1326. break;
  1327. case MICB_PULLUP_DISABLE:
  1328. if (wcd937x->pullup_ref[micb_index] > 0)
  1329. wcd937x->pullup_ref[micb_index]--;
  1330. if ((wcd937x->pullup_ref[micb_index] == 0) &&
  1331. (wcd937x->micb_ref[micb_index] == 0))
  1332. snd_soc_component_update_bits(component, micb_reg,
  1333. 0xC0, 0x00);
  1334. break;
  1335. case MICB_ENABLE:
  1336. wcd937x->micb_ref[micb_index]++;
  1337. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1338. wcd937x->ana_clk_count++;
  1339. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1340. if (wcd937x->micb_ref[micb_index] == 1) {
  1341. snd_soc_component_update_bits(component,
  1342. WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1343. snd_soc_component_update_bits(component,
  1344. WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1345. snd_soc_component_update_bits(component,
  1346. WCD937X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1347. snd_soc_component_update_bits(component,
  1348. WCD937X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1349. snd_soc_component_update_bits(component,
  1350. WCD937X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1351. snd_soc_component_update_bits(component,
  1352. micb_reg, 0xC0, 0x40);
  1353. if (post_on_event)
  1354. blocking_notifier_call_chain(
  1355. &wcd937x->mbhc->notifier, post_on_event,
  1356. &wcd937x->mbhc->wcd_mbhc);
  1357. }
  1358. if (is_dapm && post_dapm_on && wcd937x->mbhc)
  1359. blocking_notifier_call_chain(
  1360. &wcd937x->mbhc->notifier, post_dapm_on,
  1361. &wcd937x->mbhc->wcd_mbhc);
  1362. break;
  1363. case MICB_DISABLE:
  1364. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1365. wcd937x->ana_clk_count--;
  1366. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1367. if (wcd937x->micb_ref[micb_index] > 0)
  1368. wcd937x->micb_ref[micb_index]--;
  1369. if ((wcd937x->micb_ref[micb_index] == 0) &&
  1370. (wcd937x->pullup_ref[micb_index] > 0))
  1371. snd_soc_component_update_bits(component, micb_reg,
  1372. 0xC0, 0x80);
  1373. else if ((wcd937x->micb_ref[micb_index] == 0) &&
  1374. (wcd937x->pullup_ref[micb_index] == 0)) {
  1375. if (pre_off_event && wcd937x->mbhc)
  1376. blocking_notifier_call_chain(
  1377. &wcd937x->mbhc->notifier, pre_off_event,
  1378. &wcd937x->mbhc->wcd_mbhc);
  1379. snd_soc_component_update_bits(component, micb_reg,
  1380. 0xC0, 0x00);
  1381. if (post_off_event && wcd937x->mbhc)
  1382. blocking_notifier_call_chain(
  1383. &wcd937x->mbhc->notifier,
  1384. post_off_event,
  1385. &wcd937x->mbhc->wcd_mbhc);
  1386. }
  1387. mutex_lock(&wcd937x->ana_tx_clk_lock);
  1388. if (wcd937x->ana_clk_count <= 0) {
  1389. snd_soc_component_update_bits(component,
  1390. WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
  1391. 0x10, 0x00);
  1392. wcd937x->ana_clk_count = 0;
  1393. }
  1394. mutex_unlock(&wcd937x->ana_tx_clk_lock);
  1395. if (is_dapm && post_dapm_off && wcd937x->mbhc)
  1396. blocking_notifier_call_chain(
  1397. &wcd937x->mbhc->notifier, post_dapm_off,
  1398. &wcd937x->mbhc->wcd_mbhc);
  1399. break;
  1400. };
  1401. dev_dbg(component->dev, "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1402. __func__, micb_num, wcd937x->micb_ref[micb_index],
  1403. wcd937x->pullup_ref[micb_index]);
  1404. mutex_unlock(&wcd937x->micb_lock);
  1405. return 0;
  1406. }
  1407. EXPORT_SYMBOL(wcd937x_micbias_control);
  1408. void wcd937x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1409. bool bcs_disable)
  1410. {
  1411. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1412. if (wcd937x->update_wcd_event) {
  1413. if (bcs_disable)
  1414. wcd937x->update_wcd_event(wcd937x->handle,
  1415. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1416. else
  1417. wcd937x->update_wcd_event(wcd937x->handle,
  1418. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1419. }
  1420. }
  1421. static int wcd937x_get_logical_addr(struct swr_device *swr_dev)
  1422. {
  1423. int ret = 0;
  1424. uint8_t devnum = 0;
  1425. int num_retry = NUM_ATTEMPTS;
  1426. do {
  1427. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1428. if (ret) {
  1429. dev_err(&swr_dev->dev,
  1430. "%s get devnum %d for dev addr %lx failed\n",
  1431. __func__, devnum, swr_dev->addr);
  1432. /* retry after 1ms */
  1433. usleep_range(1000, 1010);
  1434. }
  1435. } while (ret && --num_retry);
  1436. swr_dev->dev_num = devnum;
  1437. return 0;
  1438. }
  1439. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1440. struct wcd_mbhc_config *mbhc_cfg)
  1441. {
  1442. if (mbhc_cfg->enable_usbc_analog) {
  1443. if (!(snd_soc_component_read32(component, WCD937X_ANA_MBHC_MECH)
  1444. & 0x20))
  1445. return true;
  1446. }
  1447. return false;
  1448. }
  1449. static int wcd937x_event_notify(struct notifier_block *block,
  1450. unsigned long val,
  1451. void *data)
  1452. {
  1453. u16 event = (val & 0xffff);
  1454. u16 amic = (val >> 0x10);
  1455. u16 mask = 0x40, reg = 0x0;
  1456. int ret = 0;
  1457. struct wcd937x_priv *wcd937x = dev_get_drvdata((struct device *)data);
  1458. struct snd_soc_component *component = wcd937x->component;
  1459. struct wcd_mbhc *mbhc;
  1460. switch (event) {
  1461. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1462. if (amic == 0x1 || amic == 0x2)
  1463. reg = WCD937X_ANA_TX_CH2;
  1464. else if (amic == 0x3)
  1465. reg = WCD937X_ANA_TX_CH3_HPF;
  1466. else
  1467. return 0;
  1468. if (amic == 0x2)
  1469. mask = 0x20;
  1470. snd_soc_component_update_bits(component, reg, mask, 0x00);
  1471. break;
  1472. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1473. snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
  1474. 0xC0, 0x00);
  1475. snd_soc_component_update_bits(component, WCD937X_ANA_EAR,
  1476. 0x80, 0x00);
  1477. snd_soc_component_update_bits(component, WCD937X_AUX_AUXPA,
  1478. 0x80, 0x00);
  1479. break;
  1480. case BOLERO_WCD_EVT_SSR_DOWN:
  1481. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1482. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1483. wcd937x->usbc_hs_status = get_usbc_hs_status(component,
  1484. mbhc->mbhc_cfg);
  1485. wcd937x_mbhc_ssr_down(wcd937x->mbhc, component);
  1486. wcd937x_reset_low(wcd937x->dev);
  1487. break;
  1488. case BOLERO_WCD_EVT_SSR_UP:
  1489. wcd937x_reset(wcd937x->dev);
  1490. /* allow reset to take effect */
  1491. usleep_range(10000, 10010);
  1492. wcd937x_get_logical_addr(wcd937x->tx_swr_dev);
  1493. wcd937x_get_logical_addr(wcd937x->rx_swr_dev);
  1494. wcd937x_init_reg(component);
  1495. regcache_mark_dirty(wcd937x->regmap);
  1496. regcache_sync(wcd937x->regmap);
  1497. /* Initialize MBHC module */
  1498. mbhc = &wcd937x->mbhc->wcd_mbhc;
  1499. ret = wcd937x_mbhc_post_ssr_init(wcd937x->mbhc, component);
  1500. if (ret) {
  1501. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1502. __func__);
  1503. } else {
  1504. wcd937x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1505. if (wcd937x->usbc_hs_status)
  1506. mdelay(500);
  1507. }
  1508. wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1509. break;
  1510. default:
  1511. dev_err(component->dev, "%s: invalid event %d\n", __func__,
  1512. event);
  1513. break;
  1514. }
  1515. return 0;
  1516. }
  1517. static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1518. int event)
  1519. {
  1520. struct snd_soc_component *component =
  1521. snd_soc_dapm_to_component(w->dapm);
  1522. int micb_num;
  1523. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1524. __func__, w->name, event);
  1525. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1526. micb_num = MIC_BIAS_1;
  1527. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1528. micb_num = MIC_BIAS_2;
  1529. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1530. micb_num = MIC_BIAS_3;
  1531. else
  1532. return -EINVAL;
  1533. switch (event) {
  1534. case SND_SOC_DAPM_PRE_PMU:
  1535. wcd937x_micbias_control(component, micb_num,
  1536. MICB_ENABLE, true);
  1537. break;
  1538. case SND_SOC_DAPM_POST_PMU:
  1539. usleep_range(1000, 1100);
  1540. break;
  1541. case SND_SOC_DAPM_POST_PMD:
  1542. wcd937x_micbias_control(component, micb_num,
  1543. MICB_DISABLE, true);
  1544. break;
  1545. };
  1546. return 0;
  1547. }
  1548. static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1549. struct snd_kcontrol *kcontrol,
  1550. int event)
  1551. {
  1552. return __wcd937x_codec_enable_micbias(w, event);
  1553. }
  1554. static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1555. int event)
  1556. {
  1557. struct snd_soc_component *component =
  1558. snd_soc_dapm_to_component(w->dapm);
  1559. int micb_num;
  1560. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1561. __func__, w->name, event);
  1562. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1563. micb_num = MIC_BIAS_1;
  1564. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1565. micb_num = MIC_BIAS_2;
  1566. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1567. micb_num = MIC_BIAS_3;
  1568. else
  1569. return -EINVAL;
  1570. switch (event) {
  1571. case SND_SOC_DAPM_PRE_PMU:
  1572. wcd937x_micbias_control(component, micb_num,
  1573. MICB_PULLUP_ENABLE, true);
  1574. break;
  1575. case SND_SOC_DAPM_POST_PMU:
  1576. /* 1 msec delay as per HW requirement */
  1577. usleep_range(1000, 1100);
  1578. break;
  1579. case SND_SOC_DAPM_POST_PMD:
  1580. wcd937x_micbias_control(component, micb_num,
  1581. MICB_PULLUP_DISABLE, true);
  1582. break;
  1583. };
  1584. return 0;
  1585. }
  1586. static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1587. struct snd_kcontrol *kcontrol,
  1588. int event)
  1589. {
  1590. return __wcd937x_codec_enable_micbias_pullup(w, event);
  1591. }
  1592. static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  1593. struct snd_ctl_elem_value *ucontrol)
  1594. {
  1595. struct snd_soc_component *component =
  1596. snd_soc_kcontrol_component(kcontrol);
  1597. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1598. ucontrol->value.integer.value[0] = wcd937x->hph_mode;
  1599. return 0;
  1600. }
  1601. static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  1602. struct snd_ctl_elem_value *ucontrol)
  1603. {
  1604. struct snd_soc_component *component =
  1605. snd_soc_kcontrol_component(kcontrol);
  1606. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1607. u32 mode_val;
  1608. mode_val = ucontrol->value.enumerated.item[0];
  1609. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  1610. if (mode_val == 0) {
  1611. dev_warn(component->dev, "%s:Invalid HPH Mode, default to class_AB\n",
  1612. __func__);
  1613. mode_val = 3; /* enum will be updated later */
  1614. }
  1615. wcd937x->hph_mode = mode_val;
  1616. return 0;
  1617. }
  1618. static int wcd937x_tx_ch_pwr_level_get(struct snd_kcontrol *kcontrol,
  1619. struct snd_ctl_elem_value *ucontrol)
  1620. {
  1621. struct snd_soc_component *component =
  1622. snd_soc_kcontrol_component(kcontrol);
  1623. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1624. if (strnstr(kcontrol->id.name, "CH1", sizeof(kcontrol->id.name)))
  1625. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[0];
  1626. else if (strnstr(kcontrol->id.name, "CH3", sizeof(kcontrol->id.name)))
  1627. ucontrol->value.integer.value[0] = wcd937x->tx_ch_pwr[1];
  1628. return 0;
  1629. }
  1630. static int wcd937x_tx_ch_pwr_level_put(struct snd_kcontrol *kcontrol,
  1631. struct snd_ctl_elem_value *ucontrol)
  1632. {
  1633. struct snd_soc_component *component =
  1634. snd_soc_kcontrol_component(kcontrol);
  1635. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1636. u32 pwr_level = ucontrol->value.enumerated.item[0];
  1637. dev_dbg(component->dev, "%s: tx ch pwr_level: %d\n",
  1638. __func__, pwr_level);
  1639. if (strnstr(kcontrol->id.name, "CH1",
  1640. sizeof(kcontrol->id.name))) {
  1641. snd_soc_component_update_bits(component,
  1642. WCD937X_ANA_TX_CH1, 0x60,
  1643. pwr_level << 0x5);
  1644. wcd937x->tx_ch_pwr[0] = pwr_level;
  1645. } else if (strnstr(kcontrol->id.name, "CH3",
  1646. sizeof(kcontrol->id.name))) {
  1647. snd_soc_component_update_bits(component,
  1648. WCD937X_ANA_TX_CH3, 0x60,
  1649. pwr_level << 0x5);
  1650. wcd937x->tx_ch_pwr[1] = pwr_level;
  1651. }
  1652. return 0;
  1653. }
  1654. static int wcd937x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  1655. struct snd_ctl_elem_value *ucontrol)
  1656. {
  1657. u8 ear_pa_gain = 0;
  1658. struct snd_soc_component *component =
  1659. snd_soc_kcontrol_component(kcontrol);
  1660. ear_pa_gain = snd_soc_component_read32(component,
  1661. WCD937X_ANA_EAR_COMPANDER_CTL);
  1662. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  1663. ucontrol->value.integer.value[0] = ear_pa_gain;
  1664. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  1665. ear_pa_gain);
  1666. return 0;
  1667. }
  1668. static int wcd937x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  1669. struct snd_ctl_elem_value *ucontrol)
  1670. {
  1671. u8 ear_pa_gain = 0;
  1672. struct snd_soc_component *component =
  1673. snd_soc_kcontrol_component(kcontrol);
  1674. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1675. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1676. __func__, ucontrol->value.integer.value[0]);
  1677. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  1678. if (!wcd937x->comp1_enable) {
  1679. snd_soc_component_update_bits(component,
  1680. WCD937X_ANA_EAR_COMPANDER_CTL,
  1681. 0x7C, ear_pa_gain);
  1682. }
  1683. return 0;
  1684. }
  1685. static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
  1686. struct snd_ctl_elem_value *ucontrol)
  1687. {
  1688. struct snd_soc_component *component =
  1689. snd_soc_kcontrol_component(kcontrol);
  1690. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1691. bool hphr;
  1692. struct soc_multi_mixer_control *mc;
  1693. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1694. hphr = mc->shift;
  1695. ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
  1696. wcd937x->comp1_enable;
  1697. return 0;
  1698. }
  1699. static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
  1700. struct snd_ctl_elem_value *ucontrol)
  1701. {
  1702. struct snd_soc_component *component =
  1703. snd_soc_kcontrol_component(kcontrol);
  1704. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1705. int value = ucontrol->value.integer.value[0];
  1706. bool hphr;
  1707. struct soc_multi_mixer_control *mc;
  1708. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  1709. hphr = mc->shift;
  1710. if (hphr)
  1711. wcd937x->comp2_enable = value;
  1712. else
  1713. wcd937x->comp1_enable = value;
  1714. return 0;
  1715. }
  1716. static int wcd937x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  1717. struct snd_kcontrol *kcontrol,
  1718. int event)
  1719. {
  1720. struct snd_soc_component *component =
  1721. snd_soc_dapm_to_component(w->dapm);
  1722. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1723. struct wcd937x_pdata *pdata = NULL;
  1724. int ret = 0;
  1725. pdata = dev_get_platdata(wcd937x->dev);
  1726. if (!pdata) {
  1727. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  1728. return -EINVAL;
  1729. }
  1730. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1731. w->name, event);
  1732. switch (event) {
  1733. case SND_SOC_DAPM_PRE_PMU:
  1734. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  1735. dev_dbg(component->dev,
  1736. "%s: buck already in enabled state\n",
  1737. __func__);
  1738. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1739. return 0;
  1740. }
  1741. ret = msm_cdc_enable_ondemand_supply(wcd937x->dev,
  1742. wcd937x->supplies,
  1743. pdata->regulator,
  1744. pdata->num_supplies,
  1745. "cdc-vdd-buck");
  1746. if (ret == -EINVAL) {
  1747. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  1748. __func__);
  1749. return ret;
  1750. }
  1751. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1752. /*
  1753. * 200us sleep is required after LDO15 is enabled as per
  1754. * HW requirement
  1755. */
  1756. usleep_range(200, 250);
  1757. break;
  1758. case SND_SOC_DAPM_POST_PMD:
  1759. set_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  1760. break;
  1761. }
  1762. return 0;
  1763. }
  1764. static const char * const rx_hph_mode_mux_text[] = {
  1765. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  1766. "CLS_H_ULP", "CLS_AB_HIFI",
  1767. };
  1768. const char * const tx_master_ch_text[] = {
  1769. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  1770. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  1771. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  1772. "SWRM_PCM_IN",
  1773. };
  1774. const struct soc_enum tx_master_ch_enum =
  1775. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  1776. tx_master_ch_text);
  1777. static void wcd937x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  1778. {
  1779. u8 ch_type = 0;
  1780. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  1781. ch_type = ADC1;
  1782. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  1783. ch_type = ADC2;
  1784. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  1785. ch_type = ADC3;
  1786. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  1787. ch_type = DMIC0;
  1788. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  1789. ch_type = DMIC1;
  1790. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  1791. ch_type = MBHC;
  1792. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  1793. ch_type = DMIC2;
  1794. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  1795. ch_type = DMIC3;
  1796. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  1797. ch_type = DMIC4;
  1798. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  1799. ch_type = DMIC5;
  1800. else
  1801. pr_err("%s: ch name: %s is not listed\n", __func__, wname);
  1802. if (ch_type)
  1803. *ch_idx = wcd937x_slave_get_slave_ch_val(ch_type);
  1804. else
  1805. *ch_idx = -EINVAL;
  1806. }
  1807. static int wcd937x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  1808. struct snd_ctl_elem_value *ucontrol)
  1809. {
  1810. struct snd_soc_component *component =
  1811. snd_soc_kcontrol_component(kcontrol);
  1812. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1813. int slave_ch_idx;
  1814. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1815. if (slave_ch_idx != -EINVAL)
  1816. ucontrol->value.integer.value[0] =
  1817. wcd937x_slave_get_master_ch_val(
  1818. wcd937x->tx_master_ch_map[slave_ch_idx]);
  1819. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  1820. __func__, ucontrol->value.integer.value[0]);
  1821. return 0;
  1822. }
  1823. static int wcd937x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  1824. struct snd_ctl_elem_value *ucontrol)
  1825. {
  1826. struct snd_soc_component *component =
  1827. snd_soc_kcontrol_component(kcontrol);
  1828. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  1829. int slave_ch_idx;
  1830. wcd937x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  1831. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  1832. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  1833. __func__, ucontrol->value.enumerated.item[0]);
  1834. if (slave_ch_idx != -EINVAL)
  1835. wcd937x->tx_master_ch_map[slave_ch_idx] =
  1836. wcd937x_slave_get_master_ch(
  1837. ucontrol->value.enumerated.item[0]);
  1838. return 0;
  1839. }
  1840. static const char * const wcd937x_tx_ch_pwr_level_text[] = {
  1841. "L0", "L1", "L2", "L3",
  1842. };
  1843. static const char * const wcd937x_ear_pa_gain_text[] = {
  1844. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  1845. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  1846. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  1847. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  1848. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  1849. };
  1850. static const struct soc_enum rx_hph_mode_mux_enum =
  1851. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  1852. rx_hph_mode_mux_text);
  1853. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_ear_pa_gain_enum,
  1854. wcd937x_ear_pa_gain_text);
  1855. static SOC_ENUM_SINGLE_EXT_DECL(wcd937x_tx_ch_pwr_level_enum,
  1856. wcd937x_tx_ch_pwr_level_text);
  1857. static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
  1858. SOC_ENUM_EXT("EAR PA GAIN", wcd937x_ear_pa_gain_enum,
  1859. wcd937x_ear_pa_gain_get, wcd937x_ear_pa_gain_put),
  1860. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  1861. wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
  1862. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1863. wcd937x_get_compander, wcd937x_set_compander),
  1864. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  1865. wcd937x_get_compander, wcd937x_set_compander),
  1866. SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
  1867. SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
  1868. SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0,
  1869. analog_gain),
  1870. SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0,
  1871. analog_gain),
  1872. SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0,
  1873. analog_gain),
  1874. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  1875. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1876. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  1877. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1878. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  1879. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1880. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  1881. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1882. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  1883. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1884. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  1885. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1886. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  1887. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1888. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  1889. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1890. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  1891. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1892. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  1893. wcd937x_tx_master_ch_get, wcd937x_tx_master_ch_put),
  1894. SOC_ENUM_EXT("TX CH1 PWR", wcd937x_tx_ch_pwr_level_enum,
  1895. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1896. SOC_ENUM_EXT("TX CH3 PWR", wcd937x_tx_ch_pwr_level_enum,
  1897. wcd937x_tx_ch_pwr_level_get, wcd937x_tx_ch_pwr_level_put),
  1898. };
  1899. static const struct snd_kcontrol_new adc1_switch[] = {
  1900. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1901. };
  1902. static const struct snd_kcontrol_new adc2_switch[] = {
  1903. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1904. };
  1905. static const struct snd_kcontrol_new adc3_switch[] = {
  1906. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1907. };
  1908. static const struct snd_kcontrol_new dmic1_switch[] = {
  1909. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1910. };
  1911. static const struct snd_kcontrol_new dmic2_switch[] = {
  1912. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1913. };
  1914. static const struct snd_kcontrol_new dmic3_switch[] = {
  1915. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1916. };
  1917. static const struct snd_kcontrol_new dmic4_switch[] = {
  1918. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1919. };
  1920. static const struct snd_kcontrol_new dmic5_switch[] = {
  1921. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1922. };
  1923. static const struct snd_kcontrol_new dmic6_switch[] = {
  1924. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1925. };
  1926. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  1927. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1928. };
  1929. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  1930. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1931. };
  1932. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  1933. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1934. };
  1935. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  1936. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1937. };
  1938. static const char * const adc2_mux_text[] = {
  1939. "INP2", "INP3"
  1940. };
  1941. static const char * const rdac3_mux_text[] = {
  1942. "RX1", "RX3"
  1943. };
  1944. static const struct soc_enum adc2_enum =
  1945. SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
  1946. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  1947. static const struct soc_enum rdac3_enum =
  1948. SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  1949. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  1950. static const struct snd_kcontrol_new tx_adc2_mux =
  1951. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  1952. static const struct snd_kcontrol_new rx_rdac3_mux =
  1953. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  1954. static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
  1955. /*input widgets*/
  1956. SND_SOC_DAPM_INPUT("AMIC1"),
  1957. SND_SOC_DAPM_INPUT("AMIC2"),
  1958. SND_SOC_DAPM_INPUT("AMIC3"),
  1959. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  1960. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  1961. SND_SOC_DAPM_INPUT("IN3_AUX"),
  1962. /*tx widgets*/
  1963. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  1964. wcd937x_codec_enable_adc,
  1965. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1966. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  1967. wcd937x_codec_enable_adc,
  1968. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1969. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  1970. NULL, 0, wcd937x_enable_req,
  1971. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1972. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
  1973. NULL, 0, wcd937x_enable_req,
  1974. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1975. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  1976. &tx_adc2_mux),
  1977. /*tx mixers*/
  1978. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  1979. adc1_switch, ARRAY_SIZE(adc1_switch),
  1980. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1981. SND_SOC_DAPM_POST_PMD),
  1982. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  1983. adc2_switch, ARRAY_SIZE(adc2_switch),
  1984. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  1985. SND_SOC_DAPM_POST_PMD),
  1986. /* micbias widgets*/
  1987. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  1988. wcd937x_codec_enable_micbias,
  1989. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1990. SND_SOC_DAPM_POST_PMD),
  1991. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  1992. wcd937x_codec_enable_micbias,
  1993. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1994. SND_SOC_DAPM_POST_PMD),
  1995. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  1996. wcd937x_codec_enable_micbias,
  1997. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1998. SND_SOC_DAPM_POST_PMD),
  1999. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2000. wcd937x_codec_enable_vdd_buck,
  2001. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2002. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2003. wcd937x_enable_clsh,
  2004. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2005. /*rx widgets*/
  2006. SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
  2007. wcd937x_codec_enable_ear_pa,
  2008. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2009. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2010. SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
  2011. wcd937x_codec_enable_aux_pa,
  2012. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2013. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2014. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
  2015. wcd937x_codec_enable_hphl_pa,
  2016. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2017. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2018. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
  2019. wcd937x_codec_enable_hphr_pa,
  2020. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2021. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2022. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2023. wcd937x_codec_hphl_dac_event,
  2024. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2025. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2026. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2027. wcd937x_codec_hphr_dac_event,
  2028. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2029. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2030. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2031. wcd937x_codec_ear_dac_event,
  2032. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2033. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2034. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2035. wcd937x_codec_aux_dac_event,
  2036. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2037. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2038. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2039. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2040. wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2041. SND_SOC_DAPM_POST_PMD),
  2042. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2043. wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2044. SND_SOC_DAPM_POST_PMD),
  2045. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2046. wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2047. SND_SOC_DAPM_POST_PMD),
  2048. /* rx mixer widgets*/
  2049. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2050. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2051. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2052. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2053. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2054. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2055. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2056. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2057. /*output widgets tx*/
  2058. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  2059. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  2060. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2061. /*output widgets rx*/
  2062. SND_SOC_DAPM_OUTPUT("EAR"),
  2063. SND_SOC_DAPM_OUTPUT("AUX"),
  2064. SND_SOC_DAPM_OUTPUT("HPHL"),
  2065. SND_SOC_DAPM_OUTPUT("HPHR"),
  2066. /* micbias pull up widgets*/
  2067. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2068. wcd937x_codec_enable_micbias_pullup,
  2069. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2070. SND_SOC_DAPM_POST_PMD),
  2071. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2072. wcd937x_codec_enable_micbias_pullup,
  2073. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2074. SND_SOC_DAPM_POST_PMD),
  2075. SND_SOC_DAPM_MICBIAS_E("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2076. wcd937x_codec_enable_micbias_pullup,
  2077. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2078. SND_SOC_DAPM_POST_PMD),
  2079. };
  2080. static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
  2081. /*input widgets*/
  2082. SND_SOC_DAPM_INPUT("AMIC4"),
  2083. /*tx widgets*/
  2084. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2085. wcd937x_codec_enable_adc,
  2086. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2087. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
  2088. NULL, 0, wcd937x_enable_req,
  2089. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2090. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2091. wcd937x_codec_enable_dmic,
  2092. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2093. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2094. wcd937x_codec_enable_dmic,
  2095. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2096. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2097. wcd937x_codec_enable_dmic,
  2098. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2099. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2100. wcd937x_codec_enable_dmic,
  2101. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2102. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2103. wcd937x_codec_enable_dmic,
  2104. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2105. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2106. wcd937x_codec_enable_dmic,
  2107. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2108. /*tx mixer widgets*/
  2109. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2110. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2111. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2112. SND_SOC_DAPM_POST_PMD),
  2113. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2114. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2115. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2116. SND_SOC_DAPM_POST_PMD),
  2117. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2118. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2119. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2120. SND_SOC_DAPM_POST_PMD),
  2121. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2122. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2123. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2124. SND_SOC_DAPM_POST_PMD),
  2125. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2126. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2127. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2128. SND_SOC_DAPM_POST_PMD),
  2129. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2130. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2131. wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2132. SND_SOC_DAPM_POST_PMD),
  2133. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2134. ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
  2135. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2136. /*output widgets*/
  2137. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  2138. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  2139. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  2140. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  2141. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  2142. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  2143. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  2144. };
  2145. static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
  2146. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2147. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2148. {"ADC1 REQ", NULL, "ADC1"},
  2149. {"ADC1", NULL, "AMIC1"},
  2150. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2151. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2152. {"ADC2 REQ", NULL, "ADC2"},
  2153. {"ADC2", NULL, "ADC2 MUX"},
  2154. {"ADC2 MUX", "INP3", "AMIC3"},
  2155. {"ADC2 MUX", "INP2", "AMIC2"},
  2156. {"IN1_HPHL", NULL, "VDD_BUCK"},
  2157. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2158. {"RX1", NULL, "IN1_HPHL"},
  2159. {"RDAC1", NULL, "RX1"},
  2160. {"HPHL_RDAC", "Switch", "RDAC1"},
  2161. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2162. {"HPHL", NULL, "HPHL PGA"},
  2163. {"IN2_HPHR", NULL, "VDD_BUCK"},
  2164. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2165. {"RX2", NULL, "IN2_HPHR"},
  2166. {"RDAC2", NULL, "RX2"},
  2167. {"HPHR_RDAC", "Switch", "RDAC2"},
  2168. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2169. {"HPHR", NULL, "HPHR PGA"},
  2170. {"IN3_AUX", NULL, "VDD_BUCK"},
  2171. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2172. {"RX3", NULL, "IN3_AUX"},
  2173. {"RDAC4", NULL, "RX3"},
  2174. {"AUX_RDAC", "Switch", "RDAC4"},
  2175. {"AUX PGA", NULL, "AUX_RDAC"},
  2176. {"AUX", NULL, "AUX PGA"},
  2177. {"RDAC3_MUX", "RX3", "RX3"},
  2178. {"RDAC3_MUX", "RX1", "RX1"},
  2179. {"RDAC3", NULL, "RDAC3_MUX"},
  2180. {"EAR_RDAC", "Switch", "RDAC3"},
  2181. {"EAR PGA", NULL, "EAR_RDAC"},
  2182. {"EAR", NULL, "EAR PGA"},
  2183. };
  2184. static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
  2185. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2186. {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
  2187. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2188. {"ADC3 REQ", NULL, "ADC3"},
  2189. {"ADC3", NULL, "AMIC4"},
  2190. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2191. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  2192. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2193. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2194. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  2195. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2196. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2197. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  2198. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2199. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2200. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  2201. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2202. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2203. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  2204. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2205. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2206. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  2207. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2208. };
  2209. static ssize_t wcd937x_version_read(struct snd_info_entry *entry,
  2210. void *file_private_data,
  2211. struct file *file,
  2212. char __user *buf, size_t count,
  2213. loff_t pos)
  2214. {
  2215. struct wcd937x_priv *priv;
  2216. char buffer[WCD937X_VERSION_ENTRY_SIZE];
  2217. int len = 0;
  2218. priv = (struct wcd937x_priv *) entry->private_data;
  2219. if (!priv) {
  2220. pr_err("%s: wcd937x priv is null\n", __func__);
  2221. return -EINVAL;
  2222. }
  2223. switch (priv->version) {
  2224. case WCD937X_VERSION_1_0:
  2225. len = snprintf(buffer, sizeof(buffer), "WCD937X_1_0\n");
  2226. break;
  2227. default:
  2228. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2229. }
  2230. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2231. }
  2232. static struct snd_info_entry_ops wcd937x_info_ops = {
  2233. .read = wcd937x_version_read,
  2234. };
  2235. static ssize_t wcd937x_variant_read(struct snd_info_entry *entry,
  2236. void *file_private_data,
  2237. struct file *file,
  2238. char __user *buf, size_t count,
  2239. loff_t pos)
  2240. {
  2241. struct wcd937x_priv *priv;
  2242. char buffer[WCD937X_VARIANT_ENTRY_SIZE];
  2243. int len = 0;
  2244. priv = (struct wcd937x_priv *) entry->private_data;
  2245. if (!priv) {
  2246. pr_err("%s: wcd937x priv is null\n", __func__);
  2247. return -EINVAL;
  2248. }
  2249. switch (priv->variant) {
  2250. case WCD9370_VARIANT:
  2251. len = snprintf(buffer, sizeof(buffer), "WCD9370\n");
  2252. break;
  2253. case WCD9375_VARIANT:
  2254. len = snprintf(buffer, sizeof(buffer), "WCD9375\n");
  2255. break;
  2256. default:
  2257. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2258. }
  2259. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2260. }
  2261. static struct snd_info_entry_ops wcd937x_variant_ops = {
  2262. .read = wcd937x_variant_read,
  2263. };
  2264. /*
  2265. * wcd937x_info_create_codec_entry - creates wcd937x module
  2266. * @codec_root: The parent directory
  2267. * @component: component instance
  2268. *
  2269. * Creates wcd937x module, variant and version entry under the given
  2270. * parent directory.
  2271. *
  2272. * Return: 0 on success or negative error code on failure.
  2273. */
  2274. int wcd937x_info_create_codec_entry(struct snd_info_entry *codec_root,
  2275. struct snd_soc_component *component)
  2276. {
  2277. struct snd_info_entry *version_entry;
  2278. struct snd_info_entry *variant_entry;
  2279. struct wcd937x_priv *priv;
  2280. struct snd_soc_card *card;
  2281. if (!codec_root || !component)
  2282. return -EINVAL;
  2283. priv = snd_soc_component_get_drvdata(component);
  2284. if (priv->entry) {
  2285. dev_dbg(priv->dev,
  2286. "%s:wcd937x module already created\n", __func__);
  2287. return 0;
  2288. }
  2289. card = component->card;
  2290. priv->entry = snd_info_create_subdir(codec_root->module,
  2291. "wcd937x", codec_root);
  2292. if (!priv->entry) {
  2293. dev_dbg(component->dev, "%s: failed to create wcd937x entry\n",
  2294. __func__);
  2295. return -ENOMEM;
  2296. }
  2297. version_entry = snd_info_create_card_entry(card->snd_card,
  2298. "version",
  2299. priv->entry);
  2300. if (!version_entry) {
  2301. dev_dbg(component->dev, "%s: failed to create wcd937x version entry\n",
  2302. __func__);
  2303. return -ENOMEM;
  2304. }
  2305. version_entry->private_data = priv;
  2306. version_entry->size = WCD937X_VERSION_ENTRY_SIZE;
  2307. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  2308. version_entry->c.ops = &wcd937x_info_ops;
  2309. if (snd_info_register(version_entry) < 0) {
  2310. snd_info_free_entry(version_entry);
  2311. return -ENOMEM;
  2312. }
  2313. priv->version_entry = version_entry;
  2314. variant_entry = snd_info_create_card_entry(card->snd_card,
  2315. "variant",
  2316. priv->entry);
  2317. if (!variant_entry) {
  2318. dev_dbg(component->dev,
  2319. "%s: failed to create wcd937x variant entry\n",
  2320. __func__);
  2321. return -ENOMEM;
  2322. }
  2323. variant_entry->private_data = priv;
  2324. variant_entry->size = WCD937X_VARIANT_ENTRY_SIZE;
  2325. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  2326. variant_entry->c.ops = &wcd937x_variant_ops;
  2327. if (snd_info_register(variant_entry) < 0) {
  2328. snd_info_free_entry(variant_entry);
  2329. return -ENOMEM;
  2330. }
  2331. priv->variant_entry = variant_entry;
  2332. return 0;
  2333. }
  2334. EXPORT_SYMBOL(wcd937x_info_create_codec_entry);
  2335. static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x,
  2336. struct wcd937x_pdata *pdata)
  2337. {
  2338. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0;
  2339. int rc = 0;
  2340. if (!pdata) {
  2341. dev_err(wcd937x->dev, "%s: NULL pdata\n", __func__);
  2342. return -ENODEV;
  2343. }
  2344. /* set micbias voltage */
  2345. vout_ctl_1 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  2346. vout_ctl_2 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  2347. vout_ctl_3 = wcd937x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  2348. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0) {
  2349. rc = -EINVAL;
  2350. goto done;
  2351. }
  2352. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, 0x3F,
  2353. vout_ctl_1);
  2354. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, 0x3F,
  2355. vout_ctl_2);
  2356. regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, 0x3F,
  2357. vout_ctl_3);
  2358. done:
  2359. return rc;
  2360. }
  2361. static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
  2362. {
  2363. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2364. struct snd_soc_dapm_context *dapm =
  2365. snd_soc_component_get_dapm(component);
  2366. int variant;
  2367. int ret = -EINVAL;
  2368. dev_info(component->dev, "%s()\n", __func__);
  2369. wcd937x = snd_soc_component_get_drvdata(component);
  2370. if (!wcd937x)
  2371. return -EINVAL;
  2372. wcd937x->component = component;
  2373. snd_soc_component_init_regmap(component, wcd937x->regmap);
  2374. variant = (snd_soc_component_read32(
  2375. component, WCD937X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  2376. wcd937x->variant = variant;
  2377. wcd937x->fw_data = devm_kzalloc(component->dev,
  2378. sizeof(*(wcd937x->fw_data)),
  2379. GFP_KERNEL);
  2380. if (!wcd937x->fw_data) {
  2381. dev_err(component->dev, "Failed to allocate fw_data\n");
  2382. ret = -ENOMEM;
  2383. goto err;
  2384. }
  2385. set_bit(WCD9XXX_MBHC_CAL, wcd937x->fw_data->cal_bit);
  2386. ret = wcd_cal_create_hwdep(wcd937x->fw_data,
  2387. WCD9XXX_CODEC_HWDEP_NODE, component);
  2388. if (ret < 0) {
  2389. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  2390. goto err_hwdep;
  2391. }
  2392. ret = wcd937x_mbhc_init(&wcd937x->mbhc, component, wcd937x->fw_data);
  2393. if (ret) {
  2394. pr_err("%s: mbhc initialization failed\n", __func__);
  2395. goto err_hwdep;
  2396. }
  2397. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  2398. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  2399. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  2400. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  2401. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  2402. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  2403. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  2404. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  2405. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  2406. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  2407. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  2408. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  2409. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  2410. snd_soc_dapm_sync(dapm);
  2411. wcd_cls_h_init(&wcd937x->clsh_info);
  2412. wcd937x_init_reg(component);
  2413. if (wcd937x->variant == WCD9375_VARIANT) {
  2414. ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
  2415. ARRAY_SIZE(wcd9375_dapm_widgets));
  2416. if (ret < 0) {
  2417. dev_err(component->dev, "%s: Failed to add snd_ctls\n",
  2418. __func__);
  2419. goto err_hwdep;
  2420. }
  2421. ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
  2422. ARRAY_SIZE(wcd9375_audio_map));
  2423. if (ret < 0) {
  2424. dev_err(component->dev, "%s: Failed to add routes\n",
  2425. __func__);
  2426. goto err_hwdep;
  2427. }
  2428. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  2429. snd_soc_dapm_ignore_suspend(dapm, "DMIC1_OUTPUT");
  2430. snd_soc_dapm_ignore_suspend(dapm, "DMIC2_OUTPUT");
  2431. snd_soc_dapm_ignore_suspend(dapm, "DMIC3_OUTPUT");
  2432. snd_soc_dapm_ignore_suspend(dapm, "DMIC4_OUTPUT");
  2433. snd_soc_dapm_ignore_suspend(dapm, "DMIC5_OUTPUT");
  2434. snd_soc_dapm_ignore_suspend(dapm, "DMIC6_OUTPUT");
  2435. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  2436. snd_soc_dapm_sync(dapm);
  2437. }
  2438. wcd937x->version = WCD937X_VERSION_1_0;
  2439. /* Register event notifier */
  2440. wcd937x->nblock.notifier_call = wcd937x_event_notify;
  2441. if (wcd937x->register_notifier) {
  2442. ret = wcd937x->register_notifier(wcd937x->handle,
  2443. &wcd937x->nblock,
  2444. true);
  2445. if (ret) {
  2446. dev_err(component->dev,
  2447. "%s: Failed to register notifier %d\n",
  2448. __func__, ret);
  2449. return ret;
  2450. }
  2451. }
  2452. return ret;
  2453. err_hwdep:
  2454. wcd937x->fw_data = NULL;
  2455. err:
  2456. return ret;
  2457. }
  2458. static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
  2459. {
  2460. struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
  2461. if (!wcd937x)
  2462. return;
  2463. if (wcd937x->register_notifier)
  2464. wcd937x->register_notifier(wcd937x->handle,
  2465. &wcd937x->nblock,
  2466. false);
  2467. return;
  2468. }
  2469. static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
  2470. .name = DRV_NAME,
  2471. .probe = wcd937x_soc_codec_probe,
  2472. .remove = wcd937x_soc_codec_remove,
  2473. .controls = wcd937x_snd_controls,
  2474. .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
  2475. .dapm_widgets = wcd937x_dapm_widgets,
  2476. .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
  2477. .dapm_routes = wcd937x_audio_map,
  2478. .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
  2479. };
  2480. #ifdef CONFIG_PM_SLEEP
  2481. static int wcd937x_suspend(struct device *dev)
  2482. {
  2483. struct wcd937x_priv *wcd937x = NULL;
  2484. int ret = 0;
  2485. struct wcd937x_pdata *pdata = NULL;
  2486. if (!dev)
  2487. return -ENODEV;
  2488. wcd937x = dev_get_drvdata(dev);
  2489. if (!wcd937x)
  2490. return -EINVAL;
  2491. pdata = dev_get_platdata(wcd937x->dev);
  2492. if (!pdata) {
  2493. dev_err(dev, "%s: pdata is NULL\n", __func__);
  2494. return -EINVAL;
  2495. }
  2496. if (test_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask)) {
  2497. ret = msm_cdc_disable_ondemand_supply(wcd937x->dev,
  2498. wcd937x->supplies,
  2499. pdata->regulator,
  2500. pdata->num_supplies,
  2501. "cdc-vdd-buck");
  2502. if (ret == -EINVAL) {
  2503. dev_err(dev, "%s: vdd buck is not disabled\n",
  2504. __func__);
  2505. return 0;
  2506. }
  2507. clear_bit(ALLOW_BUCK_DISABLE, &wcd937x->status_mask);
  2508. }
  2509. return 0;
  2510. }
  2511. static int wcd937x_resume(struct device *dev)
  2512. {
  2513. return 0;
  2514. }
  2515. #endif
  2516. static int wcd937x_reset(struct device *dev)
  2517. {
  2518. struct wcd937x_priv *wcd937x = NULL;
  2519. int rc = 0;
  2520. int value = 0;
  2521. if (!dev)
  2522. return -ENODEV;
  2523. wcd937x = dev_get_drvdata(dev);
  2524. if (!wcd937x)
  2525. return -EINVAL;
  2526. if (!wcd937x->rst_np) {
  2527. dev_err(dev, "%s: reset gpio device node not specified\n",
  2528. __func__);
  2529. return -EINVAL;
  2530. }
  2531. value = msm_cdc_pinctrl_get_state(wcd937x->rst_np);
  2532. if (value > 0)
  2533. return 0;
  2534. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2535. if (rc) {
  2536. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2537. __func__);
  2538. return rc;
  2539. }
  2540. /* 20ms sleep required after pulling the reset gpio to LOW */
  2541. usleep_range(20, 30);
  2542. rc = msm_cdc_pinctrl_select_active_state(wcd937x->rst_np);
  2543. if (rc) {
  2544. dev_err(dev, "%s: wcd active state request fail!\n",
  2545. __func__);
  2546. return rc;
  2547. }
  2548. /* 20ms sleep required after pulling the reset gpio to HIGH */
  2549. usleep_range(20, 30);
  2550. return rc;
  2551. }
  2552. static int wcd937x_read_of_property_u32(struct device *dev, const char *name,
  2553. u32 *val)
  2554. {
  2555. int rc = 0;
  2556. rc = of_property_read_u32(dev->of_node, name, val);
  2557. if (rc)
  2558. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2559. __func__, name, dev->of_node->full_name);
  2560. return rc;
  2561. }
  2562. static void wcd937x_dt_parse_micbias_info(struct device *dev,
  2563. struct wcd937x_micbias_setting *mb)
  2564. {
  2565. u32 prop_val = 0;
  2566. int rc = 0;
  2567. /* MB1 */
  2568. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  2569. NULL)) {
  2570. rc = wcd937x_read_of_property_u32(dev,
  2571. "qcom,cdc-micbias1-mv",
  2572. &prop_val);
  2573. if (!rc)
  2574. mb->micb1_mv = prop_val;
  2575. } else {
  2576. dev_info(dev, "%s: Micbias1 DT property not found\n",
  2577. __func__);
  2578. }
  2579. /* MB2 */
  2580. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  2581. NULL)) {
  2582. rc = wcd937x_read_of_property_u32(dev,
  2583. "qcom,cdc-micbias2-mv",
  2584. &prop_val);
  2585. if (!rc)
  2586. mb->micb2_mv = prop_val;
  2587. } else {
  2588. dev_info(dev, "%s: Micbias2 DT property not found\n",
  2589. __func__);
  2590. }
  2591. /* MB3 */
  2592. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  2593. NULL)) {
  2594. rc = wcd937x_read_of_property_u32(dev,
  2595. "qcom,cdc-micbias3-mv",
  2596. &prop_val);
  2597. if (!rc)
  2598. mb->micb3_mv = prop_val;
  2599. } else {
  2600. dev_info(dev, "%s: Micbias3 DT property not found\n",
  2601. __func__);
  2602. }
  2603. }
  2604. static int wcd937x_reset_low(struct device *dev)
  2605. {
  2606. struct wcd937x_priv *wcd937x = NULL;
  2607. int rc = 0;
  2608. if (!dev)
  2609. return -ENODEV;
  2610. wcd937x = dev_get_drvdata(dev);
  2611. if (!wcd937x)
  2612. return -EINVAL;
  2613. if (!wcd937x->rst_np) {
  2614. dev_err(dev, "%s: reset gpio device node not specified\n",
  2615. __func__);
  2616. return -EINVAL;
  2617. }
  2618. rc = msm_cdc_pinctrl_select_sleep_state(wcd937x->rst_np);
  2619. if (rc) {
  2620. dev_err(dev, "%s: wcd sleep state request fail!\n",
  2621. __func__);
  2622. return rc;
  2623. }
  2624. /* 20ms sleep required after pulling the reset gpio to LOW */
  2625. usleep_range(20, 30);
  2626. return rc;
  2627. }
  2628. struct wcd937x_pdata *wcd937x_populate_dt_data(struct device *dev)
  2629. {
  2630. struct wcd937x_pdata *pdata = NULL;
  2631. pdata = kzalloc(sizeof(struct wcd937x_pdata),
  2632. GFP_KERNEL);
  2633. if (!pdata)
  2634. return NULL;
  2635. pdata->rst_np = of_parse_phandle(dev->of_node,
  2636. "qcom,wcd-rst-gpio-node", 0);
  2637. if (!pdata->rst_np) {
  2638. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  2639. __func__, "qcom,wcd-rst-gpio-node",
  2640. dev->of_node->full_name);
  2641. return NULL;
  2642. }
  2643. /* Parse power supplies */
  2644. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  2645. &pdata->num_supplies);
  2646. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  2647. dev_err(dev, "%s: no power supplies defined for codec\n",
  2648. __func__);
  2649. return NULL;
  2650. }
  2651. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  2652. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  2653. wcd937x_dt_parse_micbias_info(dev, &pdata->micbias);
  2654. return pdata;
  2655. }
  2656. static int wcd937x_wakeup(void *handle, bool enable)
  2657. {
  2658. struct wcd937x_priv *priv;
  2659. if (!handle) {
  2660. pr_err("%s: NULL handle\n", __func__);
  2661. return -EINVAL;
  2662. }
  2663. priv = (struct wcd937x_priv *)handle;
  2664. if (!priv->tx_swr_dev) {
  2665. pr_err("%s: tx swr dev is NULL\n", __func__);
  2666. return -EINVAL;
  2667. }
  2668. if (enable)
  2669. return swr_device_wakeup_vote(priv->tx_swr_dev);
  2670. else
  2671. return swr_device_wakeup_unvote(priv->tx_swr_dev);
  2672. }
  2673. static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
  2674. {
  2675. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  2676. __func__, irq);
  2677. return IRQ_HANDLED;
  2678. }
  2679. static int wcd937x_bind(struct device *dev)
  2680. {
  2681. int ret = 0, i = 0;
  2682. struct wcd937x_priv *wcd937x = NULL;
  2683. struct wcd937x_pdata *pdata = NULL;
  2684. struct wcd_ctrl_platform_data *plat_data = NULL;
  2685. wcd937x = kzalloc(sizeof(struct wcd937x_priv), GFP_KERNEL);
  2686. if (!wcd937x)
  2687. return -ENOMEM;
  2688. dev_set_drvdata(dev, wcd937x);
  2689. pdata = wcd937x_populate_dt_data(dev);
  2690. if (!pdata) {
  2691. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  2692. return -EINVAL;
  2693. }
  2694. wcd937x->dev = dev;
  2695. wcd937x->dev->platform_data = pdata;
  2696. wcd937x->rst_np = pdata->rst_np;
  2697. ret = msm_cdc_init_supplies(dev, &wcd937x->supplies,
  2698. pdata->regulator, pdata->num_supplies);
  2699. if (!wcd937x->supplies) {
  2700. dev_err(dev, "%s: Cannot init wcd supplies\n",
  2701. __func__);
  2702. goto err_bind_all;
  2703. }
  2704. plat_data = dev_get_platdata(dev->parent);
  2705. if (!plat_data) {
  2706. dev_err(dev, "%s: platform data from parent is NULL\n",
  2707. __func__);
  2708. ret = -EINVAL;
  2709. goto err_bind_all;
  2710. }
  2711. wcd937x->handle = (void *)plat_data->handle;
  2712. if (!wcd937x->handle) {
  2713. dev_err(dev, "%s: handle is NULL\n", __func__);
  2714. ret = -EINVAL;
  2715. goto err_bind_all;
  2716. }
  2717. wcd937x->update_wcd_event = plat_data->update_wcd_event;
  2718. if (!wcd937x->update_wcd_event) {
  2719. dev_err(dev, "%s: update_wcd_event api is null!\n",
  2720. __func__);
  2721. ret = -EINVAL;
  2722. goto err_bind_all;
  2723. }
  2724. wcd937x->register_notifier = plat_data->register_notifier;
  2725. if (!wcd937x->register_notifier) {
  2726. dev_err(dev, "%s: register_notifier api is null!\n",
  2727. __func__);
  2728. ret = -EINVAL;
  2729. goto err_bind_all;
  2730. }
  2731. ret = msm_cdc_enable_static_supplies(dev, wcd937x->supplies,
  2732. pdata->regulator,
  2733. pdata->num_supplies);
  2734. if (ret) {
  2735. dev_err(dev, "%s: wcd static supply enable failed!\n",
  2736. __func__);
  2737. goto err_bind_all;
  2738. }
  2739. wcd937x_reset(dev);
  2740. /*
  2741. * Add 5msec delay to provide sufficient time for
  2742. * soundwire auto enumeration of slave devices as
  2743. * as per HW requirement.
  2744. */
  2745. usleep_range(5000, 5010);
  2746. wcd937x->wakeup = wcd937x_wakeup;
  2747. ret = component_bind_all(dev, wcd937x);
  2748. if (ret) {
  2749. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  2750. __func__, ret);
  2751. goto err_bind_all;
  2752. }
  2753. ret = wcd937x_parse_port_mapping(dev, "qcom,rx_swr_ch_map", CODEC_RX);
  2754. ret |= wcd937x_parse_port_mapping(dev, "qcom,tx_swr_ch_map", CODEC_TX);
  2755. if (ret) {
  2756. dev_err(dev, "Failed to read port mapping\n");
  2757. goto err;
  2758. }
  2759. wcd937x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  2760. if (!wcd937x->rx_swr_dev) {
  2761. dev_err(dev, "%s: Could not find RX swr slave device\n",
  2762. __func__);
  2763. ret = -ENODEV;
  2764. goto err;
  2765. }
  2766. wcd937x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  2767. if (!wcd937x->tx_swr_dev) {
  2768. dev_err(dev, "%s: Could not find TX swr slave device\n",
  2769. __func__);
  2770. ret = -ENODEV;
  2771. goto err;
  2772. }
  2773. wcd937x->regmap = devm_regmap_init_swr(wcd937x->tx_swr_dev,
  2774. &wcd937x_regmap_config);
  2775. if (!wcd937x->regmap) {
  2776. dev_err(dev, "%s: Regmap init failed\n",
  2777. __func__);
  2778. goto err;
  2779. }
  2780. /* Set all interupts as edge triggered */
  2781. for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
  2782. regmap_write(wcd937x->regmap,
  2783. (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
  2784. wcd937x_regmap_irq_chip.irq_drv_data = wcd937x;
  2785. wcd937x->irq_info.wcd_regmap_irq_chip = &wcd937x_regmap_irq_chip;
  2786. wcd937x->irq_info.codec_name = "WCD937X";
  2787. wcd937x->irq_info.regmap = wcd937x->regmap;
  2788. wcd937x->irq_info.dev = dev;
  2789. ret = wcd_irq_init(&wcd937x->irq_info, &wcd937x->virq);
  2790. if (ret) {
  2791. dev_err(dev, "%s: IRQ init failed: %d\n",
  2792. __func__, ret);
  2793. goto err;
  2794. }
  2795. wcd937x->tx_swr_dev->slave_irq = wcd937x->virq;
  2796. ret = wcd937x_set_micbias_data(wcd937x, pdata);
  2797. if (ret < 0) {
  2798. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  2799. goto err_irq;
  2800. }
  2801. /* default L1 power setting */
  2802. wcd937x->tx_ch_pwr[0] = 1;
  2803. wcd937x->tx_ch_pwr[1] = 1;
  2804. mutex_init(&wcd937x->micb_lock);
  2805. mutex_init(&wcd937x->ana_tx_clk_lock);
  2806. /* Request for watchdog interrupt */
  2807. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT,
  2808. "HPHR PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2809. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT,
  2810. "HPHL PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2811. wcd_request_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT,
  2812. "AUX PDM WD INT", wcd937x_wd_handle_irq, NULL);
  2813. /* Disable watchdog interrupt for HPH and AUX */
  2814. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHR_PDM_WD_INT);
  2815. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT);
  2816. wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT);
  2817. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
  2818. NULL, 0);
  2819. if (ret) {
  2820. dev_err(dev, "%s: Codec registration failed\n",
  2821. __func__);
  2822. goto err_irq;
  2823. }
  2824. return ret;
  2825. err_irq:
  2826. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2827. err:
  2828. component_unbind_all(dev, wcd937x);
  2829. err_bind_all:
  2830. dev_set_drvdata(dev, NULL);
  2831. kfree(pdata);
  2832. kfree(wcd937x);
  2833. return ret;
  2834. }
  2835. static void wcd937x_unbind(struct device *dev)
  2836. {
  2837. struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
  2838. struct wcd937x_pdata *pdata = dev_get_platdata(wcd937x->dev);
  2839. wcd_irq_exit(&wcd937x->irq_info, wcd937x->virq);
  2840. snd_soc_unregister_component(dev);
  2841. component_unbind_all(dev, wcd937x);
  2842. mutex_destroy(&wcd937x->micb_lock);
  2843. mutex_destroy(&wcd937x->ana_tx_clk_lock);
  2844. dev_set_drvdata(dev, NULL);
  2845. kfree(pdata);
  2846. kfree(wcd937x);
  2847. }
  2848. static const struct of_device_id wcd937x_dt_match[] = {
  2849. { .compatible = "qcom,wcd937x-codec" , .data = "wcd937x" },
  2850. {}
  2851. };
  2852. static const struct component_master_ops wcd937x_comp_ops = {
  2853. .bind = wcd937x_bind,
  2854. .unbind = wcd937x_unbind,
  2855. };
  2856. static int wcd937x_compare_of(struct device *dev, void *data)
  2857. {
  2858. return dev->of_node == data;
  2859. }
  2860. static void wcd937x_release_of(struct device *dev, void *data)
  2861. {
  2862. of_node_put(data);
  2863. }
  2864. static int wcd937x_add_slave_components(struct device *dev,
  2865. struct component_match **matchptr)
  2866. {
  2867. struct device_node *np, *rx_node, *tx_node;
  2868. np = dev->of_node;
  2869. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  2870. if (!rx_node) {
  2871. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  2872. return -ENODEV;
  2873. }
  2874. of_node_get(rx_node);
  2875. component_match_add_release(dev, matchptr,
  2876. wcd937x_release_of,
  2877. wcd937x_compare_of,
  2878. rx_node);
  2879. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  2880. if (!tx_node) {
  2881. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  2882. return -ENODEV;
  2883. }
  2884. of_node_get(tx_node);
  2885. component_match_add_release(dev, matchptr,
  2886. wcd937x_release_of,
  2887. wcd937x_compare_of,
  2888. tx_node);
  2889. return 0;
  2890. }
  2891. static int wcd937x_probe(struct platform_device *pdev)
  2892. {
  2893. struct component_match *match = NULL;
  2894. int ret;
  2895. ret = wcd937x_add_slave_components(&pdev->dev, &match);
  2896. if (ret)
  2897. return ret;
  2898. return component_master_add_with_match(&pdev->dev,
  2899. &wcd937x_comp_ops, match);
  2900. }
  2901. static int wcd937x_remove(struct platform_device *pdev)
  2902. {
  2903. component_master_del(&pdev->dev, &wcd937x_comp_ops);
  2904. dev_set_drvdata(&pdev->dev, NULL);
  2905. return 0;
  2906. }
  2907. #ifdef CONFIG_PM_SLEEP
  2908. static const struct dev_pm_ops wcd937x_dev_pm_ops = {
  2909. SET_SYSTEM_SLEEP_PM_OPS(
  2910. wcd937x_suspend,
  2911. wcd937x_resume
  2912. )
  2913. };
  2914. #endif
  2915. static struct platform_driver wcd937x_codec_driver = {
  2916. .probe = wcd937x_probe,
  2917. .remove = wcd937x_remove,
  2918. .driver = {
  2919. .name = "wcd937x_codec",
  2920. .owner = THIS_MODULE,
  2921. .of_match_table = of_match_ptr(wcd937x_dt_match),
  2922. #ifdef CONFIG_PM_SLEEP
  2923. .pm = &wcd937x_dev_pm_ops,
  2924. #endif
  2925. .suppress_bind_attrs = true,
  2926. },
  2927. };
  2928. module_platform_driver(wcd937x_codec_driver);
  2929. MODULE_DESCRIPTION("WCD937X Codec driver");
  2930. MODULE_LICENSE("GPL v2");