wsa884x.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x-registers.h"
  31. #include "wsa884x.h"
  32. #include "internal.h"
  33. #include "asoc/bolero-slave-internal.h"
  34. #include <linux/qti-regmap-debugfs.h>
  35. #define T1_TEMP -10
  36. #define T2_TEMP 150
  37. #define LOW_TEMP_THRESHOLD 5
  38. #define HIGH_TEMP_THRESHOLD 45
  39. #define TEMP_INVALID 0xFFFF
  40. #define WSA884X_TEMP_RETRY 3
  41. #define WSA884X_IRQ_RETRY 2
  42. #define PBR_MAX_VOLTAGE 20
  43. #define PBR_MAX_CODE 255
  44. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  45. #define MAX_NAME_LEN 40
  46. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  47. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  48. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  49. SNDRV_PCM_RATE_384000)
  50. /* Fractional Rates */
  51. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  52. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  53. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  54. SNDRV_PCM_FMTBIT_S24_LE |\
  55. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  56. #define REG_FIELD_VALUE(register_name, field_name, value) \
  57. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  58. value << FIELD_SHIFT(register_name, field_name)
  59. enum {
  60. IDLE_DETECT,
  61. NG1,
  62. NG2,
  63. NG3,
  64. };
  65. struct wsa_temp_register {
  66. u8 d1_msb;
  67. u8 d1_lsb;
  68. u8 d2_msb;
  69. u8 d2_lsb;
  70. u8 dmeas_msb;
  71. u8 dmeas_lsb;
  72. };
  73. enum {
  74. COMP_OFFSET0,
  75. COMP_OFFSET1,
  76. COMP_OFFSET2,
  77. COMP_OFFSET3,
  78. COMP_OFFSET4,
  79. };
  80. #define WSA884X_VTH_TO_REG(vth) \
  81. ((vth) != 0 ? (((vth) - 150) * PBR_MAX_CODE / (PBR_MAX_VOLTAGE * 100) + 1) : 0)
  82. struct wsa_reg_mask_val {
  83. u16 reg;
  84. u8 mask;
  85. u8 val;
  86. };
  87. static const struct wsa_reg_mask_val reg_init[] = {
  88. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  106. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  107. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  108. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  109. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  110. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  111. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  112. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  113. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  114. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  115. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  116. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  117. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  118. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  119. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  120. {REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
  121. {REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
  122. {REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
  123. };
  124. static const struct wsa_reg_mask_val reg_init_2S[] = {
  125. {REG_FIELD_VALUE(CLSH_CTL_1, SLR_MAX, 0x02)},
  126. {REG_FIELD_VALUE(CLSH_V_HD_PA, V_HD_PA, 0x13)},
  127. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_VTH, 0x03)},
  128. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_HYST, 0x03)},
  129. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG2, DAC_VCM_SHIFT, 0x06)},
  130. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG3, DAC_VCM_SHIFT, 0x14)},
  131. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG4, DAC_VCM_SHIFT, 0x19)},
  132. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG5, DAC_VCM_SHIFT, 0x1B)},
  133. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG6, DAC_VCM_SHIFT, 0x1C)},
  134. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG7, DAC_VCM_SHIFT_FINAL_OVERRIDE, 0x01)},
  135. };
  136. static const struct wsa_reg_mask_val reg_init_uvlo[] = {
  137. {WSA884X_UVLO_PROG, 0xFF, 0x77},
  138. {WSA884X_PA_FSM_TIMER0, 0xFF, 0xC0},
  139. {WSA884X_UVLO_DEGLITCH_CTL, 0xFF, 0x1D},
  140. {WSA884X_UVLO_PROG1, 0xFF, 0x40},
  141. };
  142. static int wsa884x_handle_post_irq(void *data);
  143. static int wsa884x_get_temperature(struct snd_soc_component *component,
  144. int *temp);
  145. enum {
  146. WSA8840 = 0,
  147. WSA8845 = 5,
  148. WSA8845H = 0xC,
  149. };
  150. enum {
  151. SPKR_STATUS = 0,
  152. WSA_SUPPLIES_LPM_MODE,
  153. SPKR_ADIE_LB,
  154. };
  155. enum {
  156. COMP_PORT_EN_STATUS_BIT = 0,
  157. VI_PORT_EN_STATUS_BIT,
  158. PBR_PORT_EN_STATUS_BIT,
  159. CPS_PORT_EN_STATUS_BIT,
  160. };
  161. enum {
  162. WSA884X_IRQ_INT_SAF2WAR = 0,
  163. WSA884X_IRQ_INT_WAR2SAF,
  164. WSA884X_IRQ_INT_DISABLE,
  165. WSA884X_IRQ_INT_OCP,
  166. WSA884X_IRQ_INT_CLIP,
  167. WSA884X_IRQ_INT_PDM_WD,
  168. WSA884X_IRQ_INT_CLK_WD,
  169. WSA884X_IRQ_INT_INTR_PIN,
  170. WSA884X_IRQ_INT_UVLO,
  171. WSA884X_IRQ_INT_PA_ON_ERR,
  172. WSA884X_NUM_IRQS,
  173. };
  174. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  175. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  176. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  177. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  178. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  179. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  180. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  181. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  182. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  183. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  184. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  185. };
  186. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  187. .name = "wsa884x",
  188. .irqs = wsa884x_irqs,
  189. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  190. .num_regs = 2,
  191. .status_base = WSA884X_INTR_STATUS0,
  192. .mask_base = WSA884X_INTR_MASK0,
  193. .type_base = WSA884X_INTR_LEVEL0,
  194. .ack_base = WSA884X_INTR_CLEAR0,
  195. .use_ack = 1,
  196. .runtime_pm = false,
  197. .handle_post_irq = wsa884x_handle_post_irq,
  198. .irq_drv_data = NULL,
  199. };
  200. static int wsa884x_handle_post_irq(void *data)
  201. {
  202. struct wsa884x_priv *wsa884x = data;
  203. u32 sts1 = 0, sts2 = 0;
  204. int retry = WSA884X_IRQ_RETRY;
  205. if (!wsa884x)
  206. return IRQ_NONE;
  207. if (!wsa884x->pa_mute) {
  208. do {
  209. wsa884x->pa_mute = 0;
  210. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  211. regmap_update_bits(wsa884x->regmap,
  212. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  213. usleep_range(1000, 1100);
  214. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  215. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  216. wsa884x->swr_slave->slave_irq_pending =
  217. ((sts1 || sts2) ? true : false);
  218. pr_debug("%s: IRQs Sts0: %x, Sts1: %x\n", __func__,
  219. sts1, sts2);
  220. if (wsa884x->swr_slave->slave_irq_pending) {
  221. pr_debug("%s: IRQ retries left: %0d\n",
  222. __func__, retry);
  223. regmap_update_bits(wsa884x->regmap,
  224. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  225. wsa884x->pa_mute = 1;
  226. if (retry--)
  227. usleep_range(1000, 1100);
  228. } else {
  229. break;
  230. }
  231. } while (retry);
  232. }
  233. return IRQ_HANDLED;
  234. }
  235. #ifdef CONFIG_DEBUG_FS
  236. static int codec_debug_open(struct inode *inode, struct file *file)
  237. {
  238. file->private_data = inode->i_private;
  239. return 0;
  240. }
  241. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  242. {
  243. char *token;
  244. int base, cnt;
  245. token = strsep(&buf, " ");
  246. for (cnt = 0; cnt < num_of_par; cnt++) {
  247. if (token) {
  248. if ((token[1] == 'x') || (token[1] == 'X'))
  249. base = 16;
  250. else
  251. base = 10;
  252. if (kstrtou32(token, base, &param1[cnt]) != 0)
  253. return -EINVAL;
  254. token = strsep(&buf, " ");
  255. } else {
  256. return -EINVAL;
  257. }
  258. }
  259. return 0;
  260. }
  261. static bool is_swr_slave_reg_readable(int reg)
  262. {
  263. int ret = true;
  264. if (((reg > 0x46) && (reg < 0x4A)) ||
  265. ((reg > 0x4A) && (reg < 0x50)) ||
  266. ((reg > 0x55) && (reg < 0x60)) ||
  267. ((reg > 0x60) && (reg < 0x70)) ||
  268. ((reg > 0x70) && (reg < 0xC0)) ||
  269. ((reg > 0xC1) && (reg < 0xC8)) ||
  270. ((reg > 0xC8) && (reg < 0xD0)) ||
  271. ((reg > 0xD0) && (reg < 0xE0)) ||
  272. ((reg > 0xE0) && (reg < 0xF0)) ||
  273. ((reg > 0xF0) && (reg < 0x100)) ||
  274. ((reg > 0x105) && (reg < 0x120)) ||
  275. ((reg > 0x205) && (reg < 0x220)) ||
  276. ((reg > 0x305) && (reg < 0x320)) ||
  277. ((reg > 0x405) && (reg < 0x420)) ||
  278. ((reg > 0x505) && (reg < 0x520)) ||
  279. ((reg > 0x605) && (reg < 0x620)) ||
  280. ((reg > 0x127) && (reg < 0x130)) ||
  281. ((reg > 0x227) && (reg < 0x230)) ||
  282. ((reg > 0x327) && (reg < 0x330)) ||
  283. ((reg > 0x427) && (reg < 0x430)) ||
  284. ((reg > 0x527) && (reg < 0x530)) ||
  285. ((reg > 0x627) && (reg < 0x630)) ||
  286. ((reg > 0x137) && (reg < 0x200)) ||
  287. ((reg > 0x237) && (reg < 0x300)) ||
  288. ((reg > 0x337) && (reg < 0x400)) ||
  289. ((reg > 0x437) && (reg < 0x500)) ||
  290. ((reg > 0x537) && (reg < 0x600)) ||
  291. ((reg > 0x637) && (reg < 0xF00)) ||
  292. ((reg > 0xF05) && (reg < 0xF20)) ||
  293. ((reg > 0xF25) && (reg < 0xF30)) ||
  294. ((reg > 0xF35) && (reg < 0x2000)))
  295. ret = false;
  296. return ret;
  297. }
  298. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  299. size_t count, loff_t *ppos)
  300. {
  301. int i, reg_val, len;
  302. ssize_t total = 0;
  303. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  304. if (!ubuf || !ppos)
  305. return 0;
  306. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  307. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  308. if (!is_swr_slave_reg_readable(i))
  309. continue;
  310. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  311. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  312. (reg_val & 0xFF));
  313. if (len < 0) {
  314. pr_err_ratelimited("%s: fail to fill the buffer\n", __func__);
  315. total = -EFAULT;
  316. goto copy_err;
  317. }
  318. if ((total + len) >= count - 1)
  319. break;
  320. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  321. pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
  322. total = -EFAULT;
  323. goto copy_err;
  324. }
  325. total += len;
  326. *ppos += len;
  327. }
  328. copy_err:
  329. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  330. return total;
  331. }
  332. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  333. size_t count, loff_t *ppos)
  334. {
  335. struct swr_device *pdev;
  336. if (!count || !file || !ppos || !ubuf)
  337. return -EINVAL;
  338. pdev = file->private_data;
  339. if (!pdev)
  340. return -EINVAL;
  341. if (*ppos < 0)
  342. return -EINVAL;
  343. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  344. }
  345. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  346. size_t count, loff_t *ppos)
  347. {
  348. char lbuf[SWR_SLV_RD_BUF_LEN];
  349. struct swr_device *pdev = NULL;
  350. struct wsa884x_priv *wsa884x = NULL;
  351. if (!count || !file || !ppos || !ubuf)
  352. return -EINVAL;
  353. pdev = file->private_data;
  354. if (!pdev)
  355. return -EINVAL;
  356. wsa884x = swr_get_dev_data(pdev);
  357. if (!wsa884x)
  358. return -EINVAL;
  359. if (*ppos < 0)
  360. return -EINVAL;
  361. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  362. (wsa884x->read_data & 0xFF));
  363. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  364. strnlen(lbuf, 7));
  365. }
  366. static ssize_t codec_debug_peek_write(struct file *file,
  367. const char __user *ubuf, size_t cnt, loff_t *ppos)
  368. {
  369. char lbuf[SWR_SLV_WR_BUF_LEN];
  370. int rc = 0;
  371. u32 param[5];
  372. struct swr_device *pdev = NULL;
  373. struct wsa884x_priv *wsa884x = NULL;
  374. if (!cnt || !file || !ppos || !ubuf)
  375. return -EINVAL;
  376. pdev = file->private_data;
  377. if (!pdev)
  378. return -EINVAL;
  379. wsa884x = swr_get_dev_data(pdev);
  380. if (!wsa884x)
  381. return -EINVAL;
  382. if (*ppos < 0)
  383. return -EINVAL;
  384. if (cnt > sizeof(lbuf) - 1)
  385. return -EINVAL;
  386. rc = copy_from_user(lbuf, ubuf, cnt);
  387. if (rc)
  388. return -EFAULT;
  389. lbuf[cnt] = '\0';
  390. rc = get_parameters(lbuf, param, 1);
  391. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  392. return -EINVAL;
  393. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  394. if (rc == 0)
  395. rc = cnt;
  396. else
  397. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  398. return rc;
  399. }
  400. static ssize_t codec_debug_write(struct file *file,
  401. const char __user *ubuf, size_t cnt, loff_t *ppos)
  402. {
  403. char lbuf[SWR_SLV_WR_BUF_LEN];
  404. int rc = 0;
  405. u32 param[5];
  406. struct swr_device *pdev;
  407. if (!file || !ppos || !ubuf)
  408. return -EINVAL;
  409. pdev = file->private_data;
  410. if (!pdev)
  411. return -EINVAL;
  412. if (cnt > sizeof(lbuf) - 1)
  413. return -EINVAL;
  414. rc = copy_from_user(lbuf, ubuf, cnt);
  415. if (rc)
  416. return -EFAULT;
  417. lbuf[cnt] = '\0';
  418. rc = get_parameters(lbuf, param, 2);
  419. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  420. (param[1] <= 0xFF) && (rc == 0)))
  421. return -EINVAL;
  422. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  423. if (rc == 0)
  424. rc = cnt;
  425. else
  426. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  427. return rc;
  428. }
  429. static const struct file_operations codec_debug_write_ops = {
  430. .open = codec_debug_open,
  431. .write = codec_debug_write,
  432. };
  433. static const struct file_operations codec_debug_read_ops = {
  434. .open = codec_debug_open,
  435. .read = codec_debug_read,
  436. .write = codec_debug_peek_write,
  437. };
  438. static const struct file_operations codec_debug_dump_ops = {
  439. .open = codec_debug_open,
  440. .read = codec_debug_dump,
  441. };
  442. #endif
  443. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  444. {
  445. mutex_lock(&wsa884x->res_lock);
  446. regcache_mark_dirty(wsa884x->regmap);
  447. regcache_sync(wsa884x->regmap);
  448. mutex_unlock(&wsa884x->res_lock);
  449. }
  450. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  451. {
  452. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  453. __func__, irq);
  454. return IRQ_HANDLED;
  455. }
  456. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  457. {
  458. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  459. __func__, irq);
  460. return IRQ_HANDLED;
  461. }
  462. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  463. {
  464. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  465. __func__, irq);
  466. return IRQ_HANDLED;
  467. }
  468. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  469. {
  470. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  471. __func__, irq);
  472. return IRQ_HANDLED;
  473. }
  474. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  475. {
  476. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  477. __func__, irq);
  478. return IRQ_HANDLED;
  479. }
  480. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  481. {
  482. struct wsa884x_priv *wsa884x = data;
  483. struct snd_soc_component *component = NULL;
  484. if (!wsa884x)
  485. return IRQ_NONE;
  486. component = wsa884x->component;
  487. snd_soc_component_update_bits(component,
  488. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  489. snd_soc_component_update_bits(component,
  490. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  491. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  492. __func__, irq);
  493. return IRQ_HANDLED;
  494. }
  495. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  496. {
  497. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  498. __func__, irq);
  499. return IRQ_HANDLED;
  500. }
  501. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  502. {
  503. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  504. __func__, irq);
  505. return IRQ_HANDLED;
  506. }
  507. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  508. {
  509. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  510. __func__, irq);
  511. return IRQ_HANDLED;
  512. }
  513. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  514. {
  515. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  516. struct wsa884x_priv *wsa884x = data;
  517. struct snd_soc_component *component = NULL;
  518. if (!wsa884x)
  519. return IRQ_NONE;
  520. component = wsa884x->component;
  521. if (!component)
  522. return IRQ_NONE;
  523. snd_soc_component_update_bits(component,
  524. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  525. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  526. & 0x1F);
  527. if (pa_fsm_sta)
  528. pa_fsm_err = snd_soc_component_read(component,
  529. WSA884X_PA_FSM_ERR_COND0);
  530. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  531. __func__, irq);
  532. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  533. 0x10, 0x00);
  534. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  535. 0x10, 0x10);
  536. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  537. 0x10, 0x00);
  538. return IRQ_HANDLED;
  539. }
  540. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  541. {
  542. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  543. u8 igain;
  544. u8 vgain;
  545. switch (wsa884x->bat_cfg) {
  546. case CONFIG_1S:
  547. case EXT_1S:
  548. switch (wsa884x->system_gain) {
  549. case G_21_DB:
  550. wsa884x->comp_offset = COMP_OFFSET0;
  551. wsa884x->min_gain = G_0_DB;
  552. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  553. break;
  554. case G_19P5_DB:
  555. wsa884x->comp_offset = COMP_OFFSET1;
  556. wsa884x->min_gain = G_M1P5_DB;
  557. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  558. break;
  559. case G_18_DB:
  560. wsa884x->comp_offset = COMP_OFFSET2;
  561. wsa884x->min_gain = G_M3_DB;
  562. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  563. break;
  564. case G_16P5_DB:
  565. wsa884x->comp_offset = COMP_OFFSET3;
  566. wsa884x->min_gain = G_M4P5_DB;
  567. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  568. break;
  569. default:
  570. wsa884x->comp_offset = COMP_OFFSET4;
  571. wsa884x->min_gain = G_M6_DB;
  572. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  573. break;
  574. }
  575. break;
  576. case CONFIG_3S:
  577. case EXT_3S:
  578. wsa884x->comp_offset = COMP_OFFSET0;
  579. wsa884x->min_gain = G_7P5_DB;
  580. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  581. break;
  582. case EXT_ABOVE_3S:
  583. wsa884x->comp_offset = COMP_OFFSET0;
  584. wsa884x->min_gain = G_12_DB;
  585. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  586. break;
  587. default:
  588. wsa884x->comp_offset = COMP_OFFSET0;
  589. wsa884x->min_gain = G_0_DB;
  590. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  591. break;
  592. }
  593. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  594. vgain = vsense_gain_data[wsa884x->system_gain];
  595. snd_soc_component_update_bits(component,
  596. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  597. snd_soc_component_update_bits(component,
  598. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  599. snd_soc_component_update_bits(component,
  600. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  601. if (wsa884x->comp_enable) {
  602. snd_soc_component_update_bits(component,
  603. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  604. wsa884x->comp_offset));
  605. snd_soc_component_update_bits(component,
  606. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  607. } else {
  608. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
  609. snd_soc_component_update_bits(component,
  610. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  611. snd_soc_component_update_bits(component,
  612. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  613. }
  614. return 0;
  615. }
  616. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  617. {
  618. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  619. int vth1_reg_val;
  620. int vth2_reg_val;
  621. int vth3_reg_val;
  622. int vth4_reg_val;
  623. int vth5_reg_val;
  624. int vth6_reg_val;
  625. int vth7_reg_val;
  626. int vth8_reg_val;
  627. int vth9_reg_val;
  628. int vth10_reg_val;
  629. int vth11_reg_val;
  630. int vth12_reg_val;
  631. int vth13_reg_val;
  632. int vth14_reg_val;
  633. int vth15_reg_val;
  634. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  635. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  636. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  637. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  638. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  639. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  640. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  641. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  642. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  643. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  644. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  645. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  646. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  647. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  648. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  649. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  650. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  651. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  652. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  653. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  654. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  655. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  656. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  657. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  658. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  659. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  660. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  661. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  662. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  663. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  664. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  665. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  666. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  667. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  668. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  669. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  670. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  671. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  672. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  673. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  674. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  675. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  676. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  677. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  678. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  679. return 0;
  680. }
  681. static void wsa_noise_gate_write(struct snd_soc_component *component,
  682. int imode)
  683. {
  684. switch (imode) {
  685. case NG1:
  686. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  687. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  688. break;
  689. case NG2:
  690. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  691. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x20);
  692. break;
  693. case NG3:
  694. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  695. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x10);
  696. break;
  697. default:
  698. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  699. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  700. break;
  701. }
  702. }
  703. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  704. struct snd_ctl_elem_value *ucontrol)
  705. {
  706. struct snd_soc_component *component =
  707. snd_soc_kcontrol_component(kcontrol);
  708. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  709. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  710. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  711. wsa884x->dev_mode);
  712. return 0;
  713. }
  714. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  715. struct snd_ctl_elem_value *ucontrol)
  716. {
  717. struct snd_soc_component *component =
  718. snd_soc_kcontrol_component(kcontrol);
  719. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  720. int dev_mode;
  721. int wsa_dev_index;
  722. if ((ucontrol->value.integer.value[0] >= SPEAKER) &&
  723. (ucontrol->value.integer.value[0] < MAX_DEV_MODE))
  724. dev_mode = ucontrol->value.integer.value[0];
  725. else
  726. return -EINVAL;
  727. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d\n",
  728. __func__, wsa884x->dev_mode, dev_mode);
  729. /* Check if input parameter is in range */
  730. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  731. if ((dev_mode + wsa_dev_index * 2) < (MAX_DEV_MODE * 2)) {
  732. wsa884x->dev_mode = dev_mode;
  733. wsa884x->system_gain = wsa884x->sys_gains[dev_mode + wsa_dev_index * 2];
  734. } else {
  735. return -EINVAL;
  736. }
  737. return 0;
  738. }
  739. static const char * const wsa_pa_gain_text[] = {
  740. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  741. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  742. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  743. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  744. };
  745. static const struct soc_enum wsa_pa_gain_enum =
  746. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  747. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  748. struct snd_ctl_elem_value *ucontrol)
  749. {
  750. struct snd_soc_component *component =
  751. snd_soc_kcontrol_component(kcontrol);
  752. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  753. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  754. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  755. wsa884x->pa_gain);
  756. return 0;
  757. }
  758. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  759. struct snd_ctl_elem_value *ucontrol)
  760. {
  761. struct snd_soc_component *component =
  762. snd_soc_kcontrol_component(kcontrol);
  763. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  764. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  765. __func__, ucontrol->value.integer.value[0]);
  766. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  767. return 0;
  768. }
  769. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  770. struct snd_ctl_elem_value *ucontrol)
  771. {
  772. struct snd_soc_component *component =
  773. snd_soc_kcontrol_component(kcontrol);
  774. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  775. int temp = 0;
  776. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  777. temp = wsa884x->curr_temp;
  778. else
  779. wsa884x_get_temperature(component, &temp);
  780. ucontrol->value.integer.value[0] = temp;
  781. return 0;
  782. }
  783. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  784. void *file_private_data, struct file *file,
  785. char __user *buf, size_t count, loff_t pos)
  786. {
  787. struct wsa884x_priv *wsa884x;
  788. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  789. int len = 0;
  790. wsa884x = (struct wsa884x_priv *) entry->private_data;
  791. if (!wsa884x) {
  792. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  793. return -EINVAL;
  794. }
  795. switch (wsa884x->version) {
  796. case WSA884X_VERSION_1_0:
  797. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  798. break;
  799. default:
  800. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  801. break;
  802. }
  803. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  804. }
  805. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  806. .read = wsa884x_codec_version_read,
  807. };
  808. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  809. void *file_private_data,
  810. struct file *file,
  811. char __user *buf, size_t count,
  812. loff_t pos)
  813. {
  814. struct wsa884x_priv *wsa884x;
  815. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  816. int len = 0;
  817. wsa884x = (struct wsa884x_priv *) entry->private_data;
  818. if (!wsa884x) {
  819. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  820. return -EINVAL;
  821. }
  822. switch (wsa884x->variant) {
  823. case WSA8840:
  824. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  825. break;
  826. case WSA8845:
  827. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  828. break;
  829. case WSA8845H:
  830. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  831. break;
  832. default:
  833. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  834. break;
  835. }
  836. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  837. }
  838. static struct snd_info_entry_ops wsa884x_variant_ops = {
  839. .read = wsa884x_variant_read,
  840. };
  841. /*
  842. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  843. * @codec_root: The parent directory
  844. * @component: Codec instance
  845. *
  846. * Creates wsa884x module and version entry under the given
  847. * parent directory.
  848. *
  849. * Return: 0 on success or negative error code on failure.
  850. */
  851. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  852. struct snd_soc_component *component)
  853. {
  854. struct snd_info_entry *version_entry;
  855. struct snd_info_entry *variant_entry;
  856. struct wsa884x_priv *wsa884x;
  857. struct snd_soc_card *card;
  858. char name[80];
  859. if (!codec_root || !component)
  860. return -EINVAL;
  861. wsa884x = snd_soc_component_get_drvdata(component);
  862. if (wsa884x->entry) {
  863. dev_dbg(wsa884x->dev,
  864. "%s:wsa884x module already created\n", __func__);
  865. return 0;
  866. }
  867. card = component->card;
  868. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  869. wsa884x->swr_slave->addr);
  870. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  871. (const char *)name,
  872. codec_root);
  873. if (!wsa884x->entry) {
  874. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  875. __func__);
  876. return -ENOMEM;
  877. }
  878. wsa884x->entry->mode = S_IFDIR | 0555;
  879. if (snd_info_register(wsa884x->entry) < 0) {
  880. snd_info_free_entry(wsa884x->entry);
  881. return -ENOMEM;
  882. }
  883. version_entry = snd_info_create_card_entry(card->snd_card,
  884. "version",
  885. wsa884x->entry);
  886. if (!version_entry) {
  887. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  888. __func__);
  889. snd_info_free_entry(wsa884x->entry);
  890. return -ENOMEM;
  891. }
  892. version_entry->private_data = wsa884x;
  893. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  894. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  895. version_entry->c.ops = &wsa884x_codec_info_ops;
  896. if (snd_info_register(version_entry) < 0) {
  897. snd_info_free_entry(version_entry);
  898. snd_info_free_entry(wsa884x->entry);
  899. return -ENOMEM;
  900. }
  901. wsa884x->version_entry = version_entry;
  902. variant_entry = snd_info_create_card_entry(card->snd_card,
  903. "variant",
  904. wsa884x->entry);
  905. if (!variant_entry) {
  906. dev_dbg(component->dev,
  907. "%s: failed to create wsa884x variant entry\n",
  908. __func__);
  909. snd_info_free_entry(version_entry);
  910. snd_info_free_entry(wsa884x->entry);
  911. return -ENOMEM;
  912. }
  913. variant_entry->private_data = wsa884x;
  914. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  915. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  916. variant_entry->c.ops = &wsa884x_variant_ops;
  917. if (snd_info_register(variant_entry) < 0) {
  918. snd_info_free_entry(variant_entry);
  919. snd_info_free_entry(version_entry);
  920. snd_info_free_entry(wsa884x->entry);
  921. return -ENOMEM;
  922. }
  923. wsa884x->variant_entry = variant_entry;
  924. return 0;
  925. }
  926. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  927. /*
  928. * wsa884x_codec_get_dev_num - returns swr device number
  929. * @component: Codec instance
  930. *
  931. * Return: swr device number on success or negative error
  932. * code on failure.
  933. */
  934. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  935. {
  936. struct wsa884x_priv *wsa884x;
  937. if (!component)
  938. return -EINVAL;
  939. wsa884x = snd_soc_component_get_drvdata(component);
  940. if (!wsa884x) {
  941. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  942. return -EINVAL;
  943. }
  944. return wsa884x->swr_slave->dev_num;
  945. }
  946. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  947. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  948. struct snd_ctl_elem_value *ucontrol)
  949. {
  950. struct snd_soc_component *component =
  951. snd_soc_kcontrol_component(kcontrol);
  952. struct wsa884x_priv *wsa884x;
  953. if (!component)
  954. return -EINVAL;
  955. wsa884x = snd_soc_component_get_drvdata(component);
  956. if (!wsa884x) {
  957. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  958. return -EINVAL;
  959. }
  960. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  961. return 0;
  962. }
  963. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  964. struct snd_ctl_elem_value *ucontrol)
  965. {
  966. struct snd_soc_component *component =
  967. snd_soc_kcontrol_component(kcontrol);
  968. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  969. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  970. return 0;
  971. }
  972. /*
  973. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  974. * Return: 0 Valid configuration, 1 Invalid configuration
  975. */
  976. static bool wsa884x_validate_dt_configuration_params(struct snd_soc_component *component,
  977. u8 irload, u8 ibat_cfg_dts, u8 isystem_gain)
  978. {
  979. u8 bat_cfg_reg;
  980. bool is_invalid_flag = true;
  981. bat_cfg_reg = snd_soc_component_read(component, WSA884X_VPHX_SYS_EN_STATUS);
  982. dev_info(component->dev, "VPHX EN Status: %d", bat_cfg_reg);
  983. if ((ibat_cfg_dts == EXT_1S) || (ibat_cfg_dts == EXT_2S) || (ibat_cfg_dts == EXT_3S))
  984. ibat_cfg_dts = EXT_ABOVE_3S;
  985. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  986. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  987. (EXT_ABOVE_3S <= ibat_cfg_dts && ibat_cfg_dts < CONFIG_MAX) &&
  988. (ibat_cfg_dts == bat_cfg_reg))
  989. is_invalid_flag = false;
  990. return is_invalid_flag;
  991. }
  992. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  993. struct snd_ctl_elem_value *ucontrol)
  994. {
  995. struct snd_soc_component *component =
  996. snd_soc_kcontrol_component(kcontrol);
  997. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  998. int value = ucontrol->value.integer.value[0];
  999. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  1000. __func__, wsa884x->comp_enable, value);
  1001. wsa884x->comp_enable = value;
  1002. return 0;
  1003. }
  1004. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  1005. struct snd_ctl_elem_value *ucontrol)
  1006. {
  1007. struct snd_soc_component *component =
  1008. snd_soc_kcontrol_component(kcontrol);
  1009. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1010. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  1011. return 0;
  1012. }
  1013. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  1014. struct snd_ctl_elem_value *ucontrol)
  1015. {
  1016. struct snd_soc_component *component =
  1017. snd_soc_kcontrol_component(kcontrol);
  1018. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1019. int value = ucontrol->value.integer.value[0];
  1020. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  1021. __func__, wsa884x->visense_enable, value);
  1022. wsa884x->visense_enable = value;
  1023. return 0;
  1024. }
  1025. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  1026. struct snd_ctl_elem_value *ucontrol)
  1027. {
  1028. struct snd_soc_component *component =
  1029. snd_soc_kcontrol_component(kcontrol);
  1030. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1031. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  1032. return 0;
  1033. }
  1034. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  1035. struct snd_ctl_elem_value *ucontrol)
  1036. {
  1037. struct snd_soc_component *component =
  1038. snd_soc_kcontrol_component(kcontrol);
  1039. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1040. int value = ucontrol->value.integer.value[0];
  1041. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  1042. __func__, wsa884x->pbr_enable, value);
  1043. wsa884x->pbr_enable = value;
  1044. return 0;
  1045. }
  1046. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  1047. struct snd_ctl_elem_value *ucontrol)
  1048. {
  1049. struct snd_soc_component *component =
  1050. snd_soc_kcontrol_component(kcontrol);
  1051. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1052. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  1053. return 0;
  1054. }
  1055. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  1056. struct snd_ctl_elem_value *ucontrol)
  1057. {
  1058. struct snd_soc_component *component =
  1059. snd_soc_kcontrol_component(kcontrol);
  1060. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1061. int value = ucontrol->value.integer.value[0];
  1062. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  1063. __func__, wsa884x->cps_enable, value);
  1064. wsa884x->cps_enable = value;
  1065. return 0;
  1066. }
  1067. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  1068. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  1069. wsa_pa_gain_get, wsa_pa_gain_put),
  1070. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1071. wsa_get_temp, NULL),
  1072. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1073. wsa884x_get_dev_num, NULL),
  1074. SOC_SINGLE_EXT("WSA MODE", SND_SOC_NOPM, 0, 1, 0,
  1075. wsa_dev_mode_get, wsa_dev_mode_put),
  1076. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1077. wsa884x_get_compander, wsa884x_set_compander),
  1078. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1079. wsa884x_get_visense, wsa884x_set_visense),
  1080. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1081. wsa884x_get_pbr, wsa884x_set_pbr),
  1082. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1083. wsa884x_get_cps, wsa884x_set_cps),
  1084. };
  1085. static const struct snd_kcontrol_new swr_dac_port[] = {
  1086. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1087. };
  1088. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1089. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1090. u8 *port_type)
  1091. {
  1092. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1093. *port_id = wsa884x->port[port_idx].port_id;
  1094. *num_ch = wsa884x->port[port_idx].num_ch;
  1095. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1096. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1097. *port_type = wsa884x->port[port_idx].port_type;
  1098. return 0;
  1099. }
  1100. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1101. struct snd_kcontrol *kcontrol, int event)
  1102. {
  1103. struct snd_soc_component *component =
  1104. snd_soc_dapm_to_component(w->dapm);
  1105. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1106. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1107. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1108. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1109. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1110. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1111. u8 num_port = 0;
  1112. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1113. event, w->name);
  1114. if (wsa884x == NULL)
  1115. return -EINVAL;
  1116. switch (event) {
  1117. case SND_SOC_DAPM_PRE_PMU:
  1118. wsa884x_set_port(component, SWR_DAC_PORT,
  1119. &port_id[num_port], &num_ch[num_port],
  1120. &ch_mask[num_port], &ch_rate[num_port],
  1121. &port_type[num_port]);
  1122. if (wsa884x->dev_mode == RECEIVER)
  1123. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1124. ++num_port;
  1125. wsa884x_set_port(component, SWR_COMP_PORT,
  1126. &port_id[num_port], &num_ch[num_port],
  1127. &ch_mask[num_port], &ch_rate[num_port],
  1128. &port_type[num_port]);
  1129. ++num_port;
  1130. if (wsa884x->pbr_enable) {
  1131. wsa884x_set_port(component, SWR_PBR_PORT,
  1132. &port_id[num_port], &num_ch[num_port],
  1133. &ch_mask[num_port], &ch_rate[num_port],
  1134. &port_type[num_port]);
  1135. ++num_port;
  1136. set_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1137. }
  1138. if (wsa884x->visense_enable) {
  1139. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1140. &port_id[num_port], &num_ch[num_port],
  1141. &ch_mask[num_port], &ch_rate[num_port],
  1142. &port_type[num_port]);
  1143. ++num_port;
  1144. set_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1145. }
  1146. if (wsa884x->cps_enable) {
  1147. wsa884x_set_port(component, SWR_CPS_PORT,
  1148. &port_id[num_port], &num_ch[num_port],
  1149. &ch_mask[num_port], &ch_rate[num_port],
  1150. &port_type[num_port]);
  1151. ++num_port;
  1152. set_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1153. }
  1154. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1155. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1156. &port_type[0]);
  1157. break;
  1158. case SND_SOC_DAPM_POST_PMU:
  1159. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1160. break;
  1161. case SND_SOC_DAPM_PRE_PMD:
  1162. wsa884x_set_port(component, SWR_DAC_PORT,
  1163. &port_id[num_port], &num_ch[num_port],
  1164. &ch_mask[num_port], &ch_rate[num_port],
  1165. &port_type[num_port]);
  1166. ++num_port;
  1167. wsa884x_set_port(component, SWR_COMP_PORT,
  1168. &port_id[num_port], &num_ch[num_port],
  1169. &ch_mask[num_port], &ch_rate[num_port],
  1170. &port_type[num_port]);
  1171. ++num_port;
  1172. if (wsa884x->pbr_enable &&
  1173. test_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1174. wsa884x_set_port(component, SWR_PBR_PORT,
  1175. &port_id[num_port], &num_ch[num_port],
  1176. &ch_mask[num_port], &ch_rate[num_port],
  1177. &port_type[num_port]);
  1178. ++num_port;
  1179. clear_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1180. }
  1181. if (wsa884x->visense_enable &&
  1182. test_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1183. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1184. &port_id[num_port], &num_ch[num_port],
  1185. &ch_mask[num_port], &ch_rate[num_port],
  1186. &port_type[num_port]);
  1187. ++num_port;
  1188. clear_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1189. }
  1190. if (wsa884x->cps_enable &&
  1191. test_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1192. wsa884x_set_port(component, SWR_CPS_PORT,
  1193. &port_id[num_port], &num_ch[num_port],
  1194. &ch_mask[num_port], &ch_rate[num_port],
  1195. &port_type[num_port]);
  1196. ++num_port;
  1197. clear_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1198. }
  1199. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1200. &ch_mask[0], &port_type[0]);
  1201. break;
  1202. case SND_SOC_DAPM_POST_PMD:
  1203. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1204. dev_err_ratelimited(component->dev,
  1205. "%s: set num ch failed\n", __func__);
  1206. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1207. wsa884x->swr_slave->dev_num,
  1208. false);
  1209. break;
  1210. default:
  1211. break;
  1212. }
  1213. return 0;
  1214. }
  1215. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1216. struct snd_kcontrol *kcontrol, int event)
  1217. {
  1218. struct snd_soc_component *component =
  1219. snd_soc_dapm_to_component(w->dapm);
  1220. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1221. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1222. switch (event) {
  1223. case SND_SOC_DAPM_POST_PMU:
  1224. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1225. wsa884x->swr_slave->dev_num,
  1226. true);
  1227. wsa884x_set_gain_parameters(component);
  1228. if (wsa884x->dev_mode == SPEAKER) {
  1229. snd_soc_component_update_bits(component,
  1230. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1231. } else {
  1232. snd_soc_component_update_bits(component,
  1233. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1234. snd_soc_component_update_bits(component,
  1235. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1236. snd_soc_component_update_bits(component,
  1237. REG_FIELD_VALUE(PWM_CLK_CTL,
  1238. PWM_CLK_FREQ_SEL, 0x01));
  1239. }
  1240. if (wsa884x->pbr_enable) {
  1241. snd_soc_component_update_bits(component,
  1242. REG_FIELD_VALUE(CURRENT_LIMIT,
  1243. CURRENT_LIMIT_OVRD_EN, 0x00));
  1244. switch (wsa884x->bat_cfg) {
  1245. case CONFIG_1S:
  1246. snd_soc_component_update_bits(component,
  1247. REG_FIELD_VALUE(CURRENT_LIMIT,
  1248. CURRENT_LIMIT, 0x15));
  1249. break;
  1250. case CONFIG_2S:
  1251. snd_soc_component_update_bits(component,
  1252. REG_FIELD_VALUE(CURRENT_LIMIT,
  1253. CURRENT_LIMIT, 0x11));
  1254. break;
  1255. case CONFIG_3S:
  1256. snd_soc_component_update_bits(component,
  1257. REG_FIELD_VALUE(CURRENT_LIMIT,
  1258. CURRENT_LIMIT, 0x0D));
  1259. break;
  1260. }
  1261. } else {
  1262. snd_soc_component_update_bits(component,
  1263. REG_FIELD_VALUE(CURRENT_LIMIT,
  1264. CURRENT_LIMIT_OVRD_EN, 0x01));
  1265. if (wsa884x->system_gain >= G_12_DB)
  1266. snd_soc_component_update_bits(component,
  1267. REG_FIELD_VALUE(CURRENT_LIMIT,
  1268. CURRENT_LIMIT, 0x15));
  1269. else
  1270. snd_soc_component_update_bits(component,
  1271. REG_FIELD_VALUE(CURRENT_LIMIT,
  1272. CURRENT_LIMIT, 0x09));
  1273. }
  1274. /* Force remove group */
  1275. swr_remove_from_group(wsa884x->swr_slave,
  1276. wsa884x->swr_slave->dev_num);
  1277. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask) &&
  1278. !wsa884x->pa_mute)
  1279. snd_soc_component_update_bits(component,
  1280. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1281. break;
  1282. case SND_SOC_DAPM_PRE_PMD:
  1283. snd_soc_component_update_bits(component,
  1284. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1285. snd_soc_component_update_bits(component,
  1286. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1287. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1288. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1289. wsa884x->pa_mute = 0;
  1290. break;
  1291. }
  1292. return 0;
  1293. }
  1294. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1295. SND_SOC_DAPM_INPUT("IN"),
  1296. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1297. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1298. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1299. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1300. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1301. };
  1302. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1303. {"SWR DAC_Port", "Switch", "IN"},
  1304. {"SPKR", NULL, "SWR DAC_Port"},
  1305. };
  1306. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1307. u8 num_port, unsigned int *ch_mask,
  1308. unsigned int *ch_rate, u8 *port_type)
  1309. {
  1310. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1311. int i;
  1312. if (!port || !ch_mask || !ch_rate ||
  1313. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1314. dev_err_ratelimited(component->dev,
  1315. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1316. __func__, port, ch_mask, ch_rate);
  1317. return -EINVAL;
  1318. }
  1319. for (i = 0; i < num_port; i++) {
  1320. wsa884x->port[i].port_id = port[i];
  1321. wsa884x->port[i].ch_mask = ch_mask[i];
  1322. wsa884x->port[i].ch_rate = ch_rate[i];
  1323. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1324. if (port_type)
  1325. wsa884x->port[i].port_type = port_type[i];
  1326. }
  1327. return 0;
  1328. }
  1329. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1330. static void wsa884x_codec_init(struct snd_soc_component *component)
  1331. {
  1332. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1333. int i;
  1334. if (!wsa884x)
  1335. return;
  1336. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1337. snd_soc_component_update_bits(component, reg_init[i].reg,
  1338. reg_init[i].mask, reg_init[i].val);
  1339. /* Register updates for 2S battery configuration */
  1340. if (wsa884x->bat_cfg == CONFIG_2S) {
  1341. for (i = 0; i < ARRAY_SIZE(reg_init_2S); i++)
  1342. snd_soc_component_update_bits(component, reg_init_2S[i].reg,
  1343. reg_init_2S[i].mask, reg_init_2S[i].val);
  1344. }
  1345. for (i = 0; i < ARRAY_SIZE(reg_init_uvlo); i++)
  1346. snd_soc_component_update_bits(component, reg_init_uvlo[i].reg,
  1347. reg_init_uvlo[i].mask, reg_init_uvlo[i].val);
  1348. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1349. }
  1350. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1351. struct wsa_temp_register *wsa_temp_reg)
  1352. {
  1353. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1354. if (!wsa884x) {
  1355. dev_err_ratelimited(component->dev, "%s: wsa884x is NULL\n", __func__);
  1356. return -EINVAL;
  1357. }
  1358. mutex_lock(&wsa884x->res_lock);
  1359. snd_soc_component_update_bits(component,
  1360. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1361. snd_soc_component_update_bits(component,
  1362. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1363. snd_soc_component_update_bits(component,
  1364. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1365. snd_soc_component_update_bits(component,
  1366. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1367. snd_soc_component_update_bits(component,
  1368. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1369. snd_soc_component_update_bits(component,
  1370. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1371. snd_soc_component_update_bits(component,
  1372. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1373. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1374. WSA884X_TEMP_DIN_MSB);
  1375. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1376. WSA884X_TEMP_DIN_LSB);
  1377. snd_soc_component_update_bits(component,
  1378. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1379. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1380. WSA884X_OTP_REG_1);
  1381. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1382. WSA884X_OTP_REG_2);
  1383. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1384. WSA884X_OTP_REG_3);
  1385. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1386. WSA884X_OTP_REG_4);
  1387. snd_soc_component_update_bits(component,
  1388. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1389. mutex_unlock(&wsa884x->res_lock);
  1390. return 0;
  1391. }
  1392. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1393. int *temp)
  1394. {
  1395. struct wsa_temp_register reg;
  1396. int dmeas, d1, d2;
  1397. int ret = 0;
  1398. int temp_val = 0;
  1399. int t1 = T1_TEMP;
  1400. int t2 = T2_TEMP;
  1401. u8 retry = WSA884X_TEMP_RETRY;
  1402. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1403. if (!wsa884x)
  1404. return -EINVAL;
  1405. do {
  1406. ret = wsa884x_temp_reg_read(component, &reg);
  1407. if (ret) {
  1408. pr_err_ratelimited("%s: temp read failed: %d, current temp: %d\n",
  1409. __func__, ret, wsa884x->curr_temp);
  1410. if (temp)
  1411. *temp = wsa884x->curr_temp;
  1412. return 0;
  1413. }
  1414. /*
  1415. * Temperature register values are expected to be in the
  1416. * following range.
  1417. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1418. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1419. */
  1420. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1421. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1422. reg.d1_lsb == 192)) ||
  1423. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1424. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1425. reg.d2_lsb == 192))) {
  1426. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1427. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1428. reg.d2_lsb);
  1429. }
  1430. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1431. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1432. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1433. if (d1 == d2)
  1434. temp_val = TEMP_INVALID;
  1435. else
  1436. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1437. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1438. temp_val >= HIGH_TEMP_THRESHOLD) {
  1439. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1440. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1441. if (retry--)
  1442. msleep(10);
  1443. } else {
  1444. break;
  1445. }
  1446. } while (retry);
  1447. wsa884x->curr_temp = temp_val;
  1448. if (temp)
  1449. *temp = temp_val;
  1450. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1451. __func__, temp_val, dmeas, d1, d2);
  1452. return ret;
  1453. }
  1454. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1455. {
  1456. char w_name[MAX_NAME_LEN];
  1457. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1458. struct swr_device *dev;
  1459. int variant = 0, version = 0;
  1460. struct snd_soc_dapm_context *dapm =
  1461. snd_soc_component_get_dapm(component);
  1462. if (!wsa884x)
  1463. return -EINVAL;
  1464. if (!component->name_prefix)
  1465. return -EINVAL;
  1466. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1467. dev = wsa884x->swr_slave;
  1468. wsa884x->component = component;
  1469. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1470. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1471. wsa884x->variant = variant;
  1472. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1473. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1474. wsa884x->version = version;
  1475. wsa884x->comp_offset = COMP_OFFSET2;
  1476. wsa884x_codec_init(component);
  1477. wsa884x->global_pa_cnt = 0;
  1478. memset(w_name, 0, sizeof(w_name));
  1479. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1480. sizeof(w_name));
  1481. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1482. memset(w_name, 0, sizeof(w_name));
  1483. strlcpy(w_name, "IN", sizeof(w_name));
  1484. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1485. memset(w_name, 0, sizeof(w_name));
  1486. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1487. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1488. memset(w_name, 0, sizeof(w_name));
  1489. strlcpy(w_name, "SPKR", sizeof(w_name));
  1490. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1491. snd_soc_dapm_sync(dapm);
  1492. return 0;
  1493. }
  1494. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1495. {
  1496. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1497. if (!wsa884x)
  1498. return;
  1499. snd_soc_component_exit_regmap(component);
  1500. return;
  1501. }
  1502. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1503. {
  1504. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1505. if (!wsa884x)
  1506. return 0;
  1507. wsa884x->dapm_bias_off = true;
  1508. return 0;
  1509. }
  1510. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1511. {
  1512. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1513. if (!wsa884x)
  1514. return 0;
  1515. wsa884x->dapm_bias_off = false;
  1516. return 0;
  1517. }
  1518. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1519. .name = "",
  1520. .probe = wsa884x_codec_probe,
  1521. .remove = wsa884x_codec_remove,
  1522. .controls = wsa884x_snd_controls,
  1523. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1524. .dapm_widgets = wsa884x_dapm_widgets,
  1525. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1526. .dapm_routes = wsa884x_audio_map,
  1527. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1528. .suspend = wsa884x_soc_codec_suspend,
  1529. .resume = wsa884x_soc_codec_resume,
  1530. };
  1531. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1532. {
  1533. int ret = 0;
  1534. if (enable)
  1535. ret = msm_cdc_pinctrl_select_active_state(
  1536. wsa884x->wsa_rst_np);
  1537. else
  1538. ret = msm_cdc_pinctrl_select_sleep_state(
  1539. wsa884x->wsa_rst_np);
  1540. if (ret != 0)
  1541. dev_err_ratelimited(wsa884x->dev,
  1542. "%s: Failed to turn state %d; ret=%d\n",
  1543. __func__, enable, ret);
  1544. return ret;
  1545. }
  1546. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1547. {
  1548. int ret;
  1549. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1550. if (ret)
  1551. dev_err_ratelimited(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1552. return ret;
  1553. }
  1554. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1555. {
  1556. int ret;
  1557. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1558. if (ret)
  1559. dev_err_ratelimited(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1560. return ret;
  1561. }
  1562. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1563. {
  1564. u8 retry = WSA884X_NUM_RETRY;
  1565. u8 devnum = 0;
  1566. struct swr_device *pdev;
  1567. pdev = wsa884x->swr_slave;
  1568. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1569. /* Retry after 1 msec delay */
  1570. usleep_range(1000, 1100);
  1571. }
  1572. pdev->dev_num = devnum;
  1573. wsa884x_regcache_sync(wsa884x);
  1574. return 0;
  1575. }
  1576. static int wsa884x_event_notify(struct notifier_block *nb,
  1577. unsigned long val, void *ptr)
  1578. {
  1579. u16 event = (val & 0xffff);
  1580. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1581. parent_nblock);
  1582. if (!wsa884x)
  1583. return -EINVAL;
  1584. switch (event) {
  1585. case BOLERO_SLV_EVT_SSR_UP:
  1586. wsa884x_swr_down(wsa884x);
  1587. usleep_range(500, 510);
  1588. wsa884x_swr_up(wsa884x);
  1589. /* Add delay to allow enumerate */
  1590. usleep_range(20000, 20010);
  1591. wsa884x_swr_reset(wsa884x);
  1592. dev_err(wsa884x->dev, "%s: BOLERO_SLV_EVT_SSR_UP Called", __func__);
  1593. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1594. wsa884x->swr_wsa_port_params);
  1595. break;
  1596. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1597. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1598. snd_soc_component_update_bits(wsa884x->component,
  1599. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1600. snd_soc_component_update_bits(wsa884x->component,
  1601. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1602. }
  1603. break;
  1604. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1605. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1606. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1607. break;
  1608. default:
  1609. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1610. __func__, event);
  1611. break;
  1612. }
  1613. return 0;
  1614. }
  1615. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1616. {
  1617. u32 *dt_array, map_size, max_uc;
  1618. int ret = 0;
  1619. u32 cnt = 0;
  1620. u32 i, j;
  1621. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1622. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1623. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1624. map = &wsa884x->wsa_port_params;
  1625. map_uc = &wsa884x->swr_wsa_port_params;
  1626. if (!of_find_property(dev->of_node, prop,
  1627. &map_size)) {
  1628. dev_err(dev, "missing port mapping prop %s\n", prop);
  1629. ret = -EINVAL;
  1630. goto err_port_map;
  1631. }
  1632. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1633. if (max_uc != SWR_UC_MAX) {
  1634. dev_err(dev, "%s: port params not provided for all usecases\n",
  1635. __func__);
  1636. ret = -EINVAL;
  1637. goto err_port_map;
  1638. }
  1639. dt_array = kzalloc(map_size, GFP_KERNEL);
  1640. if (!dt_array) {
  1641. ret = -ENOMEM;
  1642. goto err_port_map;
  1643. }
  1644. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1645. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1646. if (ret) {
  1647. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1648. __func__, prop);
  1649. goto err_pdata_fail;
  1650. }
  1651. for (i = 0; i < max_uc; i++) {
  1652. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1653. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1654. (*map)[i][j].offset1 = dt_array[cnt];
  1655. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1656. }
  1657. (*map_uc)[i].pp = &(*map)[i][0];
  1658. }
  1659. kfree(dt_array);
  1660. return 0;
  1661. err_pdata_fail:
  1662. kfree(dt_array);
  1663. err_port_map:
  1664. return ret;
  1665. }
  1666. static int wsa884x_enable_supplies(struct device *dev,
  1667. struct wsa884x_priv *priv)
  1668. {
  1669. int ret = 0;
  1670. /* Parse power supplies */
  1671. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1672. &priv->num_supplies);
  1673. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1674. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1675. return -EINVAL;
  1676. }
  1677. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1678. priv->regulator, priv->num_supplies);
  1679. if (!priv->supplies) {
  1680. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1681. __func__);
  1682. return ret;
  1683. }
  1684. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1685. priv->regulator,
  1686. priv->num_supplies);
  1687. if (ret)
  1688. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1689. __func__);
  1690. return ret;
  1691. }
  1692. static struct snd_soc_dai_driver wsa_dai[] = {
  1693. {
  1694. .name = "",
  1695. .playback = {
  1696. .stream_name = "",
  1697. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1698. .formats = WSA884X_FORMATS,
  1699. .rate_max = 192000,
  1700. .rate_min = 8000,
  1701. .channels_min = 1,
  1702. .channels_max = 2,
  1703. },
  1704. },
  1705. };
  1706. static int wsa884x_swr_probe(struct swr_device *pdev)
  1707. {
  1708. int ret = 0;
  1709. struct wsa884x_priv *wsa884x;
  1710. u8 devnum = 0;
  1711. bool pin_state_current = false;
  1712. struct wsa_ctrl_platform_data *plat_data = NULL;
  1713. struct snd_soc_component *component;
  1714. u32 noise_gate_mode;
  1715. char buffer[MAX_NAME_LEN];
  1716. int dev_index = 0;
  1717. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1718. u8 wo0_val;
  1719. int sys_gain_size, sys_gain_length;
  1720. int wsa_dev_index;
  1721. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1722. GFP_KERNEL);
  1723. if (!wsa884x)
  1724. return -ENOMEM;
  1725. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1726. GFP_KERNEL);
  1727. if (!wsa884x_sub_regmap_irq_chip)
  1728. return -ENOMEM;
  1729. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1730. sizeof(struct regmap_irq_chip));
  1731. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1732. if (ret) {
  1733. ret = -EPROBE_DEFER;
  1734. goto err;
  1735. }
  1736. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1737. "qcom,spkr-sd-n-node", 0);
  1738. if (!wsa884x->wsa_rst_np) {
  1739. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1740. goto err_supply;
  1741. }
  1742. swr_set_dev_data(pdev, wsa884x);
  1743. wsa884x->swr_slave = pdev;
  1744. wsa884x->dev = &pdev->dev;
  1745. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1746. wsa884x_gpio_ctrl(wsa884x, true);
  1747. /*
  1748. * Add 5msec delay to provide sufficient time for
  1749. * soundwire auto enumeration of slave devices as
  1750. * per HW requirement.
  1751. */
  1752. usleep_range(5000, 5010);
  1753. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1754. if (ret) {
  1755. dev_dbg(&pdev->dev,
  1756. "%s get devnum %d for dev addr %lx failed\n",
  1757. __func__, devnum, pdev->addr);
  1758. ret = -EPROBE_DEFER;
  1759. goto err_supply;
  1760. }
  1761. pdev->dev_num = devnum;
  1762. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1763. &wsa884x_regmap_config);
  1764. if (IS_ERR(wsa884x->regmap)) {
  1765. ret = PTR_ERR(wsa884x->regmap);
  1766. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1767. __func__, ret);
  1768. goto dev_err;
  1769. }
  1770. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1771. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1772. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1773. wsa884x->irq_info.codec_name = "WSA884X";
  1774. wsa884x->irq_info.regmap = wsa884x->regmap;
  1775. wsa884x->irq_info.dev = &pdev->dev;
  1776. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1777. if (ret) {
  1778. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1779. __func__, ret);
  1780. goto dev_err;
  1781. }
  1782. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1783. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1784. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1785. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1786. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1787. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1788. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1789. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1790. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1791. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1792. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1793. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1794. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1795. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1796. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1797. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1798. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1799. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1800. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1801. /* Under Voltage Lock out (UVLO) interrupt handle */
  1802. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1803. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1804. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1805. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1806. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1807. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1808. if (!wsa884x->driver) {
  1809. ret = -ENOMEM;
  1810. goto err_irq;
  1811. }
  1812. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1813. sizeof(struct snd_soc_component_driver));
  1814. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1815. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1816. if (!wsa884x->dai_driver) {
  1817. ret = -ENOMEM;
  1818. goto err_mem;
  1819. }
  1820. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1821. /* Get last digit from HEX format */
  1822. dev_index = (int)((char)(pdev->addr & 0xF));
  1823. dev_index += 1;
  1824. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1825. dev_index += 2;
  1826. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1827. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1828. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1829. wsa884x->dai_driver->name =
  1830. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1831. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1832. wsa884x->dai_driver->playback.stream_name =
  1833. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1834. /* Number of DAI's used is 1 */
  1835. ret = snd_soc_register_component(&pdev->dev,
  1836. wsa884x->driver, wsa884x->dai_driver, 1);
  1837. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1838. if (!component) {
  1839. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1840. ret = -EINVAL;
  1841. goto err_mem;
  1842. }
  1843. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1844. "qcom,bolero-handle", 0);
  1845. if (!wsa884x->parent_np)
  1846. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1847. "qcom,lpass-cdc-handle", 0);
  1848. if (wsa884x->parent_np) {
  1849. wsa884x->parent_dev =
  1850. of_find_device_by_node(wsa884x->parent_np);
  1851. if (wsa884x->parent_dev) {
  1852. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1853. if (plat_data) {
  1854. wsa884x->parent_nblock.notifier_call =
  1855. wsa884x_event_notify;
  1856. if (plat_data->register_notifier)
  1857. plat_data->register_notifier(
  1858. plat_data->handle,
  1859. &wsa884x->parent_nblock,
  1860. true);
  1861. wsa884x->register_notifier =
  1862. plat_data->register_notifier;
  1863. wsa884x->handle = plat_data->handle;
  1864. } else {
  1865. dev_err(&pdev->dev, "%s: plat data not found\n",
  1866. __func__);
  1867. }
  1868. } else {
  1869. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1870. __func__);
  1871. }
  1872. } else {
  1873. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1874. }
  1875. /* Start in speaker mode by default */
  1876. wsa884x->dev_mode = SPEAKER;
  1877. wsa884x->dev_index = dev_index;
  1878. /* wsa_dev_index is macro_agnostic index */
  1879. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  1880. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1881. "qcom,wsa-macro-handle", 0);
  1882. if (wsa884x->macro_np) {
  1883. wsa884x->macro_dev =
  1884. of_find_device_by_node(wsa884x->macro_np);
  1885. if (wsa884x->macro_dev) {
  1886. ret = of_property_read_u32_index(
  1887. wsa884x->macro_dev->dev.of_node,
  1888. "qcom,wsa-rloads",
  1889. wsa_dev_index,
  1890. &wsa884x->rload);
  1891. if (ret) {
  1892. dev_err(&pdev->dev,
  1893. "%s: Failed to read wsa rloads\n",
  1894. __func__);
  1895. goto err_mem;
  1896. }
  1897. ret = of_property_read_u32_index(
  1898. wsa884x->macro_dev->dev.of_node,
  1899. "qcom,wsa-bat-cfgs",
  1900. wsa_dev_index,
  1901. &wsa884x->bat_cfg);
  1902. if (ret) {
  1903. dev_err(&pdev->dev,
  1904. "%s: Failed to read wsa bat cfgs\n",
  1905. __func__);
  1906. goto err_mem;
  1907. }
  1908. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1909. "qcom,noise-gate-mode", &noise_gate_mode);
  1910. if (ret) {
  1911. dev_info(&pdev->dev,
  1912. "%s: Failed to read wsa noise gate mode\n",
  1913. __func__);
  1914. wsa884x->noise_gate_mode = IDLE_DETECT;
  1915. } else {
  1916. if (IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1917. wsa884x->noise_gate_mode = noise_gate_mode;
  1918. else
  1919. wsa884x->noise_gate_mode = IDLE_DETECT;
  1920. }
  1921. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1922. "qcom,wsa-system-gains", &sys_gain_size)) {
  1923. dev_err(&pdev->dev,
  1924. "%s: missing wsa-system-gains\n",
  1925. __func__);
  1926. goto err_mem;
  1927. }
  1928. sys_gain_length = sys_gain_size / sizeof(u32);
  1929. ret = of_property_read_u32_array(
  1930. wsa884x->macro_dev->dev.of_node,
  1931. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1932. sys_gain_length);
  1933. if (ret) {
  1934. dev_err(&pdev->dev,
  1935. "%s: Failed to read wsa system gains\n",
  1936. __func__);
  1937. goto err_mem;
  1938. }
  1939. wsa884x->system_gain = wsa884x->sys_gains[
  1940. wsa884x->dev_mode + wsa_dev_index * 2];
  1941. } else {
  1942. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1943. __func__);
  1944. goto err_mem;
  1945. }
  1946. } else {
  1947. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1948. goto err_mem;
  1949. }
  1950. dev_dbg(component->dev,
  1951. "%s: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n", __func__,
  1952. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1953. ret = wsa884x_validate_dt_configuration_params(component, wsa884x->rload,
  1954. wsa884x->bat_cfg, wsa884x->system_gain);
  1955. if (ret) {
  1956. dev_err(&pdev->dev,
  1957. "%s: invalid dt parameter: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n",
  1958. __func__, wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1959. ret = -EINVAL;
  1960. goto err_mem;
  1961. }
  1962. /* Assume that compander is enabled by default unless it is haptics sku */
  1963. if (wsa884x->variant == WSA8845H)
  1964. wsa884x->comp_enable = false;
  1965. else
  1966. wsa884x->comp_enable = true;
  1967. wsa884x_set_gain_parameters(component);
  1968. wsa884x_set_pbr_parameters(component);
  1969. /* Must write WO registers in a single write */
  1970. wo0_val = (0xC0 | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1971. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1972. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1973. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1974. snd_soc_component_update_bits(component,
  1975. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1976. if (wsa884x->dev_mode == SPEAKER) {
  1977. snd_soc_component_update_bits(component,
  1978. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1979. } else {
  1980. snd_soc_component_update_bits(component,
  1981. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1982. snd_soc_component_update_bits(component,
  1983. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1984. snd_soc_component_update_bits(component,
  1985. REG_FIELD_VALUE(PWM_CLK_CTL,
  1986. PWM_CLK_FREQ_SEL, 0x01));
  1987. }
  1988. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1989. snd_soc_component_update_bits(component,
  1990. REG_FIELD_VALUE(TOP_CTRL1,
  1991. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  1992. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  1993. if (ret) {
  1994. dev_err(&pdev->dev, "Failed to read port params\n");
  1995. goto err;
  1996. }
  1997. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1998. wsa884x->swr_wsa_port_params);
  1999. mutex_init(&wsa884x->res_lock);
  2000. #ifdef CONFIG_DEBUG_FS
  2001. if (!wsa884x->debugfs_dent) {
  2002. wsa884x->debugfs_dent = debugfs_create_dir(
  2003. dev_name(&pdev->dev), 0);
  2004. if (!IS_ERR(wsa884x->debugfs_dent)) {
  2005. wsa884x->debugfs_peek =
  2006. debugfs_create_file("swrslave_peek",
  2007. S_IFREG | 0444,
  2008. wsa884x->debugfs_dent,
  2009. (void *) pdev,
  2010. &codec_debug_read_ops);
  2011. wsa884x->debugfs_poke =
  2012. debugfs_create_file("swrslave_poke",
  2013. S_IFREG | 0444,
  2014. wsa884x->debugfs_dent,
  2015. (void *) pdev,
  2016. &codec_debug_write_ops);
  2017. wsa884x->debugfs_reg_dump =
  2018. debugfs_create_file(
  2019. "swrslave_reg_dump",
  2020. S_IFREG | 0444,
  2021. wsa884x->debugfs_dent,
  2022. (void *) pdev,
  2023. &codec_debug_dump_ops);
  2024. }
  2025. }
  2026. #endif
  2027. return 0;
  2028. err_mem:
  2029. snd_soc_unregister_component(&pdev->dev);
  2030. if (wsa884x->dai_driver) {
  2031. kfree(wsa884x->dai_driver->name);
  2032. kfree(wsa884x->dai_driver->playback.stream_name);
  2033. devm_kfree(&pdev->dev, wsa884x->dai_driver);
  2034. wsa884x->dai_driver = NULL;
  2035. }
  2036. if (wsa884x->driver) {
  2037. kfree(wsa884x->driver->name);
  2038. devm_kfree(&pdev->dev, wsa884x->driver);
  2039. wsa884x->driver = NULL;
  2040. }
  2041. err_irq:
  2042. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  2043. dev_err:
  2044. if (pin_state_current == false)
  2045. wsa884x_gpio_ctrl(wsa884x, false);
  2046. swr_remove_device(pdev);
  2047. err_supply:
  2048. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2049. wsa884x->regulator,
  2050. wsa884x->num_supplies);
  2051. err:
  2052. swr_set_dev_data(pdev, NULL);
  2053. return ret;
  2054. }
  2055. static int wsa884x_swr_remove(struct swr_device *pdev)
  2056. {
  2057. struct wsa884x_priv *wsa884x;
  2058. wsa884x = swr_get_dev_data(pdev);
  2059. if (!wsa884x) {
  2060. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  2061. return -EINVAL;
  2062. }
  2063. if (wsa884x->register_notifier)
  2064. wsa884x->register_notifier(wsa884x->handle,
  2065. &wsa884x->parent_nblock, false);
  2066. #ifdef CONFIG_DEBUG_FS
  2067. debugfs_remove_recursive(wsa884x->debugfs_dent);
  2068. wsa884x->debugfs_dent = NULL;
  2069. #endif
  2070. mutex_destroy(&wsa884x->res_lock);
  2071. snd_soc_unregister_component(&pdev->dev);
  2072. if (wsa884x->dai_driver) {
  2073. kfree(wsa884x->dai_driver->name);
  2074. kfree(wsa884x->dai_driver->playback.stream_name);
  2075. kfree(wsa884x->dai_driver);
  2076. }
  2077. if (wsa884x->driver) {
  2078. kfree(wsa884x->driver->name);
  2079. kfree(wsa884x->driver);
  2080. }
  2081. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2082. wsa884x->regulator,
  2083. wsa884x->num_supplies);
  2084. swr_set_dev_data(pdev, NULL);
  2085. return 0;
  2086. }
  2087. #ifdef CONFIG_PM_SLEEP
  2088. static int wsa884x_swr_suspend(struct device *dev)
  2089. {
  2090. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2091. if (!wsa884x) {
  2092. dev_err_ratelimited(dev, "%s: wsa884x private data is NULL\n", __func__);
  2093. return -EINVAL;
  2094. }
  2095. dev_dbg(dev, "%s: system suspend\n", __func__);
  2096. if (wsa884x->dapm_bias_off ||
  2097. (wsa884x->component &&
  2098. (snd_soc_component_get_bias_level(wsa884x->component) ==
  2099. SND_SOC_BIAS_OFF))) {
  2100. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2101. wsa884x->regulator,
  2102. wsa884x->num_supplies,
  2103. true);
  2104. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2105. }
  2106. return 0;
  2107. }
  2108. static int wsa884x_swr_resume(struct device *dev)
  2109. {
  2110. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2111. if (!wsa884x) {
  2112. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2113. return -EINVAL;
  2114. }
  2115. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2116. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2117. wsa884x->regulator,
  2118. wsa884x->num_supplies,
  2119. false);
  2120. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2121. }
  2122. dev_dbg(dev, "%s: system resume\n", __func__);
  2123. return 0;
  2124. }
  2125. #endif /* CONFIG_PM_SLEEP */
  2126. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2127. .suspend_late = wsa884x_swr_suspend,
  2128. .resume_early = wsa884x_swr_resume,
  2129. };
  2130. static const struct swr_device_id wsa884x_swr_id[] = {
  2131. {"wsa884x", 0},
  2132. {"wsa884x_2", 0},
  2133. {}
  2134. };
  2135. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2136. {
  2137. .compatible = "qcom,wsa884x",
  2138. },
  2139. {
  2140. .compatible = "qcom,wsa884x_2",
  2141. },
  2142. {}
  2143. };
  2144. static struct swr_driver wsa884x_swr_driver = {
  2145. .driver = {
  2146. .name = "wsa884x",
  2147. .owner = THIS_MODULE,
  2148. .pm = &wsa884x_swr_pm_ops,
  2149. .of_match_table = wsa884x_swr_dt_match,
  2150. },
  2151. .probe = wsa884x_swr_probe,
  2152. .remove = wsa884x_swr_remove,
  2153. .id_table = wsa884x_swr_id,
  2154. };
  2155. static int __init wsa884x_swr_init(void)
  2156. {
  2157. return swr_driver_register(&wsa884x_swr_driver);
  2158. }
  2159. static void __exit wsa884x_swr_exit(void)
  2160. {
  2161. swr_driver_unregister(&wsa884x_swr_driver);
  2162. }
  2163. module_init(wsa884x_swr_init);
  2164. module_exit(wsa884x_swr_exit);
  2165. MODULE_DESCRIPTION("WSA884x codec driver");
  2166. MODULE_LICENSE("GPL v2");