wcd934x-dsd.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/module.h>
  5. #include <linux/delay.h>
  6. #include <sound/tlv.h>
  7. #include <sound/control.h>
  8. #include <asoc/wcd934x_registers.h>
  9. #include "wcd934x-dsd.h"
  10. #define DSD_VOLUME_MAX_0dB 0
  11. #define DSD_VOLUME_MIN_M110dB -110
  12. #define DSD_VOLUME_RANGE_CHECK(x) ((x >= DSD_VOLUME_MIN_M110dB) &&\
  13. (x <= DSD_VOLUME_MAX_0dB))
  14. #define DSD_VOLUME_STEPS 3
  15. #define DSD_VOLUME_UPDATE_DELAY_MS 30
  16. #define DSD_VOLUME_USLEEP_MARGIN_US 100
  17. #define DSD_VOLUME_STEP_DELAY_US ((1000 * DSD_VOLUME_UPDATE_DELAY_MS) / \
  18. (2 * DSD_VOLUME_STEPS))
  19. #define TAVIL_VERSION_1_0 0
  20. #define TAVIL_VERSION_1_1 1
  21. static const DECLARE_TLV_DB_MINMAX(tavil_dsd_db_scale, DSD_VOLUME_MIN_M110dB,
  22. DSD_VOLUME_MAX_0dB);
  23. static const char *const dsd_if_text[] = {
  24. "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7",
  25. "DSD_DATA_PAD"
  26. };
  27. static const char * const dsd_filt0_mux_text[] = {
  28. "ZERO", "DSD_L IF MUX",
  29. };
  30. static const char * const dsd_filt1_mux_text[] = {
  31. "ZERO", "DSD_R IF MUX",
  32. };
  33. static const struct soc_enum dsd_filt0_mux_enum =
  34. SOC_ENUM_SINGLE(WCD934X_CDC_DSD0_PATH_CTL, 0,
  35. ARRAY_SIZE(dsd_filt0_mux_text), dsd_filt0_mux_text);
  36. static const struct soc_enum dsd_filt1_mux_enum =
  37. SOC_ENUM_SINGLE(WCD934X_CDC_DSD1_PATH_CTL, 0,
  38. ARRAY_SIZE(dsd_filt1_mux_text), dsd_filt1_mux_text);
  39. static SOC_ENUM_SINGLE_DECL(dsd_l_if_enum, WCD934X_CDC_DSD0_CFG0,
  40. 2, dsd_if_text);
  41. static SOC_ENUM_SINGLE_DECL(dsd_r_if_enum, WCD934X_CDC_DSD1_CFG0,
  42. 2, dsd_if_text);
  43. static const struct snd_kcontrol_new dsd_filt0_mux =
  44. SOC_DAPM_ENUM("DSD Filt0 Mux", dsd_filt0_mux_enum);
  45. static const struct snd_kcontrol_new dsd_filt1_mux =
  46. SOC_DAPM_ENUM("DSD Filt1 Mux", dsd_filt1_mux_enum);
  47. static const struct snd_kcontrol_new dsd_l_if_mux =
  48. SOC_DAPM_ENUM("DSD Left If Mux", dsd_l_if_enum);
  49. static const struct snd_kcontrol_new dsd_r_if_mux =
  50. SOC_DAPM_ENUM("DSD Right If Mux", dsd_r_if_enum);
  51. static const struct snd_soc_dapm_route tavil_dsd_audio_map[] = {
  52. {"DSD_L IF MUX", "RX0", "CDC_IF RX0 MUX"},
  53. {"DSD_L IF MUX", "RX1", "CDC_IF RX1 MUX"},
  54. {"DSD_L IF MUX", "RX2", "CDC_IF RX2 MUX"},
  55. {"DSD_L IF MUX", "RX3", "CDC_IF RX3 MUX"},
  56. {"DSD_L IF MUX", "RX4", "CDC_IF RX4 MUX"},
  57. {"DSD_L IF MUX", "RX5", "CDC_IF RX5 MUX"},
  58. {"DSD_L IF MUX", "RX6", "CDC_IF RX6 MUX"},
  59. {"DSD_L IF MUX", "RX7", "CDC_IF RX7 MUX"},
  60. {"DSD_FILTER_0", NULL, "DSD_L IF MUX"},
  61. {"DSD_FILTER_0", NULL, "RX INT1 NATIVE SUPPLY"},
  62. {"RX INT1 MIX3", "DSD HPHL Switch", "DSD_FILTER_0"},
  63. {"DSD_R IF MUX", "RX0", "CDC_IF RX0 MUX"},
  64. {"DSD_R IF MUX", "RX1", "CDC_IF RX1 MUX"},
  65. {"DSD_R IF MUX", "RX2", "CDC_IF RX2 MUX"},
  66. {"DSD_R IF MUX", "RX3", "CDC_IF RX3 MUX"},
  67. {"DSD_R IF MUX", "RX4", "CDC_IF RX4 MUX"},
  68. {"DSD_R IF MUX", "RX5", "CDC_IF RX5 MUX"},
  69. {"DSD_R IF MUX", "RX6", "CDC_IF RX6 MUX"},
  70. {"DSD_R IF MUX", "RX7", "CDC_IF RX7 MUX"},
  71. {"DSD_FILTER_1", NULL, "DSD_R IF MUX"},
  72. {"DSD_FILTER_1", NULL, "RX INT2 NATIVE SUPPLY"},
  73. {"RX INT2 MIX3", "DSD HPHR Switch", "DSD_FILTER_1"},
  74. {"DSD_FILTER_0", NULL, "RX INT3 NATIVE SUPPLY"},
  75. {"RX INT3 MIX3", "DSD LO1 Switch", "DSD_FILTER_0"},
  76. {"DSD_FILTER_1", NULL, "RX INT4 NATIVE SUPPLY"},
  77. {"RX INT4 MIX3", "DSD LO2 Switch", "DSD_FILTER_1"},
  78. };
  79. static bool is_valid_dsd_interpolator(int interp_num)
  80. {
  81. if ((interp_num == INTERP_HPHL) || (interp_num == INTERP_HPHR) ||
  82. (interp_num == INTERP_LO1) || (interp_num == INTERP_LO2))
  83. return true;
  84. return false;
  85. }
  86. /**
  87. * tavil_dsd_set_mixer_value - Set DSD HPH/LO mixer value
  88. *
  89. * @dsd_conf: pointer to dsd config
  90. * @interp_num: Interpolator number (HPHL/R, LO1/2)
  91. * @sw_value: Mixer switch value
  92. *
  93. * Returns 0 on success or -EINVAL on failure
  94. */
  95. int tavil_dsd_set_mixer_value(struct tavil_dsd_config *dsd_conf,
  96. int interp_num, int sw_value)
  97. {
  98. if (!dsd_conf)
  99. return -EINVAL;
  100. if (!is_valid_dsd_interpolator(interp_num))
  101. return -EINVAL;
  102. dsd_conf->dsd_interp_mixer[interp_num] = !!sw_value;
  103. return 0;
  104. }
  105. EXPORT_SYMBOL(tavil_dsd_set_mixer_value);
  106. /**
  107. * tavil_dsd_get_current_mixer_value - Get DSD HPH/LO mixer value
  108. *
  109. * @dsd_conf: pointer to dsd config
  110. * @interp_num: Interpolator number (HPHL/R, LO1/2)
  111. *
  112. * Returns current mixer val for success or -EINVAL for failure
  113. */
  114. int tavil_dsd_get_current_mixer_value(struct tavil_dsd_config *dsd_conf,
  115. int interp_num)
  116. {
  117. if (!dsd_conf)
  118. return -EINVAL;
  119. if (!is_valid_dsd_interpolator(interp_num))
  120. return -EINVAL;
  121. return dsd_conf->dsd_interp_mixer[interp_num];
  122. }
  123. EXPORT_SYMBOL(tavil_dsd_get_current_mixer_value);
  124. /**
  125. * tavil_dsd_set_out_select - DSD0/1 out select to HPH or LO
  126. *
  127. * @dsd_conf: pointer to dsd config
  128. * @interp_num: Interpolator number (HPHL/R, LO1/2)
  129. *
  130. * Returns 0 for success or -EINVAL for failure
  131. */
  132. int tavil_dsd_set_out_select(struct tavil_dsd_config *dsd_conf,
  133. int interp_num)
  134. {
  135. unsigned int reg, val;
  136. struct snd_soc_component *component;
  137. if (!dsd_conf || !dsd_conf->component)
  138. return -EINVAL;
  139. component = dsd_conf->component;
  140. if (!is_valid_dsd_interpolator(interp_num)) {
  141. dev_err(component->dev, "%s: Invalid Interpolator: %d for DSD\n",
  142. __func__, interp_num);
  143. return -EINVAL;
  144. }
  145. switch (interp_num) {
  146. case INTERP_HPHL:
  147. reg = WCD934X_CDC_DSD0_CFG0;
  148. val = 0x00;
  149. break;
  150. case INTERP_HPHR:
  151. reg = WCD934X_CDC_DSD1_CFG0;
  152. val = 0x00;
  153. break;
  154. case INTERP_LO1:
  155. reg = WCD934X_CDC_DSD0_CFG0;
  156. val = 0x02;
  157. break;
  158. case INTERP_LO2:
  159. reg = WCD934X_CDC_DSD1_CFG0;
  160. val = 0x02;
  161. break;
  162. default:
  163. return -EINVAL;
  164. }
  165. snd_soc_component_update_bits(component, reg, 0x02, val);
  166. return 0;
  167. }
  168. EXPORT_SYMBOL(tavil_dsd_set_out_select);
  169. /**
  170. * tavil_dsd_reset - Reset DSD block
  171. *
  172. * @dsd_conf: pointer to dsd config
  173. *
  174. */
  175. void tavil_dsd_reset(struct tavil_dsd_config *dsd_conf)
  176. {
  177. if (!dsd_conf || !dsd_conf->component)
  178. return;
  179. snd_soc_component_update_bits(dsd_conf->component,
  180. WCD934X_CDC_DSD0_PATH_CTL,
  181. 0x02, 0x02);
  182. snd_soc_component_update_bits(dsd_conf->component,
  183. WCD934X_CDC_DSD0_PATH_CTL,
  184. 0x01, 0x00);
  185. snd_soc_component_update_bits(dsd_conf->component,
  186. WCD934X_CDC_DSD1_PATH_CTL,
  187. 0x02, 0x02);
  188. snd_soc_component_update_bits(dsd_conf->component,
  189. WCD934X_CDC_DSD1_PATH_CTL,
  190. 0x01, 0x00);
  191. }
  192. EXPORT_SYMBOL(tavil_dsd_reset);
  193. /**
  194. * tavil_dsd_set_interp_rate - Set interpolator rate for DSD
  195. *
  196. * @dsd_conf: pointer to dsd config
  197. * @rx_port: RX port number
  198. * @sample_rate: Sample rate of the RX interpolator
  199. * @sample_rate_val: Interpolator rate value
  200. */
  201. void tavil_dsd_set_interp_rate(struct tavil_dsd_config *dsd_conf, u16 rx_port,
  202. u32 sample_rate, u8 sample_rate_val)
  203. {
  204. u8 dsd_inp_sel;
  205. u8 dsd0_inp, dsd1_inp;
  206. u8 val0, val1;
  207. u8 dsd0_out_sel, dsd1_out_sel;
  208. u16 int_fs_reg, interp_num = 0;
  209. struct snd_soc_component *component;
  210. if (!dsd_conf || !dsd_conf->component)
  211. return;
  212. component = dsd_conf->component;
  213. dsd_inp_sel = DSD_INP_SEL_RX0 + rx_port - WCD934X_RX_PORT_START_NUMBER;
  214. val0 = snd_soc_component_read32(component, WCD934X_CDC_DSD0_CFG0);
  215. val1 = snd_soc_component_read32(component, WCD934X_CDC_DSD1_CFG0);
  216. dsd0_inp = (val0 & 0x3C) >> 2;
  217. dsd1_inp = (val1 & 0x3C) >> 2;
  218. dsd0_out_sel = (val0 & 0x02) >> 1;
  219. dsd1_out_sel = (val1 & 0x02) >> 1;
  220. /* Set HPHL or LO1 interp rate based on out select */
  221. if (dsd_inp_sel == dsd0_inp) {
  222. interp_num = dsd0_out_sel ? INTERP_LO1 : INTERP_HPHL;
  223. dsd_conf->base_sample_rate[DSD0] = sample_rate;
  224. }
  225. /* Set HPHR or LO2 interp rate based on out select */
  226. if (dsd_inp_sel == dsd1_inp) {
  227. interp_num = dsd1_out_sel ? INTERP_LO2 : INTERP_HPHR;
  228. dsd_conf->base_sample_rate[DSD1] = sample_rate;
  229. }
  230. if (interp_num) {
  231. int_fs_reg = WCD934X_CDC_RX0_RX_PATH_CTL + 20 * interp_num;
  232. if ((snd_soc_component_read32(component, int_fs_reg) & 0x0f) <
  233. 0x09) {
  234. dev_dbg(component->dev, "%s: Set Interp %d to sample_rate val 0x%x\n",
  235. __func__, interp_num, sample_rate_val);
  236. snd_soc_component_update_bits(component, int_fs_reg,
  237. 0x0F, sample_rate_val);
  238. }
  239. }
  240. }
  241. EXPORT_SYMBOL(tavil_dsd_set_interp_rate);
  242. static int tavil_set_dsd_mode(struct snd_soc_component *component, int dsd_num,
  243. u8 *pcm_rate_val)
  244. {
  245. unsigned int dsd_out_sel_reg;
  246. u8 dsd_mode;
  247. u32 sample_rate;
  248. struct tavil_dsd_config *dsd_conf = tavil_get_dsd_config(component);
  249. if (!dsd_conf)
  250. return -EINVAL;
  251. if ((dsd_num < 0) || (dsd_num > 1))
  252. return -EINVAL;
  253. sample_rate = dsd_conf->base_sample_rate[dsd_num];
  254. dsd_out_sel_reg = WCD934X_CDC_DSD0_CFG0 + dsd_num * 16;
  255. switch (sample_rate) {
  256. case 176400:
  257. dsd_mode = 0; /* DSD_64 */
  258. *pcm_rate_val = 0xb;
  259. break;
  260. case 352800:
  261. dsd_mode = 1; /* DSD_128 */
  262. *pcm_rate_val = 0xc;
  263. break;
  264. default:
  265. dev_err(component->dev, "%s: Invalid DSD rate: %d\n",
  266. __func__, sample_rate);
  267. return -EINVAL;
  268. }
  269. snd_soc_component_update_bits(component, dsd_out_sel_reg,
  270. 0x01, dsd_mode);
  271. return 0;
  272. }
  273. static void tavil_dsd_data_pull(struct snd_soc_component *component,
  274. int dsd_num,
  275. u8 pcm_rate_val, bool enable)
  276. {
  277. u8 clk_en, mute_en;
  278. u8 dsd_inp_sel;
  279. if (enable) {
  280. clk_en = 0x20;
  281. mute_en = 0x10;
  282. } else {
  283. clk_en = 0x00;
  284. mute_en = 0x00;
  285. }
  286. if (dsd_num & 0x01) {
  287. snd_soc_component_update_bits(component,
  288. WCD934X_CDC_RX7_RX_PATH_MIX_CTL,
  289. 0x20, clk_en);
  290. dsd_inp_sel = (snd_soc_component_read32(
  291. component, WCD934X_CDC_DSD0_CFG0) &
  292. 0x3C) >> 2;
  293. dsd_inp_sel = (enable) ? dsd_inp_sel : 0;
  294. if (dsd_inp_sel < 9) {
  295. snd_soc_component_update_bits(component,
  296. WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1,
  297. 0x0F, dsd_inp_sel);
  298. snd_soc_component_update_bits(component,
  299. WCD934X_CDC_RX7_RX_PATH_MIX_CTL,
  300. 0x0F, pcm_rate_val);
  301. snd_soc_component_update_bits(component,
  302. WCD934X_CDC_RX7_RX_PATH_MIX_CTL,
  303. 0x10, mute_en);
  304. }
  305. }
  306. if (dsd_num & 0x02) {
  307. snd_soc_component_update_bits(component,
  308. WCD934X_CDC_RX8_RX_PATH_MIX_CTL,
  309. 0x20, clk_en);
  310. dsd_inp_sel = (snd_soc_component_read32(
  311. component, WCD934X_CDC_DSD1_CFG0) &
  312. 0x3C) >> 2;
  313. dsd_inp_sel = (enable) ? dsd_inp_sel : 0;
  314. if (dsd_inp_sel < 9) {
  315. snd_soc_component_update_bits(component,
  316. WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1,
  317. 0x0F, dsd_inp_sel);
  318. snd_soc_component_update_bits(component,
  319. WCD934X_CDC_RX8_RX_PATH_MIX_CTL,
  320. 0x0F, pcm_rate_val);
  321. snd_soc_component_update_bits(component,
  322. WCD934X_CDC_RX8_RX_PATH_MIX_CTL,
  323. 0x10, mute_en);
  324. }
  325. }
  326. }
  327. static void tavil_dsd_update_volume(struct tavil_dsd_config *dsd_conf)
  328. {
  329. snd_soc_component_update_bits(dsd_conf->component,
  330. WCD934X_CDC_TOP_TOP_CFG0,
  331. 0x01, 0x01);
  332. snd_soc_component_update_bits(dsd_conf->component,
  333. WCD934X_CDC_TOP_TOP_CFG0,
  334. 0x01, 0x00);
  335. }
  336. static int tavil_enable_dsd(struct snd_soc_dapm_widget *w,
  337. struct snd_kcontrol *kcontrol, int event)
  338. {
  339. struct snd_soc_component *component =
  340. snd_soc_dapm_to_component(w->dapm);
  341. struct tavil_dsd_config *dsd_conf = tavil_get_dsd_config(component);
  342. int rc, clk_users;
  343. int interp_idx;
  344. u8 pcm_rate_val;
  345. if (!dsd_conf) {
  346. dev_err(component->dev, "%s: null dsd_config pointer\n",
  347. __func__);
  348. return -EINVAL;
  349. }
  350. dev_dbg(component->dev, "%s: DSD%d, event: %d\n", __func__,
  351. w->shift, event);
  352. if (w->shift == DSD0) {
  353. /* Read out select */
  354. if (snd_soc_component_read32(
  355. component, WCD934X_CDC_DSD0_CFG0) & 0x02)
  356. interp_idx = INTERP_LO1;
  357. else
  358. interp_idx = INTERP_HPHL;
  359. } else if (w->shift == DSD1) {
  360. /* Read out select */
  361. if (snd_soc_component_read32(
  362. component, WCD934X_CDC_DSD1_CFG0) & 0x02)
  363. interp_idx = INTERP_LO2;
  364. else
  365. interp_idx = INTERP_HPHR;
  366. } else {
  367. dev_err(component->dev, "%s: Unsupported DSD:%d\n",
  368. __func__, w->shift);
  369. return -EINVAL;
  370. }
  371. switch (event) {
  372. case SND_SOC_DAPM_PRE_PMU:
  373. clk_users = tavil_codec_enable_interp_clk(component, event,
  374. interp_idx);
  375. rc = tavil_set_dsd_mode(component, w->shift, &pcm_rate_val);
  376. if (rc)
  377. return rc;
  378. tavil_dsd_data_pull(component, (1 << w->shift), pcm_rate_val,
  379. true);
  380. snd_soc_component_update_bits(component,
  381. WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL, 0x01,
  382. 0x01);
  383. if (w->shift == DSD0) {
  384. snd_soc_component_update_bits(component,
  385. WCD934X_CDC_DSD0_PATH_CTL,
  386. 0x02, 0x02);
  387. snd_soc_component_update_bits(component,
  388. WCD934X_CDC_DSD0_PATH_CTL,
  389. 0x02, 0x00);
  390. snd_soc_component_update_bits(component,
  391. WCD934X_CDC_DSD0_PATH_CTL,
  392. 0x01, 0x01);
  393. /* Apply Gain */
  394. snd_soc_component_write(component,
  395. WCD934X_CDC_DSD0_CFG1,
  396. dsd_conf->volume[DSD0]);
  397. if (dsd_conf->version == TAVIL_VERSION_1_1)
  398. tavil_dsd_update_volume(dsd_conf);
  399. } else if (w->shift == DSD1) {
  400. snd_soc_component_update_bits(component,
  401. WCD934X_CDC_DSD1_PATH_CTL,
  402. 0x02, 0x02);
  403. snd_soc_component_update_bits(component,
  404. WCD934X_CDC_DSD1_PATH_CTL,
  405. 0x02, 0x00);
  406. snd_soc_component_update_bits(component,
  407. WCD934X_CDC_DSD1_PATH_CTL,
  408. 0x01, 0x01);
  409. /* Apply Gain */
  410. snd_soc_component_write(component,
  411. WCD934X_CDC_DSD1_CFG1,
  412. dsd_conf->volume[DSD1]);
  413. if (dsd_conf->version == TAVIL_VERSION_1_1)
  414. tavil_dsd_update_volume(dsd_conf);
  415. }
  416. /* 10msec sleep required after DSD clock is set */
  417. usleep_range(10000, 10100);
  418. if (clk_users > 1) {
  419. snd_soc_component_update_bits(component,
  420. WCD934X_ANA_RX_SUPPLIES,
  421. 0x02, 0x02);
  422. if (w->shift == DSD0)
  423. snd_soc_component_update_bits(component,
  424. WCD934X_CDC_DSD0_CFG2,
  425. 0x04, 0x00);
  426. if (w->shift == DSD1)
  427. snd_soc_component_update_bits(component,
  428. WCD934X_CDC_DSD1_CFG2,
  429. 0x04, 0x00);
  430. }
  431. break;
  432. case SND_SOC_DAPM_POST_PMD:
  433. if (w->shift == DSD0) {
  434. snd_soc_component_update_bits(component,
  435. WCD934X_CDC_DSD0_CFG2,
  436. 0x04, 0x04);
  437. snd_soc_component_update_bits(component,
  438. WCD934X_CDC_DSD0_PATH_CTL,
  439. 0x01, 0x00);
  440. } else if (w->shift == DSD1) {
  441. snd_soc_component_update_bits(component,
  442. WCD934X_CDC_DSD1_CFG2,
  443. 0x04, 0x04);
  444. snd_soc_component_update_bits(component,
  445. WCD934X_CDC_DSD1_PATH_CTL,
  446. 0x01, 0x00);
  447. }
  448. tavil_codec_enable_interp_clk(component, event, interp_idx);
  449. if (!(snd_soc_component_read32(
  450. component, WCD934X_CDC_DSD0_PATH_CTL) & 0x01) &&
  451. !(snd_soc_component_read32(
  452. component, WCD934X_CDC_DSD1_PATH_CTL) & 0x01)) {
  453. snd_soc_component_update_bits(component,
  454. WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL,
  455. 0x01, 0x00);
  456. tavil_dsd_data_pull(component, 0x03, 0x04, false);
  457. tavil_dsd_reset(dsd_conf);
  458. }
  459. break;
  460. }
  461. return 0;
  462. }
  463. static int tavil_dsd_vol_info(struct snd_kcontrol *kcontrol,
  464. struct snd_ctl_elem_info *uinfo)
  465. {
  466. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  467. uinfo->count = 2;
  468. uinfo->value.integer.min = DSD_VOLUME_MIN_M110dB;
  469. uinfo->value.integer.max = DSD_VOLUME_MAX_0dB;
  470. return 0;
  471. }
  472. static int tavil_dsd_vol_put(struct snd_kcontrol *kcontrol,
  473. struct snd_ctl_elem_value *ucontrol)
  474. {
  475. struct snd_soc_component *component =
  476. snd_soc_kcontrol_component(kcontrol);
  477. struct tavil_dsd_config *dsd_conf = tavil_get_dsd_config(component);
  478. int nv[DSD_MAX], cv[DSD_MAX];
  479. int step_size, nv1;
  480. int i, dsd_idx;
  481. if (!dsd_conf)
  482. return 0;
  483. mutex_lock(&dsd_conf->vol_mutex);
  484. for (dsd_idx = DSD0; dsd_idx < DSD_MAX; dsd_idx++) {
  485. cv[dsd_idx] = dsd_conf->volume[dsd_idx];
  486. nv[dsd_idx] = ucontrol->value.integer.value[dsd_idx];
  487. }
  488. if ((!DSD_VOLUME_RANGE_CHECK(nv[DSD0])) ||
  489. (!DSD_VOLUME_RANGE_CHECK(nv[DSD1])))
  490. goto done;
  491. for (dsd_idx = DSD0; dsd_idx < DSD_MAX; dsd_idx++) {
  492. if (cv[dsd_idx] == nv[dsd_idx])
  493. continue;
  494. dev_dbg(component->dev, "%s: DSD%d cur.vol: %d, new vol: %d\n",
  495. __func__, dsd_idx, cv[dsd_idx], nv[dsd_idx]);
  496. step_size = (nv[dsd_idx] - cv[dsd_idx]) /
  497. DSD_VOLUME_STEPS;
  498. nv1 = cv[dsd_idx];
  499. for (i = 0; i < DSD_VOLUME_STEPS; i++) {
  500. nv1 += step_size;
  501. snd_soc_component_write(component,
  502. WCD934X_CDC_DSD0_CFG1 + 16 * dsd_idx,
  503. nv1);
  504. if (dsd_conf->version == TAVIL_VERSION_1_1)
  505. tavil_dsd_update_volume(dsd_conf);
  506. /* sleep required after each volume step */
  507. usleep_range(DSD_VOLUME_STEP_DELAY_US,
  508. (DSD_VOLUME_STEP_DELAY_US +
  509. DSD_VOLUME_USLEEP_MARGIN_US));
  510. }
  511. if (nv1 != nv[dsd_idx]) {
  512. snd_soc_component_write(component,
  513. WCD934X_CDC_DSD0_CFG1 + 16 * dsd_idx,
  514. nv[dsd_idx]);
  515. if (dsd_conf->version == TAVIL_VERSION_1_1)
  516. tavil_dsd_update_volume(dsd_conf);
  517. }
  518. dsd_conf->volume[dsd_idx] = nv[dsd_idx];
  519. }
  520. done:
  521. mutex_unlock(&dsd_conf->vol_mutex);
  522. return 0;
  523. }
  524. static int tavil_dsd_vol_get(struct snd_kcontrol *kcontrol,
  525. struct snd_ctl_elem_value *ucontrol)
  526. {
  527. struct snd_soc_component *component =
  528. snd_soc_kcontrol_component(kcontrol);
  529. struct tavil_dsd_config *dsd_conf = tavil_get_dsd_config(component);
  530. if (dsd_conf) {
  531. ucontrol->value.integer.value[0] = dsd_conf->volume[DSD0];
  532. ucontrol->value.integer.value[1] = dsd_conf->volume[DSD1];
  533. }
  534. return 0;
  535. }
  536. static const struct snd_kcontrol_new tavil_dsd_vol_controls[] = {
  537. {
  538. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  539. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  540. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  541. .name = "DSD Volume",
  542. .info = tavil_dsd_vol_info,
  543. .get = tavil_dsd_vol_get,
  544. .put = tavil_dsd_vol_put,
  545. .tlv = { .p = tavil_dsd_db_scale },
  546. },
  547. };
  548. static const struct snd_soc_dapm_widget tavil_dsd_widgets[] = {
  549. SND_SOC_DAPM_MUX("DSD_L IF MUX", SND_SOC_NOPM, 0, 0, &dsd_l_if_mux),
  550. SND_SOC_DAPM_MUX_E("DSD_FILTER_0", SND_SOC_NOPM, 0, 0, &dsd_filt0_mux,
  551. tavil_enable_dsd,
  552. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  553. SND_SOC_DAPM_MUX("DSD_R IF MUX", SND_SOC_NOPM, 0, 0, &dsd_r_if_mux),
  554. SND_SOC_DAPM_MUX_E("DSD_FILTER_1", SND_SOC_NOPM, 1, 0, &dsd_filt1_mux,
  555. tavil_enable_dsd,
  556. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  557. };
  558. /**
  559. * tavil_dsd_post_ssr_init - DSD intialization after subsystem restart
  560. *
  561. * @component: pointer to snd_soc_component
  562. *
  563. * Returns 0 on success or error on failure
  564. */
  565. int tavil_dsd_post_ssr_init(struct tavil_dsd_config *dsd_conf)
  566. {
  567. struct snd_soc_component *component;
  568. if (!dsd_conf || !dsd_conf->component)
  569. return -EINVAL;
  570. component = dsd_conf->component;
  571. /* Disable DSD Interrupts */
  572. snd_soc_component_update_bits(component,
  573. WCD934X_INTR_CODEC_MISC_MASK,
  574. 0x08, 0x08);
  575. /* DSD registers init */
  576. if (dsd_conf->version == TAVIL_VERSION_1_0) {
  577. snd_soc_component_update_bits(component,
  578. WCD934X_CDC_DSD0_CFG2,
  579. 0x02, 0x00);
  580. snd_soc_component_update_bits(component,
  581. WCD934X_CDC_DSD1_CFG2,
  582. 0x02, 0x00);
  583. }
  584. /* DSD0: Mute EN */
  585. snd_soc_component_update_bits(component,
  586. WCD934X_CDC_DSD0_CFG2,
  587. 0x04, 0x04);
  588. /* DSD1: Mute EN */
  589. snd_soc_component_update_bits(component,
  590. WCD934X_CDC_DSD1_CFG2,
  591. 0x04, 0x04);
  592. snd_soc_component_update_bits(component,
  593. WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG3,
  594. 0x10, 0x10);
  595. snd_soc_component_update_bits(component,
  596. WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG3,
  597. 0x10, 0x10);
  598. snd_soc_component_update_bits(component,
  599. WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG0,
  600. 0x0E, 0x0A);
  601. snd_soc_component_update_bits(component,
  602. WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG0,
  603. 0x0E, 0x0A);
  604. snd_soc_component_update_bits(component,
  605. WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG1,
  606. 0x07, 0x04);
  607. snd_soc_component_update_bits(component,
  608. WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG1,
  609. 0x07, 0x04);
  610. /* Enable DSD Interrupts */
  611. snd_soc_component_update_bits(component,
  612. WCD934X_INTR_CODEC_MISC_MASK,
  613. 0x08, 0x00);
  614. return 0;
  615. }
  616. EXPORT_SYMBOL(tavil_dsd_post_ssr_init);
  617. /**
  618. * tavil_dsd_init - DSD intialization
  619. *
  620. * @component: pointer to snd_soc_component
  621. *
  622. * Returns pointer to tavil_dsd_config for success or NULL for failure
  623. */
  624. struct tavil_dsd_config *tavil_dsd_init(struct snd_soc_component *component)
  625. {
  626. struct snd_soc_dapm_context *dapm;
  627. struct tavil_dsd_config *dsd_conf;
  628. u8 val;
  629. if (!component)
  630. return NULL;
  631. dapm = snd_soc_component_get_dapm(component);
  632. /* Read efuse register to check if DSD is supported */
  633. val = snd_soc_component_read32(component,
  634. WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14);
  635. if (val & 0x80) {
  636. dev_info(component->dev, "%s: DSD unsupported for this codec version\n",
  637. __func__);
  638. return NULL;
  639. }
  640. dsd_conf = devm_kzalloc(component->dev, sizeof(struct tavil_dsd_config),
  641. GFP_KERNEL);
  642. if (!dsd_conf)
  643. return NULL;
  644. dsd_conf->component = component;
  645. /* Read version */
  646. dsd_conf->version = snd_soc_component_read32(component,
  647. WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0);
  648. /* DSD registers init */
  649. if (dsd_conf->version == TAVIL_VERSION_1_0) {
  650. snd_soc_component_update_bits(component, WCD934X_CDC_DSD0_CFG2,
  651. 0x02, 0x00);
  652. snd_soc_component_update_bits(component, WCD934X_CDC_DSD1_CFG2,
  653. 0x02, 0x00);
  654. }
  655. /* DSD0: Mute EN */
  656. snd_soc_component_update_bits(component, WCD934X_CDC_DSD0_CFG2,
  657. 0x04, 0x04);
  658. /* DSD1: Mute EN */
  659. snd_soc_component_update_bits(component, WCD934X_CDC_DSD1_CFG2,
  660. 0x04, 0x04);
  661. snd_soc_component_update_bits(component,
  662. WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG3,
  663. 0x10, 0x10);
  664. snd_soc_component_update_bits(component,
  665. WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG3,
  666. 0x10, 0x10);
  667. snd_soc_component_update_bits(component,
  668. WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG0,
  669. 0x0E, 0x0A);
  670. snd_soc_component_update_bits(component,
  671. WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG0,
  672. 0x0E, 0x0A);
  673. snd_soc_component_update_bits(component,
  674. WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG1,
  675. 0x07, 0x04);
  676. snd_soc_component_update_bits(component,
  677. WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG1,
  678. 0x07, 0x04);
  679. snd_soc_dapm_new_controls(dapm, tavil_dsd_widgets,
  680. ARRAY_SIZE(tavil_dsd_widgets));
  681. snd_soc_dapm_add_routes(dapm, tavil_dsd_audio_map,
  682. ARRAY_SIZE(tavil_dsd_audio_map));
  683. mutex_init(&dsd_conf->vol_mutex);
  684. dsd_conf->volume[DSD0] = DSD_VOLUME_MAX_0dB;
  685. dsd_conf->volume[DSD1] = DSD_VOLUME_MAX_0dB;
  686. snd_soc_add_component_controls(component, tavil_dsd_vol_controls,
  687. ARRAY_SIZE(tavil_dsd_vol_controls));
  688. /* Enable DSD Interrupts */
  689. snd_soc_component_update_bits(component,
  690. WCD934X_INTR_CODEC_MISC_MASK, 0x08, 0x00);
  691. return dsd_conf;
  692. }
  693. EXPORT_SYMBOL(tavil_dsd_init);
  694. /**
  695. * tavil_dsd_deinit - DSD de-intialization
  696. *
  697. * @dsd_conf: pointer to tavil_dsd_config
  698. */
  699. void tavil_dsd_deinit(struct tavil_dsd_config *dsd_conf)
  700. {
  701. struct snd_soc_component *component;
  702. if (!dsd_conf)
  703. return;
  704. component = dsd_conf->component;
  705. mutex_destroy(&dsd_conf->vol_mutex);
  706. /* Disable DSD Interrupts */
  707. snd_soc_component_update_bits(component,
  708. WCD934X_INTR_CODEC_MISC_MASK, 0x08, 0x08);
  709. devm_kfree(component->dev, dsd_conf);
  710. }
  711. EXPORT_SYMBOL(tavil_dsd_deinit);