wcd9335-regmap.c 88 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/regmap.h>
  6. #include <linux/device.h>
  7. #include <asoc/core.h>
  8. #include <asoc/wcd9xxx-regmap.h>
  9. #include "wcd9335_registers.h"
  10. static const struct reg_sequence wcd9335_1_x_defaults[] = {
  11. { WCD9335_CODEC_RPM_CLK_GATE, 0x03, 0x00 },
  12. { WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN, 0x1f, 0x00 },
  13. { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x00, 0x00 },
  14. { WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x00, 0x00 },
  15. { WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG, 0x00, 0x00 },
  16. { WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG, 0x00, 0x00 },
  17. { WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG, 0x00, 0x00 },
  18. { WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG, 0x00, 0x00 },
  19. { WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD, 0x14, 0x00 },
  20. { WCD9335_CPE_SS_SS_ERROR_INT_MASK, 0x3f, 0x00 },
  21. { WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL, 0x00, 0x00 },
  22. { WCD9335_BIAS_VBG_FINE_ADJ, 0x55, 0x00 },
  23. { WCD9335_SIDO_SIDO_CCL_2, 0x6c, 0x00 },
  24. { WCD9335_SIDO_SIDO_CCL_3, 0x2d, 0x00 },
  25. { WCD9335_SIDO_SIDO_CCL_8, 0x6c, 0x00 },
  26. { WCD9335_SIDO_SIDO_CCL_10, 0x6c, 0x00 },
  27. { WCD9335_SIDO_SIDO_DRIVER_2, 0x77, 0x00 },
  28. { WCD9335_SIDO_SIDO_DRIVER_3, 0x77, 0x00 },
  29. { WCD9335_SIDO_SIDO_TEST_2, 0x00, 0x00 },
  30. { WCD9335_MBHC_ZDET_ANA_CTL, 0x00, 0x00 },
  31. { WCD9335_MBHC_FSM_DEBUG, 0xc0, 0x00 },
  32. { WCD9335_TX_1_2_ATEST_REFCTL, 0x08, 0x00 },
  33. { WCD9335_TX_3_4_ATEST_REFCTL, 0x08, 0x00 },
  34. { WCD9335_TX_5_6_ATEST_REFCTL, 0x08, 0x00 },
  35. { WCD9335_FLYBACK_VNEG_CTRL_1, 0x67, 0x00 },
  36. { WCD9335_FLYBACK_VNEG_CTRL_4, 0x5f, 0x00 },
  37. { WCD9335_FLYBACK_VNEG_CTRL_9, 0x50, 0x00 },
  38. { WCD9335_FLYBACK_VNEG_DAC_CTRL_1, 0x65, 0x00 },
  39. { WCD9335_FLYBACK_VNEG_DAC_CTRL_4, 0x40, 0x00 },
  40. { WCD9335_RX_BIAS_HPH_PA, 0xaa, 0x00 },
  41. { WCD9335_RX_BIAS_HPH_LOWPOWER, 0x62, 0x00 },
  42. { WCD9335_HPH_PA_CTL2, 0x40, 0x00 },
  43. { WCD9335_HPH_L_EN, 0x00, 0x00 },
  44. { WCD9335_HPH_R_EN, 0x00, 0x00 },
  45. { WCD9335_HPH_R_ATEST, 0x50, 0x00 },
  46. { WCD9335_HPH_RDAC_LDO_CTL, 0x00, 0x00 },
  47. { WCD9335_CDC_TX0_TX_PATH_CFG0, 0x00, 0x00 },
  48. { WCD9335_CDC_TX0_TX_PATH_CFG1, 0x00, 0x00 },
  49. { WCD9335_CDC_TX0_TX_PATH_SEC2, 0x00, 0x00 },
  50. { WCD9335_CDC_TX0_TX_PATH_SEC3, 0x0c, 0x00 },
  51. { WCD9335_CDC_TX1_TX_PATH_CFG0, 0x00, 0x00 },
  52. { WCD9335_CDC_TX1_TX_PATH_CFG1, 0x00, 0x00 },
  53. { WCD9335_CDC_TX1_TX_PATH_SEC2, 0x00, 0x00 },
  54. { WCD9335_CDC_TX1_TX_PATH_SEC3, 0x0c, 0x00 },
  55. { WCD9335_CDC_TX2_TX_PATH_CFG0, 0x00, 0x00 },
  56. { WCD9335_CDC_TX3_TX_PATH_CFG0, 0x00, 0x00 },
  57. { WCD9335_CDC_TX4_TX_PATH_CFG0, 0x00, 0x00 },
  58. { WCD9335_CDC_TX5_TX_PATH_CFG0, 0x00, 0x00 },
  59. { WCD9335_CDC_TX6_TX_PATH_CFG0, 0x00, 0x00 },
  60. { WCD9335_CDC_TX7_TX_PATH_CFG0, 0x00, 0x00 },
  61. { WCD9335_CDC_TX8_TX_PATH_CFG0, 0x00, 0x00 },
  62. { WCD9335_CDC_TX2_TX_PATH_CFG1, 0x00, 0x00 },
  63. { WCD9335_CDC_TX3_TX_PATH_CFG1, 0x00, 0x00 },
  64. { WCD9335_CDC_TX4_TX_PATH_CFG1, 0x00, 0x00 },
  65. { WCD9335_CDC_TX5_TX_PATH_CFG1, 0x00, 0x00 },
  66. { WCD9335_CDC_TX6_TX_PATH_CFG1, 0x00, 0x00 },
  67. { WCD9335_CDC_TX7_TX_PATH_CFG1, 0x00, 0x00 },
  68. { WCD9335_CDC_TX8_TX_PATH_CFG1, 0x00, 0x00 },
  69. { WCD9335_CDC_TX2_TX_PATH_SEC2, 0x00, 0x00 },
  70. { WCD9335_CDC_TX3_TX_PATH_SEC2, 0x00, 0x00 },
  71. { WCD9335_CDC_TX4_TX_PATH_SEC2, 0x00, 0x00 },
  72. { WCD9335_CDC_TX5_TX_PATH_SEC2, 0x00, 0x00 },
  73. { WCD9335_CDC_TX6_TX_PATH_SEC2, 0x00, 0x00 },
  74. { WCD9335_CDC_TX7_TX_PATH_SEC2, 0x00, 0x00 },
  75. { WCD9335_CDC_TX8_TX_PATH_SEC2, 0x00, 0x00 },
  76. { WCD9335_CDC_TX2_TX_PATH_SEC3, 0x0c, 0x00 },
  77. { WCD9335_CDC_TX3_TX_PATH_SEC3, 0x0c, 0x00 },
  78. { WCD9335_CDC_TX4_TX_PATH_SEC3, 0x0c, 0x00 },
  79. { WCD9335_CDC_TX5_TX_PATH_SEC3, 0x0c, 0x00 },
  80. { WCD9335_CDC_TX6_TX_PATH_SEC3, 0x0c, 0x00 },
  81. { WCD9335_CDC_TX7_TX_PATH_SEC3, 0x0c, 0x00 },
  82. { WCD9335_CDC_TX8_TX_PATH_SEC3, 0x0c, 0x00 },
  83. { WCD9335_CDC_COMPANDER1_CTL7, 0x0c, 0x00 },
  84. { WCD9335_CDC_COMPANDER2_CTL7, 0x0c, 0x00 },
  85. { WCD9335_CDC_COMPANDER3_CTL7, 0x0c, 0x00 },
  86. { WCD9335_CDC_COMPANDER4_CTL7, 0x0c, 0x00 },
  87. { WCD9335_CDC_COMPANDER5_CTL7, 0x0c, 0x00 },
  88. { WCD9335_CDC_COMPANDER6_CTL7, 0x0c, 0x00 },
  89. { WCD9335_CDC_COMPANDER7_CTL7, 0x0c, 0x00 },
  90. { WCD9335_CDC_COMPANDER8_CTL7, 0x0c, 0x00 },
  91. { WCD9335_CDC_RX0_RX_PATH_CFG1, 0x04, 0x00 },
  92. { WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  93. { WCD9335_CDC_RX0_RX_PATH_SEC0, 0x00, 0x00 },
  94. { WCD9335_CDC_RX0_RX_PATH_SEC1, 0x00, 0x00 },
  95. { WCD9335_CDC_RX0_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  96. { WCD9335_CDC_RX1_RX_PATH_CFG1, 0x04, 0x00 },
  97. { WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  98. { WCD9335_CDC_RX1_RX_PATH_SEC0, 0x00, 0x00 },
  99. { WCD9335_CDC_RX1_RX_PATH_SEC1, 0x00, 0x00 },
  100. { WCD9335_CDC_RX1_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  101. { WCD9335_CDC_RX2_RX_PATH_CFG1, 0x04, 0x00 },
  102. { WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  103. { WCD9335_CDC_RX2_RX_PATH_SEC0, 0x00, 0x00 },
  104. { WCD9335_CDC_RX2_RX_PATH_SEC1, 0x00, 0x00 },
  105. { WCD9335_CDC_RX2_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  106. { WCD9335_CDC_RX3_RX_PATH_CFG1, 0x04, 0x00 },
  107. { WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  108. { WCD9335_CDC_RX3_RX_PATH_SEC0, 0x00, 0x00 },
  109. { WCD9335_CDC_RX3_RX_PATH_SEC1, 0x00, 0x00 },
  110. { WCD9335_CDC_RX3_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  111. { WCD9335_CDC_RX4_RX_PATH_CFG1, 0x04, 0x00 },
  112. { WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  113. { WCD9335_CDC_RX4_RX_PATH_SEC0, 0x00, 0x00 },
  114. { WCD9335_CDC_RX4_RX_PATH_SEC1, 0x00, 0x00 },
  115. { WCD9335_CDC_RX4_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  116. { WCD9335_CDC_RX5_RX_PATH_CFG1, 0x04, 0x00 },
  117. { WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  118. { WCD9335_CDC_RX5_RX_PATH_SEC0, 0x00, 0x00 },
  119. { WCD9335_CDC_RX5_RX_PATH_SEC1, 0x00, 0x00 },
  120. { WCD9335_CDC_RX5_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  121. { WCD9335_CDC_RX6_RX_PATH_CFG1, 0x04, 0x00 },
  122. { WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  123. { WCD9335_CDC_RX6_RX_PATH_SEC0, 0x00, 0x00 },
  124. { WCD9335_CDC_RX6_RX_PATH_SEC1, 0x00, 0x00 },
  125. { WCD9335_CDC_RX6_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  126. { WCD9335_CDC_RX7_RX_PATH_CFG1, 0x04, 0x00 },
  127. { WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  128. { WCD9335_CDC_RX7_RX_PATH_SEC0, 0x00, 0x00 },
  129. { WCD9335_CDC_RX7_RX_PATH_SEC1, 0x00, 0x00 },
  130. { WCD9335_CDC_RX7_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  131. { WCD9335_CDC_RX8_RX_PATH_CFG1, 0x04, 0x00 },
  132. { WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x0e, 0x00 },
  133. { WCD9335_CDC_RX8_RX_PATH_SEC0, 0x00, 0x00 },
  134. { WCD9335_CDC_RX8_RX_PATH_SEC1, 0x00, 0x00 },
  135. { WCD9335_CDC_RX8_RX_PATH_MIX_SEC0, 0x00, 0x00 },
  136. { WCD9335_SPLINE_SRC0_CLK_RST_CTL_0, 0x00, 0x00 },
  137. { WCD9335_SPLINE_SRC1_CLK_RST_CTL_0, 0x00, 0x00 },
  138. { WCD9335_SPLINE_SRC2_CLK_RST_CTL_0, 0x00, 0x00 },
  139. { WCD9335_SPLINE_SRC3_CLK_RST_CTL_0, 0x00, 0x00 },
  140. { WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00, 0x00 },
  141. { WCD9335_TEST_DEBUG_NPL_DLY_TEST_1, 0x00, 0x00 },
  142. { WCD9335_TEST_DEBUG_NPL_DLY_TEST_2, 0x00, 0x00 },
  143. };
  144. static const struct reg_sequence wcd9335_2_0_defaults[] = {
  145. { WCD9335_CODEC_RPM_CLK_GATE, 0x07, 0x00 },
  146. { WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN, 0x3f, 0x00 },
  147. { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x01, 0x00 },
  148. { WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x10, 0x00 },
  149. { WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG, 0x08, 0x00 },
  150. { WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG, 0x08, 0x00 },
  151. { WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG, 0x08, 0x00 },
  152. { WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG, 0x08, 0x00 },
  153. { WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD, 0x13, 0x00 },
  154. { WCD9335_CPE_SS_SS_ERROR_INT_MASK, 0xff, 0x00 },
  155. { WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL, 0x40, 0x00 },
  156. { WCD9335_BIAS_VBG_FINE_ADJ, 0xc5, 0x00 },
  157. { WCD9335_SIDO_SIDO_CCL_2, 0x92, 0x00 },
  158. { WCD9335_SIDO_SIDO_CCL_3, 0x35, 0x00 },
  159. { WCD9335_SIDO_SIDO_CCL_8, 0x6e, 0x00 },
  160. { WCD9335_SIDO_SIDO_CCL_10, 0x6e, 0x00 },
  161. { WCD9335_SIDO_SIDO_DRIVER_2, 0x55, 0x00 },
  162. { WCD9335_SIDO_SIDO_DRIVER_3, 0x55, 0x00 },
  163. { WCD9335_SIDO_SIDO_TEST_2, 0x0f, 0x00 },
  164. { WCD9335_MBHC_ZDET_ANA_CTL, 0x0f, 0x00 },
  165. { WCD9335_TX_1_2_ATEST_REFCTL, 0x0a, 0x00 },
  166. { WCD9335_TX_3_4_ATEST_REFCTL, 0x0a, 0x00 },
  167. { WCD9335_TX_5_6_ATEST_REFCTL, 0x0a, 0x00 },
  168. { WCD9335_FLYBACK_VNEG_CTRL_1, 0xeb, 0x00 },
  169. { WCD9335_FLYBACK_VNEG_CTRL_4, 0x7f, 0x00 },
  170. { WCD9335_FLYBACK_VNEG_CTRL_9, 0x64, 0x00 },
  171. { WCD9335_FLYBACK_VNEG_DAC_CTRL_1, 0xed, 0x00 },
  172. { WCD9335_RX_BIAS_HPH_PA, 0x9a, 0x00 },
  173. { WCD9335_RX_BIAS_HPH_LOWPOWER, 0x82, 0x00 },
  174. { WCD9335_HPH_PA_CTL2, 0x50, 0x00 },
  175. { WCD9335_HPH_L_EN, 0x80, 0x00 },
  176. { WCD9335_HPH_R_EN, 0x80, 0x00 },
  177. { WCD9335_HPH_R_ATEST, 0x54, 0x00 },
  178. { WCD9335_HPH_RDAC_LDO_CTL, 0x33, 0x00 },
  179. { WCD9335_CDC_TX0_TX_PATH_CFG0, 0x10, 0x00 },
  180. { WCD9335_CDC_TX0_TX_PATH_CFG1, 0x02, 0x00 },
  181. { WCD9335_CDC_TX0_TX_PATH_SEC2, 0x01, 0x00 },
  182. { WCD9335_CDC_TX0_TX_PATH_SEC3, 0x3c, 0x00 },
  183. { WCD9335_CDC_TX1_TX_PATH_CFG0, 0x10, 0x00 },
  184. { WCD9335_CDC_TX1_TX_PATH_CFG1, 0x02, 0x00 },
  185. { WCD9335_CDC_TX1_TX_PATH_SEC2, 0x01, 0x00 },
  186. { WCD9335_CDC_TX1_TX_PATH_SEC3, 0x3c, 0x00 },
  187. { WCD9335_CDC_TX2_TX_PATH_CFG0, 0x10, 0x00 },
  188. { WCD9335_CDC_TX3_TX_PATH_CFG0, 0x10, 0x00 },
  189. { WCD9335_CDC_TX4_TX_PATH_CFG0, 0x10, 0x00 },
  190. { WCD9335_CDC_TX5_TX_PATH_CFG0, 0x10, 0x00 },
  191. { WCD9335_CDC_TX6_TX_PATH_CFG0, 0x10, 0x00 },
  192. { WCD9335_CDC_TX7_TX_PATH_CFG0, 0x10, 0x00 },
  193. { WCD9335_CDC_TX8_TX_PATH_CFG0, 0x10, 0x00 },
  194. { WCD9335_CDC_TX2_TX_PATH_CFG1, 0x02, 0x00 },
  195. { WCD9335_CDC_TX3_TX_PATH_CFG1, 0x02, 0x00 },
  196. { WCD9335_CDC_TX4_TX_PATH_CFG1, 0x02, 0x00 },
  197. { WCD9335_CDC_TX5_TX_PATH_CFG1, 0x02, 0x00 },
  198. { WCD9335_CDC_TX6_TX_PATH_CFG1, 0x02, 0x00 },
  199. { WCD9335_CDC_TX7_TX_PATH_CFG1, 0x02, 0x00 },
  200. { WCD9335_CDC_TX8_TX_PATH_CFG1, 0x02, 0x00 },
  201. { WCD9335_CDC_TX2_TX_PATH_SEC2, 0x01, 0x00 },
  202. { WCD9335_CDC_TX3_TX_PATH_SEC2, 0x01, 0x00 },
  203. { WCD9335_CDC_TX4_TX_PATH_SEC2, 0x01, 0x00 },
  204. { WCD9335_CDC_TX5_TX_PATH_SEC2, 0x01, 0x00 },
  205. { WCD9335_CDC_TX6_TX_PATH_SEC2, 0x01, 0x00 },
  206. { WCD9335_CDC_TX7_TX_PATH_SEC2, 0x01, 0x00 },
  207. { WCD9335_CDC_TX8_TX_PATH_SEC2, 0x01, 0x00 },
  208. { WCD9335_CDC_TX2_TX_PATH_SEC3, 0x3c, 0x00 },
  209. { WCD9335_CDC_TX3_TX_PATH_SEC3, 0x3c, 0x00 },
  210. { WCD9335_CDC_TX4_TX_PATH_SEC3, 0x3c, 0x00 },
  211. { WCD9335_CDC_TX5_TX_PATH_SEC3, 0x3c, 0x00 },
  212. { WCD9335_CDC_TX6_TX_PATH_SEC3, 0x3c, 0x00 },
  213. { WCD9335_CDC_TX7_TX_PATH_SEC3, 0x3c, 0x00 },
  214. { WCD9335_CDC_TX8_TX_PATH_SEC3, 0x3c, 0x00 },
  215. { WCD9335_CDC_COMPANDER1_CTL7, 0x08, 0x00 },
  216. { WCD9335_CDC_COMPANDER2_CTL7, 0x08, 0x00 },
  217. { WCD9335_CDC_COMPANDER3_CTL7, 0x08, 0x00 },
  218. { WCD9335_CDC_COMPANDER4_CTL7, 0x08, 0x00 },
  219. { WCD9335_CDC_COMPANDER5_CTL7, 0x08, 0x00 },
  220. { WCD9335_CDC_COMPANDER6_CTL7, 0x08, 0x00 },
  221. { WCD9335_CDC_COMPANDER7_CTL7, 0x08, 0x00 },
  222. { WCD9335_CDC_COMPANDER8_CTL7, 0x08, 0x00 },
  223. { WCD9335_CDC_RX0_RX_PATH_CFG1, 0x44, 0x00 },
  224. { WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  225. { WCD9335_CDC_RX0_RX_PATH_SEC0, 0xfc, 0x00 },
  226. { WCD9335_CDC_RX0_RX_PATH_SEC1, 0x08, 0x00 },
  227. { WCD9335_CDC_RX0_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  228. { WCD9335_CDC_RX1_RX_PATH_CFG1, 0x44, 0x00 },
  229. { WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  230. { WCD9335_CDC_RX1_RX_PATH_SEC0, 0xfc, 0x00 },
  231. { WCD9335_CDC_RX1_RX_PATH_SEC1, 0x08, 0x00 },
  232. { WCD9335_CDC_RX1_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  233. { WCD9335_CDC_RX2_RX_PATH_CFG1, 0x44, 0x00 },
  234. { WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  235. { WCD9335_CDC_RX2_RX_PATH_SEC0, 0xfc, 0x00 },
  236. { WCD9335_CDC_RX2_RX_PATH_SEC1, 0x08, 0x00 },
  237. { WCD9335_CDC_RX2_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  238. { WCD9335_CDC_RX3_RX_PATH_CFG1, 0x44, 0x00 },
  239. { WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  240. { WCD9335_CDC_RX3_RX_PATH_SEC0, 0xfc, 0x00 },
  241. { WCD9335_CDC_RX3_RX_PATH_SEC1, 0x08, 0x00 },
  242. { WCD9335_CDC_RX3_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  243. { WCD9335_CDC_RX4_RX_PATH_CFG1, 0x44, 0x00 },
  244. { WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  245. { WCD9335_CDC_RX4_RX_PATH_SEC0, 0xfc, 0x00 },
  246. { WCD9335_CDC_RX4_RX_PATH_SEC1, 0x08, 0x00 },
  247. { WCD9335_CDC_RX4_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  248. { WCD9335_CDC_RX5_RX_PATH_CFG1, 0x44, 0x00 },
  249. { WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  250. { WCD9335_CDC_RX5_RX_PATH_SEC0, 0xfc, 0x00 },
  251. { WCD9335_CDC_RX5_RX_PATH_SEC1, 0x08, 0x00 },
  252. { WCD9335_CDC_RX5_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  253. { WCD9335_CDC_RX6_RX_PATH_CFG1, 0x44, 0x00 },
  254. { WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  255. { WCD9335_CDC_RX6_RX_PATH_SEC0, 0xfc, 0x00 },
  256. { WCD9335_CDC_RX6_RX_PATH_SEC1, 0x08, 0x00 },
  257. { WCD9335_CDC_RX6_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  258. { WCD9335_CDC_RX7_RX_PATH_CFG1, 0x44, 0x00 },
  259. { WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  260. { WCD9335_CDC_RX7_RX_PATH_SEC0, 0xfc, 0x00 },
  261. { WCD9335_CDC_RX7_RX_PATH_SEC1, 0x08, 0x00 },
  262. { WCD9335_CDC_RX7_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  263. { WCD9335_CDC_RX8_RX_PATH_CFG1, 0x44, 0x00 },
  264. { WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x1e, 0x00 },
  265. { WCD9335_CDC_RX8_RX_PATH_SEC0, 0xfc, 0x00 },
  266. { WCD9335_CDC_RX8_RX_PATH_SEC1, 0x08, 0x00 },
  267. { WCD9335_CDC_RX8_RX_PATH_MIX_SEC0, 0x08, 0x00 },
  268. { WCD9335_SPLINE_SRC0_CLK_RST_CTL_0, 0x20, 0x00 },
  269. { WCD9335_SPLINE_SRC1_CLK_RST_CTL_0, 0x20, 0x00 },
  270. { WCD9335_SPLINE_SRC2_CLK_RST_CTL_0, 0x20, 0x00 },
  271. { WCD9335_SPLINE_SRC3_CLK_RST_CTL_0, 0x20, 0x00 },
  272. { WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x0c, 0x00 },
  273. { WCD9335_TEST_DEBUG_NPL_DLY_TEST_1, 0x10, 0x00 },
  274. { WCD9335_TEST_DEBUG_NPL_DLY_TEST_2, 0x60, 0x00 },
  275. { WCD9335_DATA_HUB_NATIVE_FIFO_SYNC, 0x00, 0x00 },
  276. { WCD9335_DATA_HUB_NATIVE_FIFO_STATUS, 0x00, 0x00 },
  277. { WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD, 0x60, 0x00 },
  278. { WCD9335_CPE_SS_TX_PP_CFG, 0x3C, 0x00 },
  279. { WCD9335_CPE_SS_SVA_CFG, 0x00, 0x00 },
  280. { WCD9335_MBHC_FSM_STATUS, 0x00, 0x00 },
  281. { WCD9335_FLYBACK_CTRL_1, 0x45, 0x00 },
  282. { WCD9335_CDC_TX0_TX_PATH_SEC7, 0x25, 0x00 },
  283. { WCD9335_SPLINE_SRC0_STATUS, 0x00, 0x00 },
  284. { WCD9335_SPLINE_SRC1_STATUS, 0x00, 0x00 },
  285. { WCD9335_SPLINE_SRC2_STATUS, 0x00, 0x00 },
  286. { WCD9335_SPLINE_SRC3_STATUS, 0x00, 0x00 },
  287. { WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT, 0x00, 0x00 },
  288. };
  289. static const struct reg_default wcd9335_defaults[] = {
  290. /* Page #0 registers */
  291. { WCD9335_PAGE0_PAGE_REGISTER, 0x00 },
  292. { WCD9335_CODEC_RPM_CLK_BYPASS, 0x00 },
  293. { WCD9335_CODEC_RPM_CLK_MCLK_CFG, 0x00 },
  294. { WCD9335_CODEC_RPM_RST_CTL, 0x00 },
  295. { WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x07 },
  296. { WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_1, 0x00 },
  297. { WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_2, 0x00 },
  298. { WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_3, 0x00 },
  299. { WCD9335_CODEC_RPM_PWR_CPE_IRAM_SHUTDOWN, 0x01 },
  300. { WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_1, 0xff },
  301. { WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_2, 0xff },
  302. { WCD9335_CODEC_RPM_INT_MASK, 0x3f },
  303. { WCD9335_CODEC_RPM_INT_STATUS, 0x00 },
  304. { WCD9335_CODEC_RPM_INT_CLEAR, 0x00 },
  305. { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE1, 0x00 },
  306. { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2, 0x07 },
  307. { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE3, 0x01 },
  308. { WCD9335_CHIP_TIER_CTRL_EFUSE_TEST0, 0x00 },
  309. { WCD9335_CHIP_TIER_CTRL_EFUSE_TEST1, 0x00 },
  310. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, 0x00 },
  311. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT1, 0x00 },
  312. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT2, 0x00 },
  313. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT3, 0x00 },
  314. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT4, 0x00 },
  315. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT5, 0x00 },
  316. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT6, 0x00 },
  317. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT7, 0x00 },
  318. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT8, 0x00 },
  319. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT9, 0x00 },
  320. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT10, 0x00 },
  321. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT11, 0x00 },
  322. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT12, 0x00 },
  323. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT13, 0x00 },
  324. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, 0x00 },
  325. { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, 0x00 },
  326. { WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS, 0x00 },
  327. { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO, 0x0d },
  328. { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_1, 0x00 },
  329. { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_2, 0x00 },
  330. { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_3, 0x00 },
  331. { WCD9335_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL, 0xCC },
  332. { WCD9335_CHIP_TIER_CTRL_I2C_ACTIVE, 0x00 },
  333. { WCD9335_CHIP_TIER_CTRL_PROC1_MON_CTL, 0x06 },
  334. { WCD9335_CHIP_TIER_CTRL_PROC1_MON_STATUS, 0x00 },
  335. { WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_MSB, 0x00 },
  336. { WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_LSB, 0x00 },
  337. { WCD9335_CHIP_TIER_CTRL_PROC2_MON_CTL, 0x06 },
  338. { WCD9335_CHIP_TIER_CTRL_PROC2_MON_STATUS, 0x00 },
  339. { WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_MSB, 0x00 },
  340. { WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_LSB, 0x00 },
  341. { WCD9335_CHIP_TIER_CTRL_PROC3_MON_CTL, 0x06 },
  342. { WCD9335_CHIP_TIER_CTRL_PROC3_MON_STATUS, 0x00 },
  343. { WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_MSB, 0x00 },
  344. { WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_LSB, 0x00 },
  345. { WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL, 0x0c },
  346. { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL, 0x0c },
  347. { WCD9335_DATA_HUB_DATA_HUB_I2S_CLK, 0x00 },
  348. { WCD9335_DATA_HUB_DATA_HUB_RX4_INP_CFG, 0x00 },
  349. { WCD9335_DATA_HUB_DATA_HUB_RX5_INP_CFG, 0x00 },
  350. { WCD9335_DATA_HUB_DATA_HUB_RX6_INP_CFG, 0x00 },
  351. { WCD9335_DATA_HUB_DATA_HUB_RX7_INP_CFG, 0x00 },
  352. { WCD9335_DATA_HUB_DATA_HUB_SB_TX0_INP_CFG, 0x00 },
  353. { WCD9335_DATA_HUB_DATA_HUB_SB_TX1_INP_CFG, 0x00 },
  354. { WCD9335_DATA_HUB_DATA_HUB_SB_TX2_INP_CFG, 0x00 },
  355. { WCD9335_DATA_HUB_DATA_HUB_SB_TX3_INP_CFG, 0x00 },
  356. { WCD9335_DATA_HUB_DATA_HUB_SB_TX4_INP_CFG, 0x00 },
  357. { WCD9335_DATA_HUB_DATA_HUB_SB_TX5_INP_CFG, 0x00 },
  358. { WCD9335_DATA_HUB_DATA_HUB_SB_TX6_INP_CFG, 0x00 },
  359. { WCD9335_DATA_HUB_DATA_HUB_SB_TX7_INP_CFG, 0x00 },
  360. { WCD9335_DATA_HUB_DATA_HUB_SB_TX8_INP_CFG, 0x00 },
  361. { WCD9335_DATA_HUB_DATA_HUB_SB_TX9_INP_CFG, 0x00 },
  362. { WCD9335_DATA_HUB_DATA_HUB_SB_TX10_INP_CFG, 0x00 },
  363. { WCD9335_DATA_HUB_DATA_HUB_SB_TX11_INP_CFG, 0x00 },
  364. { WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG, 0x00 },
  365. { WCD9335_DATA_HUB_DATA_HUB_SB_TX14_INP_CFG, 0x00 },
  366. { WCD9335_DATA_HUB_DATA_HUB_SB_TX15_INP_CFG, 0x00 },
  367. { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_L_CFG, 0x00 },
  368. { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG, 0x00 },
  369. { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG, 0x00 },
  370. { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG, 0x00 },
  371. { WCD9335_INTR_CFG, 0x00 },
  372. { WCD9335_INTR_CLR_COMMIT, 0x00 },
  373. { WCD9335_INTR_PIN1_MASK0, 0xff },
  374. { WCD9335_INTR_PIN1_MASK1, 0xff },
  375. { WCD9335_INTR_PIN1_MASK2, 0xff },
  376. { WCD9335_INTR_PIN1_MASK3, 0xff },
  377. { WCD9335_INTR_PIN1_STATUS0, 0x00 },
  378. { WCD9335_INTR_PIN1_STATUS1, 0x00 },
  379. { WCD9335_INTR_PIN1_STATUS2, 0x00 },
  380. { WCD9335_INTR_PIN1_STATUS3, 0x00 },
  381. { WCD9335_INTR_PIN1_CLEAR0, 0x00 },
  382. { WCD9335_INTR_PIN1_CLEAR1, 0x00 },
  383. { WCD9335_INTR_PIN1_CLEAR2, 0x00 },
  384. { WCD9335_INTR_PIN1_CLEAR3, 0x00 },
  385. { WCD9335_INTR_PIN2_MASK0, 0xff },
  386. { WCD9335_INTR_PIN2_MASK1, 0xff },
  387. { WCD9335_INTR_PIN2_MASK2, 0xff },
  388. { WCD9335_INTR_PIN2_MASK3, 0xff },
  389. { WCD9335_INTR_PIN2_STATUS0, 0x00 },
  390. { WCD9335_INTR_PIN2_STATUS1, 0x00 },
  391. { WCD9335_INTR_PIN2_STATUS2, 0x00 },
  392. { WCD9335_INTR_PIN2_STATUS3, 0x00 },
  393. { WCD9335_INTR_PIN2_CLEAR0, 0x00 },
  394. { WCD9335_INTR_PIN2_CLEAR1, 0x00 },
  395. { WCD9335_INTR_PIN2_CLEAR2, 0x00 },
  396. { WCD9335_INTR_PIN2_CLEAR3, 0x00 },
  397. { WCD9335_INTR_LEVEL0, 0x03 },
  398. { WCD9335_INTR_LEVEL1, 0xe0 },
  399. { WCD9335_INTR_LEVEL2, 0x10 },
  400. { WCD9335_INTR_LEVEL3, 0x80 },
  401. { WCD9335_INTR_BYPASS0, 0x00 },
  402. { WCD9335_INTR_BYPASS1, 0x00 },
  403. { WCD9335_INTR_BYPASS2, 0x00 },
  404. { WCD9335_INTR_BYPASS3, 0x00 },
  405. { WCD9335_INTR_SET0, 0x00 },
  406. { WCD9335_INTR_SET1, 0x00 },
  407. { WCD9335_INTR_SET2, 0x00 },
  408. { WCD9335_INTR_SET3, 0x00 },
  409. /* Page #1 registers */
  410. { WCD9335_PAGE1_PAGE_REGISTER, 0x00 },
  411. { WCD9335_CPE_FLL_USER_CTL_0, 0x71 },
  412. { WCD9335_CPE_FLL_USER_CTL_1, 0x34 },
  413. { WCD9335_CPE_FLL_USER_CTL_2, 0x0b },
  414. { WCD9335_CPE_FLL_USER_CTL_3, 0x02 },
  415. { WCD9335_CPE_FLL_USER_CTL_4, 0x04 },
  416. { WCD9335_CPE_FLL_USER_CTL_5, 0x02 },
  417. { WCD9335_CPE_FLL_USER_CTL_6, 0x64 },
  418. { WCD9335_CPE_FLL_USER_CTL_7, 0x00 },
  419. { WCD9335_CPE_FLL_USER_CTL_8, 0x94 },
  420. { WCD9335_CPE_FLL_USER_CTL_9, 0x70 },
  421. { WCD9335_CPE_FLL_L_VAL_CTL_0, 0x40 },
  422. { WCD9335_CPE_FLL_L_VAL_CTL_1, 0x00 },
  423. { WCD9335_CPE_FLL_DSM_FRAC_CTL_0, 0x00 },
  424. { WCD9335_CPE_FLL_DSM_FRAC_CTL_1, 0xff },
  425. { WCD9335_CPE_FLL_CONFIG_CTL_0, 0x6b },
  426. { WCD9335_CPE_FLL_CONFIG_CTL_1, 0x05 },
  427. { WCD9335_CPE_FLL_CONFIG_CTL_2, 0x08 },
  428. { WCD9335_CPE_FLL_CONFIG_CTL_3, 0x00 },
  429. { WCD9335_CPE_FLL_CONFIG_CTL_4, 0x10 },
  430. { WCD9335_CPE_FLL_TEST_CTL_0, 0x00 },
  431. { WCD9335_CPE_FLL_TEST_CTL_1, 0x00 },
  432. { WCD9335_CPE_FLL_TEST_CTL_2, 0x00 },
  433. { WCD9335_CPE_FLL_TEST_CTL_3, 0x00 },
  434. { WCD9335_CPE_FLL_TEST_CTL_4, 0x00 },
  435. { WCD9335_CPE_FLL_TEST_CTL_5, 0x00 },
  436. { WCD9335_CPE_FLL_TEST_CTL_6, 0x00 },
  437. { WCD9335_CPE_FLL_TEST_CTL_7, 0x33 },
  438. { WCD9335_CPE_FLL_FREQ_CTL_0, 0x00 },
  439. { WCD9335_CPE_FLL_FREQ_CTL_1, 0x00 },
  440. { WCD9335_CPE_FLL_FREQ_CTL_2, 0x00 },
  441. { WCD9335_CPE_FLL_FREQ_CTL_3, 0x00 },
  442. { WCD9335_CPE_FLL_SSC_CTL_0, 0x00 },
  443. { WCD9335_CPE_FLL_SSC_CTL_1, 0x00 },
  444. { WCD9335_CPE_FLL_SSC_CTL_2, 0x00 },
  445. { WCD9335_CPE_FLL_SSC_CTL_3, 0x00 },
  446. { WCD9335_CPE_FLL_FLL_MODE, 0x20 },
  447. { WCD9335_CPE_FLL_STATUS_0, 0x00 },
  448. { WCD9335_CPE_FLL_STATUS_1, 0x00 },
  449. { WCD9335_CPE_FLL_STATUS_2, 0x00 },
  450. { WCD9335_CPE_FLL_STATUS_3, 0x00 },
  451. { WCD9335_I2S_FLL_USER_CTL_0, 0x41 },
  452. { WCD9335_I2S_FLL_USER_CTL_1, 0x94 },
  453. { WCD9335_I2S_FLL_USER_CTL_2, 0x08 },
  454. { WCD9335_I2S_FLL_USER_CTL_3, 0x02 },
  455. { WCD9335_I2S_FLL_USER_CTL_4, 0x04 },
  456. { WCD9335_I2S_FLL_USER_CTL_5, 0x02 },
  457. { WCD9335_I2S_FLL_USER_CTL_6, 0x40 },
  458. { WCD9335_I2S_FLL_USER_CTL_7, 0x00 },
  459. { WCD9335_I2S_FLL_USER_CTL_8, 0x5f },
  460. { WCD9335_I2S_FLL_USER_CTL_9, 0x02 },
  461. { WCD9335_I2S_FLL_L_VAL_CTL_0, 0x40 },
  462. { WCD9335_I2S_FLL_L_VAL_CTL_1, 0x00 },
  463. { WCD9335_I2S_FLL_DSM_FRAC_CTL_0, 0x00 },
  464. { WCD9335_I2S_FLL_DSM_FRAC_CTL_1, 0xff },
  465. { WCD9335_I2S_FLL_CONFIG_CTL_0, 0x6b },
  466. { WCD9335_I2S_FLL_CONFIG_CTL_1, 0x05 },
  467. { WCD9335_I2S_FLL_CONFIG_CTL_2, 0x08 },
  468. { WCD9335_I2S_FLL_CONFIG_CTL_3, 0x00 },
  469. { WCD9335_I2S_FLL_CONFIG_CTL_4, 0x30 },
  470. { WCD9335_I2S_FLL_TEST_CTL_0, 0x80 },
  471. { WCD9335_I2S_FLL_TEST_CTL_1, 0x00 },
  472. { WCD9335_I2S_FLL_TEST_CTL_2, 0x00 },
  473. { WCD9335_I2S_FLL_TEST_CTL_3, 0x00 },
  474. { WCD9335_I2S_FLL_TEST_CTL_4, 0x00 },
  475. { WCD9335_I2S_FLL_TEST_CTL_5, 0x00 },
  476. { WCD9335_I2S_FLL_TEST_CTL_6, 0x00 },
  477. { WCD9335_I2S_FLL_TEST_CTL_7, 0xff },
  478. { WCD9335_I2S_FLL_FREQ_CTL_0, 0x00 },
  479. { WCD9335_I2S_FLL_FREQ_CTL_1, 0x00 },
  480. { WCD9335_I2S_FLL_FREQ_CTL_2, 0x00 },
  481. { WCD9335_I2S_FLL_FREQ_CTL_3, 0x00 },
  482. { WCD9335_I2S_FLL_SSC_CTL_0, 0x00 },
  483. { WCD9335_I2S_FLL_SSC_CTL_1, 0x00 },
  484. { WCD9335_I2S_FLL_SSC_CTL_2, 0x00 },
  485. { WCD9335_I2S_FLL_SSC_CTL_3, 0x00 },
  486. { WCD9335_I2S_FLL_FLL_MODE, 0x00 },
  487. { WCD9335_I2S_FLL_STATUS_0, 0x00 },
  488. { WCD9335_I2S_FLL_STATUS_1, 0x00 },
  489. { WCD9335_I2S_FLL_STATUS_2, 0x00 },
  490. { WCD9335_I2S_FLL_STATUS_3, 0x00 },
  491. { WCD9335_SB_FLL_USER_CTL_0, 0x41 },
  492. { WCD9335_SB_FLL_USER_CTL_1, 0x94 },
  493. { WCD9335_SB_FLL_USER_CTL_2, 0x08 },
  494. { WCD9335_SB_FLL_USER_CTL_3, 0x02 },
  495. { WCD9335_SB_FLL_USER_CTL_4, 0x04 },
  496. { WCD9335_SB_FLL_USER_CTL_5, 0x02 },
  497. { WCD9335_SB_FLL_USER_CTL_6, 0x40 },
  498. { WCD9335_SB_FLL_USER_CTL_7, 0x00 },
  499. { WCD9335_SB_FLL_USER_CTL_8, 0x5e },
  500. { WCD9335_SB_FLL_USER_CTL_9, 0x01 },
  501. { WCD9335_SB_FLL_L_VAL_CTL_0, 0x40 },
  502. { WCD9335_SB_FLL_L_VAL_CTL_1, 0x00 },
  503. { WCD9335_SB_FLL_DSM_FRAC_CTL_0, 0x00 },
  504. { WCD9335_SB_FLL_DSM_FRAC_CTL_1, 0xff },
  505. { WCD9335_SB_FLL_CONFIG_CTL_0, 0x6b },
  506. { WCD9335_SB_FLL_CONFIG_CTL_1, 0x05 },
  507. { WCD9335_SB_FLL_CONFIG_CTL_2, 0x08 },
  508. { WCD9335_SB_FLL_CONFIG_CTL_3, 0x00 },
  509. { WCD9335_SB_FLL_CONFIG_CTL_4, 0x10 },
  510. { WCD9335_SB_FLL_TEST_CTL_0, 0x00 },
  511. { WCD9335_SB_FLL_TEST_CTL_1, 0x00 },
  512. { WCD9335_SB_FLL_TEST_CTL_2, 0x00 },
  513. { WCD9335_SB_FLL_TEST_CTL_3, 0x00 },
  514. { WCD9335_SB_FLL_TEST_CTL_4, 0x00 },
  515. { WCD9335_SB_FLL_TEST_CTL_5, 0x00 },
  516. { WCD9335_SB_FLL_TEST_CTL_6, 0x00 },
  517. { WCD9335_SB_FLL_TEST_CTL_7, 0xff },
  518. { WCD9335_SB_FLL_FREQ_CTL_0, 0x00 },
  519. { WCD9335_SB_FLL_FREQ_CTL_1, 0x00 },
  520. { WCD9335_SB_FLL_FREQ_CTL_2, 0x00 },
  521. { WCD9335_SB_FLL_FREQ_CTL_3, 0x00 },
  522. { WCD9335_SB_FLL_SSC_CTL_0, 0x00 },
  523. { WCD9335_SB_FLL_SSC_CTL_1, 0x00 },
  524. { WCD9335_SB_FLL_SSC_CTL_2, 0x00 },
  525. { WCD9335_SB_FLL_SSC_CTL_3, 0x00 },
  526. { WCD9335_SB_FLL_FLL_MODE, 0x00 },
  527. { WCD9335_SB_FLL_STATUS_0, 0x00 },
  528. { WCD9335_SB_FLL_STATUS_1, 0x00 },
  529. { WCD9335_SB_FLL_STATUS_2, 0x00 },
  530. { WCD9335_SB_FLL_STATUS_3, 0x00 },
  531. /* Page #2 registers */
  532. { WCD9335_PAGE2_PAGE_REGISTER, 0x00 },
  533. { WCD9335_CPE_SS_MEM_PTR_0, 0x00 },
  534. { WCD9335_CPE_SS_MEM_PTR_1, 0x00 },
  535. { WCD9335_CPE_SS_MEM_PTR_2, 0x00 },
  536. { WCD9335_CPE_SS_MEM_CTRL, 0x08 },
  537. { WCD9335_CPE_SS_MEM_BANK_0, 0x00 },
  538. { WCD9335_CPE_SS_MEM_BANK_1, 0x00 },
  539. { WCD9335_CPE_SS_MEM_BANK_2, 0x00 },
  540. { WCD9335_CPE_SS_MEM_BANK_3, 0x00 },
  541. { WCD9335_CPE_SS_MEM_BANK_4, 0x00 },
  542. { WCD9335_CPE_SS_MEM_BANK_5, 0x00 },
  543. { WCD9335_CPE_SS_MEM_BANK_6, 0x00 },
  544. { WCD9335_CPE_SS_MEM_BANK_7, 0x00 },
  545. { WCD9335_CPE_SS_MEM_BANK_8, 0x00 },
  546. { WCD9335_CPE_SS_MEM_BANK_9, 0x00 },
  547. { WCD9335_CPE_SS_MEM_BANK_10, 0x00 },
  548. { WCD9335_CPE_SS_MEM_BANK_11, 0x00 },
  549. { WCD9335_CPE_SS_MEM_BANK_12, 0x00 },
  550. { WCD9335_CPE_SS_MEM_BANK_13, 0x00 },
  551. { WCD9335_CPE_SS_MEM_BANK_14, 0x00 },
  552. { WCD9335_CPE_SS_MEM_BANK_15, 0x00 },
  553. { WCD9335_CPE_SS_INBOX1_TRG, 0x00 },
  554. { WCD9335_CPE_SS_INBOX2_TRG, 0x00 },
  555. { WCD9335_CPE_SS_INBOX1_0, 0x00 },
  556. { WCD9335_CPE_SS_INBOX1_1, 0x00 },
  557. { WCD9335_CPE_SS_INBOX1_2, 0x00 },
  558. { WCD9335_CPE_SS_INBOX1_3, 0x00 },
  559. { WCD9335_CPE_SS_INBOX1_4, 0x00 },
  560. { WCD9335_CPE_SS_INBOX1_5, 0x00 },
  561. { WCD9335_CPE_SS_INBOX1_6, 0x00 },
  562. { WCD9335_CPE_SS_INBOX1_7, 0x00 },
  563. { WCD9335_CPE_SS_INBOX1_8, 0x00 },
  564. { WCD9335_CPE_SS_INBOX1_9, 0x00 },
  565. { WCD9335_CPE_SS_INBOX1_10, 0x00 },
  566. { WCD9335_CPE_SS_INBOX1_11, 0x00 },
  567. { WCD9335_CPE_SS_INBOX1_12, 0x00 },
  568. { WCD9335_CPE_SS_INBOX1_13, 0x00 },
  569. { WCD9335_CPE_SS_INBOX1_14, 0x00 },
  570. { WCD9335_CPE_SS_INBOX1_15, 0x00 },
  571. { WCD9335_CPE_SS_OUTBOX1_0, 0x00 },
  572. { WCD9335_CPE_SS_OUTBOX1_1, 0x00 },
  573. { WCD9335_CPE_SS_OUTBOX1_2, 0x00 },
  574. { WCD9335_CPE_SS_OUTBOX1_3, 0x00 },
  575. { WCD9335_CPE_SS_OUTBOX1_4, 0x00 },
  576. { WCD9335_CPE_SS_OUTBOX1_5, 0x00 },
  577. { WCD9335_CPE_SS_OUTBOX1_6, 0x00 },
  578. { WCD9335_CPE_SS_OUTBOX1_7, 0x00 },
  579. { WCD9335_CPE_SS_OUTBOX1_8, 0x00 },
  580. { WCD9335_CPE_SS_OUTBOX1_9, 0x00 },
  581. { WCD9335_CPE_SS_OUTBOX1_10, 0x00 },
  582. { WCD9335_CPE_SS_OUTBOX1_11, 0x00 },
  583. { WCD9335_CPE_SS_OUTBOX1_12, 0x00 },
  584. { WCD9335_CPE_SS_OUTBOX1_13, 0x00 },
  585. { WCD9335_CPE_SS_OUTBOX1_14, 0x00 },
  586. { WCD9335_CPE_SS_OUTBOX1_15, 0x00 },
  587. { WCD9335_CPE_SS_INBOX2_0, 0x00 },
  588. { WCD9335_CPE_SS_INBOX2_1, 0x00 },
  589. { WCD9335_CPE_SS_INBOX2_2, 0x00 },
  590. { WCD9335_CPE_SS_INBOX2_3, 0x00 },
  591. { WCD9335_CPE_SS_INBOX2_4, 0x00 },
  592. { WCD9335_CPE_SS_INBOX2_5, 0x00 },
  593. { WCD9335_CPE_SS_INBOX2_6, 0x00 },
  594. { WCD9335_CPE_SS_INBOX2_7, 0x00 },
  595. { WCD9335_CPE_SS_INBOX2_8, 0x00 },
  596. { WCD9335_CPE_SS_INBOX2_9, 0x00 },
  597. { WCD9335_CPE_SS_INBOX2_10, 0x00 },
  598. { WCD9335_CPE_SS_INBOX2_11, 0x00 },
  599. { WCD9335_CPE_SS_INBOX2_12, 0x00 },
  600. { WCD9335_CPE_SS_INBOX2_13, 0x00 },
  601. { WCD9335_CPE_SS_INBOX2_14, 0x00 },
  602. { WCD9335_CPE_SS_INBOX2_15, 0x00 },
  603. { WCD9335_CPE_SS_OUTBOX2_0, 0x00 },
  604. { WCD9335_CPE_SS_OUTBOX2_1, 0x00 },
  605. { WCD9335_CPE_SS_OUTBOX2_2, 0x00 },
  606. { WCD9335_CPE_SS_OUTBOX2_3, 0x00 },
  607. { WCD9335_CPE_SS_OUTBOX2_4, 0x00 },
  608. { WCD9335_CPE_SS_OUTBOX2_5, 0x00 },
  609. { WCD9335_CPE_SS_OUTBOX2_6, 0x00 },
  610. { WCD9335_CPE_SS_OUTBOX2_7, 0x00 },
  611. { WCD9335_CPE_SS_OUTBOX2_8, 0x00 },
  612. { WCD9335_CPE_SS_OUTBOX2_9, 0x00 },
  613. { WCD9335_CPE_SS_OUTBOX2_10, 0x00 },
  614. { WCD9335_CPE_SS_OUTBOX2_11, 0x00 },
  615. { WCD9335_CPE_SS_OUTBOX2_12, 0x00 },
  616. { WCD9335_CPE_SS_OUTBOX2_13, 0x00 },
  617. { WCD9335_CPE_SS_OUTBOX2_14, 0x00 },
  618. { WCD9335_CPE_SS_OUTBOX2_15, 0x00 },
  619. { WCD9335_CPE_SS_OUTBOX1_ACK, 0x00 },
  620. { WCD9335_CPE_SS_OUTBOX2_ACK, 0x00 },
  621. { WCD9335_CPE_SS_EC_BUF_INT_PERIOD, 0x3c },
  622. { WCD9335_CPE_SS_US_BUF_INT_PERIOD, 0x60 },
  623. { WCD9335_CPE_SS_CFG, 0x41 },
  624. { WCD9335_CPE_SS_US_EC_MUX_CFG, 0x00 },
  625. { WCD9335_CPE_SS_MAD_CTL, 0x00 },
  626. { WCD9335_CPE_SS_CPAR_CTL, 0x00 },
  627. { WCD9335_CPE_SS_DMIC0_CTL, 0x00 },
  628. { WCD9335_CPE_SS_DMIC1_CTL, 0x00 },
  629. { WCD9335_CPE_SS_DMIC2_CTL, 0x00 },
  630. { WCD9335_CPE_SS_DMIC_CFG, 0x80 },
  631. { WCD9335_CPE_SS_CPAR_CFG, 0x00 },
  632. { WCD9335_CPE_SS_WDOG_CFG, 0x01 },
  633. { WCD9335_CPE_SS_BACKUP_INT, 0x00 },
  634. { WCD9335_CPE_SS_STATUS, 0x00 },
  635. { WCD9335_CPE_SS_CPE_OCD_CFG, 0x00 },
  636. { WCD9335_CPE_SS_SS_ERROR_INT_STATUS, 0x00 },
  637. { WCD9335_CPE_SS_SS_ERROR_INT_CLEAR, 0x00 },
  638. { WCD9335_SOC_MAD_MAIN_CTL_1, 0x00 },
  639. { WCD9335_SOC_MAD_MAIN_CTL_2, 0x00 },
  640. { WCD9335_SOC_MAD_AUDIO_CTL_1, 0x00 },
  641. { WCD9335_SOC_MAD_AUDIO_CTL_2, 0x00 },
  642. { WCD9335_SOC_MAD_AUDIO_CTL_3, 0x00 },
  643. { WCD9335_SOC_MAD_AUDIO_CTL_4, 0x00 },
  644. { WCD9335_SOC_MAD_AUDIO_CTL_5, 0x00 },
  645. { WCD9335_SOC_MAD_AUDIO_CTL_6, 0x00 },
  646. { WCD9335_SOC_MAD_AUDIO_CTL_7, 0x00 },
  647. { WCD9335_SOC_MAD_AUDIO_CTL_8, 0x00 },
  648. { WCD9335_SOC_MAD_AUDIO_IIR_CTL_PTR, 0x00 },
  649. { WCD9335_SOC_MAD_ULTR_CTL_1, 0x00 },
  650. { WCD9335_SOC_MAD_ULTR_CTL_2, 0x00 },
  651. { WCD9335_SOC_MAD_ULTR_CTL_3, 0x00 },
  652. { WCD9335_SOC_MAD_ULTR_CTL_4, 0x00 },
  653. { WCD9335_SOC_MAD_ULTR_CTL_5, 0x00 },
  654. { WCD9335_SOC_MAD_ULTR_CTL_6, 0x00 },
  655. { WCD9335_SOC_MAD_ULTR_CTL_7, 0x00 },
  656. { WCD9335_SOC_MAD_BEACON_CTL_1, 0x00 },
  657. { WCD9335_SOC_MAD_BEACON_CTL_2, 0x00 },
  658. { WCD9335_SOC_MAD_BEACON_CTL_3, 0x00 },
  659. { WCD9335_SOC_MAD_BEACON_CTL_4, 0x00 },
  660. { WCD9335_SOC_MAD_BEACON_CTL_5, 0x00 },
  661. { WCD9335_SOC_MAD_BEACON_CTL_6, 0x00 },
  662. { WCD9335_SOC_MAD_BEACON_CTL_7, 0x00 },
  663. { WCD9335_SOC_MAD_BEACON_CTL_8, 0x00 },
  664. { WCD9335_SOC_MAD_BEACON_IIR_CTL_PTR, 0x00 },
  665. { WCD9335_SOC_MAD_BEACON_IIR_CTL_VAL, 0x00 },
  666. { WCD9335_SOC_MAD_INP_SEL, 0x00 },
  667. /* Page #6 registers */
  668. { WCD9335_PAGE6_PAGE_REGISTER, 0x00 },
  669. { WCD9335_ANA_BIAS, 0x00 },
  670. { WCD9335_ANA_CLK_TOP, 0x00 },
  671. { WCD9335_ANA_RCO, 0x30 },
  672. { WCD9335_ANA_BUCK_VOUT_A, 0xb4 },
  673. { WCD9335_ANA_BUCK_VOUT_D, 0xb4 },
  674. { WCD9335_ANA_BUCK_CTL, 0x00 },
  675. { WCD9335_ANA_BUCK_STATUS, 0xe0 },
  676. { WCD9335_ANA_RX_SUPPLIES, 0x00 },
  677. { WCD9335_ANA_HPH, 0x00 },
  678. { WCD9335_ANA_EAR, 0x00 },
  679. { WCD9335_ANA_LO_1_2, 0x00 },
  680. { WCD9335_ANA_LO_3_4, 0x00 },
  681. { WCD9335_ANA_MAD_SETUP, 0x81 },
  682. { WCD9335_ANA_AMIC1, 0x20 },
  683. { WCD9335_ANA_AMIC2, 0x00 },
  684. { WCD9335_ANA_AMIC3, 0x20 },
  685. { WCD9335_ANA_AMIC4, 0x00 },
  686. { WCD9335_ANA_AMIC5, 0x20 },
  687. { WCD9335_ANA_AMIC6, 0x00 },
  688. { WCD9335_ANA_MBHC_MECH, 0x39 },
  689. { WCD9335_ANA_MBHC_ELECT, 0x08 },
  690. { WCD9335_ANA_MBHC_ZDET, 0x00 },
  691. { WCD9335_ANA_MBHC_RESULT_1, 0x00 },
  692. { WCD9335_ANA_MBHC_RESULT_2, 0x00 },
  693. { WCD9335_ANA_MBHC_RESULT_3, 0x00 },
  694. { WCD9335_ANA_MBHC_BTN0, 0x00 },
  695. { WCD9335_ANA_MBHC_BTN1, 0x10 },
  696. { WCD9335_ANA_MBHC_BTN2, 0x20 },
  697. { WCD9335_ANA_MBHC_BTN3, 0x30 },
  698. { WCD9335_ANA_MBHC_BTN4, 0x40 },
  699. { WCD9335_ANA_MBHC_BTN5, 0x50 },
  700. { WCD9335_ANA_MBHC_BTN6, 0x60 },
  701. { WCD9335_ANA_MBHC_BTN7, 0x70 },
  702. { WCD9335_ANA_MICB1, 0x10 },
  703. { WCD9335_ANA_MICB2, 0x10 },
  704. { WCD9335_ANA_MICB2_RAMP, 0x00 },
  705. { WCD9335_ANA_MICB3, 0x10 },
  706. { WCD9335_ANA_MICB4, 0x10 },
  707. { WCD9335_ANA_VBADC, 0x00 },
  708. { WCD9335_BIAS_CTL, 0x28 },
  709. { WCD9335_CLOCK_TEST_CTL, 0x00 },
  710. { WCD9335_RCO_CTRL_1, 0x44 },
  711. { WCD9335_RCO_CTRL_2, 0x44 },
  712. { WCD9335_RCO_CAL, 0x00 },
  713. { WCD9335_RCO_CAL_1, 0x00 },
  714. { WCD9335_RCO_CAL_2, 0x00 },
  715. { WCD9335_RCO_TEST_CTRL, 0x00 },
  716. { WCD9335_RCO_CAL_OUT_1, 0x00 },
  717. { WCD9335_RCO_CAL_OUT_2, 0x00 },
  718. { WCD9335_RCO_CAL_OUT_3, 0x00 },
  719. { WCD9335_RCO_CAL_OUT_4, 0x00 },
  720. { WCD9335_RCO_CAL_OUT_5, 0x00 },
  721. { WCD9335_SIDO_SIDO_MODE_1, 0x84 },
  722. { WCD9335_SIDO_SIDO_MODE_2, 0xfe },
  723. { WCD9335_SIDO_SIDO_MODE_3, 0xf6 },
  724. { WCD9335_SIDO_SIDO_MODE_4, 0x56 },
  725. { WCD9335_SIDO_SIDO_VCL_1, 0x00 },
  726. { WCD9335_SIDO_SIDO_VCL_2, 0x6c },
  727. { WCD9335_SIDO_SIDO_VCL_3, 0x44 },
  728. { WCD9335_SIDO_SIDO_CCL_1, 0x57 },
  729. { WCD9335_SIDO_SIDO_CCL_4, 0x61 },
  730. { WCD9335_SIDO_SIDO_CCL_5, 0x6d },
  731. { WCD9335_SIDO_SIDO_CCL_6, 0x60 },
  732. { WCD9335_SIDO_SIDO_CCL_7, 0x6f },
  733. { WCD9335_SIDO_SIDO_CCL_9, 0x6e },
  734. { WCD9335_SIDO_SIDO_FILTER_1, 0x92 },
  735. { WCD9335_SIDO_SIDO_FILTER_2, 0x54 },
  736. { WCD9335_SIDO_SIDO_DRIVER_1, 0x77 },
  737. { WCD9335_SIDO_SIDO_CAL_CODE_EXT_1, 0x9c },
  738. { WCD9335_SIDO_SIDO_CAL_CODE_EXT_2, 0x82 },
  739. { WCD9335_SIDO_SIDO_CAL_CODE_OUT_1, 0x00 },
  740. { WCD9335_SIDO_SIDO_CAL_CODE_OUT_2, 0x00 },
  741. { WCD9335_SIDO_SIDO_TEST_1, 0x00 },
  742. { WCD9335_MBHC_CTL_1, 0x32 },
  743. { WCD9335_MBHC_CTL_2, 0x01 },
  744. { WCD9335_MBHC_PLUG_DETECT_CTL, 0x69 },
  745. { WCD9335_MBHC_ZDET_RAMP_CTL, 0x00 },
  746. { WCD9335_MBHC_TEST_CTL, 0x00 },
  747. { WCD9335_VBADC_SUBBLOCK_EN, 0xfe },
  748. { WCD9335_VBADC_IBIAS_FE, 0x54 },
  749. { WCD9335_VBADC_BIAS_ADC, 0x51 },
  750. { WCD9335_VBADC_FE_CTRL, 0x1c },
  751. { WCD9335_VBADC_ADC_REF, 0x20 },
  752. { WCD9335_VBADC_ADC_IO, 0x80 },
  753. { WCD9335_VBADC_ADC_SAR, 0xff },
  754. { WCD9335_VBADC_DEBUG, 0x00 },
  755. { WCD9335_VBADC_ADC_DOUTMSB, 0x00 },
  756. { WCD9335_VBADC_ADC_DOUTLSB, 0x00 },
  757. { WCD9335_LDOH_MODE, 0x2b },
  758. { WCD9335_LDOH_BIAS, 0x68 },
  759. { WCD9335_LDOH_STB_LOADS, 0x00 },
  760. { WCD9335_LDOH_SLOWRAMP, 0x50 },
  761. { WCD9335_MICB1_TEST_CTL_1, 0x1a },
  762. { WCD9335_MICB1_TEST_CTL_2, 0x18 },
  763. { WCD9335_MICB1_TEST_CTL_3, 0xa4 },
  764. { WCD9335_MICB2_TEST_CTL_1, 0x1a },
  765. { WCD9335_MICB2_TEST_CTL_2, 0x18 },
  766. { WCD9335_MICB2_TEST_CTL_3, 0x24 },
  767. { WCD9335_MICB3_TEST_CTL_1, 0x1a },
  768. { WCD9335_MICB3_TEST_CTL_2, 0x18 },
  769. { WCD9335_MICB3_TEST_CTL_3, 0xa4 },
  770. { WCD9335_MICB4_TEST_CTL_1, 0x1a },
  771. { WCD9335_MICB4_TEST_CTL_2, 0x18 },
  772. { WCD9335_MICB4_TEST_CTL_3, 0xa4 },
  773. { WCD9335_TX_COM_ADC_VCM, 0x39 },
  774. { WCD9335_TX_COM_BIAS_ATEST, 0xc0 },
  775. { WCD9335_TX_COM_ADC_INT1_IB, 0x6f },
  776. { WCD9335_TX_COM_ADC_INT2_IB, 0x4f },
  777. { WCD9335_TX_COM_TXFE_DIV_CTL, 0x2e },
  778. { WCD9335_TX_COM_TXFE_DIV_START, 0x00 },
  779. { WCD9335_TX_COM_TXFE_DIV_STOP_9P6M, 0xc7 },
  780. { WCD9335_TX_COM_TXFE_DIV_STOP_12P288M, 0xff },
  781. { WCD9335_TX_1_2_TEST_EN, 0xcc },
  782. { WCD9335_TX_1_2_ADC_IB, 0x09 },
  783. { WCD9335_TX_1_2_TEST_CTL, 0x38 },
  784. { WCD9335_TX_1_2_TEST_BLK_EN, 0xff },
  785. { WCD9335_TX_1_2_TXFE_CLKDIV, 0x00 },
  786. { WCD9335_TX_1_2_SAR1_ERR, 0x00 },
  787. { WCD9335_TX_1_2_SAR2_ERR, 0x00 },
  788. { WCD9335_TX_3_4_TEST_EN, 0xcc },
  789. { WCD9335_TX_3_4_ADC_IB, 0x09 },
  790. { WCD9335_TX_3_4_TEST_CTL, 0x38 },
  791. { WCD9335_TX_3_4_TEST_BLK_EN, 0xff },
  792. { WCD9335_TX_3_4_TXFE_CLKDIV, 0x00 },
  793. { WCD9335_TX_3_4_SAR1_ERR, 0x00 },
  794. { WCD9335_TX_3_4_SAR2_ERR, 0x00 },
  795. { WCD9335_TX_5_6_TEST_EN, 0xcc },
  796. { WCD9335_TX_5_6_ADC_IB, 0x09 },
  797. { WCD9335_TX_5_6_TEST_CTL, 0x38 },
  798. { WCD9335_TX_5_6_TEST_BLK_EN, 0xff },
  799. { WCD9335_TX_5_6_TXFE_CLKDIV, 0x00 },
  800. { WCD9335_TX_5_6_SAR1_ERR, 0x00 },
  801. { WCD9335_TX_5_6_SAR2_ERR, 0x00 },
  802. { WCD9335_CLASSH_MODE_1, 0x40 },
  803. { WCD9335_CLASSH_MODE_2, 0x3a },
  804. { WCD9335_CLASSH_MODE_3, 0x00 },
  805. { WCD9335_CLASSH_CTRL_VCL_1, 0x70 },
  806. { WCD9335_CLASSH_CTRL_VCL_2, 0xa2 },
  807. { WCD9335_CLASSH_CTRL_CCL_1, 0x51 },
  808. { WCD9335_CLASSH_CTRL_CCL_2, 0x80 },
  809. { WCD9335_CLASSH_CTRL_CCL_3, 0x80 },
  810. { WCD9335_CLASSH_CTRL_CCL_4, 0x51 },
  811. { WCD9335_CLASSH_CTRL_CCL_5, 0x00 },
  812. { WCD9335_CLASSH_BUCK_TMUX_A_D, 0x00 },
  813. { WCD9335_CLASSH_BUCK_SW_DRV_CNTL, 0x77 },
  814. { WCD9335_CLASSH_SPARE, 0x00 },
  815. { WCD9335_FLYBACK_EN, 0x4e },
  816. { WCD9335_FLYBACK_VNEG_CTRL_2, 0x45 },
  817. { WCD9335_FLYBACK_VNEG_CTRL_3, 0x74 },
  818. { WCD9335_FLYBACK_VNEG_CTRL_5, 0x83 },
  819. { WCD9335_FLYBACK_VNEG_CTRL_6, 0x98 },
  820. { WCD9335_FLYBACK_VNEG_CTRL_7, 0xa9 },
  821. { WCD9335_FLYBACK_VNEG_CTRL_8, 0x68 },
  822. { WCD9335_FLYBACK_VNEG_DAC_CTRL_2, 0x50 },
  823. { WCD9335_FLYBACK_VNEG_DAC_CTRL_3, 0xa6 },
  824. { WCD9335_FLYBACK_TEST_CTL, 0x00 },
  825. { WCD9335_RX_AUX_SW_CTL, 0x00 },
  826. { WCD9335_RX_PA_AUX_IN_CONN, 0x00 },
  827. { WCD9335_RX_TIMER_DIV, 0x74 },
  828. { WCD9335_RX_OCP_CTL, 0x1f },
  829. { WCD9335_RX_OCP_COUNT, 0x77 },
  830. { WCD9335_RX_BIAS_EAR_DAC, 0xa0 },
  831. { WCD9335_RX_BIAS_EAR_AMP, 0xaa },
  832. { WCD9335_RX_BIAS_HPH_LDO, 0xa9 },
  833. { WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8a },
  834. { WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x88 },
  835. { WCD9335_RX_BIAS_HPH_CNP1, 0x86 },
  836. { WCD9335_RX_BIAS_DIFFLO_PA, 0x80 },
  837. { WCD9335_RX_BIAS_DIFFLO_REF, 0x88 },
  838. { WCD9335_RX_BIAS_DIFFLO_LDO, 0x88 },
  839. { WCD9335_RX_BIAS_SELO_DAC_PA, 0xa8 },
  840. { WCD9335_RX_BIAS_BUCK_RST, 0x08 },
  841. { WCD9335_RX_BIAS_BUCK_VREF_ERRAMP, 0x44 },
  842. { WCD9335_RX_BIAS_FLYB_ERRAMP, 0x40 },
  843. { WCD9335_RX_BIAS_FLYB_BUFF, 0xaa },
  844. { WCD9335_RX_BIAS_FLYB_MID_RST, 0x44 },
  845. { WCD9335_HPH_L_STATUS, 0x04 },
  846. { WCD9335_HPH_R_STATUS, 0x04 },
  847. { WCD9335_HPH_CNP_EN, 0x80 },
  848. { WCD9335_HPH_CNP_WG_CTL, 0xda },
  849. { WCD9335_HPH_CNP_WG_TIME, 0x15 },
  850. { WCD9335_HPH_OCP_CTL, 0x28 },
  851. { WCD9335_HPH_AUTO_CHOP, 0x12 },
  852. { WCD9335_HPH_CHOP_CTL, 0x83 },
  853. { WCD9335_HPH_PA_CTL1, 0x46 },
  854. { WCD9335_HPH_L_TEST, 0x00 },
  855. { WCD9335_HPH_L_ATEST, 0x50 },
  856. { WCD9335_HPH_R_TEST, 0x00 },
  857. { WCD9335_HPH_RDAC_CLK_CTL1, 0x99 },
  858. { WCD9335_HPH_RDAC_CLK_CTL2, 0x9b },
  859. { WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00 },
  860. { WCD9335_HPH_REFBUFF_UHQA_CTL, 0xa8 },
  861. { WCD9335_HPH_REFBUFF_LP_CTL, 0x00 },
  862. { WCD9335_HPH_L_DAC_CTL, 0x00 },
  863. { WCD9335_HPH_R_DAC_CTL, 0x00 },
  864. { WCD9335_EAR_EN_REG, 0x60 },
  865. { WCD9335_EAR_CMBUFF, 0x0d },
  866. { WCD9335_EAR_ICTL, 0x40 },
  867. { WCD9335_EAR_EN_DBG_CTL, 0x00 },
  868. { WCD9335_EAR_CNP, 0xe0 },
  869. { WCD9335_EAR_DAC_CTL_ATEST, 0x00 },
  870. { WCD9335_EAR_STATUS_REG, 0x04 },
  871. { WCD9335_EAR_OUT_SHORT, 0x00 },
  872. { WCD9335_DIFF_LO_MISC, 0x03 },
  873. { WCD9335_DIFF_LO_LO2_COMPANDER, 0x00 },
  874. { WCD9335_DIFF_LO_LO1_COMPANDER, 0x00 },
  875. { WCD9335_DIFF_LO_COMMON, 0x40 },
  876. { WCD9335_DIFF_LO_BYPASS_EN, 0x00 },
  877. { WCD9335_DIFF_LO_CNP, 0x20 },
  878. { WCD9335_DIFF_LO_CORE_OUT_PROG, 0x00 },
  879. { WCD9335_DIFF_LO_LDO_OUT_PROG, 0x00 },
  880. { WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x9b },
  881. { WCD9335_DIFF_LO_COM_PA_FREQ, 0xb0 },
  882. { WCD9335_DIFF_LO_RESERVED_REG, 0x60 },
  883. { WCD9335_DIFF_LO_LO1_STATUS_1, 0x00 },
  884. { WCD9335_DIFF_LO_LO1_STATUS_2, 0x00 },
  885. { WCD9335_SE_LO_COM1, 0x80 },
  886. { WCD9335_SE_LO_COM2, 0x04 },
  887. { WCD9335_SE_LO_LO3_GAIN, 0x20 },
  888. { WCD9335_SE_LO_LO3_CTRL, 0x04 },
  889. { WCD9335_SE_LO_LO4_GAIN, 0x20 },
  890. { WCD9335_SE_LO_LO4_CTRL, 0x04 },
  891. { WCD9335_SE_LO_LO3_STATUS, 0x00 },
  892. { WCD9335_SE_LO_LO4_STATUS, 0x00 },
  893. /* Page #10 registers */
  894. { WCD9335_PAGE10_PAGE_REGISTER, 0x00 },
  895. { WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x00 },
  896. { WCD9335_CDC_ANC0_MODE_1_CTL, 0x00 },
  897. { WCD9335_CDC_ANC0_MODE_2_CTL, 0x00 },
  898. { WCD9335_CDC_ANC0_FF_SHIFT, 0x00 },
  899. { WCD9335_CDC_ANC0_FB_SHIFT, 0x00 },
  900. { WCD9335_CDC_ANC0_LPF_FF_A_CTL, 0x00 },
  901. { WCD9335_CDC_ANC0_LPF_FF_B_CTL, 0x00 },
  902. { WCD9335_CDC_ANC0_LPF_FB_CTL, 0x00 },
  903. { WCD9335_CDC_ANC0_SMLPF_CTL, 0x00 },
  904. { WCD9335_CDC_ANC0_DCFLT_SHIFT_CTL, 0x00 },
  905. { WCD9335_CDC_ANC0_IIR_ADAPT_CTL, 0x00 },
  906. { WCD9335_CDC_ANC0_IIR_COEFF_1_CTL, 0x00 },
  907. { WCD9335_CDC_ANC0_IIR_COEFF_2_CTL, 0x00 },
  908. { WCD9335_CDC_ANC0_FF_A_GAIN_CTL, 0x00 },
  909. { WCD9335_CDC_ANC0_FF_B_GAIN_CTL, 0x00 },
  910. { WCD9335_CDC_ANC0_FB_GAIN_CTL, 0x00 },
  911. { WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x00 },
  912. { WCD9335_CDC_ANC1_MODE_1_CTL, 0x00 },
  913. { WCD9335_CDC_ANC1_MODE_2_CTL, 0x00 },
  914. { WCD9335_CDC_ANC1_FF_SHIFT, 0x00 },
  915. { WCD9335_CDC_ANC1_FB_SHIFT, 0x00 },
  916. { WCD9335_CDC_ANC1_LPF_FF_A_CTL, 0x00 },
  917. { WCD9335_CDC_ANC1_LPF_FF_B_CTL, 0x00 },
  918. { WCD9335_CDC_ANC1_LPF_FB_CTL, 0x00 },
  919. { WCD9335_CDC_ANC1_SMLPF_CTL, 0x00 },
  920. { WCD9335_CDC_ANC1_DCFLT_SHIFT_CTL, 0x00 },
  921. { WCD9335_CDC_ANC1_IIR_ADAPT_CTL, 0x00 },
  922. { WCD9335_CDC_ANC1_IIR_COEFF_1_CTL, 0x00 },
  923. { WCD9335_CDC_ANC1_IIR_COEFF_2_CTL, 0x00 },
  924. { WCD9335_CDC_ANC1_FF_A_GAIN_CTL, 0x00 },
  925. { WCD9335_CDC_ANC1_FF_B_GAIN_CTL, 0x00 },
  926. { WCD9335_CDC_ANC1_FB_GAIN_CTL, 0x00 },
  927. { WCD9335_CDC_TX0_TX_PATH_CTL, 0x04 },
  928. { WCD9335_CDC_TX0_TX_VOL_CTL, 0x00 },
  929. { WCD9335_CDC_TX0_TX_PATH_192_CTL, 0x00 },
  930. { WCD9335_CDC_TX0_TX_PATH_192_CFG, 0x00 },
  931. { WCD9335_CDC_TX0_TX_PATH_SEC0, 0x00 },
  932. { WCD9335_CDC_TX0_TX_PATH_SEC1, 0x00 },
  933. { WCD9335_CDC_TX0_TX_PATH_SEC4, 0x20 },
  934. { WCD9335_CDC_TX0_TX_PATH_SEC5, 0x00 },
  935. { WCD9335_CDC_TX0_TX_PATH_SEC6, 0x00 },
  936. { WCD9335_CDC_TX1_TX_PATH_CTL, 0x04 },
  937. { WCD9335_CDC_TX1_TX_VOL_CTL, 0x00 },
  938. { WCD9335_CDC_TX1_TX_PATH_192_CTL, 0x00 },
  939. { WCD9335_CDC_TX1_TX_PATH_192_CFG, 0x00 },
  940. { WCD9335_CDC_TX1_TX_PATH_SEC0, 0x00 },
  941. { WCD9335_CDC_TX1_TX_PATH_SEC1, 0x00 },
  942. { WCD9335_CDC_TX1_TX_PATH_SEC4, 0x20 },
  943. { WCD9335_CDC_TX1_TX_PATH_SEC5, 0x00 },
  944. { WCD9335_CDC_TX1_TX_PATH_SEC6, 0x00 },
  945. { WCD9335_CDC_TX2_TX_PATH_CTL, 0x04 },
  946. { WCD9335_CDC_TX2_TX_VOL_CTL, 0x00 },
  947. { WCD9335_CDC_TX2_TX_PATH_192_CTL, 0x00 },
  948. { WCD9335_CDC_TX2_TX_PATH_192_CFG, 0x00 },
  949. { WCD9335_CDC_TX2_TX_PATH_SEC0, 0x00 },
  950. { WCD9335_CDC_TX2_TX_PATH_SEC1, 0x00 },
  951. { WCD9335_CDC_TX2_TX_PATH_SEC4, 0x20 },
  952. { WCD9335_CDC_TX2_TX_PATH_SEC5, 0x00 },
  953. { WCD9335_CDC_TX2_TX_PATH_SEC6, 0x00 },
  954. { WCD9335_CDC_TX3_TX_PATH_CTL, 0x04 },
  955. { WCD9335_CDC_TX3_TX_VOL_CTL, 0x00 },
  956. { WCD9335_CDC_TX3_TX_PATH_192_CTL, 0x00 },
  957. { WCD9335_CDC_TX3_TX_PATH_192_CFG, 0x00 },
  958. { WCD9335_CDC_TX3_TX_PATH_SEC0, 0x00 },
  959. { WCD9335_CDC_TX3_TX_PATH_SEC1, 0x00 },
  960. { WCD9335_CDC_TX3_TX_PATH_SEC4, 0x20 },
  961. { WCD9335_CDC_TX3_TX_PATH_SEC5, 0x00 },
  962. { WCD9335_CDC_TX3_TX_PATH_SEC6, 0x00 },
  963. { WCD9335_CDC_TX4_TX_PATH_CTL, 0x04 },
  964. { WCD9335_CDC_TX4_TX_VOL_CTL, 0x00 },
  965. { WCD9335_CDC_TX4_TX_PATH_192_CTL, 0x00 },
  966. { WCD9335_CDC_TX4_TX_PATH_192_CFG, 0x00 },
  967. { WCD9335_CDC_TX4_TX_PATH_SEC0, 0x00 },
  968. { WCD9335_CDC_TX4_TX_PATH_SEC1, 0x00 },
  969. { WCD9335_CDC_TX4_TX_PATH_SEC4, 0x20 },
  970. { WCD9335_CDC_TX4_TX_PATH_SEC5, 0x00 },
  971. { WCD9335_CDC_TX4_TX_PATH_SEC6, 0x00 },
  972. { WCD9335_CDC_TX5_TX_PATH_CTL, 0x04 },
  973. { WCD9335_CDC_TX5_TX_VOL_CTL, 0x00 },
  974. { WCD9335_CDC_TX5_TX_PATH_192_CTL, 0x00 },
  975. { WCD9335_CDC_TX5_TX_PATH_192_CFG, 0x00 },
  976. { WCD9335_CDC_TX5_TX_PATH_SEC0, 0x00 },
  977. { WCD9335_CDC_TX5_TX_PATH_SEC1, 0x00 },
  978. { WCD9335_CDC_TX5_TX_PATH_SEC4, 0x20 },
  979. { WCD9335_CDC_TX5_TX_PATH_SEC5, 0x00 },
  980. { WCD9335_CDC_TX5_TX_PATH_SEC6, 0x00 },
  981. { WCD9335_CDC_TX6_TX_PATH_CTL, 0x04 },
  982. { WCD9335_CDC_TX6_TX_VOL_CTL, 0x00 },
  983. { WCD9335_CDC_TX6_TX_PATH_192_CTL, 0x00 },
  984. { WCD9335_CDC_TX6_TX_PATH_192_CFG, 0x00 },
  985. { WCD9335_CDC_TX6_TX_PATH_SEC0, 0x00 },
  986. { WCD9335_CDC_TX6_TX_PATH_SEC1, 0x00 },
  987. { WCD9335_CDC_TX6_TX_PATH_SEC4, 0x20 },
  988. { WCD9335_CDC_TX6_TX_PATH_SEC5, 0x00 },
  989. { WCD9335_CDC_TX6_TX_PATH_SEC6, 0x00 },
  990. { WCD9335_CDC_TX7_TX_PATH_CTL, 0x04 },
  991. { WCD9335_CDC_TX7_TX_VOL_CTL, 0x00 },
  992. { WCD9335_CDC_TX7_TX_PATH_192_CTL, 0x00 },
  993. { WCD9335_CDC_TX7_TX_PATH_192_CFG, 0x00 },
  994. { WCD9335_CDC_TX7_TX_PATH_SEC0, 0x00 },
  995. { WCD9335_CDC_TX7_TX_PATH_SEC1, 0x00 },
  996. { WCD9335_CDC_TX7_TX_PATH_SEC4, 0x20 },
  997. { WCD9335_CDC_TX7_TX_PATH_SEC5, 0x00 },
  998. { WCD9335_CDC_TX7_TX_PATH_SEC6, 0x00 },
  999. { WCD9335_CDC_TX8_TX_PATH_CTL, 0x04 },
  1000. { WCD9335_CDC_TX8_TX_VOL_CTL, 0x00 },
  1001. { WCD9335_CDC_TX8_TX_PATH_192_CTL, 0x00 },
  1002. { WCD9335_CDC_TX8_TX_PATH_192_CFG, 0x00 },
  1003. { WCD9335_CDC_TX8_TX_PATH_SEC0, 0x00 },
  1004. { WCD9335_CDC_TX8_TX_PATH_SEC1, 0x00 },
  1005. { WCD9335_CDC_TX8_TX_PATH_SEC4, 0x20 },
  1006. { WCD9335_CDC_TX8_TX_PATH_SEC5, 0x00 },
  1007. { WCD9335_CDC_TX8_TX_PATH_SEC6, 0x00 },
  1008. { WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x02 },
  1009. { WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x00 },
  1010. { WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x02 },
  1011. { WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x00 },
  1012. { WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x02 },
  1013. { WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x00 },
  1014. { WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x02 },
  1015. { WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x00 },
  1016. /* Page #11 registers */
  1017. { WCD9335_PAGE11_PAGE_REGISTER, 0x00 },
  1018. { WCD9335_CDC_COMPANDER1_CTL0, 0x60 },
  1019. { WCD9335_CDC_COMPANDER1_CTL1, 0xdb },
  1020. { WCD9335_CDC_COMPANDER1_CTL2, 0xff },
  1021. { WCD9335_CDC_COMPANDER1_CTL3, 0x35 },
  1022. { WCD9335_CDC_COMPANDER1_CTL4, 0xff },
  1023. { WCD9335_CDC_COMPANDER1_CTL5, 0x00 },
  1024. { WCD9335_CDC_COMPANDER1_CTL6, 0x01 },
  1025. { WCD9335_CDC_COMPANDER2_CTL0, 0x60 },
  1026. { WCD9335_CDC_COMPANDER2_CTL1, 0xdb },
  1027. { WCD9335_CDC_COMPANDER2_CTL2, 0xff },
  1028. { WCD9335_CDC_COMPANDER2_CTL3, 0x35 },
  1029. { WCD9335_CDC_COMPANDER2_CTL4, 0xff },
  1030. { WCD9335_CDC_COMPANDER2_CTL5, 0x00 },
  1031. { WCD9335_CDC_COMPANDER2_CTL6, 0x01 },
  1032. { WCD9335_CDC_COMPANDER3_CTL0, 0x60 },
  1033. { WCD9335_CDC_COMPANDER3_CTL1, 0xdb },
  1034. { WCD9335_CDC_COMPANDER3_CTL2, 0xff },
  1035. { WCD9335_CDC_COMPANDER3_CTL3, 0x35 },
  1036. { WCD9335_CDC_COMPANDER3_CTL4, 0xff },
  1037. { WCD9335_CDC_COMPANDER3_CTL5, 0x00 },
  1038. { WCD9335_CDC_COMPANDER3_CTL6, 0x01 },
  1039. { WCD9335_CDC_COMPANDER4_CTL0, 0x60 },
  1040. { WCD9335_CDC_COMPANDER4_CTL1, 0xdb },
  1041. { WCD9335_CDC_COMPANDER4_CTL2, 0xff },
  1042. { WCD9335_CDC_COMPANDER4_CTL3, 0x35 },
  1043. { WCD9335_CDC_COMPANDER4_CTL4, 0xff },
  1044. { WCD9335_CDC_COMPANDER4_CTL5, 0x00 },
  1045. { WCD9335_CDC_COMPANDER4_CTL6, 0x01 },
  1046. { WCD9335_CDC_COMPANDER5_CTL0, 0x60 },
  1047. { WCD9335_CDC_COMPANDER5_CTL1, 0xdb },
  1048. { WCD9335_CDC_COMPANDER5_CTL2, 0xff },
  1049. { WCD9335_CDC_COMPANDER5_CTL3, 0x35 },
  1050. { WCD9335_CDC_COMPANDER5_CTL4, 0xff },
  1051. { WCD9335_CDC_COMPANDER5_CTL5, 0x00 },
  1052. { WCD9335_CDC_COMPANDER5_CTL6, 0x01 },
  1053. { WCD9335_CDC_COMPANDER6_CTL0, 0x60 },
  1054. { WCD9335_CDC_COMPANDER6_CTL1, 0xdb },
  1055. { WCD9335_CDC_COMPANDER6_CTL2, 0xff },
  1056. { WCD9335_CDC_COMPANDER6_CTL3, 0x35 },
  1057. { WCD9335_CDC_COMPANDER6_CTL4, 0xff },
  1058. { WCD9335_CDC_COMPANDER6_CTL5, 0x00 },
  1059. { WCD9335_CDC_COMPANDER6_CTL6, 0x01 },
  1060. { WCD9335_CDC_COMPANDER7_CTL0, 0x60 },
  1061. { WCD9335_CDC_COMPANDER7_CTL1, 0xdb },
  1062. { WCD9335_CDC_COMPANDER7_CTL2, 0xff },
  1063. { WCD9335_CDC_COMPANDER7_CTL3, 0x35 },
  1064. { WCD9335_CDC_COMPANDER7_CTL4, 0xff },
  1065. { WCD9335_CDC_COMPANDER7_CTL5, 0x00 },
  1066. { WCD9335_CDC_COMPANDER7_CTL6, 0x01 },
  1067. { WCD9335_CDC_COMPANDER8_CTL0, 0x60 },
  1068. { WCD9335_CDC_COMPANDER8_CTL1, 0xdb },
  1069. { WCD9335_CDC_COMPANDER8_CTL2, 0xff },
  1070. { WCD9335_CDC_COMPANDER8_CTL3, 0x35 },
  1071. { WCD9335_CDC_COMPANDER8_CTL4, 0xff },
  1072. { WCD9335_CDC_COMPANDER8_CTL5, 0x00 },
  1073. { WCD9335_CDC_COMPANDER8_CTL6, 0x01 },
  1074. { WCD9335_CDC_RX0_RX_PATH_CTL, 0x04 },
  1075. { WCD9335_CDC_RX0_RX_PATH_CFG0, 0x00 },
  1076. { WCD9335_CDC_RX0_RX_PATH_CFG2, 0x8f },
  1077. { WCD9335_CDC_RX0_RX_VOL_CTL, 0x00 },
  1078. { WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 0x04 },
  1079. { WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 0x00 },
  1080. { WCD9335_CDC_RX0_RX_PATH_SEC2, 0x00 },
  1081. { WCD9335_CDC_RX0_RX_PATH_SEC3, 0x00 },
  1082. { WCD9335_CDC_RX0_RX_PATH_SEC5, 0x00 },
  1083. { WCD9335_CDC_RX0_RX_PATH_SEC6, 0x00 },
  1084. { WCD9335_CDC_RX0_RX_PATH_SEC7, 0x00 },
  1085. { WCD9335_CDC_RX0_RX_PATH_MIX_SEC1, 0x00 },
  1086. { WCD9335_CDC_RX1_RX_PATH_CTL, 0x04 },
  1087. { WCD9335_CDC_RX1_RX_PATH_CFG0, 0x00 },
  1088. { WCD9335_CDC_RX1_RX_PATH_CFG2, 0x8f },
  1089. { WCD9335_CDC_RX1_RX_VOL_CTL, 0x00 },
  1090. { WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 0x04 },
  1091. { WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 0x00 },
  1092. { WCD9335_CDC_RX1_RX_PATH_SEC2, 0x00 },
  1093. { WCD9335_CDC_RX1_RX_PATH_SEC3, 0x00 },
  1094. { WCD9335_CDC_RX1_RX_PATH_SEC4, 0x00 },
  1095. { WCD9335_CDC_RX1_RX_PATH_SEC5, 0x00 },
  1096. { WCD9335_CDC_RX1_RX_PATH_SEC6, 0x00 },
  1097. { WCD9335_CDC_RX1_RX_PATH_SEC7, 0x00 },
  1098. { WCD9335_CDC_RX1_RX_PATH_MIX_SEC1, 0x00 },
  1099. { WCD9335_CDC_RX2_RX_PATH_CTL, 0x04 },
  1100. { WCD9335_CDC_RX2_RX_PATH_CFG0, 0x00 },
  1101. { WCD9335_CDC_RX2_RX_PATH_CFG2, 0x8f },
  1102. { WCD9335_CDC_RX2_RX_VOL_CTL, 0x00 },
  1103. { WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 0x04 },
  1104. { WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 0x00 },
  1105. { WCD9335_CDC_RX2_RX_PATH_SEC2, 0x00 },
  1106. { WCD9335_CDC_RX2_RX_PATH_SEC3, 0x00 },
  1107. { WCD9335_CDC_RX2_RX_PATH_SEC4, 0x00 },
  1108. { WCD9335_CDC_RX2_RX_PATH_SEC5, 0x00 },
  1109. { WCD9335_CDC_RX2_RX_PATH_SEC6, 0x00 },
  1110. { WCD9335_CDC_RX2_RX_PATH_SEC7, 0x00 },
  1111. { WCD9335_CDC_RX2_RX_PATH_MIX_SEC1, 0x00 },
  1112. { WCD9335_CDC_RX3_RX_PATH_CTL, 0x04 },
  1113. { WCD9335_CDC_RX3_RX_PATH_CFG0, 0x00 },
  1114. { WCD9335_CDC_RX3_RX_PATH_CFG2, 0x8f },
  1115. { WCD9335_CDC_RX3_RX_VOL_CTL, 0x00 },
  1116. { WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 0x04 },
  1117. { WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 0x00 },
  1118. { WCD9335_CDC_RX3_RX_PATH_SEC2, 0x00 },
  1119. { WCD9335_CDC_RX3_RX_PATH_SEC3, 0x00 },
  1120. { WCD9335_CDC_RX3_RX_PATH_SEC5, 0x00 },
  1121. { WCD9335_CDC_RX3_RX_PATH_SEC6, 0x00 },
  1122. { WCD9335_CDC_RX3_RX_PATH_SEC7, 0x00 },
  1123. { WCD9335_CDC_RX3_RX_PATH_MIX_SEC1, 0x00 },
  1124. { WCD9335_CDC_RX4_RX_PATH_CTL, 0x04 },
  1125. { WCD9335_CDC_RX4_RX_PATH_CFG0, 0x00 },
  1126. { WCD9335_CDC_RX4_RX_PATH_CFG2, 0x8f },
  1127. { WCD9335_CDC_RX4_RX_VOL_CTL, 0x00 },
  1128. { WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 0x04 },
  1129. { WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 0x00 },
  1130. { WCD9335_CDC_RX4_RX_PATH_SEC2, 0x00 },
  1131. { WCD9335_CDC_RX4_RX_PATH_SEC3, 0x00 },
  1132. { WCD9335_CDC_RX4_RX_PATH_SEC5, 0x00 },
  1133. { WCD9335_CDC_RX4_RX_PATH_SEC6, 0x00 },
  1134. { WCD9335_CDC_RX4_RX_PATH_SEC7, 0x00 },
  1135. { WCD9335_CDC_RX4_RX_PATH_MIX_SEC1, 0x00 },
  1136. { WCD9335_CDC_RX5_RX_PATH_CTL, 0x04 },
  1137. { WCD9335_CDC_RX5_RX_PATH_CFG0, 0x00 },
  1138. { WCD9335_CDC_RX5_RX_PATH_CFG2, 0x8f },
  1139. { WCD9335_CDC_RX5_RX_VOL_CTL, 0x00 },
  1140. { WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 0x04 },
  1141. { WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 0x00 },
  1142. { WCD9335_CDC_RX5_RX_PATH_SEC2, 0x00 },
  1143. { WCD9335_CDC_RX5_RX_PATH_SEC3, 0x00 },
  1144. { WCD9335_CDC_RX5_RX_PATH_SEC5, 0x00 },
  1145. { WCD9335_CDC_RX5_RX_PATH_SEC6, 0x00 },
  1146. { WCD9335_CDC_RX5_RX_PATH_SEC7, 0x00 },
  1147. { WCD9335_CDC_RX5_RX_PATH_MIX_SEC1, 0x00 },
  1148. { WCD9335_CDC_RX6_RX_PATH_CTL, 0x04 },
  1149. { WCD9335_CDC_RX6_RX_PATH_CFG0, 0x00 },
  1150. { WCD9335_CDC_RX6_RX_PATH_CFG2, 0x8f },
  1151. { WCD9335_CDC_RX6_RX_VOL_CTL, 0x00 },
  1152. { WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 0x04 },
  1153. { WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 0x00 },
  1154. { WCD9335_CDC_RX6_RX_PATH_SEC2, 0x00 },
  1155. { WCD9335_CDC_RX6_RX_PATH_SEC3, 0x00 },
  1156. { WCD9335_CDC_RX6_RX_PATH_SEC5, 0x00 },
  1157. { WCD9335_CDC_RX6_RX_PATH_SEC6, 0x00 },
  1158. { WCD9335_CDC_RX6_RX_PATH_SEC7, 0x00 },
  1159. { WCD9335_CDC_RX6_RX_PATH_MIX_SEC1, 0x00 },
  1160. { WCD9335_CDC_RX7_RX_PATH_CTL, 0x04 },
  1161. { WCD9335_CDC_RX7_RX_PATH_CFG0, 0x00 },
  1162. { WCD9335_CDC_RX7_RX_PATH_CFG2, 0x8f },
  1163. { WCD9335_CDC_RX7_RX_VOL_CTL, 0x00 },
  1164. { WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 0x04 },
  1165. { WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 0x00 },
  1166. { WCD9335_CDC_RX7_RX_PATH_SEC2, 0x00 },
  1167. { WCD9335_CDC_RX7_RX_PATH_SEC3, 0x00 },
  1168. { WCD9335_CDC_RX7_RX_PATH_SEC5, 0x00 },
  1169. { WCD9335_CDC_RX7_RX_PATH_SEC6, 0x00 },
  1170. { WCD9335_CDC_RX7_RX_PATH_SEC7, 0x00 },
  1171. { WCD9335_CDC_RX7_RX_PATH_MIX_SEC1, 0x00 },
  1172. { WCD9335_CDC_RX8_RX_PATH_CTL, 0x04 },
  1173. { WCD9335_CDC_RX8_RX_PATH_CFG0, 0x00 },
  1174. { WCD9335_CDC_RX8_RX_PATH_CFG2, 0x8f },
  1175. { WCD9335_CDC_RX8_RX_VOL_CTL, 0x00 },
  1176. { WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 0x04 },
  1177. { WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 0x00 },
  1178. { WCD9335_CDC_RX8_RX_PATH_SEC2, 0x00 },
  1179. { WCD9335_CDC_RX8_RX_PATH_SEC3, 0x00 },
  1180. { WCD9335_CDC_RX8_RX_PATH_SEC5, 0x00 },
  1181. { WCD9335_CDC_RX8_RX_PATH_SEC6, 0x00 },
  1182. { WCD9335_CDC_RX8_RX_PATH_SEC7, 0x00 },
  1183. { WCD9335_CDC_RX8_RX_PATH_MIX_SEC1, 0x00 },
  1184. /* Page #12 registers */
  1185. { WCD9335_PAGE12_PAGE_REGISTER, 0x00 },
  1186. { WCD9335_CDC_CLSH_CRC, 0x00 },
  1187. { WCD9335_CDC_CLSH_DLY_CTRL, 0x03 },
  1188. { WCD9335_CDC_CLSH_DECAY_CTRL, 0x02 },
  1189. { WCD9335_CDC_CLSH_HPH_V_PA, 0x1c },
  1190. { WCD9335_CDC_CLSH_EAR_V_PA, 0x39 },
  1191. { WCD9335_CDC_CLSH_HPH_V_HD, 0x0c },
  1192. { WCD9335_CDC_CLSH_EAR_V_HD, 0x0c },
  1193. { WCD9335_CDC_CLSH_K1_MSB, 0x01 },
  1194. { WCD9335_CDC_CLSH_K1_LSB, 0x00 },
  1195. { WCD9335_CDC_CLSH_K2_MSB, 0x00 },
  1196. { WCD9335_CDC_CLSH_K2_LSB, 0x80 },
  1197. { WCD9335_CDC_CLSH_IDLE_CTRL, 0x00 },
  1198. { WCD9335_CDC_CLSH_IDLE_HPH, 0x00 },
  1199. { WCD9335_CDC_CLSH_IDLE_EAR, 0x00 },
  1200. { WCD9335_CDC_CLSH_TEST0, 0x07 },
  1201. { WCD9335_CDC_CLSH_TEST1, 0x00 },
  1202. { WCD9335_CDC_CLSH_OVR_VREF, 0x00 },
  1203. { WCD9335_CDC_BOOST0_BOOST_PATH_CTL, 0x00 },
  1204. { WCD9335_CDC_BOOST0_BOOST_CTL, 0xb2 },
  1205. { WCD9335_CDC_BOOST0_BOOST_CFG1, 0x00 },
  1206. { WCD9335_CDC_BOOST0_BOOST_CFG2, 0x00 },
  1207. { WCD9335_CDC_BOOST1_BOOST_PATH_CTL, 0x00 },
  1208. { WCD9335_CDC_BOOST1_BOOST_CTL, 0xb2 },
  1209. { WCD9335_CDC_BOOST1_BOOST_CFG1, 0x00 },
  1210. { WCD9335_CDC_BOOST1_BOOST_CFG2, 0x00 },
  1211. { WCD9335_SWR_AHB_BRIDGE_WR_DATA_0, 0x00 },
  1212. { WCD9335_SWR_AHB_BRIDGE_WR_DATA_1, 0x00 },
  1213. { WCD9335_SWR_AHB_BRIDGE_WR_DATA_2, 0x00 },
  1214. { WCD9335_SWR_AHB_BRIDGE_WR_DATA_3, 0x00 },
  1215. { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0, 0x00 },
  1216. { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1, 0x00 },
  1217. { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2, 0x00 },
  1218. { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3, 0x00 },
  1219. { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0, 0x00 },
  1220. { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1, 0x00 },
  1221. { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2, 0x00 },
  1222. { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3, 0x00 },
  1223. { WCD9335_SWR_AHB_BRIDGE_RD_DATA_0, 0x00 },
  1224. { WCD9335_SWR_AHB_BRIDGE_RD_DATA_1, 0x00 },
  1225. { WCD9335_SWR_AHB_BRIDGE_RD_DATA_2, 0x00 },
  1226. { WCD9335_SWR_AHB_BRIDGE_RD_DATA_3, 0x00 },
  1227. { WCD9335_SWR_AHB_BRIDGE_ACCESS_CFG, 0x0f },
  1228. { WCD9335_SWR_AHB_BRIDGE_ACCESS_STATUS, 0x03 },
  1229. { WCD9335_CDC_VBAT_VBAT_PATH_CTL, 0x00 },
  1230. { WCD9335_CDC_VBAT_VBAT_CFG, 0x0a },
  1231. { WCD9335_CDC_VBAT_VBAT_ADC_CAL1, 0x00 },
  1232. { WCD9335_CDC_VBAT_VBAT_ADC_CAL2, 0x00 },
  1233. { WCD9335_CDC_VBAT_VBAT_ADC_CAL3, 0x04 },
  1234. { WCD9335_CDC_VBAT_VBAT_PK_EST1, 0xe0 },
  1235. { WCD9335_CDC_VBAT_VBAT_PK_EST2, 0x01 },
  1236. { WCD9335_CDC_VBAT_VBAT_PK_EST3, 0x40 },
  1237. { WCD9335_CDC_VBAT_VBAT_RF_PROC1, 0x2a },
  1238. { WCD9335_CDC_VBAT_VBAT_RF_PROC2, 0x86 },
  1239. { WCD9335_CDC_VBAT_VBAT_TAC1, 0x70 },
  1240. { WCD9335_CDC_VBAT_VBAT_TAC2, 0x18 },
  1241. { WCD9335_CDC_VBAT_VBAT_TAC3, 0x18 },
  1242. { WCD9335_CDC_VBAT_VBAT_TAC4, 0x03 },
  1243. { WCD9335_CDC_VBAT_VBAT_GAIN_UPD1, 0x01 },
  1244. { WCD9335_CDC_VBAT_VBAT_GAIN_UPD2, 0x00 },
  1245. { WCD9335_CDC_VBAT_VBAT_GAIN_UPD3, 0x64 },
  1246. { WCD9335_CDC_VBAT_VBAT_GAIN_UPD4, 0x01 },
  1247. { WCD9335_CDC_VBAT_VBAT_DEBUG1, 0x00 },
  1248. { WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON, 0x00 },
  1249. { WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL, 0x00 },
  1250. { WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
  1251. { WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
  1252. { WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
  1253. { WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
  1254. /* Page #13 registers */
  1255. { WCD9335_PAGE13_PAGE_REGISTER, 0x00 },
  1256. { WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
  1257. { WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
  1258. { WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
  1259. { WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
  1260. { WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
  1261. { WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
  1262. { WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0x00 },
  1263. { WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0x00 },
  1264. { WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0x00 },
  1265. { WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0x00 },
  1266. { WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0x00 },
  1267. { WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0x00 },
  1268. { WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0x00 },
  1269. { WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0x00 },
  1270. { WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0x00 },
  1271. { WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0x00 },
  1272. { WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0x00 },
  1273. { WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0x00 },
  1274. { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG0, 0x00 },
  1275. { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG1, 0x00 },
  1276. { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG2, 0x00 },
  1277. { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG3, 0x00 },
  1278. { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
  1279. { WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
  1280. { WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0x00 },
  1281. { WCD9335_CDC_RX_INP_MUX_ANC_CFG0, 0x00 },
  1282. { WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0, 0x00 },
  1283. { WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00 },
  1284. { WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00 },
  1285. { WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00 },
  1286. { WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00 },
  1287. { WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00 },
  1288. { WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00 },
  1289. { WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00 },
  1290. { WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00 },
  1291. { WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00 },
  1292. { WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00 },
  1293. { WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00 },
  1294. { WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00 },
  1295. { WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0x00 },
  1296. { WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0, 0x00 },
  1297. { WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0, 0x00 },
  1298. { WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0, 0x00 },
  1299. { WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0, 0x00 },
  1300. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
  1301. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
  1302. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
  1303. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
  1304. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
  1305. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
  1306. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
  1307. { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
  1308. { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0x00 },
  1309. { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0x00 },
  1310. { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0x00 },
  1311. { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3, 0x00 },
  1312. { WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
  1313. { WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
  1314. { WCD9335_CDC_PROX_DETECT_PROX_CTL, 0x08 },
  1315. { WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD0, 0x00 },
  1316. { WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD1, 0x4b },
  1317. { WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB, 0x00 },
  1318. { WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB, 0x00 },
  1319. { WCD9335_CDC_PROX_DETECT_PROX_STATUS, 0x00 },
  1320. { WCD9335_CDC_PROX_DETECT_PROX_TEST_CTRL, 0x00 },
  1321. { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB, 0x00 },
  1322. { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB, 0x00 },
  1323. { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD, 0x00 },
  1324. { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD, 0x00 },
  1325. { WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
  1326. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
  1327. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
  1328. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
  1329. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
  1330. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
  1331. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
  1332. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
  1333. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
  1334. { WCD9335_CDC_SIDETONE_IIR0_IIR_CTL, 0x40 },
  1335. { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
  1336. { WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
  1337. { WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
  1338. { WCD9335_CDC_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
  1339. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
  1340. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
  1341. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
  1342. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
  1343. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
  1344. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
  1345. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
  1346. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
  1347. { WCD9335_CDC_SIDETONE_IIR1_IIR_CTL, 0x40 },
  1348. { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
  1349. { WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
  1350. { WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
  1351. { WCD9335_CDC_TOP_TOP_CFG0, 0x00 },
  1352. { WCD9335_CDC_TOP_TOP_CFG1, 0x00 },
  1353. { WCD9335_CDC_TOP_TOP_CFG2, 0x00 },
  1354. { WCD9335_CDC_TOP_TOP_CFG3, 0x18 },
  1355. { WCD9335_CDC_TOP_TOP_CFG4, 0x00 },
  1356. { WCD9335_CDC_TOP_TOP_CFG5, 0x00 },
  1357. { WCD9335_CDC_TOP_TOP_CFG6, 0x00 },
  1358. { WCD9335_CDC_TOP_TOP_CFG7, 0x00 },
  1359. { WCD9335_CDC_TOP_HPHL_COMP_WR_LSB, 0x00 },
  1360. { WCD9335_CDC_TOP_HPHL_COMP_WR_MSB, 0x00 },
  1361. { WCD9335_CDC_TOP_HPHL_COMP_LUT, 0x00 },
  1362. { WCD9335_CDC_TOP_HPHL_COMP_RD_LSB, 0x00 },
  1363. { WCD9335_CDC_TOP_HPHL_COMP_RD_MSB, 0x00 },
  1364. { WCD9335_CDC_TOP_HPHR_COMP_WR_LSB, 0x00 },
  1365. { WCD9335_CDC_TOP_HPHR_COMP_WR_MSB, 0x00 },
  1366. { WCD9335_CDC_TOP_HPHR_COMP_LUT, 0x00 },
  1367. { WCD9335_CDC_TOP_HPHR_COMP_RD_LSB, 0x00 },
  1368. { WCD9335_CDC_TOP_HPHR_COMP_RD_MSB, 0x00 },
  1369. { WCD9335_CDC_TOP_DIFFL_COMP_WR_LSB, 0x00 },
  1370. { WCD9335_CDC_TOP_DIFFL_COMP_WR_MSB, 0x00 },
  1371. { WCD9335_CDC_TOP_DIFFL_COMP_LUT, 0x00 },
  1372. { WCD9335_CDC_TOP_DIFFL_COMP_RD_LSB, 0x00 },
  1373. { WCD9335_CDC_TOP_DIFFL_COMP_RD_MSB, 0x00 },
  1374. { WCD9335_CDC_TOP_DIFFR_COMP_WR_LSB, 0x00 },
  1375. { WCD9335_CDC_TOP_DIFFR_COMP_WR_MSB, 0x00 },
  1376. { WCD9335_CDC_TOP_DIFFR_COMP_LUT, 0x00 },
  1377. { WCD9335_CDC_TOP_DIFFR_COMP_RD_LSB, 0x00 },
  1378. { WCD9335_CDC_TOP_DIFFR_COMP_RD_MSB, 0x00 },
  1379. /* Page #0x80 registers */
  1380. { WCD9335_PAGE80_PAGE_REGISTER, 0x00 },
  1381. { WCD9335_TLMM_BIST_MODE_PINCFG, 0x00 },
  1382. { WCD9335_TLMM_RF_PA_ON_PINCFG, 0x00 },
  1383. { WCD9335_TLMM_INTR1_PINCFG, 0x00 },
  1384. { WCD9335_TLMM_INTR2_PINCFG, 0x00 },
  1385. { WCD9335_TLMM_SWR_DATA_PINCFG, 0x00 },
  1386. { WCD9335_TLMM_SWR_CLK_PINCFG, 0x00 },
  1387. { WCD9335_TLMM_SLIMBUS_DATA2_PINCFG, 0x00 },
  1388. { WCD9335_TLMM_I2C_CLK_PINCFG, 0x00 },
  1389. { WCD9335_TLMM_I2C_DATA_PINCFG, 0x00 },
  1390. { WCD9335_TLMM_I2S_RX_SD0_PINCFG, 0x00 },
  1391. { WCD9335_TLMM_I2S_RX_SD1_PINCFG, 0x00 },
  1392. { WCD9335_TLMM_I2S_RX_SCK_PINCFG, 0x00 },
  1393. { WCD9335_TLMM_I2S_RX_WS_PINCFG, 0x00 },
  1394. { WCD9335_TLMM_I2S_TX_SD0_PINCFG, 0x00 },
  1395. { WCD9335_TLMM_I2S_TX_SD1_PINCFG, 0x00 },
  1396. { WCD9335_TLMM_I2S_TX_SCK_PINCFG, 0x00 },
  1397. { WCD9335_TLMM_I2S_TX_WS_PINCFG, 0x00 },
  1398. { WCD9335_TLMM_DMIC1_CLK_PINCFG, 0x00 },
  1399. { WCD9335_TLMM_DMIC1_DATA_PINCFG, 0x00 },
  1400. { WCD9335_TLMM_DMIC2_CLK_PINCFG, 0x00 },
  1401. { WCD9335_TLMM_DMIC2_DATA_PINCFG, 0x00 },
  1402. { WCD9335_TLMM_DMIC3_CLK_PINCFG, 0x00 },
  1403. { WCD9335_TLMM_DMIC3_DATA_PINCFG, 0x00 },
  1404. { WCD9335_TLMM_JTDI_PINCFG, 0x00 },
  1405. { WCD9335_TLMM_JTDO_PINCFG, 0x00 },
  1406. { WCD9335_TLMM_JTMS_PINCFG, 0x00 },
  1407. { WCD9335_TLMM_JTCK_PINCFG, 0x00 },
  1408. { WCD9335_TLMM_JTRST_PINCFG, 0x00 },
  1409. { WCD9335_TEST_DEBUG_PIN_CTL_OE_0, 0x00 },
  1410. { WCD9335_TEST_DEBUG_PIN_CTL_OE_1, 0x00 },
  1411. { WCD9335_TEST_DEBUG_PIN_CTL_OE_2, 0x00 },
  1412. { WCD9335_TEST_DEBUG_PIN_CTL_OE_3, 0x00 },
  1413. { WCD9335_TEST_DEBUG_PIN_CTL_DATA_0, 0x00 },
  1414. { WCD9335_TEST_DEBUG_PIN_CTL_DATA_1, 0x00 },
  1415. { WCD9335_TEST_DEBUG_PIN_CTL_DATA_2, 0x00 },
  1416. { WCD9335_TEST_DEBUG_PIN_CTL_DATA_3, 0x00 },
  1417. { WCD9335_TEST_DEBUG_PAD_DRVCTL, 0x00 },
  1418. { WCD9335_TEST_DEBUG_PIN_STATUS, 0x00 },
  1419. { WCD9335_TEST_DEBUG_MEM_CTRL, 0x00 },
  1420. { WCD9335_TEST_DEBUG_DEBUG_BUS_SEL, 0x00 },
  1421. { WCD9335_TEST_DEBUG_DEBUG_JTAG, 0x00 },
  1422. { WCD9335_TEST_DEBUG_DEBUG_EN_1, 0x00 },
  1423. { WCD9335_TEST_DEBUG_DEBUG_EN_2, 0x00 },
  1424. { WCD9335_TEST_DEBUG_DEBUG_EN_3, 0x00 },
  1425. };
  1426. /*
  1427. * wcd9335_regmap_register_patch: Update register defaults based on version
  1428. * @regmap: handle to wcd9xxx regmap
  1429. * @version: wcd9335 version
  1430. *
  1431. * Returns error code in case of failure or 0 for success
  1432. */
  1433. int wcd9335_regmap_register_patch(struct regmap *regmap, int version)
  1434. {
  1435. int rc;
  1436. if (!regmap) {
  1437. pr_err("%s: regmap struct is NULL\n", __func__);
  1438. return -EINVAL;
  1439. }
  1440. switch (version) {
  1441. case TASHA_VERSION_1_0:
  1442. case TASHA_VERSION_1_1:
  1443. regcache_cache_only(regmap, true);
  1444. rc = regmap_multi_reg_write(regmap, wcd9335_1_x_defaults,
  1445. ARRAY_SIZE(wcd9335_1_x_defaults));
  1446. regcache_cache_only(regmap, false);
  1447. break;
  1448. case TASHA_VERSION_2_0:
  1449. regcache_cache_only(regmap, true);
  1450. rc = regmap_multi_reg_write(regmap, wcd9335_2_0_defaults,
  1451. ARRAY_SIZE(wcd9335_2_0_defaults));
  1452. regcache_cache_only(regmap, false);
  1453. break;
  1454. default:
  1455. pr_err("%s: unknown version: %d\n", __func__, version);
  1456. rc = -EINVAL;
  1457. break;
  1458. }
  1459. return rc;
  1460. }
  1461. EXPORT_SYMBOL(wcd9335_regmap_register_patch);
  1462. static bool wcd9335_is_readable_register(struct device *dev, unsigned int reg)
  1463. {
  1464. u8 pg_num, reg_offset;
  1465. const u8 *reg_tbl = NULL;
  1466. /*
  1467. * Get the page number from MSB of codec register. If its 0x80, assign
  1468. * the corresponding page index PAGE_0x80.
  1469. */
  1470. pg_num = reg >> 0x8;
  1471. if (pg_num == 0x80)
  1472. pg_num = PAGE_0X80;
  1473. else if (pg_num >= 0xE)
  1474. return false;
  1475. reg_tbl = wcd9335_reg[pg_num];
  1476. reg_offset = reg & 0xFF;
  1477. if (reg_tbl)
  1478. return reg_tbl[reg_offset];
  1479. else
  1480. return false;
  1481. }
  1482. static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
  1483. {
  1484. /*
  1485. * registers from 0x000 to 0x0FF are volatile because
  1486. * this space contains registers related to interrupt
  1487. * status, mask etc
  1488. */
  1489. if (reg < 0x100)
  1490. return true;
  1491. /* IIR Coeff registers are not cacheable */
  1492. if ((reg >= WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL) &&
  1493. (reg <= WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL))
  1494. return true;
  1495. if ((reg >= WCD9335_CDC_ANC0_IIR_COEFF_1_CTL) &&
  1496. (reg <= WCD9335_CDC_ANC0_FB_GAIN_CTL))
  1497. return true;
  1498. if ((reg >= WCD9335_CDC_ANC1_IIR_COEFF_1_CTL) &&
  1499. (reg <= WCD9335_CDC_ANC1_FB_GAIN_CTL))
  1500. return true;
  1501. /*
  1502. * CPE inbox and outbox registers are volatile
  1503. * since they can be updated in the codec hardware
  1504. * to indicate CPE status
  1505. */
  1506. if (reg >= WCD9335_CPE_SS_MEM_PTR_0 &&
  1507. reg <= WCD9335_CPE_SS_OUTBOX2_ACK)
  1508. return true;
  1509. if (reg >= WCD9335_RCO_CAL_OUT_1 &&
  1510. reg <= WCD9335_RCO_CAL_OUT_5)
  1511. return true;
  1512. switch (reg) {
  1513. case WCD9335_CPE_SS_INBOX1_TRG:
  1514. case WCD9335_CPE_SS_INBOX2_TRG:
  1515. case WCD9335_SWR_AHB_BRIDGE_WR_DATA_0:
  1516. case WCD9335_SWR_AHB_BRIDGE_WR_DATA_1:
  1517. case WCD9335_SWR_AHB_BRIDGE_WR_DATA_2:
  1518. case WCD9335_SWR_AHB_BRIDGE_WR_DATA_3:
  1519. case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0:
  1520. case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1:
  1521. case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2:
  1522. case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3:
  1523. case WCD9335_SWR_AHB_BRIDGE_RD_DATA_0:
  1524. case WCD9335_SWR_AHB_BRIDGE_RD_DATA_1:
  1525. case WCD9335_SWR_AHB_BRIDGE_RD_DATA_2:
  1526. case WCD9335_SWR_AHB_BRIDGE_RD_DATA_3:
  1527. case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0:
  1528. case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1:
  1529. case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2:
  1530. case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3:
  1531. case WCD9335_ANA_BIAS:
  1532. case WCD9335_ANA_CLK_TOP:
  1533. case WCD9335_ANA_RCO:
  1534. case WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL:
  1535. case WCD9335_ANA_MBHC_RESULT_3:
  1536. case WCD9335_ANA_MBHC_RESULT_2:
  1537. case WCD9335_ANA_MBHC_RESULT_1:
  1538. case WCD9335_ANA_MBHC_MECH:
  1539. case WCD9335_ANA_MBHC_ELECT:
  1540. case WCD9335_ANA_MBHC_ZDET:
  1541. case WCD9335_ANA_MICB2:
  1542. case WCD9335_CPE_SS_SS_ERROR_INT_STATUS:
  1543. case WCD9335_CPE_SS_SS_ERROR_INT_MASK:
  1544. case WCD9335_CPE_SS_SS_ERROR_INT_CLEAR:
  1545. case WCD9335_CPE_SS_STATUS:
  1546. case WCD9335_CPE_SS_BACKUP_INT:
  1547. case WCD9335_CPE_SS_CFG:
  1548. case WCD9335_SOC_MAD_MAIN_CTL_1:
  1549. case WCD9335_SOC_MAD_AUDIO_CTL_3:
  1550. case WCD9335_SOC_MAD_AUDIO_CTL_4:
  1551. case WCD9335_FLYBACK_EN:
  1552. case WCD9335_ANA_RX_SUPPLIES:
  1553. case WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL:
  1554. case WCD9335_SIDO_SIDO_CCL_2:
  1555. case WCD9335_SIDO_SIDO_CCL_4:
  1556. case WCD9335_DATA_HUB_NATIVE_FIFO_STATUS:
  1557. case WCD9335_MBHC_FSM_STATUS:
  1558. case WCD9335_SPLINE_SRC0_STATUS:
  1559. case WCD9335_SPLINE_SRC1_STATUS:
  1560. case WCD9335_SPLINE_SRC2_STATUS:
  1561. case WCD9335_SPLINE_SRC3_STATUS:
  1562. case WCD9335_SIDO_SIDO_TEST_2:
  1563. case WCD9335_SIDO_SIDO_CCL_8:
  1564. case WCD9335_BIAS_VBG_FINE_ADJ:
  1565. case WCD9335_VBADC_ADC_DOUTMSB:
  1566. case WCD9335_VBADC_ADC_DOUTLSB:
  1567. case WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL:
  1568. case WCD9335_ANA_BUCK_CTL:
  1569. return true;
  1570. default:
  1571. return false;
  1572. }
  1573. }
  1574. struct regmap_config wcd9335_regmap_config = {
  1575. .reg_bits = 16,
  1576. .val_bits = 8,
  1577. .cache_type = REGCACHE_RBTREE,
  1578. .reg_defaults = wcd9335_defaults,
  1579. .num_reg_defaults = ARRAY_SIZE(wcd9335_defaults),
  1580. .max_register = WCD9335_MAX_REGISTER,
  1581. .volatile_reg = wcd9335_is_volatile_register,
  1582. .readable_reg = wcd9335_is_readable_register,
  1583. .can_multi_write = true,
  1584. };