wcd-clsh.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, 2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <sound/soc.h>
  8. #include <linux/kernel.h>
  9. #include <linux/delay.h>
  10. #include <asoc/wcd-clsh.h>
  11. #define WCD_USLEEP_RANGE 50
  12. static void (*clsh_state_fp[NUM_CLSH_STATES])(struct snd_soc_component *,
  13. struct wcd_clsh_cdc_info *,
  14. u8 req_state, bool en, int mode);
  15. static const char *mode_to_str(int mode)
  16. {
  17. switch (mode) {
  18. case CLS_H_NORMAL:
  19. return WCD_CLSH_STRINGIFY(CLS_H_NORMAL);
  20. case CLS_H_HIFI:
  21. return WCD_CLSH_STRINGIFY(CLS_H_HIFI);
  22. case CLS_H_LOHIFI:
  23. return WCD_CLSH_STRINGIFY(CLS_H_LOHIFI);
  24. case CLS_H_LP:
  25. return WCD_CLSH_STRINGIFY(CLS_H_LP);
  26. case CLS_H_ULP:
  27. return WCD_CLSH_STRINGIFY(CLS_H_ULP);
  28. case CLS_AB:
  29. return WCD_CLSH_STRINGIFY(CLS_AB);
  30. case CLS_AB_HIFI:
  31. return WCD_CLSH_STRINGIFY(CLS_AB_HIFI);
  32. case CLS_AB_LP:
  33. return WCD_CLSH_STRINGIFY(CLS_AB_LP);
  34. case CLS_AB_LOHIFI:
  35. return WCD_CLSH_STRINGIFY(CLS_AB_LOHIFI);
  36. default:
  37. return WCD_CLSH_STRINGIFY(CLS_H_INVALID);
  38. };
  39. }
  40. static const char *state_to_str(u8 state, char *buf, size_t buflen)
  41. {
  42. int i;
  43. int cnt = 0;
  44. /*
  45. * This array of strings should match with enum wcd_clsh_state_bit.
  46. */
  47. static const char *const states[] = {
  48. "STATE_EAR",
  49. "STATE_HPH_L",
  50. "STATE_HPH_R",
  51. "STATE_AUX",
  52. };
  53. if (state == WCD_CLSH_STATE_IDLE) {
  54. snprintf(buf, buflen, "[STATE_IDLE]");
  55. goto done;
  56. }
  57. buf[0] = '\0';
  58. for (i = 0; i < ARRAY_SIZE(states); i++) {
  59. if (!(state & (1 << i)))
  60. continue;
  61. cnt = snprintf(buf, buflen - cnt - 1, "%s%s%s", buf,
  62. buf[0] == '\0' ? "[" : "|",
  63. states[i]);
  64. }
  65. if (cnt > 0)
  66. strlcat(buf + cnt, "]", buflen);
  67. done:
  68. if (buf[0] == '\0')
  69. snprintf(buf, buflen, "[STATE_UNKNOWN]");
  70. return buf;
  71. }
  72. static inline int wcd_clsh_get_int_mode(struct wcd_clsh_cdc_info *clsh_d,
  73. int clsh_state)
  74. {
  75. int mode;
  76. if ((clsh_state != WCD_CLSH_STATE_EAR) &&
  77. (clsh_state != WCD_CLSH_STATE_HPHL) &&
  78. (clsh_state != WCD_CLSH_STATE_HPHR) &&
  79. (clsh_state != WCD_CLSH_STATE_AUX))
  80. mode = CLS_NONE;
  81. else
  82. mode = clsh_d->interpolator_modes[ffs(clsh_state)];
  83. return mode;
  84. }
  85. static inline void wcd_clsh_set_int_mode(struct wcd_clsh_cdc_info *clsh_d,
  86. int clsh_state, int mode)
  87. {
  88. if ((clsh_state != WCD_CLSH_STATE_EAR) &&
  89. (clsh_state != WCD_CLSH_STATE_HPHL) &&
  90. (clsh_state != WCD_CLSH_STATE_HPHR) &&
  91. (clsh_state != WCD_CLSH_STATE_AUX))
  92. return;
  93. clsh_d->interpolator_modes[ffs(clsh_state)] = mode;
  94. }
  95. static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *component,
  96. int mode)
  97. {
  98. if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
  99. mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI)
  100. snd_soc_component_update_bits(component,
  101. WCD9XXX_ANA_RX_SUPPLIES,
  102. 0x08, 0x08); /* set to HIFI */
  103. else
  104. snd_soc_component_update_bits(component,
  105. WCD9XXX_ANA_RX_SUPPLIES,
  106. 0x08, 0x00); /* set to default */
  107. }
  108. static inline void wcd_clsh_set_flyback_mode(
  109. struct snd_soc_component *component,
  110. int mode)
  111. {
  112. if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
  113. mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) {
  114. snd_soc_component_update_bits(component,
  115. WCD9XXX_ANA_RX_SUPPLIES,
  116. 0x04, 0x04);
  117. snd_soc_component_update_bits(component,
  118. WCD9XXX_FLYBACK_VNEG_CTRL_4,
  119. 0xF0, 0x80);
  120. } else {
  121. snd_soc_component_update_bits(component,
  122. WCD9XXX_ANA_RX_SUPPLIES,
  123. 0x04, 0x00); /* set to Default */
  124. snd_soc_component_update_bits(component,
  125. WCD9XXX_FLYBACK_VNEG_CTRL_4,
  126. 0xF0, 0x70);
  127. }
  128. }
  129. static inline void wcd_clsh_force_iq_ctl(struct snd_soc_component *component,
  130. int mode, bool enable)
  131. {
  132. if (enable) {
  133. snd_soc_component_update_bits(component,
  134. WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
  135. 0xE0, 0xA0);
  136. /* 100usec delay is needed as per HW requirement */
  137. usleep_range(100, 110);
  138. snd_soc_component_update_bits(component,
  139. WCD9XXX_CLASSH_MODE_3,
  140. 0x02, 0x02);
  141. snd_soc_component_update_bits(component,
  142. WCD9XXX_CLASSH_MODE_2,
  143. 0xFF, 0x1C);
  144. if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) {
  145. snd_soc_component_update_bits(component,
  146. WCD9XXX_HPH_NEW_INT_PA_MISC2,
  147. 0x20, 0x20);
  148. snd_soc_component_update_bits(component,
  149. WCD9XXX_RX_BIAS_HPH_LOWPOWER,
  150. 0xF0, 0xC0);
  151. snd_soc_component_update_bits(component,
  152. WCD9XXX_HPH_PA_CTL1,
  153. 0x0E, 0x02);
  154. }
  155. } else {
  156. snd_soc_component_update_bits(component,
  157. WCD9XXX_HPH_NEW_INT_PA_MISC2,
  158. 0x20, 0x00);
  159. snd_soc_component_update_bits(component,
  160. WCD9XXX_RX_BIAS_HPH_LOWPOWER,
  161. 0xF0, 0x80);
  162. snd_soc_component_update_bits(component,
  163. WCD9XXX_HPH_PA_CTL1,
  164. 0x0E, 0x06);
  165. }
  166. }
  167. static void wcd_clsh_buck_ctrl(struct snd_soc_component *component,
  168. struct wcd_clsh_cdc_info *clsh_d,
  169. int mode,
  170. bool enable)
  171. {
  172. /* enable/disable buck */
  173. if ((enable && (++clsh_d->buck_users == 1)) ||
  174. (!enable && (--clsh_d->buck_users == 0))) {
  175. snd_soc_component_update_bits(component,
  176. WCD9XXX_ANA_RX_SUPPLIES,
  177. (1 << 7), (enable << 7));
  178. /*
  179. * 500us sleep is required after buck enable/disable
  180. * as per HW requirement
  181. */
  182. usleep_range(500, 510);
  183. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  184. mode == CLS_H_HIFI || mode == CLS_H_LP)
  185. snd_soc_component_update_bits(component,
  186. WCD9XXX_CLASSH_MODE_3,
  187. 0x02, 0x00);
  188. snd_soc_component_update_bits(component,
  189. WCD9XXX_CLASSH_MODE_2,
  190. 0xFF, 0x3A);
  191. /* 500usec delay is needed as per HW requirement */
  192. usleep_range(500, 500 + WCD_USLEEP_RANGE);
  193. }
  194. dev_dbg(component->dev, "%s: buck_users %d, enable %d, mode: %s\n",
  195. __func__, clsh_d->buck_users, enable, mode_to_str(mode));
  196. }
  197. static void wcd_clsh_flyback_ctrl(struct snd_soc_component *component,
  198. struct wcd_clsh_cdc_info *clsh_d,
  199. int mode,
  200. bool enable)
  201. {
  202. /* enable/disable flyback */
  203. if ((enable && (++clsh_d->flyback_users == 1)) ||
  204. (!enable && (--clsh_d->flyback_users == 0))) {
  205. snd_soc_component_update_bits(component,
  206. WCD9XXX_FLYBACK_VNEG_CTRL_1,
  207. 0xE0, 0xE0);
  208. snd_soc_component_update_bits(component,
  209. WCD9XXX_ANA_RX_SUPPLIES,
  210. (1 << 6), (enable << 6));
  211. /*
  212. * 100us sleep is required after flyback enable/disable
  213. * as per HW requirement
  214. */
  215. usleep_range(100, 110);
  216. snd_soc_component_update_bits(component,
  217. WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
  218. 0xE0, 0xE0);
  219. /* 500usec delay is needed as per HW requirement */
  220. usleep_range(500, 500 + WCD_USLEEP_RANGE);
  221. }
  222. dev_dbg(component->dev, "%s: flyback_users %d, enable %d, mode: %s\n",
  223. __func__, clsh_d->flyback_users, enable, mode_to_str(mode));
  224. }
  225. /*
  226. * Function: wcd_clsh_set_hph_mode
  227. * Params: soc component, hph mode class
  228. * Description:
  229. * This function updates class H mode configuration based on
  230. * the input mode.
  231. */
  232. void wcd_clsh_set_hph_mode(struct snd_soc_component *component,
  233. int mode)
  234. {
  235. u8 val = 0;
  236. switch (mode) {
  237. case CLS_H_NORMAL:
  238. val = 0x00;
  239. break;
  240. case CLS_AB:
  241. case CLS_H_ULP:
  242. val = 0x0C;
  243. break;
  244. case CLS_AB_HIFI:
  245. case CLS_H_HIFI:
  246. val = 0x08;
  247. break;
  248. case CLS_H_LP:
  249. case CLS_H_LOHIFI:
  250. case CLS_AB_LP:
  251. case CLS_AB_LOHIFI:
  252. val = 0x04;
  253. break;
  254. default:
  255. dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode);
  256. return;
  257. };
  258. snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val);
  259. }
  260. EXPORT_SYMBOL(wcd_clsh_set_hph_mode);
  261. static void wcd_clsh_set_flyback_current(struct snd_soc_component *component,
  262. int mode)
  263. {
  264. snd_soc_component_update_bits(component, WCD9XXX_RX_BIAS_FLYB_BUFF,
  265. 0x0F, 0x0A);
  266. snd_soc_component_update_bits(component, WCD9XXX_RX_BIAS_FLYB_BUFF,
  267. 0xF0, 0xA0);
  268. /* Sleep needed to avoid click and pop as per HW requirement */
  269. usleep_range(100, 110);
  270. }
  271. static void wcd_clsh_set_buck_regulator_mode(
  272. struct snd_soc_component *component,
  273. int mode)
  274. {
  275. snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES,
  276. 0x02, 0x00);
  277. }
  278. static void wcd_clsh_state_ear_aux(struct snd_soc_component *component,
  279. struct wcd_clsh_cdc_info *clsh_d,
  280. u8 req_state, bool is_enable, int mode)
  281. {
  282. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  283. mode_to_str(mode), is_enable ? "enable" : "disable");
  284. }
  285. static void wcd_clsh_state_hph_aux(struct snd_soc_component *component,
  286. struct wcd_clsh_cdc_info *clsh_d,
  287. u8 req_state, bool is_enable, int mode)
  288. {
  289. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  290. mode_to_str(mode), is_enable ? "enable" : "disable");
  291. }
  292. static void wcd_clsh_state_hph_ear(struct snd_soc_component *component,
  293. struct wcd_clsh_cdc_info *clsh_d,
  294. u8 req_state, bool is_enable, int mode)
  295. {
  296. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  297. mode_to_str(mode), is_enable ? "enable" : "disable");
  298. }
  299. static void wcd_clsh_state_hph_st(struct snd_soc_component *component,
  300. struct wcd_clsh_cdc_info *clsh_d,
  301. u8 req_state, bool is_enable, int mode)
  302. {
  303. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  304. mode_to_str(mode), is_enable ? "enable" : "disable");
  305. }
  306. static void wcd_clsh_state_hph_r(struct snd_soc_component *component,
  307. struct wcd_clsh_cdc_info *clsh_d,
  308. u8 req_state, bool is_enable, int mode)
  309. {
  310. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  311. mode_to_str(mode), is_enable ? "enable" : "disable");
  312. if (mode == CLS_H_NORMAL) {
  313. dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n",
  314. __func__);
  315. return;
  316. }
  317. if (is_enable) {
  318. wcd_clsh_set_buck_regulator_mode(component, mode);
  319. wcd_clsh_set_flyback_mode(component, mode);
  320. wcd_clsh_force_iq_ctl(component, mode, true);
  321. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  322. wcd_clsh_set_flyback_current(component, mode);
  323. wcd_clsh_set_buck_mode(component, mode);
  324. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  325. wcd_clsh_set_hph_mode(component, mode);
  326. } else {
  327. wcd_clsh_set_hph_mode(component, CLS_H_NORMAL);
  328. /* buck and flyback set to default mode and disable */
  329. wcd_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  330. wcd_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  331. wcd_clsh_force_iq_ctl(component, CLS_H_NORMAL, false);
  332. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  333. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  334. }
  335. }
  336. static void wcd_clsh_state_hph_l(struct snd_soc_component *component,
  337. struct wcd_clsh_cdc_info *clsh_d,
  338. u8 req_state, bool is_enable, int mode)
  339. {
  340. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  341. mode_to_str(mode), is_enable ? "enable" : "disable");
  342. if (mode == CLS_H_NORMAL) {
  343. dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n",
  344. __func__);
  345. return;
  346. }
  347. if (is_enable) {
  348. wcd_clsh_set_buck_regulator_mode(component, mode);
  349. wcd_clsh_set_flyback_mode(component, mode);
  350. wcd_clsh_force_iq_ctl(component, mode, true);
  351. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  352. wcd_clsh_set_flyback_current(component, mode);
  353. wcd_clsh_set_buck_mode(component, mode);
  354. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  355. wcd_clsh_set_hph_mode(component, mode);
  356. } else {
  357. wcd_clsh_set_hph_mode(component, CLS_H_NORMAL);
  358. /* set buck and flyback to Default Mode */
  359. wcd_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  360. wcd_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  361. wcd_clsh_force_iq_ctl(component, CLS_H_NORMAL, false);
  362. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  363. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  364. }
  365. }
  366. static void wcd_clsh_state_aux(struct snd_soc_component *component,
  367. struct wcd_clsh_cdc_info *clsh_d,
  368. u8 req_state, bool is_enable, int mode)
  369. {
  370. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  371. mode_to_str(mode), is_enable ? "enable" : "disable");
  372. if (is_enable) {
  373. wcd_clsh_set_buck_mode(component, mode);
  374. wcd_clsh_set_flyback_mode(component, mode);
  375. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  376. wcd_clsh_set_flyback_current(component, mode);
  377. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  378. } else {
  379. wcd_clsh_buck_ctrl(component, clsh_d, mode, false);
  380. wcd_clsh_flyback_ctrl(component, clsh_d, mode, false);
  381. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  382. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  383. }
  384. }
  385. static void wcd_clsh_state_ear(struct snd_soc_component *component,
  386. struct wcd_clsh_cdc_info *clsh_d,
  387. u8 req_state, bool is_enable, int mode)
  388. {
  389. dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
  390. mode_to_str(mode),
  391. is_enable ? "enable" : "disable");
  392. if (is_enable) {
  393. wcd_clsh_set_buck_regulator_mode(component, mode);
  394. wcd_clsh_set_flyback_mode(component, mode);
  395. wcd_clsh_force_iq_ctl(component, mode, true);
  396. wcd_clsh_flyback_ctrl(component, clsh_d, mode, true);
  397. wcd_clsh_set_flyback_current(component, mode);
  398. wcd_clsh_set_buck_mode(component, mode);
  399. wcd_clsh_buck_ctrl(component, clsh_d, mode, true);
  400. wcd_clsh_set_hph_mode(component, mode);
  401. } else {
  402. wcd_clsh_set_hph_mode(component, CLS_H_NORMAL);
  403. /* set buck and flyback to Default Mode */
  404. wcd_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  405. wcd_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
  406. wcd_clsh_force_iq_ctl(component, CLS_H_NORMAL, false);
  407. wcd_clsh_set_flyback_mode(component, CLS_H_NORMAL);
  408. wcd_clsh_set_buck_mode(component, CLS_H_NORMAL);
  409. }
  410. }
  411. static void wcd_clsh_state_err(struct snd_soc_component *component,
  412. struct wcd_clsh_cdc_info *clsh_d,
  413. u8 req_state, bool is_enable, int mode)
  414. {
  415. char msg[128];
  416. dev_err(component->dev,
  417. "%s Wrong request for class H state machine requested to %s %s\n",
  418. __func__, is_enable ? "enable" : "disable",
  419. state_to_str(req_state, msg, sizeof(msg)));
  420. }
  421. /*
  422. * Function: wcd_clsh_is_state_valid
  423. * Params: state
  424. * Description:
  425. * Provides information on valid states of Class H configuration
  426. */
  427. static bool wcd_clsh_is_state_valid(u8 state)
  428. {
  429. switch (state) {
  430. case WCD_CLSH_STATE_IDLE:
  431. case WCD_CLSH_STATE_EAR:
  432. case WCD_CLSH_STATE_HPHL:
  433. case WCD_CLSH_STATE_HPHR:
  434. case WCD_CLSH_STATE_HPH_ST:
  435. case WCD_CLSH_STATE_AUX:
  436. case WCD_CLSH_STATE_HPHL_AUX:
  437. case WCD_CLSH_STATE_HPHR_AUX:
  438. case WCD_CLSH_STATE_HPH_ST_AUX:
  439. case WCD_CLSH_STATE_EAR_AUX:
  440. case WCD_CLSH_STATE_HPHL_EAR:
  441. case WCD_CLSH_STATE_HPHR_EAR:
  442. case WCD_CLSH_STATE_HPH_ST_EAR:
  443. return true;
  444. default:
  445. return false;
  446. };
  447. }
  448. /*
  449. * Function: wcd_cls_h_fsm
  450. * Params: component, cdc_clsh_d, req_state, req_type, clsh_event
  451. * Description:
  452. * This function handles PRE DAC and POST DAC conditions of different devices
  453. * and updates class H configuration of different combination of devices
  454. * based on validity of their states. cdc_clsh_d will contain current
  455. * class h state information
  456. */
  457. void wcd_cls_h_fsm(struct snd_soc_component *component,
  458. struct wcd_clsh_cdc_info *cdc_clsh_d,
  459. u8 clsh_event, u8 req_state,
  460. int int_mode)
  461. {
  462. u8 old_state, new_state;
  463. char msg0[128], msg1[128];
  464. switch (clsh_event) {
  465. case WCD_CLSH_EVENT_PRE_DAC:
  466. old_state = cdc_clsh_d->state;
  467. new_state = old_state | req_state;
  468. if (!wcd_clsh_is_state_valid(new_state)) {
  469. dev_err(component->dev,
  470. "%s: Class-H not a valid new state: %s\n",
  471. __func__,
  472. state_to_str(new_state, msg0, sizeof(msg0)));
  473. return;
  474. }
  475. if (new_state == old_state) {
  476. dev_err(component->dev,
  477. "%s: Class-H already in requested state: %s\n",
  478. __func__,
  479. state_to_str(new_state, msg0, sizeof(msg0)));
  480. return;
  481. }
  482. cdc_clsh_d->state = new_state;
  483. wcd_clsh_set_int_mode(cdc_clsh_d, req_state, int_mode);
  484. (*clsh_state_fp[new_state]) (component, cdc_clsh_d, req_state,
  485. CLSH_REQ_ENABLE, int_mode);
  486. dev_dbg(component->dev,
  487. "%s: ClassH state transition from %s to %s\n",
  488. __func__, state_to_str(old_state, msg0, sizeof(msg0)),
  489. state_to_str(cdc_clsh_d->state, msg1, sizeof(msg1)));
  490. break;
  491. case WCD_CLSH_EVENT_POST_PA:
  492. old_state = cdc_clsh_d->state;
  493. new_state = old_state & (~req_state);
  494. if (new_state < NUM_CLSH_STATES) {
  495. if (!wcd_clsh_is_state_valid(old_state)) {
  496. dev_err(component->dev,
  497. "%s:Invalid old state:%s\n",
  498. __func__,
  499. state_to_str(old_state, msg0,
  500. sizeof(msg0)));
  501. return;
  502. }
  503. if (new_state == old_state) {
  504. dev_err(component->dev,
  505. "%s: Class-H already in requested state: %s\n",
  506. __func__,
  507. state_to_str(new_state, msg0,
  508. sizeof(msg0)));
  509. return;
  510. }
  511. (*clsh_state_fp[old_state]) (component, cdc_clsh_d,
  512. req_state, CLSH_REQ_DISABLE,
  513. int_mode);
  514. cdc_clsh_d->state = new_state;
  515. wcd_clsh_set_int_mode(cdc_clsh_d, req_state, CLS_NONE);
  516. dev_dbg(component->dev, "%s: ClassH state transition from %s to %s\n",
  517. __func__, state_to_str(old_state, msg0,
  518. sizeof(msg0)),
  519. state_to_str(cdc_clsh_d->state, msg1,
  520. sizeof(msg1)));
  521. }
  522. break;
  523. };
  524. }
  525. EXPORT_SYMBOL(wcd_cls_h_fsm);
  526. /*
  527. * wcd_cls_h_init: Called to init clsh info
  528. *
  529. * @clsh: pointer for clsh state information.
  530. */
  531. void wcd_cls_h_init(struct wcd_clsh_cdc_info *clsh)
  532. {
  533. int i;
  534. clsh->state = WCD_CLSH_STATE_IDLE;
  535. for (i = 0; i < NUM_CLSH_STATES; i++)
  536. clsh_state_fp[i] = wcd_clsh_state_err;
  537. clsh_state_fp[WCD_CLSH_STATE_EAR] = wcd_clsh_state_ear;
  538. clsh_state_fp[WCD_CLSH_STATE_HPHL] = wcd_clsh_state_hph_l;
  539. clsh_state_fp[WCD_CLSH_STATE_HPHR] = wcd_clsh_state_hph_r;
  540. clsh_state_fp[WCD_CLSH_STATE_HPH_ST] = wcd_clsh_state_hph_st;
  541. clsh_state_fp[WCD_CLSH_STATE_AUX] = wcd_clsh_state_aux;
  542. clsh_state_fp[WCD_CLSH_STATE_HPHL_AUX] = wcd_clsh_state_hph_aux;
  543. clsh_state_fp[WCD_CLSH_STATE_HPHR_AUX] = wcd_clsh_state_hph_aux;
  544. clsh_state_fp[WCD_CLSH_STATE_HPH_ST_AUX] =
  545. wcd_clsh_state_hph_aux;
  546. clsh_state_fp[WCD_CLSH_STATE_EAR_AUX] = wcd_clsh_state_ear_aux;
  547. clsh_state_fp[WCD_CLSH_STATE_HPHL_EAR] = wcd_clsh_state_hph_ear;
  548. clsh_state_fp[WCD_CLSH_STATE_HPHR_EAR] = wcd_clsh_state_hph_ear;
  549. clsh_state_fp[WCD_CLSH_STATE_HPH_ST_EAR] = wcd_clsh_state_hph_ear;
  550. /* Set interpolaotr modes to NONE */
  551. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_EAR, CLS_NONE);
  552. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_HPHL, CLS_NONE);
  553. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_HPHR, CLS_NONE);
  554. wcd_clsh_set_int_mode(clsh, WCD_CLSH_STATE_AUX, CLS_NONE);
  555. clsh->flyback_users = 0;
  556. clsh->buck_users = 0;
  557. }
  558. EXPORT_SYMBOL(wcd_cls_h_init);
  559. MODULE_DESCRIPTION("WCD Class-H Driver");
  560. MODULE_LICENSE("GPL v2");