ep92.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/init.h>
  6. #include <linux/delay.h>
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/i2c.h>
  10. #include <linux/slab.h>
  11. #include <linux/fs.h>
  12. #include <linux/debugfs.h>
  13. #include <linux/sysfs.h>
  14. #include <linux/kobject.h>
  15. #include <sound/core.h>
  16. #include <sound/pcm.h>
  17. #include <sound/pcm_params.h>
  18. #include <sound/tlv.h>
  19. #include <sound/soc.h>
  20. #include <linux/workqueue.h>
  21. #include "ep92.h"
  22. #define DRV_NAME "ep92_codec"
  23. #define EP92_POLL_INTERVAL_OFF_MSEC 200
  24. #define EP92_POLL_INTERVAL_ON_MSEC 20
  25. #define EP92_POLL_RUNOUT_MSEC 5000
  26. #define EP92_SYSFS_ENTRY_MAX_LEN 64
  27. #define EP92_HYST_CNT 5
  28. #define EP92_RATES (SNDRV_PCM_RATE_32000 |\
  29. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  30. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\
  31. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  32. #define EP92_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
  33. static const unsigned int ep92_samp_freq_table[8] = {
  34. 32000, 44100, 48000, 88200, 96000, 176400, 192000, 768000
  35. };
  36. static const unsigned int ep92_dsd_freq_table[4] = {
  37. 64, 128, 256, 0
  38. };
  39. /* EP92 register default values */
  40. static struct reg_default ep92_reg_defaults[] = {
  41. {EP92_BI_VENDOR_ID_0, 0x17},
  42. {EP92_BI_VENDOR_ID_1, 0x7A},
  43. {EP92_BI_DEVICE_ID_0, 0x94},
  44. {EP92_BI_DEVICE_ID_1, 0xA3},
  45. {EP92_BI_VERSION_NUM, 0x10},
  46. {EP92_BI_VERSION_YEAR, 0x09},
  47. {EP92_BI_VERSION_MONTH, 0x07},
  48. {EP92_BI_VERSION_DATE, 0x06},
  49. {EP92_BI_GENERAL_INFO_0, 0x00},
  50. {EP92_BI_GENERAL_INFO_1, 0x00},
  51. {EP92_BI_GENERAL_INFO_2, 0x00},
  52. {EP92_BI_GENERAL_INFO_3, 0x00},
  53. {EP92_BI_GENERAL_INFO_4, 0x00},
  54. {EP92_BI_GENERAL_INFO_5, 0x00},
  55. {EP92_BI_GENERAL_INFO_6, 0x00},
  56. {EP92_ISP_MODE_ENTER_ISP, 0x00},
  57. {EP92_GENERAL_CONTROL_0, 0x20},
  58. {EP92_GENERAL_CONTROL_1, 0x00},
  59. {EP92_GENERAL_CONTROL_2, 0x00},
  60. {EP92_GENERAL_CONTROL_3, 0x10},
  61. {EP92_GENERAL_CONTROL_4, 0x00},
  62. {EP92_CEC_EVENT_CODE, 0x00},
  63. {EP92_CEC_EVENT_PARAM_1, 0x00},
  64. {EP92_CEC_EVENT_PARAM_2, 0x00},
  65. {EP92_CEC_EVENT_PARAM_3, 0x00},
  66. {EP92_CEC_EVENT_PARAM_4, 0x00},
  67. {EP92_AUDIO_INFO_SYSTEM_STATUS_0, 0x00},
  68. {EP92_AUDIO_INFO_SYSTEM_STATUS_1, 0x00},
  69. {EP92_AUDIO_INFO_AUDIO_STATUS, 0x00},
  70. {EP92_AUDIO_INFO_CHANNEL_STATUS_0, 0x00},
  71. {EP92_AUDIO_INFO_CHANNEL_STATUS_1, 0x00},
  72. {EP92_AUDIO_INFO_CHANNEL_STATUS_2, 0x00},
  73. {EP92_AUDIO_INFO_CHANNEL_STATUS_3, 0x00},
  74. {EP92_AUDIO_INFO_CHANNEL_STATUS_4, 0x00},
  75. {EP92_AUDIO_INFO_ADO_INFO_FRAME_0, 0x00},
  76. {EP92_AUDIO_INFO_ADO_INFO_FRAME_1, 0x00},
  77. {EP92_AUDIO_INFO_ADO_INFO_FRAME_2, 0x00},
  78. {EP92_AUDIO_INFO_ADO_INFO_FRAME_3, 0x00},
  79. {EP92_AUDIO_INFO_ADO_INFO_FRAME_4, 0x00},
  80. {EP92_AUDIO_INFO_ADO_INFO_FRAME_5, 0x00},
  81. {EP92_OTHER_PACKETS_HDMI_VS_0, 0x00},
  82. {EP92_OTHER_PACKETS_HDMI_VS_1, 0x00},
  83. {EP92_OTHER_PACKETS_ACP_PACKET, 0x00},
  84. {EP92_OTHER_PACKETS_AVI_INFO_FRAME_0, 0x00},
  85. {EP92_OTHER_PACKETS_AVI_INFO_FRAME_1, 0x00},
  86. {EP92_OTHER_PACKETS_AVI_INFO_FRAME_2, 0x00},
  87. {EP92_OTHER_PACKETS_AVI_INFO_FRAME_3, 0x00},
  88. {EP92_OTHER_PACKETS_AVI_INFO_FRAME_4, 0x00},
  89. {EP92_OTHER_PACKETS_GC_PACKET_0, 0x00},
  90. {EP92_OTHER_PACKETS_GC_PACKET_1, 0x00},
  91. {EP92_OTHER_PACKETS_GC_PACKET_2, 0x00},
  92. };
  93. static bool ep92_volatile_register(struct device *dev, unsigned int reg)
  94. {
  95. /* do not cache register state in regmap */
  96. return true;
  97. }
  98. static bool ep92_writeable_registers(struct device *dev, unsigned int reg)
  99. {
  100. if (reg >= EP92_ISP_MODE_ENTER_ISP && reg <= EP92_GENERAL_CONTROL_4)
  101. return true;
  102. return false;
  103. }
  104. static bool ep92_readable_registers(struct device *dev, unsigned int reg)
  105. {
  106. if (reg >= EP92_BI_VENDOR_ID_0 && reg <= EP92_MAX_REGISTER_ADDR)
  107. return true;
  108. return false;
  109. }
  110. /* codec private data */
  111. struct ep92_pdata {
  112. struct regmap *regmap;
  113. struct snd_soc_component *component;
  114. struct timer_list timer;
  115. struct work_struct read_status_worker;
  116. int irq;
  117. int poll_trig;
  118. int poll_rem;
  119. int force_inactive;
  120. int hyst_tx_plug;
  121. int hyst_link_on0;
  122. int hyst_link_on1;
  123. int hyst_link_on2;
  124. int filt_tx_plug;
  125. int filt_link_on0;
  126. int filt_link_on1;
  127. int filt_link_on2;
  128. struct {
  129. u8 tx_info;
  130. u8 video_latency;
  131. } gi; /* General Info block */
  132. struct {
  133. u8 ctl;
  134. u8 rx_sel;
  135. u8 ctl2;
  136. u8 cec_volume;
  137. u8 link;
  138. } gc; /* General Control block */
  139. struct {
  140. u8 system_status_0;
  141. u8 system_status_1;
  142. u8 audio_status;
  143. u8 cs[5];
  144. u8 cc;
  145. u8 ca;
  146. } ai; /* Audio Info block */
  147. u8 old_mode;
  148. #if IS_ENABLED(CONFIG_DEBUG_FS)
  149. struct dentry *debugfs_dir;
  150. struct dentry *debugfs_file_wo;
  151. struct dentry *debugfs_file_ro;
  152. #endif /* CONFIG_DEBUG_FS */
  153. };
  154. struct ep92_mclk_cfg_info {
  155. uint32_t in_sample_rate;
  156. uint32_t out_mclk_freq;
  157. uint8_t mul_val;
  158. };
  159. #define EP92_MCLK_MUL_512 0x3
  160. #define EP92_MCLK_MUL_384 0x2
  161. #define EP92_MCLK_MUL_256 0x1
  162. #define EP92_MCLK_MUL_128 0x0
  163. #define EP92_MCLK_MUL_MASK 0x3
  164. /**
  165. * ep92_set_ext_mclk - Configure the mclk based on sample freq
  166. *
  167. * @codec: handle pointer to ep92 codec
  168. * @mclk_freq: mclk frequency to be set
  169. *
  170. * Returns 0 for sucess or appropriate negative error code
  171. */
  172. int ep92_set_ext_mclk(struct snd_soc_codec *codec, uint32_t mclk_freq)
  173. {
  174. unsigned int samp_freq = 0;
  175. struct ep92_pdata *ep92 = NULL;
  176. uint8_t value = 0;
  177. int ret = 0;
  178. if (!codec)
  179. return -EINVAL;
  180. ep92 = snd_soc_codec_get_drvdata(codec);
  181. samp_freq = ep92_samp_freq_table[(ep92->ai.audio_status) &
  182. EP92_AI_RATE_MASK];
  183. if (!mclk_freq || (mclk_freq % samp_freq)) {
  184. pr_err("%s incompatbile mclk:%u and sample freq:%u\n",
  185. __func__, mclk_freq, samp_freq);
  186. return -EINVAL;
  187. }
  188. switch (mclk_freq / samp_freq) {
  189. case 512:
  190. value = EP92_MCLK_MUL_512;
  191. break;
  192. case 384:
  193. value = EP92_MCLK_MUL_384;
  194. break;
  195. case 256:
  196. value = EP92_MCLK_MUL_256;
  197. break;
  198. case 128:
  199. value = EP92_MCLK_MUL_128;
  200. break;
  201. default:
  202. dev_err(codec->dev, "unsupported mclk:%u for sample freq:%u\n",
  203. mclk_freq, samp_freq);
  204. return -EINVAL;
  205. }
  206. pr_debug("%s mclk:%u, in sample freq:%u, write reg:0x%02x val:0x%02x\n",
  207. __func__, mclk_freq, samp_freq,
  208. EP92_GENERAL_CONTROL_2, EP92_MCLK_MUL_MASK & value);
  209. ret = snd_soc_update_bits(codec, EP92_GENERAL_CONTROL_2,
  210. EP92_MCLK_MUL_MASK, value);
  211. return (((ret == 0) || (ret == 1)) ? 0 : ret);
  212. }
  213. EXPORT_SYMBOL(ep92_set_ext_mclk);
  214. #if IS_ENABLED(CONFIG_DEBUG_FS)
  215. static int debugfs_codec_open_op(struct inode *inode, struct file *file)
  216. {
  217. file->private_data = inode->i_private;
  218. return 0;
  219. }
  220. static int debugfs_get_parameters(char *buf, u32 *param1, int num_of_par)
  221. {
  222. char *token;
  223. int base, cnt;
  224. token = strsep(&buf, " ");
  225. for (cnt = 0; cnt < num_of_par; cnt++) {
  226. if (token) {
  227. if ((token[1] == 'x') || (token[1] == 'X'))
  228. base = 16;
  229. else
  230. base = 10;
  231. if (kstrtou32(token, base, &param1[cnt]) != 0)
  232. return -EINVAL;
  233. token = strsep(&buf, " ");
  234. } else {
  235. return -EINVAL;
  236. }
  237. }
  238. return 0;
  239. }
  240. static ssize_t debugfs_codec_write_op(struct file *filp,
  241. const char __user *ubuf, size_t cnt, loff_t *ppos)
  242. {
  243. struct ep92_pdata *ep92 = (struct ep92_pdata *) filp->private_data;
  244. struct snd_soc_component *component = ep92->component;
  245. char lbuf[32];
  246. int rc;
  247. u32 param[2];
  248. if (!component)
  249. return -ENODEV;
  250. if (!filp || !ppos || !ubuf)
  251. return -EINVAL;
  252. if (cnt > sizeof(lbuf) - 1)
  253. return -EINVAL;
  254. rc = copy_from_user(lbuf, ubuf, cnt);
  255. if (rc)
  256. return -EFAULT;
  257. lbuf[cnt] = '\0';
  258. rc = debugfs_get_parameters(lbuf, param, 2);
  259. if ((param[0] < EP92_ISP_MODE_ENTER_ISP)
  260. || (param[0] > EP92_GENERAL_CONTROL_4)) {
  261. dev_err(component->dev, "%s: reg address 0x%02X out of range\n",
  262. __func__, param[0]);
  263. return -EINVAL;
  264. }
  265. if ((param[1] < 0) || (param[1] > 255)) {
  266. dev_err(component->dev, "%s: reg data 0x%02X out of range\n",
  267. __func__, param[1]);
  268. return -EINVAL;
  269. }
  270. if (rc == 0) {
  271. rc = cnt;
  272. dev_info(component->dev, "%s: reg[0x%02X]=0x%02X\n",
  273. __func__, param[0], param[1]);
  274. snd_soc_component_write(component, param[0], param[1]);
  275. } else {
  276. dev_err(component->dev, "%s: write to register addr=0x%02X failed\n",
  277. __func__, param[0]);
  278. }
  279. return rc;
  280. }
  281. static ssize_t debugfs_ep92_reg_show(struct snd_soc_component *component,
  282. char __user *ubuf, size_t count, loff_t *ppos)
  283. {
  284. int i, reg_val, len;
  285. ssize_t total = 0;
  286. char tmp_buf[20];
  287. if (!ubuf || !ppos || !component || *ppos < 0)
  288. return -EINVAL;
  289. for (i = (int) *ppos / 11; i <= EP92_MAX_REGISTER_ADDR; i++) {
  290. reg_val = snd_soc_component_read32(component, i);
  291. len = snprintf(tmp_buf, 20, "0x%02X: 0x%02X\n", i,
  292. (reg_val & 0xFF));
  293. if ((total + len) > count)
  294. break;
  295. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  296. dev_err(component->dev, "%s: fail to copy reg dump\n",
  297. __func__);
  298. total = -EFAULT;
  299. goto copy_err;
  300. }
  301. *ppos += len;
  302. total += len;
  303. }
  304. copy_err:
  305. return total;
  306. }
  307. static ssize_t debugfs_codec_read_op(struct file *filp,
  308. char __user *ubuf, size_t cnt, loff_t *ppos)
  309. {
  310. struct ep92_pdata *ep92 = (struct ep92_pdata *) filp->private_data;
  311. struct snd_soc_component *component = ep92->component;
  312. ssize_t ret_cnt;
  313. if (!component)
  314. return -ENODEV;
  315. if (!filp || !ppos || !ubuf || *ppos < 0)
  316. return -EINVAL;
  317. ret_cnt = debugfs_ep92_reg_show(component, ubuf, cnt, ppos);
  318. return ret_cnt;
  319. }
  320. static const struct file_operations debugfs_codec_ops = {
  321. .open = debugfs_codec_open_op,
  322. .write = debugfs_codec_write_op,
  323. .read = debugfs_codec_read_op,
  324. };
  325. #endif /* CONFIG_DEBUG_FS */
  326. static int ep92_send_uevent(struct ep92_pdata *ep92, char *event)
  327. {
  328. char *env[] = { event, NULL };
  329. if (!event || !ep92)
  330. return -EINVAL;
  331. if (!ep92->component)
  332. return -ENODEV;
  333. return kobject_uevent_env(&ep92->component->dev->kobj,
  334. KOBJ_CHANGE, env);
  335. }
  336. static int ep92_startup(struct snd_pcm_substream *substream,
  337. struct snd_soc_dai *dai)
  338. {
  339. return 0;
  340. }
  341. static void ep92_shutdown(struct snd_pcm_substream *substream,
  342. struct snd_soc_dai *dai)
  343. {
  344. }
  345. static int ep92_hw_params(struct snd_pcm_substream *substream,
  346. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  347. {
  348. return 0;
  349. }
  350. static struct snd_soc_dai_ops ep92_dai_ops = {
  351. .startup = ep92_startup,
  352. .shutdown = ep92_shutdown,
  353. .hw_params = ep92_hw_params,
  354. };
  355. static struct snd_soc_dai_driver ep92_dai[] = {
  356. {
  357. .name = "ep92-hdmi",
  358. .id = 1,
  359. .capture = {
  360. .stream_name = "HDMI Capture",
  361. .rate_max = 192000,
  362. .rate_min = 32000,
  363. .channels_min = 1,
  364. .channels_max = 8,
  365. .rates = EP92_RATES,
  366. .formats = EP92_FORMATS,
  367. },
  368. .ops = &ep92_dai_ops, /* callbacks */
  369. },
  370. {
  371. .name = "ep92-arc",
  372. .id = 2,
  373. .capture = {
  374. .stream_name = "ARC Capture",
  375. .rate_max = 192000,
  376. .rate_min = 32000,
  377. .channels_min = 1,
  378. .channels_max = 2,
  379. .rates = EP92_RATES,
  380. .formats = EP92_FORMATS,
  381. },
  382. .ops = &ep92_dai_ops, /* callbacks */
  383. },
  384. };
  385. static void ep92_read_general_control(struct snd_soc_component *component,
  386. struct ep92_pdata *ep92)
  387. {
  388. u8 old, change;
  389. int val;
  390. old = ep92->gi.tx_info;
  391. ep92->gi.tx_info = snd_soc_component_read32(component,
  392. EP92_BI_GENERAL_INFO_0);
  393. if (ep92->gi.tx_info == 0xff) {
  394. dev_dbg(component->dev, "ep92 EP92_BI_GENERAL_INFO_0 read 0xff\n");
  395. ep92->gi.tx_info = old;
  396. }
  397. /* implement hysteresis to prevent events on glitches */
  398. if (ep92->gi.tx_info & EP92_GI_TX_HOT_PLUG_MASK) {
  399. if (ep92->hyst_tx_plug < EP92_HYST_CNT) {
  400. ep92->hyst_tx_plug++;
  401. if ((ep92->hyst_tx_plug == EP92_HYST_CNT) &&
  402. (ep92->filt_tx_plug == 0)) {
  403. ep92->filt_tx_plug = 1;
  404. dev_dbg(component->dev, "ep92 out_plug changed to 1\n");
  405. ep92_send_uevent(ep92,
  406. "EP92EVT_OUT_PLUG=CONNECTED");
  407. }
  408. }
  409. } else {
  410. if (ep92->hyst_tx_plug > 0) {
  411. ep92->hyst_tx_plug--;
  412. if ((ep92->hyst_tx_plug == 0) &&
  413. (ep92->filt_tx_plug == 1)) {
  414. ep92->filt_tx_plug = 0;
  415. dev_dbg(component->dev, "ep92 out_plug changed to 0\n");
  416. ep92_send_uevent(ep92,
  417. "EP92EVT_OUT_PLUG=DISCONNECTED");
  418. }
  419. }
  420. }
  421. old = ep92->gi.video_latency;
  422. ep92->gi.video_latency = snd_soc_component_read32(component,
  423. EP92_BI_GENERAL_INFO_4);
  424. if (ep92->gi.video_latency == 0xff) {
  425. dev_dbg(component->dev, "ep92 EP92_BI_GENERAL_INFO_4 read 0xff\n");
  426. ep92->gi.video_latency = old;
  427. }
  428. change = ep92->gi.video_latency ^ old;
  429. if (change & EP92_GI_VIDEO_LATENCY_MASK) {
  430. val = ep92->gi.video_latency;
  431. if (val > 0)
  432. val = (val - 1) * 2;
  433. dev_dbg(component->dev, "ep92 video latency changed to %d\n", val);
  434. ep92_send_uevent(ep92, "EP92EVT_VIDEO_LATENCY=CHANGED");
  435. }
  436. old = ep92->gc.ctl;
  437. ep92->gc.ctl = snd_soc_component_read32(component,
  438. EP92_GENERAL_CONTROL_0);
  439. if (ep92->gc.ctl == 0xff) {
  440. dev_dbg(component->dev, "ep92 EP92_GENERAL_CONTROL_0 read 0xff\n");
  441. ep92->gc.ctl = old;
  442. }
  443. change = ep92->gc.ctl ^ old;
  444. if (change & EP92_GC_POWER_MASK) {
  445. val = (ep92->gc.ctl >> EP92_GC_POWER_SHIFT) &
  446. EP92_2CHOICE_MASK;
  447. dev_dbg(component->dev, "ep92 power changed to %d\n", val);
  448. if (val)
  449. ep92_send_uevent(ep92, "EP92EVT_POWER=ON");
  450. else
  451. ep92_send_uevent(ep92, "EP92EVT_POWER=OFF");
  452. }
  453. if (change & EP92_GC_AUDIO_PATH_MASK) {
  454. val = (ep92->gc.ctl >> EP92_GC_AUDIO_PATH_SHIFT) &
  455. EP92_2CHOICE_MASK;
  456. dev_dbg(component->dev, "ep92 audio_path changed to %d\n", val);
  457. if (val)
  458. ep92_send_uevent(ep92, "EP92EVT_AUDIO_PATH=TV");
  459. else
  460. ep92_send_uevent(ep92, "EP92EVT_AUDIO_PATH=SPEAKER");
  461. }
  462. if (change & EP92_GC_CEC_MUTE_MASK) {
  463. val = (ep92->gc.ctl >> EP92_GC_CEC_MUTE_SHIFT) &
  464. EP92_2CHOICE_MASK;
  465. dev_dbg(component->dev, "ep92 cec_mute changed to %d\n", val);
  466. if (val)
  467. ep92_send_uevent(ep92, "EP92EVT_CEC_MUTE=NORMAL");
  468. else
  469. ep92_send_uevent(ep92, "EP92EVT_CEC_MUTE=MUTED");
  470. }
  471. if (change & EP92_GC_ARC_EN_MASK) {
  472. val = ep92->gc.ctl & EP92_2CHOICE_MASK;
  473. dev_dbg(component->dev, "ep92 arc_en changed to %d\n", val);
  474. if (val)
  475. ep92_send_uevent(ep92, "EP92EVT_ARC_EN=ON");
  476. else
  477. ep92_send_uevent(ep92, "EP92EVT_ARC_EN=OFF");
  478. }
  479. old = ep92->gc.rx_sel;
  480. ep92->gc.rx_sel = snd_soc_component_read32(component,
  481. EP92_GENERAL_CONTROL_1);
  482. if (ep92->gc.rx_sel == 0xff) {
  483. dev_dbg(component->dev, "ep92 EP92_GENERAL_CONTROL_1 read 0xff\n");
  484. ep92->gc.rx_sel = old;
  485. }
  486. change = ep92->gc.rx_sel ^ old;
  487. if (change & EP92_GC_RX_SEL_MASK) {
  488. val = ep92->gc.rx_sel & EP92_GC_RX_SEL_MASK;
  489. dev_dbg(component->dev, "ep92 rx_sel changed to %d\n", val);
  490. ep92_send_uevent(ep92, "EP92EVT_SRC_SEL=CHANGED");
  491. }
  492. old = ep92->gc.cec_volume;
  493. ep92->gc.cec_volume = snd_soc_component_read32(component,
  494. EP92_GENERAL_CONTROL_3);
  495. if (ep92->gc.cec_volume == 0xff) {
  496. dev_dbg(component->dev, "ep92 EP92_GENERAL_CONTROL_3 read 0xff\n");
  497. ep92->gc.cec_volume = old;
  498. }
  499. change = ep92->gc.cec_volume ^ old;
  500. if (change & EP92_GC_CEC_VOLUME_MASK) {
  501. val = ep92->gc.cec_volume & EP92_GC_CEC_VOLUME_MASK;
  502. dev_dbg(component->dev, "ep92 cec_volume changed to %d\n", val);
  503. ep92_send_uevent(ep92, "EP92EVT_CEC_VOLUME=CHANGED");
  504. }
  505. old = ep92->gc.link;
  506. ep92->gc.link = snd_soc_component_read32(component,
  507. EP92_GENERAL_CONTROL_4);
  508. if (ep92->gc.link == 0xff) {
  509. dev_dbg(component->dev, "ep92 EP92_GENERAL_CONTROL_4 read 0xff\n");
  510. ep92->gc.link = old;
  511. }
  512. /* implement hysteresis to prevent events on glitches */
  513. if (ep92->gc.link & EP92_GC_LINK_ON0_MASK) {
  514. if (ep92->hyst_link_on0 < EP92_HYST_CNT) {
  515. ep92->hyst_link_on0++;
  516. if ((ep92->hyst_link_on0 == EP92_HYST_CNT) &&
  517. (ep92->filt_link_on0 == 0)) {
  518. ep92->filt_link_on0 = 1;
  519. dev_dbg(component->dev, "ep92 link_on0 changed to 1\n");
  520. ep92_send_uevent(ep92,
  521. "EP92EVT_LINK_ON0=CONNECTED");
  522. }
  523. }
  524. } else {
  525. if (ep92->hyst_link_on0 > 0) {
  526. ep92->hyst_link_on0--;
  527. if ((ep92->hyst_link_on0 == 0) &&
  528. (ep92->filt_link_on0 == 1)) {
  529. ep92->filt_link_on0 = 0;
  530. dev_dbg(component->dev, "ep92 link_on0 changed to 0\n");
  531. ep92_send_uevent(ep92,
  532. "EP92EVT_LINK_ON0=DISCONNECTED");
  533. }
  534. }
  535. }
  536. /* implement hysteresis to prevent events on glitches */
  537. if (ep92->gc.link & EP92_GC_LINK_ON1_MASK) {
  538. if (ep92->hyst_link_on1 < EP92_HYST_CNT) {
  539. ep92->hyst_link_on1++;
  540. if ((ep92->hyst_link_on1 == EP92_HYST_CNT) &&
  541. (ep92->filt_link_on1 == 0)) {
  542. ep92->filt_link_on1 = 1;
  543. dev_dbg(component->dev, "ep92 link_on1 changed to 1\n");
  544. ep92_send_uevent(ep92,
  545. "EP92EVT_LINK_ON1=CONNECTED");
  546. }
  547. }
  548. } else {
  549. if (ep92->hyst_link_on1 > 0) {
  550. ep92->hyst_link_on1--;
  551. if ((ep92->hyst_link_on1 == 0) &&
  552. (ep92->filt_link_on1 == 1)) {
  553. ep92->filt_link_on1 = 0;
  554. dev_dbg(component->dev, "ep92 link_on1 changed to 0\n");
  555. ep92_send_uevent(ep92,
  556. "EP92EVT_LINK_ON1=DISCONNECTED");
  557. }
  558. }
  559. }
  560. /* implement hysteresis to prevent events on glitches */
  561. if (ep92->gc.link & EP92_GC_LINK_ON2_MASK) {
  562. if (ep92->hyst_link_on2 < EP92_HYST_CNT) {
  563. ep92->hyst_link_on2++;
  564. if ((ep92->hyst_link_on2 == EP92_HYST_CNT) &&
  565. (ep92->filt_link_on2 == 0)) {
  566. ep92->filt_link_on2 = 1;
  567. dev_dbg(component->dev, "ep92 link_on2 changed to 1\n");
  568. ep92_send_uevent(ep92,
  569. "EP92EVT_LINK_ON2=CONNECTED");
  570. }
  571. }
  572. } else {
  573. if (ep92->hyst_link_on2 > 0) {
  574. ep92->hyst_link_on2--;
  575. if ((ep92->hyst_link_on2 == 0) &&
  576. (ep92->filt_link_on2 == 1)) {
  577. ep92->filt_link_on2 = 0;
  578. dev_dbg(component->dev, "ep92 link_on2 changed to 0\n");
  579. ep92_send_uevent(ep92,
  580. "EP92EVT_LINK_ON2=DISCONNECTED");
  581. }
  582. }
  583. }
  584. }
  585. static void ep92_read_audio_info(struct snd_soc_component *component,
  586. struct ep92_pdata *ep92)
  587. {
  588. u8 old, change;
  589. u8 new_mode;
  590. bool send_uevent = false;
  591. old = ep92->ai.system_status_0;
  592. ep92->ai.system_status_0 = snd_soc_component_read32(component,
  593. EP92_AUDIO_INFO_SYSTEM_STATUS_0);
  594. if (ep92->ai.system_status_0 == 0xff) {
  595. dev_dbg(component->dev, "ep92 EP92_AUDIO_INFO_SYSTEM_STATUS_0 read 0xff\n");
  596. ep92->ai.system_status_0 = old;
  597. }
  598. change = ep92->ai.system_status_0 ^ old;
  599. if (change & EP92_AI_MCLK_ON_MASK) {
  600. dev_dbg(component->dev, "ep92 status changed to %d\n",
  601. (ep92->ai.system_status_0 >> EP92_AI_MCLK_ON_SHIFT) &
  602. EP92_2CHOICE_MASK);
  603. send_uevent = true;
  604. }
  605. if (change & EP92_AI_AVMUTE_MASK) {
  606. dev_dbg(component->dev, "ep92 avmute changed to %d\n",
  607. (ep92->ai.system_status_0 >> EP92_AI_AVMUTE_SHIFT) &
  608. EP92_2CHOICE_MASK);
  609. send_uevent = true;
  610. }
  611. if (change & EP92_AI_LAYOUT_MASK) {
  612. dev_dbg(component->dev, "ep92 layout changed to %d\n",
  613. (ep92->ai.system_status_0) & EP92_2CHOICE_MASK);
  614. send_uevent = true;
  615. }
  616. old = ep92->ai.system_status_1;
  617. ep92->ai.system_status_1 = snd_soc_read(codec,
  618. EP92_AUDIO_INFO_SYSTEM_STATUS_1);
  619. if (ep92->ai.system_status_1 == 0xff) {
  620. dev_dbg(codec->dev,
  621. "ep92 EP92_AUDIO_INFO_SYSTEM_STATUS_1 read 0xff\n");
  622. ep92->ai.system_status_1 = old;
  623. }
  624. change = ep92->ai.system_status_1 ^ old;
  625. if (change & EP92_AI_DSD_RATE_MASK) {
  626. dev_dbg(codec->dev, "ep92 dsd rate changed to %d\n",
  627. ep92_dsd_freq_table[(ep92->ai.system_status_1 &
  628. EP92_AI_DSD_RATE_MASK)
  629. >> EP92_AI_DSD_RATE_SHIFT]);
  630. send_uevent = true;
  631. }
  632. old = ep92->ai.audio_status;
  633. ep92->ai.audio_status = snd_soc_component_read32(component,
  634. EP92_AUDIO_INFO_AUDIO_STATUS);
  635. if (ep92->ai.audio_status == 0xff) {
  636. dev_dbg(component->dev, "ep92 EP92_AUDIO_INFO_AUDIO_STATUS read 0xff\n");
  637. ep92->ai.audio_status = old;
  638. }
  639. change = ep92->ai.audio_status ^ old;
  640. if (change & EP92_AI_RATE_MASK) {
  641. dev_dbg(component->dev, "ep92 rate changed to %d\n",
  642. ep92_samp_freq_table[(ep92->ai.audio_status) &
  643. EP92_AI_RATE_MASK]);
  644. send_uevent = true;
  645. }
  646. old = ep92->ai.cs[0];
  647. ep92->ai.cs[0] = snd_soc_component_read32(component,
  648. EP92_AUDIO_INFO_CHANNEL_STATUS_0);
  649. if (ep92->ai.cs[0] == 0xff) {
  650. dev_dbg(component->dev, "ep92 EP92_AUDIO_INFO_CHANNEL_STATUS_0 read 0xff\n");
  651. ep92->ai.cs[0] = old;
  652. }
  653. change = ep92->ai.cs[0] ^ old;
  654. if (change & EP92_AI_PREEMPH_MASK) {
  655. dev_dbg(component->dev, "ep92 preemph changed to %d\n",
  656. (ep92->ai.cs[0] & EP92_AI_PREEMPH_MASK) >>
  657. EP92_AI_PREEMPH_SHIFT);
  658. send_uevent = true;
  659. }
  660. new_mode = ep92->old_mode;
  661. if (ep92->ai.audio_status & EP92_AI_DSD_ADO_MASK)
  662. new_mode = 2; /* One bit audio */
  663. else if (ep92->ai.audio_status & EP92_AI_STD_ADO_MASK) {
  664. if (ep92->ai.cs[0] & EP92_AI_NPCM_MASK)
  665. new_mode = 1; /* Compr */
  666. else
  667. new_mode = 0; /* LPCM */
  668. } else if (ep92->ai.audio_status & EP92_AI_HBR_ADO_MASK)
  669. new_mode = 1; /* Compr */
  670. if (ep92->old_mode != new_mode) {
  671. dev_dbg(component->dev, "ep92 mode changed to %d\n", new_mode);
  672. send_uevent = true;
  673. }
  674. ep92->old_mode = new_mode;
  675. old = ep92->ai.cc;
  676. ep92->ai.cc = snd_soc_component_read32(component,
  677. EP92_AUDIO_INFO_ADO_INFO_FRAME_1);
  678. if (ep92->ai.cc == 0xff) {
  679. dev_dbg(component->dev, "ep92 EP92_AUDIO_INFO_ADO_INFO_FRAME_1 read 0xff\n");
  680. ep92->ai.cc = old;
  681. }
  682. change = ep92->ai.cc ^ old;
  683. if (change & EP92_AI_CH_COUNT_MASK) {
  684. dev_dbg(component->dev, "ep92 ch_count changed to %d (%d)\n",
  685. ep92->ai.cc & EP92_AI_CH_COUNT_MASK,
  686. (ep92->ai.cc & EP92_AI_CH_COUNT_MASK) == 0 ? 0 :
  687. (ep92->ai.cc & EP92_AI_CH_COUNT_MASK) + 1);
  688. send_uevent = true;
  689. }
  690. old = ep92->ai.ca;
  691. ep92->ai.ca = snd_soc_component_read32(component,
  692. EP92_AUDIO_INFO_ADO_INFO_FRAME_4);
  693. if (ep92->ai.ca == 0xff) {
  694. dev_dbg(component->dev, "ep92 EP92_AUDIO_INFO_ADO_INFO_FRAME_4 read 0xff\n");
  695. ep92->ai.ca = old;
  696. }
  697. change = ep92->ai.ca ^ old;
  698. if (change & EP92_AI_CH_ALLOC_MASK) {
  699. dev_dbg(component->dev, "ep92 ch_alloc changed to 0x%02x\n",
  700. (ep92->ai.ca) & EP92_AI_CH_ALLOC_MASK);
  701. send_uevent = true;
  702. }
  703. if (send_uevent)
  704. ep92_send_uevent(ep92, "EP92EVT_AUDIO=MEDIA_CONFIG_CHANGE");
  705. }
  706. static void ep92_init(struct snd_soc_component *component,
  707. struct ep92_pdata *ep92)
  708. {
  709. int reg0 = 0;
  710. int reg1 = 0;
  711. int reg2 = 0;
  712. int reg3 = 0;
  713. if (!ep92 || !component)
  714. return;
  715. reg0 = snd_soc_component_read32(component, EP92_BI_VERSION_YEAR);
  716. reg1 = snd_soc_component_read32(component, EP92_BI_VERSION_MONTH);
  717. reg2 = snd_soc_component_read32(component, EP92_BI_VERSION_DATE);
  718. reg3 = snd_soc_component_read32(component, EP92_BI_VERSION_NUM);
  719. dev_info(compoent->dev, "ep92 version info %02d/%02d/%02d %d\n",
  720. reg0, reg1, reg2, reg3);
  721. /* update the format information in mixer controls */
  722. ep92_read_general_control(component, ep92);
  723. ep92_read_audio_info(component, ep92);
  724. }
  725. static int ep92_probe(struct snd_soc_component *component)
  726. {
  727. struct ep92_pdata *ep92 = snd_soc_component_get_drvdata(component);
  728. ep92->component = component;
  729. ep92_init(component, ep92);
  730. /* start polling when codec is registered */
  731. mod_timer(&ep92->timer, jiffies +
  732. msecs_to_jiffies(EP92_POLL_INTERVAL_OFF_MSEC));
  733. return 0;
  734. }
  735. static void ep92_remove(struct snd_soc_component *component)
  736. {
  737. return;
  738. }
  739. static const struct snd_soc_component_driver soc_codec_drv_ep92 = {
  740. .name = DRV_NAME,
  741. .probe = ep92_probe,
  742. .remove = ep92_remove,
  743. };
  744. static struct regmap_config ep92_regmap_config = {
  745. .reg_bits = 8,
  746. .val_bits = 8,
  747. .cache_type = REGCACHE_RBTREE,
  748. .reg_defaults = ep92_reg_defaults,
  749. .num_reg_defaults = ARRAY_SIZE(ep92_reg_defaults),
  750. .max_register = EP92_MAX_REGISTER_ADDR,
  751. .volatile_reg = ep92_volatile_register,
  752. .writeable_reg = ep92_writeable_registers,
  753. .readable_reg = ep92_readable_registers,
  754. };
  755. void ep92_read_status(struct work_struct *work)
  756. {
  757. struct ep92_pdata *ep92 = container_of(work, struct ep92_pdata,
  758. read_status_worker);
  759. struct snd_soc_component *component = ep92->component;
  760. u8 val;
  761. /* No polling before component is initialized */
  762. if (component == NULL)
  763. return;
  764. if (ep92->force_inactive)
  765. return;
  766. /* check ADO_CHF that is set when audio format has changed */
  767. val = snd_soc_component_read32(component, EP92_BI_GENERAL_INFO_1);
  768. if (val == 0xff) {
  769. /* workaround for Nak'ed first read */
  770. val = snd_soc_component_read32(component,
  771. EP92_BI_GENERAL_INFO_1);
  772. if (val == 0xff)
  773. return; /* assume device not present */
  774. }
  775. if (val & EP92_GI_ADO_CHF_MASK)
  776. dev_dbg(component->dev, "ep92 audio mode change trigger.\n");
  777. if (val & EP92_GI_CEC_ECF_MASK)
  778. dev_dbg(component->dev, "ep92 CEC change trigger.\n");
  779. /* check for general control changes */
  780. ep92_read_general_control(component, ep92);
  781. /* update the format information in mixer controls */
  782. ep92_read_audio_info(component, ep92);
  783. }
  784. static irqreturn_t ep92_irq(int irq, void *data)
  785. {
  786. struct ep92_pdata *ep92 = data;
  787. struct snd_soc_component *component = ep92->component;
  788. /* Treat interrupt before component is initialized as spurious */
  789. if (component == NULL)
  790. return IRQ_NONE;
  791. dev_dbg(component->dev, "ep92_interrupt\n");
  792. ep92->poll_trig = 1;
  793. mod_timer(&ep92->timer, jiffies +
  794. msecs_to_jiffies(EP92_POLL_INTERVAL_ON_MSEC));
  795. schedule_work(&ep92->read_status_worker);
  796. return IRQ_HANDLED;
  797. };
  798. void ep92_poll_status(struct timer_list *t)
  799. {
  800. struct ep92_pdata *ep92 = from_timer(ep92, t, timer);
  801. struct snd_soc_component *component = ep92->component;
  802. if (ep92->force_inactive)
  803. return;
  804. /* if no IRQ is configured, always keep on polling */
  805. if (ep92->irq == 0)
  806. ep92->poll_rem = EP92_POLL_RUNOUT_MSEC;
  807. /* on interrupt, start polling for some time */
  808. if (ep92->poll_trig) {
  809. if (ep92->poll_rem == 0)
  810. dev_info(component->dev, "status checking activated\n");
  811. ep92->poll_trig = 0;
  812. ep92->poll_rem = EP92_POLL_RUNOUT_MSEC;
  813. }
  814. /*
  815. * If power_on == 0, poll only until poll_rem reaches zero and stop.
  816. * This allows to system to go to low power sleep mode.
  817. * Otherwise (power_on == 1) always re-arm timer to keep on polling.
  818. */
  819. if ((ep92->gc.ctl & EP92_GC_POWER_MASK) == 0) {
  820. if (ep92->poll_rem) {
  821. mod_timer(&ep92->timer, jiffies +
  822. msecs_to_jiffies(EP92_POLL_INTERVAL_OFF_MSEC));
  823. if (ep92->poll_rem > EP92_POLL_INTERVAL_OFF_MSEC) {
  824. ep92->poll_rem -= EP92_POLL_INTERVAL_OFF_MSEC;
  825. } else {
  826. dev_info(component->dev, "status checking stopped\n");
  827. ep92->poll_rem = 0;
  828. }
  829. }
  830. } else {
  831. ep92->poll_rem = EP92_POLL_RUNOUT_MSEC;
  832. mod_timer(&ep92->timer, jiffies +
  833. msecs_to_jiffies(EP92_POLL_INTERVAL_ON_MSEC));
  834. }
  835. schedule_work(&ep92->read_status_worker);
  836. }
  837. static const struct of_device_id ep92_of_match[] = {
  838. { .compatible = "explore,ep92a6", },
  839. { }
  840. };
  841. MODULE_DEVICE_TABLE(of, ep92_of_match);
  842. static ssize_t ep92_sysfs_rda_chipid(struct device *dev,
  843. struct device_attribute *attr, char *buf)
  844. {
  845. ssize_t ret = 0;
  846. int reg0 = 0;
  847. int reg1 = 0;
  848. int reg2 = 0;
  849. int reg3 = 0;
  850. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  851. if (!ep92 || !ep92->component) {
  852. dev_err(dev, "%s: device error\n", __func__);
  853. return -ENODEV;
  854. }
  855. reg0 = snd_soc_component_read32(ep92->component, EP92_BI_VENDOR_ID_0);
  856. reg1 = snd_soc_component_read32(ep92->component, EP92_BI_VENDOR_ID_1);
  857. reg2 = snd_soc_component_read32(ep92->component, EP92_BI_DEVICE_ID_0);
  858. reg3 = snd_soc_component_read32(ep92->component, EP92_BI_DEVICE_ID_1);
  859. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%02x%02x/%02x%02x\n",
  860. reg0, reg1, reg2, reg3);
  861. dev_dbg(dev, "%s: '%s'\n", __func__, buf);
  862. return ret;
  863. }
  864. static ssize_t ep92_sysfs_rda_version(struct device *dev,
  865. struct device_attribute *attr, char *buf)
  866. {
  867. ssize_t ret = 0;
  868. int reg0 = 0;
  869. int reg1 = 0;
  870. int reg2 = 0;
  871. int reg3 = 0;
  872. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  873. if (!ep92 || !ep92->component) {
  874. dev_err(dev, "%s: device error\n", __func__);
  875. return -ENODEV;
  876. }
  877. reg0 = snd_soc_component_read32(ep92->component,
  878. EP92_BI_VERSION_YEAR);
  879. reg1 = snd_soc_component_read32(ep92->component,
  880. EP92_BI_VERSION_MONTH);
  881. reg2 = snd_soc_component_read32(ep92->component,
  882. EP92_BI_VERSION_DATE);
  883. reg3 = snd_soc_component_read32(ep92->component,
  884. EP92_BI_VERSION_NUM);
  885. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%02d/%02d/%02d %d\n",
  886. reg0, reg1, reg2, reg3);
  887. dev_dbg(dev, "%s: '%s'\n", __func__, buf);
  888. return ret;
  889. }
  890. static ssize_t ep92_sysfs_rda_audio_state(struct device *dev,
  891. struct device_attribute *attr, char *buf)
  892. {
  893. ssize_t ret;
  894. int val;
  895. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  896. if (!ep92 || !ep92->component) {
  897. dev_err(dev, "%s: device error\n", __func__);
  898. return -ENODEV;
  899. }
  900. val = (ep92->ai.system_status_0 & EP92_AI_MCLK_ON_MASK) >>
  901. EP92_AI_MCLK_ON_SHIFT;
  902. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  903. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  904. return ret;
  905. }
  906. static ssize_t ep92_sysfs_rda_audio_format(struct device *dev,
  907. struct device_attribute *attr, char *buf)
  908. {
  909. ssize_t ret;
  910. int val;
  911. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  912. if (!ep92 || !ep92->component) {
  913. dev_err(dev, "%s: device error\n", __func__);
  914. return -ENODEV;
  915. }
  916. val = ep92->old_mode;
  917. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  918. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  919. return ret;
  920. }
  921. static ssize_t ep92_sysfs_rda_dsd_rate(struct device *dev,
  922. struct device_attribute *attr, char *buf)
  923. {
  924. ssize_t ret = 0;
  925. int val;
  926. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  927. if (!ep92 || !ep92->codec) {
  928. dev_err(dev, "%s: device error\n", __func__);
  929. return -ENODEV;
  930. }
  931. val = ep92_dsd_freq_table[(ep92->ai.system_status_1 &
  932. EP92_AI_DSD_RATE_MASK) >> EP92_AI_DSD_RATE_SHIFT];
  933. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  934. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  935. return ret;
  936. }
  937. static ssize_t ep92_sysfs_rda_audio_rate(struct device *dev,
  938. struct device_attribute *attr, char *buf)
  939. {
  940. ssize_t ret;
  941. int val;
  942. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  943. if (!ep92 || !ep92->component) {
  944. dev_err(dev, "%s: device error\n", __func__);
  945. return -ENODEV;
  946. }
  947. val = ep92_samp_freq_table[(ep92->ai.audio_status) &
  948. EP92_AI_RATE_MASK];
  949. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  950. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  951. return ret;
  952. }
  953. static ssize_t ep92_sysfs_rda_audio_layout(struct device *dev,
  954. struct device_attribute *attr, char *buf)
  955. {
  956. ssize_t ret;
  957. int val;
  958. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  959. if (!ep92 || !ep92->component) {
  960. dev_err(dev, "%s: device error\n", __func__);
  961. return -ENODEV;
  962. }
  963. val = (ep92->ai.system_status_0 & EP92_AI_LAYOUT_MASK) >>
  964. EP92_AI_LAYOUT_SHIFT;
  965. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  966. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  967. return ret;
  968. }
  969. static ssize_t ep92_sysfs_rda_audio_ch_count(struct device *dev,
  970. struct device_attribute *attr, char *buf)
  971. {
  972. ssize_t ret;
  973. int val;
  974. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  975. if (!ep92 || !ep92->component) {
  976. dev_err(dev, "%s: device error\n", __func__);
  977. return -ENODEV;
  978. }
  979. val = ep92->ai.cc & EP92_AI_CH_COUNT_MASK;
  980. /* mapping is ch_count = reg_val + 1, with exception: 0 = unknown */
  981. if (val > 0)
  982. val += 1;
  983. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  984. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  985. return ret;
  986. }
  987. static ssize_t ep92_sysfs_rda_audio_ch_alloc(struct device *dev,
  988. struct device_attribute *attr, char *buf)
  989. {
  990. ssize_t ret;
  991. int val;
  992. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  993. if (!ep92 || !ep92->component) {
  994. dev_err(dev, "%s: device error\n", __func__);
  995. return -ENODEV;
  996. }
  997. val = ep92->ai.ca & EP92_AI_CH_ALLOC_MASK;
  998. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  999. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1000. return ret;
  1001. }
  1002. static ssize_t ep92_sysfs_rda_audio_preemph(struct device *dev,
  1003. struct device_attribute *attr, char *buf)
  1004. {
  1005. ssize_t ret;
  1006. int val;
  1007. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1008. if (!ep92 || !ep92->component) {
  1009. dev_err(dev, "%s: device error\n", __func__);
  1010. return -ENODEV;
  1011. }
  1012. val = (ep92->ai.cs[0] & EP92_AI_PREEMPH_MASK) >>
  1013. EP92_AI_PREEMPH_SHIFT;
  1014. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1015. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1016. return ret;
  1017. }
  1018. static ssize_t ep92_sysfs_rda_avmute(struct device *dev,
  1019. struct device_attribute *attr, char *buf)
  1020. {
  1021. ssize_t ret;
  1022. int val;
  1023. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1024. if (!ep92 || !ep92->component) {
  1025. dev_err(dev, "%s: device error\n", __func__);
  1026. return -ENODEV;
  1027. }
  1028. val = (ep92->ai.system_status_0 >> EP92_AI_AVMUTE_SHIFT) &
  1029. EP92_2CHOICE_MASK;
  1030. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1031. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1032. return ret;
  1033. }
  1034. static ssize_t ep92_sysfs_rda_link_on0(struct device *dev,
  1035. struct device_attribute *attr, char *buf)
  1036. {
  1037. ssize_t ret;
  1038. int val;
  1039. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1040. if (!ep92 || !ep92->component) {
  1041. dev_err(dev, "%s: device error\n", __func__);
  1042. return -ENODEV;
  1043. }
  1044. val = ep92->filt_link_on0;
  1045. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1046. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1047. return ret;
  1048. }
  1049. static ssize_t ep92_sysfs_rda_link_on1(struct device *dev,
  1050. struct device_attribute *attr, char *buf)
  1051. {
  1052. ssize_t ret;
  1053. int val;
  1054. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1055. if (!ep92 || !ep92->component) {
  1056. dev_err(dev, "%s: device error\n", __func__);
  1057. return -ENODEV;
  1058. }
  1059. val = ep92->filt_link_on1;
  1060. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1061. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1062. return ret;
  1063. }
  1064. static ssize_t ep92_sysfs_rda_link_on2(struct device *dev,
  1065. struct device_attribute *attr, char *buf)
  1066. {
  1067. ssize_t ret;
  1068. int val;
  1069. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1070. if (!ep92 || !ep92->component) {
  1071. dev_err(dev, "%s: device error\n", __func__);
  1072. return -ENODEV;
  1073. }
  1074. val = ep92->filt_link_on2;
  1075. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1076. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1077. return ret;
  1078. }
  1079. static ssize_t ep92_sysfs_rda_out_plug(struct device *dev,
  1080. struct device_attribute *attr, char *buf)
  1081. {
  1082. ssize_t ret;
  1083. int val;
  1084. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1085. if (!ep92 || !ep92->component) {
  1086. dev_err(dev, "%s: device error\n", __func__);
  1087. return -ENODEV;
  1088. }
  1089. val = ep92->filt_tx_plug;
  1090. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1091. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1092. return ret;
  1093. }
  1094. static ssize_t ep92_sysfs_rda_video_latency(struct device *dev,
  1095. struct device_attribute *attr, char *buf)
  1096. {
  1097. ssize_t ret;
  1098. int val;
  1099. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1100. if (!ep92 || !ep92->component) {
  1101. dev_err(dev, "%s: device error\n", __func__);
  1102. return -ENODEV;
  1103. }
  1104. val = ep92->gi.video_latency & EP92_GI_VIDEO_LATENCY_MASK;
  1105. if (val > 0)
  1106. val = (val - 1) * 2;
  1107. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1108. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1109. return ret;
  1110. }
  1111. static ssize_t ep92_sysfs_rda_arc_disable(struct device *dev,
  1112. struct device_attribute *attr, char *buf)
  1113. {
  1114. ssize_t ret;
  1115. int val;
  1116. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1117. if (!ep92 || !ep92->component) {
  1118. dev_err(dev, "%s: device error\n", __func__);
  1119. return -ENODEV;
  1120. }
  1121. val = (ep92->gc.ctl2 >> EP92_GC_ARC_DIS_SHIFT) &
  1122. EP92_2CHOICE_MASK;
  1123. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1124. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1125. return ret;
  1126. }
  1127. static ssize_t ep92_sysfs_wta_arc_disable(struct device *dev,
  1128. struct device_attribute *attr, const char *buf, size_t count)
  1129. {
  1130. int reg, val, rc;
  1131. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1132. if (!ep92 || !ep92->component) {
  1133. dev_err(dev, "%s: device error\n", __func__);
  1134. return -ENODEV;
  1135. }
  1136. rc = kstrtoint(buf, 10, &val);
  1137. if (rc) {
  1138. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1139. goto end;
  1140. }
  1141. if ((val < 0) || (val > 1)) {
  1142. dev_err(dev, "%s: value out of range.\n", __func__);
  1143. rc = -EINVAL;
  1144. goto end;
  1145. }
  1146. reg = snd_soc_component_read32(ep92->component,
  1147. EP92_GENERAL_CONTROL_2);
  1148. reg &= ~EP92_GC_ARC_DIS_MASK;
  1149. reg |= ((val << EP92_GC_ARC_DIS_SHIFT) & EP92_GC_ARC_DIS_MASK);
  1150. snd_soc_component_write(ep92->component, EP92_GENERAL_CONTROL_2, reg);
  1151. ep92->gc.ctl2 &= ~EP92_GC_ARC_DIS_MASK;
  1152. ep92->gc.ctl2 |= (val << EP92_GC_ARC_DIS_SHIFT) & EP92_GC_ARC_DIS_MASK;
  1153. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1154. end:
  1155. return rc;
  1156. }
  1157. static ssize_t ep92_sysfs_rda_power(struct device *dev,
  1158. struct device_attribute *attr, char *buf)
  1159. {
  1160. ssize_t ret;
  1161. int val;
  1162. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1163. if (!ep92 || !ep92->component) {
  1164. dev_err(dev, "%s: device error\n", __func__);
  1165. return -ENODEV;
  1166. }
  1167. val = (ep92->gc.ctl >> EP92_GC_POWER_SHIFT) & EP92_2CHOICE_MASK;
  1168. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1169. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1170. return ret;
  1171. }
  1172. static ssize_t ep92_sysfs_wta_power(struct device *dev,
  1173. struct device_attribute *attr, const char *buf, size_t count)
  1174. {
  1175. int reg, val, rc;
  1176. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1177. if (!ep92 || !ep92->component) {
  1178. dev_err(dev, "%s: device error\n", __func__);
  1179. return -ENODEV;
  1180. }
  1181. rc = kstrtoint(buf, 10, &val);
  1182. if (rc) {
  1183. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1184. goto end;
  1185. }
  1186. if ((val < 0) || (val > 1)) {
  1187. dev_err(dev, "%s: value out of range.\n", __func__);
  1188. rc = -EINVAL;
  1189. goto end;
  1190. }
  1191. reg = snd_soc_component_read32(ep92->component, EP92_GENERAL_CONTROL_0);
  1192. reg &= ~EP92_GC_POWER_MASK;
  1193. reg |= (val << EP92_GC_POWER_SHIFT) & EP92_GC_POWER_MASK;
  1194. snd_soc_component_write(ep92->component, EP92_GENERAL_CONTROL_0, reg);
  1195. ep92->gc.ctl &= ~EP92_GC_POWER_MASK;
  1196. ep92->gc.ctl |= (val << EP92_GC_POWER_SHIFT) & EP92_GC_POWER_MASK;
  1197. if (val == 1) {
  1198. ep92->poll_trig = 1;
  1199. mod_timer(&ep92->timer, jiffies +
  1200. msecs_to_jiffies(EP92_POLL_INTERVAL_ON_MSEC));
  1201. }
  1202. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1203. end:
  1204. return rc;
  1205. }
  1206. static ssize_t ep92_sysfs_rda_audio_path(struct device *dev,
  1207. struct device_attribute *attr, char *buf)
  1208. {
  1209. ssize_t ret;
  1210. int val;
  1211. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1212. if (!ep92 || !ep92->component) {
  1213. dev_err(dev, "%s: device error\n", __func__);
  1214. return -ENODEV;
  1215. }
  1216. val = (ep92->gc.ctl >> EP92_GC_AUDIO_PATH_SHIFT) & EP92_2CHOICE_MASK;
  1217. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1218. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1219. return ret;
  1220. }
  1221. static ssize_t ep92_sysfs_wta_audio_path(struct device *dev,
  1222. struct device_attribute *attr, const char *buf, size_t count)
  1223. {
  1224. int reg, val, rc;
  1225. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1226. if (!ep92 || !ep92->component) {
  1227. dev_err(dev, "%s: device error\n", __func__);
  1228. return -ENODEV;
  1229. }
  1230. rc = kstrtoint(buf, 10, &val);
  1231. if (rc) {
  1232. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1233. goto end;
  1234. }
  1235. if ((val < 0) || (val > 1)) {
  1236. dev_err(dev, "%s: value out of range.\n", __func__);
  1237. rc = -EINVAL;
  1238. goto end;
  1239. }
  1240. reg = snd_soc_component_read32(ep92->component,
  1241. EP92_GENERAL_CONTROL_0);
  1242. reg &= ~EP92_GC_AUDIO_PATH_MASK;
  1243. reg |= (val << EP92_GC_AUDIO_PATH_SHIFT) & EP92_GC_AUDIO_PATH_MASK;
  1244. snd_soc_component_write(ep92->component, EP92_GENERAL_CONTROL_0, reg);
  1245. ep92->gc.ctl &= ~EP92_GC_AUDIO_PATH_MASK;
  1246. ep92->gc.ctl |= (val << EP92_GC_AUDIO_PATH_SHIFT) &
  1247. EP92_GC_AUDIO_PATH_MASK;
  1248. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1249. end:
  1250. return rc;
  1251. }
  1252. static ssize_t ep92_sysfs_rda_src_sel(struct device *dev,
  1253. struct device_attribute *attr, char *buf)
  1254. {
  1255. ssize_t ret;
  1256. int val;
  1257. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1258. if (!ep92 || !ep92->component) {
  1259. dev_err(dev, "%s: device error\n", __func__);
  1260. return -ENODEV;
  1261. }
  1262. val = ep92->gc.rx_sel & EP92_GC_RX_SEL_MASK;
  1263. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1264. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1265. return ret;
  1266. }
  1267. static ssize_t ep92_sysfs_wta_src_sel(struct device *dev,
  1268. struct device_attribute *attr, const char *buf, size_t count)
  1269. {
  1270. int reg, val, rc;
  1271. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1272. if (!ep92 || !ep92->component) {
  1273. dev_err(dev, "%s: device error\n", __func__);
  1274. return -ENODEV;
  1275. }
  1276. rc = kstrtoint(buf, 10, &val);
  1277. if (rc) {
  1278. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1279. goto end;
  1280. }
  1281. if ((val < 0) || (val > 7)) {
  1282. dev_err(dev, "%s: value out of range.\n", __func__);
  1283. rc = -EINVAL;
  1284. goto end;
  1285. }
  1286. reg = snd_soc_component_read32(ep92->component,
  1287. EP92_GENERAL_CONTROL_1);
  1288. reg &= ~EP92_GC_RX_SEL_MASK;
  1289. reg |= (val << EP92_GC_RX_SEL_SHIFT) & EP92_GC_RX_SEL_MASK;
  1290. snd_soc_component_write(ep92->component, EP92_GENERAL_CONTROL_1, reg);
  1291. ep92->gc.rx_sel &= ~EP92_GC_RX_SEL_MASK;
  1292. ep92->gc.rx_sel |= (val << EP92_GC_RX_SEL_SHIFT) & EP92_GC_RX_SEL_MASK;
  1293. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1294. end:
  1295. return rc;
  1296. }
  1297. static ssize_t ep92_sysfs_rda_arc_enable(struct device *dev,
  1298. struct device_attribute *attr, char *buf)
  1299. {
  1300. ssize_t ret;
  1301. int val;
  1302. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1303. if (!ep92 || !ep92->component) {
  1304. dev_err(dev, "%s: device error\n", __func__);
  1305. return -ENODEV;
  1306. }
  1307. val = (ep92->gc.ctl >> EP92_GC_ARC_EN_SHIFT) & EP92_2CHOICE_MASK;
  1308. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1309. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1310. return ret;
  1311. }
  1312. static ssize_t ep92_sysfs_wta_arc_enable(struct device *dev,
  1313. struct device_attribute *attr, const char *buf, size_t count)
  1314. {
  1315. int reg, val, rc;
  1316. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1317. if (!ep92 || !ep92->component) {
  1318. dev_err(dev, "%s: device error\n", __func__);
  1319. return -ENODEV;
  1320. }
  1321. rc = kstrtoint(buf, 10, &val);
  1322. if (rc) {
  1323. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1324. goto end;
  1325. }
  1326. if ((val < 0) || (val > 1)) {
  1327. dev_err(dev, "%s: value out of range.\n", __func__);
  1328. rc = -EINVAL;
  1329. goto end;
  1330. }
  1331. reg = snd_soc_component_read32(ep92->component, EP92_GENERAL_CONTROL_0);
  1332. reg &= ~EP92_GC_ARC_EN_MASK;
  1333. reg |= (val << EP92_GC_ARC_EN_SHIFT) & EP92_GC_ARC_EN_MASK;
  1334. snd_soc_component_write(ep92->component, EP92_GENERAL_CONTROL_0, reg);
  1335. ep92->gc.ctl &= ~EP92_GC_ARC_EN_MASK;
  1336. ep92->gc.ctl |= (val << EP92_GC_ARC_EN_SHIFT) &
  1337. EP92_GC_ARC_EN_MASK;
  1338. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1339. end:
  1340. return rc;
  1341. }
  1342. static ssize_t ep92_sysfs_rda_cec_mute(struct device *dev,
  1343. struct device_attribute *attr, char *buf)
  1344. {
  1345. ssize_t ret;
  1346. int val;
  1347. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1348. if (!ep92 || !ep92->component) {
  1349. dev_err(dev, "%s: device error\n", __func__);
  1350. return -ENODEV;
  1351. }
  1352. val = (ep92->gc.ctl >> EP92_GC_CEC_MUTE_SHIFT) & EP92_2CHOICE_MASK;
  1353. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1354. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1355. return ret;
  1356. }
  1357. static ssize_t ep92_sysfs_wta_cec_mute(struct device *dev,
  1358. struct device_attribute *attr, const char *buf, size_t count)
  1359. {
  1360. int reg, val, rc;
  1361. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1362. if (!ep92 || !ep92->component) {
  1363. dev_err(dev, "%s: device error\n", __func__);
  1364. return -ENODEV;
  1365. }
  1366. rc = kstrtoint(buf, 10, &val);
  1367. if (rc) {
  1368. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1369. goto end;
  1370. }
  1371. if ((val < 0) || (val > 1)) {
  1372. dev_err(dev, "%s: value out of range.\n", __func__);
  1373. rc = -EINVAL;
  1374. goto end;
  1375. }
  1376. reg = snd_soc_component_read32(ep92->component, EP92_GENERAL_CONTROL_0);
  1377. reg &= ~EP92_GC_CEC_MUTE_MASK;
  1378. reg |= (val << EP92_GC_CEC_MUTE_SHIFT) & EP92_GC_CEC_MUTE_MASK;
  1379. snd_soc_component_write(ep92->component, EP92_GENERAL_CONTROL_0, reg);
  1380. ep92->gc.ctl &= ~EP92_GC_CEC_MUTE_MASK;
  1381. ep92->gc.ctl |= (val << EP92_GC_CEC_MUTE_SHIFT) &
  1382. EP92_GC_CEC_MUTE_MASK;
  1383. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1384. end:
  1385. return rc;
  1386. }
  1387. static ssize_t ep92_sysfs_rda_cec_volume(struct device *dev,
  1388. struct device_attribute *attr, char *buf)
  1389. {
  1390. ssize_t ret;
  1391. int val;
  1392. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1393. if (!ep92 || !ep92->component) {
  1394. dev_err(dev, "%s: device error\n", __func__);
  1395. return -ENODEV;
  1396. }
  1397. val = (ep92->gc.cec_volume >> EP92_GC_CEC_VOLUME_SHIFT) &
  1398. EP92_GC_CEC_VOLUME_MASK;
  1399. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1400. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1401. return ret;
  1402. }
  1403. static ssize_t ep92_sysfs_wta_cec_volume(struct device *dev,
  1404. struct device_attribute *attr, const char *buf, size_t count)
  1405. {
  1406. int reg, val, rc;
  1407. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1408. if (!ep92 || !ep92->component) {
  1409. dev_err(dev, "%s: device error\n", __func__);
  1410. return -ENODEV;
  1411. }
  1412. rc = kstrtoint(buf, 10, &val);
  1413. if (rc) {
  1414. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1415. goto end;
  1416. }
  1417. if ((val < 0) || (val > EP92_GC_CEC_VOLUME_MAX)) {
  1418. dev_err(dev, "%s: value out of range.\n", __func__);
  1419. rc = -EINVAL;
  1420. goto end;
  1421. }
  1422. reg = val & EP92_GC_CEC_VOLUME_MASK;
  1423. snd_soc_component_write(ep92->component, EP92_GENERAL_CONTROL_3, reg);
  1424. ep92->gc.cec_volume = val & EP92_GC_CEC_VOLUME_MASK;
  1425. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1426. end:
  1427. return rc;
  1428. }
  1429. static ssize_t ep92_sysfs_rda_runout(struct device *dev,
  1430. struct device_attribute *attr, char *buf)
  1431. {
  1432. ssize_t ret;
  1433. int val;
  1434. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1435. if (!ep92 || !ep92->component) {
  1436. dev_err(dev, "%s: device error\n", __func__);
  1437. return -ENODEV;
  1438. }
  1439. val = ep92->poll_rem;
  1440. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1441. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1442. return ret;
  1443. }
  1444. static ssize_t ep92_sysfs_rda_force_inactive(struct device *dev,
  1445. struct device_attribute *attr, char *buf)
  1446. {
  1447. ssize_t ret;
  1448. int val;
  1449. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1450. if (!ep92 || !ep92->component) {
  1451. dev_err(dev, "%s: device error\n", __func__);
  1452. return -ENODEV;
  1453. }
  1454. val = ep92->force_inactive;
  1455. ret = snprintf(buf, EP92_SYSFS_ENTRY_MAX_LEN, "%d\n", val);
  1456. dev_dbg(dev, "%s: '%d'\n", __func__, val);
  1457. return ret;
  1458. }
  1459. static ssize_t ep92_sysfs_wta_force_inactive(struct device *dev,
  1460. struct device_attribute *attr, const char *buf, size_t count)
  1461. {
  1462. int val, rc;
  1463. struct ep92_pdata *ep92 = dev_get_drvdata(dev);
  1464. if (!ep92 || !ep92->component) {
  1465. dev_err(dev, "%s: device error\n", __func__);
  1466. return -ENODEV;
  1467. }
  1468. rc = kstrtoint(buf, 10, &val);
  1469. if (rc) {
  1470. dev_err(dev, "%s: kstrtoint failed. rc=%d\n", __func__, rc);
  1471. goto end;
  1472. }
  1473. if ((val < 0) || (val > 1)) {
  1474. dev_err(dev, "%s: value out of range.\n", __func__);
  1475. rc = -EINVAL;
  1476. goto end;
  1477. }
  1478. if (val == 0) {
  1479. ep92->force_inactive = 0;
  1480. ep92->poll_trig = 1;
  1481. mod_timer(&ep92->timer, jiffies +
  1482. msecs_to_jiffies(EP92_POLL_INTERVAL_ON_MSEC));
  1483. } else {
  1484. ep92->force_inactive = 1;
  1485. ep92->poll_rem = 0;
  1486. }
  1487. rc = strnlen(buf, EP92_SYSFS_ENTRY_MAX_LEN);
  1488. end:
  1489. return rc;
  1490. }
  1491. static DEVICE_ATTR(chipid, 0444, ep92_sysfs_rda_chipid, NULL);
  1492. static DEVICE_ATTR(version, 0444, ep92_sysfs_rda_version, NULL);
  1493. static DEVICE_ATTR(audio_state, 0444, ep92_sysfs_rda_audio_state, NULL);
  1494. static DEVICE_ATTR(audio_format, 0444, ep92_sysfs_rda_audio_format, NULL);
  1495. static DEVICE_ATTR(audio_rate, 0444, ep92_sysfs_rda_audio_rate, NULL);
  1496. static DEVICE_ATTR(audio_layout, 0444, ep92_sysfs_rda_audio_layout, NULL);
  1497. static DEVICE_ATTR(audio_ch_count, 0444, ep92_sysfs_rda_audio_ch_count, NULL);
  1498. static DEVICE_ATTR(audio_ch_alloc, 0444, ep92_sysfs_rda_audio_ch_alloc, NULL);
  1499. static DEVICE_ATTR(audio_preemph, 0444, ep92_sysfs_rda_audio_preemph, NULL);
  1500. static DEVICE_ATTR(audio_avmute, 0444, ep92_sysfs_rda_avmute, NULL);
  1501. static DEVICE_ATTR(link_on0, 0444, ep92_sysfs_rda_link_on0, NULL);
  1502. static DEVICE_ATTR(link_on1, 0444, ep92_sysfs_rda_link_on1, NULL);
  1503. static DEVICE_ATTR(link_on2, 0444, ep92_sysfs_rda_link_on2, NULL);
  1504. static DEVICE_ATTR(out_plug, 0444, ep92_sysfs_rda_out_plug, NULL);
  1505. static DEVICE_ATTR(video_latency, 0444, ep92_sysfs_rda_video_latency, NULL);
  1506. static DEVICE_ATTR(arc_disable, 0644, ep92_sysfs_rda_arc_disable,
  1507. ep92_sysfs_wta_arc_disable);
  1508. static DEVICE_ATTR(power_on, 0644, ep92_sysfs_rda_power, ep92_sysfs_wta_power);
  1509. static DEVICE_ATTR(audio_path, 0644, ep92_sysfs_rda_audio_path,
  1510. ep92_sysfs_wta_audio_path);
  1511. static DEVICE_ATTR(src_sel, 0644, ep92_sysfs_rda_src_sel,
  1512. ep92_sysfs_wta_src_sel);
  1513. static DEVICE_ATTR(arc_enable, 0644, ep92_sysfs_rda_arc_enable,
  1514. ep92_sysfs_wta_arc_enable);
  1515. static DEVICE_ATTR(cec_mute, 0644, ep92_sysfs_rda_cec_mute,
  1516. ep92_sysfs_wta_cec_mute);
  1517. static DEVICE_ATTR(cec_volume, 0644, ep92_sysfs_rda_cec_volume,
  1518. ep92_sysfs_wta_cec_volume);
  1519. static DEVICE_ATTR(runout, 0444, ep92_sysfs_rda_runout, NULL);
  1520. static DEVICE_ATTR(force_inactive, 0644, ep92_sysfs_rda_force_inactive,
  1521. ep92_sysfs_wta_force_inactive);
  1522. static DEVICE_ATTR(dsd_rate, 0444, ep92_sysfs_rda_dsd_rate, NULL);
  1523. static struct attribute *ep92_fs_attrs[] = {
  1524. &dev_attr_chipid.attr,
  1525. &dev_attr_version.attr,
  1526. &dev_attr_audio_state.attr,
  1527. &dev_attr_audio_format.attr,
  1528. &dev_attr_audio_rate.attr,
  1529. &dev_attr_audio_layout.attr,
  1530. &dev_attr_audio_ch_count.attr,
  1531. &dev_attr_audio_ch_alloc.attr,
  1532. &dev_attr_audio_preemph.attr,
  1533. &dev_attr_audio_avmute.attr,
  1534. &dev_attr_link_on0.attr,
  1535. &dev_attr_link_on1.attr,
  1536. &dev_attr_link_on2.attr,
  1537. &dev_attr_out_plug.attr,
  1538. &dev_attr_video_latency.attr,
  1539. &dev_attr_arc_disable.attr,
  1540. &dev_attr_power_on.attr,
  1541. &dev_attr_audio_path.attr,
  1542. &dev_attr_src_sel.attr,
  1543. &dev_attr_arc_enable.attr,
  1544. &dev_attr_cec_mute.attr,
  1545. &dev_attr_cec_volume.attr,
  1546. &dev_attr_runout.attr,
  1547. &dev_attr_force_inactive.attr,
  1548. &dev_attr_dsd_rate.attr,
  1549. NULL,
  1550. };
  1551. static struct attribute_group ep92_fs_attrs_group = {
  1552. .attrs = ep92_fs_attrs,
  1553. };
  1554. static int ep92_sysfs_create(struct i2c_client *client,
  1555. struct ep92_pdata *ep92)
  1556. {
  1557. int rc;
  1558. rc = sysfs_create_group(&client->dev.kobj, &ep92_fs_attrs_group);
  1559. return rc;
  1560. }
  1561. static void ep92_sysfs_remove(struct i2c_client *client,
  1562. struct ep92_pdata *ep92)
  1563. {
  1564. sysfs_remove_group(&client->dev.kobj, &ep92_fs_attrs_group);
  1565. }
  1566. static int ep92_i2c_probe(struct i2c_client *client,
  1567. const struct i2c_device_id *id)
  1568. {
  1569. struct ep92_pdata *ep92;
  1570. int ret;
  1571. #if IS_ENABLED(CONFIG_DEBUG_FS)
  1572. char debugfs_dir_name[32];
  1573. #endif
  1574. ep92 = devm_kzalloc(&client->dev, sizeof(struct ep92_pdata),
  1575. GFP_KERNEL);
  1576. if (ep92 == NULL)
  1577. return -ENOMEM;
  1578. ep92->regmap = devm_regmap_init_i2c(client, &ep92_regmap_config);
  1579. if (IS_ERR(ep92->regmap)) {
  1580. ret = PTR_ERR(ep92->regmap);
  1581. dev_err(&client->dev,
  1582. "%s: Failed to allocate regmap for I2C device: %d\n",
  1583. __func__, ret);
  1584. return ret;
  1585. }
  1586. i2c_set_clientdata(client, ep92);
  1587. /* register interrupt handler */
  1588. INIT_WORK(&ep92->read_status_worker, ep92_read_status);
  1589. ep92->irq = client->irq;
  1590. if (ep92->irq) {
  1591. ret = devm_request_threaded_irq(&client->dev, ep92->irq,
  1592. NULL, ep92_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1593. "ep92_irq", ep92);
  1594. if (ret) {
  1595. dev_err(&client->dev,
  1596. "%s: Failed to request IRQ %d: %d\n",
  1597. __func__, ep92->irq, ret);
  1598. ep92->irq = 0;
  1599. }
  1600. }
  1601. /* prepare timer */
  1602. timer_setup(&ep92->timer, ep92_poll_status, 0);
  1603. ep92->poll_rem = EP92_POLL_RUNOUT_MSEC;
  1604. #if IS_ENABLED(CONFIG_DEBUG_FS)
  1605. /* debugfs interface */
  1606. snprintf(debugfs_dir_name, sizeof(debugfs_dir_name), "%s-%s",
  1607. client->name, dev_name(&client->dev));
  1608. ep92->debugfs_dir = debugfs_create_dir(debugfs_dir_name, NULL);
  1609. if (!ep92->debugfs_dir) {
  1610. dev_dbg(&client->dev,
  1611. "%s: Failed to create /sys/kernel/debug/%s for debugfs\n",
  1612. __func__, debugfs_dir_name);
  1613. return -ENOMEM;
  1614. }
  1615. ep92->debugfs_file_wo = debugfs_create_file(
  1616. "write_reg_val", S_IFREG | 0444, ep92->debugfs_dir,
  1617. (void *) ep92,
  1618. &debugfs_codec_ops);
  1619. if (!ep92->debugfs_file_wo) {
  1620. dev_dbg(&client->dev,
  1621. "%s: Failed to create /sys/kernel/debug/%s/write_reg_val\n",
  1622. __func__, debugfs_dir_name);
  1623. return -ENOMEM;
  1624. }
  1625. ep92->debugfs_file_ro = debugfs_create_file(
  1626. "show_reg_dump", S_IFREG | 0444, ep92->debugfs_dir,
  1627. (void *) ep92,
  1628. &debugfs_codec_ops);
  1629. if (!ep92->debugfs_file_ro) {
  1630. dev_dbg(&client->dev,
  1631. "%s: Failed to create /sys/kernel/debug/%s/show_reg_dump\n",
  1632. __func__, debugfs_dir_name);
  1633. return -ENOMEM;
  1634. }
  1635. #endif /* CONFIG_DEBUG_FS */
  1636. /* register component */
  1637. ret = snd_soc_register_component(&client->dev, &soc_codec_drv_ep92,
  1638. ep92_dai, ARRAY_SIZE(ep92_dai));
  1639. if (ret) {
  1640. dev_err(&client->dev, "%s %d: Failed to register CODEC: %d\n",
  1641. __func__, __LINE__, ret);
  1642. goto err_reg;
  1643. }
  1644. ret = ep92_sysfs_create(client, ep92);
  1645. if (ret) {
  1646. dev_err(&client->dev, "%s: sysfs creation failed ret=%d\n",
  1647. __func__, ret);
  1648. goto err_sysfs;
  1649. }
  1650. return 0;
  1651. err_sysfs:
  1652. snd_soc_unregister_component(&client->dev);
  1653. err_reg:
  1654. del_timer(&ep92->timer);
  1655. return ret;
  1656. }
  1657. static int ep92_i2c_remove(struct i2c_client *client)
  1658. {
  1659. struct ep92_pdata *ep92;
  1660. ep92 = i2c_get_clientdata(client);
  1661. if (ep92) {
  1662. del_timer(&ep92->timer);
  1663. #if IS_ENABLED(CONFIG_DEBUG_FS)
  1664. debugfs_remove_recursive(ep92->debugfs_dir);
  1665. #endif
  1666. }
  1667. snd_soc_unregister_component(&client->dev);
  1668. ep92_sysfs_remove(client, ep92);
  1669. return 0;
  1670. }
  1671. static const struct i2c_device_id ep92_i2c_id[] = {
  1672. { "ep92-dev", 0},
  1673. { }
  1674. };
  1675. MODULE_DEVICE_TABLE(i2c, ep92_i2c_id);
  1676. static struct i2c_driver ep92_i2c_driver = {
  1677. .probe = ep92_i2c_probe,
  1678. .remove = ep92_i2c_remove,
  1679. .id_table = ep92_i2c_id,
  1680. .driver = {
  1681. .name = "ep92",
  1682. .owner = THIS_MODULE,
  1683. .of_match_table = ep92_of_match
  1684. },
  1685. };
  1686. static int __init ep92_codec_init(void)
  1687. {
  1688. int ret = 0;
  1689. ret = i2c_add_driver(&ep92_i2c_driver);
  1690. if (ret)
  1691. pr_err("Failed to register EP92 I2C driver: %d\n", ret);
  1692. return ret;
  1693. }
  1694. module_init(ep92_codec_init);
  1695. static void __exit ep92_codec_exit(void)
  1696. {
  1697. i2c_del_driver(&ep92_i2c_driver);
  1698. }
  1699. module_exit(ep92_codec_exit);
  1700. MODULE_DESCRIPTION("EP92 HDMI repeater/switch driver");
  1701. MODULE_LICENSE("GPL v2");