dp_tx.c 113 KB

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  1. /*
  2. * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "enet.h"
  34. #include "dp_internal.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. /* TODO Add support in TSO */
  42. #define DP_DESC_NUM_FRAG(x) 0
  43. /* disable TQM_BYPASS */
  44. #define TQM_BYPASS_WAR 0
  45. /* invalid peer id for reinject*/
  46. #define DP_INVALID_PEER 0XFFFE
  47. /*mapping between hal encrypt type and cdp_sec_type*/
  48. #define MAX_CDP_SEC_TYPE 12
  49. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  50. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  51. HAL_TX_ENCRYPT_TYPE_WEP_128,
  52. HAL_TX_ENCRYPT_TYPE_WEP_104,
  53. HAL_TX_ENCRYPT_TYPE_WEP_40,
  54. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  55. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  56. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  57. HAL_TX_ENCRYPT_TYPE_WAPI,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  59. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  60. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  62. #ifdef QCA_TX_LIMIT_CHECK
  63. /**
  64. * dp_tx_limit_check - Check if allocated tx descriptors reached
  65. * soc max limit and pdev max limit
  66. * @vdev: DP vdev handle
  67. *
  68. * Return: true if allocated tx descriptors reached max configured value, else
  69. * false
  70. */
  71. static inline bool
  72. dp_tx_limit_check(struct dp_vdev *vdev)
  73. {
  74. struct dp_pdev *pdev = vdev->pdev;
  75. struct dp_soc *soc = pdev->soc;
  76. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  77. soc->num_tx_allowed) {
  78. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  79. "%s: queued packets are more than max tx, drop the frame",
  80. __func__);
  81. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  82. return true;
  83. }
  84. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  85. pdev->num_tx_allowed) {
  86. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  87. "%s: queued packets are more than max tx, drop the frame",
  88. __func__);
  89. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  90. return true;
  91. }
  92. return false;
  93. }
  94. /**
  95. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  96. * @vdev: DP pdev handle
  97. *
  98. * Return: void
  99. */
  100. static inline void
  101. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  102. {
  103. struct dp_soc *soc = pdev->soc;
  104. qdf_atomic_inc(&pdev->num_tx_outstanding);
  105. qdf_atomic_inc(&soc->num_tx_outstanding);
  106. }
  107. /**
  108. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  109. * @vdev: DP pdev handle
  110. *
  111. * Return: void
  112. */
  113. static inline void
  114. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  115. {
  116. struct dp_soc *soc = pdev->soc;
  117. qdf_atomic_dec(&pdev->num_tx_outstanding);
  118. qdf_atomic_dec(&soc->num_tx_outstanding);
  119. }
  120. #else //QCA_TX_LIMIT_CHECK
  121. static inline bool
  122. dp_tx_limit_check(struct dp_vdev *vdev)
  123. {
  124. return false;
  125. }
  126. static inline void
  127. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  128. {
  129. }
  130. static inline void
  131. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  132. {
  133. }
  134. #endif //QCA_TX_LIMIT_CHECK
  135. #if defined(FEATURE_TSO)
  136. /**
  137. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  138. *
  139. * @soc - core txrx main context
  140. * @seg_desc - tso segment descriptor
  141. * @num_seg_desc - tso number segment descriptor
  142. */
  143. static void dp_tx_tso_unmap_segment(
  144. struct dp_soc *soc,
  145. struct qdf_tso_seg_elem_t *seg_desc,
  146. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  147. {
  148. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  149. if (qdf_unlikely(!seg_desc)) {
  150. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  151. __func__, __LINE__);
  152. qdf_assert(0);
  153. } else if (qdf_unlikely(!num_seg_desc)) {
  154. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  155. __func__, __LINE__);
  156. qdf_assert(0);
  157. } else {
  158. bool is_last_seg;
  159. /* no tso segment left to do dma unmap */
  160. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  161. return;
  162. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  163. true : false;
  164. qdf_nbuf_unmap_tso_segment(soc->osdev,
  165. seg_desc, is_last_seg);
  166. num_seg_desc->num_seg.tso_cmn_num_seg--;
  167. }
  168. }
  169. /**
  170. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  171. * back to the freelist
  172. *
  173. * @soc - soc device handle
  174. * @tx_desc - Tx software descriptor
  175. */
  176. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  177. struct dp_tx_desc_s *tx_desc)
  178. {
  179. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  180. if (qdf_unlikely(!tx_desc->tso_desc)) {
  181. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  182. "%s %d TSO desc is NULL!",
  183. __func__, __LINE__);
  184. qdf_assert(0);
  185. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  186. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  187. "%s %d TSO num desc is NULL!",
  188. __func__, __LINE__);
  189. qdf_assert(0);
  190. } else {
  191. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  192. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  193. /* Add the tso num segment into the free list */
  194. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  195. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  196. tx_desc->tso_num_desc);
  197. tx_desc->tso_num_desc = NULL;
  198. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  199. }
  200. /* Add the tso segment into the free list*/
  201. dp_tx_tso_desc_free(soc,
  202. tx_desc->pool_id, tx_desc->tso_desc);
  203. tx_desc->tso_desc = NULL;
  204. }
  205. }
  206. #else
  207. static void dp_tx_tso_unmap_segment(
  208. struct dp_soc *soc,
  209. struct qdf_tso_seg_elem_t *seg_desc,
  210. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  211. {
  212. }
  213. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  214. struct dp_tx_desc_s *tx_desc)
  215. {
  216. }
  217. #endif
  218. /**
  219. * dp_tx_desc_release() - Release Tx Descriptor
  220. * @tx_desc : Tx Descriptor
  221. * @desc_pool_id: Descriptor Pool ID
  222. *
  223. * Deallocate all resources attached to Tx descriptor and free the Tx
  224. * descriptor.
  225. *
  226. * Return:
  227. */
  228. static void
  229. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  230. {
  231. struct dp_pdev *pdev = tx_desc->pdev;
  232. struct dp_soc *soc;
  233. uint8_t comp_status = 0;
  234. qdf_assert(pdev);
  235. soc = pdev->soc;
  236. if (tx_desc->frm_type == dp_tx_frm_tso)
  237. dp_tx_tso_desc_release(soc, tx_desc);
  238. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  239. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  240. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  241. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  242. dp_tx_outstanding_dec(pdev);
  243. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  244. qdf_atomic_dec(&pdev->num_tx_exception);
  245. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  246. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  247. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  248. soc->hal_soc);
  249. else
  250. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  251. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  252. "Tx Completion Release desc %d status %d outstanding %d",
  253. tx_desc->id, comp_status,
  254. qdf_atomic_read(&pdev->num_tx_outstanding));
  255. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  256. return;
  257. }
  258. /**
  259. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  260. * @vdev: DP vdev Handle
  261. * @nbuf: skb
  262. * @msdu_info: msdu_info required to create HTT metadata
  263. *
  264. * Prepares and fills HTT metadata in the frame pre-header for special frames
  265. * that should be transmitted using varying transmit parameters.
  266. * There are 2 VDEV modes that currently needs this special metadata -
  267. * 1) Mesh Mode
  268. * 2) DSRC Mode
  269. *
  270. * Return: HTT metadata size
  271. *
  272. */
  273. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  274. struct dp_tx_msdu_info_s *msdu_info)
  275. {
  276. uint32_t *meta_data = msdu_info->meta_data;
  277. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  278. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  279. uint8_t htt_desc_size;
  280. /* Size rounded of multiple of 8 bytes */
  281. uint8_t htt_desc_size_aligned;
  282. uint8_t *hdr = NULL;
  283. /*
  284. * Metadata - HTT MSDU Extension header
  285. */
  286. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  287. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  288. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  289. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  290. meta_data[0])) {
  291. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  292. htt_desc_size_aligned)) {
  293. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  294. htt_desc_size_aligned);
  295. if (!nbuf) {
  296. /*
  297. * qdf_nbuf_realloc_headroom won't do skb_clone
  298. * as skb_realloc_headroom does. so, no free is
  299. * needed here.
  300. */
  301. DP_STATS_INC(vdev,
  302. tx_i.dropped.headroom_insufficient,
  303. 1);
  304. qdf_print(" %s[%d] skb_realloc_headroom failed",
  305. __func__, __LINE__);
  306. return 0;
  307. }
  308. }
  309. /* Fill and add HTT metaheader */
  310. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  311. if (!hdr) {
  312. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  313. "Error in filling HTT metadata");
  314. return 0;
  315. }
  316. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  317. } else if (vdev->opmode == wlan_op_mode_ocb) {
  318. /* Todo - Add support for DSRC */
  319. }
  320. return htt_desc_size_aligned;
  321. }
  322. /**
  323. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  324. * @tso_seg: TSO segment to process
  325. * @ext_desc: Pointer to MSDU extension descriptor
  326. *
  327. * Return: void
  328. */
  329. #if defined(FEATURE_TSO)
  330. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  331. void *ext_desc)
  332. {
  333. uint8_t num_frag;
  334. uint32_t tso_flags;
  335. /*
  336. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  337. * tcp_flag_mask
  338. *
  339. * Checksum enable flags are set in TCL descriptor and not in Extension
  340. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  341. */
  342. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  343. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  344. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  345. tso_seg->tso_flags.ip_len);
  346. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  347. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  348. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  349. uint32_t lo = 0;
  350. uint32_t hi = 0;
  351. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  352. (tso_seg->tso_frags[num_frag].length));
  353. qdf_dmaaddr_to_32s(
  354. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  355. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  356. tso_seg->tso_frags[num_frag].length);
  357. }
  358. return;
  359. }
  360. #else
  361. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  362. void *ext_desc)
  363. {
  364. return;
  365. }
  366. #endif
  367. #if defined(FEATURE_TSO)
  368. /**
  369. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  370. * allocated and free them
  371. *
  372. * @soc: soc handle
  373. * @free_seg: list of tso segments
  374. * @msdu_info: msdu descriptor
  375. *
  376. * Return - void
  377. */
  378. static void dp_tx_free_tso_seg_list(
  379. struct dp_soc *soc,
  380. struct qdf_tso_seg_elem_t *free_seg,
  381. struct dp_tx_msdu_info_s *msdu_info)
  382. {
  383. struct qdf_tso_seg_elem_t *next_seg;
  384. while (free_seg) {
  385. next_seg = free_seg->next;
  386. dp_tx_tso_desc_free(soc,
  387. msdu_info->tx_queue.desc_pool_id,
  388. free_seg);
  389. free_seg = next_seg;
  390. }
  391. }
  392. /**
  393. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  394. * allocated and free them
  395. *
  396. * @soc: soc handle
  397. * @free_num_seg: list of tso number segments
  398. * @msdu_info: msdu descriptor
  399. * Return - void
  400. */
  401. static void dp_tx_free_tso_num_seg_list(
  402. struct dp_soc *soc,
  403. struct qdf_tso_num_seg_elem_t *free_num_seg,
  404. struct dp_tx_msdu_info_s *msdu_info)
  405. {
  406. struct qdf_tso_num_seg_elem_t *next_num_seg;
  407. while (free_num_seg) {
  408. next_num_seg = free_num_seg->next;
  409. dp_tso_num_seg_free(soc,
  410. msdu_info->tx_queue.desc_pool_id,
  411. free_num_seg);
  412. free_num_seg = next_num_seg;
  413. }
  414. }
  415. /**
  416. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  417. * do dma unmap for each segment
  418. *
  419. * @soc: soc handle
  420. * @free_seg: list of tso segments
  421. * @num_seg_desc: tso number segment descriptor
  422. *
  423. * Return - void
  424. */
  425. static void dp_tx_unmap_tso_seg_list(
  426. struct dp_soc *soc,
  427. struct qdf_tso_seg_elem_t *free_seg,
  428. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  429. {
  430. struct qdf_tso_seg_elem_t *next_seg;
  431. if (qdf_unlikely(!num_seg_desc)) {
  432. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  433. return;
  434. }
  435. while (free_seg) {
  436. next_seg = free_seg->next;
  437. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  438. free_seg = next_seg;
  439. }
  440. }
  441. #ifdef FEATURE_TSO_STATS
  442. /**
  443. * dp_tso_get_stats_idx: Retrieve the tso packet id
  444. * @pdev - pdev handle
  445. *
  446. * Return: id
  447. */
  448. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  449. {
  450. uint32_t stats_idx;
  451. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  452. % CDP_MAX_TSO_PACKETS);
  453. return stats_idx;
  454. }
  455. #else
  456. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  457. {
  458. return 0;
  459. }
  460. #endif /* FEATURE_TSO_STATS */
  461. /**
  462. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  463. * free the tso segments descriptor and
  464. * tso num segments descriptor
  465. *
  466. * @soc: soc handle
  467. * @msdu_info: msdu descriptor
  468. * @tso_seg_unmap: flag to show if dma unmap is necessary
  469. *
  470. * Return - void
  471. */
  472. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  473. struct dp_tx_msdu_info_s *msdu_info,
  474. bool tso_seg_unmap)
  475. {
  476. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  477. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  478. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  479. tso_info->tso_num_seg_list;
  480. /* do dma unmap for each segment */
  481. if (tso_seg_unmap)
  482. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  483. /* free all tso number segment descriptor though looks only have 1 */
  484. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  485. /* free all tso segment descriptor */
  486. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  487. }
  488. /**
  489. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  490. * @vdev: virtual device handle
  491. * @msdu: network buffer
  492. * @msdu_info: meta data associated with the msdu
  493. *
  494. * Return: QDF_STATUS_SUCCESS success
  495. */
  496. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  497. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  498. {
  499. struct qdf_tso_seg_elem_t *tso_seg;
  500. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  501. struct dp_soc *soc = vdev->pdev->soc;
  502. struct dp_pdev *pdev = vdev->pdev;
  503. struct qdf_tso_info_t *tso_info;
  504. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  505. tso_info = &msdu_info->u.tso_info;
  506. tso_info->curr_seg = NULL;
  507. tso_info->tso_seg_list = NULL;
  508. tso_info->num_segs = num_seg;
  509. msdu_info->frm_type = dp_tx_frm_tso;
  510. tso_info->tso_num_seg_list = NULL;
  511. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  512. while (num_seg) {
  513. tso_seg = dp_tx_tso_desc_alloc(
  514. soc, msdu_info->tx_queue.desc_pool_id);
  515. if (tso_seg) {
  516. tso_seg->next = tso_info->tso_seg_list;
  517. tso_info->tso_seg_list = tso_seg;
  518. num_seg--;
  519. } else {
  520. DP_TRACE(ERROR, "%s: Failed to alloc tso seg desc",
  521. __func__);
  522. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  523. return QDF_STATUS_E_NOMEM;
  524. }
  525. }
  526. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  527. tso_num_seg = dp_tso_num_seg_alloc(soc,
  528. msdu_info->tx_queue.desc_pool_id);
  529. if (tso_num_seg) {
  530. tso_num_seg->next = tso_info->tso_num_seg_list;
  531. tso_info->tso_num_seg_list = tso_num_seg;
  532. } else {
  533. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  534. __func__);
  535. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  536. return QDF_STATUS_E_NOMEM;
  537. }
  538. msdu_info->num_seg =
  539. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  540. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  541. msdu_info->num_seg);
  542. if (!(msdu_info->num_seg)) {
  543. /*
  544. * Free allocated TSO seg desc and number seg desc,
  545. * do unmap for segments if dma map has done.
  546. */
  547. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  548. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  549. return QDF_STATUS_E_INVAL;
  550. }
  551. tso_info->curr_seg = tso_info->tso_seg_list;
  552. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  553. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  554. msdu, msdu_info->num_seg);
  555. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  556. tso_info->msdu_stats_idx);
  557. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  558. return QDF_STATUS_SUCCESS;
  559. }
  560. #else
  561. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  562. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  563. {
  564. return QDF_STATUS_E_NOMEM;
  565. }
  566. #endif
  567. /**
  568. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  569. * @vdev: DP Vdev handle
  570. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  571. * @desc_pool_id: Descriptor Pool ID
  572. *
  573. * Return:
  574. */
  575. static
  576. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  577. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  578. {
  579. uint8_t i;
  580. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  581. struct dp_tx_seg_info_s *seg_info;
  582. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  583. struct dp_soc *soc = vdev->pdev->soc;
  584. /* Allocate an extension descriptor */
  585. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  586. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  587. if (!msdu_ext_desc) {
  588. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  589. return NULL;
  590. }
  591. if (msdu_info->exception_fw &&
  592. qdf_unlikely(vdev->mesh_vdev)) {
  593. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  594. &msdu_info->meta_data[0],
  595. sizeof(struct htt_tx_msdu_desc_ext2_t));
  596. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  597. }
  598. switch (msdu_info->frm_type) {
  599. case dp_tx_frm_sg:
  600. case dp_tx_frm_me:
  601. case dp_tx_frm_raw:
  602. seg_info = msdu_info->u.sg_info.curr_seg;
  603. /* Update the buffer pointers in MSDU Extension Descriptor */
  604. for (i = 0; i < seg_info->frag_cnt; i++) {
  605. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  606. seg_info->frags[i].paddr_lo,
  607. seg_info->frags[i].paddr_hi,
  608. seg_info->frags[i].len);
  609. }
  610. break;
  611. case dp_tx_frm_tso:
  612. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  613. &cached_ext_desc[0]);
  614. break;
  615. default:
  616. break;
  617. }
  618. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  619. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  620. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  621. msdu_ext_desc->vaddr);
  622. return msdu_ext_desc;
  623. }
  624. /**
  625. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  626. *
  627. * @skb: skb to be traced
  628. * @msdu_id: msdu_id of the packet
  629. * @vdev_id: vdev_id of the packet
  630. *
  631. * Return: None
  632. */
  633. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  634. uint8_t vdev_id)
  635. {
  636. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  637. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  638. DPTRACE(qdf_dp_trace_ptr(skb,
  639. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  640. QDF_TRACE_DEFAULT_PDEV_ID,
  641. qdf_nbuf_data_addr(skb),
  642. sizeof(qdf_nbuf_data(skb)),
  643. msdu_id, vdev_id));
  644. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  645. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  646. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  647. msdu_id, QDF_TX));
  648. }
  649. /**
  650. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  651. * @vdev: DP vdev handle
  652. * @nbuf: skb
  653. * @desc_pool_id: Descriptor pool ID
  654. * @meta_data: Metadata to the fw
  655. * @tx_exc_metadata: Handle that holds exception path metadata
  656. * Allocate and prepare Tx descriptor with msdu information.
  657. *
  658. * Return: Pointer to Tx Descriptor on success,
  659. * NULL on failure
  660. */
  661. static
  662. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  663. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  664. struct dp_tx_msdu_info_s *msdu_info,
  665. struct cdp_tx_exception_metadata *tx_exc_metadata)
  666. {
  667. uint8_t align_pad;
  668. uint8_t is_exception = 0;
  669. uint8_t htt_hdr_size;
  670. qdf_ether_header_t *eh;
  671. struct dp_tx_desc_s *tx_desc;
  672. struct dp_pdev *pdev = vdev->pdev;
  673. struct dp_soc *soc = pdev->soc;
  674. if (dp_tx_limit_check(vdev))
  675. return NULL;
  676. /* Allocate software Tx descriptor */
  677. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  678. if (qdf_unlikely(!tx_desc)) {
  679. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  680. return NULL;
  681. }
  682. dp_tx_outstanding_inc(pdev);
  683. /* Initialize the SW tx descriptor */
  684. tx_desc->nbuf = nbuf;
  685. tx_desc->frm_type = dp_tx_frm_std;
  686. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  687. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  688. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  689. tx_desc->vdev = vdev;
  690. tx_desc->pdev = pdev;
  691. tx_desc->msdu_ext_desc = NULL;
  692. tx_desc->pkt_offset = 0;
  693. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  694. if (qdf_unlikely(vdev->multipass_en)) {
  695. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  696. goto failure;
  697. }
  698. /*
  699. * For special modes (vdev_type == ocb or mesh), data frames should be
  700. * transmitted using varying transmit parameters (tx spec) which include
  701. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  702. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  703. * These frames are sent as exception packets to firmware.
  704. *
  705. * HW requirement is that metadata should always point to a
  706. * 8-byte aligned address. So we add alignment pad to start of buffer.
  707. * HTT Metadata should be ensured to be multiple of 8-bytes,
  708. * to get 8-byte aligned start address along with align_pad added
  709. *
  710. * |-----------------------------|
  711. * | |
  712. * |-----------------------------| <-----Buffer Pointer Address given
  713. * | | ^ in HW descriptor (aligned)
  714. * | HTT Metadata | |
  715. * | | |
  716. * | | | Packet Offset given in descriptor
  717. * | | |
  718. * |-----------------------------| |
  719. * | Alignment Pad | v
  720. * |-----------------------------| <----- Actual buffer start address
  721. * | SKB Data | (Unaligned)
  722. * | |
  723. * | |
  724. * | |
  725. * | |
  726. * | |
  727. * |-----------------------------|
  728. */
  729. if (qdf_unlikely((msdu_info->exception_fw)) ||
  730. (vdev->opmode == wlan_op_mode_ocb) ||
  731. (tx_exc_metadata &&
  732. tx_exc_metadata->is_tx_sniffer)) {
  733. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  734. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  735. DP_STATS_INC(vdev,
  736. tx_i.dropped.headroom_insufficient, 1);
  737. goto failure;
  738. }
  739. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  740. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  741. "qdf_nbuf_push_head failed");
  742. goto failure;
  743. }
  744. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  745. msdu_info);
  746. if (htt_hdr_size == 0)
  747. goto failure;
  748. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  749. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  750. is_exception = 1;
  751. }
  752. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  753. qdf_nbuf_map(soc->osdev, nbuf,
  754. QDF_DMA_TO_DEVICE))) {
  755. /* Handle failure */
  756. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  757. "qdf_nbuf_map failed");
  758. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  759. goto failure;
  760. }
  761. if (qdf_unlikely(vdev->nawds_enabled)) {
  762. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  763. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  764. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  765. is_exception = 1;
  766. }
  767. }
  768. #if !TQM_BYPASS_WAR
  769. if (is_exception || tx_exc_metadata)
  770. #endif
  771. {
  772. /* Temporary WAR due to TQM VP issues */
  773. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  774. qdf_atomic_inc(&pdev->num_tx_exception);
  775. }
  776. return tx_desc;
  777. failure:
  778. dp_tx_desc_release(tx_desc, desc_pool_id);
  779. return NULL;
  780. }
  781. /**
  782. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  783. * @vdev: DP vdev handle
  784. * @nbuf: skb
  785. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  786. * @desc_pool_id : Descriptor Pool ID
  787. *
  788. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  789. * information. For frames wth fragments, allocate and prepare
  790. * an MSDU extension descriptor
  791. *
  792. * Return: Pointer to Tx Descriptor on success,
  793. * NULL on failure
  794. */
  795. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  796. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  797. uint8_t desc_pool_id)
  798. {
  799. struct dp_tx_desc_s *tx_desc;
  800. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  801. struct dp_pdev *pdev = vdev->pdev;
  802. struct dp_soc *soc = pdev->soc;
  803. if (dp_tx_limit_check(vdev))
  804. return NULL;
  805. /* Allocate software Tx descriptor */
  806. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  807. if (!tx_desc) {
  808. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  809. return NULL;
  810. }
  811. dp_tx_outstanding_inc(pdev);
  812. /* Initialize the SW tx descriptor */
  813. tx_desc->nbuf = nbuf;
  814. tx_desc->frm_type = msdu_info->frm_type;
  815. tx_desc->tx_encap_type = vdev->tx_encap_type;
  816. tx_desc->vdev = vdev;
  817. tx_desc->pdev = pdev;
  818. tx_desc->pkt_offset = 0;
  819. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  820. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  821. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  822. /* Handle scattered frames - TSO/SG/ME */
  823. /* Allocate and prepare an extension descriptor for scattered frames */
  824. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  825. if (!msdu_ext_desc) {
  826. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  827. "%s Tx Extension Descriptor Alloc Fail",
  828. __func__);
  829. goto failure;
  830. }
  831. #if TQM_BYPASS_WAR
  832. /* Temporary WAR due to TQM VP issues */
  833. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  834. qdf_atomic_inc(&pdev->num_tx_exception);
  835. #endif
  836. if (qdf_unlikely(msdu_info->exception_fw))
  837. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  838. tx_desc->msdu_ext_desc = msdu_ext_desc;
  839. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  840. return tx_desc;
  841. failure:
  842. dp_tx_desc_release(tx_desc, desc_pool_id);
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_prepare_raw() - Prepare RAW packet TX
  847. * @vdev: DP vdev handle
  848. * @nbuf: buffer pointer
  849. * @seg_info: Pointer to Segment info Descriptor to be prepared
  850. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  851. * descriptor
  852. *
  853. * Return:
  854. */
  855. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  856. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  857. {
  858. qdf_nbuf_t curr_nbuf = NULL;
  859. uint16_t total_len = 0;
  860. qdf_dma_addr_t paddr;
  861. int32_t i;
  862. int32_t mapped_buf_num = 0;
  863. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  864. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  865. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  866. /* Continue only if frames are of DATA type */
  867. if (!DP_FRAME_IS_DATA(qos_wh)) {
  868. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  869. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  870. "Pkt. recd is of not data type");
  871. goto error;
  872. }
  873. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  874. if (vdev->raw_mode_war &&
  875. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  876. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  877. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  878. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  879. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  880. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  881. QDF_DMA_TO_DEVICE)) {
  882. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  883. "%s dma map error ", __func__);
  884. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  885. mapped_buf_num = i;
  886. goto error;
  887. }
  888. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  889. seg_info->frags[i].paddr_lo = paddr;
  890. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  891. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  892. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  893. total_len += qdf_nbuf_len(curr_nbuf);
  894. }
  895. seg_info->frag_cnt = i;
  896. seg_info->total_len = total_len;
  897. seg_info->next = NULL;
  898. sg_info->curr_seg = seg_info;
  899. msdu_info->frm_type = dp_tx_frm_raw;
  900. msdu_info->num_seg = 1;
  901. return nbuf;
  902. error:
  903. i = 0;
  904. while (nbuf) {
  905. curr_nbuf = nbuf;
  906. if (i < mapped_buf_num) {
  907. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  908. i++;
  909. }
  910. nbuf = qdf_nbuf_next(nbuf);
  911. qdf_nbuf_free(curr_nbuf);
  912. }
  913. return NULL;
  914. }
  915. /**
  916. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  917. * @soc: DP soc handle
  918. * @nbuf: Buffer pointer
  919. *
  920. * unmap the chain of nbufs that belong to this RAW frame.
  921. *
  922. * Return: None
  923. */
  924. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  925. qdf_nbuf_t nbuf)
  926. {
  927. qdf_nbuf_t cur_nbuf = nbuf;
  928. do {
  929. qdf_nbuf_unmap(soc->osdev, cur_nbuf, QDF_DMA_TO_DEVICE);
  930. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  931. } while (cur_nbuf);
  932. }
  933. /**
  934. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  935. * @soc: DP Soc Handle
  936. * @vdev: DP vdev handle
  937. * @tx_desc: Tx Descriptor Handle
  938. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  939. * @fw_metadata: Metadata to send to Target Firmware along with frame
  940. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  941. * @tx_exc_metadata: Handle that holds exception path meta data
  942. *
  943. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  944. * from software Tx descriptor
  945. *
  946. * Return:
  947. */
  948. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  949. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  950. uint16_t fw_metadata, uint8_t ring_id,
  951. struct cdp_tx_exception_metadata
  952. *tx_exc_metadata)
  953. {
  954. uint8_t type;
  955. uint16_t length;
  956. void *hal_tx_desc, *hal_tx_desc_cached;
  957. qdf_dma_addr_t dma_addr;
  958. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  959. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  960. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  961. tx_exc_metadata->sec_type : vdev->sec_type);
  962. /* Return Buffer Manager ID */
  963. uint8_t bm_id = ring_id;
  964. hal_ring_handle_t hal_ring_hdl = soc->tcl_data_ring[ring_id].hal_srng;
  965. hal_tx_desc_cached = (void *) cached_desc;
  966. qdf_mem_zero(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  967. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  968. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  969. type = HAL_TX_BUF_TYPE_EXT_DESC;
  970. dma_addr = tx_desc->msdu_ext_desc->paddr;
  971. } else {
  972. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  973. type = HAL_TX_BUF_TYPE_BUFFER;
  974. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  975. }
  976. qdf_assert_always(dma_addr);
  977. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  978. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  979. dma_addr, bm_id, tx_desc->id,
  980. type, soc->hal_soc);
  981. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  982. return QDF_STATUS_E_RESOURCES;
  983. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  984. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  985. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  986. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  987. vdev->pdev->lmac_id);
  988. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  989. vdev->search_type);
  990. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  991. vdev->bss_ast_idx);
  992. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  993. vdev->dscp_tid_map_id);
  994. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  995. sec_type_map[sec_type]);
  996. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  997. (vdev->bss_ast_hash & 0xF));
  998. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  999. length, type, (uint64_t)dma_addr,
  1000. tx_desc->pkt_offset, tx_desc->id);
  1001. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1002. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1003. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1004. vdev->hal_desc_addr_search_flags);
  1005. /* verify checksum offload configuration*/
  1006. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  1007. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1008. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1009. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1010. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1011. }
  1012. if (tid != HTT_TX_EXT_TID_INVALID)
  1013. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1014. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1015. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1016. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  1017. /* Sync cached descriptor with HW */
  1018. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1019. if (!hal_tx_desc) {
  1020. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1021. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1022. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1023. return QDF_STATUS_E_RESOURCES;
  1024. }
  1025. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1026. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1027. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  1028. return QDF_STATUS_SUCCESS;
  1029. }
  1030. /**
  1031. * dp_cce_classify() - Classify the frame based on CCE rules
  1032. * @vdev: DP vdev handle
  1033. * @nbuf: skb
  1034. *
  1035. * Classify frames based on CCE rules
  1036. * Return: bool( true if classified,
  1037. * else false)
  1038. */
  1039. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1040. {
  1041. qdf_ether_header_t *eh = NULL;
  1042. uint16_t ether_type;
  1043. qdf_llc_t *llcHdr;
  1044. qdf_nbuf_t nbuf_clone = NULL;
  1045. qdf_dot3_qosframe_t *qos_wh = NULL;
  1046. /* for mesh packets don't do any classification */
  1047. if (qdf_unlikely(vdev->mesh_vdev))
  1048. return false;
  1049. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1050. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1051. ether_type = eh->ether_type;
  1052. llcHdr = (qdf_llc_t *)(nbuf->data +
  1053. sizeof(qdf_ether_header_t));
  1054. } else {
  1055. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1056. /* For encrypted packets don't do any classification */
  1057. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1058. return false;
  1059. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1060. if (qdf_unlikely(
  1061. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1062. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1063. ether_type = *(uint16_t *)(nbuf->data
  1064. + QDF_IEEE80211_4ADDR_HDR_LEN
  1065. + sizeof(qdf_llc_t)
  1066. - sizeof(ether_type));
  1067. llcHdr = (qdf_llc_t *)(nbuf->data +
  1068. QDF_IEEE80211_4ADDR_HDR_LEN);
  1069. } else {
  1070. ether_type = *(uint16_t *)(nbuf->data
  1071. + QDF_IEEE80211_3ADDR_HDR_LEN
  1072. + sizeof(qdf_llc_t)
  1073. - sizeof(ether_type));
  1074. llcHdr = (qdf_llc_t *)(nbuf->data +
  1075. QDF_IEEE80211_3ADDR_HDR_LEN);
  1076. }
  1077. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1078. && (ether_type ==
  1079. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1080. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1081. return true;
  1082. }
  1083. }
  1084. return false;
  1085. }
  1086. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1087. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1088. sizeof(*llcHdr));
  1089. nbuf_clone = qdf_nbuf_clone(nbuf);
  1090. if (qdf_unlikely(nbuf_clone)) {
  1091. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1092. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1093. qdf_nbuf_pull_head(nbuf_clone,
  1094. sizeof(qdf_net_vlanhdr_t));
  1095. }
  1096. }
  1097. } else {
  1098. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1099. nbuf_clone = qdf_nbuf_clone(nbuf);
  1100. if (qdf_unlikely(nbuf_clone)) {
  1101. qdf_nbuf_pull_head(nbuf_clone,
  1102. sizeof(qdf_net_vlanhdr_t));
  1103. }
  1104. }
  1105. }
  1106. if (qdf_unlikely(nbuf_clone))
  1107. nbuf = nbuf_clone;
  1108. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1109. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1110. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1111. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1112. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1113. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1114. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1115. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1116. if (qdf_unlikely(nbuf_clone))
  1117. qdf_nbuf_free(nbuf_clone);
  1118. return true;
  1119. }
  1120. if (qdf_unlikely(nbuf_clone))
  1121. qdf_nbuf_free(nbuf_clone);
  1122. return false;
  1123. }
  1124. /**
  1125. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1126. * @vdev: DP vdev handle
  1127. * @nbuf: skb
  1128. *
  1129. * Extract the DSCP or PCP information from frame and map into TID value.
  1130. *
  1131. * Return: void
  1132. */
  1133. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1134. struct dp_tx_msdu_info_s *msdu_info)
  1135. {
  1136. uint8_t tos = 0, dscp_tid_override = 0;
  1137. uint8_t *hdr_ptr, *L3datap;
  1138. uint8_t is_mcast = 0;
  1139. qdf_ether_header_t *eh = NULL;
  1140. qdf_ethervlan_header_t *evh = NULL;
  1141. uint16_t ether_type;
  1142. qdf_llc_t *llcHdr;
  1143. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1144. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1145. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1146. eh = (qdf_ether_header_t *)nbuf->data;
  1147. hdr_ptr = eh->ether_dhost;
  1148. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1149. } else {
  1150. qdf_dot3_qosframe_t *qos_wh =
  1151. (qdf_dot3_qosframe_t *) nbuf->data;
  1152. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1153. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1154. return;
  1155. }
  1156. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1157. ether_type = eh->ether_type;
  1158. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1159. /*
  1160. * Check if packet is dot3 or eth2 type.
  1161. */
  1162. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1163. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1164. sizeof(*llcHdr));
  1165. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1166. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1167. sizeof(*llcHdr);
  1168. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1169. + sizeof(*llcHdr) +
  1170. sizeof(qdf_net_vlanhdr_t));
  1171. } else {
  1172. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1173. sizeof(*llcHdr);
  1174. }
  1175. } else {
  1176. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1177. evh = (qdf_ethervlan_header_t *) eh;
  1178. ether_type = evh->ether_type;
  1179. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1180. }
  1181. }
  1182. /*
  1183. * Find priority from IP TOS DSCP field
  1184. */
  1185. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1186. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1187. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1188. /* Only for unicast frames */
  1189. if (!is_mcast) {
  1190. /* send it on VO queue */
  1191. msdu_info->tid = DP_VO_TID;
  1192. }
  1193. } else {
  1194. /*
  1195. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1196. * from TOS byte.
  1197. */
  1198. tos = ip->ip_tos;
  1199. dscp_tid_override = 1;
  1200. }
  1201. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1202. /* TODO
  1203. * use flowlabel
  1204. *igmpmld cases to be handled in phase 2
  1205. */
  1206. unsigned long ver_pri_flowlabel;
  1207. unsigned long pri;
  1208. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1209. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1210. DP_IPV6_PRIORITY_SHIFT;
  1211. tos = pri;
  1212. dscp_tid_override = 1;
  1213. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1214. msdu_info->tid = DP_VO_TID;
  1215. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1216. /* Only for unicast frames */
  1217. if (!is_mcast) {
  1218. /* send ucast arp on VO queue */
  1219. msdu_info->tid = DP_VO_TID;
  1220. }
  1221. }
  1222. /*
  1223. * Assign all MCAST packets to BE
  1224. */
  1225. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1226. if (is_mcast) {
  1227. tos = 0;
  1228. dscp_tid_override = 1;
  1229. }
  1230. }
  1231. if (dscp_tid_override == 1) {
  1232. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1233. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1234. }
  1235. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1236. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1237. return;
  1238. }
  1239. /**
  1240. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1241. * @vdev: DP vdev handle
  1242. * @nbuf: skb
  1243. *
  1244. * Software based TID classification is required when more than 2 DSCP-TID
  1245. * mapping tables are needed.
  1246. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1247. *
  1248. * Return: void
  1249. */
  1250. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1251. struct dp_tx_msdu_info_s *msdu_info)
  1252. {
  1253. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1254. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1255. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1256. return;
  1257. /* for mesh packets don't do any classification */
  1258. if (qdf_unlikely(vdev->mesh_vdev))
  1259. return;
  1260. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1261. }
  1262. #ifdef FEATURE_WLAN_TDLS
  1263. /**
  1264. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1265. * @tx_desc: TX descriptor
  1266. *
  1267. * Return: None
  1268. */
  1269. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1270. {
  1271. if (tx_desc->vdev) {
  1272. if (tx_desc->vdev->is_tdls_frame) {
  1273. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1274. tx_desc->vdev->is_tdls_frame = false;
  1275. }
  1276. }
  1277. }
  1278. /**
  1279. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1280. * @tx_desc: TX descriptor
  1281. * @vdev: datapath vdev handle
  1282. *
  1283. * Return: None
  1284. */
  1285. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1286. struct dp_vdev *vdev)
  1287. {
  1288. struct hal_tx_completion_status ts = {0};
  1289. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1290. if (qdf_unlikely(!vdev)) {
  1291. dp_err("vdev is null!");
  1292. return;
  1293. }
  1294. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1295. if (vdev->tx_non_std_data_callback.func) {
  1296. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1297. vdev->tx_non_std_data_callback.func(
  1298. vdev->tx_non_std_data_callback.ctxt,
  1299. nbuf, ts.status);
  1300. return;
  1301. }
  1302. }
  1303. #else
  1304. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1305. {
  1306. }
  1307. static inline void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1308. struct dp_vdev *vdev)
  1309. {
  1310. }
  1311. #endif
  1312. /**
  1313. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1314. * @vdev: DP vdev handle
  1315. * @nbuf: skb
  1316. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1317. * @meta_data: Metadata to the fw
  1318. * @tx_q: Tx queue to be used for this Tx frame
  1319. * @peer_id: peer_id of the peer in case of NAWDS frames
  1320. * @tx_exc_metadata: Handle that holds exception path metadata
  1321. *
  1322. * Return: NULL on success,
  1323. * nbuf when it fails to send
  1324. */
  1325. qdf_nbuf_t
  1326. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1327. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1328. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1329. {
  1330. struct dp_pdev *pdev = vdev->pdev;
  1331. struct dp_soc *soc = pdev->soc;
  1332. struct dp_tx_desc_s *tx_desc;
  1333. QDF_STATUS status;
  1334. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1335. hal_ring_handle_t hal_ring_hdl =
  1336. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1337. uint16_t htt_tcl_metadata = 0;
  1338. uint8_t tid = msdu_info->tid;
  1339. struct cdp_tid_tx_stats *tid_stats = NULL;
  1340. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1341. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1342. msdu_info, tx_exc_metadata);
  1343. if (!tx_desc) {
  1344. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1345. vdev, tx_q->desc_pool_id);
  1346. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1347. tid_stats = &pdev->stats.tid_stats.
  1348. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1349. tid_stats->swdrop_cnt[TX_DESC_ERR]++;
  1350. return nbuf;
  1351. }
  1352. if (qdf_unlikely(soc->cce_disable)) {
  1353. if (dp_cce_classify(vdev, nbuf) == true) {
  1354. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1355. tid = DP_VO_TID;
  1356. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1357. }
  1358. }
  1359. dp_tx_update_tdls_flags(tx_desc);
  1360. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1361. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1362. "%s %d : HAL RING Access Failed -- %pK",
  1363. __func__, __LINE__, hal_ring_hdl);
  1364. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1365. tid_stats = &pdev->stats.tid_stats.
  1366. tid_tx_stats[tx_q->ring_id][tid];
  1367. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1368. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1369. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1370. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1371. goto fail_return;
  1372. }
  1373. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1374. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1375. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1376. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1377. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1378. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1379. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1380. peer_id);
  1381. } else
  1382. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1383. if (msdu_info->exception_fw) {
  1384. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1385. }
  1386. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1387. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1388. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1389. if (status != QDF_STATUS_SUCCESS) {
  1390. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1391. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1392. __func__, tx_desc, tx_q->ring_id);
  1393. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1394. tid_stats = &pdev->stats.tid_stats.
  1395. tid_tx_stats[tx_q->ring_id][tid];
  1396. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1397. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1398. qdf_nbuf_unmap(vdev->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1399. goto fail_return;
  1400. }
  1401. nbuf = NULL;
  1402. fail_return:
  1403. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1404. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1405. hif_pm_runtime_put(soc->hif_handle);
  1406. } else {
  1407. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1408. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1409. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1410. }
  1411. return nbuf;
  1412. }
  1413. /**
  1414. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1415. * @vdev: DP vdev handle
  1416. * @nbuf: skb
  1417. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1418. *
  1419. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1420. *
  1421. * Return: NULL on success,
  1422. * nbuf when it fails to send
  1423. */
  1424. #if QDF_LOCK_STATS
  1425. noinline
  1426. #else
  1427. #endif
  1428. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1429. struct dp_tx_msdu_info_s *msdu_info)
  1430. {
  1431. uint8_t i;
  1432. struct dp_pdev *pdev = vdev->pdev;
  1433. struct dp_soc *soc = pdev->soc;
  1434. struct dp_tx_desc_s *tx_desc;
  1435. bool is_cce_classified = false;
  1436. QDF_STATUS status;
  1437. uint16_t htt_tcl_metadata = 0;
  1438. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1439. hal_ring_handle_t hal_ring_hdl =
  1440. soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1441. struct cdp_tid_tx_stats *tid_stats = NULL;
  1442. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_ring_hdl))) {
  1443. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1444. "%s %d : HAL RING Access Failed -- %pK",
  1445. __func__, __LINE__, hal_ring_hdl);
  1446. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1447. tid_stats = &pdev->stats.tid_stats.
  1448. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1449. tid_stats->swdrop_cnt[TX_HAL_RING_ACCESS_ERR]++;
  1450. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1451. return nbuf;
  1452. }
  1453. if (qdf_unlikely(soc->cce_disable)) {
  1454. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1455. if (is_cce_classified) {
  1456. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1457. msdu_info->tid = DP_VO_TID;
  1458. }
  1459. }
  1460. if (msdu_info->frm_type == dp_tx_frm_me)
  1461. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1462. i = 0;
  1463. /* Print statement to track i and num_seg */
  1464. /*
  1465. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1466. * descriptors using information in msdu_info
  1467. */
  1468. while (i < msdu_info->num_seg) {
  1469. /*
  1470. * Setup Tx descriptor for an MSDU, and MSDU extension
  1471. * descriptor
  1472. */
  1473. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1474. tx_q->desc_pool_id);
  1475. if (!tx_desc) {
  1476. if (msdu_info->frm_type == dp_tx_frm_me) {
  1477. dp_tx_me_free_buf(pdev,
  1478. (void *)(msdu_info->u.sg_info
  1479. .curr_seg->frags[0].vaddr));
  1480. i++;
  1481. continue;
  1482. }
  1483. goto done;
  1484. }
  1485. if (msdu_info->frm_type == dp_tx_frm_me) {
  1486. tx_desc->me_buffer =
  1487. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1488. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1489. }
  1490. if (is_cce_classified)
  1491. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1492. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1493. if (msdu_info->exception_fw) {
  1494. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1495. }
  1496. /*
  1497. * Enqueue the Tx MSDU descriptor to HW for transmit
  1498. */
  1499. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1500. htt_tcl_metadata, tx_q->ring_id, NULL);
  1501. if (status != QDF_STATUS_SUCCESS) {
  1502. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1503. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1504. __func__, tx_desc, tx_q->ring_id);
  1505. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1506. tid_stats = &pdev->stats.tid_stats.
  1507. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1508. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1509. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1510. if (msdu_info->frm_type == dp_tx_frm_me) {
  1511. i++;
  1512. continue;
  1513. }
  1514. goto done;
  1515. }
  1516. /*
  1517. * TODO
  1518. * if tso_info structure can be modified to have curr_seg
  1519. * as first element, following 2 blocks of code (for TSO and SG)
  1520. * can be combined into 1
  1521. */
  1522. /*
  1523. * For frames with multiple segments (TSO, ME), jump to next
  1524. * segment.
  1525. */
  1526. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1527. if (msdu_info->u.tso_info.curr_seg->next) {
  1528. msdu_info->u.tso_info.curr_seg =
  1529. msdu_info->u.tso_info.curr_seg->next;
  1530. /*
  1531. * If this is a jumbo nbuf, then increment the number of
  1532. * nbuf users for each additional segment of the msdu.
  1533. * This will ensure that the skb is freed only after
  1534. * receiving tx completion for all segments of an nbuf
  1535. */
  1536. qdf_nbuf_inc_users(nbuf);
  1537. /* Check with MCL if this is needed */
  1538. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1539. }
  1540. }
  1541. /*
  1542. * For Multicast-Unicast converted packets,
  1543. * each converted frame (for a client) is represented as
  1544. * 1 segment
  1545. */
  1546. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1547. (msdu_info->frm_type == dp_tx_frm_me)) {
  1548. if (msdu_info->u.sg_info.curr_seg->next) {
  1549. msdu_info->u.sg_info.curr_seg =
  1550. msdu_info->u.sg_info.curr_seg->next;
  1551. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1552. }
  1553. }
  1554. i++;
  1555. }
  1556. nbuf = NULL;
  1557. done:
  1558. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1559. hal_srng_access_end(soc->hal_soc, hal_ring_hdl);
  1560. hif_pm_runtime_put(soc->hif_handle);
  1561. } else {
  1562. hal_srng_access_end_reap(soc->hal_soc, hal_ring_hdl);
  1563. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1564. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1565. }
  1566. return nbuf;
  1567. }
  1568. /**
  1569. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1570. * for SG frames
  1571. * @vdev: DP vdev handle
  1572. * @nbuf: skb
  1573. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1574. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1575. *
  1576. * Return: NULL on success,
  1577. * nbuf when it fails to send
  1578. */
  1579. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1580. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1581. {
  1582. uint32_t cur_frag, nr_frags;
  1583. qdf_dma_addr_t paddr;
  1584. struct dp_tx_sg_info_s *sg_info;
  1585. sg_info = &msdu_info->u.sg_info;
  1586. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1587. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1588. QDF_DMA_TO_DEVICE)) {
  1589. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1590. "dma map error");
  1591. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1592. qdf_nbuf_free(nbuf);
  1593. return NULL;
  1594. }
  1595. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1596. seg_info->frags[0].paddr_lo = paddr;
  1597. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1598. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1599. seg_info->frags[0].vaddr = (void *) nbuf;
  1600. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1601. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1602. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1603. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1604. "frag dma map error");
  1605. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1606. qdf_nbuf_free(nbuf);
  1607. return NULL;
  1608. }
  1609. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1610. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1611. seg_info->frags[cur_frag + 1].paddr_hi =
  1612. ((uint64_t) paddr) >> 32;
  1613. seg_info->frags[cur_frag + 1].len =
  1614. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1615. }
  1616. seg_info->frag_cnt = (cur_frag + 1);
  1617. seg_info->total_len = qdf_nbuf_len(nbuf);
  1618. seg_info->next = NULL;
  1619. sg_info->curr_seg = seg_info;
  1620. msdu_info->frm_type = dp_tx_frm_sg;
  1621. msdu_info->num_seg = 1;
  1622. return nbuf;
  1623. }
  1624. /**
  1625. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1626. * @vdev: DP vdev handle
  1627. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1628. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1629. *
  1630. * Return: NULL on failure,
  1631. * nbuf when extracted successfully
  1632. */
  1633. static
  1634. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1635. struct dp_tx_msdu_info_s *msdu_info,
  1636. uint16_t ppdu_cookie)
  1637. {
  1638. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1639. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1640. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1641. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1642. (msdu_info->meta_data[5], 1);
  1643. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1644. (msdu_info->meta_data[5], 1);
  1645. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1646. (msdu_info->meta_data[6], ppdu_cookie);
  1647. msdu_info->exception_fw = 1;
  1648. msdu_info->is_tx_sniffer = 1;
  1649. }
  1650. #ifdef MESH_MODE_SUPPORT
  1651. /**
  1652. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1653. and prepare msdu_info for mesh frames.
  1654. * @vdev: DP vdev handle
  1655. * @nbuf: skb
  1656. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1657. *
  1658. * Return: NULL on failure,
  1659. * nbuf when extracted successfully
  1660. */
  1661. static
  1662. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1663. struct dp_tx_msdu_info_s *msdu_info)
  1664. {
  1665. struct meta_hdr_s *mhdr;
  1666. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1667. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1668. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1669. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1670. msdu_info->exception_fw = 0;
  1671. goto remove_meta_hdr;
  1672. }
  1673. msdu_info->exception_fw = 1;
  1674. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1675. meta_data->host_tx_desc_pool = 1;
  1676. meta_data->update_peer_cache = 1;
  1677. meta_data->learning_frame = 1;
  1678. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1679. meta_data->power = mhdr->power;
  1680. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1681. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1682. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1683. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1684. meta_data->dyn_bw = 1;
  1685. meta_data->valid_pwr = 1;
  1686. meta_data->valid_mcs_mask = 1;
  1687. meta_data->valid_nss_mask = 1;
  1688. meta_data->valid_preamble_type = 1;
  1689. meta_data->valid_retries = 1;
  1690. meta_data->valid_bw_info = 1;
  1691. }
  1692. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1693. meta_data->encrypt_type = 0;
  1694. meta_data->valid_encrypt_type = 1;
  1695. meta_data->learning_frame = 0;
  1696. }
  1697. meta_data->valid_key_flags = 1;
  1698. meta_data->key_flags = (mhdr->keyix & 0x3);
  1699. remove_meta_hdr:
  1700. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1701. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1702. "qdf_nbuf_pull_head failed");
  1703. qdf_nbuf_free(nbuf);
  1704. return NULL;
  1705. }
  1706. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1707. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1708. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1709. " tid %d to_fw %d",
  1710. __func__, msdu_info->meta_data[0],
  1711. msdu_info->meta_data[1],
  1712. msdu_info->meta_data[2],
  1713. msdu_info->meta_data[3],
  1714. msdu_info->meta_data[4],
  1715. msdu_info->meta_data[5],
  1716. msdu_info->tid, msdu_info->exception_fw);
  1717. return nbuf;
  1718. }
  1719. #else
  1720. static
  1721. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1722. struct dp_tx_msdu_info_s *msdu_info)
  1723. {
  1724. return nbuf;
  1725. }
  1726. #endif
  1727. /**
  1728. * dp_check_exc_metadata() - Checks if parameters are valid
  1729. * @tx_exc - holds all exception path parameters
  1730. *
  1731. * Returns true when all the parameters are valid else false
  1732. *
  1733. */
  1734. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1735. {
  1736. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1737. HTT_INVALID_TID);
  1738. bool invalid_encap_type =
  1739. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1740. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1741. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1742. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1743. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1744. tx_exc->ppdu_cookie == 0);
  1745. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1746. invalid_cookie) {
  1747. return false;
  1748. }
  1749. return true;
  1750. }
  1751. /**
  1752. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1753. * @vap_dev: DP vdev handle
  1754. * @nbuf: skb
  1755. * @tx_exc_metadata: Handle that holds exception path meta data
  1756. *
  1757. * Entry point for Core Tx layer (DP_TX) invoked from
  1758. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1759. *
  1760. * Return: NULL on success,
  1761. * nbuf when it fails to send
  1762. */
  1763. qdf_nbuf_t
  1764. dp_tx_send_exception(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf,
  1765. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1766. {
  1767. qdf_ether_header_t *eh = NULL;
  1768. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1769. struct dp_tx_msdu_info_s msdu_info;
  1770. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1771. if (!tx_exc_metadata)
  1772. goto fail;
  1773. msdu_info.tid = tx_exc_metadata->tid;
  1774. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1775. dp_verbose_debug("skb %pM", nbuf->data);
  1776. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1777. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1779. "Invalid parameters in exception path");
  1780. goto fail;
  1781. }
  1782. /* Basic sanity checks for unsupported packets */
  1783. /* MESH mode */
  1784. if (qdf_unlikely(vdev->mesh_vdev)) {
  1785. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1786. "Mesh mode is not supported in exception path");
  1787. goto fail;
  1788. }
  1789. /* TSO or SG */
  1790. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1791. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1792. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1793. "TSO and SG are not supported in exception path");
  1794. goto fail;
  1795. }
  1796. /* RAW */
  1797. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1798. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1799. "Raw frame is not supported in exception path");
  1800. goto fail;
  1801. }
  1802. /* Mcast enhancement*/
  1803. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1804. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1805. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1806. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1807. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1808. }
  1809. }
  1810. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1811. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1812. qdf_nbuf_len(nbuf));
  1813. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1814. tx_exc_metadata->ppdu_cookie);
  1815. }
  1816. /*
  1817. * Get HW Queue to use for this frame.
  1818. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1819. * dedicated for data and 1 for command.
  1820. * "queue_id" maps to one hardware ring.
  1821. * With each ring, we also associate a unique Tx descriptor pool
  1822. * to minimize lock contention for these resources.
  1823. */
  1824. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1825. /* Single linear frame */
  1826. /*
  1827. * If nbuf is a simple linear frame, use send_single function to
  1828. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1829. * SRNG. There is no need to setup a MSDU extension descriptor.
  1830. */
  1831. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1832. tx_exc_metadata->peer_id, tx_exc_metadata);
  1833. return nbuf;
  1834. fail:
  1835. dp_verbose_debug("pkt send failed");
  1836. return nbuf;
  1837. }
  1838. /**
  1839. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1840. * @vap_dev: DP vdev handle
  1841. * @nbuf: skb
  1842. *
  1843. * Entry point for Core Tx layer (DP_TX) invoked from
  1844. * hard_start_xmit in OSIF/HDD
  1845. *
  1846. * Return: NULL on success,
  1847. * nbuf when it fails to send
  1848. */
  1849. #ifdef MESH_MODE_SUPPORT
  1850. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1851. {
  1852. struct meta_hdr_s *mhdr;
  1853. qdf_nbuf_t nbuf_mesh = NULL;
  1854. qdf_nbuf_t nbuf_clone = NULL;
  1855. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1856. uint8_t no_enc_frame = 0;
  1857. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1858. if (!nbuf_mesh) {
  1859. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1860. "qdf_nbuf_unshare failed");
  1861. return nbuf;
  1862. }
  1863. nbuf = nbuf_mesh;
  1864. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1865. if ((vdev->sec_type != cdp_sec_type_none) &&
  1866. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1867. no_enc_frame = 1;
  1868. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1869. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  1870. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1871. !no_enc_frame) {
  1872. nbuf_clone = qdf_nbuf_clone(nbuf);
  1873. if (!nbuf_clone) {
  1874. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1875. "qdf_nbuf_clone failed");
  1876. return nbuf;
  1877. }
  1878. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1879. }
  1880. if (nbuf_clone) {
  1881. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1882. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1883. } else {
  1884. qdf_nbuf_free(nbuf_clone);
  1885. }
  1886. }
  1887. if (no_enc_frame)
  1888. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1889. else
  1890. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1891. nbuf = dp_tx_send(vap_dev, nbuf);
  1892. if ((!nbuf) && no_enc_frame) {
  1893. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1894. }
  1895. return nbuf;
  1896. }
  1897. #else
  1898. qdf_nbuf_t dp_tx_send_mesh(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1899. {
  1900. return dp_tx_send(vap_dev, nbuf);
  1901. }
  1902. #endif
  1903. /**
  1904. * dp_tx_send() - Transmit a frame on a given VAP
  1905. * @vap_dev: DP vdev handle
  1906. * @nbuf: skb
  1907. *
  1908. * Entry point for Core Tx layer (DP_TX) invoked from
  1909. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1910. * cases
  1911. *
  1912. * Return: NULL on success,
  1913. * nbuf when it fails to send
  1914. */
  1915. qdf_nbuf_t dp_tx_send(struct cdp_vdev *vap_dev, qdf_nbuf_t nbuf)
  1916. {
  1917. qdf_ether_header_t *eh = NULL;
  1918. struct dp_tx_msdu_info_s msdu_info;
  1919. struct dp_tx_seg_info_s seg_info;
  1920. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1921. uint16_t peer_id = HTT_INVALID_PEER;
  1922. qdf_nbuf_t nbuf_mesh = NULL;
  1923. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1924. qdf_mem_zero(&seg_info, sizeof(seg_info));
  1925. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1926. dp_verbose_debug("skb %pM", nbuf->data);
  1927. /*
  1928. * Set Default Host TID value to invalid TID
  1929. * (TID override disabled)
  1930. */
  1931. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1932. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1933. if (qdf_unlikely(vdev->mesh_vdev)) {
  1934. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1935. &msdu_info);
  1936. if (!nbuf_mesh) {
  1937. dp_verbose_debug("Extracting mesh metadata failed");
  1938. return nbuf;
  1939. }
  1940. nbuf = nbuf_mesh;
  1941. }
  1942. /*
  1943. * Get HW Queue to use for this frame.
  1944. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1945. * dedicated for data and 1 for command.
  1946. * "queue_id" maps to one hardware ring.
  1947. * With each ring, we also associate a unique Tx descriptor pool
  1948. * to minimize lock contention for these resources.
  1949. */
  1950. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1951. /*
  1952. * TCL H/W supports 2 DSCP-TID mapping tables.
  1953. * Table 1 - Default DSCP-TID mapping table
  1954. * Table 2 - 1 DSCP-TID override table
  1955. *
  1956. * If we need a different DSCP-TID mapping for this vap,
  1957. * call tid_classify to extract DSCP/ToS from frame and
  1958. * map to a TID and store in msdu_info. This is later used
  1959. * to fill in TCL Input descriptor (per-packet TID override).
  1960. */
  1961. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1962. /*
  1963. * Classify the frame and call corresponding
  1964. * "prepare" function which extracts the segment (TSO)
  1965. * and fragmentation information (for TSO , SG, ME, or Raw)
  1966. * into MSDU_INFO structure which is later used to fill
  1967. * SW and HW descriptors.
  1968. */
  1969. if (qdf_nbuf_is_tso(nbuf)) {
  1970. dp_verbose_debug("TSO frame %pK", vdev);
  1971. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  1972. qdf_nbuf_len(nbuf));
  1973. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1974. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  1975. qdf_nbuf_len(nbuf));
  1976. return nbuf;
  1977. }
  1978. goto send_multiple;
  1979. }
  1980. /* SG */
  1981. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1982. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1983. if (!nbuf)
  1984. return NULL;
  1985. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  1986. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1987. qdf_nbuf_len(nbuf));
  1988. goto send_multiple;
  1989. }
  1990. #ifdef ATH_SUPPORT_IQUE
  1991. /* Mcast to Ucast Conversion*/
  1992. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1993. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1994. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1995. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1996. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  1997. DP_STATS_INC_PKT(vdev,
  1998. tx_i.mcast_en.mcast_pkt, 1,
  1999. qdf_nbuf_len(nbuf));
  2000. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2001. QDF_STATUS_SUCCESS) {
  2002. return NULL;
  2003. }
  2004. }
  2005. }
  2006. #endif
  2007. /* RAW */
  2008. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2009. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2010. if (!nbuf)
  2011. return NULL;
  2012. dp_verbose_debug("Raw frame %pK", vdev);
  2013. goto send_multiple;
  2014. }
  2015. /* Single linear frame */
  2016. /*
  2017. * If nbuf is a simple linear frame, use send_single function to
  2018. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2019. * SRNG. There is no need to setup a MSDU extension descriptor.
  2020. */
  2021. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2022. return nbuf;
  2023. send_multiple:
  2024. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2025. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2026. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2027. return nbuf;
  2028. }
  2029. /**
  2030. * dp_tx_reinject_handler() - Tx Reinject Handler
  2031. * @tx_desc: software descriptor head pointer
  2032. * @status : Tx completion status from HTT descriptor
  2033. *
  2034. * This function reinjects frames back to Target.
  2035. * Todo - Host queue needs to be added
  2036. *
  2037. * Return: none
  2038. */
  2039. static
  2040. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2041. {
  2042. struct dp_vdev *vdev;
  2043. struct dp_peer *peer = NULL;
  2044. uint32_t peer_id = HTT_INVALID_PEER;
  2045. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2046. qdf_nbuf_t nbuf_copy = NULL;
  2047. struct dp_tx_msdu_info_s msdu_info;
  2048. struct dp_peer *sa_peer = NULL;
  2049. struct dp_ast_entry *ast_entry = NULL;
  2050. struct dp_soc *soc = NULL;
  2051. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2052. #ifdef WDS_VENDOR_EXTENSION
  2053. int is_mcast = 0, is_ucast = 0;
  2054. int num_peers_3addr = 0;
  2055. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2056. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2057. #endif
  2058. vdev = tx_desc->vdev;
  2059. soc = vdev->pdev->soc;
  2060. qdf_assert(vdev);
  2061. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2062. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2063. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2064. "%s Tx reinject path", __func__);
  2065. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2066. qdf_nbuf_len(tx_desc->nbuf));
  2067. qdf_spin_lock_bh(&(soc->ast_lock));
  2068. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2069. (soc,
  2070. (uint8_t *)(eh->ether_shost),
  2071. vdev->pdev->pdev_id);
  2072. if (ast_entry)
  2073. sa_peer = ast_entry->peer;
  2074. qdf_spin_unlock_bh(&(soc->ast_lock));
  2075. #ifdef WDS_VENDOR_EXTENSION
  2076. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2077. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2078. } else {
  2079. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2080. }
  2081. is_ucast = !is_mcast;
  2082. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2083. if (peer->bss_peer)
  2084. continue;
  2085. /* Detect wds peers that use 3-addr framing for mcast.
  2086. * if there are any, the bss_peer is used to send the
  2087. * the mcast frame using 3-addr format. all wds enabled
  2088. * peers that use 4-addr framing for mcast frames will
  2089. * be duplicated and sent as 4-addr frames below.
  2090. */
  2091. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2092. num_peers_3addr = 1;
  2093. break;
  2094. }
  2095. }
  2096. #endif
  2097. if (qdf_unlikely(vdev->mesh_vdev)) {
  2098. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2099. } else {
  2100. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2101. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  2102. #ifdef WDS_VENDOR_EXTENSION
  2103. /*
  2104. * . if 3-addr STA, then send on BSS Peer
  2105. * . if Peer WDS enabled and accept 4-addr mcast,
  2106. * send mcast on that peer only
  2107. * . if Peer WDS enabled and accept 4-addr ucast,
  2108. * send ucast on that peer only
  2109. */
  2110. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2111. (peer->wds_enabled &&
  2112. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2113. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2114. #else
  2115. ((peer->bss_peer &&
  2116. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  2117. peer->nawds_enabled)) {
  2118. #endif
  2119. peer_id = DP_INVALID_PEER;
  2120. if (peer->nawds_enabled) {
  2121. peer_id = peer->peer_ids[0];
  2122. if (sa_peer == peer) {
  2123. QDF_TRACE(
  2124. QDF_MODULE_ID_DP,
  2125. QDF_TRACE_LEVEL_DEBUG,
  2126. " %s: multicast packet",
  2127. __func__);
  2128. DP_STATS_INC(peer,
  2129. tx.nawds_mcast_drop, 1);
  2130. continue;
  2131. }
  2132. }
  2133. nbuf_copy = qdf_nbuf_copy(nbuf);
  2134. if (!nbuf_copy) {
  2135. QDF_TRACE(QDF_MODULE_ID_DP,
  2136. QDF_TRACE_LEVEL_DEBUG,
  2137. FL("nbuf copy failed"));
  2138. break;
  2139. }
  2140. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2141. nbuf_copy,
  2142. &msdu_info,
  2143. peer_id,
  2144. NULL);
  2145. if (nbuf_copy) {
  2146. QDF_TRACE(QDF_MODULE_ID_DP,
  2147. QDF_TRACE_LEVEL_DEBUG,
  2148. FL("pkt send failed"));
  2149. qdf_nbuf_free(nbuf_copy);
  2150. } else {
  2151. if (peer_id != DP_INVALID_PEER)
  2152. DP_STATS_INC_PKT(peer,
  2153. tx.nawds_mcast,
  2154. 1, qdf_nbuf_len(nbuf));
  2155. }
  2156. }
  2157. }
  2158. }
  2159. if (vdev->nawds_enabled) {
  2160. peer_id = DP_INVALID_PEER;
  2161. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2162. 1, qdf_nbuf_len(nbuf));
  2163. nbuf = dp_tx_send_msdu_single(vdev,
  2164. nbuf,
  2165. &msdu_info,
  2166. peer_id, NULL);
  2167. if (nbuf) {
  2168. QDF_TRACE(QDF_MODULE_ID_DP,
  2169. QDF_TRACE_LEVEL_DEBUG,
  2170. FL("pkt send failed"));
  2171. qdf_nbuf_free(nbuf);
  2172. }
  2173. } else
  2174. qdf_nbuf_free(nbuf);
  2175. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2176. }
  2177. /**
  2178. * dp_tx_inspect_handler() - Tx Inspect Handler
  2179. * @tx_desc: software descriptor head pointer
  2180. * @status : Tx completion status from HTT descriptor
  2181. *
  2182. * Handles Tx frames sent back to Host for inspection
  2183. * (ProxyARP)
  2184. *
  2185. * Return: none
  2186. */
  2187. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2188. {
  2189. struct dp_soc *soc;
  2190. struct dp_pdev *pdev = tx_desc->pdev;
  2191. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2192. "%s Tx inspect path",
  2193. __func__);
  2194. qdf_assert(pdev);
  2195. soc = pdev->soc;
  2196. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2197. qdf_nbuf_len(tx_desc->nbuf));
  2198. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2199. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2200. }
  2201. #ifdef FEATURE_PERPKT_INFO
  2202. /**
  2203. * dp_get_completion_indication_for_stack() - send completion to stack
  2204. * @soc : dp_soc handle
  2205. * @pdev: dp_pdev handle
  2206. * @peer: dp peer handle
  2207. * @ts: transmit completion status structure
  2208. * @netbuf: Buffer pointer for free
  2209. *
  2210. * This function is used for indication whether buffer needs to be
  2211. * sent to stack for freeing or not
  2212. */
  2213. QDF_STATUS
  2214. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2215. struct dp_pdev *pdev,
  2216. struct dp_peer *peer,
  2217. struct hal_tx_completion_status *ts,
  2218. qdf_nbuf_t netbuf,
  2219. uint64_t time_latency)
  2220. {
  2221. struct tx_capture_hdr *ppdu_hdr;
  2222. uint16_t peer_id = ts->peer_id;
  2223. uint32_t ppdu_id = ts->ppdu_id;
  2224. uint8_t first_msdu = ts->first_msdu;
  2225. uint8_t last_msdu = ts->last_msdu;
  2226. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2227. !pdev->latency_capture_enable))
  2228. return QDF_STATUS_E_NOSUPPORT;
  2229. if (!peer) {
  2230. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2231. FL("Peer Invalid"));
  2232. return QDF_STATUS_E_INVAL;
  2233. }
  2234. if (pdev->mcopy_mode) {
  2235. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2236. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2237. return QDF_STATUS_E_INVAL;
  2238. }
  2239. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2240. pdev->m_copy_id.tx_peer_id = peer_id;
  2241. }
  2242. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2243. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2244. FL("No headroom"));
  2245. return QDF_STATUS_E_NOMEM;
  2246. }
  2247. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2248. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2249. QDF_MAC_ADDR_SIZE);
  2250. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2251. QDF_MAC_ADDR_SIZE);
  2252. ppdu_hdr->ppdu_id = ppdu_id;
  2253. ppdu_hdr->peer_id = peer_id;
  2254. ppdu_hdr->first_msdu = first_msdu;
  2255. ppdu_hdr->last_msdu = last_msdu;
  2256. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2257. ppdu_hdr->tsf = ts->tsf;
  2258. ppdu_hdr->time_latency = time_latency;
  2259. }
  2260. return QDF_STATUS_SUCCESS;
  2261. }
  2262. /**
  2263. * dp_send_completion_to_stack() - send completion to stack
  2264. * @soc : dp_soc handle
  2265. * @pdev: dp_pdev handle
  2266. * @peer_id: peer_id of the peer for which completion came
  2267. * @ppdu_id: ppdu_id
  2268. * @netbuf: Buffer pointer for free
  2269. *
  2270. * This function is used to send completion to stack
  2271. * to free buffer
  2272. */
  2273. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2274. uint16_t peer_id, uint32_t ppdu_id,
  2275. qdf_nbuf_t netbuf)
  2276. {
  2277. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2278. netbuf, peer_id,
  2279. WDI_NO_VAL, pdev->pdev_id);
  2280. }
  2281. #else
  2282. static QDF_STATUS
  2283. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2284. struct dp_pdev *pdev,
  2285. struct dp_peer *peer,
  2286. struct hal_tx_completion_status *ts,
  2287. qdf_nbuf_t netbuf,
  2288. uint64_t time_latency)
  2289. {
  2290. return QDF_STATUS_E_NOSUPPORT;
  2291. }
  2292. static void
  2293. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2294. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2295. {
  2296. }
  2297. #endif
  2298. /**
  2299. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2300. * @soc: Soc handle
  2301. * @desc: software Tx descriptor to be processed
  2302. *
  2303. * Return: none
  2304. */
  2305. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2306. struct dp_tx_desc_s *desc)
  2307. {
  2308. struct dp_vdev *vdev = desc->vdev;
  2309. qdf_nbuf_t nbuf = desc->nbuf;
  2310. /* nbuf already freed in vdev detach path */
  2311. if (!nbuf)
  2312. return;
  2313. /* If it is TDLS mgmt, don't unmap or free the frame */
  2314. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2315. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2316. /* 0 : MSDU buffer, 1 : MLE */
  2317. if (desc->msdu_ext_desc) {
  2318. /* TSO free */
  2319. if (hal_tx_ext_desc_get_tso_enable(
  2320. desc->msdu_ext_desc->vaddr)) {
  2321. /* unmap eash TSO seg before free the nbuf */
  2322. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2323. desc->tso_num_desc);
  2324. qdf_nbuf_free(nbuf);
  2325. return;
  2326. }
  2327. }
  2328. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2329. if (qdf_unlikely(!vdev)) {
  2330. qdf_nbuf_free(nbuf);
  2331. return;
  2332. }
  2333. if (qdf_likely(!vdev->mesh_vdev))
  2334. qdf_nbuf_free(nbuf);
  2335. else {
  2336. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2337. qdf_nbuf_free(nbuf);
  2338. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2339. } else
  2340. vdev->osif_tx_free_ext((nbuf));
  2341. }
  2342. }
  2343. #ifdef MESH_MODE_SUPPORT
  2344. /**
  2345. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2346. * in mesh meta header
  2347. * @tx_desc: software descriptor head pointer
  2348. * @ts: pointer to tx completion stats
  2349. * Return: none
  2350. */
  2351. static
  2352. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2353. struct hal_tx_completion_status *ts)
  2354. {
  2355. struct meta_hdr_s *mhdr;
  2356. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2357. if (!tx_desc->msdu_ext_desc) {
  2358. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2359. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2360. "netbuf %pK offset %d",
  2361. netbuf, tx_desc->pkt_offset);
  2362. return;
  2363. }
  2364. }
  2365. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2366. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2367. "netbuf %pK offset %lu", netbuf,
  2368. sizeof(struct meta_hdr_s));
  2369. return;
  2370. }
  2371. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2372. mhdr->rssi = ts->ack_frame_rssi;
  2373. mhdr->channel = tx_desc->pdev->operating_channel;
  2374. }
  2375. #else
  2376. static
  2377. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2378. struct hal_tx_completion_status *ts)
  2379. {
  2380. }
  2381. #endif
  2382. /**
  2383. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2384. * to pass in correct fields
  2385. *
  2386. * @vdev: pdev handle
  2387. * @tx_desc: tx descriptor
  2388. * @tid: tid value
  2389. * @ring_id: TCL or WBM ring number for transmit path
  2390. * Return: none
  2391. */
  2392. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2393. struct dp_tx_desc_s *tx_desc,
  2394. uint8_t tid, uint8_t ring_id)
  2395. {
  2396. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2397. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2398. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2399. return;
  2400. current_timestamp = qdf_ktime_to_ms(qdf_ktime_get());
  2401. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2402. timestamp_hw_enqueue = tx_desc->timestamp;
  2403. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2404. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2405. timestamp_hw_enqueue);
  2406. interframe_delay = (uint32_t)(timestamp_ingress -
  2407. vdev->prev_tx_enq_tstamp);
  2408. /*
  2409. * Delay in software enqueue
  2410. */
  2411. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2412. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2413. /*
  2414. * Delay between packet enqueued to HW and Tx completion
  2415. */
  2416. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2417. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2418. /*
  2419. * Update interframe delay stats calculated at hardstart receive point.
  2420. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2421. * interframe delay will not be calculate correctly for 1st frame.
  2422. * On the other side, this will help in avoiding extra per packet check
  2423. * of !vdev->prev_tx_enq_tstamp.
  2424. */
  2425. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2426. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2427. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2428. }
  2429. /**
  2430. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2431. * per wbm ring
  2432. *
  2433. * @tx_desc: software descriptor head pointer
  2434. * @ts: Tx completion status
  2435. * @peer: peer handle
  2436. * @ring_id: ring number
  2437. *
  2438. * Return: None
  2439. */
  2440. static inline void
  2441. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2442. struct hal_tx_completion_status *ts,
  2443. struct dp_peer *peer, uint8_t ring_id)
  2444. {
  2445. struct dp_pdev *pdev = peer->vdev->pdev;
  2446. struct dp_soc *soc = NULL;
  2447. uint8_t mcs, pkt_type;
  2448. uint8_t tid = ts->tid;
  2449. uint32_t length;
  2450. struct cdp_tid_tx_stats *tid_stats;
  2451. if (!pdev)
  2452. return;
  2453. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2454. tid = CDP_MAX_DATA_TIDS - 1;
  2455. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2456. soc = pdev->soc;
  2457. mcs = ts->mcs;
  2458. pkt_type = ts->pkt_type;
  2459. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2460. dp_err("Release source is not from TQM");
  2461. return;
  2462. }
  2463. length = qdf_nbuf_len(tx_desc->nbuf);
  2464. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2465. if (qdf_unlikely(pdev->delay_stats_flag))
  2466. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2467. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2468. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2469. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2470. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2471. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2472. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2473. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2474. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2475. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2476. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2477. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2478. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2479. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2480. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2481. /*
  2482. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2483. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2484. * are no completions for failed cases. Hence updating tx_failed from
  2485. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2486. * then this has to be removed
  2487. */
  2488. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2489. peer->stats.tx.dropped.fw_rem_notx +
  2490. peer->stats.tx.dropped.fw_rem_tx +
  2491. peer->stats.tx.dropped.age_out +
  2492. peer->stats.tx.dropped.fw_reason1 +
  2493. peer->stats.tx.dropped.fw_reason2 +
  2494. peer->stats.tx.dropped.fw_reason3;
  2495. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2496. tid_stats->tqm_status_cnt[ts->status]++;
  2497. }
  2498. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2499. return;
  2500. }
  2501. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2502. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2503. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2504. /*
  2505. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2506. * Return from here if HTT PPDU events are enabled.
  2507. */
  2508. if (!(soc->process_tx_status))
  2509. return;
  2510. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2511. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2512. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2513. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2514. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2515. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2516. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2517. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2518. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2519. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2520. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2521. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2522. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2523. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2524. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2525. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2526. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2527. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2528. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2529. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2530. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2531. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2532. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2533. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2534. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2535. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2536. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2537. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2538. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2539. &peer->stats, ts->peer_id,
  2540. UPDATE_PEER_STATS, pdev->pdev_id);
  2541. #endif
  2542. }
  2543. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2544. /**
  2545. * dp_tx_flow_pool_lock() - take flow pool lock
  2546. * @soc: core txrx main context
  2547. * @tx_desc: tx desc
  2548. *
  2549. * Return: None
  2550. */
  2551. static inline
  2552. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2553. struct dp_tx_desc_s *tx_desc)
  2554. {
  2555. struct dp_tx_desc_pool_s *pool;
  2556. uint8_t desc_pool_id;
  2557. desc_pool_id = tx_desc->pool_id;
  2558. pool = &soc->tx_desc[desc_pool_id];
  2559. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2560. }
  2561. /**
  2562. * dp_tx_flow_pool_unlock() - release flow pool lock
  2563. * @soc: core txrx main context
  2564. * @tx_desc: tx desc
  2565. *
  2566. * Return: None
  2567. */
  2568. static inline
  2569. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2570. struct dp_tx_desc_s *tx_desc)
  2571. {
  2572. struct dp_tx_desc_pool_s *pool;
  2573. uint8_t desc_pool_id;
  2574. desc_pool_id = tx_desc->pool_id;
  2575. pool = &soc->tx_desc[desc_pool_id];
  2576. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2577. }
  2578. #else
  2579. static inline
  2580. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2581. {
  2582. }
  2583. static inline
  2584. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2585. {
  2586. }
  2587. #endif
  2588. /**
  2589. * dp_tx_notify_completion() - Notify tx completion for this desc
  2590. * @soc: core txrx main context
  2591. * @tx_desc: tx desc
  2592. * @netbuf: buffer
  2593. *
  2594. * Return: none
  2595. */
  2596. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2597. struct dp_tx_desc_s *tx_desc,
  2598. qdf_nbuf_t netbuf)
  2599. {
  2600. void *osif_dev;
  2601. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2602. qdf_assert(tx_desc);
  2603. dp_tx_flow_pool_lock(soc, tx_desc);
  2604. if (!tx_desc->vdev ||
  2605. !tx_desc->vdev->osif_vdev) {
  2606. dp_tx_flow_pool_unlock(soc, tx_desc);
  2607. return;
  2608. }
  2609. osif_dev = tx_desc->vdev->osif_vdev;
  2610. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2611. dp_tx_flow_pool_unlock(soc, tx_desc);
  2612. if (tx_compl_cbk)
  2613. tx_compl_cbk(netbuf, osif_dev);
  2614. }
  2615. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2616. * @pdev: pdev handle
  2617. * @tid: tid value
  2618. * @txdesc_ts: timestamp from txdesc
  2619. * @ppdu_id: ppdu id
  2620. *
  2621. * Return: none
  2622. */
  2623. #ifdef FEATURE_PERPKT_INFO
  2624. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2625. struct dp_peer *peer,
  2626. uint8_t tid,
  2627. uint64_t txdesc_ts,
  2628. uint32_t ppdu_id)
  2629. {
  2630. uint64_t delta_ms;
  2631. struct cdp_tx_sojourn_stats *sojourn_stats;
  2632. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2633. return;
  2634. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2635. tid >= CDP_DATA_TID_MAX))
  2636. return;
  2637. if (qdf_unlikely(!pdev->sojourn_buf))
  2638. return;
  2639. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2640. qdf_nbuf_data(pdev->sojourn_buf);
  2641. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2642. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2643. txdesc_ts;
  2644. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2645. delta_ms);
  2646. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2647. sojourn_stats->num_msdus[tid] = 1;
  2648. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2649. peer->avg_sojourn_msdu[tid].internal;
  2650. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2651. pdev->sojourn_buf, HTT_INVALID_PEER,
  2652. WDI_NO_VAL, pdev->pdev_id);
  2653. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2654. sojourn_stats->num_msdus[tid] = 0;
  2655. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2656. }
  2657. #else
  2658. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2659. uint8_t tid,
  2660. uint64_t txdesc_ts,
  2661. uint32_t ppdu_id)
  2662. {
  2663. }
  2664. #endif
  2665. /**
  2666. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2667. * @soc: DP Soc handle
  2668. * @tx_desc: software Tx descriptor
  2669. * @ts : Tx completion status from HAL/HTT descriptor
  2670. *
  2671. * Return: none
  2672. */
  2673. static inline void
  2674. dp_tx_comp_process_desc(struct dp_soc *soc,
  2675. struct dp_tx_desc_s *desc,
  2676. struct hal_tx_completion_status *ts,
  2677. struct dp_peer *peer)
  2678. {
  2679. uint64_t time_latency = 0;
  2680. /*
  2681. * m_copy/tx_capture modes are not supported for
  2682. * scatter gather packets
  2683. */
  2684. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  2685. time_latency = (qdf_ktime_to_ms(qdf_ktime_get()) -
  2686. desc->timestamp);
  2687. }
  2688. if (!(desc->msdu_ext_desc)) {
  2689. if (QDF_STATUS_SUCCESS ==
  2690. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  2691. return;
  2692. }
  2693. if (QDF_STATUS_SUCCESS ==
  2694. dp_get_completion_indication_for_stack(soc,
  2695. desc->pdev,
  2696. peer, ts,
  2697. desc->nbuf,
  2698. time_latency)) {
  2699. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2700. QDF_DMA_TO_DEVICE);
  2701. dp_send_completion_to_stack(soc,
  2702. desc->pdev,
  2703. ts->peer_id,
  2704. ts->ppdu_id,
  2705. desc->nbuf);
  2706. return;
  2707. }
  2708. }
  2709. dp_tx_comp_free_buf(soc, desc);
  2710. }
  2711. /**
  2712. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2713. * @tx_desc: software descriptor head pointer
  2714. * @ts: Tx completion status
  2715. * @peer: peer handle
  2716. * @ring_id: ring number
  2717. *
  2718. * Return: none
  2719. */
  2720. static inline
  2721. void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2722. struct hal_tx_completion_status *ts,
  2723. struct dp_peer *peer, uint8_t ring_id)
  2724. {
  2725. uint32_t length;
  2726. qdf_ether_header_t *eh;
  2727. struct dp_soc *soc = NULL;
  2728. struct dp_vdev *vdev = tx_desc->vdev;
  2729. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2730. if (!vdev || !nbuf) {
  2731. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2732. "invalid tx descriptor. vdev or nbuf NULL");
  2733. goto out;
  2734. }
  2735. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2736. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  2737. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2738. QDF_TRACE_DEFAULT_PDEV_ID,
  2739. qdf_nbuf_data_addr(nbuf),
  2740. sizeof(qdf_nbuf_data(nbuf)),
  2741. tx_desc->id,
  2742. ts->status));
  2743. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2744. "-------------------- \n"
  2745. "Tx Completion Stats: \n"
  2746. "-------------------- \n"
  2747. "ack_frame_rssi = %d \n"
  2748. "first_msdu = %d \n"
  2749. "last_msdu = %d \n"
  2750. "msdu_part_of_amsdu = %d \n"
  2751. "rate_stats valid = %d \n"
  2752. "bw = %d \n"
  2753. "pkt_type = %d \n"
  2754. "stbc = %d \n"
  2755. "ldpc = %d \n"
  2756. "sgi = %d \n"
  2757. "mcs = %d \n"
  2758. "ofdma = %d \n"
  2759. "tones_in_ru = %d \n"
  2760. "tsf = %d \n"
  2761. "ppdu_id = %d \n"
  2762. "transmit_cnt = %d \n"
  2763. "tid = %d \n"
  2764. "peer_id = %d\n",
  2765. ts->ack_frame_rssi, ts->first_msdu,
  2766. ts->last_msdu, ts->msdu_part_of_amsdu,
  2767. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  2768. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  2769. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  2770. ts->transmit_cnt, ts->tid, ts->peer_id);
  2771. soc = vdev->pdev->soc;
  2772. /* Update SoC level stats */
  2773. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2774. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2775. /* Update per-packet stats for mesh mode */
  2776. if (qdf_unlikely(vdev->mesh_vdev) &&
  2777. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2778. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  2779. length = qdf_nbuf_len(nbuf);
  2780. /* Update peer level stats */
  2781. if (!peer) {
  2782. QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_DP,
  2783. "peer is null or deletion in progress");
  2784. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2785. goto out;
  2786. }
  2787. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  2788. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  2789. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2790. if ((peer->vdev->tx_encap_type ==
  2791. htt_cmn_pkt_type_ethernet) &&
  2792. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  2793. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2794. }
  2795. }
  2796. } else {
  2797. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2798. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2799. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2800. }
  2801. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  2802. #ifdef QCA_SUPPORT_RDK_STATS
  2803. if (soc->wlanstats_enabled)
  2804. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  2805. tx_desc->timestamp,
  2806. ts->ppdu_id);
  2807. #endif
  2808. out:
  2809. return;
  2810. }
  2811. /**
  2812. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  2813. * @soc: core txrx main context
  2814. * @comp_head: software descriptor head pointer
  2815. * @ring_id: ring number
  2816. *
  2817. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2818. * and release the software descriptors after processing is complete
  2819. *
  2820. * Return: none
  2821. */
  2822. static void
  2823. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  2824. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  2825. {
  2826. struct dp_tx_desc_s *desc;
  2827. struct dp_tx_desc_s *next;
  2828. struct hal_tx_completion_status ts = {0};
  2829. struct dp_peer *peer;
  2830. qdf_nbuf_t netbuf;
  2831. desc = comp_head;
  2832. while (desc) {
  2833. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  2834. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2835. dp_tx_comp_process_tx_status(desc, &ts, peer, ring_id);
  2836. netbuf = desc->nbuf;
  2837. /* check tx complete notification */
  2838. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  2839. dp_tx_notify_completion(soc, desc, netbuf);
  2840. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  2841. if (peer)
  2842. dp_peer_unref_del_find_by_id(peer);
  2843. next = desc->next;
  2844. dp_tx_desc_release(desc, desc->pool_id);
  2845. desc = next;
  2846. }
  2847. }
  2848. /**
  2849. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2850. * @tx_desc: software descriptor head pointer
  2851. * @status : Tx completion status from HTT descriptor
  2852. * @ring_id: ring number
  2853. *
  2854. * This function will process HTT Tx indication messages from Target
  2855. *
  2856. * Return: none
  2857. */
  2858. static
  2859. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  2860. uint8_t ring_id)
  2861. {
  2862. uint8_t tx_status;
  2863. struct dp_pdev *pdev;
  2864. struct dp_vdev *vdev;
  2865. struct dp_soc *soc;
  2866. struct hal_tx_completion_status ts = {0};
  2867. uint32_t *htt_desc = (uint32_t *)status;
  2868. struct dp_peer *peer;
  2869. struct cdp_tid_tx_stats *tid_stats = NULL;
  2870. struct htt_soc *htt_handle;
  2871. qdf_assert(tx_desc->pdev);
  2872. pdev = tx_desc->pdev;
  2873. vdev = tx_desc->vdev;
  2874. soc = pdev->soc;
  2875. if (!vdev)
  2876. return;
  2877. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  2878. htt_handle = (struct htt_soc *)soc->htt_handle;
  2879. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  2880. switch (tx_status) {
  2881. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2882. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2883. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2884. {
  2885. uint8_t tid;
  2886. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  2887. ts.peer_id =
  2888. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  2889. htt_desc[2]);
  2890. ts.tid =
  2891. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  2892. htt_desc[2]);
  2893. } else {
  2894. ts.peer_id = HTT_INVALID_PEER;
  2895. ts.tid = HTT_INVALID_TID;
  2896. }
  2897. ts.ppdu_id =
  2898. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  2899. htt_desc[1]);
  2900. ts.ack_frame_rssi =
  2901. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  2902. htt_desc[1]);
  2903. ts.first_msdu = 1;
  2904. ts.last_msdu = 1;
  2905. tid = ts.tid;
  2906. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2907. tid = CDP_MAX_DATA_TIDS - 1;
  2908. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2909. if (qdf_unlikely(pdev->delay_stats_flag))
  2910. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  2911. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  2912. tid_stats->htt_status_cnt[tx_status]++;
  2913. }
  2914. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2915. if (qdf_likely(peer))
  2916. dp_peer_unref_del_find_by_id(peer);
  2917. dp_tx_comp_process_tx_status(tx_desc, &ts, peer, ring_id);
  2918. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  2919. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2920. break;
  2921. }
  2922. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2923. {
  2924. dp_tx_reinject_handler(tx_desc, status);
  2925. break;
  2926. }
  2927. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2928. {
  2929. dp_tx_inspect_handler(tx_desc, status);
  2930. break;
  2931. }
  2932. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2933. {
  2934. dp_tx_mec_handler(vdev, status);
  2935. break;
  2936. }
  2937. default:
  2938. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2939. "%s Invalid HTT tx_status %d\n",
  2940. __func__, tx_status);
  2941. break;
  2942. }
  2943. }
  2944. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  2945. static inline
  2946. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2947. {
  2948. bool limit_hit = false;
  2949. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  2950. limit_hit =
  2951. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  2952. if (limit_hit)
  2953. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  2954. return limit_hit;
  2955. }
  2956. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2957. {
  2958. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  2959. }
  2960. #else
  2961. static inline
  2962. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  2963. {
  2964. return false;
  2965. }
  2966. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  2967. {
  2968. return false;
  2969. }
  2970. #endif
  2971. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  2972. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  2973. uint32_t quota)
  2974. {
  2975. void *tx_comp_hal_desc;
  2976. uint8_t buffer_src;
  2977. uint8_t pool_id;
  2978. uint32_t tx_desc_id;
  2979. struct dp_tx_desc_s *tx_desc = NULL;
  2980. struct dp_tx_desc_s *head_desc = NULL;
  2981. struct dp_tx_desc_s *tail_desc = NULL;
  2982. uint32_t num_processed = 0;
  2983. uint32_t count = 0;
  2984. bool force_break = false;
  2985. DP_HIST_INIT();
  2986. more_data:
  2987. /* Re-initialize local variables to be re-used */
  2988. head_desc = NULL;
  2989. tail_desc = NULL;
  2990. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  2991. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2992. "%s %d : HAL RING Access Failed -- %pK",
  2993. __func__, __LINE__, hal_ring_hdl);
  2994. return 0;
  2995. }
  2996. /* Find head descriptor from completion ring */
  2997. while (qdf_likely(tx_comp_hal_desc =
  2998. hal_srng_dst_get_next(soc->hal_soc, hal_ring_hdl))) {
  2999. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3000. /* If this buffer was not released by TQM or FW, then it is not
  3001. * Tx completion indication, assert */
  3002. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3003. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3004. uint8_t wbm_internal_error;
  3005. QDF_TRACE(QDF_MODULE_ID_DP,
  3006. QDF_TRACE_LEVEL_FATAL,
  3007. "Tx comp release_src != TQM | FW but from %d",
  3008. buffer_src);
  3009. hal_dump_comp_desc(tx_comp_hal_desc);
  3010. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3011. /* When WBM sees NULL buffer_addr_info in any of
  3012. * ingress rings it sends an error indication,
  3013. * with wbm_internal_error=1, to a specific ring.
  3014. * The WBM2SW ring used to indicate these errors is
  3015. * fixed in HW, and that ring is being used as Tx
  3016. * completion ring. These errors are not related to
  3017. * Tx completions, and should just be ignored
  3018. */
  3019. wbm_internal_error =
  3020. hal_get_wbm_internal_error(tx_comp_hal_desc);
  3021. if (wbm_internal_error) {
  3022. QDF_TRACE(QDF_MODULE_ID_DP,
  3023. QDF_TRACE_LEVEL_ERROR,
  3024. "Tx comp wbm_internal_error!!!\n");
  3025. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3026. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3027. buffer_src)
  3028. dp_handle_wbm_internal_error(
  3029. soc,
  3030. tx_comp_hal_desc,
  3031. hal_tx_comp_get_buffer_type(
  3032. tx_comp_hal_desc));
  3033. continue;
  3034. } else {
  3035. qdf_assert_always(0);
  3036. }
  3037. }
  3038. /* Get descriptor id */
  3039. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3040. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3041. DP_TX_DESC_ID_POOL_OS;
  3042. /* Find Tx descriptor */
  3043. tx_desc = dp_tx_desc_find(soc, pool_id,
  3044. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3045. DP_TX_DESC_ID_PAGE_OS,
  3046. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3047. DP_TX_DESC_ID_OFFSET_OS);
  3048. /*
  3049. * If the descriptor is already freed in vdev_detach,
  3050. * continue to next descriptor
  3051. */
  3052. if (!tx_desc->vdev && !tx_desc->flags) {
  3053. QDF_TRACE(QDF_MODULE_ID_DP,
  3054. QDF_TRACE_LEVEL_INFO,
  3055. "Descriptor freed in vdev_detach %d",
  3056. tx_desc_id);
  3057. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3058. count++;
  3059. continue;
  3060. }
  3061. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3062. QDF_TRACE(QDF_MODULE_ID_DP,
  3063. QDF_TRACE_LEVEL_INFO,
  3064. "pdev in down state %d",
  3065. tx_desc_id);
  3066. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3067. count++;
  3068. dp_tx_comp_free_buf(soc, tx_desc);
  3069. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3070. continue;
  3071. }
  3072. /*
  3073. * If the release source is FW, process the HTT status
  3074. */
  3075. if (qdf_unlikely(buffer_src ==
  3076. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3077. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3078. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3079. htt_tx_status);
  3080. dp_tx_process_htt_completion(tx_desc,
  3081. htt_tx_status, ring_id);
  3082. } else {
  3083. /* Pool id is not matching. Error */
  3084. if (tx_desc->pool_id != pool_id) {
  3085. QDF_TRACE(QDF_MODULE_ID_DP,
  3086. QDF_TRACE_LEVEL_FATAL,
  3087. "Tx Comp pool id %d not matched %d",
  3088. pool_id, tx_desc->pool_id);
  3089. qdf_assert_always(0);
  3090. }
  3091. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3092. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3093. QDF_TRACE(QDF_MODULE_ID_DP,
  3094. QDF_TRACE_LEVEL_FATAL,
  3095. "Txdesc invalid, flgs = %x,id = %d",
  3096. tx_desc->flags, tx_desc_id);
  3097. qdf_assert_always(0);
  3098. }
  3099. /* First ring descriptor on the cycle */
  3100. if (!head_desc) {
  3101. head_desc = tx_desc;
  3102. tail_desc = tx_desc;
  3103. }
  3104. tail_desc->next = tx_desc;
  3105. tx_desc->next = NULL;
  3106. tail_desc = tx_desc;
  3107. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3108. /* Collect hw completion contents */
  3109. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3110. &tx_desc->comp, 1);
  3111. }
  3112. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3113. /*
  3114. * Processed packet count is more than given quota
  3115. * stop to processing
  3116. */
  3117. if (num_processed >= quota) {
  3118. force_break = true;
  3119. break;
  3120. }
  3121. count++;
  3122. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3123. break;
  3124. }
  3125. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3126. /* Process the reaped descriptors */
  3127. if (head_desc)
  3128. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3129. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3130. if (!force_break &&
  3131. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3132. hal_ring_hdl)) {
  3133. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3134. if (!hif_exec_should_yield(soc->hif_handle,
  3135. int_ctx->dp_intr_id))
  3136. goto more_data;
  3137. }
  3138. }
  3139. DP_TX_HIST_STATS_PER_PDEV();
  3140. return num_processed;
  3141. }
  3142. #ifdef FEATURE_WLAN_TDLS
  3143. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3144. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3145. {
  3146. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3147. struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
  3148. if (!vdev) {
  3149. dp_err("vdev handle for id %d is NULL", vdev_id);
  3150. return NULL;
  3151. }
  3152. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3153. vdev->is_tdls_frame = true;
  3154. return dp_tx_send(dp_vdev_to_cdp_vdev(vdev), msdu_list);
  3155. }
  3156. #endif
  3157. /**
  3158. * dp_tx_vdev_attach() - attach vdev to dp tx
  3159. * @vdev: virtual device instance
  3160. *
  3161. * Return: QDF_STATUS_SUCCESS: success
  3162. * QDF_STATUS_E_RESOURCES: Error return
  3163. */
  3164. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3165. {
  3166. /*
  3167. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3168. */
  3169. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3170. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3171. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3172. vdev->vdev_id);
  3173. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  3174. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  3175. /*
  3176. * Set HTT Extension Valid bit to 0 by default
  3177. */
  3178. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3179. dp_tx_vdev_update_search_flags(vdev);
  3180. return QDF_STATUS_SUCCESS;
  3181. }
  3182. #ifndef FEATURE_WDS
  3183. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3184. {
  3185. return false;
  3186. }
  3187. #endif
  3188. /**
  3189. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3190. * @vdev: virtual device instance
  3191. *
  3192. * Return: void
  3193. *
  3194. */
  3195. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3196. {
  3197. struct dp_soc *soc = vdev->pdev->soc;
  3198. /*
  3199. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3200. * for TDLS link
  3201. *
  3202. * Enable AddrY (SA based search) only for non-WDS STA and
  3203. * ProxySTA VAP (in HKv1) modes.
  3204. *
  3205. * In all other VAP modes, only DA based search should be
  3206. * enabled
  3207. */
  3208. if (vdev->opmode == wlan_op_mode_sta &&
  3209. vdev->tdls_link_connected)
  3210. vdev->hal_desc_addr_search_flags =
  3211. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3212. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3213. !dp_tx_da_search_override(vdev))
  3214. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3215. else
  3216. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3217. /* Set search type only when peer map v2 messaging is enabled
  3218. * as we will have the search index (AST hash) only when v2 is
  3219. * enabled
  3220. */
  3221. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3222. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3223. else
  3224. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3225. }
  3226. static inline bool
  3227. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3228. struct dp_vdev *vdev,
  3229. struct dp_tx_desc_s *tx_desc)
  3230. {
  3231. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3232. return false;
  3233. /*
  3234. * if vdev is given, then only check whether desc
  3235. * vdev match. if vdev is NULL, then check whether
  3236. * desc pdev match.
  3237. */
  3238. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3239. }
  3240. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3241. /**
  3242. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3243. *
  3244. * @soc: Handle to DP SoC structure
  3245. * @tx_desc: pointer of one TX desc
  3246. * @desc_pool_id: TX Desc pool id
  3247. */
  3248. static inline void
  3249. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3250. uint8_t desc_pool_id)
  3251. {
  3252. struct dp_tx_desc_pool_s *pool = &soc->tx_desc[desc_pool_id];
  3253. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3254. tx_desc->vdev = NULL;
  3255. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3256. }
  3257. /**
  3258. * dp_tx_desc_flush() - release resources associated
  3259. * to TX Desc
  3260. *
  3261. * @dp_pdev: Handle to DP pdev structure
  3262. * @vdev: virtual device instance
  3263. * NULL: no specific Vdev is required and check all allcated TX desc
  3264. * on this pdev.
  3265. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3266. *
  3267. * @force_free:
  3268. * true: flush the TX desc.
  3269. * false: only reset the Vdev in each allocated TX desc
  3270. * that associated to current Vdev.
  3271. *
  3272. * This function will go through the TX desc pool to flush
  3273. * the outstanding TX data or reset Vdev to NULL in associated TX
  3274. * Desc.
  3275. */
  3276. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3277. struct dp_vdev *vdev,
  3278. bool force_free)
  3279. {
  3280. uint8_t i;
  3281. uint32_t j;
  3282. uint32_t num_desc, page_id, offset;
  3283. uint16_t num_desc_per_page;
  3284. struct dp_soc *soc = pdev->soc;
  3285. struct dp_tx_desc_s *tx_desc = NULL;
  3286. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3287. if (!vdev && !force_free) {
  3288. dp_err("Reset TX desc vdev, Vdev param is required!");
  3289. return;
  3290. }
  3291. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3292. tx_desc_pool = &soc->tx_desc[i];
  3293. if (!(tx_desc_pool->pool_size) ||
  3294. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3295. !(tx_desc_pool->desc_pages.cacheable_pages))
  3296. continue;
  3297. num_desc = tx_desc_pool->pool_size;
  3298. num_desc_per_page =
  3299. tx_desc_pool->desc_pages.num_element_per_page;
  3300. for (j = 0; j < num_desc; j++) {
  3301. page_id = j / num_desc_per_page;
  3302. offset = j % num_desc_per_page;
  3303. if (qdf_unlikely(!(tx_desc_pool->
  3304. desc_pages.cacheable_pages)))
  3305. break;
  3306. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3307. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3308. /*
  3309. * Free TX desc if force free is
  3310. * required, otherwise only reset vdev
  3311. * in this TX desc.
  3312. */
  3313. if (force_free) {
  3314. dp_tx_comp_free_buf(soc, tx_desc);
  3315. dp_tx_desc_release(tx_desc, i);
  3316. } else {
  3317. dp_tx_desc_reset_vdev(soc, tx_desc,
  3318. i);
  3319. }
  3320. }
  3321. }
  3322. }
  3323. }
  3324. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3325. static inline void
  3326. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3327. uint8_t desc_pool_id)
  3328. {
  3329. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3330. tx_desc->vdev = NULL;
  3331. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3332. }
  3333. static void dp_tx_desc_flush(struct dp_pdev *pdev,
  3334. struct dp_vdev *vdev,
  3335. bool force_free)
  3336. {
  3337. uint8_t i, num_pool;
  3338. uint32_t j;
  3339. uint32_t num_desc, page_id, offset;
  3340. uint16_t num_desc_per_page;
  3341. struct dp_soc *soc = pdev->soc;
  3342. struct dp_tx_desc_s *tx_desc = NULL;
  3343. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3344. if (!vdev && !force_free) {
  3345. dp_err("Reset TX desc vdev, Vdev param is required!");
  3346. return;
  3347. }
  3348. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3349. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3350. for (i = 0; i < num_pool; i++) {
  3351. tx_desc_pool = &soc->tx_desc[i];
  3352. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3353. continue;
  3354. num_desc_per_page =
  3355. tx_desc_pool->desc_pages.num_element_per_page;
  3356. for (j = 0; j < num_desc; j++) {
  3357. page_id = j / num_desc_per_page;
  3358. offset = j % num_desc_per_page;
  3359. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3360. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3361. if (force_free) {
  3362. dp_tx_comp_free_buf(soc, tx_desc);
  3363. dp_tx_desc_release(tx_desc, i);
  3364. } else {
  3365. dp_tx_desc_reset_vdev(soc, tx_desc,
  3366. i);
  3367. }
  3368. }
  3369. }
  3370. }
  3371. }
  3372. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3373. /**
  3374. * dp_tx_vdev_detach() - detach vdev from dp tx
  3375. * @vdev: virtual device instance
  3376. *
  3377. * Return: QDF_STATUS_SUCCESS: success
  3378. * QDF_STATUS_E_RESOURCES: Error return
  3379. */
  3380. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3381. {
  3382. struct dp_pdev *pdev = vdev->pdev;
  3383. /* Reset TX desc associated to this Vdev as NULL */
  3384. dp_tx_desc_flush(pdev, vdev, false);
  3385. dp_tx_vdev_multipass_deinit(vdev);
  3386. return QDF_STATUS_SUCCESS;
  3387. }
  3388. /**
  3389. * dp_tx_pdev_attach() - attach pdev to dp tx
  3390. * @pdev: physical device instance
  3391. *
  3392. * Return: QDF_STATUS_SUCCESS: success
  3393. * QDF_STATUS_E_RESOURCES: Error return
  3394. */
  3395. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  3396. {
  3397. struct dp_soc *soc = pdev->soc;
  3398. /* Initialize Flow control counters */
  3399. qdf_atomic_init(&pdev->num_tx_exception);
  3400. qdf_atomic_init(&pdev->num_tx_outstanding);
  3401. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3402. /* Initialize descriptors in TCL Ring */
  3403. hal_tx_init_data_ring(soc->hal_soc,
  3404. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3405. }
  3406. return QDF_STATUS_SUCCESS;
  3407. }
  3408. /**
  3409. * dp_tx_pdev_detach() - detach pdev from dp tx
  3410. * @pdev: physical device instance
  3411. *
  3412. * Return: QDF_STATUS_SUCCESS: success
  3413. * QDF_STATUS_E_RESOURCES: Error return
  3414. */
  3415. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3416. {
  3417. /* flush TX outstanding data per pdev */
  3418. dp_tx_desc_flush(pdev, NULL, true);
  3419. dp_tx_me_exit(pdev);
  3420. return QDF_STATUS_SUCCESS;
  3421. }
  3422. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3423. /* Pools will be allocated dynamically */
  3424. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3425. int num_desc)
  3426. {
  3427. uint8_t i;
  3428. for (i = 0; i < num_pool; i++) {
  3429. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3430. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3431. }
  3432. return 0;
  3433. }
  3434. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3435. {
  3436. uint8_t i;
  3437. for (i = 0; i < num_pool; i++)
  3438. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3439. }
  3440. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3441. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3442. int num_desc)
  3443. {
  3444. uint8_t i;
  3445. /* Allocate software Tx descriptor pools */
  3446. for (i = 0; i < num_pool; i++) {
  3447. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3448. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3449. "%s Tx Desc Pool alloc %d failed %pK",
  3450. __func__, i, soc);
  3451. return ENOMEM;
  3452. }
  3453. }
  3454. return 0;
  3455. }
  3456. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3457. {
  3458. uint8_t i;
  3459. for (i = 0; i < num_pool; i++) {
  3460. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  3461. if (dp_tx_desc_pool_free(soc, i)) {
  3462. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3463. "%s Tx Desc Pool Free failed", __func__);
  3464. }
  3465. }
  3466. }
  3467. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3468. #ifndef QCA_MEM_ATTACH_ON_WIFI3
  3469. /**
  3470. * dp_tso_attach_wifi3() - TSO attach handler
  3471. * @txrx_soc: Opaque Dp handle
  3472. *
  3473. * Reserve TSO descriptor buffers
  3474. *
  3475. * Return: QDF_STATUS_E_FAILURE on failure or
  3476. * QDF_STATUS_SUCCESS on success
  3477. */
  3478. static
  3479. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3480. {
  3481. return dp_tso_soc_attach(txrx_soc);
  3482. }
  3483. /**
  3484. * dp_tso_detach_wifi3() - TSO Detach handler
  3485. * @txrx_soc: Opaque Dp handle
  3486. *
  3487. * Deallocate TSO descriptor buffers
  3488. *
  3489. * Return: QDF_STATUS_E_FAILURE on failure or
  3490. * QDF_STATUS_SUCCESS on success
  3491. */
  3492. static
  3493. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3494. {
  3495. return dp_tso_soc_detach(txrx_soc);
  3496. }
  3497. #else
  3498. static
  3499. QDF_STATUS dp_tso_attach_wifi3(void *txrx_soc)
  3500. {
  3501. return QDF_STATUS_SUCCESS;
  3502. }
  3503. static
  3504. QDF_STATUS dp_tso_detach_wifi3(void *txrx_soc)
  3505. {
  3506. return QDF_STATUS_SUCCESS;
  3507. }
  3508. #endif
  3509. QDF_STATUS dp_tso_soc_detach(void *txrx_soc)
  3510. {
  3511. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3512. uint8_t i;
  3513. uint8_t num_pool;
  3514. uint32_t num_desc;
  3515. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3516. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3517. for (i = 0; i < num_pool; i++)
  3518. dp_tx_tso_desc_pool_free(soc, i);
  3519. dp_info("%s TSO Desc Pool %d Free descs = %d",
  3520. __func__, num_pool, num_desc);
  3521. for (i = 0; i < num_pool; i++)
  3522. dp_tx_tso_num_seg_pool_free(soc, i);
  3523. dp_info("%s TSO Num of seg Desc Pool %d Free descs = %d",
  3524. __func__, num_pool, num_desc);
  3525. return QDF_STATUS_SUCCESS;
  3526. }
  3527. /**
  3528. * dp_tso_attach() - TSO attach handler
  3529. * @txrx_soc: Opaque Dp handle
  3530. *
  3531. * Reserve TSO descriptor buffers
  3532. *
  3533. * Return: QDF_STATUS_E_FAILURE on failure or
  3534. * QDF_STATUS_SUCCESS on success
  3535. */
  3536. QDF_STATUS dp_tso_soc_attach(void *txrx_soc)
  3537. {
  3538. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3539. uint8_t i;
  3540. uint8_t num_pool;
  3541. uint32_t num_desc;
  3542. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3543. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3544. for (i = 0; i < num_pool; i++) {
  3545. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  3546. dp_err("TSO Desc Pool alloc %d failed %pK",
  3547. i, soc);
  3548. return QDF_STATUS_E_FAILURE;
  3549. }
  3550. }
  3551. dp_info("%s TSO Desc Alloc %d, descs = %d",
  3552. __func__, num_pool, num_desc);
  3553. for (i = 0; i < num_pool; i++) {
  3554. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  3555. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  3556. i, soc);
  3557. return QDF_STATUS_E_FAILURE;
  3558. }
  3559. }
  3560. return QDF_STATUS_SUCCESS;
  3561. }
  3562. /**
  3563. * dp_tx_soc_detach() - detach soc from dp tx
  3564. * @soc: core txrx main context
  3565. *
  3566. * This function will detach dp tx into main device context
  3567. * will free dp tx resource and initialize resources
  3568. *
  3569. * Return: QDF_STATUS_SUCCESS: success
  3570. * QDF_STATUS_E_RESOURCES: Error return
  3571. */
  3572. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  3573. {
  3574. uint8_t num_pool;
  3575. uint16_t num_desc;
  3576. uint16_t num_ext_desc;
  3577. uint8_t i;
  3578. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3579. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3580. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3581. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3582. dp_tx_flow_control_deinit(soc);
  3583. dp_tx_delete_static_pools(soc, num_pool);
  3584. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3585. "%s Tx Desc Pool Free num_pool = %d, descs = %d",
  3586. __func__, num_pool, num_desc);
  3587. for (i = 0; i < num_pool; i++) {
  3588. if (dp_tx_ext_desc_pool_free(soc, i)) {
  3589. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3590. "%s Tx Ext Desc Pool Free failed",
  3591. __func__);
  3592. return QDF_STATUS_E_RESOURCES;
  3593. }
  3594. }
  3595. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3596. "%s MSDU Ext Desc Pool %d Free descs = %d",
  3597. __func__, num_pool, num_ext_desc);
  3598. status = dp_tso_detach_wifi3(soc);
  3599. if (status != QDF_STATUS_SUCCESS)
  3600. return status;
  3601. return QDF_STATUS_SUCCESS;
  3602. }
  3603. /**
  3604. * dp_tx_soc_attach() - attach soc to dp tx
  3605. * @soc: core txrx main context
  3606. *
  3607. * This function will attach dp tx into main device context
  3608. * will allocate dp tx resource and initialize resources
  3609. *
  3610. * Return: QDF_STATUS_SUCCESS: success
  3611. * QDF_STATUS_E_RESOURCES: Error return
  3612. */
  3613. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  3614. {
  3615. uint8_t i;
  3616. uint8_t num_pool;
  3617. uint32_t num_desc;
  3618. uint32_t num_ext_desc;
  3619. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3620. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3621. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3622. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  3623. if (num_pool > MAX_TXDESC_POOLS)
  3624. goto fail;
  3625. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  3626. goto fail;
  3627. dp_tx_flow_control_init(soc);
  3628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3629. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  3630. __func__, num_pool, num_desc);
  3631. /* Allocate extension tx descriptor pools */
  3632. for (i = 0; i < num_pool; i++) {
  3633. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  3634. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3635. "MSDU Ext Desc Pool alloc %d failed %pK",
  3636. i, soc);
  3637. goto fail;
  3638. }
  3639. }
  3640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3641. "%s MSDU Ext Desc Alloc %d, descs = %d",
  3642. __func__, num_pool, num_ext_desc);
  3643. status = dp_tso_attach_wifi3((void *)soc);
  3644. if (status != QDF_STATUS_SUCCESS)
  3645. goto fail;
  3646. /* Initialize descriptors in TCL Rings */
  3647. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3648. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3649. hal_tx_init_data_ring(soc->hal_soc,
  3650. soc->tcl_data_ring[i].hal_srng);
  3651. }
  3652. }
  3653. /*
  3654. * todo - Add a runtime config option to enable this.
  3655. */
  3656. /*
  3657. * Due to multiple issues on NPR EMU, enable it selectively
  3658. * only for NPR EMU, should be removed, once NPR platforms
  3659. * are stable.
  3660. */
  3661. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  3662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3663. "%s HAL Tx init Success", __func__);
  3664. return QDF_STATUS_SUCCESS;
  3665. fail:
  3666. /* Detach will take care of freeing only allocated resources */
  3667. dp_tx_soc_detach(soc);
  3668. return QDF_STATUS_E_RESOURCES;
  3669. }