qcs405.c 212 KB

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  1. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/input.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_qos.h>
  23. #include <sound/core.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/info.h>
  29. #include <dsp/audio_notifier.h>
  30. #include <dsp/q6afe-v2.h>
  31. #include <dsp/q6core.h>
  32. #include "device_event.h"
  33. #include "msm-pcm-routing-v2.h"
  34. #include "codecs/msm-cdc-pinctrl.h"
  35. #include "codecs/wcd9335.h"
  36. #include "codecs/wsa881x.h"
  37. #include "codecs/csra66x0/csra66x0.h"
  38. #include <dt-bindings/sound/audio-codec-port-types.h>
  39. #include "codecs/bolero/bolero-cdc.h"
  40. #include "codecs/bolero/wsa-macro.h"
  41. #define DRV_NAME "qcs405-asoc-snd"
  42. #define __CHIPSET__ "QCS405 "
  43. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  44. #define DEV_NAME_STR_LEN 32
  45. #define SAMPLING_RATE_8KHZ 8000
  46. #define SAMPLING_RATE_11P025KHZ 11025
  47. #define SAMPLING_RATE_16KHZ 16000
  48. #define SAMPLING_RATE_22P05KHZ 22050
  49. #define SAMPLING_RATE_32KHZ 32000
  50. #define SAMPLING_RATE_44P1KHZ 44100
  51. #define SAMPLING_RATE_48KHZ 48000
  52. #define SAMPLING_RATE_88P2KHZ 88200
  53. #define SAMPLING_RATE_96KHZ 96000
  54. #define SAMPLING_RATE_176P4KHZ 176400
  55. #define SAMPLING_RATE_192KHZ 192000
  56. #define SAMPLING_RATE_352P8KHZ 352800
  57. #define SAMPLING_RATE_384KHZ 384000
  58. #define WSA8810_NAME_1 "wsa881x.20170211"
  59. #define WSA8810_NAME_2 "wsa881x.20170212"
  60. #define WCN_CDC_SLIM_RX_CH_MAX 2
  61. #define WCN_CDC_SLIM_TX_CH_MAX 3
  62. #define TDM_CHANNEL_MAX 8
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  65. enum {
  66. SLIM_RX_0 = 0,
  67. SLIM_RX_1,
  68. SLIM_RX_2,
  69. SLIM_RX_3,
  70. SLIM_RX_4,
  71. SLIM_RX_5,
  72. SLIM_RX_6,
  73. SLIM_RX_7,
  74. SLIM_RX_MAX,
  75. };
  76. enum {
  77. SLIM_TX_0 = 0,
  78. SLIM_TX_1,
  79. SLIM_TX_2,
  80. SLIM_TX_3,
  81. SLIM_TX_4,
  82. SLIM_TX_5,
  83. SLIM_TX_6,
  84. SLIM_TX_7,
  85. SLIM_TX_8,
  86. SLIM_TX_MAX,
  87. };
  88. enum {
  89. PRIM_MI2S = 0,
  90. SEC_MI2S,
  91. TERT_MI2S,
  92. QUAT_MI2S,
  93. QUIN_MI2S,
  94. MI2S_MAX,
  95. };
  96. enum {
  97. PRIM_AUX_PCM = 0,
  98. SEC_AUX_PCM,
  99. TERT_AUX_PCM,
  100. QUAT_AUX_PCM,
  101. QUIN_AUX_PCM,
  102. AUX_PCM_MAX,
  103. };
  104. enum {
  105. WSA_CDC_DMA_RX_0 = 0,
  106. WSA_CDC_DMA_RX_1,
  107. CDC_DMA_RX_MAX,
  108. };
  109. enum {
  110. WSA_CDC_DMA_TX_0 = 0,
  111. WSA_CDC_DMA_TX_1,
  112. WSA_CDC_DMA_TX_2,
  113. VA_CDC_DMA_TX_0,
  114. VA_CDC_DMA_TX_1,
  115. CDC_DMA_TX_MAX,
  116. };
  117. struct mi2s_conf {
  118. struct mutex lock;
  119. u32 ref_cnt;
  120. u32 msm_is_mi2s_master;
  121. };
  122. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  123. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  124. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  125. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  126. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  127. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
  128. };
  129. struct dev_config {
  130. u32 sample_rate;
  131. u32 bit_format;
  132. u32 channels;
  133. };
  134. struct msm_wsa881x_dev_info {
  135. struct device_node *of_node;
  136. u32 index;
  137. };
  138. struct msm_csra66x0_dev_info {
  139. struct device_node *of_node;
  140. u32 index;
  141. };
  142. enum pinctrl_pin_state {
  143. STATE_DISABLE = 0, /* All pins are in sleep state */
  144. STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
  145. STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
  146. };
  147. struct msm_pinctrl_info {
  148. struct pinctrl *pinctrl;
  149. struct pinctrl_state *mi2s_disable;
  150. struct pinctrl_state *tdm_disable;
  151. struct pinctrl_state *mi2s_active;
  152. struct pinctrl_state *tdm_active;
  153. enum pinctrl_pin_state curr_state;
  154. };
  155. struct msm_asoc_mach_data {
  156. struct snd_info_entry *codec_root;
  157. struct msm_pinctrl_info pinctrl_info;
  158. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  159. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  160. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  161. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  162. int dmic_01_gpio_cnt;
  163. int dmic_23_gpio_cnt;
  164. int dmic_45_gpio_cnt;
  165. int dmic_67_gpio_cnt;
  166. };
  167. struct msm_asoc_wcd93xx_codec {
  168. void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
  169. enum afe_config_type config_type);
  170. };
  171. static const char *const pin_states[] = {"sleep", "i2s-active",
  172. "tdm-active"};
  173. enum {
  174. TDM_0 = 0,
  175. TDM_1,
  176. TDM_2,
  177. TDM_3,
  178. TDM_4,
  179. TDM_5,
  180. TDM_6,
  181. TDM_7,
  182. TDM_PORT_MAX,
  183. };
  184. enum {
  185. TDM_PRI = 0,
  186. TDM_SEC,
  187. TDM_TERT,
  188. TDM_QUAT,
  189. TDM_QUIN,
  190. TDM_INTERFACE_MAX,
  191. };
  192. struct tdm_port {
  193. u32 mode;
  194. u32 channel;
  195. };
  196. /* TDM default config */
  197. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  198. { /* PRI TDM */
  199. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  200. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  201. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  202. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  203. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  204. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  205. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  206. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  207. },
  208. { /* SEC TDM */
  209. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  210. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  211. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  212. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  213. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  214. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  215. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  216. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  217. },
  218. { /* TERT TDM */
  219. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  220. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  227. },
  228. { /* QUAT TDM */
  229. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  230. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  237. },
  238. { /* QUIN TDM */
  239. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  240. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  247. }
  248. };
  249. /* TDM default config */
  250. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  251. { /* PRI TDM */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  259. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  260. },
  261. { /* SEC TDM */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  270. },
  271. { /* TERT TDM */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  280. },
  281. { /* QUAT TDM */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  290. },
  291. { /* QUIN TDM */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  300. }
  301. };
  302. /* Default configuration of slimbus channels */
  303. static struct dev_config slim_rx_cfg[] = {
  304. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  305. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  306. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  307. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  308. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  309. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  310. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  311. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  312. };
  313. static struct dev_config slim_tx_cfg[] = {
  314. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  315. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  316. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  317. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  318. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  319. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  320. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  321. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  322. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  323. };
  324. /* Default configuration of Codec DMA Interface Tx */
  325. static struct dev_config cdc_dma_rx_cfg[] = {
  326. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  327. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  328. };
  329. /* Default configuration of Codec DMA Interface Rx */
  330. static struct dev_config cdc_dma_tx_cfg[] = {
  331. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  332. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  333. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  334. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  335. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  336. };
  337. static struct dev_config usb_rx_cfg = {
  338. .sample_rate = SAMPLING_RATE_48KHZ,
  339. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  340. .channels = 2,
  341. };
  342. static struct dev_config usb_tx_cfg = {
  343. .sample_rate = SAMPLING_RATE_48KHZ,
  344. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  345. .channels = 1,
  346. };
  347. static struct dev_config proxy_rx_cfg = {
  348. .sample_rate = SAMPLING_RATE_48KHZ,
  349. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  350. .channels = 2,
  351. };
  352. /* Default configuration of MI2S channels */
  353. static struct dev_config mi2s_rx_cfg[] = {
  354. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  355. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  356. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  357. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  358. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  359. };
  360. static struct dev_config mi2s_tx_cfg[] = {
  361. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  362. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  363. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  364. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  365. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  366. };
  367. static struct dev_config aux_pcm_rx_cfg[] = {
  368. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  369. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  370. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  371. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  372. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  373. };
  374. static struct dev_config aux_pcm_tx_cfg[] = {
  375. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  376. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  377. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  378. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  379. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  380. };
  381. static int msm_vi_feed_tx_ch = 2;
  382. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  383. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  384. "Five", "Six", "Seven",
  385. "Eight"};
  386. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  387. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  388. "S32_LE"};
  389. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  390. "KHZ_32", "KHZ_44P1", "KHZ_48",
  391. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  392. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  393. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  394. "KHZ_44P1", "KHZ_48",
  395. "KHZ_88P2", "KHZ_96"};
  396. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  397. "Five", "Six", "Seven",
  398. "Eight"};
  399. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  400. "Six", "Seven", "Eight"};
  401. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  402. "KHZ_16", "KHZ_22P05",
  403. "KHZ_32", "KHZ_44P1", "KHZ_48",
  404. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  405. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  406. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  407. "Five", "Six", "Seven", "Eight"};
  408. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  409. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  410. "KHZ_48", "KHZ_176P4",
  411. "KHZ_352P8"};
  412. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  413. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  414. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  415. "KHZ_48", "KHZ_96", "KHZ_192"};
  416. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  417. "Five", "Six", "Seven",
  418. "Eight"};
  419. static const char *const qos_text[] = {"Disable", "Enable"};
  420. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  421. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  422. "Five", "Six", "Seven",
  423. "Eight"};
  424. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  425. "KHZ_16", "KHZ_22P05",
  426. "KHZ_32", "KHZ_44P1", "KHZ_48",
  427. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  428. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  429. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  430. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  431. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  432. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  433. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  434. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  435. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  436. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  437. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  438. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  439. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  440. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  441. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  442. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  443. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  444. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  445. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  446. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  447. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  448. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  449. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  450. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  451. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  452. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  453. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  454. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  455. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  456. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  457. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  458. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  459. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  460. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  461. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  462. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  463. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  464. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  465. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  466. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  467. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  468. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  469. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  470. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  471. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  472. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  473. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  474. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  475. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  476. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  477. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  478. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  479. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  480. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  481. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  482. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  483. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  484. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  485. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  486. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  487. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  488. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  489. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  490. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  491. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  492. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  493. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  494. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  495. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  496. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  497. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  498. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  499. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  500. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  501. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  502. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  507. cdc_dma_sample_rate_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  509. cdc_dma_sample_rate_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  511. cdc_dma_sample_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  513. cdc_dma_sample_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  515. cdc_dma_sample_rate_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  517. cdc_dma_sample_rate_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  519. cdc_dma_sample_rate_text);
  520. static struct platform_device *spdev;
  521. static bool is_initial_boot;
  522. static bool codec_reg_done;
  523. static struct snd_soc_aux_dev *msm_aux_dev;
  524. static struct snd_soc_codec_conf *msm_codec_conf;
  525. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  526. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  527. int enable, bool dapm);
  528. static int msm_wsa881x_init(struct snd_soc_component *component);
  529. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  530. struct snd_ctl_elem_value *ucontrol);
  531. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  532. {"MIC BIAS1", NULL, "MCLK TX"},
  533. {"MIC BIAS2", NULL, "MCLK TX"},
  534. {"MIC BIAS3", NULL, "MCLK TX"},
  535. {"MIC BIAS4", NULL, "MCLK TX"},
  536. };
  537. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  538. {
  539. AFE_API_VERSION_I2S_CONFIG,
  540. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  541. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  542. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  543. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  544. 0,
  545. },
  546. {
  547. AFE_API_VERSION_I2S_CONFIG,
  548. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  549. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  550. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  551. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  552. 0,
  553. },
  554. {
  555. AFE_API_VERSION_I2S_CONFIG,
  556. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  557. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  558. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  559. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  560. 0,
  561. },
  562. {
  563. AFE_API_VERSION_I2S_CONFIG,
  564. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  565. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  566. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  567. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  568. 0,
  569. },
  570. {
  571. AFE_API_VERSION_I2S_CONFIG,
  572. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  573. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  574. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  575. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  576. 0,
  577. }
  578. };
  579. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  580. static int slim_get_sample_rate_val(int sample_rate)
  581. {
  582. int sample_rate_val = 0;
  583. switch (sample_rate) {
  584. case SAMPLING_RATE_8KHZ:
  585. sample_rate_val = 0;
  586. break;
  587. case SAMPLING_RATE_16KHZ:
  588. sample_rate_val = 1;
  589. break;
  590. case SAMPLING_RATE_32KHZ:
  591. sample_rate_val = 2;
  592. break;
  593. case SAMPLING_RATE_44P1KHZ:
  594. sample_rate_val = 3;
  595. break;
  596. case SAMPLING_RATE_48KHZ:
  597. sample_rate_val = 4;
  598. break;
  599. case SAMPLING_RATE_88P2KHZ:
  600. sample_rate_val = 5;
  601. break;
  602. case SAMPLING_RATE_96KHZ:
  603. sample_rate_val = 6;
  604. break;
  605. case SAMPLING_RATE_176P4KHZ:
  606. sample_rate_val = 7;
  607. break;
  608. case SAMPLING_RATE_192KHZ:
  609. sample_rate_val = 8;
  610. break;
  611. case SAMPLING_RATE_352P8KHZ:
  612. sample_rate_val = 9;
  613. break;
  614. case SAMPLING_RATE_384KHZ:
  615. sample_rate_val = 10;
  616. break;
  617. default:
  618. sample_rate_val = 4;
  619. break;
  620. }
  621. return sample_rate_val;
  622. }
  623. static int slim_get_sample_rate(int value)
  624. {
  625. int sample_rate = 0;
  626. switch (value) {
  627. case 0:
  628. sample_rate = SAMPLING_RATE_8KHZ;
  629. break;
  630. case 1:
  631. sample_rate = SAMPLING_RATE_16KHZ;
  632. break;
  633. case 2:
  634. sample_rate = SAMPLING_RATE_32KHZ;
  635. break;
  636. case 3:
  637. sample_rate = SAMPLING_RATE_44P1KHZ;
  638. break;
  639. case 4:
  640. sample_rate = SAMPLING_RATE_48KHZ;
  641. break;
  642. case 5:
  643. sample_rate = SAMPLING_RATE_88P2KHZ;
  644. break;
  645. case 6:
  646. sample_rate = SAMPLING_RATE_96KHZ;
  647. break;
  648. case 7:
  649. sample_rate = SAMPLING_RATE_176P4KHZ;
  650. break;
  651. case 8:
  652. sample_rate = SAMPLING_RATE_192KHZ;
  653. break;
  654. case 9:
  655. sample_rate = SAMPLING_RATE_352P8KHZ;
  656. break;
  657. case 10:
  658. sample_rate = SAMPLING_RATE_384KHZ;
  659. break;
  660. default:
  661. sample_rate = SAMPLING_RATE_48KHZ;
  662. break;
  663. }
  664. return sample_rate;
  665. }
  666. static int slim_get_bit_format_val(int bit_format)
  667. {
  668. int val = 0;
  669. switch (bit_format) {
  670. case SNDRV_PCM_FORMAT_S32_LE:
  671. val = 3;
  672. break;
  673. case SNDRV_PCM_FORMAT_S24_3LE:
  674. val = 2;
  675. break;
  676. case SNDRV_PCM_FORMAT_S24_LE:
  677. val = 1;
  678. break;
  679. case SNDRV_PCM_FORMAT_S16_LE:
  680. default:
  681. val = 0;
  682. break;
  683. }
  684. return val;
  685. }
  686. static int slim_get_bit_format(int val)
  687. {
  688. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  689. switch (val) {
  690. case 0:
  691. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  692. break;
  693. case 1:
  694. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  695. break;
  696. case 2:
  697. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  698. break;
  699. case 3:
  700. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  701. break;
  702. default:
  703. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  704. break;
  705. }
  706. return bit_fmt;
  707. }
  708. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  709. {
  710. int port_id = 0;
  711. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  712. port_id = SLIM_RX_0;
  713. } else if (strnstr(kcontrol->id.name,
  714. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  715. port_id = SLIM_RX_2;
  716. } else if (strnstr(kcontrol->id.name,
  717. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  718. port_id = SLIM_RX_5;
  719. } else if (strnstr(kcontrol->id.name,
  720. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  721. port_id = SLIM_RX_6;
  722. } else if (strnstr(kcontrol->id.name,
  723. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  724. port_id = SLIM_TX_0;
  725. } else if (strnstr(kcontrol->id.name,
  726. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  727. port_id = SLIM_TX_1;
  728. } else {
  729. pr_err("%s: unsupported channel: %s",
  730. __func__, kcontrol->id.name);
  731. return -EINVAL;
  732. }
  733. return port_id;
  734. }
  735. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  736. struct snd_ctl_elem_value *ucontrol)
  737. {
  738. int ch_num = slim_get_port_idx(kcontrol);
  739. if (ch_num < 0)
  740. return ch_num;
  741. ucontrol->value.enumerated.item[0] =
  742. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  743. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  744. ch_num, slim_rx_cfg[ch_num].sample_rate,
  745. ucontrol->value.enumerated.item[0]);
  746. return 0;
  747. }
  748. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  749. struct snd_ctl_elem_value *ucontrol)
  750. {
  751. int ch_num = slim_get_port_idx(kcontrol);
  752. if (ch_num < 0)
  753. return ch_num;
  754. slim_rx_cfg[ch_num].sample_rate =
  755. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  756. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  757. ch_num, slim_rx_cfg[ch_num].sample_rate,
  758. ucontrol->value.enumerated.item[0]);
  759. return 0;
  760. }
  761. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  762. struct snd_ctl_elem_value *ucontrol)
  763. {
  764. int ch_num = slim_get_port_idx(kcontrol);
  765. if (ch_num < 0)
  766. return ch_num;
  767. ucontrol->value.enumerated.item[0] =
  768. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  769. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  770. ch_num, slim_tx_cfg[ch_num].sample_rate,
  771. ucontrol->value.enumerated.item[0]);
  772. return 0;
  773. }
  774. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  775. struct snd_ctl_elem_value *ucontrol)
  776. {
  777. int sample_rate = 0;
  778. int ch_num = slim_get_port_idx(kcontrol);
  779. if (ch_num < 0)
  780. return ch_num;
  781. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  782. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  783. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  784. __func__, sample_rate);
  785. return -EINVAL;
  786. }
  787. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  788. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  789. ch_num, slim_tx_cfg[ch_num].sample_rate,
  790. ucontrol->value.enumerated.item[0]);
  791. return 0;
  792. }
  793. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  794. struct snd_ctl_elem_value *ucontrol)
  795. {
  796. int ch_num = slim_get_port_idx(kcontrol);
  797. if (ch_num < 0)
  798. return ch_num;
  799. ucontrol->value.enumerated.item[0] =
  800. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  801. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  802. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  803. ucontrol->value.enumerated.item[0]);
  804. return 0;
  805. }
  806. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  807. struct snd_ctl_elem_value *ucontrol)
  808. {
  809. int ch_num = slim_get_port_idx(kcontrol);
  810. if (ch_num < 0)
  811. return ch_num;
  812. slim_rx_cfg[ch_num].bit_format =
  813. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  814. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  815. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  816. ucontrol->value.enumerated.item[0]);
  817. return 0;
  818. }
  819. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  820. struct snd_ctl_elem_value *ucontrol)
  821. {
  822. int ch_num = slim_get_port_idx(kcontrol);
  823. if (ch_num < 0)
  824. return ch_num;
  825. ucontrol->value.enumerated.item[0] =
  826. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  827. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  828. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  829. ucontrol->value.enumerated.item[0]);
  830. return 0;
  831. }
  832. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  833. struct snd_ctl_elem_value *ucontrol)
  834. {
  835. int ch_num = slim_get_port_idx(kcontrol);
  836. if (ch_num < 0)
  837. return ch_num;
  838. slim_tx_cfg[ch_num].bit_format =
  839. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  840. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  841. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  842. ucontrol->value.enumerated.item[0]);
  843. return 0;
  844. }
  845. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  846. struct snd_ctl_elem_value *ucontrol)
  847. {
  848. int ch_num = slim_get_port_idx(kcontrol);
  849. if (ch_num < 0)
  850. return ch_num;
  851. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  852. ch_num, slim_rx_cfg[ch_num].channels);
  853. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  854. return 0;
  855. }
  856. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  857. struct snd_ctl_elem_value *ucontrol)
  858. {
  859. int ch_num = slim_get_port_idx(kcontrol);
  860. if (ch_num < 0)
  861. return ch_num;
  862. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  863. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  864. ch_num, slim_rx_cfg[ch_num].channels);
  865. return 1;
  866. }
  867. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  868. struct snd_ctl_elem_value *ucontrol)
  869. {
  870. int ch_num = slim_get_port_idx(kcontrol);
  871. if (ch_num < 0)
  872. return ch_num;
  873. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  874. ch_num, slim_tx_cfg[ch_num].channels);
  875. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  876. return 0;
  877. }
  878. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  879. struct snd_ctl_elem_value *ucontrol)
  880. {
  881. int ch_num = slim_get_port_idx(kcontrol);
  882. if (ch_num < 0)
  883. return ch_num;
  884. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  885. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  886. ch_num, slim_tx_cfg[ch_num].channels);
  887. return 1;
  888. }
  889. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  890. struct snd_ctl_elem_value *ucontrol)
  891. {
  892. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  893. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  894. ucontrol->value.integer.value[0]);
  895. return 0;
  896. }
  897. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  898. struct snd_ctl_elem_value *ucontrol)
  899. {
  900. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  901. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  902. return 1;
  903. }
  904. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  905. struct snd_ctl_elem_value *ucontrol)
  906. {
  907. /*
  908. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  909. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  910. * value.
  911. */
  912. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  913. case SAMPLING_RATE_96KHZ:
  914. ucontrol->value.integer.value[0] = 5;
  915. break;
  916. case SAMPLING_RATE_88P2KHZ:
  917. ucontrol->value.integer.value[0] = 4;
  918. break;
  919. case SAMPLING_RATE_48KHZ:
  920. ucontrol->value.integer.value[0] = 3;
  921. break;
  922. case SAMPLING_RATE_44P1KHZ:
  923. ucontrol->value.integer.value[0] = 2;
  924. break;
  925. case SAMPLING_RATE_16KHZ:
  926. ucontrol->value.integer.value[0] = 1;
  927. break;
  928. case SAMPLING_RATE_8KHZ:
  929. default:
  930. ucontrol->value.integer.value[0] = 0;
  931. break;
  932. }
  933. pr_debug("%s: sample rate = %d", __func__,
  934. slim_rx_cfg[SLIM_RX_7].sample_rate);
  935. return 0;
  936. }
  937. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  938. struct snd_ctl_elem_value *ucontrol)
  939. {
  940. switch (ucontrol->value.integer.value[0]) {
  941. case 1:
  942. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  943. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  944. break;
  945. case 2:
  946. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  947. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  948. break;
  949. case 3:
  950. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  951. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  952. break;
  953. case 4:
  954. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  955. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  956. break;
  957. case 5:
  958. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  959. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  960. break;
  961. case 0:
  962. default:
  963. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  964. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  965. break;
  966. }
  967. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  968. __func__,
  969. slim_rx_cfg[SLIM_RX_7].sample_rate,
  970. slim_tx_cfg[SLIM_TX_7].sample_rate,
  971. ucontrol->value.enumerated.item[0]);
  972. return 0;
  973. }
  974. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  975. {
  976. int idx = 0;
  977. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  978. sizeof("WSA_CDC_DMA_RX_0")))
  979. idx = WSA_CDC_DMA_RX_0;
  980. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  981. sizeof("WSA_CDC_DMA_RX_0")))
  982. idx = WSA_CDC_DMA_RX_1;
  983. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  984. sizeof("WSA_CDC_DMA_TX_0")))
  985. idx = WSA_CDC_DMA_TX_0;
  986. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  987. sizeof("WSA_CDC_DMA_TX_1")))
  988. idx = WSA_CDC_DMA_TX_1;
  989. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  990. sizeof("WSA_CDC_DMA_TX_2")))
  991. idx = WSA_CDC_DMA_TX_2;
  992. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  993. sizeof("VA_CDC_DMA_TX_0")))
  994. idx = VA_CDC_DMA_TX_0;
  995. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  996. sizeof("VA_CDC_DMA_TX_1")))
  997. idx = VA_CDC_DMA_TX_1;
  998. else {
  999. pr_err("%s: unsupported port: %s\n",
  1000. __func__, kcontrol->id.name);
  1001. return -EINVAL;
  1002. }
  1003. return idx;
  1004. }
  1005. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1006. struct snd_ctl_elem_value *ucontrol)
  1007. {
  1008. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1009. if (ch_num < 0)
  1010. return ch_num;
  1011. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1012. cdc_dma_rx_cfg[ch_num].channels - 1);
  1013. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1014. return 0;
  1015. }
  1016. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1017. struct snd_ctl_elem_value *ucontrol)
  1018. {
  1019. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1020. if (ch_num < 0)
  1021. return ch_num;
  1022. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1023. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1024. cdc_dma_rx_cfg[ch_num].channels);
  1025. return 1;
  1026. }
  1027. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1028. struct snd_ctl_elem_value *ucontrol)
  1029. {
  1030. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1031. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1032. case SNDRV_PCM_FORMAT_S32_LE:
  1033. ucontrol->value.integer.value[0] = 3;
  1034. break;
  1035. case SNDRV_PCM_FORMAT_S24_3LE:
  1036. ucontrol->value.integer.value[0] = 2;
  1037. break;
  1038. case SNDRV_PCM_FORMAT_S24_LE:
  1039. ucontrol->value.integer.value[0] = 1;
  1040. break;
  1041. case SNDRV_PCM_FORMAT_S16_LE:
  1042. default:
  1043. ucontrol->value.integer.value[0] = 0;
  1044. break;
  1045. }
  1046. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1047. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1048. ucontrol->value.integer.value[0]);
  1049. return 0;
  1050. }
  1051. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1052. struct snd_ctl_elem_value *ucontrol)
  1053. {
  1054. int rc = 0;
  1055. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1056. switch (ucontrol->value.integer.value[0]) {
  1057. case 3:
  1058. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1059. break;
  1060. case 2:
  1061. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1062. break;
  1063. case 1:
  1064. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1065. break;
  1066. case 0:
  1067. default:
  1068. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1069. break;
  1070. }
  1071. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1072. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1073. ucontrol->value.integer.value[0]);
  1074. return rc;
  1075. }
  1076. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1077. {
  1078. int sample_rate_val = 0;
  1079. switch (sample_rate) {
  1080. case SAMPLING_RATE_8KHZ:
  1081. sample_rate_val = 0;
  1082. break;
  1083. case SAMPLING_RATE_16KHZ:
  1084. sample_rate_val = 1;
  1085. break;
  1086. case SAMPLING_RATE_32KHZ:
  1087. sample_rate_val = 2;
  1088. break;
  1089. case SAMPLING_RATE_44P1KHZ:
  1090. sample_rate_val = 3;
  1091. break;
  1092. case SAMPLING_RATE_48KHZ:
  1093. sample_rate_val = 4;
  1094. break;
  1095. case SAMPLING_RATE_88P2KHZ:
  1096. sample_rate_val = 5;
  1097. break;
  1098. case SAMPLING_RATE_96KHZ:
  1099. sample_rate_val = 6;
  1100. break;
  1101. case SAMPLING_RATE_176P4KHZ:
  1102. sample_rate_val = 7;
  1103. break;
  1104. case SAMPLING_RATE_192KHZ:
  1105. sample_rate_val = 8;
  1106. break;
  1107. case SAMPLING_RATE_352P8KHZ:
  1108. sample_rate_val = 9;
  1109. break;
  1110. case SAMPLING_RATE_384KHZ:
  1111. sample_rate_val = 10;
  1112. break;
  1113. default:
  1114. sample_rate_val = 4;
  1115. break;
  1116. }
  1117. return sample_rate_val;
  1118. }
  1119. static int cdc_dma_get_sample_rate(int value)
  1120. {
  1121. int sample_rate = 0;
  1122. switch (value) {
  1123. case 0:
  1124. sample_rate = SAMPLING_RATE_8KHZ;
  1125. break;
  1126. case 1:
  1127. sample_rate = SAMPLING_RATE_16KHZ;
  1128. break;
  1129. case 2:
  1130. sample_rate = SAMPLING_RATE_32KHZ;
  1131. break;
  1132. case 3:
  1133. sample_rate = SAMPLING_RATE_44P1KHZ;
  1134. break;
  1135. case 4:
  1136. sample_rate = SAMPLING_RATE_48KHZ;
  1137. break;
  1138. case 5:
  1139. sample_rate = SAMPLING_RATE_88P2KHZ;
  1140. break;
  1141. case 6:
  1142. sample_rate = SAMPLING_RATE_96KHZ;
  1143. break;
  1144. case 7:
  1145. sample_rate = SAMPLING_RATE_176P4KHZ;
  1146. break;
  1147. case 8:
  1148. sample_rate = SAMPLING_RATE_192KHZ;
  1149. break;
  1150. case 9:
  1151. sample_rate = SAMPLING_RATE_352P8KHZ;
  1152. break;
  1153. case 10:
  1154. sample_rate = SAMPLING_RATE_384KHZ;
  1155. break;
  1156. default:
  1157. sample_rate = SAMPLING_RATE_48KHZ;
  1158. break;
  1159. }
  1160. return sample_rate;
  1161. }
  1162. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1163. struct snd_ctl_elem_value *ucontrol)
  1164. {
  1165. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1166. if (ch_num < 0)
  1167. return ch_num;
  1168. ucontrol->value.enumerated.item[0] =
  1169. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1170. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1171. cdc_dma_rx_cfg[ch_num].sample_rate);
  1172. return 0;
  1173. }
  1174. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1175. struct snd_ctl_elem_value *ucontrol)
  1176. {
  1177. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1178. if (ch_num < 0)
  1179. return ch_num;
  1180. cdc_dma_rx_cfg[ch_num].sample_rate =
  1181. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1182. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1183. __func__, ucontrol->value.enumerated.item[0],
  1184. cdc_dma_rx_cfg[ch_num].sample_rate);
  1185. return 0;
  1186. }
  1187. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1188. struct snd_ctl_elem_value *ucontrol)
  1189. {
  1190. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1191. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1192. cdc_dma_tx_cfg[ch_num].channels);
  1193. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1194. return 0;
  1195. }
  1196. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1197. struct snd_ctl_elem_value *ucontrol)
  1198. {
  1199. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1200. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1201. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1202. cdc_dma_tx_cfg[ch_num].channels);
  1203. return 1;
  1204. }
  1205. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1206. struct snd_ctl_elem_value *ucontrol)
  1207. {
  1208. int sample_rate_val;
  1209. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1210. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1211. case SAMPLING_RATE_384KHZ:
  1212. sample_rate_val = 12;
  1213. break;
  1214. case SAMPLING_RATE_352P8KHZ:
  1215. sample_rate_val = 11;
  1216. break;
  1217. case SAMPLING_RATE_192KHZ:
  1218. sample_rate_val = 10;
  1219. break;
  1220. case SAMPLING_RATE_176P4KHZ:
  1221. sample_rate_val = 9;
  1222. break;
  1223. case SAMPLING_RATE_96KHZ:
  1224. sample_rate_val = 8;
  1225. break;
  1226. case SAMPLING_RATE_88P2KHZ:
  1227. sample_rate_val = 7;
  1228. break;
  1229. case SAMPLING_RATE_48KHZ:
  1230. sample_rate_val = 6;
  1231. break;
  1232. case SAMPLING_RATE_44P1KHZ:
  1233. sample_rate_val = 5;
  1234. break;
  1235. case SAMPLING_RATE_32KHZ:
  1236. sample_rate_val = 4;
  1237. break;
  1238. case SAMPLING_RATE_22P05KHZ:
  1239. sample_rate_val = 3;
  1240. break;
  1241. case SAMPLING_RATE_16KHZ:
  1242. sample_rate_val = 2;
  1243. break;
  1244. case SAMPLING_RATE_11P025KHZ:
  1245. sample_rate_val = 1;
  1246. break;
  1247. case SAMPLING_RATE_8KHZ:
  1248. sample_rate_val = 0;
  1249. break;
  1250. default:
  1251. sample_rate_val = 6;
  1252. break;
  1253. }
  1254. ucontrol->value.integer.value[0] = sample_rate_val;
  1255. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1256. cdc_dma_tx_cfg[ch_num].sample_rate);
  1257. return 0;
  1258. }
  1259. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1260. struct snd_ctl_elem_value *ucontrol)
  1261. {
  1262. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1263. switch (ucontrol->value.integer.value[0]) {
  1264. case 12:
  1265. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1266. break;
  1267. case 11:
  1268. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1269. break;
  1270. case 10:
  1271. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1272. break;
  1273. case 9:
  1274. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1275. break;
  1276. case 8:
  1277. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1278. break;
  1279. case 7:
  1280. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1281. break;
  1282. case 6:
  1283. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1284. break;
  1285. case 5:
  1286. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1287. break;
  1288. case 4:
  1289. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1290. break;
  1291. case 3:
  1292. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1293. break;
  1294. case 2:
  1295. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1296. break;
  1297. case 1:
  1298. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1299. break;
  1300. case 0:
  1301. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1302. break;
  1303. default:
  1304. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1305. break;
  1306. }
  1307. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1308. __func__, ucontrol->value.integer.value[0],
  1309. cdc_dma_tx_cfg[ch_num].sample_rate);
  1310. return 0;
  1311. }
  1312. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1313. struct snd_ctl_elem_value *ucontrol)
  1314. {
  1315. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1316. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1317. case SNDRV_PCM_FORMAT_S32_LE:
  1318. ucontrol->value.integer.value[0] = 3;
  1319. break;
  1320. case SNDRV_PCM_FORMAT_S24_3LE:
  1321. ucontrol->value.integer.value[0] = 2;
  1322. break;
  1323. case SNDRV_PCM_FORMAT_S24_LE:
  1324. ucontrol->value.integer.value[0] = 1;
  1325. break;
  1326. case SNDRV_PCM_FORMAT_S16_LE:
  1327. default:
  1328. ucontrol->value.integer.value[0] = 0;
  1329. break;
  1330. }
  1331. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1332. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1333. ucontrol->value.integer.value[0]);
  1334. return 0;
  1335. }
  1336. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1337. struct snd_ctl_elem_value *ucontrol)
  1338. {
  1339. int rc = 0;
  1340. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1341. switch (ucontrol->value.integer.value[0]) {
  1342. case 3:
  1343. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1344. break;
  1345. case 2:
  1346. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1347. break;
  1348. case 1:
  1349. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1350. break;
  1351. case 0:
  1352. default:
  1353. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1354. break;
  1355. }
  1356. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1357. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1358. ucontrol->value.integer.value[0]);
  1359. return rc;
  1360. }
  1361. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1362. struct snd_ctl_elem_value *ucontrol)
  1363. {
  1364. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1365. usb_rx_cfg.channels);
  1366. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1367. return 0;
  1368. }
  1369. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1370. struct snd_ctl_elem_value *ucontrol)
  1371. {
  1372. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1373. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1374. return 1;
  1375. }
  1376. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1377. struct snd_ctl_elem_value *ucontrol)
  1378. {
  1379. int sample_rate_val;
  1380. switch (usb_rx_cfg.sample_rate) {
  1381. case SAMPLING_RATE_384KHZ:
  1382. sample_rate_val = 12;
  1383. break;
  1384. case SAMPLING_RATE_352P8KHZ:
  1385. sample_rate_val = 11;
  1386. break;
  1387. case SAMPLING_RATE_192KHZ:
  1388. sample_rate_val = 10;
  1389. break;
  1390. case SAMPLING_RATE_176P4KHZ:
  1391. sample_rate_val = 9;
  1392. break;
  1393. case SAMPLING_RATE_96KHZ:
  1394. sample_rate_val = 8;
  1395. break;
  1396. case SAMPLING_RATE_88P2KHZ:
  1397. sample_rate_val = 7;
  1398. break;
  1399. case SAMPLING_RATE_48KHZ:
  1400. sample_rate_val = 6;
  1401. break;
  1402. case SAMPLING_RATE_44P1KHZ:
  1403. sample_rate_val = 5;
  1404. break;
  1405. case SAMPLING_RATE_32KHZ:
  1406. sample_rate_val = 4;
  1407. break;
  1408. case SAMPLING_RATE_22P05KHZ:
  1409. sample_rate_val = 3;
  1410. break;
  1411. case SAMPLING_RATE_16KHZ:
  1412. sample_rate_val = 2;
  1413. break;
  1414. case SAMPLING_RATE_11P025KHZ:
  1415. sample_rate_val = 1;
  1416. break;
  1417. case SAMPLING_RATE_8KHZ:
  1418. default:
  1419. sample_rate_val = 0;
  1420. break;
  1421. }
  1422. ucontrol->value.integer.value[0] = sample_rate_val;
  1423. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1424. usb_rx_cfg.sample_rate);
  1425. return 0;
  1426. }
  1427. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1428. struct snd_ctl_elem_value *ucontrol)
  1429. {
  1430. switch (ucontrol->value.integer.value[0]) {
  1431. case 12:
  1432. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1433. break;
  1434. case 11:
  1435. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1436. break;
  1437. case 10:
  1438. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1439. break;
  1440. case 9:
  1441. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1442. break;
  1443. case 8:
  1444. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1445. break;
  1446. case 7:
  1447. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1448. break;
  1449. case 6:
  1450. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1451. break;
  1452. case 5:
  1453. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1454. break;
  1455. case 4:
  1456. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1457. break;
  1458. case 3:
  1459. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1460. break;
  1461. case 2:
  1462. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1463. break;
  1464. case 1:
  1465. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1466. break;
  1467. case 0:
  1468. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1469. break;
  1470. default:
  1471. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1472. break;
  1473. }
  1474. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1475. __func__, ucontrol->value.integer.value[0],
  1476. usb_rx_cfg.sample_rate);
  1477. return 0;
  1478. }
  1479. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1480. struct snd_ctl_elem_value *ucontrol)
  1481. {
  1482. switch (usb_rx_cfg.bit_format) {
  1483. case SNDRV_PCM_FORMAT_S32_LE:
  1484. ucontrol->value.integer.value[0] = 3;
  1485. break;
  1486. case SNDRV_PCM_FORMAT_S24_3LE:
  1487. ucontrol->value.integer.value[0] = 2;
  1488. break;
  1489. case SNDRV_PCM_FORMAT_S24_LE:
  1490. ucontrol->value.integer.value[0] = 1;
  1491. break;
  1492. case SNDRV_PCM_FORMAT_S16_LE:
  1493. default:
  1494. ucontrol->value.integer.value[0] = 0;
  1495. break;
  1496. }
  1497. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1498. __func__, usb_rx_cfg.bit_format,
  1499. ucontrol->value.integer.value[0]);
  1500. return 0;
  1501. }
  1502. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1503. struct snd_ctl_elem_value *ucontrol)
  1504. {
  1505. int rc = 0;
  1506. switch (ucontrol->value.integer.value[0]) {
  1507. case 3:
  1508. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1509. break;
  1510. case 2:
  1511. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1512. break;
  1513. case 1:
  1514. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1515. break;
  1516. case 0:
  1517. default:
  1518. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1519. break;
  1520. }
  1521. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1522. __func__, usb_rx_cfg.bit_format,
  1523. ucontrol->value.integer.value[0]);
  1524. return rc;
  1525. }
  1526. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1527. struct snd_ctl_elem_value *ucontrol)
  1528. {
  1529. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1530. usb_tx_cfg.channels);
  1531. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1532. return 0;
  1533. }
  1534. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1535. struct snd_ctl_elem_value *ucontrol)
  1536. {
  1537. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1538. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1539. return 1;
  1540. }
  1541. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1542. struct snd_ctl_elem_value *ucontrol)
  1543. {
  1544. int sample_rate_val;
  1545. switch (usb_tx_cfg.sample_rate) {
  1546. case SAMPLING_RATE_384KHZ:
  1547. sample_rate_val = 12;
  1548. break;
  1549. case SAMPLING_RATE_352P8KHZ:
  1550. sample_rate_val = 11;
  1551. break;
  1552. case SAMPLING_RATE_192KHZ:
  1553. sample_rate_val = 10;
  1554. break;
  1555. case SAMPLING_RATE_176P4KHZ:
  1556. sample_rate_val = 9;
  1557. break;
  1558. case SAMPLING_RATE_96KHZ:
  1559. sample_rate_val = 8;
  1560. break;
  1561. case SAMPLING_RATE_88P2KHZ:
  1562. sample_rate_val = 7;
  1563. break;
  1564. case SAMPLING_RATE_48KHZ:
  1565. sample_rate_val = 6;
  1566. break;
  1567. case SAMPLING_RATE_44P1KHZ:
  1568. sample_rate_val = 5;
  1569. break;
  1570. case SAMPLING_RATE_32KHZ:
  1571. sample_rate_val = 4;
  1572. break;
  1573. case SAMPLING_RATE_22P05KHZ:
  1574. sample_rate_val = 3;
  1575. break;
  1576. case SAMPLING_RATE_16KHZ:
  1577. sample_rate_val = 2;
  1578. break;
  1579. case SAMPLING_RATE_11P025KHZ:
  1580. sample_rate_val = 1;
  1581. break;
  1582. case SAMPLING_RATE_8KHZ:
  1583. sample_rate_val = 0;
  1584. break;
  1585. default:
  1586. sample_rate_val = 6;
  1587. break;
  1588. }
  1589. ucontrol->value.integer.value[0] = sample_rate_val;
  1590. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1591. usb_tx_cfg.sample_rate);
  1592. return 0;
  1593. }
  1594. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1595. struct snd_ctl_elem_value *ucontrol)
  1596. {
  1597. switch (ucontrol->value.integer.value[0]) {
  1598. case 12:
  1599. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1600. break;
  1601. case 11:
  1602. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1603. break;
  1604. case 10:
  1605. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1606. break;
  1607. case 9:
  1608. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1609. break;
  1610. case 8:
  1611. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1612. break;
  1613. case 7:
  1614. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1615. break;
  1616. case 6:
  1617. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1618. break;
  1619. case 5:
  1620. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1621. break;
  1622. case 4:
  1623. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1624. break;
  1625. case 3:
  1626. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1627. break;
  1628. case 2:
  1629. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1630. break;
  1631. case 1:
  1632. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1633. break;
  1634. case 0:
  1635. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1636. break;
  1637. default:
  1638. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1639. break;
  1640. }
  1641. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1642. __func__, ucontrol->value.integer.value[0],
  1643. usb_tx_cfg.sample_rate);
  1644. return 0;
  1645. }
  1646. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1647. struct snd_ctl_elem_value *ucontrol)
  1648. {
  1649. switch (usb_tx_cfg.bit_format) {
  1650. case SNDRV_PCM_FORMAT_S32_LE:
  1651. ucontrol->value.integer.value[0] = 3;
  1652. break;
  1653. case SNDRV_PCM_FORMAT_S24_3LE:
  1654. ucontrol->value.integer.value[0] = 2;
  1655. break;
  1656. case SNDRV_PCM_FORMAT_S24_LE:
  1657. ucontrol->value.integer.value[0] = 1;
  1658. break;
  1659. case SNDRV_PCM_FORMAT_S16_LE:
  1660. default:
  1661. ucontrol->value.integer.value[0] = 0;
  1662. break;
  1663. }
  1664. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1665. __func__, usb_tx_cfg.bit_format,
  1666. ucontrol->value.integer.value[0]);
  1667. return 0;
  1668. }
  1669. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1670. struct snd_ctl_elem_value *ucontrol)
  1671. {
  1672. int rc = 0;
  1673. switch (ucontrol->value.integer.value[0]) {
  1674. case 3:
  1675. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1676. break;
  1677. case 2:
  1678. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1679. break;
  1680. case 1:
  1681. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1682. break;
  1683. case 0:
  1684. default:
  1685. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1686. break;
  1687. }
  1688. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1689. __func__, usb_tx_cfg.bit_format,
  1690. ucontrol->value.integer.value[0]);
  1691. return rc;
  1692. }
  1693. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1694. struct snd_ctl_elem_value *ucontrol)
  1695. {
  1696. pr_debug("%s: proxy_rx channels = %d\n",
  1697. __func__, proxy_rx_cfg.channels);
  1698. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1699. return 0;
  1700. }
  1701. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1702. struct snd_ctl_elem_value *ucontrol)
  1703. {
  1704. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1705. pr_debug("%s: proxy_rx channels = %d\n",
  1706. __func__, proxy_rx_cfg.channels);
  1707. return 1;
  1708. }
  1709. static int tdm_get_sample_rate(int value)
  1710. {
  1711. int sample_rate = 0;
  1712. switch (value) {
  1713. case 0:
  1714. sample_rate = SAMPLING_RATE_8KHZ;
  1715. break;
  1716. case 1:
  1717. sample_rate = SAMPLING_RATE_16KHZ;
  1718. break;
  1719. case 2:
  1720. sample_rate = SAMPLING_RATE_32KHZ;
  1721. break;
  1722. case 3:
  1723. sample_rate = SAMPLING_RATE_48KHZ;
  1724. break;
  1725. case 4:
  1726. sample_rate = SAMPLING_RATE_176P4KHZ;
  1727. break;
  1728. case 5:
  1729. sample_rate = SAMPLING_RATE_352P8KHZ;
  1730. break;
  1731. default:
  1732. sample_rate = SAMPLING_RATE_48KHZ;
  1733. break;
  1734. }
  1735. return sample_rate;
  1736. }
  1737. static int aux_pcm_get_sample_rate(int value)
  1738. {
  1739. int sample_rate;
  1740. switch (value) {
  1741. case 1:
  1742. sample_rate = SAMPLING_RATE_16KHZ;
  1743. break;
  1744. case 0:
  1745. default:
  1746. sample_rate = SAMPLING_RATE_8KHZ;
  1747. break;
  1748. }
  1749. return sample_rate;
  1750. }
  1751. static int tdm_get_sample_rate_val(int sample_rate)
  1752. {
  1753. int sample_rate_val = 0;
  1754. switch (sample_rate) {
  1755. case SAMPLING_RATE_8KHZ:
  1756. sample_rate_val = 0;
  1757. break;
  1758. case SAMPLING_RATE_16KHZ:
  1759. sample_rate_val = 1;
  1760. break;
  1761. case SAMPLING_RATE_32KHZ:
  1762. sample_rate_val = 2;
  1763. break;
  1764. case SAMPLING_RATE_48KHZ:
  1765. sample_rate_val = 3;
  1766. break;
  1767. case SAMPLING_RATE_176P4KHZ:
  1768. sample_rate_val = 4;
  1769. break;
  1770. case SAMPLING_RATE_352P8KHZ:
  1771. sample_rate_val = 5;
  1772. break;
  1773. default:
  1774. sample_rate_val = 3;
  1775. break;
  1776. }
  1777. return sample_rate_val;
  1778. }
  1779. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1780. {
  1781. int sample_rate_val;
  1782. switch (sample_rate) {
  1783. case SAMPLING_RATE_16KHZ:
  1784. sample_rate_val = 1;
  1785. break;
  1786. case SAMPLING_RATE_8KHZ:
  1787. default:
  1788. sample_rate_val = 0;
  1789. break;
  1790. }
  1791. return sample_rate_val;
  1792. }
  1793. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1794. struct tdm_port *port)
  1795. {
  1796. if (port) {
  1797. if (strnstr(kcontrol->id.name, "PRI",
  1798. sizeof(kcontrol->id.name))) {
  1799. port->mode = TDM_PRI;
  1800. } else if (strnstr(kcontrol->id.name, "SEC",
  1801. sizeof(kcontrol->id.name))) {
  1802. port->mode = TDM_SEC;
  1803. } else if (strnstr(kcontrol->id.name, "TERT",
  1804. sizeof(kcontrol->id.name))) {
  1805. port->mode = TDM_TERT;
  1806. } else if (strnstr(kcontrol->id.name, "QUAT",
  1807. sizeof(kcontrol->id.name))) {
  1808. port->mode = TDM_QUAT;
  1809. } else if (strnstr(kcontrol->id.name, "QUIN",
  1810. sizeof(kcontrol->id.name))) {
  1811. port->mode = TDM_QUIN;
  1812. } else {
  1813. pr_err("%s: unsupported mode in: %s",
  1814. __func__, kcontrol->id.name);
  1815. return -EINVAL;
  1816. }
  1817. if (strnstr(kcontrol->id.name, "RX_0",
  1818. sizeof(kcontrol->id.name)) ||
  1819. strnstr(kcontrol->id.name, "TX_0",
  1820. sizeof(kcontrol->id.name))) {
  1821. port->channel = TDM_0;
  1822. } else if (strnstr(kcontrol->id.name, "RX_1",
  1823. sizeof(kcontrol->id.name)) ||
  1824. strnstr(kcontrol->id.name, "TX_1",
  1825. sizeof(kcontrol->id.name))) {
  1826. port->channel = TDM_1;
  1827. } else if (strnstr(kcontrol->id.name, "RX_2",
  1828. sizeof(kcontrol->id.name)) ||
  1829. strnstr(kcontrol->id.name, "TX_2",
  1830. sizeof(kcontrol->id.name))) {
  1831. port->channel = TDM_2;
  1832. } else if (strnstr(kcontrol->id.name, "RX_3",
  1833. sizeof(kcontrol->id.name)) ||
  1834. strnstr(kcontrol->id.name, "TX_3",
  1835. sizeof(kcontrol->id.name))) {
  1836. port->channel = TDM_3;
  1837. } else if (strnstr(kcontrol->id.name, "RX_4",
  1838. sizeof(kcontrol->id.name)) ||
  1839. strnstr(kcontrol->id.name, "TX_4",
  1840. sizeof(kcontrol->id.name))) {
  1841. port->channel = TDM_4;
  1842. } else if (strnstr(kcontrol->id.name, "RX_5",
  1843. sizeof(kcontrol->id.name)) ||
  1844. strnstr(kcontrol->id.name, "TX_5",
  1845. sizeof(kcontrol->id.name))) {
  1846. port->channel = TDM_5;
  1847. } else if (strnstr(kcontrol->id.name, "RX_6",
  1848. sizeof(kcontrol->id.name)) ||
  1849. strnstr(kcontrol->id.name, "TX_6",
  1850. sizeof(kcontrol->id.name))) {
  1851. port->channel = TDM_6;
  1852. } else if (strnstr(kcontrol->id.name, "RX_7",
  1853. sizeof(kcontrol->id.name)) ||
  1854. strnstr(kcontrol->id.name, "TX_7",
  1855. sizeof(kcontrol->id.name))) {
  1856. port->channel = TDM_7;
  1857. } else {
  1858. pr_err("%s: unsupported channel in: %s",
  1859. __func__, kcontrol->id.name);
  1860. return -EINVAL;
  1861. }
  1862. } else
  1863. return -EINVAL;
  1864. return 0;
  1865. }
  1866. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1867. struct snd_ctl_elem_value *ucontrol)
  1868. {
  1869. struct tdm_port port;
  1870. int ret = tdm_get_port_idx(kcontrol, &port);
  1871. if (ret) {
  1872. pr_err("%s: unsupported control: %s",
  1873. __func__, kcontrol->id.name);
  1874. } else {
  1875. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1876. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1877. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1878. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1879. ucontrol->value.enumerated.item[0]);
  1880. }
  1881. return ret;
  1882. }
  1883. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1884. struct snd_ctl_elem_value *ucontrol)
  1885. {
  1886. struct tdm_port port;
  1887. int ret = tdm_get_port_idx(kcontrol, &port);
  1888. if (ret) {
  1889. pr_err("%s: unsupported control: %s",
  1890. __func__, kcontrol->id.name);
  1891. } else {
  1892. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1893. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1894. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1895. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1896. ucontrol->value.enumerated.item[0]);
  1897. }
  1898. return ret;
  1899. }
  1900. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1901. struct snd_ctl_elem_value *ucontrol)
  1902. {
  1903. struct tdm_port port;
  1904. int ret = tdm_get_port_idx(kcontrol, &port);
  1905. if (ret) {
  1906. pr_err("%s: unsupported control: %s",
  1907. __func__, kcontrol->id.name);
  1908. } else {
  1909. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1910. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1911. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1912. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1913. ucontrol->value.enumerated.item[0]);
  1914. }
  1915. return ret;
  1916. }
  1917. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1918. struct snd_ctl_elem_value *ucontrol)
  1919. {
  1920. struct tdm_port port;
  1921. int ret = tdm_get_port_idx(kcontrol, &port);
  1922. if (ret) {
  1923. pr_err("%s: unsupported control: %s",
  1924. __func__, kcontrol->id.name);
  1925. } else {
  1926. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1927. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1928. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1929. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1930. ucontrol->value.enumerated.item[0]);
  1931. }
  1932. return ret;
  1933. }
  1934. static int tdm_get_format(int value)
  1935. {
  1936. int format = 0;
  1937. switch (value) {
  1938. case 0:
  1939. format = SNDRV_PCM_FORMAT_S16_LE;
  1940. break;
  1941. case 1:
  1942. format = SNDRV_PCM_FORMAT_S24_LE;
  1943. break;
  1944. case 2:
  1945. format = SNDRV_PCM_FORMAT_S32_LE;
  1946. break;
  1947. default:
  1948. format = SNDRV_PCM_FORMAT_S16_LE;
  1949. break;
  1950. }
  1951. return format;
  1952. }
  1953. static int tdm_get_format_val(int format)
  1954. {
  1955. int value = 0;
  1956. switch (format) {
  1957. case SNDRV_PCM_FORMAT_S16_LE:
  1958. value = 0;
  1959. break;
  1960. case SNDRV_PCM_FORMAT_S24_LE:
  1961. value = 1;
  1962. break;
  1963. case SNDRV_PCM_FORMAT_S32_LE:
  1964. value = 2;
  1965. break;
  1966. default:
  1967. value = 0;
  1968. break;
  1969. }
  1970. return value;
  1971. }
  1972. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1973. struct snd_ctl_elem_value *ucontrol)
  1974. {
  1975. struct tdm_port port;
  1976. int ret = tdm_get_port_idx(kcontrol, &port);
  1977. if (ret) {
  1978. pr_err("%s: unsupported control: %s",
  1979. __func__, kcontrol->id.name);
  1980. } else {
  1981. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1982. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1983. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1984. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1985. ucontrol->value.enumerated.item[0]);
  1986. }
  1987. return ret;
  1988. }
  1989. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1990. struct snd_ctl_elem_value *ucontrol)
  1991. {
  1992. struct tdm_port port;
  1993. int ret = tdm_get_port_idx(kcontrol, &port);
  1994. if (ret) {
  1995. pr_err("%s: unsupported control: %s",
  1996. __func__, kcontrol->id.name);
  1997. } else {
  1998. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1999. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2000. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2001. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2002. ucontrol->value.enumerated.item[0]);
  2003. }
  2004. return ret;
  2005. }
  2006. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2007. struct snd_ctl_elem_value *ucontrol)
  2008. {
  2009. struct tdm_port port;
  2010. int ret = tdm_get_port_idx(kcontrol, &port);
  2011. if (ret) {
  2012. pr_err("%s: unsupported control: %s",
  2013. __func__, kcontrol->id.name);
  2014. } else {
  2015. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2016. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2017. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2018. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2019. ucontrol->value.enumerated.item[0]);
  2020. }
  2021. return ret;
  2022. }
  2023. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2024. struct snd_ctl_elem_value *ucontrol)
  2025. {
  2026. struct tdm_port port;
  2027. int ret = tdm_get_port_idx(kcontrol, &port);
  2028. if (ret) {
  2029. pr_err("%s: unsupported control: %s",
  2030. __func__, kcontrol->id.name);
  2031. } else {
  2032. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2033. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2034. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2035. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2036. ucontrol->value.enumerated.item[0]);
  2037. }
  2038. return ret;
  2039. }
  2040. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2041. struct snd_ctl_elem_value *ucontrol)
  2042. {
  2043. struct tdm_port port;
  2044. int ret = tdm_get_port_idx(kcontrol, &port);
  2045. if (ret) {
  2046. pr_err("%s: unsupported control: %s",
  2047. __func__, kcontrol->id.name);
  2048. } else {
  2049. ucontrol->value.enumerated.item[0] =
  2050. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2051. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2052. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2053. ucontrol->value.enumerated.item[0]);
  2054. }
  2055. return ret;
  2056. }
  2057. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2058. struct snd_ctl_elem_value *ucontrol)
  2059. {
  2060. struct tdm_port port;
  2061. int ret = tdm_get_port_idx(kcontrol, &port);
  2062. if (ret) {
  2063. pr_err("%s: unsupported control: %s",
  2064. __func__, kcontrol->id.name);
  2065. } else {
  2066. tdm_rx_cfg[port.mode][port.channel].channels =
  2067. ucontrol->value.enumerated.item[0] + 1;
  2068. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2069. tdm_rx_cfg[port.mode][port.channel].channels,
  2070. ucontrol->value.enumerated.item[0] + 1);
  2071. }
  2072. return ret;
  2073. }
  2074. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2075. struct snd_ctl_elem_value *ucontrol)
  2076. {
  2077. struct tdm_port port;
  2078. int ret = tdm_get_port_idx(kcontrol, &port);
  2079. if (ret) {
  2080. pr_err("%s: unsupported control: %s",
  2081. __func__, kcontrol->id.name);
  2082. } else {
  2083. ucontrol->value.enumerated.item[0] =
  2084. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2085. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2086. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2087. ucontrol->value.enumerated.item[0]);
  2088. }
  2089. return ret;
  2090. }
  2091. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2092. struct snd_ctl_elem_value *ucontrol)
  2093. {
  2094. struct tdm_port port;
  2095. int ret = tdm_get_port_idx(kcontrol, &port);
  2096. if (ret) {
  2097. pr_err("%s: unsupported control: %s",
  2098. __func__, kcontrol->id.name);
  2099. } else {
  2100. tdm_tx_cfg[port.mode][port.channel].channels =
  2101. ucontrol->value.enumerated.item[0] + 1;
  2102. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2103. tdm_tx_cfg[port.mode][port.channel].channels,
  2104. ucontrol->value.enumerated.item[0] + 1);
  2105. }
  2106. return ret;
  2107. }
  2108. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2109. {
  2110. int idx;
  2111. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2112. sizeof("PRIM_AUX_PCM")))
  2113. idx = PRIM_AUX_PCM;
  2114. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2115. sizeof("SEC_AUX_PCM")))
  2116. idx = SEC_AUX_PCM;
  2117. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2118. sizeof("TERT_AUX_PCM")))
  2119. idx = TERT_AUX_PCM;
  2120. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2121. sizeof("QUAT_AUX_PCM")))
  2122. idx = QUAT_AUX_PCM;
  2123. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2124. sizeof("QUIN_AUX_PCM")))
  2125. idx = QUIN_AUX_PCM;
  2126. else {
  2127. pr_err("%s: unsupported port: %s",
  2128. __func__, kcontrol->id.name);
  2129. idx = -EINVAL;
  2130. }
  2131. return idx;
  2132. }
  2133. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2134. struct snd_ctl_elem_value *ucontrol)
  2135. {
  2136. int idx = aux_pcm_get_port_idx(kcontrol);
  2137. if (idx < 0)
  2138. return idx;
  2139. aux_pcm_rx_cfg[idx].sample_rate =
  2140. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2141. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2142. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2143. ucontrol->value.enumerated.item[0]);
  2144. return 0;
  2145. }
  2146. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2147. struct snd_ctl_elem_value *ucontrol)
  2148. {
  2149. int idx = aux_pcm_get_port_idx(kcontrol);
  2150. if (idx < 0)
  2151. return idx;
  2152. ucontrol->value.enumerated.item[0] =
  2153. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2154. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2155. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2156. ucontrol->value.enumerated.item[0]);
  2157. return 0;
  2158. }
  2159. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2160. struct snd_ctl_elem_value *ucontrol)
  2161. {
  2162. int idx = aux_pcm_get_port_idx(kcontrol);
  2163. if (idx < 0)
  2164. return idx;
  2165. aux_pcm_tx_cfg[idx].sample_rate =
  2166. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2167. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2168. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2169. ucontrol->value.enumerated.item[0]);
  2170. return 0;
  2171. }
  2172. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2173. struct snd_ctl_elem_value *ucontrol)
  2174. {
  2175. int idx = aux_pcm_get_port_idx(kcontrol);
  2176. if (idx < 0)
  2177. return idx;
  2178. ucontrol->value.enumerated.item[0] =
  2179. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2180. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2181. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2182. ucontrol->value.enumerated.item[0]);
  2183. return 0;
  2184. }
  2185. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2186. {
  2187. int idx;
  2188. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2189. sizeof("PRIM_MI2S_RX")))
  2190. idx = PRIM_MI2S;
  2191. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2192. sizeof("SEC_MI2S_RX")))
  2193. idx = SEC_MI2S;
  2194. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2195. sizeof("TERT_MI2S_RX")))
  2196. idx = TERT_MI2S;
  2197. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2198. sizeof("QUAT_MI2S_RX")))
  2199. idx = QUAT_MI2S;
  2200. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2201. sizeof("QUIN_MI2S_RX")))
  2202. idx = QUIN_MI2S;
  2203. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2204. sizeof("PRIM_MI2S_TX")))
  2205. idx = PRIM_MI2S;
  2206. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2207. sizeof("SEC_MI2S_TX")))
  2208. idx = SEC_MI2S;
  2209. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2210. sizeof("TERT_MI2S_TX")))
  2211. idx = TERT_MI2S;
  2212. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2213. sizeof("QUAT_MI2S_TX")))
  2214. idx = QUAT_MI2S;
  2215. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2216. sizeof("QUIN_MI2S_TX")))
  2217. idx = QUIN_MI2S;
  2218. else {
  2219. pr_err("%s: unsupported channel: %s",
  2220. __func__, kcontrol->id.name);
  2221. idx = -EINVAL;
  2222. }
  2223. return idx;
  2224. }
  2225. static int mi2s_get_sample_rate_val(int sample_rate)
  2226. {
  2227. int sample_rate_val;
  2228. switch (sample_rate) {
  2229. case SAMPLING_RATE_8KHZ:
  2230. sample_rate_val = 0;
  2231. break;
  2232. case SAMPLING_RATE_11P025KHZ:
  2233. sample_rate_val = 1;
  2234. break;
  2235. case SAMPLING_RATE_16KHZ:
  2236. sample_rate_val = 2;
  2237. break;
  2238. case SAMPLING_RATE_22P05KHZ:
  2239. sample_rate_val = 3;
  2240. break;
  2241. case SAMPLING_RATE_32KHZ:
  2242. sample_rate_val = 4;
  2243. break;
  2244. case SAMPLING_RATE_44P1KHZ:
  2245. sample_rate_val = 5;
  2246. break;
  2247. case SAMPLING_RATE_48KHZ:
  2248. sample_rate_val = 6;
  2249. break;
  2250. case SAMPLING_RATE_96KHZ:
  2251. sample_rate_val = 7;
  2252. break;
  2253. case SAMPLING_RATE_192KHZ:
  2254. sample_rate_val = 8;
  2255. break;
  2256. default:
  2257. sample_rate_val = 6;
  2258. break;
  2259. }
  2260. return sample_rate_val;
  2261. }
  2262. static int mi2s_get_sample_rate(int value)
  2263. {
  2264. int sample_rate;
  2265. switch (value) {
  2266. case 0:
  2267. sample_rate = SAMPLING_RATE_8KHZ;
  2268. break;
  2269. case 1:
  2270. sample_rate = SAMPLING_RATE_11P025KHZ;
  2271. break;
  2272. case 2:
  2273. sample_rate = SAMPLING_RATE_16KHZ;
  2274. break;
  2275. case 3:
  2276. sample_rate = SAMPLING_RATE_22P05KHZ;
  2277. break;
  2278. case 4:
  2279. sample_rate = SAMPLING_RATE_32KHZ;
  2280. break;
  2281. case 5:
  2282. sample_rate = SAMPLING_RATE_44P1KHZ;
  2283. break;
  2284. case 6:
  2285. sample_rate = SAMPLING_RATE_48KHZ;
  2286. break;
  2287. case 7:
  2288. sample_rate = SAMPLING_RATE_96KHZ;
  2289. break;
  2290. case 8:
  2291. sample_rate = SAMPLING_RATE_192KHZ;
  2292. break;
  2293. default:
  2294. sample_rate = SAMPLING_RATE_48KHZ;
  2295. break;
  2296. }
  2297. return sample_rate;
  2298. }
  2299. static int mi2s_auxpcm_get_format(int value)
  2300. {
  2301. int format;
  2302. switch (value) {
  2303. case 0:
  2304. format = SNDRV_PCM_FORMAT_S16_LE;
  2305. break;
  2306. case 1:
  2307. format = SNDRV_PCM_FORMAT_S24_LE;
  2308. break;
  2309. case 2:
  2310. format = SNDRV_PCM_FORMAT_S24_3LE;
  2311. break;
  2312. case 3:
  2313. format = SNDRV_PCM_FORMAT_S32_LE;
  2314. break;
  2315. default:
  2316. format = SNDRV_PCM_FORMAT_S16_LE;
  2317. break;
  2318. }
  2319. return format;
  2320. }
  2321. static int mi2s_auxpcm_get_format_value(int format)
  2322. {
  2323. int value;
  2324. switch (format) {
  2325. case SNDRV_PCM_FORMAT_S16_LE:
  2326. value = 0;
  2327. break;
  2328. case SNDRV_PCM_FORMAT_S24_LE:
  2329. value = 1;
  2330. break;
  2331. case SNDRV_PCM_FORMAT_S24_3LE:
  2332. value = 2;
  2333. break;
  2334. case SNDRV_PCM_FORMAT_S32_LE:
  2335. value = 3;
  2336. break;
  2337. default:
  2338. value = 0;
  2339. break;
  2340. }
  2341. return value;
  2342. }
  2343. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2344. struct snd_ctl_elem_value *ucontrol)
  2345. {
  2346. int idx = mi2s_get_port_idx(kcontrol);
  2347. if (idx < 0)
  2348. return idx;
  2349. mi2s_rx_cfg[idx].sample_rate =
  2350. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2351. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2352. idx, mi2s_rx_cfg[idx].sample_rate,
  2353. ucontrol->value.enumerated.item[0]);
  2354. return 0;
  2355. }
  2356. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2357. struct snd_ctl_elem_value *ucontrol)
  2358. {
  2359. int idx = mi2s_get_port_idx(kcontrol);
  2360. if (idx < 0)
  2361. return idx;
  2362. ucontrol->value.enumerated.item[0] =
  2363. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2364. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2365. idx, mi2s_rx_cfg[idx].sample_rate,
  2366. ucontrol->value.enumerated.item[0]);
  2367. return 0;
  2368. }
  2369. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2370. struct snd_ctl_elem_value *ucontrol)
  2371. {
  2372. int idx = mi2s_get_port_idx(kcontrol);
  2373. if (idx < 0)
  2374. return idx;
  2375. mi2s_tx_cfg[idx].sample_rate =
  2376. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2377. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2378. idx, mi2s_tx_cfg[idx].sample_rate,
  2379. ucontrol->value.enumerated.item[0]);
  2380. return 0;
  2381. }
  2382. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2383. struct snd_ctl_elem_value *ucontrol)
  2384. {
  2385. int idx = mi2s_get_port_idx(kcontrol);
  2386. if (idx < 0)
  2387. return idx;
  2388. ucontrol->value.enumerated.item[0] =
  2389. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2390. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2391. idx, mi2s_tx_cfg[idx].sample_rate,
  2392. ucontrol->value.enumerated.item[0]);
  2393. return 0;
  2394. }
  2395. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2396. struct snd_ctl_elem_value *ucontrol)
  2397. {
  2398. int idx = mi2s_get_port_idx(kcontrol);
  2399. if (idx < 0)
  2400. return idx;
  2401. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2402. idx, mi2s_rx_cfg[idx].channels);
  2403. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2404. return 0;
  2405. }
  2406. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2407. struct snd_ctl_elem_value *ucontrol)
  2408. {
  2409. int idx = mi2s_get_port_idx(kcontrol);
  2410. if (idx < 0)
  2411. return idx;
  2412. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2413. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2414. idx, mi2s_rx_cfg[idx].channels);
  2415. return 1;
  2416. }
  2417. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2418. struct snd_ctl_elem_value *ucontrol)
  2419. {
  2420. int idx = mi2s_get_port_idx(kcontrol);
  2421. if (idx < 0)
  2422. return idx;
  2423. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2424. idx, mi2s_tx_cfg[idx].channels);
  2425. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2426. return 0;
  2427. }
  2428. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2429. struct snd_ctl_elem_value *ucontrol)
  2430. {
  2431. int idx = mi2s_get_port_idx(kcontrol);
  2432. if (idx < 0)
  2433. return idx;
  2434. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2435. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2436. idx, mi2s_tx_cfg[idx].channels);
  2437. return 1;
  2438. }
  2439. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2440. struct snd_ctl_elem_value *ucontrol)
  2441. {
  2442. int idx = mi2s_get_port_idx(kcontrol);
  2443. if (idx < 0)
  2444. return idx;
  2445. ucontrol->value.enumerated.item[0] =
  2446. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2447. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2448. idx, mi2s_rx_cfg[idx].bit_format,
  2449. ucontrol->value.enumerated.item[0]);
  2450. return 0;
  2451. }
  2452. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2453. struct snd_ctl_elem_value *ucontrol)
  2454. {
  2455. int idx = mi2s_get_port_idx(kcontrol);
  2456. if (idx < 0)
  2457. return idx;
  2458. mi2s_rx_cfg[idx].bit_format =
  2459. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2460. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2461. idx, mi2s_rx_cfg[idx].bit_format,
  2462. ucontrol->value.enumerated.item[0]);
  2463. return 0;
  2464. }
  2465. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2466. struct snd_ctl_elem_value *ucontrol)
  2467. {
  2468. int idx = mi2s_get_port_idx(kcontrol);
  2469. if (idx < 0)
  2470. return idx;
  2471. ucontrol->value.enumerated.item[0] =
  2472. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2473. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2474. idx, mi2s_tx_cfg[idx].bit_format,
  2475. ucontrol->value.enumerated.item[0]);
  2476. return 0;
  2477. }
  2478. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2479. struct snd_ctl_elem_value *ucontrol)
  2480. {
  2481. int idx = mi2s_get_port_idx(kcontrol);
  2482. if (idx < 0)
  2483. return idx;
  2484. mi2s_tx_cfg[idx].bit_format =
  2485. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2486. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2487. idx, mi2s_tx_cfg[idx].bit_format,
  2488. ucontrol->value.enumerated.item[0]);
  2489. return 0;
  2490. }
  2491. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  2492. struct snd_ctl_elem_value *ucontrol)
  2493. {
  2494. int idx = aux_pcm_get_port_idx(kcontrol);
  2495. if (idx < 0)
  2496. return idx;
  2497. ucontrol->value.enumerated.item[0] =
  2498. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  2499. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2500. idx, aux_pcm_rx_cfg[idx].bit_format,
  2501. ucontrol->value.enumerated.item[0]);
  2502. return 0;
  2503. }
  2504. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  2505. struct snd_ctl_elem_value *ucontrol)
  2506. {
  2507. int idx = aux_pcm_get_port_idx(kcontrol);
  2508. if (idx < 0)
  2509. return idx;
  2510. aux_pcm_rx_cfg[idx].bit_format =
  2511. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2512. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2513. idx, aux_pcm_rx_cfg[idx].bit_format,
  2514. ucontrol->value.enumerated.item[0]);
  2515. return 0;
  2516. }
  2517. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  2518. struct snd_ctl_elem_value *ucontrol)
  2519. {
  2520. int idx = aux_pcm_get_port_idx(kcontrol);
  2521. if (idx < 0)
  2522. return idx;
  2523. ucontrol->value.enumerated.item[0] =
  2524. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  2525. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2526. idx, aux_pcm_tx_cfg[idx].bit_format,
  2527. ucontrol->value.enumerated.item[0]);
  2528. return 0;
  2529. }
  2530. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  2531. struct snd_ctl_elem_value *ucontrol)
  2532. {
  2533. int idx = aux_pcm_get_port_idx(kcontrol);
  2534. if (idx < 0)
  2535. return idx;
  2536. aux_pcm_tx_cfg[idx].bit_format =
  2537. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2538. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2539. idx, aux_pcm_tx_cfg[idx].bit_format,
  2540. ucontrol->value.enumerated.item[0]);
  2541. return 0;
  2542. }
  2543. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  2544. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  2545. slim_rx_ch_get, slim_rx_ch_put),
  2546. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  2547. slim_rx_ch_get, slim_rx_ch_put),
  2548. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  2549. slim_tx_ch_get, slim_tx_ch_put),
  2550. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  2551. slim_tx_ch_get, slim_tx_ch_put),
  2552. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  2553. slim_rx_ch_get, slim_rx_ch_put),
  2554. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  2555. slim_rx_ch_get, slim_rx_ch_put),
  2556. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  2557. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2558. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  2559. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2560. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  2561. slim_rx_bit_format_get, slim_rx_bit_format_put),
  2562. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  2563. slim_tx_bit_format_get, slim_tx_bit_format_put),
  2564. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  2565. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2566. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  2567. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2568. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  2569. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  2570. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  2571. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2572. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  2573. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  2574. };
  2575. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  2576. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2577. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2578. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2579. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2580. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2581. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2582. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2583. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2584. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  2585. va_cdc_dma_tx_0_sample_rate,
  2586. cdc_dma_tx_sample_rate_get,
  2587. cdc_dma_tx_sample_rate_put),
  2588. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  2589. va_cdc_dma_tx_1_sample_rate,
  2590. cdc_dma_tx_sample_rate_get,
  2591. cdc_dma_tx_sample_rate_put),
  2592. };
  2593. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  2594. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  2595. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  2596. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2597. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2598. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2599. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2600. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2601. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2602. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2603. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2604. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2605. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2606. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2607. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2608. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2609. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2610. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2611. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2612. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2613. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2614. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2615. wsa_cdc_dma_rx_0_sample_rate,
  2616. cdc_dma_rx_sample_rate_get,
  2617. cdc_dma_rx_sample_rate_put),
  2618. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2619. wsa_cdc_dma_rx_1_sample_rate,
  2620. cdc_dma_rx_sample_rate_get,
  2621. cdc_dma_rx_sample_rate_put),
  2622. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2623. wsa_cdc_dma_tx_0_sample_rate,
  2624. cdc_dma_tx_sample_rate_get,
  2625. cdc_dma_tx_sample_rate_put),
  2626. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2627. wsa_cdc_dma_tx_1_sample_rate,
  2628. cdc_dma_tx_sample_rate_get,
  2629. cdc_dma_tx_sample_rate_put),
  2630. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2631. wsa_cdc_dma_tx_2_sample_rate,
  2632. cdc_dma_tx_sample_rate_get,
  2633. cdc_dma_tx_sample_rate_put),
  2634. };
  2635. static const struct snd_kcontrol_new msm_snd_controls[] = {
  2636. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  2637. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  2638. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  2639. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  2640. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  2641. proxy_rx_ch_get, proxy_rx_ch_put),
  2642. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  2643. usb_audio_rx_format_get, usb_audio_rx_format_put),
  2644. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  2645. usb_audio_tx_format_get, usb_audio_tx_format_put),
  2646. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  2647. msm_bt_sample_rate_get,
  2648. msm_bt_sample_rate_put),
  2649. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  2650. usb_audio_rx_sample_rate_get,
  2651. usb_audio_rx_sample_rate_put),
  2652. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  2653. usb_audio_tx_sample_rate_get,
  2654. usb_audio_tx_sample_rate_put),
  2655. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2656. tdm_rx_sample_rate_get,
  2657. tdm_rx_sample_rate_put),
  2658. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2659. tdm_tx_sample_rate_get,
  2660. tdm_tx_sample_rate_put),
  2661. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  2662. tdm_rx_format_get,
  2663. tdm_rx_format_put),
  2664. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  2665. tdm_tx_format_get,
  2666. tdm_tx_format_put),
  2667. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  2668. tdm_rx_ch_get,
  2669. tdm_rx_ch_put),
  2670. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  2671. tdm_tx_ch_get,
  2672. tdm_tx_ch_put),
  2673. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2674. tdm_rx_sample_rate_get,
  2675. tdm_rx_sample_rate_put),
  2676. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2677. tdm_tx_sample_rate_get,
  2678. tdm_tx_sample_rate_put),
  2679. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  2680. tdm_rx_format_get,
  2681. tdm_rx_format_put),
  2682. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  2683. tdm_tx_format_get,
  2684. tdm_tx_format_put),
  2685. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  2686. tdm_rx_ch_get,
  2687. tdm_rx_ch_put),
  2688. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  2689. tdm_tx_ch_get,
  2690. tdm_tx_ch_put),
  2691. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2692. tdm_rx_sample_rate_get,
  2693. tdm_rx_sample_rate_put),
  2694. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2695. tdm_tx_sample_rate_get,
  2696. tdm_tx_sample_rate_put),
  2697. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  2698. tdm_rx_format_get,
  2699. tdm_rx_format_put),
  2700. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  2701. tdm_tx_format_get,
  2702. tdm_tx_format_put),
  2703. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  2704. tdm_rx_ch_get,
  2705. tdm_rx_ch_put),
  2706. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  2707. tdm_tx_ch_get,
  2708. tdm_tx_ch_put),
  2709. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2710. tdm_rx_sample_rate_get,
  2711. tdm_rx_sample_rate_put),
  2712. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2713. tdm_tx_sample_rate_get,
  2714. tdm_tx_sample_rate_put),
  2715. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  2716. tdm_rx_format_get,
  2717. tdm_rx_format_put),
  2718. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  2719. tdm_tx_format_get,
  2720. tdm_tx_format_put),
  2721. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  2722. tdm_rx_ch_get,
  2723. tdm_rx_ch_put),
  2724. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  2725. tdm_tx_ch_get,
  2726. tdm_tx_ch_put),
  2727. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  2728. tdm_rx_sample_rate_get,
  2729. tdm_rx_sample_rate_put),
  2730. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  2731. tdm_tx_sample_rate_get,
  2732. tdm_tx_sample_rate_put),
  2733. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  2734. tdm_rx_format_get,
  2735. tdm_rx_format_put),
  2736. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  2737. tdm_tx_format_get,
  2738. tdm_tx_format_put),
  2739. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  2740. tdm_rx_ch_get,
  2741. tdm_rx_ch_put),
  2742. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  2743. tdm_tx_ch_get,
  2744. tdm_tx_ch_put),
  2745. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  2746. aux_pcm_rx_sample_rate_get,
  2747. aux_pcm_rx_sample_rate_put),
  2748. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  2749. aux_pcm_rx_sample_rate_get,
  2750. aux_pcm_rx_sample_rate_put),
  2751. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  2752. aux_pcm_rx_sample_rate_get,
  2753. aux_pcm_rx_sample_rate_put),
  2754. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  2755. aux_pcm_rx_sample_rate_get,
  2756. aux_pcm_rx_sample_rate_put),
  2757. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  2758. aux_pcm_rx_sample_rate_get,
  2759. aux_pcm_rx_sample_rate_put),
  2760. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  2761. aux_pcm_tx_sample_rate_get,
  2762. aux_pcm_tx_sample_rate_put),
  2763. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  2764. aux_pcm_tx_sample_rate_get,
  2765. aux_pcm_tx_sample_rate_put),
  2766. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  2767. aux_pcm_tx_sample_rate_get,
  2768. aux_pcm_tx_sample_rate_put),
  2769. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  2770. aux_pcm_tx_sample_rate_get,
  2771. aux_pcm_tx_sample_rate_put),
  2772. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  2773. aux_pcm_tx_sample_rate_get,
  2774. aux_pcm_tx_sample_rate_put),
  2775. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  2776. mi2s_rx_sample_rate_get,
  2777. mi2s_rx_sample_rate_put),
  2778. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  2779. mi2s_rx_sample_rate_get,
  2780. mi2s_rx_sample_rate_put),
  2781. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  2782. mi2s_rx_sample_rate_get,
  2783. mi2s_rx_sample_rate_put),
  2784. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  2785. mi2s_rx_sample_rate_get,
  2786. mi2s_rx_sample_rate_put),
  2787. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  2788. mi2s_rx_sample_rate_get,
  2789. mi2s_rx_sample_rate_put),
  2790. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  2791. mi2s_tx_sample_rate_get,
  2792. mi2s_tx_sample_rate_put),
  2793. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  2794. mi2s_tx_sample_rate_get,
  2795. mi2s_tx_sample_rate_put),
  2796. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  2797. mi2s_tx_sample_rate_get,
  2798. mi2s_tx_sample_rate_put),
  2799. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  2800. mi2s_tx_sample_rate_get,
  2801. mi2s_tx_sample_rate_put),
  2802. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  2803. mi2s_tx_sample_rate_get,
  2804. mi2s_tx_sample_rate_put),
  2805. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  2806. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2807. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  2808. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2809. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  2810. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2811. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  2812. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2813. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  2814. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2815. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  2816. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2817. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  2818. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2819. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  2820. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2821. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  2822. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  2823. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  2824. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  2825. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  2826. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2827. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  2828. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2829. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  2830. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2831. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  2832. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2833. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  2834. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2835. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  2836. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2837. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  2838. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2839. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  2840. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2841. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  2842. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  2843. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  2844. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  2845. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  2846. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2847. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  2848. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2849. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  2850. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2851. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  2852. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2853. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2854. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2855. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2856. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2857. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  2858. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2859. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  2860. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2861. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  2862. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  2863. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  2864. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  2865. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  2866. msm_snd_vad_cfg_put),
  2867. };
  2868. static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec,
  2869. int enable, bool dapm)
  2870. {
  2871. int ret = 0;
  2872. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2873. ret = tasha_cdc_mclk_enable(codec, enable, dapm);
  2874. } else {
  2875. dev_err(codec->dev, "%s: unknown codec to enable ext clk\n",
  2876. __func__);
  2877. ret = -EINVAL;
  2878. }
  2879. return ret;
  2880. }
  2881. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec,
  2882. int enable, bool dapm)
  2883. {
  2884. int ret = 0;
  2885. if (!strcmp(dev_name(codec->dev), "tasha_codec")) {
  2886. ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm);
  2887. } else {
  2888. dev_err(codec->dev, "%s: unknown codec to enable TX ext clk\n",
  2889. __func__);
  2890. ret = -EINVAL;
  2891. }
  2892. return ret;
  2893. }
  2894. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  2895. struct snd_kcontrol *kcontrol, int event)
  2896. {
  2897. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2898. pr_debug("%s: event = %d\n", __func__, event);
  2899. switch (event) {
  2900. case SND_SOC_DAPM_PRE_PMU:
  2901. return msm_snd_enable_codec_ext_tx_clk(codec, 1, true);
  2902. case SND_SOC_DAPM_POST_PMD:
  2903. return msm_snd_enable_codec_ext_tx_clk(codec, 0, true);
  2904. }
  2905. return 0;
  2906. }
  2907. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  2908. struct snd_kcontrol *kcontrol, int event)
  2909. {
  2910. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2911. pr_debug("%s: event = %d\n", __func__, event);
  2912. switch (event) {
  2913. case SND_SOC_DAPM_PRE_PMU:
  2914. return msm_snd_enable_codec_ext_clk(codec, 1, true);
  2915. case SND_SOC_DAPM_POST_PMD:
  2916. return msm_snd_enable_codec_ext_clk(codec, 0, true);
  2917. }
  2918. return 0;
  2919. }
  2920. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  2921. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  2922. msm_mclk_event,
  2923. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2924. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  2925. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2926. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  2927. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  2928. };
  2929. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  2930. struct snd_kcontrol *kcontrol, int event)
  2931. {
  2932. struct msm_asoc_mach_data *pdata = NULL;
  2933. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2934. int ret = 0;
  2935. uint32_t dmic_idx;
  2936. int *dmic_gpio_cnt;
  2937. struct device_node *dmic_gpio;
  2938. char *wname;
  2939. wname = strpbrk(w->name, "01234567");
  2940. if (!wname) {
  2941. dev_err(codec->dev, "%s: widget not found\n", __func__);
  2942. return -EINVAL;
  2943. }
  2944. ret = kstrtouint(wname, 10, &dmic_idx);
  2945. if (ret < 0) {
  2946. dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n",
  2947. __func__);
  2948. return -EINVAL;
  2949. }
  2950. pdata = snd_soc_card_get_drvdata(codec->component.card);
  2951. switch (dmic_idx) {
  2952. case 0:
  2953. case 1:
  2954. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  2955. dmic_gpio = pdata->dmic_01_gpio_p;
  2956. break;
  2957. case 2:
  2958. case 3:
  2959. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  2960. dmic_gpio = pdata->dmic_23_gpio_p;
  2961. break;
  2962. case 4:
  2963. case 5:
  2964. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  2965. dmic_gpio = pdata->dmic_45_gpio_p;
  2966. break;
  2967. case 6:
  2968. case 7:
  2969. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  2970. dmic_gpio = pdata->dmic_67_gpio_p;
  2971. break;
  2972. default:
  2973. dev_err(codec->dev, "%s: Invalid DMIC Selection\n",
  2974. __func__);
  2975. return -EINVAL;
  2976. }
  2977. dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  2978. __func__, event, dmic_idx, *dmic_gpio_cnt);
  2979. switch (event) {
  2980. case SND_SOC_DAPM_PRE_PMU:
  2981. (*dmic_gpio_cnt)++;
  2982. if (*dmic_gpio_cnt == 1) {
  2983. ret = msm_cdc_pinctrl_select_active_state(
  2984. dmic_gpio);
  2985. if (ret < 0) {
  2986. dev_err(codec->dev, "%s: gpio set cannot be activated %sd\n",
  2987. __func__, "dmic_gpio");
  2988. return ret;
  2989. }
  2990. }
  2991. break;
  2992. case SND_SOC_DAPM_POST_PMD:
  2993. (*dmic_gpio_cnt)--;
  2994. if (*dmic_gpio_cnt == 0) {
  2995. ret = msm_cdc_pinctrl_select_sleep_state(
  2996. dmic_gpio);
  2997. if (ret < 0) {
  2998. dev_err(codec->dev, "%s: gpio set cannot be de-activated %sd\n",
  2999. __func__, "dmic_gpio");
  3000. return ret;
  3001. }
  3002. }
  3003. break;
  3004. default:
  3005. dev_err(codec->dev, "%s: invalid DAPM event %d\n",
  3006. __func__, event);
  3007. return -EINVAL;
  3008. }
  3009. return 0;
  3010. }
  3011. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  3012. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  3013. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  3014. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  3015. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  3016. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  3017. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  3018. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  3019. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  3020. };
  3021. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  3022. };
  3023. static inline int param_is_mask(int p)
  3024. {
  3025. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  3026. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  3027. }
  3028. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  3029. int n)
  3030. {
  3031. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  3032. }
  3033. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  3034. unsigned int bit)
  3035. {
  3036. if (bit >= SNDRV_MASK_MAX)
  3037. return;
  3038. if (param_is_mask(n)) {
  3039. struct snd_mask *m = param_to_mask(p, n);
  3040. m->bits[0] = 0;
  3041. m->bits[1] = 0;
  3042. m->bits[bit >> 5] |= (1 << (bit & 31));
  3043. }
  3044. }
  3045. static int msm_slim_get_ch_from_beid(int32_t be_id)
  3046. {
  3047. int ch_id = 0;
  3048. switch (be_id) {
  3049. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3050. ch_id = SLIM_RX_0;
  3051. break;
  3052. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3053. ch_id = SLIM_RX_1;
  3054. break;
  3055. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3056. ch_id = SLIM_RX_2;
  3057. break;
  3058. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3059. ch_id = SLIM_RX_3;
  3060. break;
  3061. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3062. ch_id = SLIM_RX_4;
  3063. break;
  3064. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3065. ch_id = SLIM_RX_6;
  3066. break;
  3067. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3068. ch_id = SLIM_TX_0;
  3069. break;
  3070. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3071. ch_id = SLIM_TX_3;
  3072. break;
  3073. default:
  3074. ch_id = SLIM_RX_0;
  3075. break;
  3076. }
  3077. return ch_id;
  3078. }
  3079. static int msm_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  3080. {
  3081. *port_id = 0xFFFF;
  3082. switch (be_id) {
  3083. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3084. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  3085. break;
  3086. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3087. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  3088. break;
  3089. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3090. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  3091. break;
  3092. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3093. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  3094. break;
  3095. default:
  3096. return -EINVAL;
  3097. }
  3098. return 0;
  3099. }
  3100. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  3101. {
  3102. int idx = 0;
  3103. switch (be_id) {
  3104. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3105. idx = WSA_CDC_DMA_RX_0;
  3106. break;
  3107. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3108. idx = WSA_CDC_DMA_TX_0;
  3109. break;
  3110. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3111. idx = WSA_CDC_DMA_RX_1;
  3112. break;
  3113. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3114. idx = WSA_CDC_DMA_TX_1;
  3115. break;
  3116. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3117. idx = WSA_CDC_DMA_TX_2;
  3118. break;
  3119. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3120. idx = VA_CDC_DMA_TX_0;
  3121. break;
  3122. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3123. idx = VA_CDC_DMA_TX_1;
  3124. break;
  3125. default:
  3126. idx = VA_CDC_DMA_TX_0;
  3127. break;
  3128. }
  3129. return idx;
  3130. }
  3131. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3132. struct snd_pcm_hw_params *params)
  3133. {
  3134. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3135. struct snd_interval *rate = hw_param_interval(params,
  3136. SNDRV_PCM_HW_PARAM_RATE);
  3137. struct snd_interval *channels = hw_param_interval(params,
  3138. SNDRV_PCM_HW_PARAM_CHANNELS);
  3139. int rc = 0;
  3140. int idx;
  3141. void *config = NULL;
  3142. struct snd_soc_codec *codec = NULL;
  3143. pr_debug("%s: format = %d, rate = %d\n",
  3144. __func__, params_format(params), params_rate(params));
  3145. switch (dai_link->id) {
  3146. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  3147. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  3148. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  3149. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  3150. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  3151. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  3152. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3153. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3154. slim_rx_cfg[idx].bit_format);
  3155. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  3156. channels->min = channels->max = slim_rx_cfg[idx].channels;
  3157. break;
  3158. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  3159. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  3160. idx = msm_slim_get_ch_from_beid(dai_link->id);
  3161. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3162. slim_tx_cfg[idx].bit_format);
  3163. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  3164. channels->min = channels->max = slim_tx_cfg[idx].channels;
  3165. break;
  3166. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  3167. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3168. slim_tx_cfg[1].bit_format);
  3169. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  3170. channels->min = channels->max = slim_tx_cfg[1].channels;
  3171. break;
  3172. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  3173. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3174. SNDRV_PCM_FORMAT_S32_LE);
  3175. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3176. channels->min = channels->max = msm_vi_feed_tx_ch;
  3177. break;
  3178. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  3179. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3180. slim_rx_cfg[5].bit_format);
  3181. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  3182. channels->min = channels->max = slim_rx_cfg[5].channels;
  3183. break;
  3184. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  3185. codec = rtd->codec;
  3186. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  3187. channels->min = channels->max = 1;
  3188. config = msm_codec_fn.get_afe_config_fn(codec,
  3189. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  3190. if (config) {
  3191. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  3192. config, SLIMBUS_5_TX);
  3193. if (rc)
  3194. pr_err("%s: Failed to set slimbus slave port config %d\n",
  3195. __func__, rc);
  3196. }
  3197. break;
  3198. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3199. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3200. slim_rx_cfg[SLIM_RX_7].bit_format);
  3201. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3202. channels->min = channels->max =
  3203. slim_rx_cfg[SLIM_RX_7].channels;
  3204. break;
  3205. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3206. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3207. channels->min = channels->max =
  3208. slim_tx_cfg[SLIM_TX_7].channels;
  3209. break;
  3210. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3211. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3212. channels->min = channels->max =
  3213. slim_tx_cfg[SLIM_TX_8].channels;
  3214. break;
  3215. case MSM_BACKEND_DAI_USB_RX:
  3216. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3217. usb_rx_cfg.bit_format);
  3218. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3219. channels->min = channels->max = usb_rx_cfg.channels;
  3220. break;
  3221. case MSM_BACKEND_DAI_USB_TX:
  3222. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3223. usb_tx_cfg.bit_format);
  3224. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3225. channels->min = channels->max = usb_tx_cfg.channels;
  3226. break;
  3227. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3228. channels->min = channels->max = proxy_rx_cfg.channels;
  3229. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3230. break;
  3231. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3232. channels->min = channels->max =
  3233. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3234. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3235. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3236. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3237. break;
  3238. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3239. channels->min = channels->max =
  3240. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3241. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3242. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3243. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3244. break;
  3245. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3246. channels->min = channels->max =
  3247. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3248. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3249. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3250. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3251. break;
  3252. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3253. channels->min = channels->max =
  3254. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3255. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3256. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3257. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3258. break;
  3259. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3260. channels->min = channels->max =
  3261. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3262. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3263. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3264. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3265. break;
  3266. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3267. channels->min = channels->max =
  3268. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3269. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3270. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3271. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3272. break;
  3273. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3274. channels->min = channels->max =
  3275. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3276. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3277. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3278. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3279. break;
  3280. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3281. channels->min = channels->max =
  3282. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3283. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3284. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3285. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3286. break;
  3287. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3288. channels->min = channels->max =
  3289. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3290. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3291. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3292. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3293. break;
  3294. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3295. channels->min = channels->max =
  3296. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3297. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3298. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3299. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3300. break;
  3301. case MSM_BACKEND_DAI_AUXPCM_RX:
  3302. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3303. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3304. rate->min = rate->max =
  3305. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3306. channels->min = channels->max =
  3307. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3308. break;
  3309. case MSM_BACKEND_DAI_AUXPCM_TX:
  3310. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3311. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3312. rate->min = rate->max =
  3313. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3314. channels->min = channels->max =
  3315. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3316. break;
  3317. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3318. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3319. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3320. rate->min = rate->max =
  3321. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3322. channels->min = channels->max =
  3323. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3324. break;
  3325. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3326. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3327. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3328. rate->min = rate->max =
  3329. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3330. channels->min = channels->max =
  3331. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3332. break;
  3333. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3334. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3335. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3336. rate->min = rate->max =
  3337. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3338. channels->min = channels->max =
  3339. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3340. break;
  3341. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3342. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3343. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3344. rate->min = rate->max =
  3345. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3346. channels->min = channels->max =
  3347. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3348. break;
  3349. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3350. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3351. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3352. rate->min = rate->max =
  3353. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3354. channels->min = channels->max =
  3355. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3356. break;
  3357. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3358. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3359. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3360. rate->min = rate->max =
  3361. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3362. channels->min = channels->max =
  3363. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3364. break;
  3365. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3366. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3367. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3368. rate->min = rate->max =
  3369. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3370. channels->min = channels->max =
  3371. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3372. break;
  3373. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3374. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3375. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3376. rate->min = rate->max =
  3377. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3378. channels->min = channels->max =
  3379. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3380. break;
  3381. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3382. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3383. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3384. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3385. channels->min = channels->max =
  3386. mi2s_rx_cfg[PRIM_MI2S].channels;
  3387. break;
  3388. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3389. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3390. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3391. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3392. channels->min = channels->max =
  3393. mi2s_tx_cfg[PRIM_MI2S].channels;
  3394. break;
  3395. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3396. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3397. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3398. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3399. channels->min = channels->max =
  3400. mi2s_rx_cfg[SEC_MI2S].channels;
  3401. break;
  3402. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3403. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3404. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3405. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3406. channels->min = channels->max =
  3407. mi2s_tx_cfg[SEC_MI2S].channels;
  3408. break;
  3409. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3410. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3411. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3412. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3413. channels->min = channels->max =
  3414. mi2s_rx_cfg[TERT_MI2S].channels;
  3415. break;
  3416. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3417. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3418. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3419. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3420. channels->min = channels->max =
  3421. mi2s_tx_cfg[TERT_MI2S].channels;
  3422. break;
  3423. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3424. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3425. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3426. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3427. channels->min = channels->max =
  3428. mi2s_rx_cfg[QUAT_MI2S].channels;
  3429. break;
  3430. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3431. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3432. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3433. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3434. channels->min = channels->max =
  3435. mi2s_tx_cfg[QUAT_MI2S].channels;
  3436. break;
  3437. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3438. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3439. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3440. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3441. channels->min = channels->max =
  3442. mi2s_rx_cfg[QUIN_MI2S].channels;
  3443. break;
  3444. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3445. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3446. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3447. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3448. channels->min = channels->max =
  3449. mi2s_tx_cfg[QUIN_MI2S].channels;
  3450. break;
  3451. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3452. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3453. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3454. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3455. cdc_dma_rx_cfg[idx].bit_format);
  3456. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3457. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3458. break;
  3459. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3460. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3461. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3462. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3463. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3464. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3465. cdc_dma_tx_cfg[idx].bit_format);
  3466. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3467. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3468. break;
  3469. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3470. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3471. SNDRV_PCM_FORMAT_S32_LE);
  3472. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3473. channels->min = channels->max = msm_vi_feed_tx_ch;
  3474. break;
  3475. default:
  3476. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3477. break;
  3478. }
  3479. return rc;
  3480. }
  3481. static int msm_afe_set_config(struct snd_soc_codec *codec)
  3482. {
  3483. int ret = 0;
  3484. void *config_data = NULL;
  3485. if (!msm_codec_fn.get_afe_config_fn) {
  3486. dev_err(codec->dev, "%s: codec get afe config not init'ed\n",
  3487. __func__);
  3488. return -EINVAL;
  3489. }
  3490. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3491. AFE_CDC_REGISTERS_CONFIG);
  3492. if (config_data) {
  3493. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  3494. if (ret) {
  3495. dev_err(codec->dev,
  3496. "%s: Failed to set codec registers config %d\n",
  3497. __func__, ret);
  3498. return ret;
  3499. }
  3500. }
  3501. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3502. AFE_CDC_REGISTER_PAGE_CONFIG);
  3503. if (config_data) {
  3504. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  3505. 0);
  3506. if (ret)
  3507. dev_err(codec->dev,
  3508. "%s: Failed to set cdc register page config\n",
  3509. __func__);
  3510. }
  3511. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3512. AFE_SLIMBUS_SLAVE_CONFIG);
  3513. if (config_data) {
  3514. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  3515. if (ret) {
  3516. dev_err(codec->dev,
  3517. "%s: Failed to set slimbus slave config %d\n",
  3518. __func__, ret);
  3519. return ret;
  3520. }
  3521. }
  3522. return 0;
  3523. }
  3524. static void msm_afe_clear_config(void)
  3525. {
  3526. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  3527. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  3528. }
  3529. static int msm_adsp_power_up_config(struct snd_soc_codec *codec,
  3530. struct snd_card *card)
  3531. {
  3532. int ret = 0;
  3533. unsigned long timeout;
  3534. int adsp_ready = 0;
  3535. bool snd_card_online = 0;
  3536. timeout = jiffies +
  3537. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  3538. do {
  3539. if (!snd_card_online) {
  3540. snd_card_online = snd_card_is_online_state(card);
  3541. pr_debug("%s: Sound card is %s\n", __func__,
  3542. snd_card_online ? "Online" : "Offline");
  3543. }
  3544. if (!adsp_ready) {
  3545. adsp_ready = q6core_is_adsp_ready();
  3546. pr_debug("%s: ADSP Audio is %s\n", __func__,
  3547. adsp_ready ? "ready" : "not ready");
  3548. }
  3549. if (snd_card_online && adsp_ready)
  3550. break;
  3551. /*
  3552. * Sound card/ADSP will be coming up after subsystem restart and
  3553. * it might not be fully up when the control reaches
  3554. * here. So, wait for 50msec before checking ADSP state
  3555. */
  3556. msleep(50);
  3557. } while (time_after(timeout, jiffies));
  3558. if (!snd_card_online || !adsp_ready) {
  3559. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  3560. __func__,
  3561. snd_card_online ? "Online" : "Offline",
  3562. adsp_ready ? "ready" : "not ready");
  3563. ret = -ETIMEDOUT;
  3564. goto err;
  3565. }
  3566. ret = msm_afe_set_config(codec);
  3567. if (ret)
  3568. pr_err("%s: Failed to set AFE config. err %d\n",
  3569. __func__, ret);
  3570. return 0;
  3571. err:
  3572. return ret;
  3573. }
  3574. static int qcs405_notifier_service_cb(struct notifier_block *this,
  3575. unsigned long opcode, void *ptr)
  3576. {
  3577. int ret;
  3578. struct snd_soc_card *card = NULL;
  3579. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  3580. struct snd_soc_pcm_runtime *rtd;
  3581. struct snd_soc_codec *codec;
  3582. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  3583. switch (opcode) {
  3584. case AUDIO_NOTIFIER_SERVICE_DOWN:
  3585. /*
  3586. * Use flag to ignore initial boot notifications
  3587. * On initial boot msm_adsp_power_up_config is
  3588. * called on init. There is no need to clear
  3589. * and set the config again on initial boot.
  3590. */
  3591. if (is_initial_boot)
  3592. break;
  3593. msm_afe_clear_config();
  3594. break;
  3595. case AUDIO_NOTIFIER_SERVICE_UP:
  3596. if (is_initial_boot) {
  3597. is_initial_boot = false;
  3598. break;
  3599. }
  3600. if (!spdev)
  3601. return -EINVAL;
  3602. card = platform_get_drvdata(spdev);
  3603. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  3604. if (!rtd) {
  3605. dev_err(card->dev,
  3606. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  3607. __func__, be_dl_name);
  3608. ret = -EINVAL;
  3609. goto err;
  3610. }
  3611. codec = rtd->codec;
  3612. ret = msm_adsp_power_up_config(codec, card->snd_card);
  3613. if (ret < 0) {
  3614. dev_err(card->dev,
  3615. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  3616. __func__, ret);
  3617. goto err;
  3618. }
  3619. break;
  3620. default:
  3621. break;
  3622. }
  3623. err:
  3624. return NOTIFY_OK;
  3625. }
  3626. static struct notifier_block service_nb = {
  3627. .notifier_call = qcs405_notifier_service_cb,
  3628. .priority = -INT_MAX,
  3629. };
  3630. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  3631. {
  3632. int ret = 0;
  3633. void *config_data;
  3634. struct snd_soc_codec *codec = rtd->codec;
  3635. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3636. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3637. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3638. struct snd_card *card;
  3639. struct msm_asoc_mach_data *pdata =
  3640. snd_soc_card_get_drvdata(rtd->card);
  3641. /*
  3642. * Codec SLIMBUS configuration
  3643. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  3644. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  3645. * TX14, TX15, TX16
  3646. */
  3647. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  3648. 151, 152, 153, 154, 155, 156};
  3649. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  3650. 134, 135, 136, 137, 138, 139,
  3651. 140, 141, 142, 143};
  3652. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  3653. rtd->pmdown_time = 0;
  3654. ret = snd_soc_add_codec_controls(codec, msm_snd_sb_controls,
  3655. ARRAY_SIZE(msm_snd_sb_controls));
  3656. if (ret < 0) {
  3657. pr_err("%s: add_codec_controls failed, err %d\n",
  3658. __func__, ret);
  3659. return ret;
  3660. }
  3661. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  3662. ARRAY_SIZE(msm_dapm_widgets));
  3663. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  3664. ARRAY_SIZE(wcd_audio_paths));
  3665. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  3666. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  3667. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  3668. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  3669. snd_soc_dapm_sync(dapm);
  3670. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3671. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3672. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  3673. ret = msm_adsp_power_up_config(codec, rtd->card->snd_card);
  3674. if (ret) {
  3675. dev_err(codec->dev, "%s: Failed to set AFE config %d\n",
  3676. __func__, ret);
  3677. goto err;
  3678. }
  3679. config_data = msm_codec_fn.get_afe_config_fn(codec,
  3680. AFE_AANC_VERSION);
  3681. if (config_data) {
  3682. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  3683. if (ret) {
  3684. dev_err(codec->dev, "%s: Failed to set aanc version %d\n",
  3685. __func__, ret);
  3686. goto err;
  3687. }
  3688. }
  3689. card = rtd->card->snd_card;
  3690. if (!pdata->codec_root)
  3691. pdata->codec_root = snd_info_create_subdir(card->module,
  3692. "codecs", card->proc_root);
  3693. if (!pdata->codec_root) {
  3694. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  3695. __func__);
  3696. ret = 0;
  3697. goto err;
  3698. }
  3699. tasha_codec_info_create_codec_entry(pdata->codec_root, codec);
  3700. codec_reg_done = true;
  3701. return 0;
  3702. err:
  3703. return ret;
  3704. }
  3705. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3706. {
  3707. int ret = 0;
  3708. struct snd_soc_codec *codec = rtd->codec;
  3709. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3710. struct snd_card *card;
  3711. struct msm_asoc_mach_data *pdata =
  3712. snd_soc_card_get_drvdata(rtd->card);
  3713. ret = snd_soc_add_codec_controls(codec, msm_snd_va_controls,
  3714. ARRAY_SIZE(msm_snd_va_controls));
  3715. if (ret < 0) {
  3716. dev_err(codec->dev, "%s: add_codec_controls for va failed, err %d\n",
  3717. __func__, ret);
  3718. return ret;
  3719. }
  3720. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  3721. ARRAY_SIZE(msm_va_dapm_widgets));
  3722. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  3723. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  3724. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  3725. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  3726. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  3727. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  3728. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  3729. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  3730. snd_soc_dapm_sync(dapm);
  3731. card = rtd->card->snd_card;
  3732. if (!pdata->codec_root)
  3733. pdata->codec_root = snd_info_create_subdir(card->module,
  3734. "codecs", card->proc_root);
  3735. if (!pdata->codec_root) {
  3736. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  3737. __func__);
  3738. ret = 0;
  3739. goto done;
  3740. }
  3741. bolero_info_create_codec_entry(pdata->codec_root, codec);
  3742. done:
  3743. return ret;
  3744. }
  3745. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  3746. {
  3747. int ret = 0;
  3748. struct snd_soc_codec *codec = rtd->codec;
  3749. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  3750. struct snd_soc_component *aux_comp;
  3751. struct snd_card *card;
  3752. struct msm_asoc_mach_data *pdata =
  3753. snd_soc_card_get_drvdata(rtd->card);
  3754. ret = snd_soc_add_codec_controls(codec, msm_snd_wsa_controls,
  3755. ARRAY_SIZE(msm_snd_wsa_controls));
  3756. if (ret < 0) {
  3757. dev_err(codec->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  3758. __func__, ret);
  3759. return ret;
  3760. }
  3761. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  3762. ARRAY_SIZE(msm_wsa_dapm_widgets));
  3763. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  3764. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  3765. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  3766. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  3767. snd_soc_dapm_sync(dapm);
  3768. /*
  3769. * Send speaker configuration only for WSA8810.
  3770. * Default configuration is for WSA8815.
  3771. */
  3772. dev_dbg(codec->dev, "%s: Number of aux devices: %d\n",
  3773. __func__, rtd->card->num_aux_devs);
  3774. if (rtd->card->num_aux_devs &&
  3775. !list_empty(&rtd->card->component_dev_list)) {
  3776. aux_comp = list_first_entry(
  3777. &rtd->card->component_dev_list,
  3778. struct snd_soc_component,
  3779. card_aux_list);
  3780. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  3781. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  3782. wsa_macro_set_spkr_mode(rtd->codec,
  3783. WSA_MACRO_SPKR_MODE_1);
  3784. wsa_macro_set_spkr_gain_offset(rtd->codec,
  3785. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  3786. }
  3787. }
  3788. card = rtd->card->snd_card;
  3789. if (!pdata->codec_root)
  3790. pdata->codec_root = snd_info_create_subdir(card->module,
  3791. "codecs", card->proc_root);
  3792. if (!pdata->codec_root) {
  3793. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  3794. __func__);
  3795. ret = 0;
  3796. goto done;
  3797. }
  3798. bolero_info_create_codec_entry(pdata->codec_root, codec);
  3799. done:
  3800. return ret;
  3801. }
  3802. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  3803. {
  3804. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  3805. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
  3806. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3807. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  3808. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  3809. }
  3810. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  3811. struct snd_pcm_hw_params *params)
  3812. {
  3813. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3814. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3815. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3816. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3817. int ret = 0;
  3818. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  3819. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3820. u32 user_set_tx_ch = 0;
  3821. u32 rx_ch_count;
  3822. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3823. ret = snd_soc_dai_get_channel_map(codec_dai,
  3824. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3825. if (ret < 0) {
  3826. pr_err("%s: failed to get codec chan map, err:%d\n",
  3827. __func__, ret);
  3828. goto err;
  3829. }
  3830. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  3831. pr_debug("%s: rx_5_ch=%d\n", __func__,
  3832. slim_rx_cfg[5].channels);
  3833. rx_ch_count = slim_rx_cfg[5].channels;
  3834. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  3835. pr_debug("%s: rx_2_ch=%d\n", __func__,
  3836. slim_rx_cfg[2].channels);
  3837. rx_ch_count = slim_rx_cfg[2].channels;
  3838. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  3839. pr_debug("%s: rx_6_ch=%d\n", __func__,
  3840. slim_rx_cfg[6].channels);
  3841. rx_ch_count = slim_rx_cfg[6].channels;
  3842. } else {
  3843. pr_debug("%s: rx_0_ch=%d\n", __func__,
  3844. slim_rx_cfg[0].channels);
  3845. rx_ch_count = slim_rx_cfg[0].channels;
  3846. }
  3847. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3848. rx_ch_count, rx_ch);
  3849. if (ret < 0) {
  3850. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3851. __func__, ret);
  3852. goto err;
  3853. }
  3854. } else {
  3855. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  3856. codec_dai->name, codec_dai->id, user_set_tx_ch);
  3857. ret = snd_soc_dai_get_channel_map(codec_dai,
  3858. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3859. if (ret < 0) {
  3860. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  3861. __func__, ret);
  3862. goto err;
  3863. }
  3864. /* For <codec>_tx1 case */
  3865. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  3866. user_set_tx_ch = slim_tx_cfg[0].channels;
  3867. /* For <codec>_tx3 case */
  3868. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  3869. user_set_tx_ch = slim_tx_cfg[1].channels;
  3870. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  3871. user_set_tx_ch = msm_vi_feed_tx_ch;
  3872. else
  3873. user_set_tx_ch = tx_ch_cnt;
  3874. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  3875. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  3876. tx_ch_cnt, dai_link->id);
  3877. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3878. user_set_tx_ch, tx_ch, 0, 0);
  3879. if (ret < 0)
  3880. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  3881. __func__, ret);
  3882. }
  3883. err:
  3884. return ret;
  3885. }
  3886. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  3887. struct snd_pcm_hw_params *params)
  3888. {
  3889. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3890. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3891. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3892. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3893. int ret = 0;
  3894. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  3895. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3896. u32 user_set_tx_ch = 0;
  3897. u32 user_set_rx_ch = 0;
  3898. u32 ch_id;
  3899. ret = snd_soc_dai_get_channel_map(codec_dai,
  3900. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  3901. &rx_ch_cdc_dma);
  3902. if (ret < 0) {
  3903. pr_err("%s: failed to get codec chan map, err:%d\n",
  3904. __func__, ret);
  3905. goto err;
  3906. }
  3907. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3908. switch (dai_link->id) {
  3909. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3910. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3911. {
  3912. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3913. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  3914. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  3915. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  3916. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  3917. user_set_rx_ch, &rx_ch_cdc_dma);
  3918. if (ret < 0) {
  3919. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3920. __func__, ret);
  3921. goto err;
  3922. }
  3923. }
  3924. break;
  3925. }
  3926. } else {
  3927. switch (dai_link->id) {
  3928. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3929. {
  3930. user_set_tx_ch = msm_vi_feed_tx_ch;
  3931. }
  3932. break;
  3933. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3934. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3935. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3936. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3937. {
  3938. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3939. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  3940. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  3941. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  3942. }
  3943. break;
  3944. }
  3945. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  3946. &tx_ch_cdc_dma, 0, 0);
  3947. if (ret < 0) {
  3948. pr_err("%s: failed to set cpu chan map, err:%d\n",
  3949. __func__, ret);
  3950. goto err;
  3951. }
  3952. }
  3953. err:
  3954. return ret;
  3955. }
  3956. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  3957. struct snd_pcm_hw_params *params)
  3958. {
  3959. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3960. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  3961. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3962. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3963. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  3964. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  3965. int ret;
  3966. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  3967. codec_dai->name, codec_dai->id);
  3968. ret = snd_soc_dai_get_channel_map(codec_dai,
  3969. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  3970. if (ret) {
  3971. dev_err(rtd->dev,
  3972. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  3973. __func__, ret);
  3974. goto err;
  3975. }
  3976. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  3977. __func__, tx_ch_cnt, dai_link->id);
  3978. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3979. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  3980. if (ret)
  3981. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  3982. __func__, ret);
  3983. err:
  3984. return ret;
  3985. }
  3986. static int msm_get_port_id(int be_id)
  3987. {
  3988. int afe_port_id;
  3989. switch (be_id) {
  3990. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3991. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  3992. break;
  3993. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3994. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  3995. break;
  3996. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3997. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  3998. break;
  3999. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4000. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  4001. break;
  4002. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4003. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  4004. break;
  4005. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4006. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  4007. break;
  4008. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4009. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  4010. break;
  4011. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4012. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  4013. break;
  4014. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4015. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  4016. break;
  4017. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4018. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  4019. break;
  4020. default:
  4021. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  4022. afe_port_id = -EINVAL;
  4023. }
  4024. return afe_port_id;
  4025. }
  4026. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  4027. {
  4028. u32 bit_per_sample;
  4029. switch (bit_format) {
  4030. case SNDRV_PCM_FORMAT_S32_LE:
  4031. case SNDRV_PCM_FORMAT_S24_3LE:
  4032. case SNDRV_PCM_FORMAT_S24_LE:
  4033. bit_per_sample = 32;
  4034. break;
  4035. case SNDRV_PCM_FORMAT_S16_LE:
  4036. default:
  4037. bit_per_sample = 16;
  4038. break;
  4039. }
  4040. return bit_per_sample;
  4041. }
  4042. static void update_mi2s_clk_val(int dai_id, int stream)
  4043. {
  4044. u32 bit_per_sample;
  4045. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4046. bit_per_sample =
  4047. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  4048. mi2s_clk[dai_id].clk_freq_in_hz =
  4049. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4050. } else {
  4051. bit_per_sample =
  4052. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  4053. mi2s_clk[dai_id].clk_freq_in_hz =
  4054. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  4055. }
  4056. }
  4057. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  4058. {
  4059. int ret = 0;
  4060. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4061. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4062. int port_id = 0;
  4063. int index = cpu_dai->id;
  4064. port_id = msm_get_port_id(rtd->dai_link->id);
  4065. if (port_id < 0) {
  4066. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  4067. ret = port_id;
  4068. goto err;
  4069. }
  4070. if (enable) {
  4071. update_mi2s_clk_val(index, substream->stream);
  4072. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  4073. mi2s_clk[index].clk_freq_in_hz);
  4074. }
  4075. mi2s_clk[index].enable = enable;
  4076. ret = afe_set_lpass_clock_v2(port_id,
  4077. &mi2s_clk[index]);
  4078. if (ret < 0) {
  4079. dev_err(rtd->card->dev,
  4080. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  4081. __func__, port_id, ret);
  4082. goto err;
  4083. }
  4084. err:
  4085. return ret;
  4086. }
  4087. static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
  4088. enum pinctrl_pin_state new_state)
  4089. {
  4090. int ret = 0;
  4091. int curr_state = 0;
  4092. if (pinctrl_info == NULL) {
  4093. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4094. ret = -EINVAL;
  4095. goto err;
  4096. }
  4097. if (pinctrl_info->pinctrl == NULL) {
  4098. pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
  4099. ret = -EINVAL;
  4100. goto err;
  4101. }
  4102. curr_state = pinctrl_info->curr_state;
  4103. pinctrl_info->curr_state = new_state;
  4104. pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
  4105. pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
  4106. if (curr_state == pinctrl_info->curr_state) {
  4107. pr_debug("%s: Already in same state\n", __func__);
  4108. goto err;
  4109. }
  4110. if (curr_state != STATE_DISABLE &&
  4111. pinctrl_info->curr_state != STATE_DISABLE) {
  4112. pr_debug("%s: state already active cannot switch\n", __func__);
  4113. ret = -EIO;
  4114. goto err;
  4115. }
  4116. switch (pinctrl_info->curr_state) {
  4117. case STATE_MI2S_ACTIVE:
  4118. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4119. pinctrl_info->mi2s_active);
  4120. if (ret) {
  4121. pr_err("%s: MI2S state select failed with %d\n",
  4122. __func__, ret);
  4123. ret = -EIO;
  4124. goto err;
  4125. }
  4126. break;
  4127. case STATE_TDM_ACTIVE:
  4128. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4129. pinctrl_info->tdm_active);
  4130. if (ret) {
  4131. pr_err("%s: TDM state select failed with %d\n",
  4132. __func__, ret);
  4133. ret = -EIO;
  4134. goto err;
  4135. }
  4136. break;
  4137. case STATE_DISABLE:
  4138. if (curr_state == STATE_MI2S_ACTIVE) {
  4139. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4140. pinctrl_info->mi2s_disable);
  4141. } else {
  4142. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4143. pinctrl_info->tdm_disable);
  4144. }
  4145. if (ret) {
  4146. pr_err("%s: state disable failed with %d\n",
  4147. __func__, ret);
  4148. ret = -EIO;
  4149. goto err;
  4150. }
  4151. break;
  4152. default:
  4153. pr_err("%s: TLMM pin state is invalid\n", __func__);
  4154. return -EINVAL;
  4155. }
  4156. err:
  4157. return ret;
  4158. }
  4159. static void msm_release_pinctrl(struct platform_device *pdev)
  4160. {
  4161. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4162. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4163. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4164. if (pinctrl_info->pinctrl) {
  4165. devm_pinctrl_put(pinctrl_info->pinctrl);
  4166. pinctrl_info->pinctrl = NULL;
  4167. }
  4168. }
  4169. static int msm_get_pinctrl(struct platform_device *pdev)
  4170. {
  4171. struct snd_soc_card *card = platform_get_drvdata(pdev);
  4172. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4173. struct msm_pinctrl_info *pinctrl_info = NULL;
  4174. struct pinctrl *pinctrl;
  4175. int ret;
  4176. pinctrl_info = &pdata->pinctrl_info;
  4177. if (pinctrl_info == NULL) {
  4178. pr_err("%s: pinctrl_info is NULL\n", __func__);
  4179. return -EINVAL;
  4180. }
  4181. pinctrl = devm_pinctrl_get(&pdev->dev);
  4182. if (IS_ERR_OR_NULL(pinctrl)) {
  4183. pr_err("%s: Unable to get pinctrl handle\n", __func__);
  4184. return -EINVAL;
  4185. }
  4186. pinctrl_info->pinctrl = pinctrl;
  4187. /* get all the states handles from Device Tree */
  4188. pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
  4189. "quat-mi2s-sleep");
  4190. if (IS_ERR(pinctrl_info->mi2s_disable)) {
  4191. pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
  4192. goto err;
  4193. }
  4194. pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
  4195. "quat-mi2s-active");
  4196. if (IS_ERR(pinctrl_info->mi2s_active)) {
  4197. pr_err("%s: could not get mi2s_active pinstate\n", __func__);
  4198. goto err;
  4199. }
  4200. pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
  4201. "quat-tdm-sleep");
  4202. if (IS_ERR(pinctrl_info->tdm_disable)) {
  4203. pr_err("%s: could not get tdm_disable pinstate\n", __func__);
  4204. goto err;
  4205. }
  4206. pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
  4207. "quat-tdm-active");
  4208. if (IS_ERR(pinctrl_info->tdm_active)) {
  4209. pr_err("%s: could not get tdm_active pinstate\n",
  4210. __func__);
  4211. goto err;
  4212. }
  4213. /* Reset the TLMM pins to a default state */
  4214. ret = pinctrl_select_state(pinctrl_info->pinctrl,
  4215. pinctrl_info->mi2s_disable);
  4216. if (ret != 0) {
  4217. pr_err("%s: Disable TLMM pins failed with %d\n",
  4218. __func__, ret);
  4219. ret = -EIO;
  4220. goto err;
  4221. }
  4222. pinctrl_info->curr_state = STATE_DISABLE;
  4223. return 0;
  4224. err:
  4225. devm_pinctrl_put(pinctrl);
  4226. pinctrl_info->pinctrl = NULL;
  4227. return -EINVAL;
  4228. }
  4229. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4230. struct snd_pcm_hw_params *params)
  4231. {
  4232. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4233. struct snd_interval *rate = hw_param_interval(params,
  4234. SNDRV_PCM_HW_PARAM_RATE);
  4235. struct snd_interval *channels = hw_param_interval(params,
  4236. SNDRV_PCM_HW_PARAM_CHANNELS);
  4237. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  4238. channels->min = channels->max =
  4239. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4240. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4241. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4242. rate->min = rate->max =
  4243. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4244. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  4245. channels->min = channels->max =
  4246. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4247. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4248. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4249. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4250. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  4251. channels->min = channels->max =
  4252. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4253. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4254. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4255. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4256. } else {
  4257. pr_err("%s: dai id 0x%x not supported\n",
  4258. __func__, cpu_dai->id);
  4259. return -EINVAL;
  4260. }
  4261. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  4262. __func__, cpu_dai->id, channels->max, rate->max,
  4263. params_format(params));
  4264. return 0;
  4265. }
  4266. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  4267. struct snd_pcm_hw_params *params)
  4268. {
  4269. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4270. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4271. int ret = 0;
  4272. int slot_width = 32;
  4273. int channels, slots;
  4274. unsigned int slot_mask, rate, clk_freq;
  4275. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  4276. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  4277. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4278. switch (cpu_dai->id) {
  4279. case AFE_PORT_ID_PRIMARY_TDM_RX:
  4280. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4281. break;
  4282. case AFE_PORT_ID_SECONDARY_TDM_RX:
  4283. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4284. break;
  4285. case AFE_PORT_ID_TERTIARY_TDM_RX:
  4286. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4287. break;
  4288. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  4289. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4290. break;
  4291. case AFE_PORT_ID_QUINARY_TDM_RX:
  4292. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4293. break;
  4294. case AFE_PORT_ID_PRIMARY_TDM_TX:
  4295. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4296. break;
  4297. case AFE_PORT_ID_SECONDARY_TDM_TX:
  4298. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4299. break;
  4300. case AFE_PORT_ID_TERTIARY_TDM_TX:
  4301. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4302. break;
  4303. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  4304. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4305. break;
  4306. case AFE_PORT_ID_QUINARY_TDM_TX:
  4307. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4308. break;
  4309. default:
  4310. pr_err("%s: dai id 0x%x not supported\n",
  4311. __func__, cpu_dai->id);
  4312. return -EINVAL;
  4313. }
  4314. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4315. /*2 slot config - bits 0 and 1 set for the first two slots */
  4316. slot_mask = 0x0000FFFF >> (16-slots);
  4317. channels = slots;
  4318. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  4319. __func__, slot_width, slots);
  4320. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  4321. slots, slot_width);
  4322. if (ret < 0) {
  4323. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  4324. __func__, ret);
  4325. goto end;
  4326. }
  4327. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4328. 0, NULL, channels, slot_offset);
  4329. if (ret < 0) {
  4330. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  4331. __func__, ret);
  4332. goto end;
  4333. }
  4334. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  4335. /*2 slot config - bits 0 and 1 set for the first two slots */
  4336. slot_mask = 0x0000FFFF >> (16-slots);
  4337. channels = slots;
  4338. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  4339. __func__, slot_width, slots);
  4340. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  4341. slots, slot_width);
  4342. if (ret < 0) {
  4343. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  4344. __func__, ret);
  4345. goto end;
  4346. }
  4347. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4348. channels, slot_offset, 0, NULL);
  4349. if (ret < 0) {
  4350. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  4351. __func__, ret);
  4352. goto end;
  4353. }
  4354. } else {
  4355. ret = -EINVAL;
  4356. pr_err("%s: invalid use case, err:%d\n",
  4357. __func__, ret);
  4358. goto end;
  4359. }
  4360. rate = params_rate(params);
  4361. clk_freq = rate * slot_width * slots;
  4362. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  4363. if (ret < 0)
  4364. pr_err("%s: failed to set tdm clk, err:%d\n",
  4365. __func__, ret);
  4366. end:
  4367. return ret;
  4368. }
  4369. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  4370. {
  4371. int ret = 0;
  4372. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4373. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4374. struct snd_soc_card *card = rtd->card;
  4375. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4376. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4377. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4378. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4379. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4380. ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
  4381. if (ret)
  4382. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4383. __func__, ret);
  4384. }
  4385. return ret;
  4386. }
  4387. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  4388. {
  4389. int ret = 0;
  4390. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4391. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4392. struct snd_soc_card *card = rtd->card;
  4393. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4394. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4395. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  4396. if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
  4397. (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
  4398. ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
  4399. if (ret)
  4400. pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
  4401. __func__, ret);
  4402. }
  4403. }
  4404. static struct snd_soc_ops qcs405_tdm_be_ops = {
  4405. .hw_params = qcs405_tdm_snd_hw_params,
  4406. .startup = qcs405_tdm_snd_startup,
  4407. .shutdown = qcs405_tdm_snd_shutdown
  4408. };
  4409. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4410. {
  4411. cpumask_t mask;
  4412. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4413. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4414. cpumask_clear(&mask);
  4415. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4416. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4417. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4418. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4419. pm_qos_add_request(&substream->latency_pm_qos_req,
  4420. PM_QOS_CPU_DMA_LATENCY,
  4421. MSM_LL_QOS_VALUE);
  4422. return 0;
  4423. }
  4424. static struct snd_soc_ops msm_fe_qos_ops = {
  4425. .prepare = msm_fe_qos_prepare,
  4426. };
  4427. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4428. {
  4429. int ret = 0;
  4430. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4431. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4432. int index = cpu_dai->id;
  4433. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4434. struct snd_soc_card *card = rtd->card;
  4435. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4436. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4437. int ret_pinctrl = 0;
  4438. dev_dbg(rtd->card->dev,
  4439. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4440. __func__, substream->name, substream->stream,
  4441. cpu_dai->name, cpu_dai->id);
  4442. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4443. ret = -EINVAL;
  4444. dev_err(rtd->card->dev,
  4445. "%s: CPU DAI id (%d) out of range\n",
  4446. __func__, cpu_dai->id);
  4447. goto err;
  4448. }
  4449. /*
  4450. * Mutex protection in case the same MI2S
  4451. * interface using for both TX and RX so
  4452. * that the same clock won't be enable twice.
  4453. */
  4454. mutex_lock(&mi2s_intf_conf[index].lock);
  4455. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4456. /* Check if msm needs to provide the clock to the interface */
  4457. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4458. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4459. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4460. }
  4461. ret = msm_mi2s_set_sclk(substream, true);
  4462. if (ret < 0) {
  4463. dev_err(rtd->card->dev,
  4464. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4465. __func__, ret);
  4466. goto clean_up;
  4467. }
  4468. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4469. if (ret < 0) {
  4470. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4471. __func__, index, ret);
  4472. goto clk_off;
  4473. }
  4474. if (index == QUAT_MI2S) {
  4475. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4476. STATE_MI2S_ACTIVE);
  4477. if (ret_pinctrl)
  4478. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4479. __func__, ret_pinctrl);
  4480. }
  4481. }
  4482. clk_off:
  4483. if (ret < 0)
  4484. msm_mi2s_set_sclk(substream, false);
  4485. clean_up:
  4486. if (ret < 0)
  4487. mi2s_intf_conf[index].ref_cnt--;
  4488. mutex_unlock(&mi2s_intf_conf[index].lock);
  4489. err:
  4490. return ret;
  4491. }
  4492. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4493. {
  4494. int ret;
  4495. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4496. int index = rtd->cpu_dai->id;
  4497. struct snd_soc_card *card = rtd->card;
  4498. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4499. struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
  4500. int ret_pinctrl = 0;
  4501. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4502. substream->name, substream->stream);
  4503. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4504. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4505. return;
  4506. }
  4507. mutex_lock(&mi2s_intf_conf[index].lock);
  4508. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4509. ret = msm_mi2s_set_sclk(substream, false);
  4510. if (ret < 0)
  4511. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4512. __func__, index, ret);
  4513. if (index == QUAT_MI2S) {
  4514. ret_pinctrl = msm_set_pinctrl(pinctrl_info,
  4515. STATE_DISABLE);
  4516. if (ret_pinctrl)
  4517. pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
  4518. __func__, ret_pinctrl);
  4519. }
  4520. }
  4521. mutex_unlock(&mi2s_intf_conf[index].lock);
  4522. }
  4523. static struct snd_soc_ops msm_mi2s_be_ops = {
  4524. .startup = msm_mi2s_snd_startup,
  4525. .shutdown = msm_mi2s_snd_shutdown,
  4526. };
  4527. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4528. .hw_params = msm_snd_cdc_dma_hw_params,
  4529. };
  4530. static struct snd_soc_ops msm_be_ops = {
  4531. .hw_params = msm_snd_hw_params,
  4532. };
  4533. static struct snd_soc_ops msm_wcn_ops = {
  4534. .hw_params = msm_wcn_hw_params,
  4535. };
  4536. /* Digital audio interface glue - connects codec <---> CPU */
  4537. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4538. /* FrontEnd DAI Links */
  4539. {
  4540. .name = MSM_DAILINK_NAME(Media1),
  4541. .stream_name = "MultiMedia1",
  4542. .cpu_dai_name = "MultiMedia1",
  4543. .platform_name = "msm-pcm-dsp.0",
  4544. .dynamic = 1,
  4545. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4546. .dpcm_playback = 1,
  4547. .dpcm_capture = 1,
  4548. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4549. SND_SOC_DPCM_TRIGGER_POST},
  4550. .codec_dai_name = "snd-soc-dummy-dai",
  4551. .codec_name = "snd-soc-dummy",
  4552. .ignore_suspend = 1,
  4553. /* this dainlink has playback support */
  4554. .ignore_pmdown_time = 1,
  4555. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4556. },
  4557. {
  4558. .name = MSM_DAILINK_NAME(Media2),
  4559. .stream_name = "MultiMedia2",
  4560. .cpu_dai_name = "MultiMedia2",
  4561. .platform_name = "msm-pcm-dsp.0",
  4562. .dynamic = 1,
  4563. .dpcm_playback = 1,
  4564. .dpcm_capture = 1,
  4565. .codec_dai_name = "snd-soc-dummy-dai",
  4566. .codec_name = "snd-soc-dummy",
  4567. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4568. SND_SOC_DPCM_TRIGGER_POST},
  4569. .ignore_suspend = 1,
  4570. /* this dainlink has playback support */
  4571. .ignore_pmdown_time = 1,
  4572. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4573. },
  4574. {
  4575. .name = "VoiceMMode1",
  4576. .stream_name = "VoiceMMode1",
  4577. .cpu_dai_name = "VoiceMMode1",
  4578. .platform_name = "msm-pcm-voice",
  4579. .dynamic = 1,
  4580. .dpcm_playback = 1,
  4581. .dpcm_capture = 1,
  4582. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4583. SND_SOC_DPCM_TRIGGER_POST},
  4584. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4585. .ignore_suspend = 1,
  4586. .ignore_pmdown_time = 1,
  4587. .codec_dai_name = "snd-soc-dummy-dai",
  4588. .codec_name = "snd-soc-dummy",
  4589. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4590. },
  4591. {
  4592. .name = "MSM VoIP",
  4593. .stream_name = "VoIP",
  4594. .cpu_dai_name = "VoIP",
  4595. .platform_name = "msm-voip-dsp",
  4596. .dynamic = 1,
  4597. .dpcm_playback = 1,
  4598. .dpcm_capture = 1,
  4599. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4600. SND_SOC_DPCM_TRIGGER_POST},
  4601. .codec_dai_name = "snd-soc-dummy-dai",
  4602. .codec_name = "snd-soc-dummy",
  4603. .ignore_suspend = 1,
  4604. /* this dainlink has playback support */
  4605. .ignore_pmdown_time = 1,
  4606. .id = MSM_FRONTEND_DAI_VOIP,
  4607. },
  4608. {
  4609. .name = MSM_DAILINK_NAME(ULL),
  4610. .stream_name = "MultiMedia3",
  4611. .cpu_dai_name = "MultiMedia3",
  4612. .platform_name = "msm-pcm-dsp.2",
  4613. .dynamic = 1,
  4614. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4615. .dpcm_playback = 1,
  4616. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4617. SND_SOC_DPCM_TRIGGER_POST},
  4618. .codec_dai_name = "snd-soc-dummy-dai",
  4619. .codec_name = "snd-soc-dummy",
  4620. .ignore_suspend = 1,
  4621. /* this dainlink has playback support */
  4622. .ignore_pmdown_time = 1,
  4623. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4624. },
  4625. /* Hostless PCM purpose */
  4626. {
  4627. .name = "SLIMBUS_0 Hostless",
  4628. .stream_name = "SLIMBUS_0 Hostless",
  4629. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  4630. .platform_name = "msm-pcm-hostless",
  4631. .dynamic = 1,
  4632. .dpcm_playback = 1,
  4633. .dpcm_capture = 1,
  4634. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4635. SND_SOC_DPCM_TRIGGER_POST},
  4636. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4637. .ignore_suspend = 1,
  4638. /* this dailink has playback support */
  4639. .ignore_pmdown_time = 1,
  4640. .codec_dai_name = "snd-soc-dummy-dai",
  4641. .codec_name = "snd-soc-dummy",
  4642. },
  4643. {
  4644. .name = "MSM AFE-PCM RX",
  4645. .stream_name = "AFE-PROXY RX",
  4646. .cpu_dai_name = "msm-dai-q6-dev.241",
  4647. .codec_name = "msm-stub-codec.1",
  4648. .codec_dai_name = "msm-stub-rx",
  4649. .platform_name = "msm-pcm-afe",
  4650. .dpcm_playback = 1,
  4651. .ignore_suspend = 1,
  4652. /* this dainlink has playback support */
  4653. .ignore_pmdown_time = 1,
  4654. },
  4655. {
  4656. .name = "MSM AFE-PCM TX",
  4657. .stream_name = "AFE-PROXY TX",
  4658. .cpu_dai_name = "msm-dai-q6-dev.240",
  4659. .codec_name = "msm-stub-codec.1",
  4660. .codec_dai_name = "msm-stub-tx",
  4661. .platform_name = "msm-pcm-afe",
  4662. .dpcm_capture = 1,
  4663. .ignore_suspend = 1,
  4664. },
  4665. {
  4666. .name = MSM_DAILINK_NAME(Compress1),
  4667. .stream_name = "Compress1",
  4668. .cpu_dai_name = "MultiMedia4",
  4669. .platform_name = "msm-compress-dsp",
  4670. .dynamic = 1,
  4671. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4672. .dpcm_playback = 1,
  4673. .dpcm_capture = 1,
  4674. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4675. SND_SOC_DPCM_TRIGGER_POST},
  4676. .codec_dai_name = "snd-soc-dummy-dai",
  4677. .codec_name = "snd-soc-dummy",
  4678. .ignore_suspend = 1,
  4679. .ignore_pmdown_time = 1,
  4680. /* this dainlink has playback support */
  4681. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4682. },
  4683. {
  4684. .name = "AUXPCM Hostless",
  4685. .stream_name = "AUXPCM Hostless",
  4686. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4687. .platform_name = "msm-pcm-hostless",
  4688. .dynamic = 1,
  4689. .dpcm_playback = 1,
  4690. .dpcm_capture = 1,
  4691. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4692. SND_SOC_DPCM_TRIGGER_POST},
  4693. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4694. .ignore_suspend = 1,
  4695. /* this dainlink has playback support */
  4696. .ignore_pmdown_time = 1,
  4697. .codec_dai_name = "snd-soc-dummy-dai",
  4698. .codec_name = "snd-soc-dummy",
  4699. },
  4700. {
  4701. .name = "SLIMBUS_1 Hostless",
  4702. .stream_name = "SLIMBUS_1 Hostless",
  4703. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  4704. .platform_name = "msm-pcm-hostless",
  4705. .dynamic = 1,
  4706. .dpcm_playback = 1,
  4707. .dpcm_capture = 1,
  4708. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4709. SND_SOC_DPCM_TRIGGER_POST},
  4710. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4711. .ignore_suspend = 1,
  4712. /* this dailink has playback support */
  4713. .ignore_pmdown_time = 1,
  4714. .codec_dai_name = "snd-soc-dummy-dai",
  4715. .codec_name = "snd-soc-dummy",
  4716. },
  4717. {
  4718. .name = "SLIMBUS_3 Hostless",
  4719. .stream_name = "SLIMBUS_3 Hostless",
  4720. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  4721. .platform_name = "msm-pcm-hostless",
  4722. .dynamic = 1,
  4723. .dpcm_playback = 1,
  4724. .dpcm_capture = 1,
  4725. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4726. SND_SOC_DPCM_TRIGGER_POST},
  4727. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4728. .ignore_suspend = 1,
  4729. /* this dailink has playback support */
  4730. .ignore_pmdown_time = 1,
  4731. .codec_dai_name = "snd-soc-dummy-dai",
  4732. .codec_name = "snd-soc-dummy",
  4733. },
  4734. {
  4735. .name = "SLIMBUS_4 Hostless",
  4736. .stream_name = "SLIMBUS_4 Hostless",
  4737. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  4738. .platform_name = "msm-pcm-hostless",
  4739. .dynamic = 1,
  4740. .dpcm_playback = 1,
  4741. .dpcm_capture = 1,
  4742. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4743. SND_SOC_DPCM_TRIGGER_POST},
  4744. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4745. .ignore_suspend = 1,
  4746. /* this dailink has playback support */
  4747. .ignore_pmdown_time = 1,
  4748. .codec_dai_name = "snd-soc-dummy-dai",
  4749. .codec_name = "snd-soc-dummy",
  4750. },
  4751. {
  4752. .name = MSM_DAILINK_NAME(LowLatency),
  4753. .stream_name = "MultiMedia5",
  4754. .cpu_dai_name = "MultiMedia5",
  4755. .platform_name = "msm-pcm-dsp.1",
  4756. .dynamic = 1,
  4757. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4758. .dpcm_playback = 1,
  4759. .dpcm_capture = 1,
  4760. .codec_dai_name = "snd-soc-dummy-dai",
  4761. .codec_name = "snd-soc-dummy",
  4762. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4763. SND_SOC_DPCM_TRIGGER_POST},
  4764. .ignore_suspend = 1,
  4765. /* this dainlink has playback support */
  4766. .ignore_pmdown_time = 1,
  4767. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4768. .ops = &msm_fe_qos_ops,
  4769. },
  4770. {
  4771. .name = "Listen 1 Audio Service",
  4772. .stream_name = "Listen 1 Audio Service",
  4773. .cpu_dai_name = "LSM1",
  4774. .platform_name = "msm-lsm-client",
  4775. .dynamic = 1,
  4776. .dpcm_capture = 1,
  4777. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4778. SND_SOC_DPCM_TRIGGER_POST },
  4779. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4780. .ignore_suspend = 1,
  4781. .codec_dai_name = "snd-soc-dummy-dai",
  4782. .codec_name = "snd-soc-dummy",
  4783. .id = MSM_FRONTEND_DAI_LSM1,
  4784. },
  4785. /* Multiple Tunnel instances */
  4786. {
  4787. .name = MSM_DAILINK_NAME(Compress2),
  4788. .stream_name = "Compress2",
  4789. .cpu_dai_name = "MultiMedia7",
  4790. .platform_name = "msm-compress-dsp",
  4791. .dynamic = 1,
  4792. .dpcm_playback = 1,
  4793. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4794. SND_SOC_DPCM_TRIGGER_POST},
  4795. .codec_dai_name = "snd-soc-dummy-dai",
  4796. .codec_name = "snd-soc-dummy",
  4797. .ignore_suspend = 1,
  4798. .ignore_pmdown_time = 1,
  4799. /* this dainlink has playback support */
  4800. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4801. },
  4802. {
  4803. .name = MSM_DAILINK_NAME(MultiMedia10),
  4804. .stream_name = "MultiMedia10",
  4805. .cpu_dai_name = "MultiMedia10",
  4806. .platform_name = "msm-pcm-dsp.1",
  4807. .dynamic = 1,
  4808. .dpcm_playback = 1,
  4809. .dpcm_capture = 1,
  4810. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4811. SND_SOC_DPCM_TRIGGER_POST},
  4812. .codec_dai_name = "snd-soc-dummy-dai",
  4813. .codec_name = "snd-soc-dummy",
  4814. .ignore_suspend = 1,
  4815. .ignore_pmdown_time = 1,
  4816. /* this dainlink has playback support */
  4817. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4818. },
  4819. {
  4820. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4821. .stream_name = "MM_NOIRQ",
  4822. .cpu_dai_name = "MultiMedia8",
  4823. .platform_name = "msm-pcm-dsp-noirq",
  4824. .dynamic = 1,
  4825. .dpcm_playback = 1,
  4826. .dpcm_capture = 1,
  4827. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4828. SND_SOC_DPCM_TRIGGER_POST},
  4829. .codec_dai_name = "snd-soc-dummy-dai",
  4830. .codec_name = "snd-soc-dummy",
  4831. .ignore_suspend = 1,
  4832. .ignore_pmdown_time = 1,
  4833. /* this dainlink has playback support */
  4834. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4835. .ops = &msm_fe_qos_ops,
  4836. },
  4837. /* HDMI Hostless */
  4838. {
  4839. .name = "HDMI_RX_HOSTLESS",
  4840. .stream_name = "HDMI_RX_HOSTLESS",
  4841. .cpu_dai_name = "HDMI_HOSTLESS",
  4842. .platform_name = "msm-pcm-hostless",
  4843. .dynamic = 1,
  4844. .dpcm_playback = 1,
  4845. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4846. SND_SOC_DPCM_TRIGGER_POST},
  4847. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4848. .ignore_suspend = 1,
  4849. .ignore_pmdown_time = 1,
  4850. .codec_dai_name = "snd-soc-dummy-dai",
  4851. .codec_name = "snd-soc-dummy",
  4852. },
  4853. {
  4854. .name = "VoiceMMode2",
  4855. .stream_name = "VoiceMMode2",
  4856. .cpu_dai_name = "VoiceMMode2",
  4857. .platform_name = "msm-pcm-voice",
  4858. .dynamic = 1,
  4859. .dpcm_playback = 1,
  4860. .dpcm_capture = 1,
  4861. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4862. SND_SOC_DPCM_TRIGGER_POST},
  4863. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4864. .ignore_suspend = 1,
  4865. .ignore_pmdown_time = 1,
  4866. .codec_dai_name = "snd-soc-dummy-dai",
  4867. .codec_name = "snd-soc-dummy",
  4868. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4869. },
  4870. /* LSM FE */
  4871. {
  4872. .name = "Listen 2 Audio Service",
  4873. .stream_name = "Listen 2 Audio Service",
  4874. .cpu_dai_name = "LSM2",
  4875. .platform_name = "msm-lsm-client",
  4876. .dynamic = 1,
  4877. .dpcm_capture = 1,
  4878. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4879. SND_SOC_DPCM_TRIGGER_POST },
  4880. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4881. .ignore_suspend = 1,
  4882. .codec_dai_name = "snd-soc-dummy-dai",
  4883. .codec_name = "snd-soc-dummy",
  4884. .id = MSM_FRONTEND_DAI_LSM2,
  4885. },
  4886. {
  4887. .name = "Listen 3 Audio Service",
  4888. .stream_name = "Listen 3 Audio Service",
  4889. .cpu_dai_name = "LSM3",
  4890. .platform_name = "msm-lsm-client",
  4891. .dynamic = 1,
  4892. .dpcm_capture = 1,
  4893. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4894. SND_SOC_DPCM_TRIGGER_POST },
  4895. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4896. .ignore_suspend = 1,
  4897. .codec_dai_name = "snd-soc-dummy-dai",
  4898. .codec_name = "snd-soc-dummy",
  4899. .id = MSM_FRONTEND_DAI_LSM3,
  4900. },
  4901. {
  4902. .name = "Listen 4 Audio Service",
  4903. .stream_name = "Listen 4 Audio Service",
  4904. .cpu_dai_name = "LSM4",
  4905. .platform_name = "msm-lsm-client",
  4906. .dynamic = 1,
  4907. .dpcm_capture = 1,
  4908. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4909. SND_SOC_DPCM_TRIGGER_POST },
  4910. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4911. .ignore_suspend = 1,
  4912. .codec_dai_name = "snd-soc-dummy-dai",
  4913. .codec_name = "snd-soc-dummy",
  4914. .id = MSM_FRONTEND_DAI_LSM4,
  4915. },
  4916. {
  4917. .name = "Listen 5 Audio Service",
  4918. .stream_name = "Listen 5 Audio Service",
  4919. .cpu_dai_name = "LSM5",
  4920. .platform_name = "msm-lsm-client",
  4921. .dynamic = 1,
  4922. .dpcm_capture = 1,
  4923. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4924. SND_SOC_DPCM_TRIGGER_POST },
  4925. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4926. .ignore_suspend = 1,
  4927. .codec_dai_name = "snd-soc-dummy-dai",
  4928. .codec_name = "snd-soc-dummy",
  4929. .id = MSM_FRONTEND_DAI_LSM5,
  4930. },
  4931. {
  4932. .name = "Listen 6 Audio Service",
  4933. .stream_name = "Listen 6 Audio Service",
  4934. .cpu_dai_name = "LSM6",
  4935. .platform_name = "msm-lsm-client",
  4936. .dynamic = 1,
  4937. .dpcm_capture = 1,
  4938. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4939. SND_SOC_DPCM_TRIGGER_POST },
  4940. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4941. .ignore_suspend = 1,
  4942. .codec_dai_name = "snd-soc-dummy-dai",
  4943. .codec_name = "snd-soc-dummy",
  4944. .id = MSM_FRONTEND_DAI_LSM6,
  4945. },
  4946. {
  4947. .name = "Listen 7 Audio Service",
  4948. .stream_name = "Listen 7 Audio Service",
  4949. .cpu_dai_name = "LSM7",
  4950. .platform_name = "msm-lsm-client",
  4951. .dynamic = 1,
  4952. .dpcm_capture = 1,
  4953. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4954. SND_SOC_DPCM_TRIGGER_POST },
  4955. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4956. .ignore_suspend = 1,
  4957. .codec_dai_name = "snd-soc-dummy-dai",
  4958. .codec_name = "snd-soc-dummy",
  4959. .id = MSM_FRONTEND_DAI_LSM7,
  4960. },
  4961. {
  4962. .name = "Listen 8 Audio Service",
  4963. .stream_name = "Listen 8 Audio Service",
  4964. .cpu_dai_name = "LSM8",
  4965. .platform_name = "msm-lsm-client",
  4966. .dynamic = 1,
  4967. .dpcm_capture = 1,
  4968. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4969. SND_SOC_DPCM_TRIGGER_POST },
  4970. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4971. .ignore_suspend = 1,
  4972. .codec_dai_name = "snd-soc-dummy-dai",
  4973. .codec_name = "snd-soc-dummy",
  4974. .id = MSM_FRONTEND_DAI_LSM8,
  4975. },
  4976. {
  4977. .name = MSM_DAILINK_NAME(Media9),
  4978. .stream_name = "MultiMedia9",
  4979. .cpu_dai_name = "MultiMedia9",
  4980. .platform_name = "msm-pcm-dsp.0",
  4981. .dynamic = 1,
  4982. .dpcm_playback = 1,
  4983. .dpcm_capture = 1,
  4984. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4985. SND_SOC_DPCM_TRIGGER_POST},
  4986. .codec_dai_name = "snd-soc-dummy-dai",
  4987. .codec_name = "snd-soc-dummy",
  4988. .ignore_suspend = 1,
  4989. /* this dainlink has playback support */
  4990. .ignore_pmdown_time = 1,
  4991. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4992. },
  4993. {
  4994. .name = MSM_DAILINK_NAME(Compress4),
  4995. .stream_name = "Compress4",
  4996. .cpu_dai_name = "MultiMedia11",
  4997. .platform_name = "msm-compress-dsp",
  4998. .dynamic = 1,
  4999. .dpcm_playback = 1,
  5000. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5001. SND_SOC_DPCM_TRIGGER_POST},
  5002. .codec_dai_name = "snd-soc-dummy-dai",
  5003. .codec_name = "snd-soc-dummy",
  5004. .ignore_suspend = 1,
  5005. .ignore_pmdown_time = 1,
  5006. /* this dainlink has playback support */
  5007. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  5008. },
  5009. {
  5010. .name = MSM_DAILINK_NAME(Compress5),
  5011. .stream_name = "Compress5",
  5012. .cpu_dai_name = "MultiMedia12",
  5013. .platform_name = "msm-compress-dsp",
  5014. .dynamic = 1,
  5015. .dpcm_playback = 1,
  5016. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5017. SND_SOC_DPCM_TRIGGER_POST},
  5018. .codec_dai_name = "snd-soc-dummy-dai",
  5019. .codec_name = "snd-soc-dummy",
  5020. .ignore_suspend = 1,
  5021. .ignore_pmdown_time = 1,
  5022. /* this dainlink has playback support */
  5023. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  5024. },
  5025. {
  5026. .name = MSM_DAILINK_NAME(Compress6),
  5027. .stream_name = "Compress6",
  5028. .cpu_dai_name = "MultiMedia13",
  5029. .platform_name = "msm-compress-dsp",
  5030. .dynamic = 1,
  5031. .dpcm_playback = 1,
  5032. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5033. SND_SOC_DPCM_TRIGGER_POST},
  5034. .codec_dai_name = "snd-soc-dummy-dai",
  5035. .codec_name = "snd-soc-dummy",
  5036. .ignore_suspend = 1,
  5037. .ignore_pmdown_time = 1,
  5038. /* this dainlink has playback support */
  5039. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  5040. },
  5041. {
  5042. .name = MSM_DAILINK_NAME(Compress7),
  5043. .stream_name = "Compress7",
  5044. .cpu_dai_name = "MultiMedia14",
  5045. .platform_name = "msm-compress-dsp",
  5046. .dynamic = 1,
  5047. .dpcm_playback = 1,
  5048. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5049. SND_SOC_DPCM_TRIGGER_POST},
  5050. .codec_dai_name = "snd-soc-dummy-dai",
  5051. .codec_name = "snd-soc-dummy",
  5052. .ignore_suspend = 1,
  5053. .ignore_pmdown_time = 1,
  5054. /* this dainlink has playback support */
  5055. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5056. },
  5057. {
  5058. .name = MSM_DAILINK_NAME(Compress8),
  5059. .stream_name = "Compress8",
  5060. .cpu_dai_name = "MultiMedia15",
  5061. .platform_name = "msm-compress-dsp",
  5062. .dynamic = 1,
  5063. .dpcm_playback = 1,
  5064. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5065. SND_SOC_DPCM_TRIGGER_POST},
  5066. .codec_dai_name = "snd-soc-dummy-dai",
  5067. .codec_name = "snd-soc-dummy",
  5068. .ignore_suspend = 1,
  5069. .ignore_pmdown_time = 1,
  5070. /* this dainlink has playback support */
  5071. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5072. },
  5073. {
  5074. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5075. .stream_name = "MM_NOIRQ_2",
  5076. .cpu_dai_name = "MultiMedia16",
  5077. .platform_name = "msm-pcm-dsp-noirq",
  5078. .dynamic = 1,
  5079. .dpcm_playback = 1,
  5080. .dpcm_capture = 1,
  5081. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5082. SND_SOC_DPCM_TRIGGER_POST},
  5083. .codec_dai_name = "snd-soc-dummy-dai",
  5084. .codec_name = "snd-soc-dummy",
  5085. .ignore_suspend = 1,
  5086. .ignore_pmdown_time = 1,
  5087. /* this dainlink has playback support */
  5088. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5089. },
  5090. {
  5091. .name = "SLIMBUS_8 Hostless",
  5092. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  5093. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5094. .platform_name = "msm-pcm-hostless",
  5095. .dynamic = 1,
  5096. .dpcm_capture = 1,
  5097. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5098. SND_SOC_DPCM_TRIGGER_POST},
  5099. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5100. .ignore_suspend = 1,
  5101. .codec_dai_name = "snd-soc-dummy-dai",
  5102. .codec_name = "snd-soc-dummy",
  5103. },
  5104. /* Hostless PCM purpose */
  5105. {
  5106. .name = "CDC_DMA Hostless",
  5107. .stream_name = "CDC_DMA Hostless",
  5108. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5109. .platform_name = "msm-pcm-hostless",
  5110. .dynamic = 1,
  5111. .dpcm_playback = 1,
  5112. .dpcm_capture = 1,
  5113. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5114. SND_SOC_DPCM_TRIGGER_POST},
  5115. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5116. .ignore_suspend = 1,
  5117. /* this dailink has playback support */
  5118. .ignore_pmdown_time = 1,
  5119. .codec_dai_name = "snd-soc-dummy-dai",
  5120. .codec_name = "snd-soc-dummy",
  5121. },
  5122. };
  5123. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5124. {
  5125. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5126. .stream_name = "WSA CDC DMA0 Capture",
  5127. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5128. .platform_name = "msm-pcm-hostless",
  5129. .codec_name = "bolero_codec",
  5130. .codec_dai_name = "wsa_macro_vifeedback",
  5131. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5132. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5133. .ignore_suspend = 1,
  5134. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5135. .ops = &msm_cdc_dma_be_ops,
  5136. },
  5137. };
  5138. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5139. {
  5140. .name = MSM_DAILINK_NAME(ASM Loopback),
  5141. .stream_name = "MultiMedia6",
  5142. .cpu_dai_name = "MultiMedia6",
  5143. .platform_name = "msm-pcm-loopback",
  5144. .dynamic = 1,
  5145. .dpcm_playback = 1,
  5146. .dpcm_capture = 1,
  5147. .codec_dai_name = "snd-soc-dummy-dai",
  5148. .codec_name = "snd-soc-dummy",
  5149. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5150. SND_SOC_DPCM_TRIGGER_POST},
  5151. .ignore_suspend = 1,
  5152. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5153. .ignore_pmdown_time = 1,
  5154. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5155. },
  5156. {
  5157. .name = "USB Audio Hostless",
  5158. .stream_name = "USB Audio Hostless",
  5159. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5160. .platform_name = "msm-pcm-hostless",
  5161. .dynamic = 1,
  5162. .dpcm_playback = 1,
  5163. .dpcm_capture = 1,
  5164. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5165. SND_SOC_DPCM_TRIGGER_POST},
  5166. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5167. .ignore_suspend = 1,
  5168. .ignore_pmdown_time = 1,
  5169. .codec_dai_name = "snd-soc-dummy-dai",
  5170. .codec_name = "snd-soc-dummy",
  5171. },
  5172. {
  5173. .name = "SLIMBUS_7 Hostless",
  5174. .stream_name = "SLIMBUS_7 Hostless",
  5175. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5176. .platform_name = "msm-pcm-hostless",
  5177. .dynamic = 1,
  5178. .dpcm_capture = 1,
  5179. .dpcm_playback = 1,
  5180. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5181. SND_SOC_DPCM_TRIGGER_POST},
  5182. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5183. .ignore_suspend = 1,
  5184. .ignore_pmdown_time = 1,
  5185. .codec_dai_name = "snd-soc-dummy-dai",
  5186. .codec_name = "snd-soc-dummy",
  5187. },
  5188. };
  5189. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5190. /* Backend AFE DAI Links */
  5191. {
  5192. .name = LPASS_BE_AFE_PCM_RX,
  5193. .stream_name = "AFE Playback",
  5194. .cpu_dai_name = "msm-dai-q6-dev.224",
  5195. .platform_name = "msm-pcm-routing",
  5196. .codec_name = "msm-stub-codec.1",
  5197. .codec_dai_name = "msm-stub-rx",
  5198. .no_pcm = 1,
  5199. .dpcm_playback = 1,
  5200. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5201. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5202. /* this dainlink has playback support */
  5203. .ignore_pmdown_time = 1,
  5204. .ignore_suspend = 1,
  5205. },
  5206. {
  5207. .name = LPASS_BE_AFE_PCM_TX,
  5208. .stream_name = "AFE Capture",
  5209. .cpu_dai_name = "msm-dai-q6-dev.225",
  5210. .platform_name = "msm-pcm-routing",
  5211. .codec_name = "msm-stub-codec.1",
  5212. .codec_dai_name = "msm-stub-tx",
  5213. .no_pcm = 1,
  5214. .dpcm_capture = 1,
  5215. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5216. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5217. .ignore_suspend = 1,
  5218. },
  5219. /* Incall Record Uplink BACK END DAI Link */
  5220. {
  5221. .name = LPASS_BE_INCALL_RECORD_TX,
  5222. .stream_name = "Voice Uplink Capture",
  5223. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5224. .platform_name = "msm-pcm-routing",
  5225. .codec_name = "msm-stub-codec.1",
  5226. .codec_dai_name = "msm-stub-tx",
  5227. .no_pcm = 1,
  5228. .dpcm_capture = 1,
  5229. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5230. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5231. .ignore_suspend = 1,
  5232. },
  5233. /* Incall Record Downlink BACK END DAI Link */
  5234. {
  5235. .name = LPASS_BE_INCALL_RECORD_RX,
  5236. .stream_name = "Voice Downlink Capture",
  5237. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5238. .platform_name = "msm-pcm-routing",
  5239. .codec_name = "msm-stub-codec.1",
  5240. .codec_dai_name = "msm-stub-tx",
  5241. .no_pcm = 1,
  5242. .dpcm_capture = 1,
  5243. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5244. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5245. .ignore_suspend = 1,
  5246. },
  5247. /* Incall Music BACK END DAI Link */
  5248. {
  5249. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5250. .stream_name = "Voice Farend Playback",
  5251. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5252. .platform_name = "msm-pcm-routing",
  5253. .codec_name = "msm-stub-codec.1",
  5254. .codec_dai_name = "msm-stub-rx",
  5255. .no_pcm = 1,
  5256. .dpcm_playback = 1,
  5257. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5258. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5259. .ignore_suspend = 1,
  5260. .ignore_pmdown_time = 1,
  5261. },
  5262. /* Incall Music 2 BACK END DAI Link */
  5263. {
  5264. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5265. .stream_name = "Voice2 Farend Playback",
  5266. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5267. .platform_name = "msm-pcm-routing",
  5268. .codec_name = "msm-stub-codec.1",
  5269. .codec_dai_name = "msm-stub-rx",
  5270. .no_pcm = 1,
  5271. .dpcm_playback = 1,
  5272. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5273. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5274. .ignore_suspend = 1,
  5275. .ignore_pmdown_time = 1,
  5276. },
  5277. {
  5278. .name = LPASS_BE_USB_AUDIO_RX,
  5279. .stream_name = "USB Audio Playback",
  5280. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5281. .platform_name = "msm-pcm-routing",
  5282. .codec_name = "msm-stub-codec.1",
  5283. .codec_dai_name = "msm-stub-rx",
  5284. .no_pcm = 1,
  5285. .dpcm_playback = 1,
  5286. .id = MSM_BACKEND_DAI_USB_RX,
  5287. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5288. .ignore_pmdown_time = 1,
  5289. .ignore_suspend = 1,
  5290. },
  5291. {
  5292. .name = LPASS_BE_USB_AUDIO_TX,
  5293. .stream_name = "USB Audio Capture",
  5294. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5295. .platform_name = "msm-pcm-routing",
  5296. .codec_name = "msm-stub-codec.1",
  5297. .codec_dai_name = "msm-stub-tx",
  5298. .no_pcm = 1,
  5299. .dpcm_capture = 1,
  5300. .id = MSM_BACKEND_DAI_USB_TX,
  5301. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5302. .ignore_suspend = 1,
  5303. },
  5304. {
  5305. .name = LPASS_BE_PRI_TDM_RX_0,
  5306. .stream_name = "Primary TDM0 Playback",
  5307. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5308. .platform_name = "msm-pcm-routing",
  5309. .codec_name = "msm-stub-codec.1",
  5310. .codec_dai_name = "msm-stub-rx",
  5311. .no_pcm = 1,
  5312. .dpcm_playback = 1,
  5313. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5314. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5315. .ops = &qcs405_tdm_be_ops,
  5316. .ignore_suspend = 1,
  5317. .ignore_pmdown_time = 1,
  5318. },
  5319. {
  5320. .name = LPASS_BE_PRI_TDM_TX_0,
  5321. .stream_name = "Primary TDM0 Capture",
  5322. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5323. .platform_name = "msm-pcm-routing",
  5324. .codec_name = "msm-stub-codec.1",
  5325. .codec_dai_name = "msm-stub-tx",
  5326. .no_pcm = 1,
  5327. .dpcm_capture = 1,
  5328. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5329. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5330. .ops = &qcs405_tdm_be_ops,
  5331. .ignore_suspend = 1,
  5332. },
  5333. {
  5334. .name = LPASS_BE_SEC_TDM_RX_0,
  5335. .stream_name = "Secondary TDM0 Playback",
  5336. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5337. .platform_name = "msm-pcm-routing",
  5338. .codec_name = "msm-stub-codec.1",
  5339. .codec_dai_name = "msm-stub-rx",
  5340. .no_pcm = 1,
  5341. .dpcm_playback = 1,
  5342. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5343. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5344. .ops = &qcs405_tdm_be_ops,
  5345. .ignore_suspend = 1,
  5346. .ignore_pmdown_time = 1,
  5347. },
  5348. {
  5349. .name = LPASS_BE_SEC_TDM_TX_0,
  5350. .stream_name = "Secondary TDM0 Capture",
  5351. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5352. .platform_name = "msm-pcm-routing",
  5353. .codec_name = "msm-stub-codec.1",
  5354. .codec_dai_name = "msm-stub-tx",
  5355. .no_pcm = 1,
  5356. .dpcm_capture = 1,
  5357. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5358. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5359. .ops = &qcs405_tdm_be_ops,
  5360. .ignore_suspend = 1,
  5361. },
  5362. {
  5363. .name = LPASS_BE_TERT_TDM_RX_0,
  5364. .stream_name = "Tertiary TDM0 Playback",
  5365. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5366. .platform_name = "msm-pcm-routing",
  5367. .codec_name = "msm-stub-codec.1",
  5368. .codec_dai_name = "msm-stub-rx",
  5369. .no_pcm = 1,
  5370. .dpcm_playback = 1,
  5371. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5372. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5373. .ops = &qcs405_tdm_be_ops,
  5374. .ignore_suspend = 1,
  5375. .ignore_pmdown_time = 1,
  5376. },
  5377. {
  5378. .name = LPASS_BE_TERT_TDM_TX_0,
  5379. .stream_name = "Tertiary TDM0 Capture",
  5380. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5381. .platform_name = "msm-pcm-routing",
  5382. .codec_name = "msm-stub-codec.1",
  5383. .codec_dai_name = "msm-stub-tx",
  5384. .no_pcm = 1,
  5385. .dpcm_capture = 1,
  5386. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5387. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5388. .ops = &qcs405_tdm_be_ops,
  5389. .ignore_suspend = 1,
  5390. },
  5391. {
  5392. .name = LPASS_BE_QUAT_TDM_RX_0,
  5393. .stream_name = "Quaternary TDM0 Playback",
  5394. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5395. .platform_name = "msm-pcm-routing",
  5396. .codec_name = "msm-stub-codec.1",
  5397. .codec_dai_name = "msm-stub-rx",
  5398. .no_pcm = 1,
  5399. .dpcm_playback = 1,
  5400. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5401. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5402. .ops = &qcs405_tdm_be_ops,
  5403. .ignore_suspend = 1,
  5404. .ignore_pmdown_time = 1,
  5405. },
  5406. {
  5407. .name = LPASS_BE_QUAT_TDM_TX_0,
  5408. .stream_name = "Quaternary TDM0 Capture",
  5409. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5410. .platform_name = "msm-pcm-routing",
  5411. .codec_name = "msm-stub-codec.1",
  5412. .codec_dai_name = "msm-stub-tx",
  5413. .no_pcm = 1,
  5414. .dpcm_capture = 1,
  5415. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5416. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5417. .ops = &qcs405_tdm_be_ops,
  5418. .ignore_suspend = 1,
  5419. },
  5420. {
  5421. .name = LPASS_BE_QUIN_TDM_RX_0,
  5422. .stream_name = "Quinary TDM0 Playback",
  5423. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5424. .platform_name = "msm-pcm-routing",
  5425. .codec_name = "msm-stub-codec.1",
  5426. .codec_dai_name = "msm-stub-rx",
  5427. .no_pcm = 1,
  5428. .dpcm_playback = 1,
  5429. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5430. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  5431. .ops = &qcs405_tdm_be_ops,
  5432. .ignore_suspend = 1,
  5433. .ignore_pmdown_time = 1,
  5434. },
  5435. {
  5436. .name = LPASS_BE_QUIN_TDM_TX_0,
  5437. .stream_name = "Quinary TDM0 Capture",
  5438. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5439. .platform_name = "msm-pcm-routing",
  5440. .codec_name = "msm-stub-codec.1",
  5441. .codec_dai_name = "msm-stub-tx",
  5442. .no_pcm = 1,
  5443. .dpcm_capture = 1,
  5444. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5445. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5446. .ops = &qcs405_tdm_be_ops,
  5447. .ignore_suspend = 1,
  5448. },
  5449. };
  5450. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  5451. {
  5452. .name = LPASS_BE_SLIMBUS_0_RX,
  5453. .stream_name = "Slimbus Playback",
  5454. .cpu_dai_name = "msm-dai-q6-dev.16384",
  5455. .platform_name = "msm-pcm-routing",
  5456. .codec_name = "tasha_codec",
  5457. .codec_dai_name = "tasha_mix_rx1",
  5458. .no_pcm = 1,
  5459. .dpcm_playback = 1,
  5460. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  5461. .init = &msm_audrx_init,
  5462. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5463. /* this dainlink has playback support */
  5464. .ignore_pmdown_time = 1,
  5465. .ignore_suspend = 1,
  5466. .ops = &msm_be_ops,
  5467. },
  5468. {
  5469. .name = LPASS_BE_SLIMBUS_0_TX,
  5470. .stream_name = "Slimbus Capture",
  5471. .cpu_dai_name = "msm-dai-q6-dev.16385",
  5472. .platform_name = "msm-pcm-routing",
  5473. .codec_name = "tasha_codec",
  5474. .codec_dai_name = "tasha_tx1",
  5475. .no_pcm = 1,
  5476. .dpcm_capture = 1,
  5477. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  5478. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5479. .ignore_suspend = 1,
  5480. .ops = &msm_be_ops,
  5481. },
  5482. {
  5483. .name = LPASS_BE_SLIMBUS_1_RX,
  5484. .stream_name = "Slimbus1 Playback",
  5485. .cpu_dai_name = "msm-dai-q6-dev.16386",
  5486. .platform_name = "msm-pcm-routing",
  5487. .codec_name = "tasha_codec",
  5488. .codec_dai_name = "tasha_mix_rx1",
  5489. .no_pcm = 1,
  5490. .dpcm_playback = 1,
  5491. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  5492. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5493. .ops = &msm_be_ops,
  5494. /* dai link has playback support */
  5495. .ignore_pmdown_time = 1,
  5496. .ignore_suspend = 1,
  5497. },
  5498. {
  5499. .name = LPASS_BE_SLIMBUS_1_TX,
  5500. .stream_name = "Slimbus1 Capture",
  5501. .cpu_dai_name = "msm-dai-q6-dev.16387",
  5502. .platform_name = "msm-pcm-routing",
  5503. .codec_name = "tasha_codec",
  5504. .codec_dai_name = "tasha_tx3",
  5505. .no_pcm = 1,
  5506. .dpcm_capture = 1,
  5507. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  5508. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5509. .ops = &msm_be_ops,
  5510. .ignore_suspend = 1,
  5511. },
  5512. {
  5513. .name = LPASS_BE_SLIMBUS_2_RX,
  5514. .stream_name = "Slimbus2 Playback",
  5515. .cpu_dai_name = "msm-dai-q6-dev.16388",
  5516. .platform_name = "msm-pcm-routing",
  5517. .codec_name = "tasha_codec",
  5518. .codec_dai_name = "tasha_rx2",
  5519. .no_pcm = 1,
  5520. .dpcm_playback = 1,
  5521. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  5522. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5523. .ops = &msm_be_ops,
  5524. .ignore_pmdown_time = 1,
  5525. .ignore_suspend = 1,
  5526. },
  5527. {
  5528. .name = LPASS_BE_SLIMBUS_3_RX,
  5529. .stream_name = "Slimbus3 Playback",
  5530. .cpu_dai_name = "msm-dai-q6-dev.16390",
  5531. .platform_name = "msm-pcm-routing",
  5532. .codec_name = "tasha_codec",
  5533. .codec_dai_name = "tasha_mix_rx1",
  5534. .no_pcm = 1,
  5535. .dpcm_playback = 1,
  5536. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  5537. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5538. .ops = &msm_be_ops,
  5539. /* dai link has playback support */
  5540. .ignore_pmdown_time = 1,
  5541. .ignore_suspend = 1,
  5542. },
  5543. {
  5544. .name = LPASS_BE_SLIMBUS_3_TX,
  5545. .stream_name = "Slimbus3 Capture",
  5546. .cpu_dai_name = "msm-dai-q6-dev.16391",
  5547. .platform_name = "msm-pcm-routing",
  5548. .codec_name = "tasha_codec",
  5549. .codec_dai_name = "tasha_tx1",
  5550. .no_pcm = 1,
  5551. .dpcm_capture = 1,
  5552. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  5553. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5554. .ops = &msm_be_ops,
  5555. .ignore_suspend = 1,
  5556. },
  5557. {
  5558. .name = LPASS_BE_SLIMBUS_4_RX,
  5559. .stream_name = "Slimbus4 Playback",
  5560. .cpu_dai_name = "msm-dai-q6-dev.16392",
  5561. .platform_name = "msm-pcm-routing",
  5562. .codec_name = "tasha_codec",
  5563. .codec_dai_name = "tasha_mix_rx1",
  5564. .no_pcm = 1,
  5565. .dpcm_playback = 1,
  5566. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  5567. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5568. .ops = &msm_be_ops,
  5569. /* dai link has playback support */
  5570. .ignore_pmdown_time = 1,
  5571. .ignore_suspend = 1,
  5572. },
  5573. {
  5574. .name = LPASS_BE_SLIMBUS_5_RX,
  5575. .stream_name = "Slimbus5 Playback",
  5576. .cpu_dai_name = "msm-dai-q6-dev.16394",
  5577. .platform_name = "msm-pcm-routing",
  5578. .codec_name = "tasha_codec",
  5579. .codec_dai_name = "tasha_rx3",
  5580. .no_pcm = 1,
  5581. .dpcm_playback = 1,
  5582. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  5583. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5584. .ops = &msm_be_ops,
  5585. /* dai link has playback support */
  5586. .ignore_pmdown_time = 1,
  5587. .ignore_suspend = 1,
  5588. },
  5589. {
  5590. .name = LPASS_BE_SLIMBUS_6_RX,
  5591. .stream_name = "Slimbus6 Playback",
  5592. .cpu_dai_name = "msm-dai-q6-dev.16396",
  5593. .platform_name = "msm-pcm-routing",
  5594. .codec_name = "tasha_codec",
  5595. .codec_dai_name = "tasha_rx4",
  5596. .no_pcm = 1,
  5597. .dpcm_playback = 1,
  5598. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  5599. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5600. .ops = &msm_be_ops,
  5601. /* dai link has playback support */
  5602. .ignore_pmdown_time = 1,
  5603. .ignore_suspend = 1,
  5604. },
  5605. /* Slimbus VI Recording */
  5606. {
  5607. .name = LPASS_BE_SLIMBUS_TX_VI,
  5608. .stream_name = "Slimbus4 Capture",
  5609. .cpu_dai_name = "msm-dai-q6-dev.16393",
  5610. .platform_name = "msm-pcm-routing",
  5611. .codec_name = "tasha_codec",
  5612. .codec_dai_name = "tasha_vifeedback",
  5613. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  5614. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5615. .ops = &msm_be_ops,
  5616. .ignore_suspend = 1,
  5617. .no_pcm = 1,
  5618. .dpcm_capture = 1,
  5619. .ignore_pmdown_time = 1,
  5620. },
  5621. };
  5622. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5623. {
  5624. .name = LPASS_BE_SLIMBUS_7_RX,
  5625. .stream_name = "Slimbus7 Playback",
  5626. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5627. .platform_name = "msm-pcm-routing",
  5628. .codec_name = "btfmslim_slave",
  5629. /* BT codec driver determines capabilities based on
  5630. * dai name, bt codecdai name should always contains
  5631. * supported usecase information
  5632. */
  5633. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5634. .no_pcm = 1,
  5635. .dpcm_playback = 1,
  5636. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5637. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5638. .ops = &msm_wcn_ops,
  5639. /* dai link has playback support */
  5640. .ignore_pmdown_time = 1,
  5641. .ignore_suspend = 1,
  5642. },
  5643. {
  5644. .name = LPASS_BE_SLIMBUS_7_TX,
  5645. .stream_name = "Slimbus7 Capture",
  5646. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5647. .platform_name = "msm-pcm-routing",
  5648. .codec_name = "btfmslim_slave",
  5649. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5650. .no_pcm = 1,
  5651. .dpcm_capture = 1,
  5652. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5653. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5654. .ops = &msm_wcn_ops,
  5655. .ignore_suspend = 1,
  5656. },
  5657. {
  5658. .name = LPASS_BE_SLIMBUS_8_TX,
  5659. .stream_name = "Slimbus8 Capture",
  5660. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5661. .platform_name = "msm-pcm-routing",
  5662. .codec_name = "btfmslim_slave",
  5663. .codec_dai_name = "btfm_fm_slim_tx",
  5664. .no_pcm = 1,
  5665. .dpcm_capture = 1,
  5666. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5667. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5668. .init = &msm_wcn_init,
  5669. .ops = &msm_wcn_ops,
  5670. .ignore_suspend = 1,
  5671. },
  5672. };
  5673. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5674. {
  5675. .name = LPASS_BE_PRI_MI2S_RX,
  5676. .stream_name = "Primary MI2S Playback",
  5677. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5678. .platform_name = "msm-pcm-routing",
  5679. .codec_name = "msm-stub-codec.1",
  5680. .codec_dai_name = "msm-stub-rx",
  5681. .no_pcm = 1,
  5682. .dpcm_playback = 1,
  5683. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5684. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5685. .ops = &msm_mi2s_be_ops,
  5686. .ignore_suspend = 1,
  5687. .ignore_pmdown_time = 1,
  5688. },
  5689. {
  5690. .name = LPASS_BE_PRI_MI2S_TX,
  5691. .stream_name = "Primary MI2S Capture",
  5692. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5693. .platform_name = "msm-pcm-routing",
  5694. .codec_name = "msm-stub-codec.1",
  5695. .codec_dai_name = "msm-stub-tx",
  5696. .no_pcm = 1,
  5697. .dpcm_capture = 1,
  5698. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5699. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5700. .ops = &msm_mi2s_be_ops,
  5701. .ignore_suspend = 1,
  5702. },
  5703. {
  5704. .name = LPASS_BE_SEC_MI2S_RX,
  5705. .stream_name = "Secondary MI2S Playback",
  5706. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5707. .platform_name = "msm-pcm-routing",
  5708. .codec_name = "msm-stub-codec.1",
  5709. .codec_dai_name = "msm-stub-rx",
  5710. .no_pcm = 1,
  5711. .dpcm_playback = 1,
  5712. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5713. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5714. .ops = &msm_mi2s_be_ops,
  5715. .ignore_suspend = 1,
  5716. .ignore_pmdown_time = 1,
  5717. },
  5718. {
  5719. .name = LPASS_BE_SEC_MI2S_TX,
  5720. .stream_name = "Secondary MI2S Capture",
  5721. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5722. .platform_name = "msm-pcm-routing",
  5723. .codec_name = "msm-stub-codec.1",
  5724. .codec_dai_name = "msm-stub-tx",
  5725. .no_pcm = 1,
  5726. .dpcm_capture = 1,
  5727. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5728. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5729. .ops = &msm_mi2s_be_ops,
  5730. .ignore_suspend = 1,
  5731. },
  5732. {
  5733. .name = LPASS_BE_TERT_MI2S_RX,
  5734. .stream_name = "Tertiary MI2S Playback",
  5735. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5736. .platform_name = "msm-pcm-routing",
  5737. .codec_name = "msm-stub-codec.1",
  5738. .codec_dai_name = "msm-stub-rx",
  5739. .no_pcm = 1,
  5740. .dpcm_playback = 1,
  5741. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5742. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5743. .ops = &msm_mi2s_be_ops,
  5744. .ignore_suspend = 1,
  5745. .ignore_pmdown_time = 1,
  5746. },
  5747. {
  5748. .name = LPASS_BE_TERT_MI2S_TX,
  5749. .stream_name = "Tertiary MI2S Capture",
  5750. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5751. .platform_name = "msm-pcm-routing",
  5752. .codec_name = "msm-stub-codec.1",
  5753. .codec_dai_name = "msm-stub-tx",
  5754. .no_pcm = 1,
  5755. .dpcm_capture = 1,
  5756. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5757. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5758. .ops = &msm_mi2s_be_ops,
  5759. .ignore_suspend = 1,
  5760. },
  5761. {
  5762. .name = LPASS_BE_QUAT_MI2S_RX,
  5763. .stream_name = "Quaternary MI2S Playback",
  5764. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5765. .platform_name = "msm-pcm-routing",
  5766. .codec_name = "msm-stub-codec.1",
  5767. .codec_dai_name = "msm-stub-rx",
  5768. .no_pcm = 1,
  5769. .dpcm_playback = 1,
  5770. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5771. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5772. .ops = &msm_mi2s_be_ops,
  5773. .ignore_suspend = 1,
  5774. .ignore_pmdown_time = 1,
  5775. },
  5776. {
  5777. .name = LPASS_BE_QUAT_MI2S_TX,
  5778. .stream_name = "Quaternary MI2S Capture",
  5779. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5780. .platform_name = "msm-pcm-routing",
  5781. .codec_name = "msm-stub-codec.1",
  5782. .codec_dai_name = "msm-stub-tx",
  5783. .no_pcm = 1,
  5784. .dpcm_capture = 1,
  5785. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5786. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5787. .ops = &msm_mi2s_be_ops,
  5788. .ignore_suspend = 1,
  5789. },
  5790. {
  5791. .name = LPASS_BE_QUIN_MI2S_RX,
  5792. .stream_name = "Quinary MI2S Playback",
  5793. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5794. .platform_name = "msm-pcm-routing",
  5795. .codec_name = "msm-stub-codec.1",
  5796. .codec_dai_name = "msm-stub-rx",
  5797. .no_pcm = 1,
  5798. .dpcm_playback = 1,
  5799. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5800. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5801. .ops = &msm_mi2s_be_ops,
  5802. .ignore_suspend = 1,
  5803. .ignore_pmdown_time = 1,
  5804. },
  5805. {
  5806. .name = LPASS_BE_QUIN_MI2S_TX,
  5807. .stream_name = "Quinary MI2S Capture",
  5808. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5809. .platform_name = "msm-pcm-routing",
  5810. .codec_name = "msm-stub-codec.1",
  5811. .codec_dai_name = "msm-stub-tx",
  5812. .no_pcm = 1,
  5813. .dpcm_capture = 1,
  5814. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5815. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5816. .ops = &msm_mi2s_be_ops,
  5817. .ignore_suspend = 1,
  5818. },
  5819. };
  5820. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5821. /* Primary AUX PCM Backend DAI Links */
  5822. {
  5823. .name = LPASS_BE_AUXPCM_RX,
  5824. .stream_name = "AUX PCM Playback",
  5825. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5826. .platform_name = "msm-pcm-routing",
  5827. .codec_name = "msm-stub-codec.1",
  5828. .codec_dai_name = "msm-stub-rx",
  5829. .no_pcm = 1,
  5830. .dpcm_playback = 1,
  5831. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5832. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5833. .ignore_pmdown_time = 1,
  5834. .ignore_suspend = 1,
  5835. },
  5836. {
  5837. .name = LPASS_BE_AUXPCM_TX,
  5838. .stream_name = "AUX PCM Capture",
  5839. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5840. .platform_name = "msm-pcm-routing",
  5841. .codec_name = "msm-stub-codec.1",
  5842. .codec_dai_name = "msm-stub-tx",
  5843. .no_pcm = 1,
  5844. .dpcm_capture = 1,
  5845. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5846. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5847. .ignore_suspend = 1,
  5848. },
  5849. /* Secondary AUX PCM Backend DAI Links */
  5850. {
  5851. .name = LPASS_BE_SEC_AUXPCM_RX,
  5852. .stream_name = "Sec AUX PCM Playback",
  5853. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5854. .platform_name = "msm-pcm-routing",
  5855. .codec_name = "msm-stub-codec.1",
  5856. .codec_dai_name = "msm-stub-rx",
  5857. .no_pcm = 1,
  5858. .dpcm_playback = 1,
  5859. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5860. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5861. .ignore_pmdown_time = 1,
  5862. .ignore_suspend = 1,
  5863. },
  5864. {
  5865. .name = LPASS_BE_SEC_AUXPCM_TX,
  5866. .stream_name = "Sec AUX PCM Capture",
  5867. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5868. .platform_name = "msm-pcm-routing",
  5869. .codec_name = "msm-stub-codec.1",
  5870. .codec_dai_name = "msm-stub-tx",
  5871. .no_pcm = 1,
  5872. .dpcm_capture = 1,
  5873. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5874. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5875. .ignore_suspend = 1,
  5876. },
  5877. /* Tertiary AUX PCM Backend DAI Links */
  5878. {
  5879. .name = LPASS_BE_TERT_AUXPCM_RX,
  5880. .stream_name = "Tert AUX PCM Playback",
  5881. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5882. .platform_name = "msm-pcm-routing",
  5883. .codec_name = "msm-stub-codec.1",
  5884. .codec_dai_name = "msm-stub-rx",
  5885. .no_pcm = 1,
  5886. .dpcm_playback = 1,
  5887. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5888. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5889. .ignore_suspend = 1,
  5890. },
  5891. {
  5892. .name = LPASS_BE_TERT_AUXPCM_TX,
  5893. .stream_name = "Tert AUX PCM Capture",
  5894. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5895. .platform_name = "msm-pcm-routing",
  5896. .codec_name = "msm-stub-codec.1",
  5897. .codec_dai_name = "msm-stub-tx",
  5898. .no_pcm = 1,
  5899. .dpcm_capture = 1,
  5900. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5901. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5902. .ignore_suspend = 1,
  5903. },
  5904. /* Quaternary AUX PCM Backend DAI Links */
  5905. {
  5906. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5907. .stream_name = "Quat AUX PCM Playback",
  5908. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5909. .platform_name = "msm-pcm-routing",
  5910. .codec_name = "msm-stub-codec.1",
  5911. .codec_dai_name = "msm-stub-rx",
  5912. .no_pcm = 1,
  5913. .dpcm_playback = 1,
  5914. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5915. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5916. .ignore_pmdown_time = 1,
  5917. .ignore_suspend = 1,
  5918. },
  5919. {
  5920. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5921. .stream_name = "Quat AUX PCM Capture",
  5922. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5923. .platform_name = "msm-pcm-routing",
  5924. .codec_name = "msm-stub-codec.1",
  5925. .codec_dai_name = "msm-stub-tx",
  5926. .no_pcm = 1,
  5927. .dpcm_capture = 1,
  5928. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5929. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5930. .ignore_suspend = 1,
  5931. },
  5932. /* Quinary AUX PCM Backend DAI Links */
  5933. {
  5934. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5935. .stream_name = "Quin AUX PCM Playback",
  5936. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5937. .platform_name = "msm-pcm-routing",
  5938. .codec_name = "msm-stub-codec.1",
  5939. .codec_dai_name = "msm-stub-rx",
  5940. .no_pcm = 1,
  5941. .dpcm_playback = 1,
  5942. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5943. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5944. .ignore_pmdown_time = 1,
  5945. .ignore_suspend = 1,
  5946. },
  5947. {
  5948. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5949. .stream_name = "Quin AUX PCM Capture",
  5950. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5951. .platform_name = "msm-pcm-routing",
  5952. .codec_name = "msm-stub-codec.1",
  5953. .codec_dai_name = "msm-stub-tx",
  5954. .no_pcm = 1,
  5955. .dpcm_capture = 1,
  5956. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5957. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5958. .ignore_suspend = 1,
  5959. },
  5960. };
  5961. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5962. /* WSA CDC DMA Backend DAI Links */
  5963. {
  5964. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5965. .stream_name = "WSA CDC DMA0 Playback",
  5966. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  5967. .platform_name = "msm-pcm-routing",
  5968. .codec_name = "bolero_codec",
  5969. .codec_dai_name = "wsa_macro_rx1",
  5970. .no_pcm = 1,
  5971. .dpcm_playback = 1,
  5972. .init = &msm_wsa_cdc_dma_init,
  5973. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5974. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5975. .ignore_pmdown_time = 1,
  5976. .ignore_suspend = 1,
  5977. .ops = &msm_cdc_dma_be_ops,
  5978. },
  5979. {
  5980. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5981. .stream_name = "WSA CDC DMA1 Playback",
  5982. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  5983. .platform_name = "msm-pcm-routing",
  5984. .codec_name = "bolero_codec",
  5985. .codec_dai_name = "wsa_macro_rx_mix",
  5986. .no_pcm = 1,
  5987. .dpcm_playback = 1,
  5988. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5989. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5990. .ignore_pmdown_time = 1,
  5991. .ignore_suspend = 1,
  5992. .ops = &msm_cdc_dma_be_ops,
  5993. },
  5994. {
  5995. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5996. .stream_name = "WSA CDC DMA1 Capture",
  5997. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  5998. .platform_name = "msm-pcm-routing",
  5999. .codec_name = "bolero_codec",
  6000. .codec_dai_name = "wsa_macro_echo",
  6001. .no_pcm = 1,
  6002. .dpcm_capture = 1,
  6003. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6004. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6005. .ignore_suspend = 1,
  6006. .ops = &msm_cdc_dma_be_ops,
  6007. },
  6008. };
  6009. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6010. {
  6011. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6012. .stream_name = "VA CDC DMA0 Capture",
  6013. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6014. .platform_name = "msm-pcm-routing",
  6015. .codec_name = "bolero_codec",
  6016. .codec_dai_name = "va_macro_tx1",
  6017. .no_pcm = 1,
  6018. .dpcm_capture = 1,
  6019. .init = &msm_va_cdc_dma_init,
  6020. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6021. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6022. .ignore_suspend = 1,
  6023. .ops = &msm_cdc_dma_be_ops,
  6024. },
  6025. {
  6026. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6027. .stream_name = "VA CDC DMA1 Capture",
  6028. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6029. .platform_name = "msm-pcm-routing",
  6030. .codec_name = "bolero_codec",
  6031. .codec_dai_name = "va_macro_tx2",
  6032. .no_pcm = 1,
  6033. .dpcm_capture = 1,
  6034. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6035. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6036. .ignore_suspend = 1,
  6037. .ops = &msm_cdc_dma_be_ops,
  6038. },
  6039. };
  6040. static struct snd_soc_dai_link msm_qcs405_dai_links[
  6041. ARRAY_SIZE(msm_common_dai_links) +
  6042. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6043. ARRAY_SIZE(msm_common_be_dai_links) +
  6044. ARRAY_SIZE(msm_tasha_be_dai_links) +
  6045. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6046. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6047. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6048. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6049. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6050. ARRAY_SIZE(msm_bolero_fe_dai_links)];
  6051. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  6052. {
  6053. int ret = 0;
  6054. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  6055. &service_nb);
  6056. if (ret < 0)
  6057. pr_err("%s: Audio notifier register failed ret = %d\n",
  6058. __func__, ret);
  6059. return ret;
  6060. }
  6061. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  6062. struct snd_ctl_elem_value *ucontrol)
  6063. {
  6064. int ret = 0;
  6065. int port_id;
  6066. uint32_t vad_enable = ucontrol->value.integer.value[0];
  6067. uint32_t preroll_config = ucontrol->value.integer.value[1];
  6068. uint32_t vad_intf = ucontrol->value.integer.value[2];
  6069. if ((preroll_config < 0) || (preroll_config > 1000) ||
  6070. (vad_enable < 0) || (vad_enable > 1) ||
  6071. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  6072. pr_err("%s: Invalid arguments\n", __func__);
  6073. ret = -EINVAL;
  6074. goto done;
  6075. }
  6076. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  6077. vad_enable, preroll_config, vad_intf);
  6078. ret = msm_vad_get_portid_from_beid(vad_intf, &port_id);
  6079. if (ret) {
  6080. pr_err("%s: Invalid vad interface\n", __func__);
  6081. goto done;
  6082. }
  6083. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  6084. done:
  6085. return ret;
  6086. }
  6087. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  6088. {
  6089. int ret = 0;
  6090. uint32_t tasha_codec = 0;
  6091. ret = afe_cal_init_hwdep(card);
  6092. if (ret) {
  6093. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  6094. ret = 0;
  6095. }
  6096. /* tasha late probe when it is present */
  6097. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  6098. &tasha_codec);
  6099. if (ret) {
  6100. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  6101. ret = 0;
  6102. } else {
  6103. if (tasha_codec) {
  6104. ret = msm_snd_card_tasha_late_probe(card);
  6105. if (ret)
  6106. dev_err(card->dev, "%s: tasha late probe err\n",
  6107. __func__);
  6108. }
  6109. }
  6110. return ret;
  6111. }
  6112. struct snd_soc_card snd_soc_card_qcs405_msm = {
  6113. .name = "qcs405-snd-card",
  6114. .controls = msm_snd_controls,
  6115. .num_controls = ARRAY_SIZE(msm_snd_controls),
  6116. .late_probe = msm_snd_card_codec_late_probe,
  6117. };
  6118. static int msm_populate_dai_link_component_of_node(
  6119. struct snd_soc_card *card)
  6120. {
  6121. int i, index, ret = 0;
  6122. struct device *cdev = card->dev;
  6123. struct snd_soc_dai_link *dai_link = card->dai_link;
  6124. struct device_node *np;
  6125. if (!cdev) {
  6126. pr_err("%s: Sound card device memory NULL\n", __func__);
  6127. return -ENODEV;
  6128. }
  6129. for (i = 0; i < card->num_links; i++) {
  6130. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6131. continue;
  6132. /* populate platform_of_node for snd card dai links */
  6133. if (dai_link[i].platform_name &&
  6134. !dai_link[i].platform_of_node) {
  6135. index = of_property_match_string(cdev->of_node,
  6136. "asoc-platform-names",
  6137. dai_link[i].platform_name);
  6138. if (index < 0) {
  6139. pr_err("%s: No match found for platform name: %s\n",
  6140. __func__, dai_link[i].platform_name);
  6141. ret = index;
  6142. goto err;
  6143. }
  6144. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6145. index);
  6146. if (!np) {
  6147. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  6148. __func__, dai_link[i].platform_name,
  6149. index);
  6150. ret = -ENODEV;
  6151. goto err;
  6152. }
  6153. dai_link[i].platform_of_node = np;
  6154. dai_link[i].platform_name = NULL;
  6155. }
  6156. /* populate cpu_of_node for snd card dai links */
  6157. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6158. index = of_property_match_string(cdev->of_node,
  6159. "asoc-cpu-names",
  6160. dai_link[i].cpu_dai_name);
  6161. if (index >= 0) {
  6162. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6163. index);
  6164. if (!np) {
  6165. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  6166. __func__,
  6167. dai_link[i].cpu_dai_name);
  6168. ret = -ENODEV;
  6169. goto err;
  6170. }
  6171. dai_link[i].cpu_of_node = np;
  6172. dai_link[i].cpu_dai_name = NULL;
  6173. }
  6174. }
  6175. /* populate codec_of_node for snd card dai links */
  6176. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6177. index = of_property_match_string(cdev->of_node,
  6178. "asoc-codec-names",
  6179. dai_link[i].codec_name);
  6180. if (index < 0)
  6181. continue;
  6182. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6183. index);
  6184. if (!np) {
  6185. pr_err("%s: retrieving phandle for codec %s failed\n",
  6186. __func__, dai_link[i].codec_name);
  6187. ret = -ENODEV;
  6188. goto err;
  6189. }
  6190. dai_link[i].codec_of_node = np;
  6191. dai_link[i].codec_name = NULL;
  6192. }
  6193. }
  6194. err:
  6195. return ret;
  6196. }
  6197. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6198. /* FrontEnd DAI Links */
  6199. {
  6200. .name = "MSMSTUB Media1",
  6201. .stream_name = "MultiMedia1",
  6202. .cpu_dai_name = "MultiMedia1",
  6203. .platform_name = "msm-pcm-dsp.0",
  6204. .dynamic = 1,
  6205. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6206. .dpcm_playback = 1,
  6207. .dpcm_capture = 1,
  6208. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6209. SND_SOC_DPCM_TRIGGER_POST},
  6210. .codec_dai_name = "snd-soc-dummy-dai",
  6211. .codec_name = "snd-soc-dummy",
  6212. .ignore_suspend = 1,
  6213. /* this dainlink has playback support */
  6214. .ignore_pmdown_time = 1,
  6215. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6216. },
  6217. };
  6218. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6219. /* Backend DAI Links */
  6220. {
  6221. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6222. .stream_name = "VA CDC DMA0 Capture",
  6223. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6224. .platform_name = "msm-pcm-routing",
  6225. .codec_name = "bolero_codec",
  6226. .codec_dai_name = "va_macro_tx1",
  6227. .no_pcm = 1,
  6228. .dpcm_capture = 1,
  6229. .init = &msm_va_cdc_dma_init,
  6230. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6231. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6232. .ignore_suspend = 1,
  6233. .ops = &msm_cdc_dma_be_ops,
  6234. },
  6235. {
  6236. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6237. .stream_name = "VA CDC DMA1 Capture",
  6238. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6239. .platform_name = "msm-pcm-routing",
  6240. .codec_name = "bolero_codec",
  6241. .codec_dai_name = "va_macro_tx2",
  6242. .no_pcm = 1,
  6243. .dpcm_capture = 1,
  6244. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6245. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6246. .ignore_suspend = 1,
  6247. .ops = &msm_cdc_dma_be_ops,
  6248. },
  6249. };
  6250. static struct snd_soc_dai_link msm_stub_dai_links[
  6251. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6252. ARRAY_SIZE(msm_stub_be_dai_links)];
  6253. struct snd_soc_card snd_soc_card_stub_msm = {
  6254. .name = "qcs405-stub-snd-card",
  6255. };
  6256. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  6257. { .compatible = "qcom,qcs405-asoc-snd",
  6258. .data = "codec"},
  6259. { .compatible = "qcom,qcs405-asoc-snd-stub",
  6260. .data = "stub_codec"},
  6261. {},
  6262. };
  6263. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6264. {
  6265. struct snd_soc_card *card = NULL;
  6266. struct snd_soc_dai_link *dailink;
  6267. int total_links = 0;
  6268. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  6269. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  6270. const struct of_device_id *match;
  6271. int rc = 0;
  6272. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  6273. if (!match) {
  6274. dev_err(dev, "%s: No DT match found for sound card\n",
  6275. __func__);
  6276. return NULL;
  6277. }
  6278. if (!strcmp(match->data, "codec")) {
  6279. card = &snd_soc_card_qcs405_msm;
  6280. memcpy(msm_qcs405_dai_links + total_links,
  6281. msm_common_dai_links,
  6282. sizeof(msm_common_dai_links));
  6283. total_links += ARRAY_SIZE(msm_common_dai_links);
  6284. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  6285. &wsa_bolero_codec);
  6286. if (rc) {
  6287. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  6288. __func__);
  6289. } else {
  6290. if (wsa_bolero_codec) {
  6291. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  6292. __func__);
  6293. memcpy(msm_qcs405_dai_links + total_links,
  6294. msm_bolero_fe_dai_links,
  6295. sizeof(msm_bolero_fe_dai_links));
  6296. total_links +=
  6297. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6298. }
  6299. }
  6300. memcpy(msm_qcs405_dai_links + total_links,
  6301. msm_common_misc_fe_dai_links,
  6302. sizeof(msm_common_misc_fe_dai_links));
  6303. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6304. memcpy(msm_qcs405_dai_links + total_links,
  6305. msm_common_be_dai_links,
  6306. sizeof(msm_common_be_dai_links));
  6307. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6308. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  6309. &tasha_codec);
  6310. if (rc) {
  6311. dev_dbg(dev, "%s: No DT match tasha codec\n",
  6312. __func__);
  6313. } else {
  6314. if (tasha_codec) {
  6315. memcpy(msm_qcs405_dai_links + total_links,
  6316. msm_tasha_be_dai_links,
  6317. sizeof(msm_tasha_be_dai_links));
  6318. total_links +=
  6319. ARRAY_SIZE(msm_tasha_be_dai_links);
  6320. }
  6321. }
  6322. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  6323. &va_bolero_codec);
  6324. if (rc) {
  6325. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  6326. __func__);
  6327. } else {
  6328. if (va_bolero_codec) {
  6329. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  6330. __func__);
  6331. memcpy(msm_qcs405_dai_links + total_links,
  6332. msm_va_cdc_dma_be_dai_links,
  6333. sizeof(msm_va_cdc_dma_be_dai_links));
  6334. total_links +=
  6335. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6336. }
  6337. }
  6338. if (wsa_bolero_codec) {
  6339. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  6340. __func__);
  6341. memcpy(msm_qcs405_dai_links + total_links,
  6342. msm_wsa_cdc_dma_be_dai_links,
  6343. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6344. total_links +=
  6345. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6346. }
  6347. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6348. &mi2s_audio_intf);
  6349. if (rc) {
  6350. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6351. __func__);
  6352. } else {
  6353. if (mi2s_audio_intf) {
  6354. memcpy(msm_qcs405_dai_links + total_links,
  6355. msm_mi2s_be_dai_links,
  6356. sizeof(msm_mi2s_be_dai_links));
  6357. total_links +=
  6358. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6359. }
  6360. }
  6361. rc = of_property_read_u32(dev->of_node,
  6362. "qcom,auxpcm-audio-intf",
  6363. &auxpcm_audio_intf);
  6364. if (rc) {
  6365. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6366. __func__);
  6367. } else {
  6368. if (auxpcm_audio_intf) {
  6369. memcpy(msm_qcs405_dai_links + total_links,
  6370. msm_auxpcm_be_dai_links,
  6371. sizeof(msm_auxpcm_be_dai_links));
  6372. total_links +=
  6373. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6374. }
  6375. }
  6376. dailink = msm_qcs405_dai_links;
  6377. } else if (!strcmp(match->data, "stub_codec")) {
  6378. card = &snd_soc_card_stub_msm;
  6379. memcpy(msm_stub_dai_links + total_links,
  6380. msm_stub_fe_dai_links,
  6381. sizeof(msm_stub_fe_dai_links));
  6382. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  6383. memcpy(msm_stub_dai_links + total_links,
  6384. msm_stub_be_dai_links,
  6385. sizeof(msm_stub_be_dai_links));
  6386. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  6387. dailink = msm_stub_dai_links;
  6388. }
  6389. if (card) {
  6390. card->dai_link = dailink;
  6391. card->num_links = total_links;
  6392. }
  6393. return card;
  6394. }
  6395. static int msm_wsa881x_init(struct snd_soc_component *component)
  6396. {
  6397. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6398. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6399. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6400. SPKR_L_BOOST, SPKR_L_VI};
  6401. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6402. SPKR_R_BOOST, SPKR_R_VI};
  6403. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6404. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6405. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6406. struct msm_asoc_mach_data *pdata;
  6407. struct snd_soc_dapm_context *dapm;
  6408. int ret = 0;
  6409. if (!codec) {
  6410. pr_err("%s codec is NULL\n", __func__);
  6411. return -EINVAL;
  6412. }
  6413. dapm = snd_soc_codec_get_dapm(codec);
  6414. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6415. dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
  6416. __func__, codec->component.name);
  6417. wsa881x_set_channel_map(codec, &spkleft_ports[0],
  6418. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6419. &ch_rate[0], &spkleft_port_types[0]);
  6420. if (dapm->component) {
  6421. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6422. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6423. }
  6424. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6425. dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
  6426. __func__, codec->component.name);
  6427. wsa881x_set_channel_map(codec, &spkright_ports[0],
  6428. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6429. &ch_rate[0], &spkright_port_types[0]);
  6430. if (dapm->component) {
  6431. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6432. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6433. }
  6434. } else {
  6435. dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
  6436. codec->component.name);
  6437. ret = -EINVAL;
  6438. goto err;
  6439. }
  6440. pdata = snd_soc_card_get_drvdata(component->card);
  6441. if (pdata && pdata->codec_root)
  6442. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6443. codec);
  6444. err:
  6445. return ret;
  6446. }
  6447. static int msm_init_wsa_dev(struct platform_device *pdev,
  6448. struct snd_soc_card *card)
  6449. {
  6450. struct device_node *wsa_of_node;
  6451. u32 wsa_max_devs;
  6452. u32 wsa_dev_cnt;
  6453. int i;
  6454. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6455. const char *wsa_auxdev_name_prefix[1];
  6456. char *dev_name_str = NULL;
  6457. int found = 0;
  6458. int ret = 0;
  6459. /* Get maximum WSA device count for this platform */
  6460. ret = of_property_read_u32(pdev->dev.of_node,
  6461. "qcom,wsa-max-devs", &wsa_max_devs);
  6462. if (ret) {
  6463. dev_info(&pdev->dev,
  6464. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6465. __func__, pdev->dev.of_node->full_name, ret);
  6466. card->num_aux_devs = 0;
  6467. return 0;
  6468. }
  6469. if (wsa_max_devs == 0) {
  6470. dev_warn(&pdev->dev,
  6471. "%s: Max WSA devices is 0 for this target?\n",
  6472. __func__);
  6473. card->num_aux_devs = 0;
  6474. return 0;
  6475. }
  6476. /* Get count of WSA device phandles for this platform */
  6477. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6478. "qcom,wsa-devs", NULL);
  6479. if (wsa_dev_cnt == -ENOENT) {
  6480. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6481. __func__);
  6482. goto err;
  6483. } else if (wsa_dev_cnt <= 0) {
  6484. dev_err(&pdev->dev,
  6485. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6486. __func__, wsa_dev_cnt);
  6487. ret = -EINVAL;
  6488. goto err;
  6489. }
  6490. /*
  6491. * Expect total phandles count to be NOT less than maximum possible
  6492. * WSA count. However, if it is less, then assign same value to
  6493. * max count as well.
  6494. */
  6495. if (wsa_dev_cnt < wsa_max_devs) {
  6496. dev_dbg(&pdev->dev,
  6497. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6498. __func__, wsa_max_devs, wsa_dev_cnt);
  6499. wsa_max_devs = wsa_dev_cnt;
  6500. }
  6501. /* Make sure prefix string passed for each WSA device */
  6502. ret = of_property_count_strings(pdev->dev.of_node,
  6503. "qcom,wsa-aux-dev-prefix");
  6504. if (ret != wsa_dev_cnt) {
  6505. dev_err(&pdev->dev,
  6506. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6507. __func__, wsa_dev_cnt, ret);
  6508. ret = -EINVAL;
  6509. goto err;
  6510. }
  6511. /*
  6512. * Alloc mem to store phandle and index info of WSA device, if already
  6513. * registered with ALSA core
  6514. */
  6515. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6516. sizeof(struct msm_wsa881x_dev_info),
  6517. GFP_KERNEL);
  6518. if (!wsa881x_dev_info) {
  6519. ret = -ENOMEM;
  6520. goto err;
  6521. }
  6522. /*
  6523. * search and check whether all WSA devices are already
  6524. * registered with ALSA core or not. If found a node, store
  6525. * the node and the index in a local array of struct for later
  6526. * use.
  6527. */
  6528. for (i = 0; i < wsa_dev_cnt; i++) {
  6529. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6530. "qcom,wsa-devs", i);
  6531. if (unlikely(!wsa_of_node)) {
  6532. /* we should not be here */
  6533. dev_err(&pdev->dev,
  6534. "%s: wsa dev node is not present\n",
  6535. __func__);
  6536. ret = -EINVAL;
  6537. goto err_free_dev_info;
  6538. }
  6539. if (soc_find_component(wsa_of_node, NULL)) {
  6540. /* WSA device registered with ALSA core */
  6541. wsa881x_dev_info[found].of_node = wsa_of_node;
  6542. wsa881x_dev_info[found].index = i;
  6543. found++;
  6544. if (found == wsa_max_devs)
  6545. break;
  6546. }
  6547. }
  6548. if (found < wsa_max_devs) {
  6549. dev_err(&pdev->dev,
  6550. "%s: failed to find %d components. Found only %d\n",
  6551. __func__, wsa_max_devs, found);
  6552. return -EPROBE_DEFER;
  6553. }
  6554. dev_info(&pdev->dev,
  6555. "%s: found %d wsa881x devices registered with ALSA core\n",
  6556. __func__, found);
  6557. card->num_aux_devs = wsa_max_devs;
  6558. card->num_configs = wsa_max_devs;
  6559. /* Alloc array of AUX devs struct */
  6560. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6561. sizeof(struct snd_soc_aux_dev),
  6562. GFP_KERNEL);
  6563. if (!msm_aux_dev) {
  6564. ret = -ENOMEM;
  6565. goto err_free_dev_info;
  6566. }
  6567. /* Alloc array of codec conf struct */
  6568. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6569. sizeof(struct snd_soc_codec_conf),
  6570. GFP_KERNEL);
  6571. if (!msm_codec_conf) {
  6572. ret = -ENOMEM;
  6573. goto err_free_aux_dev;
  6574. }
  6575. for (i = 0; i < card->num_aux_devs; i++) {
  6576. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6577. GFP_KERNEL);
  6578. if (!dev_name_str) {
  6579. ret = -ENOMEM;
  6580. goto err_free_cdc_conf;
  6581. }
  6582. ret = of_property_read_string_index(pdev->dev.of_node,
  6583. "qcom,wsa-aux-dev-prefix",
  6584. wsa881x_dev_info[i].index,
  6585. wsa_auxdev_name_prefix);
  6586. if (ret) {
  6587. dev_err(&pdev->dev,
  6588. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6589. __func__, ret);
  6590. ret = -EINVAL;
  6591. goto err_free_dev_name_str;
  6592. }
  6593. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6594. msm_aux_dev[i].name = dev_name_str;
  6595. msm_aux_dev[i].codec_name = NULL;
  6596. msm_aux_dev[i].codec_of_node =
  6597. wsa881x_dev_info[i].of_node;
  6598. msm_aux_dev[i].init = msm_wsa881x_init;
  6599. msm_codec_conf[i].dev_name = NULL;
  6600. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  6601. msm_codec_conf[i].of_node =
  6602. wsa881x_dev_info[i].of_node;
  6603. }
  6604. card->codec_conf = msm_codec_conf;
  6605. card->aux_dev = msm_aux_dev;
  6606. return 0;
  6607. err_free_dev_name_str:
  6608. devm_kfree(&pdev->dev, dev_name_str);
  6609. err_free_cdc_conf:
  6610. devm_kfree(&pdev->dev, msm_codec_conf);
  6611. err_free_aux_dev:
  6612. devm_kfree(&pdev->dev, msm_aux_dev);
  6613. err_free_dev_info:
  6614. devm_kfree(&pdev->dev, wsa881x_dev_info);
  6615. err:
  6616. return ret;
  6617. }
  6618. static int msm_csra66x0_init(struct snd_soc_component *component)
  6619. {
  6620. struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  6621. if (!codec) {
  6622. pr_err("%s codec is NULL\n", __func__);
  6623. return -EINVAL;
  6624. }
  6625. return 0;
  6626. }
  6627. static int msm_init_csra_dev(struct platform_device *pdev,
  6628. struct snd_soc_card *card)
  6629. {
  6630. struct device_node *csra_of_node;
  6631. u32 csra_max_devs;
  6632. u32 csra_dev_cnt;
  6633. char *dev_name_str = NULL;
  6634. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  6635. const char *csra_auxdev_name_prefix[1];
  6636. int i;
  6637. int found = 0;
  6638. int ret = 0;
  6639. /* Get maximum CSRA device count for this platform */
  6640. ret = of_property_read_u32(pdev->dev.of_node,
  6641. "qcom,csra-max-devs", &csra_max_devs);
  6642. if (ret) {
  6643. dev_info(&pdev->dev,
  6644. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  6645. __func__, pdev->dev.of_node->full_name, ret);
  6646. card->num_aux_devs = 0;
  6647. return 0;
  6648. }
  6649. if (csra_max_devs == 0) {
  6650. dev_warn(&pdev->dev,
  6651. "%s: Max CSRA devices is 0 for this target?\n",
  6652. __func__);
  6653. return 0;
  6654. }
  6655. /* Get count of CSRA device phandles for this platform */
  6656. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6657. "qcom,csra-devs", NULL);
  6658. if (csra_dev_cnt == -ENOENT) {
  6659. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  6660. __func__);
  6661. goto err;
  6662. } else if (csra_dev_cnt <= 0) {
  6663. dev_err(&pdev->dev,
  6664. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  6665. __func__, csra_dev_cnt);
  6666. ret = -EINVAL;
  6667. goto err;
  6668. }
  6669. /*
  6670. * Expect total phandles count to be NOT less than maximum possible
  6671. * CSRA count. However, if it is less, then assign same value to
  6672. * max count as well.
  6673. */
  6674. if (csra_dev_cnt < csra_max_devs) {
  6675. dev_dbg(&pdev->dev,
  6676. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  6677. __func__, csra_max_devs, csra_dev_cnt);
  6678. csra_max_devs = csra_dev_cnt;
  6679. }
  6680. /* Make sure prefix string passed for each CSRA device */
  6681. ret = of_property_count_strings(pdev->dev.of_node,
  6682. "qcom,csra-aux-dev-prefix");
  6683. if (ret != csra_dev_cnt) {
  6684. dev_err(&pdev->dev,
  6685. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  6686. __func__, csra_dev_cnt, ret);
  6687. ret = -EINVAL;
  6688. goto err;
  6689. }
  6690. /*
  6691. * Alloc mem to store phandle and index info of CSRA device, if already
  6692. * registered with ALSA core
  6693. */
  6694. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  6695. sizeof(struct msm_csra66x0_dev_info),
  6696. GFP_KERNEL);
  6697. if (!csra66x0_dev_info) {
  6698. ret = -ENOMEM;
  6699. goto err;
  6700. }
  6701. /*
  6702. * search and check whether all CSRA devices are already
  6703. * registered with ALSA core or not. If found a node, store
  6704. * the node and the index in a local array of struct for later
  6705. * use.
  6706. */
  6707. for (i = 0; i < csra_dev_cnt; i++) {
  6708. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  6709. "qcom,csra-devs", i);
  6710. if (unlikely(!csra_of_node)) {
  6711. /* we should not be here */
  6712. dev_err(&pdev->dev,
  6713. "%s: csra dev node is not present\n",
  6714. __func__);
  6715. ret = -EINVAL;
  6716. goto err_free_dev_info;
  6717. }
  6718. if (soc_find_component(csra_of_node, NULL)) {
  6719. /* CSRA device registered with ALSA core */
  6720. csra66x0_dev_info[found].of_node = csra_of_node;
  6721. csra66x0_dev_info[found].index = i;
  6722. found++;
  6723. if (found == csra_max_devs)
  6724. break;
  6725. }
  6726. }
  6727. if (found < csra_max_devs) {
  6728. dev_dbg(&pdev->dev,
  6729. "%s: failed to find %d components. Found only %d\n",
  6730. __func__, csra_max_devs, found);
  6731. return -EPROBE_DEFER;
  6732. }
  6733. dev_info(&pdev->dev,
  6734. "%s: found %d csra66x0 devices registered with ALSA core\n",
  6735. __func__, found);
  6736. card->num_aux_devs = csra_max_devs;
  6737. card->num_configs = csra_max_devs;
  6738. /* Alloc array of AUX devs struct */
  6739. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6740. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  6741. if (!msm_aux_dev) {
  6742. ret = -ENOMEM;
  6743. goto err_free_dev_info;
  6744. }
  6745. /* Alloc array of codec conf struct */
  6746. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6747. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  6748. if (!msm_codec_conf) {
  6749. ret = -ENOMEM;
  6750. goto err_free_aux_dev;
  6751. }
  6752. for (i = 0; i < card->num_aux_devs; i++) {
  6753. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6754. GFP_KERNEL);
  6755. if (!dev_name_str) {
  6756. ret = -ENOMEM;
  6757. goto err_free_cdc_conf;
  6758. }
  6759. ret = of_property_read_string_index(pdev->dev.of_node,
  6760. "qcom,csra-aux-dev-prefix",
  6761. csra66x0_dev_info[i].index,
  6762. csra_auxdev_name_prefix);
  6763. if (ret) {
  6764. dev_err(&pdev->dev,
  6765. "%s: failed to read csra aux dev prefix, ret = %d\n",
  6766. __func__, ret);
  6767. ret = -EINVAL;
  6768. goto err_free_dev_name_str;
  6769. }
  6770. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  6771. msm_aux_dev[i].name = dev_name_str;
  6772. msm_aux_dev[i].codec_name = NULL;
  6773. msm_aux_dev[i].codec_of_node =
  6774. csra66x0_dev_info[i].of_node;
  6775. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  6776. msm_codec_conf[i].dev_name = NULL;
  6777. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  6778. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  6779. }
  6780. card->codec_conf = msm_codec_conf;
  6781. card->aux_dev = msm_aux_dev;
  6782. return 0;
  6783. err_free_dev_name_str:
  6784. devm_kfree(&pdev->dev, dev_name_str);
  6785. err_free_cdc_conf:
  6786. devm_kfree(&pdev->dev, msm_codec_conf);
  6787. err_free_aux_dev:
  6788. devm_kfree(&pdev->dev, msm_aux_dev);
  6789. err_free_dev_info:
  6790. devm_kfree(&pdev->dev, csra66x0_dev_info);
  6791. err:
  6792. return ret;
  6793. }
  6794. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6795. {
  6796. int count;
  6797. u32 mi2s_master_slave[MI2S_MAX];
  6798. int ret;
  6799. for (count = 0; count < MI2S_MAX; count++) {
  6800. mutex_init(&mi2s_intf_conf[count].lock);
  6801. mi2s_intf_conf[count].ref_cnt = 0;
  6802. }
  6803. ret = of_property_read_u32_array(pdev->dev.of_node,
  6804. "qcom,msm-mi2s-master",
  6805. mi2s_master_slave, MI2S_MAX);
  6806. if (ret) {
  6807. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6808. __func__);
  6809. } else {
  6810. for (count = 0; count < MI2S_MAX; count++) {
  6811. mi2s_intf_conf[count].msm_is_mi2s_master =
  6812. mi2s_master_slave[count];
  6813. }
  6814. }
  6815. }
  6816. static void msm_i2s_auxpcm_deinit(void)
  6817. {
  6818. int count;
  6819. for (count = 0; count < MI2S_MAX; count++) {
  6820. mutex_destroy(&mi2s_intf_conf[count].lock);
  6821. mi2s_intf_conf[count].ref_cnt = 0;
  6822. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6823. }
  6824. }
  6825. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6826. {
  6827. struct snd_soc_card *card;
  6828. struct msm_asoc_mach_data *pdata;
  6829. int ret;
  6830. u32 val;
  6831. if (!pdev->dev.of_node) {
  6832. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  6833. return -EINVAL;
  6834. }
  6835. pdata = devm_kzalloc(&pdev->dev,
  6836. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6837. if (!pdata)
  6838. return -ENOMEM;
  6839. card = populate_snd_card_dailinks(&pdev->dev);
  6840. if (!card) {
  6841. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6842. ret = -EINVAL;
  6843. goto err;
  6844. }
  6845. card->dev = &pdev->dev;
  6846. platform_set_drvdata(pdev, card);
  6847. snd_soc_card_set_drvdata(card, pdata);
  6848. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6849. if (ret) {
  6850. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  6851. ret);
  6852. goto err;
  6853. }
  6854. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6855. if (ret) {
  6856. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  6857. ret);
  6858. goto err;
  6859. }
  6860. ret = msm_populate_dai_link_component_of_node(card);
  6861. if (ret) {
  6862. ret = -EPROBE_DEFER;
  6863. goto err;
  6864. }
  6865. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  6866. if (ret) {
  6867. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  6868. val = 0;
  6869. }
  6870. if (val) {
  6871. ret = msm_init_csra_dev(pdev, card);
  6872. if (ret)
  6873. goto err;
  6874. } else {
  6875. ret = msm_init_wsa_dev(pdev, card);
  6876. if (ret)
  6877. goto err;
  6878. }
  6879. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6880. "qcom,cdc-dmic01-gpios",
  6881. 0);
  6882. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6883. "qcom,cdc-dmic23-gpios",
  6884. 0);
  6885. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6886. "qcom,cdc-dmic45-gpios",
  6887. 0);
  6888. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6889. "qcom,cdc-dmic67-gpios",
  6890. 0);
  6891. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6892. if (ret == -EPROBE_DEFER) {
  6893. if (codec_reg_done)
  6894. ret = -EINVAL;
  6895. goto err;
  6896. } else if (ret) {
  6897. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  6898. ret);
  6899. goto err;
  6900. }
  6901. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  6902. spdev = pdev;
  6903. /* Parse pinctrl info from devicetree */
  6904. ret = msm_get_pinctrl(pdev);
  6905. if (!ret) {
  6906. pr_debug("%s: pinctrl parsing successful\n", __func__);
  6907. } else {
  6908. dev_dbg(&pdev->dev,
  6909. "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
  6910. __func__, ret);
  6911. ret = 0;
  6912. }
  6913. msm_i2s_auxpcm_init(pdev);
  6914. is_initial_boot = true;
  6915. return 0;
  6916. err:
  6917. msm_release_pinctrl(pdev);
  6918. return ret;
  6919. }
  6920. static int msm_asoc_machine_remove(struct platform_device *pdev)
  6921. {
  6922. audio_notifier_deregister("qcs405");
  6923. msm_i2s_auxpcm_deinit();
  6924. msm_release_pinctrl(pdev);
  6925. return 0;
  6926. }
  6927. static struct platform_driver qcs405_asoc_machine_driver = {
  6928. .driver = {
  6929. .name = DRV_NAME,
  6930. .owner = THIS_MODULE,
  6931. .pm = &snd_soc_pm_ops,
  6932. .of_match_table = qcs405_asoc_machine_of_match,
  6933. },
  6934. .probe = msm_asoc_machine_probe,
  6935. .remove = msm_asoc_machine_remove,
  6936. };
  6937. module_platform_driver(qcs405_asoc_machine_driver);
  6938. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  6939. MODULE_LICENSE("GPL v2");
  6940. MODULE_ALIAS("platform:" DRV_NAME);
  6941. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);