hal_rx.h 71 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_RX_H_
  19. #define _HAL_RX_H_
  20. #include <hal_internal.h>
  21. /**
  22. * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason"
  23. *
  24. * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected
  25. * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing
  26. */
  27. enum hal_reo_error_status {
  28. HAL_REO_ERROR_DETECTED = 0,
  29. HAL_REO_ROUTING_INSTRUCTION = 1,
  30. };
  31. /**
  32. * @msdu_flags: [0] first_msdu_in_mpdu
  33. * [1] last_msdu_in_mpdu
  34. * [2] msdu_continuation - MSDU spread across buffers
  35. * [23] sa_is_valid - SA match in peer table
  36. * [24] sa_idx_timeout - Timeout while searching for SA match
  37. * [25] da_is_valid - Used to identtify intra-bss forwarding
  38. * [26] da_is_MCBC
  39. * [27] da_idx_timeout - Timeout while searching for DA match
  40. *
  41. */
  42. struct hal_rx_msdu_desc_info {
  43. uint32_t msdu_flags;
  44. uint16_t msdu_len; /* 14 bits for length */
  45. };
  46. /**
  47. * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO
  48. *
  49. * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU
  50. * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU
  51. * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation
  52. * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST
  53. * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out
  54. * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST
  55. * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address
  56. * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out
  57. */
  58. enum hal_rx_msdu_desc_flags {
  59. HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0),
  60. HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1),
  61. HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2),
  62. HAL_MSDU_F_SA_IS_VALID = (0x1 << 23),
  63. HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24),
  64. HAL_MSDU_F_DA_IS_VALID = (0x1 << 25),
  65. HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26),
  66. HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27)
  67. };
  68. /*
  69. * @msdu_count: no. of msdus in the MPDU
  70. * @mpdu_seq: MPDU sequence number
  71. * @mpdu_flags [0] Fragment flag
  72. * [1] MPDU_retry_bit
  73. * [2] AMPDU flag
  74. * [3] raw_ampdu
  75. * @peer_meta_data: Upper bits containing peer id, vdev id
  76. */
  77. struct hal_rx_mpdu_desc_info {
  78. uint16_t msdu_count;
  79. uint16_t mpdu_seq; /* 12 bits for length */
  80. uint32_t mpdu_flags;
  81. uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */
  82. };
  83. /**
  84. * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO
  85. *
  86. * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation)
  87. * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU
  88. * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU
  89. * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU
  90. */
  91. enum hal_rx_mpdu_desc_flags {
  92. HAL_MPDU_F_FRAGMENT = (0x1 << 20),
  93. HAL_MPDU_F_RETRY_BIT = (0x1 << 21),
  94. HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22),
  95. HAL_MPDU_F_RAW_AMPDU = (0x1 << 30)
  96. };
  97. /**
  98. * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in
  99. * BUFFER_ADDR_INFO structure
  100. *
  101. * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
  102. * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
  103. * descriptor list
  104. * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
  105. * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
  106. * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
  107. * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
  108. * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
  109. */
  110. enum hal_rx_ret_buf_manager {
  111. HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0,
  112. HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1,
  113. HAL_RX_BUF_RBM_FW_BM = 2,
  114. HAL_RX_BUF_RBM_SW0_BM = 3,
  115. HAL_RX_BUF_RBM_SW1_BM = 4,
  116. HAL_RX_BUF_RBM_SW2_BM = 5,
  117. HAL_RX_BUF_RBM_SW3_BM = 6,
  118. };
  119. /*
  120. * Given the offset of a field in bytes, returns uint8_t *
  121. */
  122. #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
  123. (((uint8_t *)(_ptr)) + (_off_in_bytes))
  124. /*
  125. * Given the offset of a field in bytes, returns uint32_t *
  126. */
  127. #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
  128. (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
  129. #define _HAL_MS(_word, _mask, _shift) \
  130. (((_word) & (_mask)) >> (_shift))
  131. /*
  132. * macro to set the LSW of the nbuf data physical address
  133. * to the rxdma ring entry
  134. */
  135. #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \
  136. ((*(((unsigned int *) buff_addr_info) + \
  137. (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
  138. (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
  139. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
  140. /*
  141. * macro to set the LSB of MSW of the nbuf data physical address
  142. * to the rxdma ring entry
  143. */
  144. #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \
  145. ((*(((unsigned int *) buff_addr_info) + \
  146. (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
  147. (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
  148. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
  149. /*
  150. * macro to set the cookie into the rxdma ring entry
  151. */
  152. #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
  153. ((*(((unsigned int *) buff_addr_info) + \
  154. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  155. ~((cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
  156. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)); \
  157. ((*(((unsigned int *) buff_addr_info) + \
  158. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  159. (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
  160. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
  161. /*
  162. * macro to set the manager into the rxdma ring entry
  163. */
  164. #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
  165. ((*(((unsigned int *) buff_addr_info) + \
  166. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
  167. ~((manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
  168. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)); \
  169. ((*(((unsigned int *) buff_addr_info) + \
  170. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
  171. (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
  172. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)
  173. #define HAL_RX_ERROR_STATUS_GET(reo_desc) \
  174. (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \
  175. REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\
  176. REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \
  177. REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB))
  178. #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \
  179. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  180. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \
  181. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \
  182. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB))
  183. #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \
  184. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  185. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \
  186. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \
  187. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB))
  188. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  189. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  190. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  191. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  192. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  193. #define HAL_RX_BUF_RBM_GET(buff_addr_info) \
  194. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  195. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\
  196. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \
  197. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB))
  198. /* TODO: Convert the following structure fields accesseses to offsets */
  199. #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \
  200. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  201. (((struct reo_destination_ring *) \
  202. reo_desc)->buf_or_link_desc_addr_info)))
  203. #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \
  204. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  205. (((struct reo_destination_ring *) \
  206. reo_desc)->buf_or_link_desc_addr_info)))
  207. #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \
  208. (HAL_RX_BUF_COOKIE_GET(& \
  209. (((struct reo_destination_ring *) \
  210. reo_desc)->buf_or_link_desc_addr_info)))
  211. #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \
  212. ((mpdu_info_ptr \
  213. [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \
  214. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \
  215. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB)
  216. #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \
  217. ((mpdu_info_ptr \
  218. [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \
  219. RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \
  220. RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB)
  221. #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \
  222. ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \
  223. RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \
  224. RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB)
  225. #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \
  226. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \
  227. RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK)
  228. #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \
  229. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \
  230. RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK)
  231. #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \
  232. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \
  233. RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK)
  234. #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \
  235. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \
  236. RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK)
  237. #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \
  238. (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \
  239. HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \
  240. HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \
  241. HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr))
  242. #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \
  243. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  244. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \
  245. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \
  246. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB))
  247. /*
  248. * NOTE: None of the following _GET macros need a right
  249. * shift by the corresponding _LSB. This is because, they are
  250. * finally taken and "OR'ed" into a single word again.
  251. */
  252. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  253. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  254. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  255. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  256. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  257. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  258. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  259. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK)
  260. #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \
  261. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  262. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \
  263. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  264. #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  265. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  266. RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \
  267. RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK)
  268. #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  269. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  270. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \
  271. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK)
  272. #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  273. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  274. RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \
  275. RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK)
  276. #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \
  277. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  278. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \
  279. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK)
  280. #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  281. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  282. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \
  283. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK)
  284. #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \
  285. (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  286. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  287. HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \
  288. HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  289. HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \
  290. HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  291. HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
  292. HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
  293. #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
  294. ((struct rx_msdu_desc_info *) \
  295. _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
  296. RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
  297. static inline void hal_rx_mpdu_desc_info_get(void *desc_addr,
  298. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  299. {
  300. struct reo_destination_ring *reo_dst_ring;
  301. uint32_t mpdu_info[NUM_OF_DWORDS_RX_MPDU_DESC_INFO];
  302. reo_dst_ring = (struct reo_destination_ring *) desc_addr;
  303. qdf_mem_copy(&mpdu_info,
  304. (const void *)&reo_dst_ring->rx_mpdu_desc_info_details,
  305. sizeof(struct rx_mpdu_desc_info));
  306. mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
  307. mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info);
  308. mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info);
  309. mpdu_desc_info->peer_meta_data =
  310. HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info);
  311. }
  312. /*
  313. * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor.
  314. * @ Specifically flags needed are:
  315. * @ first_msdu_in_mpdu, last_msdu_in_mpdu,
  316. * @ msdu_continuation, sa_is_valid,
  317. * @ sa_idx_timeout, da_is_valid, da_idx_timeout,
  318. * @ da_is_MCBC
  319. *
  320. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current
  321. * @ descriptor
  322. * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor
  323. * @ Return: void
  324. */
  325. static inline void hal_rx_msdu_desc_info_get(void *desc_addr,
  326. struct hal_rx_msdu_desc_info *msdu_desc_info)
  327. {
  328. struct reo_destination_ring *reo_dst_ring;
  329. uint32_t msdu_info[NUM_OF_DWORDS_RX_MSDU_DESC_INFO];
  330. reo_dst_ring = (struct reo_destination_ring *) desc_addr;
  331. qdf_mem_copy(&msdu_info,
  332. (const void *)&reo_dst_ring->rx_msdu_desc_info_details,
  333. sizeof(struct rx_msdu_desc_info));
  334. msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info);
  335. msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info);
  336. }
  337. /*
  338. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  339. * rxdma ring entry.
  340. * @rxdma_entry: descriptor entry
  341. * @paddr: physical address of nbuf data pointer.
  342. * @cookie: SW cookie used as a index to SW rx desc.
  343. * @manager: who owns the nbuf (host, NSS, etc...).
  344. *
  345. */
  346. static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry,
  347. qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager)
  348. {
  349. uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
  350. uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
  351. HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
  352. HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
  353. HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
  354. HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
  355. }
  356. /*
  357. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  358. * pre-header.
  359. */
  360. /*
  361. * Every Rx packet starts at an offset from the top of the buffer.
  362. * If the host hasn't subscribed to any specific TLV, there is
  363. * still space reserved for the following TLV's from the start of
  364. * the buffer:
  365. * -- RX ATTENTION
  366. * -- RX MPDU START
  367. * -- RX MSDU START
  368. * -- RX MSDU END
  369. * -- RX MPDU END
  370. * -- RX PACKET HEADER (802.11)
  371. * If the host subscribes to any of the TLV's above, that TLV
  372. * if populated by the HW
  373. */
  374. #define NUM_DWORDS_TAG 1
  375. /* By default the packet header TLV is 128 bytes */
  376. #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128
  377. #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \
  378. (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2)
  379. #define RX_PKT_OFFSET_WORDS \
  380. ( \
  381. NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \
  382. NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \
  383. NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \
  384. NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \
  385. NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \
  386. NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \
  387. )
  388. #define RX_PKT_OFFSET_BYTES \
  389. (RX_PKT_OFFSET_WORDS << 2)
  390. #define RX_PKT_HDR_TLV_LEN 120
  391. /*
  392. * Each RX descriptor TLV is preceded by 1 DWORD "tag"
  393. */
  394. struct rx_attention_tlv {
  395. uint32_t tag;
  396. struct rx_attention rx_attn;
  397. };
  398. struct rx_mpdu_start_tlv {
  399. uint32_t tag;
  400. struct rx_mpdu_start rx_mpdu_start;
  401. };
  402. struct rx_msdu_start_tlv {
  403. uint32_t tag;
  404. struct rx_msdu_start rx_msdu_start;
  405. };
  406. struct rx_msdu_end_tlv {
  407. uint32_t tag;
  408. struct rx_msdu_end rx_msdu_end;
  409. };
  410. struct rx_mpdu_end_tlv {
  411. uint32_t tag;
  412. struct rx_mpdu_end rx_mpdu_end;
  413. };
  414. struct rx_pkt_hdr_tlv {
  415. uint32_t tag; /* 4 B */
  416. uint32_t phy_ppdu_id; /* 4 B */
  417. char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */
  418. };
  419. #define RXDMA_OPTIMIZATION
  420. #ifdef RXDMA_OPTIMIZATION
  421. /*
  422. * The RX_PADDING_BYTES is required so that the TLV's don't
  423. * spread across the 128 byte boundary
  424. * RXDMA optimization requires:
  425. * 1) MSDU_END & ATTENTION TLV's follow in that order
  426. * 2) TLV's don't span across 128 byte lines
  427. * 3) Rx Buffer is nicely aligned on the 128 byte boundary
  428. */
  429. #if defined(WCSS_VERSION) && \
  430. ((defined(CONFIG_WIN) && (WCSS_VERSION >= 96)) || \
  431. (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
  432. #define RX_PADDING0_BYTES 4
  433. #endif
  434. #define RX_PADDING1_BYTES 16
  435. struct rx_pkt_tlvs {
  436. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  437. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  438. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  439. #if defined(WCSS_VERSION) && \
  440. ((defined(CONFIG_WIN) && (WCSS_VERSION >= 96)) || \
  441. (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
  442. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  443. #endif
  444. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  445. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  446. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  447. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  448. };
  449. #else /* RXDMA_OPTIMIZATION */
  450. struct rx_pkt_tlvs {
  451. struct rx_attention_tlv attn_tlv;
  452. struct rx_mpdu_start_tlv mpdu_start_tlv;
  453. struct rx_msdu_start_tlv msdu_start_tlv;
  454. struct rx_msdu_end_tlv msdu_end_tlv;
  455. struct rx_mpdu_end_tlv mpdu_end_tlv;
  456. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  457. };
  458. #endif /* RXDMA_OPTIMIZATION */
  459. #define RX_PKT_TLVS_LEN (sizeof(struct rx_pkt_tlvs))
  460. /*
  461. * Get msdu_done bit from the RX_ATTENTION TLV
  462. */
  463. #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \
  464. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  465. RX_ATTENTION_2_MSDU_DONE_OFFSET)), \
  466. RX_ATTENTION_2_MSDU_DONE_MASK, \
  467. RX_ATTENTION_2_MSDU_DONE_LSB))
  468. static inline uint32_t
  469. hal_rx_attn_msdu_done_get(uint8_t *buf)
  470. {
  471. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  472. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  473. uint32_t msdu_done;
  474. msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn);
  475. return msdu_done;
  476. }
  477. #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \
  478. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  479. RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \
  480. RX_ATTENTION_1_FIRST_MPDU_MASK, \
  481. RX_ATTENTION_1_FIRST_MPDU_LSB))
  482. /*
  483. * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention
  484. * @buf: pointer to rx_pkt_tlvs
  485. *
  486. * reutm: uint32_t(first_msdu)
  487. */
  488. static inline uint32_t
  489. hal_rx_attn_first_mpdu_get(uint8_t *buf)
  490. {
  491. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  492. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  493. uint32_t first_mpdu;
  494. first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
  495. return first_mpdu;
  496. }
  497. /*
  498. * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
  499. */
  500. #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \
  501. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  502. RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \
  503. RX_MPDU_INFO_8_PEER_META_DATA_MASK, \
  504. RX_MPDU_INFO_8_PEER_META_DATA_LSB))
  505. static inline uint32_t
  506. hal_rx_mpdu_peer_meta_data_get(uint8_t *buf)
  507. {
  508. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  509. struct rx_mpdu_start *mpdu_start =
  510. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  511. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  512. uint32_t peer_meta_data;
  513. peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info);
  514. return peer_meta_data;
  515. }
  516. #if defined(WCSS_VERSION) && \
  517. ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
  518. (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
  519. #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
  520. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  521. RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
  522. RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
  523. RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
  524. #else
  525. #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
  526. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  527. RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET)), \
  528. RX_MSDU_END_9_L3_HEADER_PADDING_MASK, \
  529. RX_MSDU_END_9_L3_HEADER_PADDING_LSB))
  530. #endif
  531. /**
  532. * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the
  533. * l3_header padding from rx_msdu_end TLV
  534. *
  535. * @ buf: pointer to the start of RX PKT TLV headers
  536. * Return: number of l3 header padding bytes
  537. */
  538. static inline uint32_t
  539. hal_rx_msdu_end_l3_hdr_padding_get(uint8_t *buf)
  540. {
  541. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  542. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  543. uint32_t l3_header_padding;
  544. l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  545. return l3_header_padding;
  546. }
  547. #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
  548. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  549. RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
  550. RX_MSDU_END_5_SA_IS_VALID_MASK, \
  551. RX_MSDU_END_5_SA_IS_VALID_LSB))
  552. /**
  553. * hal_rx_msdu_end_sa_is_valid_get(): API to get the
  554. * sa_is_valid bit from rx_msdu_end TLV
  555. *
  556. * @ buf: pointer to the start of RX PKT TLV headers
  557. * Return: sa_is_valid bit
  558. */
  559. static inline uint8_t
  560. hal_rx_msdu_end_sa_is_valid_get(uint8_t *buf)
  561. {
  562. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  563. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  564. uint8_t sa_is_valid;
  565. sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
  566. return sa_is_valid;
  567. }
  568. #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
  569. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  570. RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \
  571. RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
  572. RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
  573. /**
  574. * hal_rx_msdu_end_sa_sw_peer_id_get(): API to get the
  575. * sa_sw_peer_id from rx_msdu_end TLV
  576. *
  577. * @ buf: pointer to the start of RX PKT TLV headers
  578. * Return: sa_sw_peer_id index
  579. */
  580. static inline uint32_t
  581. hal_rx_msdu_end_sa_sw_peer_id_get(uint8_t *buf)
  582. {
  583. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  584. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  585. uint32_t sa_sw_peer_id;
  586. sa_sw_peer_id = HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  587. return sa_sw_peer_id;
  588. }
  589. #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \
  590. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  591. RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \
  592. RX_MSDU_START_1_MSDU_LENGTH_MASK, \
  593. RX_MSDU_START_1_MSDU_LENGTH_LSB))
  594. /**
  595. * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length
  596. * from rx_msdu_start TLV
  597. *
  598. * @ buf: pointer to the start of RX PKT TLV headers
  599. * Return: msdu length
  600. */
  601. static inline uint32_t
  602. hal_rx_msdu_start_msdu_len_get(uint8_t *buf)
  603. {
  604. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  605. struct rx_msdu_start *msdu_start =
  606. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  607. uint32_t msdu_len;
  608. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  609. return msdu_len;
  610. }
  611. #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \
  612. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  613. RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \
  614. RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \
  615. RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB))
  616. /*
  617. * hal_rx_msdu_start_bw_get(): API to get the Bandwidth
  618. * Interval from rx_msdu_start
  619. *
  620. * @buf: pointer to the start of RX PKT TLV header
  621. * Return: uint32_t(bw)
  622. */
  623. static inline uint32_t
  624. hal_rx_msdu_start_bw_get(uint8_t *buf)
  625. {
  626. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  627. struct rx_msdu_start *msdu_start =
  628. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  629. uint32_t bw;
  630. bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
  631. return bw;
  632. }
  633. #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
  634. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  635. RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
  636. RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
  637. RX_MSDU_START_5_RECEPTION_TYPE_LSB))
  638. /*
  639. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  640. * Interval from rx_msdu_start
  641. *
  642. * @buf: pointer to the start of RX PKT TLV header
  643. * Return: uint32_t(reception_type)
  644. */
  645. static inline uint32_t
  646. hal_rx_msdu_start_reception_type_get(uint8_t *buf)
  647. {
  648. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  649. struct rx_msdu_start *msdu_start =
  650. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  651. uint32_t reception_type;
  652. reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
  653. return reception_type;
  654. }
  655. #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \
  656. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  657. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  658. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  659. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  660. /**
  661. * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash
  662. * from rx_msdu_start TLV
  663. *
  664. * @ buf: pointer to the start of RX PKT TLV headers
  665. * Return: toeplitz hash
  666. */
  667. static inline uint32_t
  668. hal_rx_msdu_start_toeplitz_get(uint8_t *buf)
  669. {
  670. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  671. struct rx_msdu_start *msdu_start =
  672. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  673. return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start);
  674. }
  675. /*
  676. * Get qos_control_valid from RX_MPDU_START
  677. */
  678. #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
  679. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  680. RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
  681. RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
  682. RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
  683. static inline uint32_t
  684. hal_rx_mpdu_start_mpdu_qos_control_valid_get(uint8_t *buf)
  685. {
  686. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  687. struct rx_mpdu_start *mpdu_start =
  688. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  689. uint32_t qos_control_valid;
  690. qos_control_valid = HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
  691. &(mpdu_start->rx_mpdu_info_details));
  692. return qos_control_valid;
  693. }
  694. /*
  695. * Get tid from RX_MPDU_START
  696. */
  697. #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
  698. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  699. RX_MPDU_INFO_3_TID_OFFSET)), \
  700. RX_MPDU_INFO_3_TID_MASK, \
  701. RX_MPDU_INFO_3_TID_LSB))
  702. static inline uint32_t
  703. hal_rx_mpdu_start_tid_get(uint8_t *buf)
  704. {
  705. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  706. struct rx_mpdu_start *mpdu_start =
  707. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  708. uint32_t tid;
  709. tid = HAL_RX_MPDU_INFO_TID_GET(
  710. &(mpdu_start->rx_mpdu_info_details));
  711. return tid;
  712. }
  713. /*
  714. * Get SW peer id from RX_MPDU_START
  715. */
  716. #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
  717. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
  718. RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \
  719. RX_MPDU_INFO_1_SW_PEER_ID_MASK, \
  720. RX_MPDU_INFO_1_SW_PEER_ID_LSB))
  721. static inline uint32_t
  722. hal_rx_mpdu_start_sw_peer_id_get(uint8_t *buf)
  723. {
  724. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  725. struct rx_mpdu_start *mpdu_start =
  726. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  727. uint32_t sw_peer_id;
  728. sw_peer_id = HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
  729. &(mpdu_start->rx_mpdu_info_details));
  730. return sw_peer_id;
  731. }
  732. #if defined(WCSS_VERSION) && \
  733. ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
  734. (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
  735. #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
  736. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  737. RX_MSDU_START_5_SGI_OFFSET)), \
  738. RX_MSDU_START_5_SGI_MASK, \
  739. RX_MSDU_START_5_SGI_LSB))
  740. #else
  741. #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
  742. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  743. RX_MSDU_START_6_SGI_OFFSET)), \
  744. RX_MSDU_START_6_SGI_MASK, \
  745. RX_MSDU_START_6_SGI_LSB))
  746. #endif
  747. /**
  748. * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd
  749. * Interval from rx_msdu_start TLV
  750. *
  751. * @buf: pointer to the start of RX PKT TLV headers
  752. * Return: uint32_t(sgi)
  753. */
  754. static inline uint32_t
  755. hal_rx_msdu_start_sgi_get(uint8_t *buf)
  756. {
  757. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  758. struct rx_msdu_start *msdu_start =
  759. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  760. uint32_t sgi;
  761. sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
  762. return sgi;
  763. }
  764. #if defined(WCSS_VERSION) && \
  765. ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
  766. (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
  767. #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
  768. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  769. RX_MSDU_START_5_RATE_MCS_OFFSET)), \
  770. RX_MSDU_START_5_RATE_MCS_MASK, \
  771. RX_MSDU_START_5_RATE_MCS_LSB))
  772. #else
  773. #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
  774. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  775. RX_MSDU_START_6_RATE_MCS_OFFSET)), \
  776. RX_MSDU_START_6_RATE_MCS_MASK, \
  777. RX_MSDU_START_6_RATE_MCS_LSB))
  778. #endif
  779. /**
  780. * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate
  781. * from rx_msdu_start TLV
  782. *
  783. * @buf: pointer to the start of RX PKT TLV headers
  784. * Return: uint32_t(rate_mcs)
  785. */
  786. static inline uint32_t
  787. hal_rx_msdu_start_rate_mcs_get(uint8_t *buf)
  788. {
  789. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  790. struct rx_msdu_start *msdu_start =
  791. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  792. uint32_t rate_mcs;
  793. rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
  794. return rate_mcs;
  795. }
  796. #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
  797. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  798. RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \
  799. RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
  800. RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
  801. /*
  802. * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the
  803. * packet from rx_attention
  804. *
  805. * @buf: pointer to the start of RX PKT TLV header
  806. * Return: uint32_t(decryt status)
  807. */
  808. static inline uint32_t
  809. hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf)
  810. {
  811. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  812. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  813. uint32_t is_decrypt = 0;
  814. uint32_t decrypt_status;
  815. decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
  816. if (!decrypt_status)
  817. is_decrypt = 1;
  818. return is_decrypt;
  819. }
  820. /*
  821. * Get key index from RX_MSDU_END
  822. */
  823. #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \
  824. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  825. RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \
  826. RX_MSDU_END_2_KEY_ID_OCTET_MASK, \
  827. RX_MSDU_END_2_KEY_ID_OCTET_LSB))
  828. /*
  829. * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet
  830. * from rx_msdu_end
  831. *
  832. * @buf: pointer to the start of RX PKT TLV header
  833. * Return: uint32_t(key id)
  834. */
  835. static inline uint32_t
  836. hal_rx_msdu_get_keyid(uint8_t *buf)
  837. {
  838. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  839. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  840. uint32_t keyid_octet;
  841. keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end);
  842. return (keyid_octet >> 6) & 0x3;
  843. }
  844. #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \
  845. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  846. RX_MSDU_START_5_USER_RSSI_OFFSET)), \
  847. RX_MSDU_START_5_USER_RSSI_MASK, \
  848. RX_MSDU_START_5_USER_RSSI_LSB))
  849. /*
  850. * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt
  851. * from rx_msdu_start
  852. *
  853. * @buf: pointer to the start of RX PKT TLV header
  854. * Return: uint32_t(rssi)
  855. */
  856. static inline uint32_t
  857. hal_rx_msdu_start_get_rssi(uint8_t *buf)
  858. {
  859. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  860. struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  861. uint32_t rssi;
  862. rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
  863. return rssi;
  864. }
  865. #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \
  866. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  867. RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \
  868. RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
  869. RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
  870. /*
  871. * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel
  872. * from rx_msdu_start
  873. *
  874. * @buf: pointer to the start of RX PKT TLV header
  875. * Return: uint32_t(frequency)
  876. */
  877. static inline uint32_t
  878. hal_rx_msdu_start_get_freq(uint8_t *buf)
  879. {
  880. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  881. struct rx_msdu_start *msdu_start =
  882. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  883. uint32_t freq;
  884. freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  885. return freq;
  886. }
  887. #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
  888. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  889. RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
  890. RX_MSDU_START_5_PKT_TYPE_MASK, \
  891. RX_MSDU_START_5_PKT_TYPE_LSB))
  892. /*
  893. * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type
  894. * from rx_msdu_start
  895. *
  896. * @buf: pointer to the start of RX PKT TLV header
  897. * Return: uint32_t(pkt type)
  898. */
  899. static inline uint32_t
  900. hal_rx_msdu_start_get_pkt_type(uint8_t *buf)
  901. {
  902. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  903. struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  904. uint32_t pkt_type;
  905. pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
  906. return pkt_type;
  907. }
  908. #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \
  909. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  910. RX_MSDU_START_5_NSS_OFFSET)), \
  911. RX_MSDU_START_5_NSS_MASK, \
  912. RX_MSDU_START_5_NSS_LSB))
  913. /*
  914. * hal_rx_msdu_start_nss_get(): API to get the NSS
  915. * Interval from rx_msdu_start
  916. *
  917. * @buf: pointer to the start of RX PKT TLV header
  918. * Return: uint32_t(nss)
  919. */
  920. static inline uint32_t
  921. hal_rx_msdu_start_nss_get(uint8_t *buf)
  922. {
  923. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  924. struct rx_msdu_start *msdu_start =
  925. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  926. uint32_t nss;
  927. nss = HAL_RX_MSDU_START_NSS_GET(msdu_start);
  928. return nss;
  929. }
  930. #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
  931. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  932. RX_MPDU_INFO_2_TO_DS_OFFSET)), \
  933. RX_MPDU_INFO_2_TO_DS_MASK, \
  934. RX_MPDU_INFO_2_TO_DS_LSB))
  935. /*
  936. * hal_rx_mpdu_get_tods(): API to get the tods info
  937. * from rx_mpdu_start
  938. *
  939. * @buf: pointer to the start of RX PKT TLV header
  940. * Return: uint32_t(to_ds)
  941. */
  942. static inline uint32_t
  943. hal_rx_mpdu_get_to_ds(uint8_t *buf)
  944. {
  945. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  946. struct rx_mpdu_start *mpdu_start =
  947. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  948. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  949. uint32_t to_ds;
  950. to_ds = HAL_RX_MPDU_GET_TODS(mpdu_info);
  951. return to_ds;
  952. }
  953. #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
  954. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  955. RX_MPDU_INFO_2_FR_DS_OFFSET)), \
  956. RX_MPDU_INFO_2_FR_DS_MASK, \
  957. RX_MPDU_INFO_2_FR_DS_LSB))
  958. /*
  959. * hal_rx_mpdu_get_fr_ds(): API to get the from ds info
  960. * from rx_mpdu_start
  961. *
  962. * @buf: pointer to the start of RX PKT TLV header
  963. * Return: uint32_t(fr_ds)
  964. */
  965. static inline uint32_t
  966. hal_rx_mpdu_get_fr_ds(uint8_t *buf)
  967. {
  968. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  969. struct rx_mpdu_start *mpdu_start =
  970. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  971. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  972. uint32_t fr_ds;
  973. fr_ds = HAL_RX_MPDU_GET_FROMDS(mpdu_info);
  974. return fr_ds;
  975. }
  976. #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
  977. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  978. RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \
  979. RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \
  980. RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB))
  981. #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
  982. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  983. RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \
  984. RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \
  985. RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB))
  986. #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
  987. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  988. RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
  989. RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
  990. RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
  991. #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
  992. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  993. RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
  994. RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
  995. RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
  996. #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
  997. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  998. RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
  999. RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
  1000. RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
  1001. #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
  1002. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  1003. RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
  1004. RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
  1005. RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
  1006. /*
  1007. * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu
  1008. *
  1009. * @buf: pointer to the start of RX PKT TLV headera
  1010. * @mac_addr: pointer to mac address
  1011. * Return: sucess/failure
  1012. */
  1013. static inline
  1014. QDF_STATUS hal_rx_mpdu_get_addr1(uint8_t *buf, uint8_t *mac_addr)
  1015. {
  1016. struct __attribute__((__packed__)) hal_addr1 {
  1017. uint32_t ad1_31_0;
  1018. uint16_t ad1_47_32;
  1019. };
  1020. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1021. struct rx_mpdu_start *mpdu_start =
  1022. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1023. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  1024. struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
  1025. uint32_t mac_addr_ad1_valid;
  1026. mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
  1027. if (mac_addr_ad1_valid) {
  1028. addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
  1029. addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
  1030. return QDF_STATUS_SUCCESS;
  1031. }
  1032. return QDF_STATUS_E_FAILURE;
  1033. }
  1034. /*
  1035. * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu
  1036. * in the packet
  1037. *
  1038. * @buf: pointer to the start of RX PKT TLV header
  1039. * @mac_addr: pointer to mac address
  1040. * Return: sucess/failure
  1041. */
  1042. static inline
  1043. QDF_STATUS hal_rx_mpdu_get_addr2(uint8_t *buf, uint8_t *mac_addr)
  1044. {
  1045. struct __attribute__((__packed__)) hal_addr2 {
  1046. uint16_t ad2_15_0;
  1047. uint32_t ad2_47_16;
  1048. };
  1049. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1050. struct rx_mpdu_start *mpdu_start =
  1051. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1052. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  1053. struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
  1054. uint32_t mac_addr_ad2_valid;
  1055. mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
  1056. if (mac_addr_ad2_valid) {
  1057. addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
  1058. addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
  1059. return QDF_STATUS_SUCCESS;
  1060. }
  1061. return QDF_STATUS_E_FAILURE;
  1062. }
  1063. #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
  1064. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  1065. RX_MSDU_END_13_DA_IDX_OFFSET)), \
  1066. RX_MSDU_END_13_DA_IDX_MASK, \
  1067. RX_MSDU_END_13_DA_IDX_LSB))
  1068. /**
  1069. * hal_rx_msdu_end_da_idx_get: API to get da_idx
  1070. * from rx_msdu_end TLV
  1071. *
  1072. * @ buf: pointer to the start of RX PKT TLV headers
  1073. * Return: da index
  1074. */
  1075. static inline uint16_t
  1076. hal_rx_msdu_end_da_idx_get(uint8_t *buf)
  1077. {
  1078. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1079. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1080. uint16_t da_idx;
  1081. da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  1082. return da_idx;
  1083. }
  1084. #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
  1085. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  1086. RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \
  1087. RX_MSDU_END_5_DA_IS_VALID_MASK, \
  1088. RX_MSDU_END_5_DA_IS_VALID_LSB))
  1089. /**
  1090. * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid
  1091. * from rx_msdu_end TLV
  1092. *
  1093. * @ buf: pointer to the start of RX PKT TLV headers
  1094. * Return: da_is_valid
  1095. */
  1096. static inline uint8_t
  1097. hal_rx_msdu_end_da_is_valid_get(uint8_t *buf)
  1098. {
  1099. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1100. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1101. uint8_t da_is_valid;
  1102. da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
  1103. return da_is_valid;
  1104. }
  1105. #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
  1106. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  1107. RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
  1108. RX_MSDU_END_5_DA_IS_MCBC_MASK, \
  1109. RX_MSDU_END_5_DA_IS_MCBC_LSB))
  1110. /**
  1111. * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
  1112. * from rx_msdu_end TLV
  1113. *
  1114. * @ buf: pointer to the start of RX PKT TLV headers
  1115. * Return: da_is_mcbc
  1116. */
  1117. static inline uint8_t
  1118. hal_rx_msdu_end_da_is_mcbc_get(uint8_t *buf)
  1119. {
  1120. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1121. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1122. uint8_t da_is_mcbc;
  1123. da_is_mcbc = HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
  1124. return da_is_mcbc;
  1125. }
  1126. /*******************************************************************************
  1127. * RX ERROR APIS
  1128. ******************************************************************************/
  1129. #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \
  1130. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  1131. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \
  1132. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
  1133. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
  1134. /**
  1135. * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR
  1136. * from rx_mpdu_end TLV
  1137. *
  1138. * @buf: pointer to the start of RX PKT TLV headers
  1139. * Return: uint32_t(decrypt_err)
  1140. */
  1141. static inline uint32_t
  1142. hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf)
  1143. {
  1144. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1145. struct rx_mpdu_end *mpdu_end =
  1146. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  1147. uint32_t decrypt_err;
  1148. decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
  1149. return decrypt_err;
  1150. }
  1151. #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
  1152. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  1153. RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
  1154. RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
  1155. RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
  1156. /**
  1157. * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR
  1158. * from rx_mpdu_end TLV
  1159. *
  1160. * @buf: pointer to the start of RX PKT TLV headers
  1161. * Return: uint32_t(mic_err)
  1162. */
  1163. static inline uint32_t
  1164. hal_rx_mpdu_end_mic_err_get(uint8_t *buf)
  1165. {
  1166. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1167. struct rx_mpdu_end *mpdu_end =
  1168. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  1169. uint32_t mic_err;
  1170. mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
  1171. return mic_err;
  1172. }
  1173. /*******************************************************************************
  1174. * RX REO ERROR APIS
  1175. ******************************************************************************/
  1176. #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
  1177. ((struct rx_msdu_details *) \
  1178. _OFFSET_TO_BYTE_PTR((link_desc),\
  1179. RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
  1180. #define HAL_RX_NUM_MSDU_DESC 6
  1181. struct hal_rx_msdu_list {
  1182. struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
  1183. uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC];
  1184. };
  1185. struct hal_buf_info {
  1186. uint64_t paddr;
  1187. uint32_t sw_cookie;
  1188. };
  1189. /**
  1190. * hal_rx_msdu_link_desc_get: API to get the MSDU information
  1191. * from the MSDU link descriptor
  1192. *
  1193. * @ msdu_link_desc: Opaque pointer used by HAL to get to the
  1194. * MSDU link descriptor (struct rx_msdu_link)
  1195. * @ msdu_list: Return the list of MSDUs contained in this link descriptor
  1196. * Return: void
  1197. */
  1198. static inline void hal_rx_msdu_list_get(void *msdu_link_desc,
  1199. struct hal_rx_msdu_list *msdu_list, uint8_t *num_msdus)
  1200. {
  1201. struct rx_msdu_details *msdu_details;
  1202. struct rx_msdu_desc_info *msdu_desc_info;
  1203. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1204. int i;
  1205. *num_msdus = 0;
  1206. msdu_details = HAL_RX_LINK_DESC_MSDU0_PTR(msdu_link);
  1207. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  1208. msdu_desc_info = HAL_RX_MSDU_DESC_INFO_GET(&msdu_details[i]);
  1209. msdu_list->msdu_info[i].msdu_flags =
  1210. HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  1211. msdu_list->msdu_info[i].msdu_len =
  1212. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  1213. msdu_list->sw_cookie[i] =
  1214. HAL_RX_BUF_COOKIE_GET(
  1215. &msdu_details[i].buffer_addr_info_details);
  1216. }
  1217. *num_msdus = i;
  1218. }
  1219. /**
  1220. * hal_rx_reo_buf_paddr_get: Gets the physical address and
  1221. * cookie from the REO destination ring element
  1222. *
  1223. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1224. * the current descriptor
  1225. * @ buf_info: structure to return the buffer information
  1226. * Return: void
  1227. */
  1228. static inline void hal_rx_reo_buf_paddr_get(void *rx_desc,
  1229. struct hal_buf_info *buf_info)
  1230. {
  1231. struct reo_destination_ring *reo_ring =
  1232. (struct reo_destination_ring *)rx_desc;
  1233. buf_info->paddr =
  1234. (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
  1235. ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
  1236. buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring);
  1237. }
  1238. /**
  1239. * enum hal_reo_error_code: Indicates that type of buffer or descriptor
  1240. *
  1241. * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer
  1242. * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link
  1243. * descriptor
  1244. */
  1245. enum hal_rx_reo_buf_type {
  1246. HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0,
  1247. HAL_RX_REO_MSDU_LINK_DESC_TYPE,
  1248. };
  1249. #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \
  1250. (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \
  1251. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \
  1252. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB)
  1253. /**
  1254. * enum hal_reo_error_code: Error code describing the type of error detected
  1255. *
  1256. * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the
  1257. * REO_ENTRANCE ring is set to 0
  1258. * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set
  1259. * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session
  1260. * having been setup
  1261. * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN,
  1262. * Retry bit set: duplicate frame
  1263. * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame
  1264. * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame)
  1265. * received with 2K jump in SN
  1266. * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN
  1267. * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received
  1268. * with SN falling within the OOR window
  1269. * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the
  1270. * OOR window
  1271. * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session
  1272. * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN
  1273. * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet
  1274. * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  1275. * of the ‘Seq_2k_error_detected_flag’ been set in the REO Queue descriptor
  1276. * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  1277. * of the ‘pn_error_detected_flag’ been set in the REO Queue descriptor
  1278. * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of
  1279. * the queue descriptor(address) being blocked as SW/FW seems to be currently
  1280. * in the process of making updates to this descriptor
  1281. */
  1282. enum hal_reo_error_code {
  1283. HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0,
  1284. HAL_REO_ERR_QUEUE_DESC_INVALID,
  1285. HAL_REO_ERR_AMPDU_IN_NON_BA,
  1286. HAL_REO_ERR_NON_BA_DUPLICATE,
  1287. HAL_REO_ERR_BA_DUPLICATE,
  1288. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP,
  1289. HAL_REO_ERR_BAR_FRAME_2K_JUMP,
  1290. HAL_REO_ERR_REGULAR_FRAME_OOR,
  1291. HAL_REO_ERR_BAR_FRAME_OOR,
  1292. HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION,
  1293. HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN,
  1294. HAL_REO_ERR_PN_CHECK_FAILED,
  1295. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET,
  1296. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET,
  1297. HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET
  1298. };
  1299. #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \
  1300. (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \
  1301. REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \
  1302. REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB)
  1303. /**
  1304. * hal_rx_is_pn_error() - Indicate if this error was caused by a
  1305. * PN check failure
  1306. *
  1307. * @reo_desc: opaque pointer used by HAL to get the REO destination entry
  1308. *
  1309. * Return: true: error caused by PN check, false: other error
  1310. */
  1311. static inline bool hal_rx_reo_is_pn_error(void *rx_desc)
  1312. {
  1313. struct reo_destination_ring *reo_desc =
  1314. (struct reo_destination_ring *)rx_desc;
  1315. return ((HAL_RX_REO_ERROR_GET(reo_desc) ==
  1316. HAL_REO_ERR_PN_CHECK_FAILED) |
  1317. (HAL_RX_REO_ERROR_GET(reo_desc) ==
  1318. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ?
  1319. true : false;
  1320. }
  1321. /**
  1322. * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in
  1323. * the sequence number
  1324. *
  1325. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1326. *
  1327. * Return: true: error caused by 2K jump, false: other error
  1328. */
  1329. static inline bool hal_rx_reo_is_2k_jump(void *rx_desc)
  1330. {
  1331. struct reo_destination_ring *reo_desc =
  1332. (struct reo_destination_ring *)rx_desc;
  1333. return ((HAL_RX_REO_ERROR_GET(reo_desc) ==
  1334. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) |
  1335. (HAL_RX_REO_ERROR_GET(reo_desc) ==
  1336. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ?
  1337. true : false;
  1338. }
  1339. /**
  1340. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  1341. *
  1342. * @ soc : HAL version of the SOC pointer
  1343. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  1344. * @ buf_addr_info : void pointer to the buffer_addr_info
  1345. *
  1346. * Return: void
  1347. */
  1348. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  1349. static inline void hal_rx_msdu_link_desc_set(struct hal_soc *soc,
  1350. void *src_srng_desc, void *buf_addr_info)
  1351. {
  1352. struct wbm_release_ring *wbm_rel_srng =
  1353. (struct wbm_release_ring *)src_srng_desc;
  1354. /* Structure copy !!! */
  1355. wbm_rel_srng->released_buff_or_desc_addr_info =
  1356. *((struct buffer_addr_info *)buf_addr_info);
  1357. }
  1358. /*
  1359. * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to
  1360. * REO entrance ring
  1361. *
  1362. * @ soc: HAL version of the SOC pointer
  1363. * @ pa: Physical address of the MSDU Link Descriptor
  1364. * @ cookie: SW cookie to get to the virtual address
  1365. * @ error_enabled_reo_q: Argument to determine whether this needs to go
  1366. * to the error enabled REO queue
  1367. *
  1368. * Return: void
  1369. */
  1370. static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc,
  1371. uint64_t pa, uint32_t cookie, bool error_enabled_reo_q)
  1372. {
  1373. /* TODO */
  1374. }
  1375. /**
  1376. * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the
  1377. * BUFFER_ADDR_INFO, give the RX descriptor
  1378. * (Assumption -- BUFFER_ADDR_INFO is the
  1379. * first field in the descriptor structure)
  1380. */
  1381. #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) ((void *)(ring_desc))
  1382. #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1383. #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1384. /**
  1385. * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager"
  1386. * from the BUFFER_ADDR_INFO structure
  1387. * given a REO destination ring descriptor.
  1388. * @ ring_desc: RX(REO/WBM release) destination ring descriptor
  1389. *
  1390. * Return: uint8_t (value of the return_buffer_manager)
  1391. */
  1392. static inline
  1393. uint8_t hal_rx_ret_buf_manager_get(void *ring_desc)
  1394. {
  1395. /*
  1396. * The following macro takes buf_addr_info as argument,
  1397. * but since buf_addr_info is the first field in ring_desc
  1398. * Hence the following call is OK
  1399. */
  1400. return HAL_RX_BUF_RBM_GET(ring_desc);
  1401. }
  1402. /*******************************************************************************
  1403. * RX WBM ERROR APIS
  1404. ******************************************************************************/
  1405. /**
  1406. * enum hal_rx_wbm_error_source: Indicates which module initiated the
  1407. * release of this buffer or descriptor
  1408. *
  1409. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  1410. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  1411. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  1412. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  1413. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  1414. */
  1415. enum hal_rx_wbm_error_source {
  1416. HAL_RX_WBM_ERR_SRC_TQM = 0,
  1417. HAL_RX_WBM_ERR_SRC_RXDMA,
  1418. HAL_RX_WBM_ERR_SRC_REO,
  1419. HAL_RX_WBM_ERR_SRC_FW,
  1420. HAL_RX_WBM_ERR_SRC_SW,
  1421. };
  1422. #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1423. (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \
  1424. WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \
  1425. WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB)
  1426. /**
  1427. * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor
  1428. * released
  1429. *
  1430. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  1431. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  1432. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  1433. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  1434. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  1435. */
  1436. enum hal_rx_wbm_buf_type {
  1437. HAL_RX_WBM_BUF_TYPE_REL_BUF = 0,
  1438. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC,
  1439. HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC,
  1440. HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC,
  1441. HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC,
  1442. };
  1443. #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1444. (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \
  1445. WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \
  1446. WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB)
  1447. /**
  1448. * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed
  1449. * the frame to this release ring
  1450. *
  1451. * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this
  1452. * frame to this queue
  1453. * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per
  1454. * received routing instructions. No error within REO was detected
  1455. */
  1456. enum hal_rx_wbm_reo_push_reason {
  1457. HAL_RX_WBM_REO_PSH_RSN_ERROR = 0,
  1458. HAL_RX_WBM_REO_PSH_RSN_ROUTE,
  1459. };
  1460. #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1461. (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \
  1462. WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \
  1463. WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB)
  1464. #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1465. (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \
  1466. WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \
  1467. WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB)
  1468. /**
  1469. * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to
  1470. * this release ring
  1471. *
  1472. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed
  1473. * this frame to this queue
  1474. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue
  1475. * per received routing instructions. No error within RXDMA was detected
  1476. */
  1477. enum hal_rx_wbm_rxdma_push_reason {
  1478. HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0,
  1479. HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE,
  1480. };
  1481. #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \
  1482. (((*(((uint32_t *) wbm_desc) + \
  1483. (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \
  1484. WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \
  1485. WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB)
  1486. #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \
  1487. (((*(((uint32_t *) wbm_desc) + \
  1488. (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \
  1489. WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \
  1490. WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB)
  1491. #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \
  1492. HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \
  1493. wbm_desc)->released_buff_or_desc_addr_info)
  1494. /**
  1495. * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured
  1496. * humman readable format.
  1497. * @ rx_attn: pointer the rx_attention TLV in pkt.
  1498. * @ dbg_level: log level.
  1499. *
  1500. * Return: void
  1501. */
  1502. static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn,
  1503. uint8_t dbg_level)
  1504. {
  1505. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  1506. "\n--------------------\n"
  1507. "rx_attention tlv \n"
  1508. "\n--------------------\n"
  1509. "rxpcu_mpdu_filter_in_category : %d\n"
  1510. "sw_frame_group_id : %d\n"
  1511. "reserved_0 : %d\n"
  1512. "phy_ppdu_id : %d\n"
  1513. "first_mpdu : %d\n"
  1514. "reserved_1a : %d\n"
  1515. "mcast_bcast : %d\n"
  1516. "ast_index_not_found : %d\n"
  1517. "ast_index_timeout : %d\n"
  1518. "power_mgmt : %d\n"
  1519. "non_qos : %d\n"
  1520. "null_data : %d\n"
  1521. "mgmt_type : %d\n"
  1522. "ctrl_type : %d\n"
  1523. "more_data : %d\n"
  1524. "eosp : %d\n"
  1525. "a_msdu_error : %d\n"
  1526. "fragment_flag : %d\n"
  1527. "order : %d\n"
  1528. "cce_match : %d\n"
  1529. "overflow_err : %d\n"
  1530. "msdu_length_err : %d\n"
  1531. "tcp_udp_chksum_fail : %d\n"
  1532. "ip_chksum_fail : %d\n"
  1533. "sa_idx_invalid : %d\n"
  1534. "da_idx_invalid : %d\n"
  1535. "reserved_1b : %d\n"
  1536. "rx_in_tx_decrypt_byp : %d\n"
  1537. "encrypt_required : %d\n"
  1538. "directed : %d\n"
  1539. "buffer_fragment : %d\n"
  1540. "mpdu_length_err : %d\n"
  1541. "tkip_mic_err : %d\n"
  1542. "decrypt_err : %d\n"
  1543. "unencrypted_frame_err : %d\n"
  1544. "fcs_err : %d\n"
  1545. "flow_idx_timeout : %d\n"
  1546. "flow_idx_invalid : %d\n"
  1547. "wifi_parser_error : %d\n"
  1548. "amsdu_parser_error : %d\n"
  1549. "sa_idx_timeout : %d\n"
  1550. "da_idx_timeout : %d\n"
  1551. "msdu_limit_error : %d\n"
  1552. "da_is_valid : %d\n"
  1553. "da_is_mcbc : %d\n"
  1554. "sa_is_valid : %d\n"
  1555. "decrypt_status_code : %d\n"
  1556. "rx_bitmap_not_updated : %d\n"
  1557. "reserved_2 : %d\n"
  1558. "msdu_done : %d\n",
  1559. rx_attn->rxpcu_mpdu_filter_in_category,
  1560. rx_attn->sw_frame_group_id,
  1561. rx_attn->reserved_0,
  1562. rx_attn->phy_ppdu_id,
  1563. rx_attn->first_mpdu,
  1564. rx_attn->reserved_1a,
  1565. rx_attn->mcast_bcast,
  1566. rx_attn->ast_index_not_found,
  1567. rx_attn->ast_index_timeout,
  1568. rx_attn->power_mgmt,
  1569. rx_attn->non_qos,
  1570. rx_attn->null_data,
  1571. rx_attn->mgmt_type,
  1572. rx_attn->ctrl_type,
  1573. rx_attn->more_data,
  1574. rx_attn->eosp,
  1575. rx_attn->a_msdu_error,
  1576. rx_attn->fragment_flag,
  1577. rx_attn->order,
  1578. rx_attn->cce_match,
  1579. rx_attn->overflow_err,
  1580. rx_attn->msdu_length_err,
  1581. rx_attn->tcp_udp_chksum_fail,
  1582. rx_attn->ip_chksum_fail,
  1583. rx_attn->sa_idx_invalid,
  1584. rx_attn->da_idx_invalid,
  1585. rx_attn->reserved_1b,
  1586. rx_attn->rx_in_tx_decrypt_byp,
  1587. rx_attn->encrypt_required,
  1588. rx_attn->directed,
  1589. rx_attn->buffer_fragment,
  1590. rx_attn->mpdu_length_err,
  1591. rx_attn->tkip_mic_err,
  1592. rx_attn->decrypt_err,
  1593. rx_attn->unencrypted_frame_err,
  1594. rx_attn->fcs_err,
  1595. rx_attn->flow_idx_timeout,
  1596. rx_attn->flow_idx_invalid,
  1597. rx_attn->wifi_parser_error,
  1598. rx_attn->amsdu_parser_error,
  1599. rx_attn->sa_idx_timeout,
  1600. rx_attn->da_idx_timeout,
  1601. rx_attn->msdu_limit_error,
  1602. rx_attn->da_is_valid,
  1603. rx_attn->da_is_mcbc,
  1604. rx_attn->sa_is_valid,
  1605. rx_attn->decrypt_status_code,
  1606. rx_attn->rx_bitmap_not_updated,
  1607. rx_attn->reserved_2,
  1608. rx_attn->msdu_done);
  1609. }
  1610. /**
  1611. * hal_rx_dump_mpdu_start_tlv: dump RX mpdu_start TLV in structured
  1612. * human readable format.
  1613. * @ mpdu_start: pointer the rx_attention TLV in pkt.
  1614. * @ dbg_level: log level.
  1615. *
  1616. * Return: void
  1617. */
  1618. static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start,
  1619. uint8_t dbg_level)
  1620. {
  1621. struct rx_mpdu_info *mpdu_info =
  1622. (struct rx_mpdu_info *) &mpdu_start->rx_mpdu_info_details;
  1623. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  1624. "\n--------------------\n"
  1625. "rx_mpdu_start tlv \n"
  1626. "--------------------\n"
  1627. "rxpcu_mpdu_filter_in_category: %d\n"
  1628. "sw_frame_group_id: %d\n"
  1629. "ndp_frame: %d\n"
  1630. "phy_err: %d\n"
  1631. "phy_err_during_mpdu_header: %d\n"
  1632. "protocol_version_err: %d\n"
  1633. "ast_based_lookup_valid: %d\n"
  1634. "phy_ppdu_id: %d\n"
  1635. "ast_index: %d\n"
  1636. "sw_peer_id: %d\n"
  1637. "mpdu_frame_control_valid: %d\n"
  1638. "mpdu_duration_valid: %d\n"
  1639. "mac_addr_ad1_valid: %d\n"
  1640. "mac_addr_ad2_valid: %d\n"
  1641. "mac_addr_ad3_valid: %d\n"
  1642. "mac_addr_ad4_valid: %d\n"
  1643. "mpdu_sequence_control_valid: %d\n"
  1644. "mpdu_qos_control_valid: %d\n"
  1645. "mpdu_ht_control_valid: %d\n"
  1646. "frame_encryption_info_valid: %d\n"
  1647. "fr_ds: %d\n"
  1648. "to_ds: %d\n"
  1649. "encrypted: %d\n"
  1650. "mpdu_retry: %d\n"
  1651. "mpdu_sequence_number: %d\n"
  1652. "epd_en: %d\n"
  1653. "all_frames_shall_be_encrypted: %d\n"
  1654. "encrypt_type: %d\n"
  1655. "mesh_sta: %d\n"
  1656. "bssid_hit: %d\n"
  1657. "bssid_number: %d\n"
  1658. "tid: %d\n"
  1659. "pn_31_0: %d\n"
  1660. "pn_63_32: %d\n"
  1661. "pn_95_64: %d\n"
  1662. "pn_127_96: %d\n"
  1663. "peer_meta_data: %d\n"
  1664. "rxpt_classify_info.reo_destination_indication: %d\n"
  1665. "rxpt_classify_info.use_flow_id_toeplitz_clfy: %d\n"
  1666. "rx_reo_queue_desc_addr_31_0: %d\n"
  1667. "rx_reo_queue_desc_addr_39_32: %d\n"
  1668. "receive_queue_number: %d\n"
  1669. "pre_delim_err_warning: %d\n"
  1670. "first_delim_err: %d\n"
  1671. "key_id_octet: %d\n"
  1672. "new_peer_entry: %d\n"
  1673. "decrypt_needed: %d\n"
  1674. "decap_type: %d\n"
  1675. "rx_insert_vlan_c_tag_padding: %d\n"
  1676. "rx_insert_vlan_s_tag_padding: %d\n"
  1677. "strip_vlan_c_tag_decap: %d\n"
  1678. "strip_vlan_s_tag_decap: %d\n"
  1679. "pre_delim_count: %d\n"
  1680. "ampdu_flag: %d\n"
  1681. "bar_frame: %d\n"
  1682. "mpdu_length: %d\n"
  1683. "first_mpdu: %d\n"
  1684. "mcast_bcast: %d\n"
  1685. "ast_index_not_found: %d\n"
  1686. "ast_index_timeout: %d\n"
  1687. "power_mgmt: %d\n"
  1688. "non_qos: %d\n"
  1689. "null_data: %d\n"
  1690. "mgmt_type: %d\n"
  1691. "ctrl_type: %d\n"
  1692. "more_data: %d\n"
  1693. "eosp: %d\n"
  1694. "fragment_flag: %d\n"
  1695. "order: %d\n"
  1696. "u_apsd_trigger: %d\n"
  1697. "encrypt_required: %d\n"
  1698. "directed: %d\n"
  1699. "mpdu_frame_control_field: %d\n"
  1700. "mpdu_duration_field: %d\n"
  1701. "mac_addr_ad1_31_0: %d\n"
  1702. "mac_addr_ad1_47_32: %d\n"
  1703. "mac_addr_ad2_15_0: %d\n"
  1704. "mac_addr_ad2_47_16: %d\n"
  1705. "mac_addr_ad3_31_0: %d\n"
  1706. "mac_addr_ad3_47_32: %d\n"
  1707. "mpdu_sequence_control_field: %d\n"
  1708. "mac_addr_ad4_31_0: %d\n"
  1709. "mac_addr_ad4_47_32: %d\n"
  1710. "mpdu_qos_control_field: %d\n"
  1711. "mpdu_ht_control_field: %d\n",
  1712. mpdu_info->rxpcu_mpdu_filter_in_category,
  1713. mpdu_info->sw_frame_group_id,
  1714. mpdu_info->ndp_frame,
  1715. mpdu_info->phy_err,
  1716. mpdu_info->phy_err_during_mpdu_header,
  1717. mpdu_info->protocol_version_err,
  1718. mpdu_info->ast_based_lookup_valid,
  1719. mpdu_info->phy_ppdu_id,
  1720. mpdu_info->ast_index,
  1721. mpdu_info->sw_peer_id,
  1722. mpdu_info->mpdu_frame_control_valid,
  1723. mpdu_info->mpdu_duration_valid,
  1724. mpdu_info->mac_addr_ad1_valid,
  1725. mpdu_info->mac_addr_ad2_valid,
  1726. mpdu_info->mac_addr_ad3_valid,
  1727. mpdu_info->mac_addr_ad4_valid,
  1728. mpdu_info->mpdu_sequence_control_valid,
  1729. mpdu_info->mpdu_qos_control_valid,
  1730. mpdu_info->mpdu_ht_control_valid,
  1731. mpdu_info->frame_encryption_info_valid,
  1732. mpdu_info->fr_ds,
  1733. mpdu_info->to_ds,
  1734. mpdu_info->encrypted,
  1735. mpdu_info->mpdu_retry,
  1736. mpdu_info->mpdu_sequence_number,
  1737. mpdu_info->epd_en,
  1738. mpdu_info->all_frames_shall_be_encrypted,
  1739. mpdu_info->encrypt_type,
  1740. mpdu_info->mesh_sta,
  1741. mpdu_info->bssid_hit,
  1742. mpdu_info->bssid_number,
  1743. mpdu_info->tid,
  1744. mpdu_info->pn_31_0,
  1745. mpdu_info->pn_63_32,
  1746. mpdu_info->pn_95_64,
  1747. mpdu_info->pn_127_96,
  1748. mpdu_info->peer_meta_data,
  1749. mpdu_info->rxpt_classify_info_details.reo_destination_indication,
  1750. mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy,
  1751. mpdu_info->rx_reo_queue_desc_addr_31_0,
  1752. mpdu_info->rx_reo_queue_desc_addr_39_32,
  1753. mpdu_info->receive_queue_number,
  1754. mpdu_info->pre_delim_err_warning,
  1755. mpdu_info->first_delim_err,
  1756. mpdu_info->key_id_octet,
  1757. mpdu_info->new_peer_entry,
  1758. mpdu_info->decrypt_needed,
  1759. mpdu_info->decap_type,
  1760. mpdu_info->rx_insert_vlan_c_tag_padding,
  1761. mpdu_info->rx_insert_vlan_s_tag_padding,
  1762. mpdu_info->strip_vlan_c_tag_decap,
  1763. mpdu_info->strip_vlan_s_tag_decap,
  1764. mpdu_info->pre_delim_count,
  1765. mpdu_info->ampdu_flag,
  1766. mpdu_info->bar_frame,
  1767. mpdu_info->mpdu_length,
  1768. mpdu_info->first_mpdu,
  1769. mpdu_info->mcast_bcast,
  1770. mpdu_info->ast_index_not_found,
  1771. mpdu_info->ast_index_timeout,
  1772. mpdu_info->power_mgmt,
  1773. mpdu_info->non_qos,
  1774. mpdu_info->null_data,
  1775. mpdu_info->mgmt_type,
  1776. mpdu_info->ctrl_type,
  1777. mpdu_info->more_data,
  1778. mpdu_info->eosp,
  1779. mpdu_info->fragment_flag,
  1780. mpdu_info->order,
  1781. mpdu_info->u_apsd_trigger,
  1782. mpdu_info->encrypt_required,
  1783. mpdu_info->directed,
  1784. mpdu_info->mpdu_frame_control_field,
  1785. mpdu_info->mpdu_duration_field,
  1786. mpdu_info->mac_addr_ad1_31_0,
  1787. mpdu_info->mac_addr_ad1_47_32,
  1788. mpdu_info->mac_addr_ad2_15_0,
  1789. mpdu_info->mac_addr_ad2_47_16,
  1790. mpdu_info->mac_addr_ad3_31_0,
  1791. mpdu_info->mac_addr_ad3_47_32,
  1792. mpdu_info->mpdu_sequence_control_field,
  1793. mpdu_info->mac_addr_ad4_31_0,
  1794. mpdu_info->mac_addr_ad4_47_32,
  1795. mpdu_info->mpdu_qos_control_field,
  1796. mpdu_info->mpdu_ht_control_field);
  1797. }
  1798. /**
  1799. * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured
  1800. * human readable format.
  1801. * @ msdu_start: pointer the msdu_start TLV in pkt.
  1802. * @ dbg_level: log level.
  1803. *
  1804. * Return: void
  1805. */
  1806. static void hal_rx_dump_msdu_start_tlv(struct rx_msdu_start *msdu_start,
  1807. uint8_t dbg_level)
  1808. {
  1809. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  1810. "\n--------------------\n"
  1811. "rx_msdu_start tlv \n"
  1812. "--------------------\n"
  1813. "rxpcu_mpdu_filter_in_category: %d\n"
  1814. "sw_frame_group_id: %d\n"
  1815. "phy_ppdu_id: %d\n"
  1816. "msdu_length: %d\n"
  1817. "ipsec_esp: %d\n"
  1818. "l3_offset: %d\n"
  1819. "ipsec_ah: %d\n"
  1820. "l4_offset: %d\n"
  1821. "msdu_number: %d\n"
  1822. "decap_format: %d\n"
  1823. "ipv4_proto: %d\n"
  1824. "ipv6_proto: %d\n"
  1825. "tcp_proto: %d\n"
  1826. "udp_proto: %d\n"
  1827. "ip_frag: %d\n"
  1828. "tcp_only_ack: %d\n"
  1829. "da_is_bcast_mcast: %d\n"
  1830. "toeplitz_hash: %d\n"
  1831. "ip4_protocol_ip6_next_header: %d\n"
  1832. "toeplitz_hash_2_or_4: %d\n"
  1833. "flow_id_toeplitz: %d\n"
  1834. "user_rssi: %d\n"
  1835. "pkt_type: %d\n"
  1836. "stbc: %d\n"
  1837. "sgi: %d\n"
  1838. "rate_mcs: %d\n"
  1839. "receive_bandwidth: %d\n"
  1840. "reception_type: %d\n"
  1841. "nss: %d\n"
  1842. "ppdu_start_timestamp: %d\n"
  1843. "sw_phy_meta_data: %d\n",
  1844. msdu_start->rxpcu_mpdu_filter_in_category,
  1845. msdu_start->sw_frame_group_id,
  1846. msdu_start->phy_ppdu_id,
  1847. msdu_start->msdu_length,
  1848. msdu_start->ipsec_esp,
  1849. msdu_start->l3_offset,
  1850. msdu_start->ipsec_ah,
  1851. msdu_start->l4_offset,
  1852. msdu_start->msdu_number,
  1853. msdu_start->decap_format,
  1854. msdu_start->ipv4_proto,
  1855. msdu_start->ipv6_proto,
  1856. msdu_start->tcp_proto,
  1857. msdu_start->udp_proto,
  1858. msdu_start->ip_frag,
  1859. msdu_start->tcp_only_ack,
  1860. msdu_start->da_is_bcast_mcast,
  1861. msdu_start->toeplitz_hash,
  1862. msdu_start->ip4_protocol_ip6_next_header,
  1863. msdu_start->toeplitz_hash_2_or_4,
  1864. msdu_start->flow_id_toeplitz,
  1865. msdu_start->user_rssi,
  1866. msdu_start->pkt_type,
  1867. msdu_start->stbc,
  1868. msdu_start->sgi,
  1869. msdu_start->rate_mcs,
  1870. msdu_start->receive_bandwidth,
  1871. msdu_start->reception_type,
  1872. msdu_start->nss,
  1873. msdu_start->ppdu_start_timestamp,
  1874. msdu_start->sw_phy_meta_data);
  1875. }
  1876. /**
  1877. * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured
  1878. * human readable format.
  1879. * @ msdu_end: pointer the msdu_end TLV in pkt.
  1880. * @ dbg_level: log level.
  1881. *
  1882. * Return: void
  1883. */
  1884. static inline void hal_rx_dump_msdu_end_tlv(struct rx_msdu_end *msdu_end,
  1885. uint8_t dbg_level)
  1886. {
  1887. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  1888. "\n--------------------\n"
  1889. "rx_msdu_end tlv \n"
  1890. "--------------------\n"
  1891. "rxpcu_mpdu_filter_in_category: %d\n"
  1892. "sw_frame_group_id: %d\n"
  1893. "phy_ppdu_id: %d\n"
  1894. "ip_hdr_chksum: %d\n"
  1895. "tcp_udp_chksum: %d\n"
  1896. "key_id_octet: %d\n"
  1897. "cce_super_rule: %d\n"
  1898. "cce_classify_not_done_truncat: %d\n"
  1899. "cce_classify_not_done_cce_dis: %d\n"
  1900. "ext_wapi_pn_63_48: %d\n"
  1901. "ext_wapi_pn_95_64: %d\n"
  1902. "ext_wapi_pn_127_96: %d\n"
  1903. "reported_mpdu_length: %d\n"
  1904. "first_msdu: %d\n"
  1905. "last_msdu: %d\n"
  1906. "sa_idx_timeout: %d\n"
  1907. "da_idx_timeout: %d\n"
  1908. "msdu_limit_error: %d\n"
  1909. "flow_idx_timeout: %d\n"
  1910. "flow_idx_invalid: %d\n"
  1911. "wifi_parser_error: %d\n"
  1912. "amsdu_parser_error: %d\n"
  1913. "sa_is_valid: %d\n"
  1914. "da_is_valid: %d\n"
  1915. "da_is_mcbc: %d\n"
  1916. "l3_header_padding: %d\n"
  1917. "ipv6_options_crc: %d\n"
  1918. "tcp_seq_number: %d\n"
  1919. "tcp_ack_number: %d\n"
  1920. "tcp_flag: %d\n"
  1921. "lro_eligible: %d\n"
  1922. "window_size: %d\n"
  1923. "da_offset: %d\n"
  1924. "sa_offset: %d\n"
  1925. "da_offset_valid: %d\n"
  1926. "sa_offset_valid: %d\n"
  1927. "type_offset: %d\n"
  1928. "rule_indication_31_0: %d\n"
  1929. "rule_indication_63_32: %d\n"
  1930. "sa_idx: %d\n"
  1931. "da_idx: %d\n"
  1932. "msdu_drop: %d\n"
  1933. "reo_destination_indication: %d\n"
  1934. "flow_idx: %d\n"
  1935. "fse_metadata: %d\n"
  1936. "cce_metadata: %d\n"
  1937. "sa_sw_peer_id: %d\n",
  1938. msdu_end->rxpcu_mpdu_filter_in_category,
  1939. msdu_end->sw_frame_group_id,
  1940. msdu_end->phy_ppdu_id,
  1941. msdu_end->ip_hdr_chksum,
  1942. msdu_end->tcp_udp_chksum,
  1943. msdu_end->key_id_octet,
  1944. msdu_end->cce_super_rule,
  1945. msdu_end->cce_classify_not_done_truncate,
  1946. msdu_end->cce_classify_not_done_cce_dis,
  1947. msdu_end->ext_wapi_pn_63_48,
  1948. msdu_end->ext_wapi_pn_95_64,
  1949. msdu_end->ext_wapi_pn_127_96,
  1950. msdu_end->reported_mpdu_length,
  1951. msdu_end->first_msdu,
  1952. msdu_end->last_msdu,
  1953. msdu_end->sa_idx_timeout,
  1954. msdu_end->da_idx_timeout,
  1955. msdu_end->msdu_limit_error,
  1956. msdu_end->flow_idx_timeout,
  1957. msdu_end->flow_idx_invalid,
  1958. msdu_end->wifi_parser_error,
  1959. msdu_end->amsdu_parser_error,
  1960. msdu_end->sa_is_valid,
  1961. msdu_end->da_is_valid,
  1962. msdu_end->da_is_mcbc,
  1963. msdu_end->l3_header_padding,
  1964. msdu_end->ipv6_options_crc,
  1965. msdu_end->tcp_seq_number,
  1966. msdu_end->tcp_ack_number,
  1967. msdu_end->tcp_flag,
  1968. msdu_end->lro_eligible,
  1969. msdu_end->window_size,
  1970. msdu_end->da_offset,
  1971. msdu_end->sa_offset,
  1972. msdu_end->da_offset_valid,
  1973. msdu_end->sa_offset_valid,
  1974. msdu_end->type_offset,
  1975. msdu_end->rule_indication_31_0,
  1976. msdu_end->rule_indication_63_32,
  1977. msdu_end->sa_idx,
  1978. msdu_end->da_idx,
  1979. msdu_end->msdu_drop,
  1980. msdu_end->reo_destination_indication,
  1981. msdu_end->flow_idx,
  1982. msdu_end->fse_metadata,
  1983. msdu_end->cce_metadata,
  1984. msdu_end->sa_sw_peer_id);
  1985. }
  1986. /**
  1987. * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured
  1988. * human readable format.
  1989. * @ mpdu_end: pointer the mpdu_end TLV in pkt.
  1990. * @ dbg_level: log level.
  1991. *
  1992. * Return: void
  1993. */
  1994. static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end,
  1995. uint8_t dbg_level)
  1996. {
  1997. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  1998. "\n--------------------\n"
  1999. "rx_mpdu_end tlv \n"
  2000. "--------------------\n"
  2001. "rxpcu_mpdu_filter_in_category: %d\n"
  2002. "sw_frame_group_id: %d\n"
  2003. "phy_ppdu_id: %d\n"
  2004. "unsup_ktype_short_frame: %d\n"
  2005. "rx_in_tx_decrypt_byp: %d\n"
  2006. "overflow_err: %d\n"
  2007. "mpdu_length_err: %d\n"
  2008. "tkip_mic_err: %d\n"
  2009. "decrypt_err: %d\n"
  2010. "unencrypted_frame_err: %d\n"
  2011. "pn_fields_contain_valid_info: %d\n"
  2012. "fcs_err: %d\n"
  2013. "msdu_length_err: %d\n"
  2014. "rxdma0_destination_ring: %d\n"
  2015. "rxdma1_destination_ring: %d\n"
  2016. "decrypt_status_code: %d\n"
  2017. "rx_bitmap_not_updated: %d\n",
  2018. mpdu_end->rxpcu_mpdu_filter_in_category,
  2019. mpdu_end->sw_frame_group_id,
  2020. mpdu_end->phy_ppdu_id,
  2021. mpdu_end->unsup_ktype_short_frame,
  2022. mpdu_end->rx_in_tx_decrypt_byp,
  2023. mpdu_end->overflow_err,
  2024. mpdu_end->mpdu_length_err,
  2025. mpdu_end->tkip_mic_err,
  2026. mpdu_end->decrypt_err,
  2027. mpdu_end->unencrypted_frame_err,
  2028. mpdu_end->pn_fields_contain_valid_info,
  2029. mpdu_end->fcs_err,
  2030. mpdu_end->msdu_length_err,
  2031. mpdu_end->rxdma0_destination_ring,
  2032. mpdu_end->rxdma1_destination_ring,
  2033. mpdu_end->decrypt_status_code,
  2034. mpdu_end->rx_bitmap_not_updated);
  2035. }
  2036. /**
  2037. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  2038. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  2039. * @ dbg_level: log level.
  2040. *
  2041. * Return: void
  2042. */
  2043. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_hdr_tlv *pkt_hdr_tlv,
  2044. uint8_t dbg_level)
  2045. {
  2046. QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
  2047. "\n---------------\n"
  2048. "rx_pkt_hdr_tlv \n"
  2049. "---------------\n"
  2050. "phy_ppdu_id %d \n",
  2051. pkt_hdr_tlv->phy_ppdu_id);
  2052. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, dbg_level,
  2053. pkt_hdr_tlv->rx_pkt_hdr, 128);
  2054. }
  2055. /**
  2056. * hal_rx_dump_pkt_tlvs: API to print all member elements of
  2057. * RX TLVs
  2058. * @ buf: pointer the pkt buffer.
  2059. * @ dbg_level: log level.
  2060. *
  2061. * Return: void
  2062. */
  2063. static inline void hal_rx_dump_pkt_tlvs(uint8_t *buf, uint8_t dbg_level)
  2064. {
  2065. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *) buf;
  2066. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  2067. struct rx_mpdu_start *mpdu_start =
  2068. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  2069. struct rx_msdu_start *msdu_start =
  2070. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  2071. struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  2072. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  2073. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  2074. hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level);
  2075. hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level);
  2076. hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level);
  2077. hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level);
  2078. hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level);
  2079. hal_rx_dump_pkt_hdr_tlv(pkt_hdr_tlv, dbg_level);
  2080. }
  2081. #endif /* _HAL_RX_H */